From 4122b87486fab99baa85170ae59fb3643ec8c63f Mon Sep 17 00:00:00 2001
From: Kathy Gray
Date: Tue, 4 Nov 2014 16:12:21 +0000
Subject: Fixes bugs: 	not setting starting bit of vector properly 	not
 treating properly if when given a non boolean --- bool largely removed in
 place of bit, removing many/most is_one casts but true and false are still
 possible values 	coerces between bit vectors of length one and bits
 again, because reading from a register can otherwise be wrong with respect to
 the interface

---
 src/test/power.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/power.sail b/src/test/power.sail
index a57193fd..4305c099 100644
--- a/src/test/power.sail
+++ b/src/test/power.sail
@@ -347,7 +347,7 @@ val extern unit -> unit effect { barr } EIEIO_Sync
 (* XXX effect for trap? *)
 val extern unit -> unit effect pure trap
 
-register (bool) mode64bit
+register (bit[1]) mode64bit
 register (bool) bigendianmode
 
 val bit[64] -> unit effect {rreg,wreg} set_overflow_cr0 
-- 
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