From 0eda3ccb8f3003bbc0366ee1bead89c9408e185f Mon Sep 17 00:00:00 2001
From: Kathy Gray
Date: Fri, 16 Jan 2015 14:30:26 +0000
Subject: more for loop corrections, as well as pattern match error

---
 src/lem_interp/interp_interface.lem | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/lem_interp/interp_interface.lem')

diff --git a/src/lem_interp/interp_interface.lem b/src/lem_interp/interp_interface.lem
index a5966c6a..ae29a2e9 100644
--- a/src/lem_interp/interp_interface.lem
+++ b/src/lem_interp/interp_interface.lem
@@ -126,12 +126,14 @@ specifies a part of the field, indexed w.r.t. the register as a whole *)
 
 
 (* because reg_name contains slice which currently contains Big_int.big_int, the default OCaml comparison is not sufficient and we need to define explicit type classes *)
+let slice_eq (s1l,s1r) (s2l,s2r) = (s1l = s2l) && (s1r = s2r)
+
 let reg_nameEqual r1 r2 = 
   match (r1,r2) with
   | (Reg s1 l1, Reg s2 l2) -> s1=s2 && l1=l2
-  | (Reg_slice s1 sl1, Reg_slice s2 sl2) -> s1=s2 && sl1=sl2
-  | (Reg_field s1 f1 sl1, Reg_field s2 f2 sl2) -> s1=s2 && f1=f2 && sl1=sl2
-  | (Reg_f_slice s1 f1 sl1 sl1', Reg_f_slice s2 f2 sl2 sl2') -> s1=s2 && f1=f2 && sl1=sl2 && sl1'=sl2'
+  | (Reg_slice s1 sl1, Reg_slice s2 sl2) -> s1=s2 && (slice_eq sl1 sl2)
+  | (Reg_field s1 f1 sl1, Reg_field s2 f2 sl2) -> s1=s2 && f1=f2 && (slice_eq sl1 sl2)
+  | (Reg_f_slice s1 f1 sl1 sl1', Reg_f_slice s2 f2 sl2 sl2') -> s1=s2 && f1=f2 && (slice_eq sl1 sl2) && (slice_eq sl1' sl2')
   | _ -> false
   end
 
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