From d1d7f0ef16080200187230d9708155668af6edbf Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 25 Oct 2017 12:19:08 +0100
Subject: Avoid name clash in generated Lem (complains due to added val spec)

---
 src/gen_lib/sail_operators.lem        | 2 +-
 src/gen_lib/sail_operators_mwords.lem | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gen_lib')

diff --git a/src/gen_lib/sail_operators.lem b/src/gen_lib/sail_operators.lem
index d9bf8454..524d7ef6 100644
--- a/src/gen_lib/sail_operators.lem
+++ b/src/gen_lib/sail_operators.lem
@@ -36,7 +36,7 @@ let norm_dec = reset_vector_start
 let adjust_start_index (start, v) = set_vector_start (start, v)
 
 let cast_vec_bool v = bitU_to_bool (extract_only_element v)
-let cast_bit_vec (start, len, b) = Vector (repeat [b] len) start false
+let cast_bit_vec_basic (start, len, b) = Vector (repeat [b] len) start false
 let cast_boolvec_bitvec (Vector bs start inc) =
   Vector (List.map bool_to_bitU bs) start inc
 
diff --git a/src/gen_lib/sail_operators_mwords.lem b/src/gen_lib/sail_operators_mwords.lem
index 8fb158de..d4dca80c 100644
--- a/src/gen_lib/sail_operators_mwords.lem
+++ b/src/gen_lib/sail_operators_mwords.lem
@@ -97,7 +97,7 @@ let norm_dec v = v (*reset_bitvector_start*)
 let adjust_start_index (start, v) = v (*set_bitvector_start (start, v)*)
 
 let cast_vec_bool v = bitU_to_bool (extract_only_bit v)
-let cast_bit_vec (start, len, b) = vec_to_bvec (Vector [b] start false)
+let cast_bit_vec_basic (start, len, b) = vec_to_bvec (Vector [b] start false)
 let cast_boolvec_bitvec (Vector bs start inc) =
   vec_to_bvec (Vector (List.map bool_to_bitU bs) start inc)
 
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