From 2cef8d0c31a09ea4fac9a48faff882dde4e98641 Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Mon, 10 Sep 2018 12:16:42 -0700 Subject: RISC-V: Refactor c platform bits. --- riscv/riscv_platform_impl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 riscv/riscv_platform_impl.c (limited to 'riscv/riscv_platform_impl.c') diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c new file mode 100644 index 00000000..1a1d42a7 --- /dev/null +++ b/riscv/riscv_platform_impl.c @@ -0,0 +1,17 @@ +#include "riscv_platform_impl.h" + +/* Settings of the platform implementation, with common defaults. */ + +bool rv_enable_dirty_update = false; +bool rv_enable_misaligned = false; + +uint64_t rv_ram_base = UINT64_C(0x80000000); +uint64_t rv_ram_size = UINT64_C(0x80000000); + +uint64_t rv_rom_base = UINT64_C(0x1000); +uint64_t rv_rom_size = UINT64_C(0x100); + +uint64_t rv_clint_base = UINT64_C(0x2000000); +uint64_t rv_clint_size = UINT64_C(0xc0000); + +uint64_t rv_htif_tohost = UINT64_C(0x80001000); -- cgit v1.2.3 From 8525e0b26eaec05c2c031279693cd61c544fc12a Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Fri, 28 Sep 2018 18:37:11 -0700 Subject: RISC-V: tick the clock in the C platform. --- riscv/riscv_platform_impl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/riscv_platform_impl.c') diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c index 1a1d42a7..3135895d 100644 --- a/riscv/riscv_platform_impl.c +++ b/riscv/riscv_platform_impl.c @@ -15,3 +15,4 @@ uint64_t rv_clint_base = UINT64_C(0x2000000); uint64_t rv_clint_size = UINT64_C(0xc0000); uint64_t rv_htif_tohost = UINT64_C(0x80001000); +uint64_t rv_insns_per_tick = UINT64_C(100); -- cgit v1.2.3 From 2a511449bcd694a5a8e2d16fb65262c914861ba3 Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Tue, 2 Oct 2018 12:02:00 -0700 Subject: RISC-V: implement terminal output for C platform. --- riscv/riscv_platform_impl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'riscv/riscv_platform_impl.c') diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c index 3135895d..d8d52da0 100644 --- a/riscv/riscv_platform_impl.c +++ b/riscv/riscv_platform_impl.c @@ -1,4 +1,6 @@ #include "riscv_platform_impl.h" +#include +#include /* Settings of the platform implementation, with common defaults. */ @@ -16,3 +18,11 @@ uint64_t rv_clint_size = UINT64_C(0xc0000); uint64_t rv_htif_tohost = UINT64_C(0x80001000); uint64_t rv_insns_per_tick = UINT64_C(100); + +int term_fd = 1; // set during startup +void plat_term_write_impl(char c) +{ + if (write(term_fd, &c, sizeof(c)) < 0) { + fprintf(stderr, "Unable to write to terminal!\n"); + } +} -- cgit v1.2.3 From d43b475507ed9144b26be124376c3e656005a416 Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Mon, 8 Oct 2018 09:35:11 -0700 Subject: RISC-V: Add a platform knob to control mtval contents on illegal instruction faults. --- riscv/riscv_platform_impl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'riscv/riscv_platform_impl.c') diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c index d8d52da0..04a661c0 100644 --- a/riscv/riscv_platform_impl.c +++ b/riscv/riscv_platform_impl.c @@ -4,8 +4,9 @@ /* Settings of the platform implementation, with common defaults. */ -bool rv_enable_dirty_update = false; -bool rv_enable_misaligned = false; +bool rv_enable_dirty_update = false; +bool rv_enable_misaligned = false; +bool rv_mtval_has_illegal_inst_bits = false; uint64_t rv_ram_base = UINT64_C(0x80000000); uint64_t rv_ram_size = UINT64_C(0x80000000); -- cgit v1.2.3