From 74e459da59e8411de84bded89d010e62fd735d29 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Fri, 22 Jun 2018 17:14:35 -0700
Subject: Make riscv pte dirty-bit update handling configurable via a platform
 cli option. Fix a redundant clock tick.

---
 riscv/riscv_extras.lem | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'riscv/riscv_extras.lem')

diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 60f5dde9..60d9852a 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -68,6 +68,10 @@ val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a
 let plat_clint_size () = wordFromInteger 0
 declare ocaml target_rep function plat_clint_size = `Platform.clint_size`
 
+val plat_enable_dirty_update : unit -> bool
+let plat_enable_dirty_update () = false
+declare ocaml target_rep function plat_enable_dirty_update = `Platform.enable_dirty_update`
+
 val plat_insns_per_tick : unit -> integer
 let plat_insns_per_tick () = 1
 declare ocaml target_rep function plat_insns_per_tick = `Platform.insns_per_tick`
-- 
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