From 86e6b9e26b76e4af4e5ba056b2e5e7efc98b8efd Mon Sep 17 00:00:00 2001
From: Jon French
Date: Wed, 9 May 2018 14:08:42 +0100
Subject: start of riscv assembly mappings

---
 riscv/prelude.sail | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'riscv/prelude.sail')

diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index d667573e..6a627d22 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -3,6 +3,10 @@ default Order dec
 type bits ('n : Int) = vector('n, dec, bit)
 union option ('a : Type) = {None : unit, Some : 'a}
 
+val spaces : nat <-> string
+val opt_spaces : nat <-> string
+val hex_bits : forall 'n. (atom('n), bits('n)) <-> string
+
 val eq_atom = {ocaml: "eq_int", lem: "eq", c: "eq_int"} : forall 'n 'm. (atom('n), atom('m)) -> bool
 val lteq_atom = "lteq" : forall 'n 'm. (atom('n), atom('m)) -> bool
 val gteq_atom = "gteq" : forall 'n 'm. (atom('n), atom('m)) -> bool
-- 
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