From 28874bde2f7ad58e76ebe8d779d3920d74ca1db6 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 28 Jun 2016 14:23:11 +0100
Subject: Munge exception destination PC so we hit the correct address even
 when kcc.base is non-zero.

---
 mips/mips_prelude.sail  | 6 ++++--
 mips/mips_wrappers.sail | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

(limited to 'mips')

diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail
index 5cccee3f..5be1a3cc 100644
--- a/mips/mips_prelude.sail
+++ b/mips/mips_prelude.sail
@@ -279,7 +279,7 @@ function (bit[5]) ExceptionCode ((Exception) ex) =
 
 val Exception -> unit effect {rreg, wreg} SignalException
 
-function unit SignalExceptionMIPS ((Exception) ex) = 
+function unit SignalExceptionMIPS ((Exception) ex, (bit[64]) kccBase) = 
   {
     (* Only update EPC and BD if not already in EXL mode *)
     if (~ (CP0Status.EXL)) then 
@@ -311,7 +311,9 @@ function unit SignalExceptionMIPS ((Exception) ex) =
                    0xFFFFFFFFBFC00200
                 else
                    0xFFFFFFFF80000000;
-      nextPC := vectorBase + EXTS(vectorOffset);
+      (* On CHERI we have to subtract KCC.base so that we end up at the 
+         right absolute vector address after indirecting via new PCC *)
+      nextPC := ((bit[64])(vectorBase + EXTS(vectorOffset))) - kccBase;
       CP0Cause.ExcCode      := ExceptionCode(ex);
       CP0Status.EXL         := 1;
   }
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail
index 36cbe0d4..e8b17a29 100644
--- a/mips/mips_wrappers.sail
+++ b/mips/mips_wrappers.sail
@@ -52,6 +52,6 @@ function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType
 
 let have_cp2 = false
 
-function unit SignalException ((Exception) ex) = SignalExceptionMIPS(ex)
+function unit SignalException ((Exception) ex) = SignalExceptionMIPS(ex, 0x0000000000000000)
 
 function unit ERETHook() = ()
-- 
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