From b08f0e8538081d8efbbbd6431e739a0b83307678 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 17 May 2018 17:42:20 +0100
Subject: build fixes: add back tag effect skips required for mips. Move UART
 check in to correct place in main.sail. Remove add_atom and sub_atom from
 prelude as we get them from arith.sail.

---
 mips/main.sail | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'mips/main.sail')

diff --git a/mips/main.sail b/mips/main.sail
index 45ced6d7..c444d2dc 100644
--- a/mips/main.sail
+++ b/mips/main.sail
@@ -9,6 +9,13 @@ function fetch_and_execute () = {
   nextPC = if inBranchDelay then delayedPC else PC + 4;
   cp2_next_pc();
   instCount = instCount + 1;
+  if UART_WRITTEN then {
+    putchar(unsigned(UART_WDATA));
+    UART_WRITTEN = 0b0;
+  };
+  /* the following skips are required on mips to fake the tag effects otherwise type checker complains  */
+  skip_rmemt();
+  skip_wmvt();
   print_bits("PC: ", PC);
   try {
     let pc_pa = TranslatePC(PC);
@@ -30,10 +37,6 @@ function fetch_and_execute () = {
        just continue from nextPC, which should have been set to the appropriate
        exception vector (along with clearing branchPending etc.) . */
   };
-  if UART_WRITTEN then {
-    putchar(unsigned(UART_WDATA));
-    UART_WRITTEN = 0b0;
-  }
 }
 
 val elf_entry = {
-- 
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