From 0952ebb7800fe1c396f6916c33bbc19a3b895308 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Tue, 28 Nov 2017 18:48:19 +0000
Subject: Small update to trivial sizeof rewrites so we can handle all cases in
 aarch64 vector instructions.

There's maybe a better more general way to do this but I'm not sure
what that would be.
---
 lib/ocaml_rts/sail_lib.ml | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'lib')

diff --git a/lib/ocaml_rts/sail_lib.ml b/lib/ocaml_rts/sail_lib.ml
index 3cf4505d..dfdd1db9 100644
--- a/lib/ocaml_rts/sail_lib.ml
+++ b/lib/ocaml_rts/sail_lib.ml
@@ -413,6 +413,8 @@ let real_power (x, y) = Num.power_num x (Num.num_of_big_int y)
 let add_real (x, y) = Num.add_num x y
 let sub_real (x, y) = Num.sub_num x y
 
+let abs_real x = Num.abs_num x
+
 let lt (x, y) = lt_big_int x y
 let gt (x, y) = gt_big_int x y
 let lteq (x, y) = le_big_int x y
@@ -422,6 +424,7 @@ let pow2 x = power_big_int_positive_int x 2
 
 let max_int (x, y) = max_big_int x y
 let min_int (x, y) = min_big_int x y
+let abs_int x = abs_big_int x
 
 let undefined_real () = Num.num_of_int 0
 
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