From dd76fdfd819bb1a5423cea369df0e7f2ae449b62 Mon Sep 17 00:00:00 2001 From: Alasdair Date: Fri, 31 Jul 2020 13:30:53 +0100 Subject: Remove old specs that have more up to date version Move outdated things into old subdirectory --- arm/gen/ast.hgen | 44 - arm/gen/fold.hgen | 44 - arm/gen/herdtools_ast_to_shallow_ast.hgen | 335 ------ arm/gen/herdtools_types_to_shallow_types.hgen | 153 --- arm/gen/lexer.hgen | 309 ------ arm/gen/map.hgen | 44 - arm/gen/parser.hgen | 1396 ------------------------- arm/gen/pretty.hgen | 393 ------- arm/gen/regs_out_in.hgen | 155 --- arm/gen/sail_trans_out.hgen | 326 ------ arm/gen/shallow_ast_to_herdtools_ast.hgen | 326 ------ arm/gen/shallow_types_to_herdtools_types.hgen | 154 --- arm/gen/token_types.hgen | 85 -- arm/gen/tokens.hgen | 78 -- arm/gen/trans_sail.hgen | 379 ------- arm/gen/types.hgen | 90 -- arm/gen/types_sail_trans_out.hgen | 189 ---- arm/gen/types_trans_sail.hgen | 119 --- 18 files changed, 4619 deletions(-) delete mode 100644 arm/gen/ast.hgen delete mode 100644 arm/gen/fold.hgen delete mode 100644 arm/gen/herdtools_ast_to_shallow_ast.hgen delete mode 100644 arm/gen/herdtools_types_to_shallow_types.hgen delete mode 100644 arm/gen/lexer.hgen delete mode 100644 arm/gen/map.hgen delete mode 100644 arm/gen/parser.hgen delete mode 100644 arm/gen/pretty.hgen delete mode 100644 arm/gen/regs_out_in.hgen delete mode 100644 arm/gen/sail_trans_out.hgen delete mode 100644 arm/gen/shallow_ast_to_herdtools_ast.hgen delete mode 100644 arm/gen/shallow_types_to_herdtools_types.hgen delete mode 100644 arm/gen/token_types.hgen delete mode 100644 arm/gen/tokens.hgen delete mode 100644 arm/gen/trans_sail.hgen delete mode 100644 arm/gen/types.hgen delete mode 100644 arm/gen/types_sail_trans_out.hgen delete mode 100644 arm/gen/types_trans_sail.hgen (limited to 'arm/gen') diff --git a/arm/gen/ast.hgen b/arm/gen/ast.hgen deleted file mode 100644 index 60f130d7..00000000 --- a/arm/gen/ast.hgen +++ /dev/null @@ -1,44 +0,0 @@ - | `AArch64TMStart of inst_reg (* t *) - | `AArch64TMCommit - | `AArch64TMAbort of boolean*bit5 (* retry,reason *) - | `AArch64TMTest - - | `AArch64ImplementationDefinedTestBeginEnd of boolean (* isEnd *) - | `AArch64ImplementationDefinedStopFetching - | `AArch64ImplementationDefinedThreadStart - | `AArch64AddSubCarry of inst_reg*inst_reg*inst_reg*reg_size*boolean*boolean (* d,n,m,datasize,sub_op,setflags *) - | `AArch64AddSubExtendRegister of inst_reg*inst_reg*inst_reg*reg_size*boolean*boolean*extendType*range0_7 (* d,n,m,datasize,sub_op,setflags,extend_type,shift *) - | `AArch64AddSubShiftedRegister of inst_reg*inst_reg*inst_reg*reg_size*boolean*boolean*shiftType*range0_63 (* d,n,m,datasize,sub_op,setflags,shift_type,shift_amount *) - | `AArch64AddSubImmediate of inst_reg*inst_reg*reg_size*boolean*boolean*reg_size_bits (* d,n,datasize,sub_op,setflags,imm *) - | `AArch64Address of inst_reg*boolean*bit64 (* d,page,imm *) - | `AArch64LogicalImmediate of inst_reg*inst_reg*reg_size*boolean*logicalOp*reg_size_bits (* d,n,datasize,setflags,op,imm *) - | `AArch64LogicalShiftedRegister of inst_reg*inst_reg*inst_reg*reg_size*boolean*logicalOp*shiftType*range0_63*boolean (* d,n,m,datasize,setflags,op,shift_type,shift_amount,invert *) - | `AArch64Shift of inst_reg*inst_reg*inst_reg*reg_size*shiftType (* d,n,m,datasize,shift_type *) - | `AArch64BranchConditional of bit64*bit4 (* offset,condition *) - | `AArch64BranchImmediate of branchType*bit64 (* branch_type,offset *) - | `AArch64BitfieldMove of inst_reg*inst_reg*reg_size*boolean*boolean*uinteger*uinteger*reg_size_bits*reg_size_bits (* d,n,datasize,inzero,extend,R,S,wmask,tmask *) - | `AArch64BranchRegister of inst_reg*branchType (* n,branch_type *) - | `AArch64CompareAndBranch of inst_reg*reg_size*boolean*bit64 (* t,datasize,iszero,offset *) - | `AArch64ConditionalCompareImmediate of inst_reg*reg_size*boolean*bit4*bit4*reg_size_bits (* n,datasize,sub_op,condition,flags,imm *) - | `AArch64ConditionalCompareRegister of inst_reg*inst_reg*reg_size*boolean*bit4*bit4 (* n,m,datasize,sub_op,condition,flags *) - | `AArch64ClearExclusiveMonitor of uinteger (* imm *) - | `AArch64CountLeading of inst_reg*inst_reg*reg_size*countOp (* d,n,datasize,opcode *) - | `AArch64CRC of inst_reg*inst_reg*inst_reg*data_size*boolean (* d,n,m,size,crc32c *) - | `AArch64ConditionalSelect of inst_reg*inst_reg*inst_reg*reg_size*bit4*boolean*boolean (* d,n,m,datasize,condition,else_inv,else_inc *) - | `AArch64Barrier of memBarrierOp*mBReqDomain*mBReqTypes (* op,domain,types *) - | `AArch64ExtractRegister of inst_reg*inst_reg*inst_reg*reg_size*uinteger (* d,n,m,datasize,lsb *) - | `AArch64Hint of systemHintOp (* op *) - | `AArch64LoadStoreAcqExc of inst_reg*inst_reg*inst_reg*inst_reg*accType*boolean*boolean*memOp*uinteger*reg_size*data_size (* n,t,t2,s,acctype,excl,pair,memop,elsize,regsize,datasize *) - | `AArch64LoadStorePair of boolean*boolean*inst_reg*inst_reg*inst_reg*accType*memOp*boolean*data_size*bit64 (* wback,postindex,n,t,t2,acctype,memop,signed,datasize,offset *) - | `AArch64LoadImmediate of inst_reg*inst_reg*accType*memOp*boolean*boolean*boolean*bit64*reg_size*data_size (* n,t,acctype,memop,signed,wback,postindex,offset,regsize,datasize *) - | `AArch64LoadLiteral of inst_reg*memOp*boolean*uinteger*bit64*data_size (* t,memop,signed,size,offset,datasize *) - | `AArch64LoadRegister of inst_reg*inst_reg*inst_reg*accType*memOp*boolean*boolean*boolean*extendType*uinteger*reg_size*data_size (* n,t,m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize *) - | `AArch64MultiplyAddSub of inst_reg*inst_reg*inst_reg*inst_reg*reg_size*data_size*boolean (* d,n,m,a,destsize,datasize,sub_op *) - | `AArch64MoveWide of inst_reg*reg_size*bit16*uinteger*moveWideOp (* d,datasize,imm,pos,opcode *) - | `AArch64Reverse of inst_reg*inst_reg*reg_size*revOp (* d,n,datasize,op *) - | `AArch64Division of inst_reg*inst_reg*inst_reg*reg_size*boolean (* d,n,m,datasize,unsigned *) - | `AArch64MultiplyAddSubLong of inst_reg*inst_reg*inst_reg*inst_reg*reg_size*data_size*boolean*boolean (* d,n,m,a,destsize,datasize,sub_op,unsigned *) - | `AArch64MultiplyHigh of inst_reg*inst_reg*inst_reg*inst_reg*reg_size*data_size*boolean (* d,n,m,a,destsize,datasize,unsigned *) - | `AArch64TestBitAndBranch of inst_reg*reg_size*uinteger*bit*bit64 (* t,datasize,bit_pos,bit_val,offset *) - | `AArch64MoveSystemRegister of inst_reg*uinteger*uinteger*uinteger*uinteger*uinteger*boolean (* t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read *) - | `AArch64MoveSystemImmediate of bit4*pSTATEField (* operand,field *) diff --git a/arm/gen/fold.hgen b/arm/gen/fold.hgen deleted file mode 100644 index 4062d8e6..00000000 --- a/arm/gen/fold.hgen +++ /dev/null @@ -1,44 +0,0 @@ -| `AArch64TMStart t -> fold_reg t (y_reg, y_sreg) -| `AArch64TMCommit -> (y_reg, y_sreg) -| `AArch64TMAbort (retry,reason) -> (y_reg, y_sreg) -| `AArch64TMTest -> (y_reg, y_sreg) - -| `AArch64ImplementationDefinedStopFetching -> (y_reg, y_sreg) -| `AArch64ImplementationDefinedThreadStart -> (y_reg, y_sreg) -| `AArch64ImplementationDefinedTestBeginEnd (isEnd) -> (y_reg, y_sreg) -| `AArch64AddSubCarry (d,n,m,datasize,sub_op,setflags) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64AddSubExtendRegister (d,n,m,datasize,sub_op,setflags,extend_type,shift) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64AddSubShiftedRegister (d,n,m,datasize,sub_op,setflags,shift_type,shift_amount) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64AddSubImmediate (d,n,datasize,sub_op,setflags,imm) -> fold_reg n (fold_reg d (y_reg, y_sreg)) -| `AArch64Address (d,page,imm) -> fold_reg d (y_reg, y_sreg) -| `AArch64LogicalImmediate (d,n,datasize,setflags,op,imm) -> fold_reg n (fold_reg d (y_reg, y_sreg)) -| `AArch64LogicalShiftedRegister (d,n,m,datasize,setflags,op,shift_type,shift_amount,invert) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64Shift (d,n,m,datasize,shift_type) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64BranchConditional (offset,condition) -> (y_reg, y_sreg) -| `AArch64BranchImmediate (branch_type,offset) -> (y_reg, y_sreg) -| `AArch64BitfieldMove (d,n,datasize,inzero,extend,_R,_S,wmask,tmask) -> fold_reg n (fold_reg d (y_reg, y_sreg)) -| `AArch64BranchRegister (n,branch_type) -> fold_reg n (y_reg, y_sreg) -| `AArch64CompareAndBranch (t,datasize,iszero,offset) -> fold_reg t (y_reg, y_sreg) -| `AArch64ConditionalCompareImmediate (n,datasize,sub_op,condition,flags,imm) -> fold_reg n (y_reg, y_sreg) -| `AArch64ConditionalCompareRegister (n,m,datasize,sub_op,condition,flags) -> fold_reg m (fold_reg n (y_reg, y_sreg)) -| `AArch64ClearExclusiveMonitor (imm) -> (y_reg, y_sreg) -| `AArch64CountLeading (d,n,datasize,opcode) -> fold_reg n (fold_reg d (y_reg, y_sreg)) -| `AArch64CRC (d,n,m,size,crc32c) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64ConditionalSelect (d,n,m,datasize,condition,else_inv,else_inc) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64Barrier (op,domain,types) -> (y_reg, y_sreg) -| `AArch64ExtractRegister (d,n,m,datasize,lsb) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64Hint (op) -> (y_reg, y_sreg) -| `AArch64LoadStoreAcqExc (n,t,t2,s,acctype,excl,pair,memop,elsize,regsize,datasize) -> fold_reg s (fold_reg t2 (fold_reg t (fold_reg n (y_reg, y_sreg)))) -| `AArch64LoadStorePair (wback,postindex,n,t,t2,acctype,memop,signed,datasize,offset) -> fold_reg t2 (fold_reg t (fold_reg n (y_reg, y_sreg))) -| `AArch64LoadImmediate (n,t,acctype,memop,signed,wback,postindex,offset,regsize,datasize) -> fold_reg t (fold_reg n (y_reg, y_sreg)) -| `AArch64LoadLiteral (t,memop,signed,size,offset,datasize) -> fold_reg t (y_reg, y_sreg) -| `AArch64LoadRegister (n,t,m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize) -> fold_reg m (fold_reg t (fold_reg n (y_reg, y_sreg))) -| `AArch64MultiplyAddSub (d,n,m,a,destsize,datasize,sub_op) -> fold_reg a (fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg)))) -| `AArch64MoveWide (d,datasize,imm,pos,opcode) -> fold_reg d (y_reg, y_sreg) -| `AArch64Reverse (d,n,datasize,op) -> fold_reg n (fold_reg d (y_reg, y_sreg)) -| `AArch64Division (d,n,m,datasize,unsigned) -> fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg))) -| `AArch64MultiplyAddSubLong (d,n,m,a,destsize,datasize,sub_op,unsigned) -> fold_reg a (fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg)))) -| `AArch64MultiplyHigh (d,n,m,a,destsize,datasize,unsigned) -> fold_reg a (fold_reg m (fold_reg n (fold_reg d (y_reg, y_sreg)))) -| `AArch64TestBitAndBranch (t,datasize,bit_pos,bit_val,offset) -> fold_reg t (y_reg, y_sreg) -| `AArch64MoveSystemRegister (t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read) -> fold_reg t (y_reg, y_sreg) -| `AArch64MoveSystemImmediate (operand,field) -> (y_reg, y_sreg) diff --git a/arm/gen/herdtools_ast_to_shallow_ast.hgen b/arm/gen/herdtools_ast_to_shallow_ast.hgen deleted file mode 100644 index 5a19e483..00000000 --- a/arm/gen/herdtools_ast_to_shallow_ast.hgen +++ /dev/null @@ -1,335 +0,0 @@ -| `AArch64TMStart t -> TMStart (translate_reg "t" t) - -| `AArch64TMCommit -> TMCommit - -| `AArch64TMAbort (retry,reason) -> - TMAbort - (translate_boolean "retry" retry, - translate_bit5 "reason" reason) - -| `AArch64TMTest -> TMTest - -| `AArch64ImplementationDefinedStopFetching -> - ImplementationDefinedStopFetching - -| `AArch64ImplementationDefinedThreadStart -> - ImplementationDefinedThreadStart - -| `AArch64ImplementationDefinedTestBeginEnd(isEnd) -> - ImplementationDefinedTestBeginEnd - (translate_boolean "isEnd" isEnd) - -| `AArch64AddSubCarry(d,n,m,datasize,sub_op,setflags) -> - AddSubCarry - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_boolean "setflags" setflags) - -| `AArch64AddSubExtendRegister (d,n,m,datasize,sub_op,setflags,extend_type,shift) -> - AddSubExtendRegister - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_boolean "setflags" setflags, - translate_extendType "extend_type" extend_type, - translate_range0_7 "shift" shift) - -| `AArch64AddSubShiftedRegister (d,n,m,datasize,sub_op,setflags,shift_type,shift_amount) -> - AddSubShiftedRegister - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_boolean "setflags" setflags, - translate_shiftType "shift_type" shift_type, - translate_range0_63 "shift_amount" shift_amount) - -| `AArch64AddSubImmediate (d,n,datasize,sub_op,setflags,imm) -> - AddSubImmediate - (translate_reg "d" d, - translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_boolean "setflags" setflags, - translate_reg_size_bits "imm" imm) - -| `AArch64Address (d,page,imm) -> - Address0 - (translate_reg "d" d, - translate_boolean "page" page, - translate_bit64 "imm" imm) - -| `AArch64LogicalImmediate (d,n,datasize,setflags,op,imm) -> - LogicalImmediate - (translate_reg "d" d, - translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_boolean "setflags" setflags, - translate_logicalOp "op" op, - translate_reg_size_bits "imm" imm) - -| `AArch64LogicalShiftedRegister (d,n,m,datasize,setflags,op,shift_type,shift_amount,invert) -> - LogicalShiftedRegister - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "setflags" setflags, - translate_logicalOp "op" op, - translate_shiftType "shift_type" shift_type, - translate_range0_63 "shift_amount" shift_amount, - translate_boolean "invert" invert) - -| `AArch64Shift (d,n,m,datasize,shift_type) -> - Shift - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_shiftType "shift_type" shift_type) - -| `AArch64BranchConditional (offset,condition) -> - BranchConditional - (translate_bit64 "offset" offset, - translate_bit4 "condition" condition) - -| `AArch64BranchImmediate (branch_type,offset) -> - BranchImmediate - (translate_branchType "branch_type" branch_type, - translate_bit64 "offset" offset) - -| `AArch64BitfieldMove (d,n,datasize,inzero,extend,_R,_S,wmask,tmask) -> - BitfieldMove - (translate_reg "d" d, - translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_boolean "inzero" inzero, - translate_boolean "extend" extend, - translate_uinteger "_R" _R, - translate_uinteger "_S" _S, - translate_reg_size_bits "wmask" wmask, - translate_reg_size_bits "tmask" tmask) - -| `AArch64BranchRegister (n,branch_type) -> - BranchRegister - (translate_reg "n" n, - translate_branchType "branch_type" branch_type) - -| `AArch64CompareAndBranch (t,datasize,iszero,offset) -> - CompareAndBranch - (translate_reg "t" t, - translate_reg_size "datasize" datasize, - translate_boolean "iszero" iszero, - translate_bit64 "offset" offset) - -| `AArch64ConditionalCompareImmediate (n,datasize,sub_op,condition,flags,imm) -> - ConditionalCompareImmediate - (translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_bit4 "condition" condition, - translate_bit4 "flags" flags, - translate_reg_size_bits "imm" imm) - -| `AArch64ConditionalCompareRegister (n,m,datasize,sub_op,condition,flags) -> - ConditionalCompareRegister - (translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_bit4 "condition" condition, - translate_bit4 "flags" flags) - -| `AArch64ClearExclusiveMonitor (imm) -> - ClearExclusiveMonitor - (translate_uinteger "imm" imm) - -| `AArch64CountLeading (d,n,datasize,opcode) -> - CountLeading - (translate_reg "d" d, - translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_countOp "opcode" opcode) - -| `AArch64CRC (d,n,m,size,crc32c) -> - CRC - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_data_size "size" size, - translate_boolean "crc32c" crc32c) - -| `AArch64ConditionalSelect (d,n,m,datasize,condition,else_inv,else_inc) -> - ConditionalSelect - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_bit4 "condition" condition, - translate_boolean "else_inv" else_inv, - translate_boolean "else_inc" else_inc) - -| `AArch64Barrier (op,domain,types) -> - Barrier2 - (translate_memBarrierOp "op" op, - translate_mBReqDomain "domain" domain, - translate_mBReqTypes "types" types) - -| `AArch64ExtractRegister (d,n,m,datasize,lsb) -> - ExtractRegister - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_uinteger "lsb" lsb) - -| `AArch64Hint (op) -> - Hint - (translate_systemHintOp "op" op) - -| `AArch64LoadStoreAcqExc (n,t,t2,s,acctype,excl,pair,memop,elsize,regsize,datasize) -> - LoadStoreAcqExc - (translate_reg "n" n, - translate_reg "t" t, - translate_reg "t2" t2, - translate_reg "s" s, - translate_accType "acctype" acctype, - translate_boolean "excl" excl, - translate_boolean "pair" pair, - translate_memOp "memop" memop, - translate_uinteger "elsize" elsize, - translate_reg_size "regsize" regsize, - translate_data_size "datasize" datasize) - -| `AArch64LoadStorePair (wback,postindex,n,t,t2,acctype,memop,signed,datasize,offset) -> - LoadStorePair - (translate_boolean "wback" wback, - translate_boolean "postindex" postindex, - translate_reg "n" n, - translate_reg "t" t, - translate_reg "t2" t2, - translate_accType "acctype" acctype, - translate_memOp "memop" memop, - translate_boolean "signed" signed, - translate_data_size "datasize" datasize, - translate_bit64 "offset" offset) - -| `AArch64LoadImmediate (n,t,acctype,memop,signed,wback,postindex,offset,regsize,datasize) -> - LoadImmediate - (translate_reg "n" n, - translate_reg "t" t, - translate_accType "acctype" acctype, - translate_memOp "memop" memop, - translate_boolean "signed" signed, - translate_boolean "wback" wback, - translate_boolean "postindex" postindex, - translate_bit64 "offset" offset, - translate_reg_size "regsize" regsize, - translate_data_size "datasize" datasize) - -| `AArch64LoadLiteral (t,memop,signed,size,offset,datasize) -> - LoadLiteral - (translate_reg "t" t, - translate_memOp "memop" memop, - translate_boolean "signed" signed, - translate_uinteger "size" size, - translate_bit64 "offset" offset, - translate_data_size "datasize" datasize) - -| `AArch64LoadRegister (n,t,m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize) -> - LoadRegister - (translate_reg "n" n, - translate_reg "t" t, - translate_reg "m" m, - translate_accType "acctype" acctype, - translate_memOp "memop" memop, - translate_boolean "signed" signed, - translate_boolean "wback" wback, - translate_boolean "postindex" postindex, - translate_extendType "extend_type" extend_type, - translate_uinteger "shift" shift, - translate_reg_size "regsize" regsize, - translate_data_size "datasize" datasize) - -| `AArch64MultiplyAddSub (d,n,m,a,destsize,datasize,sub_op) -> - MultiplyAddSub - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg "a" a, - translate_reg_size "destsize" destsize, - translate_data_size "datasize" datasize, - translate_boolean "sub_op" sub_op) - -| `AArch64MoveWide (d,datasize,imm,pos,opcode) -> - MoveWide - (translate_reg "d" d, - translate_reg_size "datasize" datasize, - translate_bit16 "imm" imm, - translate_uinteger "pos" pos, - translate_moveWideOp "opcode" opcode) - -| `AArch64Reverse (d,n,datasize,op) -> - Reverse - (translate_reg "d" d, - translate_reg "n" n, - translate_reg_size "datasize" datasize, - translate_revOp "op" op) - -| `AArch64Division (d,n,m,datasize,unsigned) -> - Division - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg_size "datasize" datasize, - translate_boolean "unsigned" unsigned) - -| `AArch64MultiplyAddSubLong (d,n,m,a,destsize,datasize,sub_op,unsigned) -> - MultiplyAddSubLong - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg "a" a, - translate_reg_size "destsize" destsize, - translate_data_size "datasize" datasize, - translate_boolean "sub_op" sub_op, - translate_boolean "unsigned" unsigned) - -| `AArch64MultiplyHigh (d,n,m,a,destsize,datasize,unsigned) -> - MultiplyHigh - (translate_reg "d" d, - translate_reg "n" n, - translate_reg "m" m, - translate_reg "a" a, - translate_reg_size "destsize" destsize, - translate_data_size "datasize" datasize, - translate_boolean "unsigned" unsigned) - -| `AArch64TestBitAndBranch (t,datasize,bit_pos,bit_val,offset) -> - TestBitAndBranch - (translate_reg "t" t, - translate_reg_size "datasize" datasize, - translate_uinteger "bit_pos" bit_pos, - translate_bit "bit_val" bit_val, - translate_bit64 "offset" offset) - -| `AArch64MoveSystemRegister (t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read) -> - MoveSystemRegister - (translate_reg "t" t, - translate_uinteger "sys_op0" sys_op0, - translate_uinteger "sys_op1" sys_op1, - translate_uinteger "sys_op2" sys_op2, - translate_uinteger "sys_crn" sys_crn, - translate_uinteger "sys_crm" sys_crm, - translate_boolean "read" read) - -| `AArch64MoveSystemImmediate (operand,field) -> - MoveSystemImmediate - (translate_bit4 "operand" operand, - translate_pSTATEField "field" field) diff --git a/arm/gen/herdtools_types_to_shallow_types.hgen b/arm/gen/herdtools_types_to_shallow_types.hgen deleted file mode 100644 index e14a37e3..00000000 --- a/arm/gen/herdtools_types_to_shallow_types.hgen +++ /dev/null @@ -1,153 +0,0 @@ -open Sail_values - -let is_inc = false - -let translate_big_int bits (name : string) value = - (name, Range0 (Some bits), IInt.bit_list_of_integer bits value) - -let translate_big_bit bits (name:string) value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int bits,value) - -let translate_int (size : int) (name:string) value = (Nat_big_num.of_int value) - -let translate_bits bits (name:string) value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int bits,Nat_big_num.of_int value) - -let translate_bool _ = function - | true -> B1 - | false -> B0 - -let translate_reg_size name value = - match value with - | Set32 -> (Nat_big_num.of_int 32) - | Set64 -> (Nat_big_num.of_int 64) - -let translate_reg name value = - (Nat_big_num.of_int (inst_reg_to_int value)) - - -let translate_reg_size_bits name value = - match value with - | R32Bits value -> translate_bits 32 name value - | R64Bits value -> translate_big_bit 64 name value - -let translate_data_size name value = - match value with - | DataSize8 -> (Nat_big_num.of_int 8) - | DataSize16 -> (Nat_big_num.of_int 16) - | DataSize32 -> (Nat_big_num.of_int 32) - | DataSize64 -> (Nat_big_num.of_int 64) - -let translate_reg_index = translate_int 5 - -let translate_boolean = translate_bool - -let translate_range0_7 = translate_int 3 - -let translate_range0_63 = translate_int 6 - -let translate_bit64 = translate_big_bit 64 - -let translate_bit4 = translate_bits 4 -let translate_bit5 = translate_bits 5 -let translate_bit16 = translate_bits 16 - -let translate_bit = translate_bool - -let translate_range8_64 = translate_int 7 - -let translate_uinteger = translate_int 63 - -let translate_extendType _ = function - | ExtendType_UXTB -> ArmV8_embed_types.ExtendType_UXTB - | ExtendType_UXTH -> ArmV8_embed_types.ExtendType_UXTH - | ExtendType_UXTW -> ArmV8_embed_types.ExtendType_UXTW - | ExtendType_UXTX -> ArmV8_embed_types.ExtendType_UXTX - | ExtendType_SXTB -> ArmV8_embed_types.ExtendType_SXTB - | ExtendType_SXTH -> ArmV8_embed_types.ExtendType_SXTH - | ExtendType_SXTW -> ArmV8_embed_types.ExtendType_SXTW - | ExtendType_SXTX -> ArmV8_embed_types.ExtendType_SXTX - -let translate_shiftType _ = function - | ShiftType_LSL -> ArmV8_embed_types.ShiftType_LSL - | ShiftType_LSR -> ArmV8_embed_types.ShiftType_LSR - | ShiftType_ASR -> ArmV8_embed_types.ShiftType_ASR - | ShiftType_ROR -> ArmV8_embed_types.ShiftType_ROR - -let translate_logicalOp _ = function - | LogicalOp_AND -> ArmV8_embed_types.LogicalOp_AND - | LogicalOp_EOR -> ArmV8_embed_types.LogicalOp_EOR - | LogicalOp_ORR -> ArmV8_embed_types.LogicalOp_ORR - -let translate_branchType _ = function - | BranchType_CALL -> ArmV8_embed_types.BranchType_CALL - | BranchType_ERET -> ArmV8_embed_types.BranchType_ERET - | BranchType_DBGEXIT -> ArmV8_embed_types.BranchType_DBGEXIT - | BranchType_RET -> ArmV8_embed_types.BranchType_RET - | BranchType_JMP -> ArmV8_embed_types.BranchType_JMP - | BranchType_EXCEPTION -> ArmV8_embed_types.BranchType_EXCEPTION - | BranchType_UNKNOWN -> ArmV8_embed_types.BranchType_UNKNOWN - -let translate_countOp _ = function - | CountOp_CLZ -> ArmV8_embed_types.CountOp_CLZ - | CountOp_CLS -> ArmV8_embed_types.CountOp_CLS - | CountOp_CNT -> ArmV8_embed_types.CountOp_CNT - -let translate_memBarrierOp _ = function - | MemBarrierOp_DSB -> ArmV8_embed_types.MemBarrierOp_DSB - | MemBarrierOp_DMB -> ArmV8_embed_types.MemBarrierOp_DMB - | MemBarrierOp_ISB -> ArmV8_embed_types.MemBarrierOp_ISB - -let translate_mBReqDomain _ = function - | MBReqDomain_Nonshareable -> ArmV8_embed_types.MBReqDomain_Nonshareable - | MBReqDomain_InnerShareable -> ArmV8_embed_types.MBReqDomain_InnerShareable - | MBReqDomain_OuterShareable -> ArmV8_embed_types.MBReqDomain_OuterShareable - | MBReqDomain_FullSystem -> ArmV8_embed_types.MBReqDomain_FullSystem - -let translate_mBReqTypes _ = function - | MBReqTypes_Reads -> ArmV8_embed_types.MBReqTypes_Reads - | MBReqTypes_Writes -> ArmV8_embed_types.MBReqTypes_Writes - | MBReqTypes_All -> ArmV8_embed_types.MBReqTypes_All - -let translate_systemHintOp _ = function - | SystemHintOp_NOP -> ArmV8_embed_types.SystemHintOp_NOP - | SystemHintOp_YIELD -> ArmV8_embed_types.SystemHintOp_YIELD - | SystemHintOp_WFE -> ArmV8_embed_types.SystemHintOp_WFE - | SystemHintOp_WFI -> ArmV8_embed_types.SystemHintOp_WFI - | SystemHintOp_SEV -> ArmV8_embed_types.SystemHintOp_SEV - | SystemHintOp_SEVL -> ArmV8_embed_types.SystemHintOp_SEVL - -let translate_accType _ = function - | AccType_NORMAL -> ArmV8_embed_types.AccType_NORMAL - | AccType_VEC -> ArmV8_embed_types.AccType_VEC - | AccType_STREAM -> ArmV8_embed_types.AccType_STREAM - | AccType_VECSTREAM -> ArmV8_embed_types.AccType_VECSTREAM - | AccType_ATOMIC -> ArmV8_embed_types.AccType_ATOMIC - | AccType_ORDERED -> ArmV8_embed_types.AccType_ORDERED - | AccType_UNPRIV -> ArmV8_embed_types.AccType_UNPRIV - | AccType_IFETCH -> ArmV8_embed_types.AccType_IFETCH - | AccType_PTW -> ArmV8_embed_types.AccType_PTW - | AccType_DC -> ArmV8_embed_types.AccType_DC - | AccType_IC -> ArmV8_embed_types.AccType_IC - | AccType_AT -> ArmV8_embed_types.AccType_AT - -let translate_memOp _ = function - | MemOp_LOAD -> ArmV8_embed_types.MemOp_LOAD - | MemOp_STORE -> ArmV8_embed_types.MemOp_STORE - | MemOp_PREFETCH -> ArmV8_embed_types.MemOp_PREFETCH - -let translate_moveWideOp _ = function - | MoveWideOp_N -> ArmV8_embed_types.MoveWideOp_N - | MoveWideOp_Z -> ArmV8_embed_types.MoveWideOp_Z - | MoveWideOp_K -> ArmV8_embed_types.MoveWideOp_K - -let translate_revOp _ = function - | RevOp_RBIT -> ArmV8_embed_types.RevOp_RBIT - | RevOp_REV16 -> ArmV8_embed_types.RevOp_REV16 - | RevOp_REV32 -> ArmV8_embed_types.RevOp_REV32 - | RevOp_REV64 -> ArmV8_embed_types.RevOp_REV64 - -let translate_pSTATEField _ = function - | PSTATEField_DAIFSet -> ArmV8_embed_types.PSTATEField_DAIFSet - | PSTATEField_DAIFClr -> ArmV8_embed_types.PSTATEField_DAIFClr - | PSTATEField_SP -> ArmV8_embed_types.PSTATEField_SP diff --git a/arm/gen/lexer.hgen b/arm/gen/lexer.hgen deleted file mode 100644 index 6ff24317..00000000 --- a/arm/gen/lexer.hgen +++ /dev/null @@ -1,309 +0,0 @@ -(* instructions: *) - - "TSTART" , TSTART {txt="TSTART"} ; - "TCOMMIT", TCOMMIT {txt="TCOMMIT"} ; - "TABORT" , TABORT {txt="TABORT"} ; - "TTEST" , TTEST {txt="TTEST"} ; - - "ADC" , ADCSBC {txt="ADC"; sub_op = false; setflags = false} ; - "SBC" , ADCSBC {txt="SBC"; sub_op = true; setflags = false} ; - "ADCS" , ADCSBC {txt="ADCS"; sub_op = false; setflags = true} ; - "SBCS" , ADCSBC {txt="SBCS"; sub_op = true; setflags = true} ; - - "ADD" , ADDSUB {txt="ADD"; sub_op=false; setflags=false} ; - "SUB" , ADDSUB {txt="SUB"; sub_op=true; setflags=false} ; - "ADDS" , ADDSUB {txt="ADDS"; sub_op=false; setflags=true} ; - "SUBS" , ADDSUB {txt="SUBS"; sub_op=true; setflags=true} ; - - "ADR" , ADR {txt="ADR"; page=false} ; - "ADRP" , ADR {txt="ADRP"; page=true} ; - - "AND" , LOGOP {txt="AND"; op = LogicalOp_AND; setflags = false; invert = false} ; - "ANDS" , LOGOP {txt="ANDS"; op = LogicalOp_AND; setflags = true; invert = false} ; - "EOR" , LOGOP {txt="EOR"; op = LogicalOp_EOR; setflags = false; invert = false} ; - "ORR" , LOGOP {txt="ORR"; op = LogicalOp_ORR; setflags = false; invert = false} ; - "BIC" , LOGOP {txt="BIC"; op = LogicalOp_AND; setflags = false; invert = true} ; - "BICS" , LOGOP {txt="BICS"; op = LogicalOp_AND; setflags = true; invert = true} ; - "EON" , LOGOP {txt="EON"; op = LogicalOp_EOR; setflags = false; invert = true} ; - "ORN" , LOGOP {txt="ORN"; op = LogicalOp_ORR; setflags = false; invert = true} ; - - "ASRV" , SHIFTOP {txt="ASRV"; shift_type=ShiftType_ASR} ; - "LSLV" , SHIFTOP {txt="LSLV"; shift_type=ShiftType_LSL} ; - "LSRV" , SHIFTOP {txt="LSRV"; shift_type=ShiftType_LSR} ; - "RORV" , SHIFTOP {txt="RORV"; shift_type=ShiftType_ROR} ; - - "B.EQ" , BCOND {txt="B.EQ"; condition=0b0000} ; - "B.NE" , BCOND {txt="B.NE"; condition=0b0001} ; - "B.CS" , BCOND {txt="B.CS"; condition=0b0010} ; - "B.HS" , BCOND {txt="B.CS"; condition=0b0010} ; - "B.CC" , BCOND {txt="B.CC"; condition=0b0011} ; - "B.LO" , BCOND {txt="B.CC"; condition=0b0011} ; - "B.MI" , BCOND {txt="B.MI"; condition=0b0100} ; - "B.PL" , BCOND {txt="B.PL"; condition=0b0101} ; - "B.VS" , BCOND {txt="B.VS"; condition=0b0110} ; - "B.VC" , BCOND {txt="B.VC"; condition=0b0111} ; - "B.HI" , BCOND {txt="B.HI"; condition=0b1000} ; - "B.LS" , BCOND {txt="B.LS"; condition=0b1001} ; - "B.GE" , BCOND {txt="B.GE"; condition=0b1010} ; - "B.LT" , BCOND {txt="B.LT"; condition=0b1011} ; - "B.GT" , BCOND {txt="B.GT"; condition=0b1100} ; - "B.LE" , BCOND {txt="B.LE"; condition=0b1101} ; - "B.AL" , BCOND {txt="B.AL"; condition=0b1110} ; - "B.NV" , BCOND {txt="B.NV"; condition=0b1111} ; (* ARM: exists only to provide a valid disassembly - of the 0b1111 encoding, otherwise its - behavior is identical to AL *) - - "B" , B {txt="B"; branch_type=BranchType_JMP} ; - "BL" , B {txt="BL"; branch_type=BranchType_CALL} ; - - "BR" , BR {txt="BR"; branch_type=BranchType_JMP} ; - "BLR" , BR {txt="BLR"; branch_type=BranchType_CALL} ; - - "CBZ" , CBZ {txt="CBZ"; iszero=true} ; - "CBNZ" , CBZ {txt="CBNZ"; iszero=false} ; - - "BFM" , BFM {txt="BFM"; inzero=false; extend=false} ; - "SBFM" , BFM {txt="SBFM"; inzero=true; extend=true} ; - "UBFM" , BFM {txt="UBFM"; inzero=true; extend=false} ; - - "CCMN" , CCM {txt="CCMN"; sub_op=false} ; - "CCMP" , CCM {txt="CCMP"; sub_op=true} ; - - "CMN" , CM {txt="CMN"; sub_op=false} ; - "CMP" , CM {txt="CMP"; sub_op=true} ; - - "CLS" , CL {txt="CLS"; opcode=CountOp_CLS} ; - "CLZ" , CL {txt="CLZ"; opcode=CountOp_CLZ} ; - - "CRC32B" , CRC {txt="CRC32B"; size = DataSize8; crc32c = false} ; - "CRC32H" , CRC {txt="CRC32H"; size = DataSize16; crc32c = false} ; - "CRC32W" , CRC {txt="CRC32W"; size = DataSize32; crc32c = false} ; - "CRC32CB" , CRC {txt="CRC32CB"; size = DataSize8; crc32c = true} ; - "CRC32CH" , CRC {txt="CRC32CH"; size = DataSize16; crc32c = true} ; - "CRC32CW" , CRC {txt="CRC32CW"; size = DataSize32; crc32c = true} ; - - "CRC32X" , CRC32X {txt="CRC32X"; crc32c=false} ; - "CRC32CX" , CRC32X {txt="CRC32CX"; crc32c=true} ; - - "CSEL" , CSEL {txt="CSEL"; else_inv = false; else_inc = false} ; - "CSINC" , CSEL {txt="CSINC"; else_inv = false; else_inc = true} ; - "CSINV" , CSEL {txt="CSINV"; else_inv = true; else_inc = false} ; - "CSNEG" , CSEL {txt="CSNEG"; else_inv = true; else_inc = true} ; - - "CSET" , CSET {txt="CSET"; else_inv = false; else_inc = true} ; - "CSETM" , CSETM {txt="CSETM"; else_inv = true; else_inc = false} ; - - "CINC" , CON {txt="CINC"; else_inv = false; else_inc = true} ; - "CINV" , CON {txt="CINV"; else_inv = true; else_inc = false} ; - "CNEG" , CON {txt="CNEG"; else_inv = true; else_inc = true} ; - - "DMB" , MEMBARR {txt="DMB"; op=MemBarrierOp_DMB} ; - "DSB" , MEMBARR {txt="DSB"; op=MemBarrierOp_DSB} ; - - "LDAR" , LDAXR {txt="LDAR"; acctype=AccType_ORDERED; excl=false; memop=MemOp_LOAD; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "LDARB" , LDAXR {txt="LDARB"; acctype=AccType_ORDERED; excl=false; memop=MemOp_LOAD; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "LDARH" , LDAXR {txt="LDARH"; acctype=AccType_ORDERED; excl=false; memop=MemOp_LOAD; var32={elsize=16; datasize=DataSize16}; var64=false} ; - "LDAXR" , LDAXR {txt="LDAXR"; acctype=AccType_ORDERED; excl=true; memop=MemOp_LOAD; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "LDAXRB" , LDAXR {txt="LDAXRB"; acctype=AccType_ORDERED; excl=true; memop=MemOp_LOAD; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "LDAXRH" , LDAXR {txt="LDAXRH"; acctype=AccType_ORDERED; excl=true; memop=MemOp_LOAD; var32={elsize=16; datasize=DataSize16}; var64=false} ; - "LDXR" , LDAXR {txt="LDXR"; acctype=AccType_ATOMIC; excl=true; memop=MemOp_LOAD; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "LDXRB" , LDAXR {txt="LDXRB"; acctype=AccType_ATOMIC; excl=true; memop=MemOp_LOAD; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "LDXRH" , LDAXR {txt="LDXRH"; acctype=AccType_ATOMIC; excl=true; memop=MemOp_LOAD; var32={elsize=16; datasize=DataSize16}; var64=false} ; - "STLR" , LDAXR {txt="STLR"; acctype=AccType_ORDERED; excl=false; memop=MemOp_STORE; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "STLRB" , LDAXR {txt="STLRB"; acctype=AccType_ORDERED; excl=false; memop=MemOp_STORE; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "STLRH" , LDAXR {txt="STLRH"; acctype=AccType_ORDERED; excl=false; memop=MemOp_STORE; var32={elsize=16; datasize=DataSize16}; var64=false} ; - - "STLXR" , STLXR {txt="STLXR"; acctype=AccType_ORDERED; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "STLXRB" , STLXR {txt="STLXRB"; acctype=AccType_ORDERED; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "STLXRH" , STLXR {txt="STLXRH"; acctype=AccType_ORDERED; var32={elsize=16; datasize=DataSize16}; var64=false} ; - "STXR" , STLXR {txt="STXR"; acctype=AccType_ATOMIC; var32={elsize=32; datasize=DataSize32}; var64=true} ; - "STXRB" , STLXR {txt="STXRB"; acctype=AccType_ATOMIC; var32={elsize=8; datasize=DataSize8}; var64=false} ; - "STXRH" , STLXR {txt="STXRH"; acctype=AccType_ATOMIC; var32={elsize=16; datasize=DataSize16}; var64=false} ; - - - "LDAXP" , LDXP {txt="LDAXP"; acctype=AccType_ORDERED} ; - "LDXP" , LDXP {txt="LDXP"; acctype=AccType_ATOMIC} ; - - "STLXP" , STXP {txt="STLXP"; acctype=AccType_ORDERED} ; - "STXP" , STXP {txt="STXP"; acctype=AccType_ATOMIC} ; - - "LDR" , LDSTR {txt="LDR"; memop=MemOp_LOAD; signed=false; lit32=true; var32=Some {datasize=DataSize32}; var64=Some {datasize=DataSize64}; lit64=Some {datasize=DataSize64; size=8}} ; - "LDRB" , LDSTR {txt="LDRB"; memop=MemOp_LOAD; signed=false; lit32=false; var32=Some {datasize=DataSize8}; var64=None; lit64=None} ; - "LDRH" , LDSTR {txt="LDRH"; memop=MemOp_LOAD; signed=false; lit32=false; var32=Some {datasize=DataSize16}; var64=None; lit64=None} ; - "LDRSB" , LDSTR {txt="LDRSB"; memop=MemOp_LOAD; signed=true; lit32=false; var32=Some {datasize=DataSize8}; var64=Some {datasize=DataSize8}; lit64=None} ; - "LDRSH" , LDSTR {txt="LDRSH"; memop=MemOp_LOAD; signed=true; lit32=false; var32=Some {datasize=DataSize16}; var64=Some {datasize=DataSize16}; lit64=None} ; - "LDRSW" , LDSTR {txt="LDRSW"; memop=MemOp_LOAD; signed=true; lit32=false; var32=None; var64=Some {datasize=DataSize32}; lit64=Some {datasize=DataSize32; size=4}} ; - "STR" , LDSTR {txt="STR"; memop=MemOp_STORE; signed=false; lit32=false; var32=Some {datasize=DataSize32}; var64=Some {datasize=DataSize64}; lit64=None} ; - "STRB" , LDSTR {txt="STRB"; memop=MemOp_STORE; signed=false; lit32=false; var32=Some {datasize=DataSize8}; var64=None; lit64=None} ; - "STRH" , LDSTR {txt="STRH"; memop=MemOp_STORE; signed=false; lit32=false; var32=Some {datasize=DataSize16}; var64=None; lit64=None} ; - - "LDTR" , LDSTTUR {txt="LDTR"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize32}; off64=Some {datasize=DataSize64}} ; - "LDTRB" , LDSTTUR {txt="LDTRB"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize8}; off64=None} ; - "LDTRH" , LDSTTUR {txt="LDTRH"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize16}; off64=None} ; - "LDTRSB" , LDSTTUR {txt="LDTRSB"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=true; off32=Some {datasize=DataSize8}; off64=Some {datasize=DataSize8}} ; - "LDTRSH" , LDSTTUR {txt="LDTRSH"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=true; off32=Some {datasize=DataSize16}; off64=Some {datasize=DataSize16}} ; - "LDTRSW" , LDSTTUR {txt="LDTRSW"; memop=MemOp_LOAD; acctype=AccType_UNPRIV; signed=true; off32=None; off64=Some {datasize=DataSize32}} ; - "LDUR" , LDSTTUR {txt="LDUR"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize32}; off64=Some {datasize=DataSize64}} ; - "LDURB" , LDSTTUR {txt="LDURB"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize8}; off64=None} ; - "LDURH" , LDSTTUR {txt="LDURH"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize16}; off64=None} ; - "LDURSB" , LDSTTUR {txt="LDURSB"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=true; off32=Some {datasize=DataSize8}; off64=Some {datasize=DataSize8}} ; - "LDURSH" , LDSTTUR {txt="LDURSH"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=true; off32=Some {datasize=DataSize16}; off64=Some {datasize=DataSize16}} ; - "LDURSW" , LDSTTUR {txt="LDURSW"; memop=MemOp_LOAD; acctype=AccType_NORMAL; signed=true; off32=None; off64=Some {datasize=DataSize32}} ; - "STTR" , LDSTTUR {txt="STTR"; memop=MemOp_STORE; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize32}; off64=Some {datasize=DataSize64}} ; - "STTRB" , LDSTTUR {txt="STTRB"; memop=MemOp_STORE; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize8}; off64=None} ; - "STTRH" , LDSTTUR {txt="STTRH"; memop=MemOp_STORE; acctype=AccType_UNPRIV; signed=false; off32=Some {datasize=DataSize16}; off64=None} ; - "STUR" , LDSTTUR {txt="STUR"; memop=MemOp_STORE; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize32}; off64=Some {datasize=DataSize64}} ; - "STURB" , LDSTTUR {txt="STURB"; memop=MemOp_STORE; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize8}; off64=None} ; - "STURH" , LDSTTUR {txt="STURH"; memop=MemOp_STORE; acctype=AccType_NORMAL; signed=false; off32=Some {datasize=DataSize16}; off64=None} ; - - "MADD" , MADDSUB {txt="MADD"; sub_op=false} ; - "MSUB" , MADDSUB {txt="MSUB"; sub_op=true} ; - - "MUL" , MUL {txt="MUL"; sub_op=false} ; - "MNEG" , MUL {txt="MNEG"; sub_op=true} ; - - "MOVK" , MOVWIDE {txt="MOVK"; opcode=MoveWideOp_K} ; - "MOVN" , MOVWIDE {txt="MOVN"; opcode=MoveWideOp_N} ; - "MOVZ" , MOVWIDE {txt="MOVZ"; opcode=MoveWideOp_Z} ; - - "NEG" , NEG {txt="NEG"; setflags=false} ; - "NEGS" , NEG {txt="NEGS"; setflags=true} ; - - "NGC" , NGC {txt="NGC"; setflags=false} ; - "NGCS" , NGC {txt="NGCS"; setflags=true} ; - - "RBIT" , REV {txt="RBIT"; op32=Some RevOp_RBIT; op64=RevOp_RBIT} ; - "REV" , REV {txt="REV"; op32=Some RevOp_REV32; op64=RevOp_REV64} ; - "REV16" , REV {txt="REV16"; op32=Some RevOp_REV16; op64=RevOp_REV16} ; - "REV32" , REV {txt="REV32"; op32=None; op64=RevOp_REV32} ; - - "SDIV" , DIV {txt="SDIV"; unsigned=false} ; - "UDIV" , DIV {txt="UDIV"; unsigned=true} ; - - "SMADDL" , MADDSUBL {txt="SMADDL"; sub_op=false; unsigned=false} ; - "SMSUBL" , MADDSUBL {txt="SMSUBL"; sub_op=true; unsigned=false} ; - "UMADDL" , MADDSUBL {txt="UMADDL"; sub_op=false; unsigned=true} ; - "UMSUBL" , MADDSUBL {txt="UMSUBL"; sub_op=true; unsigned=true} ; - - "SMULH" , MULH {txt="SMULH"; unsigned=false} ; - "UMULH" , MULH {txt="UMULH"; unsigned=true} ; - - "SMULL" , MULL {txt="SMULL"; unsigned=false} ; - "UMULL" , MULL {txt="UMULL"; unsigned=true} ; - - "LDP" , LDSTP {txt="LDP"; memop=MemOp_LOAD} ; - "STP" , LDSTP {txt="STP"; memop=MemOp_STORE} ; - - "TBZ" , TBZ {txt="TBZ"; bit_val=false} ; - "TBNZ" , TBZ {txt="TBNZ"; bit_val=true} ; - - "SBFIZ" , BFIZ {txt="SBFIZ"; extend=true} ; - "UBFIZ" , BFIZ {txt="UBFIZ"; extend=false} ; - - "SBFX" , BFX {txt="SBFX"; extend=true} ; - "UBFX" , BFX {txt="UBFX"; extend=false} ; - - "SMNEGL" , MNEGL {txt="SMNEGL"; unsigned=false} ; - "UMNEGL" , MNEGL {txt="UMNEGL"; unsigned=true} ; - - "BFI" , BFI {txt="BFI"} ; - "BFXIL" , BFXIL {txt="BFXIL"} ; - "CLREX" , CLREX {txt="CLREX"} ; - "EXTR" , EXTR {txt="EXTR"} ; - "HINT" , HINT {txt="HINT"} ; - "ISB" , ISB {txt="ISB"} ; - "LDPSW" , LDPSW {txt="LDPSW"} ; - "MOV" , MOV {txt="MOV"} ; - "MVN" , MVN {txt="MVN"} ; - "NOP" , NOP {txt="NOP"} ; - "PRFM" , PRFM {txt="PRFM"} ; - "PRFUM" , PRFUM {txt="PRFUM"} ; - "RET" , RET {txt="RET"} ; - "TST" , TST {txt="TST"} ; - "MRS" , MRS {txt="MRS"} ; - "MSR" , MSR {txt="MSR"} ; - - -(*** instructions/operands ***) - - "LSL" , SHIFT {txt="LSL"; shift_type=ShiftType_LSL} ; - "LSR" , SHIFT {txt="LSR"; shift_type=ShiftType_LSR} ; - "ASR" , SHIFT {txt="ASR"; shift_type=ShiftType_ASR} ; - "ROR" , SHIFT {txt="ROR"; shift_type=ShiftType_ROR} ; - - "UXTB" , EXTEND {txt="UXTB"; _type=ExtendType_UXTB; inst=Some {extend=false; imms=7}} ; - "UXTH" , EXTEND {txt="UXTH"; _type=ExtendType_UXTH; inst=Some {extend=false; imms=15}} ; - "UXTW" , EXTEND {txt="UXTW"; _type=ExtendType_UXTW; inst=None} ; - "UXTX" , EXTEND {txt="UXTX"; _type=ExtendType_UXTX; inst=None} ; - "SXTB" , EXTEND {txt="SXTB"; _type=ExtendType_SXTB; inst=Some {extend=true; imms=7}} ; - "SXTH" , EXTEND {txt="SXTH"; _type=ExtendType_SXTH; inst=Some {extend=true; imms=15}} ; - "SXTW" , EXTEND {txt="SXTW"; _type=ExtendType_SXTW; inst=Some {extend=true; imms=31}} ; - "SXTX" , EXTEND {txt="SXTX"; _type=ExtendType_SXTX; inst=None} ; - -(*** operands: ***) - - "EQ" , COND 0b0000 ; - "NE" , COND 0b0001 ; - "CS" , COND 0b0010 ; - "HS" , COND 0b0010 ; - "CC" , COND 0b0011 ; - "LO" , COND 0b0011 ; - "MI" , COND 0b0100 ; - "PL" , COND 0b0101 ; - "VS" , COND 0b0110 ; - "VC" , COND 0b0111 ; - "HI" , COND 0b1000 ; - "LS" , COND 0b1001 ; - "GE" , COND 0b1010 ; - "LT" , COND 0b1011 ; - "GT" , COND 0b1100 ; - "LE" , COND 0b1101 ; - "AL" , COND 0b1110 ; - "NV" , COND 0b1111 ; (* ARM: exists only to provide a valid disassembly - of the 0b1111 encoding, otherwise its - behavior is identical to AL *) - - "OSHLD" , BARROP {domain=MBReqDomain_OuterShareable; types=MBReqTypes_Reads} ; - "OSHST" , BARROP {domain=MBReqDomain_OuterShareable; types=MBReqTypes_Writes} ; - "OSH" , BARROP {domain=MBReqDomain_OuterShareable; types=MBReqTypes_All} ; - "NSHLD" , BARROP {domain=MBReqDomain_Nonshareable; types=MBReqTypes_Reads} ; - "NSHST" , BARROP {domain=MBReqDomain_Nonshareable; types=MBReqTypes_Writes} ; - "NSH" , BARROP {domain=MBReqDomain_Nonshareable; types=MBReqTypes_All} ; - "ISHLD" , BARROP {domain=MBReqDomain_InnerShareable; types=MBReqTypes_Reads} ; - "ISHST" , BARROP {domain=MBReqDomain_InnerShareable; types=MBReqTypes_Writes} ; - "ISH" , BARROP {domain=MBReqDomain_InnerShareable; types=MBReqTypes_All} ; - "LD" , BARROP {domain=MBReqDomain_FullSystem; types=MBReqTypes_Reads} ; - "ST" , BARROP {domain=MBReqDomain_FullSystem; types=MBReqTypes_Writes} ; - "SY" , BARROP {domain=MBReqDomain_FullSystem; types=MBReqTypes_All} ; - - "PLDL1KEEP" , PRFOP (X (Ireg R0)) ; - "PLDL1STRM" , PRFOP (X (Ireg R1)) ; - "PLDL2KEEP" , PRFOP (X (Ireg R2)) ; - "PLDL2STRM" , PRFOP (X (Ireg R3)) ; - "PLDL3KEEP" , PRFOP (X (Ireg R4)) ; - "PLDL3STRM" , PRFOP (X (Ireg R5)) ; - - "PLIL1KEEP" , PRFOP (X (Ireg R8)) ; - "PLIL1STRM" , PRFOP (X (Ireg R9)) ; - "PLIL2KEEP" , PRFOP (X (Ireg R10)) ; - "PLIL2STRM" , PRFOP (X (Ireg R11)) ; - "PLIL3KEEP" , PRFOP (X (Ireg R12)) ; - "PLIL3STRM" , PRFOP (X (Ireg R13)) ; - - "PSTL1KEEP" , PRFOP (X (Ireg R16)) ; - "PSTL1STRM" , PRFOP (X (Ireg R17)) ; - "PSTL2KEEP" , PRFOP (X (Ireg R18)) ; - "PSTL2STRM" , PRFOP (X (Ireg R19)) ; - "PSTL3KEEP" , PRFOP (X (Ireg R20)) ; - "PSTL3STRM" , PRFOP (X (Ireg R21)) ; - - "NZCV" , SYSREG {sys_op0=0b11; sys_op1=0b011; sys_op2=0b000; sys_crn=0b0100; sys_crm=0b0010} ; - "DAIF" , SYSREG {sys_op0=0b11; sys_op1=0b011; sys_op2=0b001; sys_crn=0b0100; sys_crm=0b0010} ; - "TPIDR_EL0" , SYSREG {sys_op0=0b11; sys_op1=0b011; sys_op2=0b010; sys_crn=0b1101; sys_crm=0b0000} ; - "TPIDR_EL1" , SYSREG {sys_op0=0b11; sys_op1=0b000; sys_op2=0b100; sys_crn=0b1101; sys_crm=0b0000} ; - "TPIDR_EL2" , SYSREG {sys_op0=0b11; sys_op1=0b100; sys_op2=0b010; sys_crn=0b1101; sys_crm=0b0000} ; - "TPIDR_EL3" , SYSREG {sys_op0=0b11; sys_op1=0b011; sys_op2=0b011; sys_crn=0b1101; sys_crm=0b0000} ; - - "SPSel" , PSTATEFIELD (PSTATEField_SP) ; - "DAIFSet" , PSTATEFIELD (PSTATEField_DAIFSet) ; - "DAIFClr" , PSTATEFIELD (PSTATEField_DAIFClr) ; diff --git a/arm/gen/map.hgen b/arm/gen/map.hgen deleted file mode 100644 index 62899c91..00000000 --- a/arm/gen/map.hgen +++ /dev/null @@ -1,44 +0,0 @@ -| `AArch64TMStart t -> `AArch64TMStart (map_reg t) -| `AArch64TMCommit -> `AArch64TMCommit -| `AArch64TMAbort (retry,reason) -> `AArch64TMAbort (retry,reason) -| `AArch64TMTest -> `AArch64TMTest - -| `AArch64ImplementationDefinedStopFetching -> `AArch64ImplementationDefinedStopFetching -| `AArch64ImplementationDefinedThreadStart -> `AArch64ImplementationDefinedThreadStart -| `AArch64ImplementationDefinedTestBeginEnd (isEnd) -> `AArch64ImplementationDefinedTestBeginEnd (isEnd) -| `AArch64AddSubCarry (d,n,m,datasize,sub_op,setflags) -> `AArch64AddSubCarry (map_reg d,map_reg n,map_reg m,datasize,sub_op,setflags) -| `AArch64AddSubExtendRegister (d,n,m,datasize,sub_op,setflags,extend_type,shift) -> `AArch64AddSubExtendRegister (map_reg d,map_reg n,map_reg m,datasize,sub_op,setflags,extend_type,shift) -| `AArch64AddSubShiftedRegister (d,n,m,datasize,sub_op,setflags,shift_type,shift_amount) -> `AArch64AddSubShiftedRegister (map_reg d,map_reg n,map_reg m,datasize,sub_op,setflags,shift_type,shift_amount) -| `AArch64AddSubImmediate (d,n,datasize,sub_op,setflags,imm) -> `AArch64AddSubImmediate (map_reg d,map_reg n,datasize,sub_op,setflags,imm) -| `AArch64Address (d,page,imm) -> `AArch64Address (map_reg d,page,imm) -| `AArch64LogicalImmediate (d,n,datasize,setflags,op,imm) -> `AArch64LogicalImmediate (map_reg d,map_reg n,datasize,setflags,op,imm) -| `AArch64LogicalShiftedRegister (d,n,m,datasize,setflags,op,shift_type,shift_amount,invert) -> `AArch64LogicalShiftedRegister (map_reg d,map_reg n,map_reg m,datasize,setflags,op,shift_type,shift_amount,invert) -| `AArch64Shift (d,n,m,datasize,shift_type) -> `AArch64Shift (map_reg d,map_reg n,map_reg m,datasize,shift_type) -| `AArch64BranchConditional (offset,condition) -> `AArch64BranchConditional (offset,condition) -| `AArch64BranchImmediate (branch_type,offset) -> `AArch64BranchImmediate (branch_type,offset) -| `AArch64BitfieldMove (d,n,datasize,inzero,extend,_R,_S,wmask,tmask) -> `AArch64BitfieldMove (map_reg d,map_reg n,datasize,inzero,extend,_R,_S,wmask,tmask) -| `AArch64BranchRegister (n,branch_type) -> `AArch64BranchRegister (map_reg n,branch_type) -| `AArch64CompareAndBranch (t,datasize,iszero,offset) -> `AArch64CompareAndBranch (map_reg t,datasize,iszero,offset) -| `AArch64ConditionalCompareImmediate (n,datasize,sub_op,condition,flags,imm) -> `AArch64ConditionalCompareImmediate (map_reg n,datasize,sub_op,condition,flags,imm) -| `AArch64ConditionalCompareRegister (n,m,datasize,sub_op,condition,flags) -> `AArch64ConditionalCompareRegister (map_reg n,map_reg m,datasize,sub_op,condition,flags) -| `AArch64ClearExclusiveMonitor (imm) -> `AArch64ClearExclusiveMonitor (imm) -| `AArch64CountLeading (d,n,datasize,opcode) -> `AArch64CountLeading (map_reg d,map_reg n,datasize,opcode) -| `AArch64CRC (d,n,m,size,crc32c) -> `AArch64CRC (map_reg d,map_reg n,map_reg m,size,crc32c) -| `AArch64ConditionalSelect (d,n,m,datasize,condition,else_inv,else_inc) -> `AArch64ConditionalSelect (map_reg d,map_reg n,map_reg m,datasize,condition,else_inv,else_inc) -| `AArch64Barrier (op,domain,types) -> `AArch64Barrier (op,domain,types) -| `AArch64ExtractRegister (d,n,m,datasize,lsb) -> `AArch64ExtractRegister (map_reg d,map_reg n,map_reg m,datasize,lsb) -| `AArch64Hint (op) -> `AArch64Hint (op) -| `AArch64LoadStoreAcqExc (n,t,t2,s,acctype,excl,pair,memop,elsize,regsize,datasize) -> `AArch64LoadStoreAcqExc (map_reg n,map_reg t,map_reg t2,map_reg s,acctype,excl,pair,memop,elsize,regsize,datasize) -| `AArch64LoadStorePair (wback,postindex,n,t,t2,acctype,memop,signed,datasize,offset) -> `AArch64LoadStorePair (wback,postindex,map_reg n,map_reg t,map_reg t2,acctype,memop,signed,datasize,offset) -| `AArch64LoadImmediate (n,t,acctype,memop,signed,wback,postindex,offset,regsize,datasize) -> `AArch64LoadImmediate (map_reg n,map_reg t,acctype,memop,signed,wback,postindex,offset,regsize,datasize) -| `AArch64LoadLiteral (t,memop,signed,size,offset,datasize) -> `AArch64LoadLiteral (map_reg t,memop,signed,size,offset,datasize) -| `AArch64LoadRegister (n,t,m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize) -> `AArch64LoadRegister (map_reg n,map_reg t,map_reg m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize) -| `AArch64MultiplyAddSub (d,n,m,a,destsize,datasize,sub_op) -> `AArch64MultiplyAddSub (map_reg d,map_reg n,map_reg m,map_reg a,destsize,datasize,sub_op) -| `AArch64MoveWide (d,datasize,imm,pos,opcode) -> `AArch64MoveWide (map_reg d,datasize,imm,pos,opcode) -| `AArch64Reverse (d,n,datasize,op) -> `AArch64Reverse (map_reg d,map_reg n,datasize,op) -| `AArch64Division (d,n,m,datasize,unsigned) -> `AArch64Division (map_reg d,map_reg n,map_reg m,datasize,unsigned) -| `AArch64MultiplyAddSubLong (d,n,m,a,destsize,datasize,sub_op,unsigned) -> `AArch64MultiplyAddSubLong (map_reg d,map_reg n,map_reg m,map_reg a,destsize,datasize,sub_op,unsigned) -| `AArch64MultiplyHigh (d,n,m,a,destsize,datasize,unsigned) -> `AArch64MultiplyHigh (map_reg d,map_reg n,map_reg m,map_reg a,destsize,datasize,unsigned) -| `AArch64TestBitAndBranch (t,datasize,bit_pos,bit_val,offset) -> `AArch64TestBitAndBranch (map_reg t,datasize,bit_pos,bit_val,offset) -| `AArch64MoveSystemRegister (t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read) -> `AArch64MoveSystemRegister (map_reg t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read) -| `AArch64MoveSystemImmediate (operand,field) -> `AArch64MoveSystemImmediate (operand,field) diff --git a/arm/gen/parser.hgen b/arm/gen/parser.hgen deleted file mode 100644 index 94ce6fcf..00000000 --- a/arm/gen/parser.hgen +++ /dev/null @@ -1,1396 +0,0 @@ - /* TSTART */ - | TSTART xreg - { if not (isregzr $2) then error_registers ("expected " ^ $1.txt ^ " ") - else `AArch64TMStart $2 } - - /* TCOMMIT */ - | TCOMMIT - { `AArch64TMCommit } - - /* TABORT */ - | TABORT imm - { if not (iskbituimm 6 $2) then error_arg " must be in the range 0 to 63" - else `AArch64TMAbort (($2 lsr 5) <> 0, $2 mod 32) } - - /* TTEST */ - | TTEST - {`AArch64TMTest} - - | ADCSBC wreg COMMA wreg COMMA wreg - { if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , ") - else `AArch64AddSubCarry ($2,$4,$6,Set32,$1.sub_op,$1.setflags) } - | ADCSBC xreg COMMA xreg COMMA xreg - { if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , ") - else `AArch64AddSubCarry ($2,$4,$6,Set64,$1.sub_op,$1.setflags) } - - /* ADC/ADCS/SBC/SBCS */ - - | ADCSBC wreg COMMA wreg COMMA wreg - { if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , ") - else `AArch64AddSubCarry ($2,$4,$6,Set32,$1.sub_op,$1.setflags) } - | ADCSBC xreg COMMA xreg COMMA xreg - { if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , ") - else `AArch64AddSubCarry ($2,$4,$6,Set64,$1.sub_op,$1.setflags) } - - /* ADD/SUB/ADDS/SUBS (extended register), and when noted (shifted register) */ - - | ADDSUB wreg COMMA wreg COMMA wreg - { (* ambiguous with (shifted register) *) - if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then - error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then - error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else `AArch64AddSubExtendRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,ExtendType_UXTW,0) } - | ADDSUB wreg COMMA wreg COMMA wreg COMMA EXTEND - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then - error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then - error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else `AArch64AddSubExtendRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,$8._type,0) } - | ADDSUB wreg COMMA wreg COMMA wreg COMMA SHIFT - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if (not $1.setflags) && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else `AArch64AddSubExtendRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,ExtendType_UXTW,0) } - | ADDSUB wreg COMMA wreg COMMA wreg COMMA EXTEND imm - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4" - else `AArch64AddSubExtendRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,$8._type,$9) } - | ADDSUB wreg COMMA wreg COMMA wreg COMMA SHIFT imm - { if (issp $2 || issp $4) then - begin - (* (extended register) *) - if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4" - else `AArch64AddSubExtendRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,ExtendType_UXTW,$9) - end - else - begin - (* (shifted register) *) - if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, #}") - else if $8.shift_type = ShiftType_ROR then error_arg " must be one of LSL,LSR,ASR" - else if not (0 <= $9 && $9 <= 31) then error_arg " must be in the range 0 to 31" - else `AArch64AddSubShiftedRegister ($2,$4,$6,Set32,$1.sub_op,$1.setflags,$8.shift_type,$9) - end } - - | ADDSUB xreg COMMA xreg COMMA xreg - { (* ambiguous with (shifted register) *) - if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,ExtendType_UXTX,0) } - | ADDSUB xreg COMMA xreg COMMA wreg COMMA EXTEND - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if $8._type = ExtendType_UXTX || $8._type = ExtendType_SXTX then error_arg " doesn't match " - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,$8._type,0) } - | ADDSUB xreg COMMA xreg COMMA wreg COMMA SHIFT - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,ExtendType_UXTX,0) } - | ADDSUB xreg COMMA xreg COMMA wreg COMMA EXTEND imm - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4." - else if $8._type = ExtendType_UXTX || $8._type = ExtendType_SXTX then error_arg " doesn't match " - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,$8._type,$9) } - | ADDSUB xreg COMMA xreg COMMA wreg COMMA SHIFT imm - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4." - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,ExtendType_UXTX,$9) } - | ADDSUB xreg COMMA xreg COMMA xreg COMMA EXTEND - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8._type = ExtendType_UXTX || $8._type = ExtendType_SXTX) then error_arg " doesn't match " - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,$8._type,0) } - | ADDSUB xreg COMMA xreg COMMA xreg COMMA SHIFT - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,ExtendType_UXTX,0) } - | ADDSUB xreg COMMA xreg COMMA xreg COMMA EXTEND imm - { if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4." - else if not ($8._type = ExtendType_UXTX || $8._type = ExtendType_SXTX) then error_arg " doesn't match " - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,$8._type,$9) } - | ADDSUB xreg COMMA xreg COMMA xreg COMMA SHIFT imm - { if (issp $2 || issp $4) then - begin - (* (extended register) *) - if $1.setflags && not (isregzr $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not $1.setflags && not (isregsp $2 && isregsp $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, {#}}") - else if not ($8.shift_type = ShiftType_LSL) then error_arg " must be one of UXTB,UXTH,UXTW,UXTX,SXTB,SXTH,SXTW,SXTX,LSL" - else if not (0 <= $9 && $9 <= 4) then error_arg " must be in the range 0 to 4." - else `AArch64AddSubExtendRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,ExtendType_UXTX,$9) - end - else - begin - (* (shifted register) *) - if not (isregzr $2 && isregzr $4 && isregzr $6) then error_registers ("expected " ^ $1.txt ^ " , , {, #}") - else if $8.shift_type = ShiftType_ROR then error_arg " must be one of LSL,LSR,ASR" - else if not (0 <= $9 && $9 <= 63) then error_arg " must be in the range 0 to 63" - else `AArch64AddSubShiftedRegister ($2,$4,$6,Set64,$1.sub_op,$1.setflags,$8.shift_type,$9) - end } - - /* ADD/SUB/ADDS/SUBS (immediate) */ - - | ADDSUB wreg COMMA wreg COMMA imm - { if $1.setflags && not (isregzr $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not $1.setflags && not (isregsp $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not (0 <= $6 && $6 <= 4095) then error_arg " must be in the range 0 to 4095" - else `AArch64AddSubImmediate ($2,$4,Set32,$1.sub_op,$1.setflags,reg_size_bits_R32_of_int $6) } - | ADDSUB wreg COMMA wreg COMMA imm COMMA SHIFT imm - { if $1.setflags && not (isregzr $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not $1.setflags && not (isregsp $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not (0 <= $6 && $6 <= 4095) then error_arg " must be in the range 0 to 4095" - else if not ($8.shift_type = ShiftType_LSL && ($9 = 0 || $9 = 12)) then error_arg " must be 'LSL #0' or 'LSL #12'" - else `AArch64AddSubImmediate ($2,$4,Set32,$1.sub_op,$1.setflags,reg_size_bits_R32_of_int ($6 lsl $9)) } - | ADDSUB xreg COMMA xreg COMMA imm - { if $1.setflags && not (isregzr $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not $1.setflags && not (isregsp $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not (0 <= $6 && $6 <= 4095) then error_arg " must be in the range 0 to 4095" - else `AArch64AddSubImmediate ($2,$4,Set64,$1.sub_op,$1.setflags,reg_size_bits_R64_of_int $6) } - | ADDSUB xreg COMMA xreg COMMA imm COMMA SHIFT imm - { if $1.setflags && not (isregzr $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not $1.setflags && not (isregsp $2 && isregsp $4) then error_registers ("expected " ^ $1.txt ^ " , , #{, }") - else if not (0 <= $6 && $6 <= 4095) then error_arg " must be in the range 0 to 4095" - else if not ($8.shift_type = ShiftType_LSL && ($9 = 0 || $9 = 12)) then error_arg " must be 'LSL #0' or 'LSL #12'" - else `AArch64AddSubImmediate ($2,$4,Set64,$1.sub_op,$1.setflags,reg_size_bits_R64_of_int ($6 lsl $9)) } - - /* ADR/ADRP */ -/* - | ADR xreg COMMA NAME - { if not (isregzr $2) then error_registers ("expected " ^ $1.txt ^ " ,