From eae01f8c348235ea552c67ce323a1ada3dbc8b08 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Thu, 6 Sep 2018 17:17:23 +0100
Subject: RISCV: Get enough of the RISCV platform into C to run some tests

---
 lib/sail.c             |  7 ++++++-
 riscv/main.sail        |  4 +++-
 riscv/reset_vec.S      | 12 ++++++++++++
 riscv/riscv_platform.c | 34 ++++++++++++++++++++++++++--------
 4 files changed, 47 insertions(+), 10 deletions(-)
 create mode 100644 riscv/reset_vec.S

diff --git a/lib/sail.c b/lib/sail.c
index 886f6a37..42ee8209 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -1,3 +1,4 @@
+#define _GNU_SOURCE
 #include<assert.h>
 #include<inttypes.h>
 #include<stdbool.h>
@@ -1111,9 +1112,13 @@ void string_of_int(sail_string *str, const sail_int i)
   gmp_asprintf(str, "%Zd", i);
 }
 
+/* asprinf is a GNU extension, but it should exist on BSD */
 void string_of_mach_bits(sail_string *str, const mach_bits op)
 {
-  exit(EXIT_FAILURE);
+  int bytes = asprintf(str, "0x%" PRIx64, op);
+  if (bytes == -1) {
+    fprintf(stderr, "Could not print bits 0x%" PRIx64 "\n", op);
+  }
 }
 
 void string_of_sail_bits(sail_string *str, const sail_bits op)
diff --git a/riscv/main.sail b/riscv/main.sail
index 32f14177..dbf41f49 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -12,7 +12,9 @@ val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wre
 
 function main () = {
 
-  PC = __GetSlice_int(64, elf_entry(), 0);
+  // PC = __GetSlice_int(64, elf_entry(), 0);
+  PC = zero_extend(0x1000, 64);
+  print_bits("PC = ", PC);
   try {
     init_platform();
     init_sys();
diff --git a/riscv/reset_vec.S b/riscv/reset_vec.S
new file mode 100644
index 00000000..526bbc79
--- /dev/null
+++ b/riscv/reset_vec.S
@@ -0,0 +1,12 @@
+.global _start
+
+.text
+
+_start:
+	auipc	t0, 0x0
+	addi	a1, t0, 32
+	csrr	a0, mhartid
+	ld	t0, 24(t0)
+	jr	t0
+.short  0x0000
+.word	0x00000000, 0x80000000
diff --git a/riscv/riscv_platform.c b/riscv/riscv_platform.c
index d21824a3..6330ae4d 100644
--- a/riscv/riscv_platform.c
+++ b/riscv/riscv_platform.c
@@ -9,25 +9,41 @@ bool plat_enable_misaligned_access(unit u)
 { return false; }
 
 mach_bits plat_ram_base(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x80000000);
+}
 
 mach_bits plat_ram_size(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x80000000);
+}
 
 mach_bits plat_rom_base(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x1000);
+}
 
 mach_bits plat_rom_size(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x100);
+}
 
 mach_bits plat_clint_base(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x2000000);
+}
 
 mach_bits plat_clint_size(unit u)
-{ return 0; }
+{
+  return UINT64_C(0xc0000);
+}
 
 bool within_phys_mem(mach_bits addr, sail_int len)
-{ return 0; }
+{
+  printf("within_phys_mem\n");
+  exit(EXIT_FAILURE);
+  return 0;
+}
 
 unit load_reservation(mach_bits addr)
 { return UNIT; }
@@ -45,7 +61,9 @@ void plat_insns_per_tick(sail_int *rop, unit u)
 { }
 
 mach_bits plat_htif_tohost(unit u)
-{ return 0; }
+{
+  return UINT64_C(0x2000000);
+}
 
 unit memea(mach_bits len, sail_int n)
 {
-- 
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