From e865a47422dc186d9721cb208ebab1f1a7d7624e Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Mon, 7 May 2018 17:53:00 -0700
Subject: Adjust default pte update setting to match spike's default.

---
 riscv/riscv_vmem.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index cc365769..26282d3e 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -255,7 +255,7 @@ union TR39_Result = {
   TR39_Failure : PTW_Error
 }
 
-let enable_dirty_update = true
+let enable_dirty_update = false
 
 val translate39 : (vaddr39, AccessType, Privilege, bool, bool, nat) -> TR39_Result effect {rreg, wreg, wmv, escape, rmem}
 function translate39(vAddr, ac, priv, mxr, sum, level) = {
-- 
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