From 938f06bc6c711ef3e777beaace7da8d4aee158b9 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Thu, 10 May 2018 17:38:36 +0100 Subject: Document the register_inaccessible function. --- cheri/cheri_prelude_common.sail | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cheri/cheri_prelude_common.sail b/cheri/cheri_prelude_common.sail index e6273281..47c8759c 100644 --- a/cheri/cheri_prelude_common.sail +++ b/cheri/cheri_prelude_common.sail @@ -261,6 +261,9 @@ function pcc_access_system_regs () = let pcc = capRegToCapStruct(PCC) in (pcc.access_system_regs) +/*! +The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. + */ val register_inaccessible : regno -> bool effect {rreg} function register_inaccessible(r) = ((r == IDC) & inCCallDelay) | -- cgit v1.2.3 From 6846d314b5fdc90d7c3a3ee656ebbf12cbdf7f8d Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Thu, 10 May 2018 17:40:48 +0100 Subject: latex: don't include the prefix in the label. This means we have the option of omitting valspec in documentation if it is deemed too verbose and still have hyperlinks work. The caveat is that it could result in multiply defined labels. --- src/latex.ml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/latex.ml b/src/latex.ml index f16dddd8..8688eaa8 100644 --- a/src/latex.ml +++ b/src/latex.ml @@ -123,7 +123,7 @@ let commands = ref StringSet.empty let rec latex_command ?prefix:(prefix="") ?label:(label=None) dir cmd no_loc ((l, _) as annot) = let labelling = match label with | None -> "" - | Some l -> Printf.sprintf "\\label{%s%s}" prefix l + | Some l -> Printf.sprintf "\\label{%s}" l in let cmd = !opt_prefix_latex ^ prefix ^ cmd in if StringSet.mem cmd !commands then -- cgit v1.2.3 From 619bd9b568f6f8f5691a66602b7635834d3d13a2 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 11 May 2018 11:31:47 +0100 Subject: Avoid generating latex files that differ only by case because this causes confusion on case insensitive file systems (e.g. mac). --- src/latex.ml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/latex.ml b/src/latex.ml index 8688eaa8..3233a4ac 100644 --- a/src/latex.ml +++ b/src/latex.ml @@ -126,11 +126,12 @@ let rec latex_command ?prefix:(prefix="") ?label:(label=None) dir cmd no_loc ((l | Some l -> Printf.sprintf "\\label{%s}" l in let cmd = !opt_prefix_latex ^ prefix ^ cmd in - if StringSet.mem cmd !commands then + let lcmd = String.lowercase cmd in (* lowercase to avoid file names differing only by case *) + if StringSet.mem lcmd !commands then latex_command ~label:label dir (cmd ^ "v") no_loc annot else begin - commands := StringSet.add cmd !commands; + commands := StringSet.add lcmd !commands; let oc = open_out (Filename.concat dir (cmd ^ "_sail.tex")) in output_string oc (Pretty_print_sail.to_string (latex_loc no_loc l)); close_out oc; -- cgit v1.2.3 From 17c786ea27bf644efdae271b8a93bd5ce1d730e8 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 11 May 2018 11:32:31 +0100 Subject: Remove unneeded _sail suffix from latex files. --- src/latex.ml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/latex.ml b/src/latex.ml index 3233a4ac..0520d074 100644 --- a/src/latex.ml +++ b/src/latex.ml @@ -132,10 +132,10 @@ let rec latex_command ?prefix:(prefix="") ?label:(label=None) dir cmd no_loc ((l else begin commands := StringSet.add lcmd !commands; - let oc = open_out (Filename.concat dir (cmd ^ "_sail.tex")) in + let oc = open_out (Filename.concat dir (cmd ^ ".tex")) in output_string oc (Pretty_print_sail.to_string (latex_loc no_loc l)); close_out oc; - string (Printf.sprintf "\\newcommand{\\%s}{%s " cmd labelling) ^^ (docstring l) ^^ string (Printf.sprintf "\\lstinputlisting[language=sail]{%s/%s_sail.tex}}" dir cmd) + string (Printf.sprintf "\\newcommand{\\%s}{%s " cmd labelling) ^^ (docstring l) ^^ string (Printf.sprintf "\\lstinputlisting[language=sail]{%s/%s.tex}}" dir cmd) end let latex_command_id ?prefix:(prefix="") dir id no_loc annot = -- cgit v1.2.3 From db3b6d21c18f4ac516c2554db6890274d2b8292c Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Thu, 10 May 2018 14:23:49 +0100 Subject: Remove buggy bit list comparison functions from Lem library Found bugs by running CHERI test suite on Isabelle-exported model: signed less-than for bit lists was missing negations for the two's complement, and unsigned less-than compared the reverse lists. Since all other backends implement this in Sail, it seems best to just remove this code. Also add support for infix operators to Lem backend, by z-encoding their identifiers like the other backends do. --- mips/prelude.sail | 8 ++++---- riscv/prelude.sail | 10 +++++----- src/gen_lib/sail_operators.lem | 30 ------------------------------ src/gen_lib/sail_operators_bitlists.lem | 16 ---------------- src/gen_lib/sail_operators_mwords.lem | 16 ---------------- src/pretty_print_lem.ml | 22 ++++++++-------------- 6 files changed, 17 insertions(+), 85 deletions(-) diff --git a/mips/prelude.sail b/mips/prelude.sail index 152996f1..e0bcd8cf 100644 --- a/mips/prelude.sail +++ b/mips/prelude.sail @@ -242,10 +242,10 @@ infix 4 >=_s infix 4 <_u infix 4 >=_u -val operator <_s = {lem: "slt_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_s = {lem: "sgteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator <_u = {lem: "ult_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_u = {lem: "ugteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool +val operator <_s : forall 'n. (bits('n), bits('n)) -> bool +val operator >=_s : forall 'n. (bits('n), bits('n)) -> bool +val operator <_u : forall 'n. (bits('n), bits('n)) -> bool +val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool function operator <_s (x, y) = signed(x) < signed(y) function operator >=_s (x, y) = signed(x) >= signed(y) diff --git a/riscv/prelude.sail b/riscv/prelude.sail index d667573e..c92497c1 100644 --- a/riscv/prelude.sail +++ b/riscv/prelude.sail @@ -350,11 +350,11 @@ infix 4 <_u infix 4 >=_u infix 4 <=_u -val operator <_s = {lem: "slt_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_s = {lem: "sgteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator <_u = {lem: "ult_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_u = {lem: "ugteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool -val operator <=_u = {lem: "ulteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool +val operator <_s : forall 'n. (bits('n), bits('n)) -> bool +val operator >=_s : forall 'n. (bits('n), bits('n)) -> bool +val operator <_u : forall 'n. (bits('n), bits('n)) -> bool +val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool +val operator <=_u : forall 'n. (bits('n), bits('n)) -> bool function operator <_s (x, y) = signed(x) < signed(y) function operator >=_s (x, y) = signed(x) >= signed(y) diff --git a/src/gen_lib/sail_operators.lem b/src/gen_lib/sail_operators.lem index 78aab65e..0c5da675 100644 --- a/src/gen_lib/sail_operators.lem +++ b/src/gen_lib/sail_operators.lem @@ -194,36 +194,6 @@ let neq_bv l r = not (eq_bv l r) let inline neq_mword l r = (l <> r) -val ult_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool -let ult_bv l r = lexicographicLess (List.reverse (bits_of l)) (List.reverse (bits_of r)) -let ulteq_bv l r = (eq_bv l r) || (ult_bv l r) -let ugt_bv l r = not (ulteq_bv l r) -let ugteq_bv l r = (eq_bv l r) || (ugt_bv l r) - -val slt_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool -let slt_bv l r = - match (most_significant l, most_significant r) with - | (B0, B0) -> ult_bv l r - | (B0, B1) -> false - | (B1, B0) -> true - | (B1, B1) -> - let l' = add_one_bit_ignore_overflow (bits_of l) in - let r' = add_one_bit_ignore_overflow (bits_of r) in - ugt_bv l' r' - | (BU, BU) -> ult_bv l r - | (BU, _) -> true - | (_, BU) -> false - end -let slteq_bv l r = (eq_bv l r) || (slt_bv l r) -let sgt_bv l r = not (slteq_bv l r) -let sgteq_bv l r = (eq_bv l r) || (sgt_bv l r) - -val ucmp_mword : forall 'a. Size 'a => (integer -> integer -> bool) -> mword 'a -> mword 'a -> bool -let inline ucmp_mword cmp l r = cmp (unsignedIntegerFromWord l) (unsignedIntegerFromWord r) - -val scmp_mword : forall 'a. Size 'a => (integer -> integer -> bool) -> mword 'a -> mword 'a -> bool -let inline scmp_mword cmp l r = cmp (signedIntegerFromWord l) (signedIntegerFromWord r) - val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a let get_slice_int_bv len n lo = let hi = lo + len - 1 in diff --git a/src/gen_lib/sail_operators_bitlists.lem b/src/gen_lib/sail_operators_bitlists.lem index fed293b4..19e9b519 100644 --- a/src/gen_lib/sail_operators_bitlists.lem +++ b/src/gen_lib/sail_operators_bitlists.lem @@ -308,21 +308,5 @@ let set_slice (out_len:ii) (slice_len:ii) out (n:ii) v = val eq_vec : list bitU -> list bitU -> bool val neq_vec : list bitU -> list bitU -> bool -val ult_vec : list bitU -> list bitU -> bool -val slt_vec : list bitU -> list bitU -> bool -val ugt_vec : list bitU -> list bitU -> bool -val sgt_vec : list bitU -> list bitU -> bool -val ulteq_vec : list bitU -> list bitU -> bool -val slteq_vec : list bitU -> list bitU -> bool -val ugteq_vec : list bitU -> list bitU -> bool -val sgteq_vec : list bitU -> list bitU -> bool let eq_vec = eq_bv let neq_vec = neq_bv -let ult_vec = ult_bv -let slt_vec = slt_bv -let ugt_vec = ugt_bv -let sgt_vec = sgt_bv -let ulteq_vec = ulteq_bv -let slteq_vec = slteq_bv -let ugteq_vec = ugteq_bv -let sgteq_vec = sgteq_bv diff --git a/src/gen_lib/sail_operators_mwords.lem b/src/gen_lib/sail_operators_mwords.lem index 077dfb02..22d5b246 100644 --- a/src/gen_lib/sail_operators_mwords.lem +++ b/src/gen_lib/sail_operators_mwords.lem @@ -329,21 +329,5 @@ let set_slice (out_len:ii) (slice_len:ii) out (n:ii) v = val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ult_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val slt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ugt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val sgt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool let inline eq_vec = eq_mword let inline neq_vec = neq_mword -let inline ult_vec = ucmp_mword (<) -let inline slt_vec = scmp_mword (<) -let inline ugt_vec = ucmp_mword (>) -let inline sgt_vec = scmp_mword (>) -let inline ulteq_vec = ucmp_mword (<=) -let inline slteq_vec = scmp_mword (<=) -let inline ugteq_vec = ucmp_mword (>=) -let inline sgteq_vec = scmp_mword (>=) diff --git a/src/pretty_print_lem.ml b/src/pretty_print_lem.ml index c181249d..58bbfc4b 100644 --- a/src/pretty_print_lem.ml +++ b/src/pretty_print_lem.ml @@ -111,10 +111,7 @@ let rec fix_id remove_tick name = match name with let doc_id_lem (Id_aux(i,_)) = match i with | Id i -> string (fix_id false i) - | DeIid x -> - (* add an extra space through empty to avoid a closing-comment - * token in case of x ending with star. *) - parens (separate space [colon; string x; empty]) + | DeIid x -> string (Util.zencode_string ("op " ^ x)) let doc_id_lem_type (Id_aux(i,_)) = match i with @@ -122,10 +119,7 @@ let doc_id_lem_type (Id_aux(i,_)) = | Id("nat") -> string "ii" | Id("option") -> string "maybe" | Id i -> string (fix_id false i) - | DeIid x -> - (* add an extra space through empty to avoid a closing-comment - * token in case of x ending with star. *) - parens (separate space [colon; string x; empty]) + | DeIid x -> string (Util.zencode_string ("op " ^ x)) let doc_id_lem_ctor (Id_aux(i,_)) = match i with @@ -135,10 +129,11 @@ let doc_id_lem_ctor (Id_aux(i,_)) = | Id("Some") -> string "Just" | Id("None") -> string "Nothing" | Id i -> string (fix_id false (String.capitalize i)) - | DeIid x -> - (* add an extra space through empty to avoid a closing-comment - * token in case of x ending with star. *) - separate space [colon; string (String.capitalize x); empty] + | DeIid x -> string (Util.zencode_string ("op " ^ x)) + +let deinfix = function + | Id_aux (Id v, l) -> Id_aux (DeIid v, l) + | Id_aux (DeIid v, l) -> Id_aux (DeIid v, l) let doc_var_lem kid = string (fix_id true (string_of_kid kid)) @@ -880,8 +875,7 @@ let doc_exp_lem, doc_let_lem = | E_assert (e1,e2) -> align (liftR (separate space [string "assert_exp"; expY e1; expY e2])) | E_app_infix (e1,id,e2) -> - raise (Reporting_basic.err_unreachable l - "E_app_infix should have been rewritten before pretty-printing") + expV aexp_needed (E_aux (E_app (deinfix id, [e1; e2]), (l, annot))) | E_var(lexp, eq_exp, in_exp) -> raise (report l "E_vars should have been removed before pretty-printing") | E_internal_plet (pat,e1,e2) -> -- cgit v1.2.3 From dac309174585e861fc685b621c2675d3999e740f Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 14:16:30 +0100 Subject: Add uart stub with registers based on ARM uart spec --- aarch64/uart.sail | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 aarch64/uart.sail diff --git a/aarch64/uart.sail b/aarch64/uart.sail new file mode 100644 index 00000000..442a175e --- /dev/null +++ b/aarch64/uart.sail @@ -0,0 +1,100 @@ +$include "prelude.sail" + +val "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m) + +register _UART_ADDR : bits(52) + +val initialize_uart : bits(52) -> unit effect {wreg} + +function initialize_uart(base_address) = { + _UART_ADDR = base_address; +} + +register UARTDR : bits(12) +register UARTRSR : bits(4) +register UARTFR : bits(9) +register UARTILPR : bits(8) +register UARTIBRD : bits(16) +register UARTFBRD : bits(6) +register UARTLCR_H : bits(8) +register UARTCR : bits(16) +register UARTIFLS : bits(6) +register UARTIMSC : bits(11) +register UARTRIS : bits(11) +register UARTMIS : bits(11) + +/* write only, so implement as function? */ +val UARTICR : bits(11) -> unit +function UARTICR(b) = () /* TODO */ + +register UARTDMACR : bits(3) + +val write_uart : forall 'n, 0 <= 'n <= 32. (bits(12), bits('n)) -> unit effect {escape, wreg} + +function write_uart(offset, data) = { + let data = zero_extend(data, 32); + match offset { + 0x000 => UARTDR = data[0, 12], + 0x004 => UARTRSR = data[0, 4], + /* 0x008 - 0x014 Reserved */ + /* 0x018 UARTFR read only */ + /* 0x01C Reserved */ + 0x020 => UARTILPR = data[0, 8], + 0x024 => UARTIBRD = data[0, 16], + 0x028 => UARTFBRD = data[0, 6], + 0x02C => UARTLCR_H = data[0, 8], + 0x030 => UARTCR = data[0, 16], + 0x034 => UARTIFLS = data[0, 6], + 0x038 => UARTIMSC = data[0, 11], + /* 0x03C UARTRIS read only */ + /* 0x040 UARTMIS read only */ + 0x044 => UARTICR() = data[0, 11], + 0x048 => UARTDMACR = data[0, 3], + + _ => throw(Error_Undefined()) + } +} + +val read_uart : bits(12) -> bits(32) effect {escape, rreg} + +function read_uart(offset) = { + let data : {'n, 0 <= 'n <= 32. bits('n)} = match offset { + 0x000 => UARTDR, + 0x004 => UARTRSR, + /* 0x008 - 0x014 Reserved */ + 0x018 => UARTFR, + /* 0x01C Reserved */ + 0x020 => UARTILPR, + 0x024 => UARTIBRD, + 0x028 => UARTFBRD, + 0x02C => UARTLCR_H, + 0x030 => UARTCR, + 0x034 => UARTIFLS, + 0x038 => UARTIMSC, + 0x03C => UARTRIS, + 0x040 => UARTMIS, + /* 0x044 UARTICR write only */ + 0x048 => UARTDMACR, + + _ => throw(Error_Undefined()) + }; + zero_extend(data, 32) +} + +val reset_uart : unit -> unit effect {wreg, undef} + +function reset_uart() = { + UARTDR = undefined; + UARTRSR = 0x0; + UARTFR = undefined : bits(1) @ 0b10010 @ undefined : bits(3); + UARTILPR = 0x00; + UARTIBRD = 0x0000; + UARTFBRD = 0b00_0000; + UARTLCR_H = 0x00; + UARTCR = 0x0300; + UARTIFLS = 0b01 @ 0x2; + UARTIMSC = 0b000_0000_0000; + UARTRIS = 0x00 @ undefined : bits(3); + UARTMIS = 0x00 @ undefined : bits(3); + UARTDMACR = 0b000 +} \ No newline at end of file -- cgit v1.2.3 From 7f86be11dbc8e764c172fb30d32a34ec6862587c Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 11 May 2018 15:45:05 +0100 Subject: prepare sail 0.2 release --- opam | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/opam b/opam index 04722afd..9eadca20 100644 --- a/opam +++ b/opam @@ -1,6 +1,6 @@ opam-version: "1.2" name: "sail" -version: "0.1" +version: "0.2" maintainer: "Sail Devs " authors: [ "Alasdair Armstrong" @@ -29,6 +29,6 @@ depends: [ "linenoise" "ott" {>= "0.28"} "lem" - "linksem" + "linksem" {>= "0.2"} ] available: [ocaml-version >= "4.02.3"] -- cgit v1.2.3 From 2a6e5eca7b28c5069e402a34ec36b7a6e18b274e Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 11 May 2018 16:06:55 +0100 Subject: add .git to dev-repo in opam file to satisfy opam-publish. --- opam | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opam b/opam index 9eadca20..3e3c93a9 100644 --- a/opam +++ b/opam @@ -17,7 +17,7 @@ authors: [ homepage: "http://www.cl.cam.ac.uk/~pes20/sail/" bug-reports: "https://github.com/rems-project/sail/issues" license: "BSD3" -dev-repo: "https://github.com/rems-project/sail" +dev-repo: "https://github.com/rems-project/sail.git" build: [make "INSTALL_DIR=%{prefix}%" "SHARE_DIR=%{sail:share}%" "isail"] install: [make "INSTALL_DIR=%{prefix}%" "SHARE_DIR=%{sail:share}%" "install"] remove: [make "INSTALL_DIR=%{prefix}%" "SHARE_DIR=%{sail:share}%" "uninstall"] -- cgit v1.2.3 From 3b2185dabdd5003c7553a7c86eab201cdebd5630 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Fri, 11 May 2018 15:25:27 +0100 Subject: Add snapshot of generated Isabelle theories Currently contains Lem and Sail libraries, and RISC-V and CHERI-MIPS specs. --- lib/isabelle/manual/Manual.thy | 2 +- lib/isabelle/manual/document.pdf | Bin 216829 -> 0 bytes snapshots/isabelle/Manual.pdf | Bin 0 -> 208530 bytes snapshots/isabelle/Manual.thy | 464 + snapshots/isabelle/README.md | 25 + snapshots/isabelle/cheri/Cheri.thy | 10570 +++++++++++++++++++ snapshots/isabelle/cheri/Cheri_lemmas.thy | 1205 +++ snapshots/isabelle/cheri/Cheri_types.thy | 2432 +++++ snapshots/isabelle/cheri/Mips_extras.thy | 251 + snapshots/isabelle/lib/lem/LICENSE | 524 + snapshots/isabelle/lib/lem/Lem.thy | 108 + snapshots/isabelle/lib/lem/LemExtraDefs.thy | 1259 +++ snapshots/isabelle/lib/lem/Lem_assert_extra.thy | 45 + snapshots/isabelle/lib/lem/Lem_basic_classes.thy | 500 + snapshots/isabelle/lib/lem/Lem_bool.thy | 75 + snapshots/isabelle/lib/lem/Lem_either.thy | 85 + snapshots/isabelle/lib/lem/Lem_function.thy | 72 + snapshots/isabelle/lib/lem/Lem_function_extra.thy | 29 + snapshots/isabelle/lib/lem/Lem_list.thy | 776 ++ snapshots/isabelle/lib/lem/Lem_list_extra.thy | 117 + snapshots/isabelle/lib/lem/Lem_machine_word.thy | 450 + snapshots/isabelle/lib/lem/Lem_map.thy | 159 + snapshots/isabelle/lib/lem/Lem_map_extra.thy | 82 + snapshots/isabelle/lib/lem/Lem_maybe.thy | 113 + snapshots/isabelle/lib/lem/Lem_maybe_extra.thy | 24 + snapshots/isabelle/lib/lem/Lem_num.thy | 1302 +++ snapshots/isabelle/lib/lem/Lem_num_extra.thy | 34 + snapshots/isabelle/lib/lem/Lem_pervasives.thy | 31 + .../isabelle/lib/lem/Lem_pervasives_extra.thy | 26 + snapshots/isabelle/lib/lem/Lem_relation.thy | 449 + snapshots/isabelle/lib/lem/Lem_set.thy | 325 + snapshots/isabelle/lib/lem/Lem_set_extra.thy | 121 + snapshots/isabelle/lib/lem/Lem_set_helpers.thy | 50 + snapshots/isabelle/lib/lem/Lem_show.thy | 87 + snapshots/isabelle/lib/lem/Lem_show_extra.thy | 74 + snapshots/isabelle/lib/lem/Lem_sorting.thy | 110 + snapshots/isabelle/lib/lem/Lem_string.thy | 75 + snapshots/isabelle/lib/lem/Lem_string_extra.thy | 137 + snapshots/isabelle/lib/lem/Lem_tuple.thy | 51 + snapshots/isabelle/lib/lem/Lem_word.thy | 1024 ++ snapshots/isabelle/lib/lem/ROOT | 7 + snapshots/isabelle/lib/sail/Hoare.thy | 320 + snapshots/isabelle/lib/sail/Prompt.thy | 150 + snapshots/isabelle/lib/sail/Prompt_monad.thy | 267 + .../isabelle/lib/sail/Prompt_monad_lemmas.thy | 170 + snapshots/isabelle/lib/sail/ROOT | 11 + snapshots/isabelle/lib/sail/Sail_instr_kinds.thy | 494 + snapshots/isabelle/lib/sail/Sail_operators.thy | 326 + .../isabelle/lib/sail/Sail_operators_bitlists.thy | 773 ++ .../isabelle/lib/sail/Sail_operators_mwords.thy | 638 ++ .../lib/sail/Sail_operators_mwords_lemmas.thy | 112 + snapshots/isabelle/lib/sail/Sail_values.thy | 1215 +++ snapshots/isabelle/lib/sail/Sail_values_lemmas.thy | 206 + snapshots/isabelle/lib/sail/State.thy | 102 + snapshots/isabelle/lib/sail/State_lemmas.thy | 202 + snapshots/isabelle/lib/sail/State_monad.thy | 375 + snapshots/isabelle/lib/sail/State_monad_lemmas.thy | 232 + snapshots/isabelle/riscv/Riscv.thy | 7876 ++++++++++++++ snapshots/isabelle/riscv/Riscv_duopod.thy | 461 + snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy | 48 + snapshots/isabelle/riscv/Riscv_duopod_types.thy | 170 + snapshots/isabelle/riscv/Riscv_extras.thy | 126 + snapshots/isabelle/riscv/Riscv_lemmas.thy | 350 + snapshots/isabelle/riscv/Riscv_types.thy | 1052 ++ 64 files changed, 38945 insertions(+), 1 deletion(-) delete mode 100644 lib/isabelle/manual/document.pdf create mode 100644 snapshots/isabelle/Manual.pdf create mode 100644 snapshots/isabelle/Manual.thy create mode 100644 snapshots/isabelle/README.md create mode 100644 snapshots/isabelle/cheri/Cheri.thy create mode 100644 snapshots/isabelle/cheri/Cheri_lemmas.thy create mode 100644 snapshots/isabelle/cheri/Cheri_types.thy create mode 100644 snapshots/isabelle/cheri/Mips_extras.thy create mode 100644 snapshots/isabelle/lib/lem/LICENSE create mode 100644 snapshots/isabelle/lib/lem/Lem.thy create mode 100644 snapshots/isabelle/lib/lem/LemExtraDefs.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_assert_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_basic_classes.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_bool.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_either.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_function.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_function_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_list.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_list_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_machine_word.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_map.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_map_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_maybe.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_maybe_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_num.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_num_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_pervasives.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_relation.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_set.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_set_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_set_helpers.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_show.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_show_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_sorting.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_string.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_string_extra.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_tuple.thy create mode 100644 snapshots/isabelle/lib/lem/Lem_word.thy create mode 100644 snapshots/isabelle/lib/lem/ROOT create mode 100644 snapshots/isabelle/lib/sail/Hoare.thy create mode 100644 snapshots/isabelle/lib/sail/Prompt.thy create mode 100644 snapshots/isabelle/lib/sail/Prompt_monad.thy create mode 100644 snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy create mode 100644 snapshots/isabelle/lib/sail/ROOT create mode 100644 snapshots/isabelle/lib/sail/Sail_instr_kinds.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_operators.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_operators_mwords.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_values.thy create mode 100644 snapshots/isabelle/lib/sail/Sail_values_lemmas.thy create mode 100644 snapshots/isabelle/lib/sail/State.thy create mode 100644 snapshots/isabelle/lib/sail/State_lemmas.thy create mode 100644 snapshots/isabelle/lib/sail/State_monad.thy create mode 100644 snapshots/isabelle/lib/sail/State_monad_lemmas.thy create mode 100644 snapshots/isabelle/riscv/Riscv.thy create mode 100644 snapshots/isabelle/riscv/Riscv_duopod.thy create mode 100644 snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy create mode 100644 snapshots/isabelle/riscv/Riscv_duopod_types.thy create mode 100644 snapshots/isabelle/riscv/Riscv_extras.thy create mode 100644 snapshots/isabelle/riscv/Riscv_lemmas.thy create mode 100644 snapshots/isabelle/riscv/Riscv_types.thy diff --git a/lib/isabelle/manual/Manual.thy b/lib/isabelle/manual/Manual.thy index 53175ec9..6cdfbfa1 100644 --- a/lib/isabelle/manual/Manual.thy +++ b/lib/isabelle/manual/Manual.thy @@ -24,7 +24,7 @@ follow the instructions. In order to generate theorem prover definitions, Sail specifications are first translated to Lem, which then generates definitions for Isabelle/HOL. Lem can also generate HOL4 definitions, though we have -not yet tested that for our ISA specifications. To produce Coq +not yet tested that extensively for our ISA specifications. To produce Coq definitions, we envisage implementing a direct Sail-to-Coq backend, to preserve the Sail dependent types (it's possible that the Lem-to-Coq backend, which in general does not produce good Coq definitions, would diff --git a/lib/isabelle/manual/document.pdf b/lib/isabelle/manual/document.pdf deleted file mode 100644 index 200f8e22..00000000 Binary files a/lib/isabelle/manual/document.pdf and /dev/null differ diff --git a/snapshots/isabelle/Manual.pdf b/snapshots/isabelle/Manual.pdf new file mode 100644 index 00000000..62066f8f Binary files /dev/null and b/snapshots/isabelle/Manual.pdf differ diff --git a/snapshots/isabelle/Manual.thy b/snapshots/isabelle/Manual.thy new file mode 100644 index 00000000..c9eaa18a --- /dev/null +++ b/snapshots/isabelle/Manual.thy @@ -0,0 +1,464 @@ +(*<*) +theory Manual + imports + Sail.State_lemmas + Sail.Sail_operators_mwords_lemmas + Sail.Hoare + "riscv/Riscv_duopod_lemmas" +begin + +declare [[show_question_marks = false]] +(*>*) + +section \Getting Started\ + +text \This manual describes how to use Sail specifications for reasoning in Isabelle/HOL. +For instructions on how to set up the Sail tool and its dependencies, see @{path INSTALL.md}. +As an additional setup step for Isabelle generation, it is useful to build an Isabelle heap image +of the Sail library. +This will allow you to start Isabelle with the Sail library pre-loaded using the +@{verbatim "-l Sail"} option. +For this purpose, run @{verbatim "make heap-img"} in the @{path "lib/isabelle"} subdirectory of Sail and +follow the instructions. + +In order to generate theorem prover definitions, Sail specifications +are first translated to Lem, which then generates definitions for +Isabelle/HOL. Lem can also generate HOL4 definitions, though we have +not yet tested that extensively for our ISA specifications. To produce Coq +definitions, we envisage implementing a direct Sail-to-Coq backend, to +preserve the Sail dependent types (it's possible that the Lem-to-Coq +backend, which in general does not produce good Coq definitions, would +actually produce usable Coq definitions for a monomorphised ISA +specification, but we have not tested that). + +The translation to Lem is activated by passing the @{verbatim "-lem"} command line flag to Sail. +For example, the following call in the @{path riscv} directory will generate Lem definitions +for the RISC-V "duopod" (a fragment of the RISC-V specification with only two instructions, +used for illustration purposes): +@{verbatim [display] +"sail -lem -o riscv_duopod -lem_mwords -lem_lib Riscv_extras + prelude.sail riscv_duopod.sail"} +This uses the following options: + \<^item> @{verbatim "-lem"} activates the generation of Lem definitions. + \<^item> @{verbatim "-o riscv_duopod"} specifies the prefix for the output filenames. This invocation + of Sail will generate the files + \<^item> @{path riscv_duopod_types.lem}, containing the definitions of the types used in the + specification, + \<^item> @{path riscv_duopod.lem}, containing the main definitions, e.g.~of the instructions, and + \<^item> @{path Riscv_duopod_lemmas.thy} containing generated helper lemmas, (currently) mainly + simplification rules for lifting register reads and writes from the free monad to the + state monad supported by Sail (cf.~Section~\ref{sec:monads}). + \<^item> @{verbatim "-lem_mwords"} specifies that the generated definitions should use the machine + word representation of bitvectors (cf.~Section~\ref{sec:mwords}). This works out-of-the-box + for the RISC-V specification, but might require monomorphisation (e.g.~using the + @{verbatim "-auto_mono"} command line flag) for specifications that have functions that + are polymorphic in bitvector lengths. + \<^item> @{verbatim "-lem_lib Riscv_extras"} specifies an additional Lem library to be imported. + It contains Lem implementations for some wrappers and primitive functions that are declared + as external functions in the Sail source code, such as wrappers for reading and writing memory. + +Isabelle definitions can then be generated by passing the @{verbatim "-isa"} flag to Lem. +In order for Lem to find the Sail library, the subdirectories @{path "src/gen_lib"} and +@{path "src/lem_interp"} of Sail will have to be added to Lem's include path using the +@{verbatim "-lib"} option, e.g. + +@{verbatim [display] +"lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib + riscv_extras.lem riscv_duopod_types.lem riscv_duopod.lem"} + +For further examples, see the @{path Makefile}s of the other specifications included in the Sail +distribution.\ + +section \An Example of a Sail Specification in Isabelle/HOL\ + +text \A Sail specification typically comprises a @{term decode} function specifying a mapping from raw +instruction opcodes to a more abstract representation, an @{term execute} function specifying the +behaviour of instructions, further auxiliary functions and datatypes, and register declarations. + +For example, in the RISC-V duopod, there are two instructions: a load instruction and an +add instruction with one register and one immediate operand. Their abstract syntax is represented +using the following datatype: +@{datatype [display] ast} +Both instructions take an immediate 12-bit argument (used as an offset in the case of the load +instruction), and two 5-bit arguments encoding the source and the destination register, +respectively. The @{term ITYPE} instruction takes another argument encoding the type of operation +(where only addition is implemented in the ``duopod'' fragment of RISC-V). + +The function @{term [source] "decode :: 32 word \ ast option"} is implemented in the Sail source +code using bitvector pattern matching on the opcode. The Lem backend translates this to an +if-then-else-cascade that compares the given opcode against one pattern after another: +@{thm [display] decode_def[of opcode for opcode]} +This decode function is pure, although decoding might be effectful in other specifications (e.g., +because the decoding depends on the register state). Sail uses its effect system to determine +whether a function has side-effects and needs to be be monadic (cf.~Section~\ref{sec:monads} for +more details about the monads). + +The @{term execute} function, for example, is monadic. +Its clause for the load instruction of the RISC-V duopod is defined as follows, where +@{text \} is infix syntax for the monadic bind: +@{thm [display] execute_LOAD_def[of imm rs rd for imm rs rd]} +The instruction first reads the base address from the source register @{term rs}, then adds the +offset given in the immediate argument @{term imm}, calls the @{term MEMr} auxiliary function to +read eight bytes starting at the calculated address, and writes the result into the destination +register @{term rd}. + +Note that the @{term execute} function is special-cased in that Sail attempts to split it up into +auxiliary functions (one per AST node) in order to avoid letting it become too large. The main +@{term execute} function dispatches its inputs to the auxiliary functions: +@{thm [display] execute.simps[of imm rs rd for imm rs rd]} + +Apart from function and type definitions, Sail source code contains register declarations. +A @{type regstate} record gets generated from these for use in the state monad, e.g. +@{theory_text [display] +\record regstate = + Xs ::" ( 64 Word.word) list " + nextPC ::" 64 Word.word " + PC ::" 64 Word.word "\ +} +In the RISC-V specification, the general-purpose register file is declared as one register +@{term Xs} containing the 32 registers of 64 bits each, which gets mapped to a list of +64-bit words (see Section~\ref{sec:types} for more information on vectors and lists in general). +In addition to the register state record, a reference constant is generated for each register, +e.g.~@{term PC_ref}, which is used when the register is passed to Sail functions as an argument. +These constants are records that contain the register name as a string, as well as getter and +setter functions. We discuss them in more detail together with the monads in +Section~\ref{sec:monads}.\ + +section \Sail Library\ + +text \The overall theory graph of the Sail library is depicted in Figure~\ref{fig:session-graph}. +The library includes mappings of common operations on the basic types (Section~\ref{sec:types}), in +particular bitvector operations for both the bitlist representation and the machine word +representation of bitvectors (Section~\ref{sec:bitvectors}). +It also includes theories defining the two monads currently supported: a state monad with exceptions +and nondeterminism (cf.~Section~\ref{sec:state-monad}), and a free monad of an effects datatype +(Section~\ref{sec:free-monad}).\ + +text_raw \ +\begin{figure}[p] + \begin{center} + \includegraphics[width=\textwidth,height=\textheight,keepaspectratio]{Sail_session_graph} + \end{center} + \caption{Session graph of the Sail library \label{fig:session-graph}} +\end{figure} +\ + +text \The main definitions have been written in Lem and can therefore also be exported to theorem +provers other than Isabelle. The Isabelle-specific parts of the library are contained in the +theories named with the suffix @{path "_lemmas"}. They contain mostly simplification rules, but +also congruence rules for the @{term [source] bind} operations of the monads, for example, which +are needed by the function package when processing recursive monadic functions.\ + +subsection \Basic types \label{sec:types}\ + +text \The basic Sail types @{verbatim bool}, @{verbatim string}, @{verbatim list}, @{verbatim unit} +and @{verbatim real} are directly mapped to the Isabelle types of the same name. + +The numeric types @{verbatim int}, @{verbatim nat}, @{verbatim atom}, and @{verbatim range} are +treated in Sail as integers with constraints. The latter are not currently translated to Lem +or Isabelle, so these types are all mapped to the Isabelle type @{type int}. + +Bits are represented by a type that can also represent undefined bits: +@{datatype [display] bitU} +This provides one way to handle undefined cases of partial functions, such as division by zero. +In general, the guiding principle in the Sail library is to make partiality of library functions +explicit by returning an option type, and to provide wrappers implementing common ways to handle +undefined cases. For example, the function @{term quot_vec} for bitvector division comes in the +following variants: + \<^item> @{term quot_vec_maybe} returns an option type, with + @{lemma "quot_vec_maybe w 0 = None" by (auto simp: quot_vec_maybe_def quot_bv_def arith_op_bv_no0_def)}. + \<^item> @{term quot_vec_fail} is monadic and either returns the result or raises an exception. + \<^item> @{term quot_vec_oracle} is monadic and uses the @{term Undefined} effect in the exception case + to fill the result with bits drawn from a bitstream oracle. + \<^item> @{term quot_vec} is pure and returns an arbitrary (but fixed) value in the exception case, + currently defined as follows: For the bitlist representation of bitvectors, + @{term "quot_vec w 0"} returns a list filled with @{term BU}, while for the machine word + representation, the function gets mapped to Isabelle's division operation on machine words, + which defines @{lemma "(w :: ('a::len) word) div 0 = 0" by (simp add: word_div_def)}. + +Which variant is to be used for a given specification can be chosen by using the corresponding +binding for the Lem backend in the Sail source (typically in @{verbatim prelude.sail}). + +Vectors in Sail are mapped to lists in Isabelle, except for bitvectors, which are special-cased. +Both increasing and decreasing indexing order are supported by having two versions for each +operation that involves indexing, such as @{term update_list_inc} and @{term update_list_dec}, +or @{term subrange_list_inc} and @{term subrange_list_dec}. These operations are defined in the +theory @{theory Sail_values}, while @{theory Sail_values_lemmas} provides simplification rules +such as + +@{lemma "access_list_inc xs i = xs ! nat i" by auto} \\ +@{thm access_list_dec_nth} + +Note that, while Sail allows functions that are polymorphic in the indexing order, this kind of +polymorphism is not currently supported by the translation to Lem. It is not needed by the +currently existing specifications, however, since the indexing order is always fixed.\ + +subsection \Bitvectors \label{sec:bitvectors} \label{sec:mwords}\ + +(*subsubsection \Bit Lists \label{sec:bitlists}\ + +subsubsection \Machine Words \label{sec:mwords}\*) + +text \The Lem backend of Sail supports two representations of bitvectors: bit lists and machine +words. The former is less convenient for proofs, because it typically leads to many proof +obligations about bitvector lengths. These are avoided with machine words, where length +information is contained in the types, e.g.~@{typ "64 word"}. However, Isabelle/HOL does not support +dependent types, which makes bitvector length polymorphism problematic. Sail includes an analysis +and rewriting pass for monomorphising bitvector lengths, splitting up length-polymorphic functions +into multiple clauses with concrete bitvector lengths. This is not enabled by default, however, +so Sail generates Lem definitions using bit lists unless the @{verbatim "-lem_mwords"} command +line flag is used. + +The theory @{theory Sail_values} defines a (Lem) typeclass @{verbatim Bitvector}, which provides +an interface to some basic bitvector operations and has instantiations for both bit lists and machine +words. It is mainly intended for internal use in the Sail library,\<^footnote>\Lem typeclasses are not very +convenient to use in Isabelle, as they get translated to dictionaries that have to be passed to functions +using the typeclass.\ to implement library functions supporting either one of the bitvector +representations. For use in Sail specifications, wrappers are defined in the theories +@{path Sail_operators_bitlists} and @{path Sail_operators_mwords}, respectively. An import of the +right theory is automatically added to the generated files, depending on which bitvector +representation is used. Hence, bitvector operations can be referred to in the Sail source code +using uniform names, e.g.~@{term add_vec}, @{term update_vec_dec}, or @{term subrange_vec_inc}. +The theory @{theory Sail_operators_mwords_lemmas} sets up simplification rules that relate these +operations to the native operations in Isabelle, e.g. + +@{lemma "add_vec l r = l + r" by simp} \\ +@{lemma "and_vec l r = l AND r" by auto} \\ +@{thm access_vec_dec_test_bit}\ + +subsection \Monads \label{sec:monads}\ + +text \The definitions generated by Sail are designed to support reasoning in both concurrent and +sequential settings. For the former, we use a free monad of an effect datatype that provides +fine-grained information about the register and memory effects of monadic expressions, suitable +for integration with relaxed memory models. For the sequential case, we use a state monad (with +exceptions and nondeterminism). + +The generated definitions use the free monad, and the sequential case is supported via a lifting +to the state monad defined in the theory @{theory State}. Simplification rules are set up in the +theory @{theory State_lemmas}, allowing seamless reasoning about the generated definitions in terms +of the state monad.\ + +subsubsection \State Monad \label{sec:state-monad}\ + +text \The state monad supports nondeterminism and exceptions and is defined in a standard way: +a monadic expression maps a state to a set of results together with a corresponding successor +state. The type @{typ "('regs, 'a, 'e) monadS"} is a synonym for +@{typeof [display] "returnS a :: ('regs, 'a, 'e) monadS"} +Here, @{typ "'a"} and @{typ "'e"} are parameters for the return value type and the exception type, +respectively. The latter is instantiated in generated definitions with either the type +@{term exception}, if the Sail source code defines that type, or with @{typ unit} otherwise. +A result of a monadic expression can be either a value, a non-recoverable failure, or an +exception thrown (that may be caught using @{term try_catch}): +@{datatype [display] ex} +@{datatype [display, names_short] result} + +The @{type sequential_state} record has the following fields: + \<^item> @{term regstate} contains the register state. + \<^item> @{term memstate} stores the memory, represented as a map from (@{typ int}) addresses to + (@{typ "bitU list"}) bytes. + \<^item> Similarly, @{term tagstate} field stores a single bit per address, used by some specifications + to model tagged memory. + \<^item> The @{term write_ea} field of type @{typeof "write_ea s"} stores the type, address, and size + of the last announced memory write, if any. + \<^item> The @{term last_exclusive_operation_was_load} flag is used to determine whether exclusive + operations can succeed. + \<^item> The function stored in the @{term next_bool} field together with the seed in the @{term seed} + field are used as a random bit generator for undefined values. The @{term next_bool} + function takes the current seed as an argument and returns a @{type bool} and the next seed. + +The library defines several combinators and wrappers in addition to the standard monadic bind and +return (called @{term bindS} and @{term returnS} here, where the suffix @{term S} differentiates them +from the @{term [source] bind} and @{term return} functions of the free monad). The functions +@{term readS} and @{term updateS} provide direct access to the state, but there are more specific +wrappers for common tasks such as + \<^item> @{term read_regS} and @{term write_regS} for accessing registers (taking a register reference + as an argument), + \<^item> @{term read_memS} for reading memory, + \<^item> @{term write_mem_eaS} and @{term write_mem_valS} to announce and perform a memory write, + respectively, and + \<^item> @{term undefined_boolS} gets a value from the random bit generator. + +Nondeterminism can be introduced using @{term chooseS} to pick a value from a set, failure by +@{term failS} or @{term exitS} (with or without failure message, respectively), assertions by +@{term assert_expS} (causing a failure if the assertion fails), and exceptions by @{term throwS}. +The latter can be caught using @{term try_catchS}, which takes a monadic expression and an +exception handler as arguments. + +The exception mechanism is also used to implement early returns by throwing and catching return +values: A function body with one or more early returns of type @{typ 'a} (and exception type +@{typ 'e}) is lifted to a monadic expression with exception type @{typ "('a + 'e)"} using +@{term liftSR}, such that an early return of the value @{term a} throws @{term "Inl a"}, and a +regular exception @{term e} is thrown as @{term "Inr e"}. The function body is then wrapped in +@{term catch_early_returnS} to lower it back to the default monad and exception type. These +liftings and lowerings are automatically inserted by Sail for functions with early returns.\<^footnote>\To be +precise, Sail's Lem backend uses the corresponding constructs for the free monad, but the state +monad version presented here can be obtained using the monad transformation presented in the next +section.\ + +Finally, there are the loop combinators @{term foreachS}, @{term whileS}, and @{term untilS}. +Loop bodies are required to be of type @{typ unit} in the Sail source code, but during the +translation to Lem they get rewritten into functions that take a tuple with the current values of +local mutable variables that they might update as an (additional) argument, and return the updated +values. Hence, the type of @{term foreachS}, for example, is +@{term [display, source] "foreachS :: 'a list \ 'vars \ ('a \ 'vars \ ('regs, 'vars, 'e) monadS) \ ('regs, 'vars, 'e) monadS"} +Note that there is no general termination proof for @{term whileS} and @{term untilS}, so the +termination predicates @{term "whileS_dom"} or @{term "untilS_dom"} have to be proved for concrete +instances.\ + +subsubsection \Free Monad \label{sec:free-monad}\ + +text \In addition to the state monad, the theory @{theory Prompt_monad} defines a free monad of an +effect datatype. A monadic expression either returns a pure value @{term a}, denoted +@{term "Done a"}, or it has an effect. The latter can be a failure or an exception, or an effect +together with a continuation. For example, @{term \Read_reg ''PC'' k\} represents a request to +read the register @{term PC} and continue as @{term k}, which is a function that takes the +register value as a parameter and returns another monadic expression. Another example is +@{term "Undefined k"}, which requests a Boolean value from the execution context, e.g.~to resolve +an undefined bit to a concrete value. Again, the value is expected to be passed as an argument to +the continuation @{term k}. The complete set of supported monadic outcomes is captured in the +following datatype: + +@{datatype [display] monad} + +The effects are designed to be usable as an interface to relaxed memory models. For example, +@{term Footprint} tells the memory model that the register footprint of the instruction should be +re-calculated. The Boolean parameters of the continuations of the @{term Write_memv}, +@{term Write_tag}, and @{term Excl_res} effects allow the memory model to inform the instruction +whether a memory write has succeeded (or may succeed). + +The same set of combinators and wrappers as for the state monad is defined for this monad. The +names are the same, but without the suffix @{term S}, e.g.~@{term read_reg}, @{term write_mem_val}, +@{term undefined_bool}, @{term throw}, @{term try_catch}, etc.~(with the exception of the loop +combinators, which are called @{term foreachM}, @{term whileM}, and @{term untilM}; the names +@{term foreach}, @{term [names_short] while}, and @{term until} are reserved for the pure versions +of the loop combinators). + +The monad is parametric in the register type used for the register effects. One technical +complication is that, in general, this requires a single type that can subsume all the types of +registers occurring in a specification. Otherwise, it would not be possible to find a single +instantiation of the @{type monad} type to assign to a function that involves reading or writing +multiple registers with different types, for example. To solve this problem, the translation from +Sail to Lem generates a union type @{typ register_value} with constructors for all register base +types of the given specification and the built-in type constructors @{term vector}, @{type list}, +and @{type option}. In the case of the RISC-V duopod, this is + +@{datatype [display] register_value} + +For example, a value of the (complete) @{term Xs} register file (whose Sail type is +@{verbatim "vector(32, dec, vector(64, dec, bit))"}) is represented as @{term "Regval_vector (32, False, xs)"}, +where @{term xs} is a list of words wrapped in @{term Regval_vector_64_dec_bit}. + +Sail also generates conversion functions to and from @{type register_value}, e.g. + +@{term [source, show_types] "regval_of_vector_64_dec_bit :: 64 word \ register_value"} \\ +@{term [source, show_types] "vector_64_dec_bit_of_regval :: register_value \ 64 word option"} + +where the latter is partial. +The conversion functions for @{term Regval_vector}, @{term Regval_list}, and @{term Regval_option} +are higher-order functions that take the corresponding conversion function for the encapsulated +type as a parameter, e.g. + +@{term [source, show_types] "regval_of_vector :: ('a \ register_value) \ int \ bool \ 'a list \ register_value"} \\ +@{term [source, show_types] "vector_of_regval :: (register_value \ 'a option) \ register_value \ 'a list option"} + +The latter only returns a value if \emph{all} elements of the vector can be successfully converted +from @{typ register_value} to @{typ "'a"}. + +For each register, the matching pair of conversion functions is recorded in its +@{type register_ref} record, e.g. + +@{thm [display] PC_ref_def} +@{thm [display] Xs_ref_def} + +The @{term read_reg} wrapper, for example, takes such a reference as a parameter, generates a +@{term Read_reg} effect with the register name, and casts the register value received as input via +@{term of_regval}. If the latter fails because the environment passed a value of the wrong type +to the continuation, then @{term read_reg} halts with a @{term Failure}. The state monad wrappers +@{term read_regS} and @{term write_regS} also take such a register reference as an argument, but +use the getters and setters in the @{term read_from} and @{term write_to} fields to access the +register state record: +@{thm [display] read_regS_def write_regS_def} + +Sail aims to generate Isabelle definitions that can be used with either the state or the free monad. +To achieve this, the definitions are generated using the free monad, and a lifting to the state +monad is provided together with simplification rules. These include generic simplification rules +(proved in the theory @{theory State_lemmas}) such as +@{thm [display] + liftState_return[where r = "(get_regval, set_regval)"] + liftState_bind[where r = "(get_regval, set_regval)"] + liftState_try_catch[where r = "(get_regval, set_regval)"]} +They also include more specific lemmas about register reads and writes: The lifting of these +involves a back-and-forth conversion between the type of the register and the @{type register_value} +type at the interface between the monads, which can fail in general. As long as the generated +register references are used, however, it is guaranteed to succeed, and this is made explicit in +lemmas such as +@{thm [display] liftS_read_reg_PC liftS_write_reg_PC} +which are generated (together with their proofs) for each register and placed in a theory with +the suffix @{path "_lemmas"}, e.g.~@{path Riscv_duopod_lemmas}. +The aim of these lemmas is to allow a smooth transition from the free to the state monad via +simplification, as in the following example.\ + +section \Example Proof \label{sec:ex-proof}\ + +text \As a toy example for illustration, we prove that the add instruction in the RISC-V duopod +actually performs an addition. We consider the sequential case and use the state monad. The +theory @{theory Hoare} defines (a shallow embedding of) a simple Hoare logic, where +@{term "PrePost P f Q"} denotes a triple of a precondition @{term P}, monadic expression @{term f}, +and postcondition @{term Q}. Its validity is defined by +@{thm [display] PrePost_def} +There is also a quadruple variant, with separate postconditions for the regular and the exception +case, defined as +@{thm [display, names_short] PrePostE_def} +The theory includes standard proof rules for both of these variants, in particular rules +giving weakest preconditions of the predefined primitives of the monad, collected under the names +@{attribute PrePost_intro} and @{attribute PrePostE_intro}, respectively. + +The instruction we are considering is defined as +@{thm [display] execute_ITYPE.simps[of _ rs for rs]} + +We first declare two simplification rules and an abbreviation, for stating the lemma more +conveniently: @{term "getXs r s"} reads general-purpose register @{term r} in state @{term s}, +where register 0 is special-cased and hard-wired to the constant 0, as defined in the RISC-V +specification.\ + +abbreviation "getXs r s \ if r = 0 then 0 else access_list_dec (Xs (regstate s)) (uint r)" + +lemma EXTS_scast[simp]: "EXTS len w = scast w" + by (simp add: EXTS_def sign_extend_def) + +declare regbits_to_regno_def[simp] + +text \We prove that a postcondition of the instruction is that the destination register holds the +sum of the initial value of the source register and the immediate operand (unless the destination +register is the constant zero register). Moreover, we require the instruction to succeed, so +the postcondition for the exception case is @{term False}. In the precondition, we remember +the initial value @{term v} of the source register for use in the postcondition (since it might get +overwritten if @{term "rs = rd"}). We also explicitly assume that there are 32 general-purpose +registers; due to the use of a list for the @{term Xs} register file, this information is currently +not preserved by the translation.\ + +lemma + fixes rs rd :: regbits and v :: "64 word" and imm :: "12 word" + + defines "pre s \ (getXs rs s = v \ length (Xs (regstate s)) = 32)" + defines "instr \ execute (ITYPE (imm, rs, rd, RISCV_ADDI))" + defines "post a s \ (rd = 0 \ getXs rd s = v + (scast imm))" + + shows "PrePostE pre (liftS instr) post (\_ _. False)" + + unfolding pre_def instr_def post_def + by (simp add: rX_def wX_def cong: bindS_cong if_cong split del: if_split) + (rule PrePostE_strengthen_pre, (rule PrePostE_intro)+, auto simp: uint_0_iff) + +text \The proof begins with a simplification step, which not only unfolds the definitions of the +auxiliary functions @{term rX} and @{term wX}, but also performs the lifting from the free monad +to the state monad. We apply the rule @{thm [source] PrePostE_strengthen_pre} (in a +backward manner) to allow a weaker precondition, then use the rules in @{attribute PrePostE_intro} +to derive a weakest precondition, and then use @{method auto} to show that it is implied by +the given precondition. For more serious proofs, one will want to set up specialised proof +tactics. This example uses only basic proof methods, to make the reasoning steps more explicit.\ + +(*<*) +end +(*>*) diff --git a/snapshots/isabelle/README.md b/snapshots/isabelle/README.md new file mode 100644 index 00000000..b1d9db23 --- /dev/null +++ b/snapshots/isabelle/README.md @@ -0,0 +1,25 @@ +# Isabelle Snapshots of Sail Specifications + +This directory contains snapshots of the Isabelle theories generated by Sail +for the CHERI-MIPS, RISC-V, and ARM v8.3 specifications, together with +snapshots of the Sail and Lem libraries. These snapshots are provided for +convenience, and are not guaranteed to be up-to-date. + +In order to open a theory of one of the specifications in Isabelle, use the `-l +Sail` command-line flag to load the session containing the Sail library. +Snapshots of the Sail and Lem libraries are in the `lib/sail` and `lib/lem` +directories, respectively. You can tell Isabelle where to find them using the +`-d` flag, as in + +``` +isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy +``` + +This will open the RISC-V specification. + +The file `Manual.thy` (and its PDF rendering in `Manual.pdf`) contains an +introduction on how to use the Sail specifications in Isabelle. + +The Lem library files in `lib/lem` have been generated from the +[Lem](https://github.com/rems-project/lem) sources. The Lem license can be +found in `lib/lem/LICENSE`. diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy new file mode 100644 index 00000000..eed49a23 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri.thy @@ -0,0 +1,10570 @@ +chapter \Generated by Lem from cheri.lem.\ + +theory "Cheri" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Cheri_types" + "Mips_extras" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Cheri_types*) +(*open import Mips_extras*) + +definition cap_size :: " int " where + " cap_size = ( (( 32 :: int)::ii))" + + +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +definition undefined_option :: " 'a \((register_value),('a option),(exception))monad " where + " undefined_option typ_a = ( undefined_unit () \ internal_pick [None,Some typ_a])" + + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +definition neq_bool :: " bool \ bool \ bool " where + " neq_bool x y = ( \ (((x = y))))" + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MIPS_write :: "(64)Word.word \ int \('p8_times_n_::len)Word.word \((register_value),(unit),(exception))monad " where + " MIPS_write addr width data = ( + write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data )" + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MIPS_read :: "(64)Word.word \ int \((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MIPS_read addr width = ( + (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'p8_times_n_::len)Word.word) M))" + + + + +(*val undefined_exception : unit -> M exception*) + +definition undefined_exception :: " unit \((register_value),(exception),(exception))monad " where + " undefined_exception _ = ( + (undefined_unit () \ + undefined_string () ) \ (\ (w__0 :: string) . + ((undefined_unit () \ + undefined_unit () ) \ + undefined_unit () ) \ + internal_pick + [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))" + + +(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition sign_extend1 :: " int \('n::len)Word.word \('m::len)Word.word " where + " sign_extend1 (m__tv :: int) v = ( (sign_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +definition zero_extend1 :: " int \('n::len)Word.word \('m::len)Word.word " where + " zero_extend1 (m__tv :: int) v = ( (zero_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition zeros0 :: " int \ unit \('n::len)Word.word " where + " zeros0 (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition ones :: " int \ unit \('n::len)Word.word " where + " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \ ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \ ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \ bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val bits_to_bool : mword ty1 -> bool*) + +definition bits_to_bool :: "(1)Word.word \ bool " where + " bits_to_bool x = ( bit_to_bool ((access_vec_dec x (( 0 :: int)::ii))))" + + +(* +function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. +*) +(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) + +definition to_bits :: "('l::len)itself \ int \('l::len)Word.word " where + " to_bits l n = ( + (let l = (size_itself_int l) in + (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) + +definition mask0 :: " int \('m::len)Word.word \('n::len)Word.word " where + " mask0 (n__tv :: int) bs = ( + (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))" + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \('n::len)Word.word \('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \('n::len)Word.word \('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \ int \ int \('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \ int \ int \ bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \ int \ int \ bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word \ int \ int \('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \('n::len)Word.word \ int \ int \ int \('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \ int \ int \('n::len)Word.word \ int \ int \ bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word \ int \ int \('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) + j' + :: ( 'm::len)Word.word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) + ((j' - (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \('n::len)Word.word \ int \ int \ int \('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \('n::len)Word.word \ int \ int \ int \('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \ int \ int \ int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \ int \ int \ int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \ int \('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + +(*val undefined_CauseReg : unit -> M CauseReg*) + +definition undefined_CauseReg :: " unit \((register_value),(CauseReg),(exception))monad " where + " undefined_CauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + internal_pick [Mk_CauseReg w__0]))" + + +(*val _get_CauseReg : CauseReg -> mword ty32*) + +fun get_CauseReg :: " CauseReg \(32)Word.word " where + " get_CauseReg (Mk_CauseReg (v)) = ( v )" + + +(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) + +definition set_CauseReg :: "((regstate),(register_value),(CauseReg))register_ref \(32)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_CauseReg v) in + write_reg r_ref r)))" + + +(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) + +(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) + +(*val _get_CauseReg_BD : CauseReg -> mword ty1*) + +fun get_CauseReg_BD :: " CauseReg \(1)Word.word " where + " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_BD r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_BD :: " CauseReg \(1)Word.word \ CauseReg " where + " update_CauseReg_BD (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_CE : CauseReg -> mword ty2*) + +fun get_CauseReg_CE :: " CauseReg \(2)Word.word " where + " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" + + +(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) + +definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_CE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) + +fun update_CauseReg_CE :: " CauseReg \(2)Word.word \ CauseReg " where + " update_CauseReg_CE (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IV : CauseReg -> mword ty1*) + +fun get_CauseReg_IV :: " CauseReg \(1)Word.word " where + " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_IV r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_IV :: " CauseReg \(1)Word.word \ CauseReg " where + " update_CauseReg_IV (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_WP : CauseReg -> mword ty1*) + +fun get_CauseReg_WP :: " CauseReg \(1)Word.word " where + " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_WP r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_WP :: " CauseReg \(1)Word.word \ CauseReg " where + " update_CauseReg_WP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IP : CauseReg -> mword ty8*) + +fun get_CauseReg_IP :: " CauseReg \(8)Word.word " where + " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) + +definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_IP r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) + +fun update_CauseReg_IP :: " CauseReg \(8)Word.word \ CauseReg " where + " update_CauseReg_IP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) + +fun get_CauseReg_ExcCode :: " CauseReg \(5)Word.word " where + " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" + + +(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) + +definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \(5)Word.word \((register_value),(unit),(exception))monad " where + " set_CauseReg_ExcCode r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) + +fun update_CauseReg_ExcCode :: " CauseReg \(5)Word.word \ CauseReg " where + " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) + +(*val _get_CapCauseReg_ExcCode : CapCauseReg -> mword ty8*) + +(*val _set_CapCauseReg_ExcCode : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) + +definition undefined_TLBEntryLoReg :: " unit \((register_value),(TLBEntryLoReg),(exception))monad " where + " undefined_TLBEntryLoReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryLoReg w__0]))" + + +(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) + +fun get_TLBEntryLoReg :: " TLBEntryLoReg \(64)Word.word " where + " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )" + + +(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) + +definition set_TLBEntryLoReg :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_TLBEntryLoReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \(1)Word.word " where + " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \(1)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \(1)Word.word " where + " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \(1)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) + +fun get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \(24)Word.word " where + " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) + +definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(24)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_PFN r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \(24)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) + +fun get_TLBEntryLoReg_C :: " TLBEntryLoReg \(3)Word.word " where + " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) + +definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(3)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_C r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_C :: " TLBEntryLoReg \(3)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_D :: " TLBEntryLoReg \(1)Word.word " where + " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_D r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_D :: " TLBEntryLoReg \(1)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_V :: " TLBEntryLoReg \(1)Word.word " where + " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_V r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_V :: " TLBEntryLoReg \(1)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_G :: " TLBEntryLoReg \(1)Word.word " where + " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_G r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \(1)Word.word \ TLBEntryLoReg " where + " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) + +definition undefined_TLBEntryHiReg :: " unit \((register_value),(TLBEntryHiReg),(exception))monad " where + " undefined_TLBEntryHiReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryHiReg w__0]))" + + +(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) + +fun get_TLBEntryHiReg :: " TLBEntryHiReg \(64)Word.word " where + " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )" + + +(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +definition set_TLBEntryHiReg :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_TLBEntryHiReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) + +fun get_TLBEntryHiReg_R :: " TLBEntryHiReg \(2)Word.word " where + " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) + +definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_R r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_R :: " TLBEntryHiReg \(2)Word.word \ TLBEntryHiReg " where + " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) + +fun get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \(27)Word.word " where + " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = ( + (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) + +definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \(27)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_VPN2 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \(27)Word.word \ TLBEntryHiReg " where + " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) + +fun get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \(8)Word.word " where + " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) + +definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_ASID r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \(8)Word.word \ TLBEntryHiReg " where + " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_ContextReg : unit -> M ContextReg*) + +definition undefined_ContextReg :: " unit \((register_value),(ContextReg),(exception))monad " where + " undefined_ContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + internal_pick [Mk_ContextReg w__0]))" + + +(*val _get_ContextReg : ContextReg -> mword ty64*) + +fun get_ContextReg :: " ContextReg \(64)Word.word " where + " get_ContextReg (Mk_ContextReg (v)) = ( v )" + + +(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +definition set_ContextReg :: "((regstate),(register_value),(ContextReg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_ContextReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_ContextReg v) in + write_reg r_ref r)))" + + +(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) + +fun get_ContextReg_PTEBase :: " ContextReg \(41)Word.word " where + " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" + + +(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) + +definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \(41)Word.word \((register_value),(unit),(exception))monad " where + " set_ContextReg_PTEBase r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) + +fun update_ContextReg_PTEBase :: " ContextReg \(41)Word.word \ ContextReg " where + " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) + +fun get_ContextReg_BadVPN2 :: " ContextReg \(19)Word.word " where + " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" + + +(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) + +definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \(19)Word.word \((register_value),(unit),(exception))monad " where + " set_ContextReg_BadVPN2 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) + +fun update_ContextReg_BadVPN2 :: " ContextReg \(19)Word.word \ ContextReg " where + " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_XContextReg : unit -> M XContextReg*) + +definition undefined_XContextReg :: " unit \((register_value),(XContextReg),(exception))monad " where + " undefined_XContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + internal_pick [Mk_XContextReg w__0]))" + + +(*val _get_XContextReg : XContextReg -> mword ty64*) + +fun get_XContextReg :: " XContextReg \(64)Word.word " where + " get_XContextReg (Mk_XContextReg (v)) = ( v )" + + +(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +definition set_XContextReg :: "((regstate),(register_value),(XContextReg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_XContextReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_XContextReg v) in + write_reg r_ref r)))" + + +(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) + +fun get_XContextReg_XPTEBase :: " XContextReg \(31)Word.word " where + " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" + + +(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) + +definition set_XContextReg_XPTEBase :: "((regstate),(register_value),(XContextReg))register_ref \(31)Word.word \((register_value),(unit),(exception))monad " where + " set_XContextReg_XPTEBase r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) + +fun update_XContextReg_XPTEBase :: " XContextReg \(31)Word.word \ XContextReg " where + " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XR : XContextReg -> mword ty2*) + +fun get_XContextReg_XR :: " XContextReg \(2)Word.word " where + " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" + + +(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) + +definition set_XContextReg_XR :: "((regstate),(register_value),(XContextReg))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_XContextReg_XR r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) + +fun update_XContextReg_XR :: " XContextReg \(2)Word.word \ XContextReg " where + " update_XContextReg_XR (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) + +fun get_XContextReg_XBadVPN2 :: " XContextReg \(27)Word.word " where + " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" + + +(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) + +definition set_XContextReg_XBadVPN2 :: "((regstate),(register_value),(XContextReg))register_ref \(27)Word.word \((register_value),(unit),(exception))monad " where + " set_XContextReg_XBadVPN2 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) + +fun update_XContextReg_XBadVPN2 :: " XContextReg \(27)Word.word \ XContextReg " where + " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +definition TLBNumEntries :: " int " where + " TLBNumEntries = ( (( 64 :: int)::ii))" + + +definition TLBIndexMax :: "(6)Word.word " where + " TLBIndexMax = ( (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))" + + +(*val MAX : integer -> integer*) + +definition MAX :: " int \ int " where + " MAX n = ( ((pow2 n)) - (( 1 :: int)::ii))" + + +definition MAX_U64 :: " int " where + " MAX_U64 = ( MAX (( 64 :: int)::ii))" + + +definition MAX_VA :: " int " where + " MAX_VA = ( MAX (( 40 :: int)::ii))" + + +definition MAX_PA :: " int " where + " MAX_PA = ( MAX (( 36 :: int)::ii))" + + +(*val undefined_TLBEntry : unit -> M TLBEntry*) + +definition undefined_TLBEntry :: " unit \((register_value),(TLBEntry),(exception))monad " where + " undefined_TLBEntry _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii) :: ( 117 Word.word) M) \ (\ (w__0 :: 117 Word.word) . + internal_pick [Mk_TLBEntry w__0]))" + + +(*val _get_TLBEntry : TLBEntry -> mword ty117*) + +fun get_TLBEntry :: " TLBEntry \(117)Word.word " where + " get_TLBEntry (Mk_TLBEntry (v)) = ( v )" + + +(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +definition set_TLBEntry :: "((regstate),(register_value),(TLBEntry))register_ref \(117)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_TLBEntry v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) + +fun get_TLBEntry_pagemask :: " TLBEntry \(16)Word.word " where + " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) :: 16 Word.word))" + + +(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) + +definition set_TLBEntry_pagemask :: "((regstate),(register_value),(TLBEntry))register_ref \(16)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_pagemask r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) + +fun update_TLBEntry_pagemask :: " TLBEntry \(16)Word.word \ TLBEntry " where + " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_r : TLBEntry -> mword ty2*) + +fun get_TLBEntry_r :: " TLBEntry \(2)Word.word " where + " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) + +definition set_TLBEntry_r :: "((regstate),(register_value),(TLBEntry))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_r r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) + +fun update_TLBEntry_r :: " TLBEntry \(2)Word.word \ TLBEntry " where + " update_TLBEntry_r (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) + +fun get_TLBEntry_vpn2 :: " TLBEntry \(27)Word.word " where + " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) + +definition set_TLBEntry_vpn2 :: "((regstate),(register_value),(TLBEntry))register_ref \(27)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_vpn2 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) + +fun update_TLBEntry_vpn2 :: " TLBEntry \(27)Word.word \ TLBEntry " where + " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) + +fun get_TLBEntry_asid :: " TLBEntry \(8)Word.word " where + " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) + +definition set_TLBEntry_asid :: "((regstate),(register_value),(TLBEntry))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_asid r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) + +fun update_TLBEntry_asid :: " TLBEntry \(8)Word.word \ TLBEntry " where + " update_TLBEntry_asid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_g : TLBEntry -> mword ty1*) + +fun get_TLBEntry_g :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_g :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_g r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_g :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_g (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) + +fun get_TLBEntry_valid :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_valid :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_valid r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_valid :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_valid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps1 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps1 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps1 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl1 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl1 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl1 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn1 :: " TLBEntry \(24)Word.word " where + " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn1 :: "((regstate),(register_value),(TLBEntry))register_ref \(24)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn1 :: " TLBEntry \(24)Word.word \ TLBEntry " where + " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c1 :: " TLBEntry \(3)Word.word " where + " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c1 :: "((regstate),(register_value),(TLBEntry))register_ref \(3)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_c1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c1 :: " TLBEntry \(3)Word.word \ TLBEntry " where + " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d1 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d1 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_d1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d1 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v1 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v1 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_v1 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v1 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps0 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps0 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps0 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl0 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl0 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl0 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn0 :: " TLBEntry \(24)Word.word " where + " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn0 :: "((regstate),(register_value),(TLBEntry))register_ref \(24)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn0 :: " TLBEntry \(24)Word.word \ TLBEntry " where + " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c0 :: " TLBEntry \(3)Word.word " where + " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c0 :: "((regstate),(register_value),(TLBEntry))register_ref \(3)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_c0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c0 :: " TLBEntry \(3)Word.word \ TLBEntry " where + " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d0 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d0 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_d0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d0 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v0 :: " TLBEntry \(1)Word.word " where + " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v0 :: "((regstate),(register_value),(TLBEntry))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_TLBEntry_v0 r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v0 :: " TLBEntry \(1)Word.word \ TLBEntry " where + " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 117 Word.word)))" + + +definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref)list " where + " TLBEntries = ( + [TLBEntry63_ref,TLBEntry62_ref,TLBEntry61_ref,TLBEntry60_ref,TLBEntry59_ref,TLBEntry58_ref, + TLBEntry57_ref,TLBEntry56_ref,TLBEntry55_ref,TLBEntry54_ref,TLBEntry53_ref,TLBEntry52_ref, + TLBEntry51_ref,TLBEntry50_ref,TLBEntry49_ref,TLBEntry48_ref,TLBEntry47_ref,TLBEntry46_ref, + TLBEntry45_ref,TLBEntry44_ref,TLBEntry43_ref,TLBEntry42_ref,TLBEntry41_ref,TLBEntry40_ref, + TLBEntry39_ref,TLBEntry38_ref,TLBEntry37_ref,TLBEntry36_ref,TLBEntry35_ref,TLBEntry34_ref, + TLBEntry33_ref,TLBEntry32_ref,TLBEntry31_ref,TLBEntry30_ref,TLBEntry29_ref,TLBEntry28_ref, + TLBEntry27_ref,TLBEntry26_ref,TLBEntry25_ref,TLBEntry24_ref,TLBEntry23_ref,TLBEntry22_ref, + TLBEntry21_ref,TLBEntry20_ref,TLBEntry19_ref,TLBEntry18_ref,TLBEntry17_ref,TLBEntry16_ref, + TLBEntry15_ref,TLBEntry14_ref,TLBEntry13_ref,TLBEntry12_ref,TLBEntry11_ref,TLBEntry10_ref, + TLBEntry09_ref,TLBEntry08_ref,TLBEntry07_ref,TLBEntry06_ref,TLBEntry05_ref,TLBEntry04_ref, + TLBEntry03_ref,TLBEntry02_ref,TLBEntry01_ref,TLBEntry00_ref])" + + +(*val undefined_StatusReg : unit -> M StatusReg*) + +definition undefined_StatusReg :: " unit \((register_value),(StatusReg),(exception))monad " where + " undefined_StatusReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + internal_pick [Mk_StatusReg w__0]))" + + +(*val _get_StatusReg : StatusReg -> mword ty32*) + +fun get_StatusReg :: " StatusReg \(32)Word.word " where + " get_StatusReg (Mk_StatusReg (v)) = ( v )" + + +(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) + +definition set_StatusReg :: "((regstate),(register_value),(StatusReg))register_ref \(32)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_StatusReg v) in + write_reg r_ref r)))" + + +(*val _get_StatusReg_CU : StatusReg -> mword ty4*) + +fun get_StatusReg_CU :: " StatusReg \(4)Word.word " where + " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" + + +(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) + +definition set_StatusReg_CU :: "((regstate),(register_value),(StatusReg))register_ref \(4)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_CU r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) + +fun update_StatusReg_CU :: " StatusReg \(4)Word.word \ StatusReg " where + " update_StatusReg_CU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_BEV : StatusReg -> mword ty1*) + +fun get_StatusReg_BEV :: " StatusReg \(1)Word.word " where + " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_BEV :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_BEV r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_BEV :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_BEV (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IM : StatusReg -> mword ty8*) + +fun get_StatusReg_IM :: " StatusReg \(8)Word.word " where + " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) + +definition set_StatusReg_IM :: "((regstate),(register_value),(StatusReg))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_IM r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) + +fun update_StatusReg_IM :: " StatusReg \(8)Word.word \ StatusReg " where + " update_StatusReg_IM (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KX : StatusReg -> mword ty1*) + +fun get_StatusReg_KX :: " StatusReg \(1)Word.word " where + " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_KX :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_KX r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_KX :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_KX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_SX : StatusReg -> mword ty1*) + +fun get_StatusReg_SX :: " StatusReg \(1)Word.word " where + " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_SX :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_SX r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_SX :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_SX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_UX : StatusReg -> mword ty1*) + +fun get_StatusReg_UX :: " StatusReg \(1)Word.word " where + " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_UX :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_UX r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_UX :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_UX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KSU : StatusReg -> mword ty2*) + +fun get_StatusReg_KSU :: " StatusReg \(2)Word.word " where + " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" + + +(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) + +definition set_StatusReg_KSU :: "((regstate),(register_value),(StatusReg))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_KSU r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) + +fun update_StatusReg_KSU :: " StatusReg \(2)Word.word \ StatusReg " where + " update_StatusReg_KSU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_ERL : StatusReg -> mword ty1*) + +fun get_StatusReg_ERL :: " StatusReg \(1)Word.word " where + " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_ERL :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_ERL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_ERL :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_ERL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_EXL : StatusReg -> mword ty1*) + +fun get_StatusReg_EXL :: " StatusReg \(1)Word.word " where + " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_EXL :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_EXL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_EXL :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_EXL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IE : StatusReg -> mword ty1*) + +fun get_StatusReg_IE :: " StatusReg \(1)Word.word " where + " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_IE :: "((regstate),(register_value),(StatusReg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_StatusReg_IE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_IE :: " StatusReg \(1)Word.word \ StatusReg " where + " update_StatusReg_IE (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 32 Word.word)))" + + +(*val execute_branch : mword ty64 -> M unit*) + +definition execute_branch :: "(64)Word.word \((register_value),(unit),(exception))monad " where + " execute_branch pc = ( + write_reg delayedPC_ref pc \ write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val NotWordVal : mword ty64 -> bool*) + +definition NotWordVal :: "(64)Word.word \ bool " where + " NotWordVal word1 = ( + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word1 (( 31 :: int)::ii))) :: 1 Word.word)) (( 32 :: int)::ii) + :: 32 Word.word)) \ ((subrange_vec_dec word1 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))))" + + +(*val rGPR : mword ty5 -> M (mword ty64)*) + +definition rGPR :: "(5)Word.word \((register_value),((64)Word.word),(exception))monad " where + " rGPR idx = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg GPR_ref \ (\ (w__0 :: ( 64 bits) list) . + return ((access_list_dec w__0 i :: 64 Word.word)))))" + + +(*val wGPR : mword ty5 -> mword ty64 -> M unit*) + +definition wGPR :: "(5)Word.word \(64)Word.word \((register_value),(unit),(exception))monad " where + " wGPR idx v = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then return () + else + read_reg GPR_ref \ (\ (w__0 :: ( 64 Word.word) list) . + write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list)))))" + + + + + + + + + + + + + + + + +(*val Exception_of_num : integer -> Exception*) + +definition Exception_of_num :: " int \ Exception " where + " Exception_of_num arg0 = ( + (let l__81 = arg0 in + if (((l__81 = (( 0 :: int)::ii)))) then Interrupt + else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod + else if (((l__81 = (( 2 :: int)::ii)))) then TLBL + else if (((l__81 = (( 3 :: int)::ii)))) then TLBS + else if (((l__81 = (( 4 :: int)::ii)))) then AdEL + else if (((l__81 = (( 5 :: int)::ii)))) then AdES + else if (((l__81 = (( 6 :: int)::ii)))) then Sys + else if (((l__81 = (( 7 :: int)::ii)))) then Bp + else if (((l__81 = (( 8 :: int)::ii)))) then ResI + else if (((l__81 = (( 9 :: int)::ii)))) then CpU + else if (((l__81 = (( 10 :: int)::ii)))) then Ov + else if (((l__81 = (( 11 :: int)::ii)))) then Tr + else if (((l__81 = (( 12 :: int)::ii)))) then C2E + else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap + else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL + else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS + else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL + else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS + else MCheck))" + + +(*val num_of_Exception : Exception -> integer*) + +fun num_of_Exception :: " Exception \ int " where + " num_of_Exception Interrupt = ( (( 0 :: int)::ii))" +|" num_of_Exception TLBMod = ( (( 1 :: int)::ii))" +|" num_of_Exception TLBL = ( (( 2 :: int)::ii))" +|" num_of_Exception TLBS = ( (( 3 :: int)::ii))" +|" num_of_Exception AdEL = ( (( 4 :: int)::ii))" +|" num_of_Exception AdES = ( (( 5 :: int)::ii))" +|" num_of_Exception Sys = ( (( 6 :: int)::ii))" +|" num_of_Exception Bp = ( (( 7 :: int)::ii))" +|" num_of_Exception ResI = ( (( 8 :: int)::ii))" +|" num_of_Exception CpU = ( (( 9 :: int)::ii))" +|" num_of_Exception Ov = ( (( 10 :: int)::ii))" +|" num_of_Exception Tr = ( (( 11 :: int)::ii))" +|" num_of_Exception C2E = ( (( 12 :: int)::ii))" +|" num_of_Exception C2Trap = ( (( 13 :: int)::ii))" +|" num_of_Exception XTLBRefillL = ( (( 14 :: int)::ii))" +|" num_of_Exception XTLBRefillS = ( (( 15 :: int)::ii))" +|" num_of_Exception XTLBInvL = ( (( 16 :: int)::ii))" +|" num_of_Exception XTLBInvS = ( (( 17 :: int)::ii))" +|" num_of_Exception MCheck = ( (( 18 :: int)::ii))" + + +(*val undefined_Exception : unit -> M Exception*) + +definition undefined_Exception :: " unit \((register_value),(Exception),(exception))monad " where + " undefined_Exception _ = ( + internal_pick + [Interrupt,TLBMod,TLBL,TLBS,AdEL,AdES,Sys,Bp,ResI,CpU,Ov,Tr,C2E,C2Trap,XTLBRefillL,XTLBRefillS,XTLBInvL,XTLBInvS,MCheck])" + + +(*val ExceptionCode : Exception -> mword ty5*) + +definition ExceptionCode :: " Exception \(5)Word.word " where + " ExceptionCode ex = ( + (let (x :: 8 bits) = + ((case ex of + Interrupt => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + | TLBMod => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word) + | TLBL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | TLBS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | AdEL => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word) + | AdES => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word) + | Sys => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word) + | Bp => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word) + | ResI => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word) + | CpU => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word) + | Ov => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B0] :: 8 Word.word) + | Tr => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B1] :: 8 Word.word) + | C2E => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | C2Trap => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | XTLBInvL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBInvS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | MCheck => (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word) + )) in + (subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)))" + + +(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionMIPS :: " Exception \(64)Word.word \((register_value),'o,(exception))monad " where + " SignalExceptionMIPS ex kccBase = ( + read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + ((if ((\ ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg inBranchDelay_ref :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + write_reg CP0EPC_ref ((sub_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)) \ + set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] :: 1 Word.word)) + else + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + write_reg CP0EPC_ref w__3 \ set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] :: 1 Word.word))) + else return () ) \ + read_reg CP0Status_ref) \ (\ (w__4 :: StatusReg) . + (let vectorOffset = + (if ((bits_to_bool ((get_StatusReg_EXL w__4 :: 1 Word.word)))) then + (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if ((((((ex = XTLBRefillL))) \ (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if (((ex = C2Trap))) then (vec_of_bits [B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) in + read_reg CP0Status_ref \ (\ (w__5 :: StatusReg) . + (let (vectorBase :: 64 bits) = + (if ((bits_to_bool ((get_StatusReg_BEV w__5 :: 1 Word.word)))) then + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) in + ((write_reg + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) + kccBase + :: 64 Word.word)) \ + set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex :: 5 Word.word))) \ + set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] :: 1 Word.word)) \ throw (ISAException () )))))))" + + +(*val SignalException : forall 'o. Exception -> M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*) + +(*val capRegToCapStruct : mword ty257 -> CapStruct*) + +definition capRegToCapStruct :: "(257)Word.word \ CapStruct " where + " capRegToCapStruct capReg = ( + (| CapStruct_tag = ((bit_to_bool ((access_vec_dec capReg (( 256 :: int)::ii))))), + CapStruct_padding = ((subrange_vec_dec capReg (( 255 :: int)::ii) (( 248 :: int)::ii) :: 8 Word.word)), + CapStruct_otype = ((subrange_vec_dec capReg (( 247 :: int)::ii) (( 224 :: int)::ii) :: 24 Word.word)), + CapStruct_uperms = ((subrange_vec_dec capReg (( 223 :: int)::ii) (( 208 :: int)::ii) :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((subrange_vec_dec capReg (( 207 :: int)::ii) (( 204 :: int)::ii) :: 4 Word.word)), + CapStruct_access_system_regs = ((bit_to_bool ((access_vec_dec capReg (( 203 :: int)::ii))))), + CapStruct_permit_unseal = ((bit_to_bool ((access_vec_dec capReg (( 202 :: int)::ii))))), + CapStruct_permit_ccall = ((bit_to_bool ((access_vec_dec capReg (( 201 :: int)::ii))))), + CapStruct_permit_seal = ((bit_to_bool ((access_vec_dec capReg (( 200 :: int)::ii))))), + CapStruct_permit_store_local_cap = ((bit_to_bool ((access_vec_dec capReg (( 199 :: int)::ii))))), + CapStruct_permit_store_cap = ((bit_to_bool ((access_vec_dec capReg (( 198 :: int)::ii))))), + CapStruct_permit_load_cap = ((bit_to_bool ((access_vec_dec capReg (( 197 :: int)::ii))))), + CapStruct_permit_store = ((bit_to_bool ((access_vec_dec capReg (( 196 :: int)::ii))))), + CapStruct_permit_load = ((bit_to_bool ((access_vec_dec capReg (( 195 :: int)::ii))))), + CapStruct_permit_execute = ((bit_to_bool ((access_vec_dec capReg (( 194 :: int)::ii))))), + CapStruct_global = ((bit_to_bool ((access_vec_dec capReg (( 193 :: int)::ii))))), + CapStruct_sealed = ((bit_to_bool ((access_vec_dec capReg (( 192 :: int)::ii))))), + CapStruct_address = ((subrange_vec_dec capReg (( 191 :: int)::ii) (( 128 :: int)::ii) :: 64 Word.word)), + CapStruct_base = ((subrange_vec_dec capReg (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)), + CapStruct_length = ((subrange_vec_dec capReg (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + + +(*val getCapPerms : CapStruct -> mword ty31*) + +definition getCapPerms :: " CapStruct \(31)Word.word " where + " getCapPerms cap = ( + (concat_vec(CapStruct_uperms cap) + ((concat_vec(CapStruct_perm_reserved11_14 cap) + ((concat_vec ((bool_to_bits(CapStruct_access_system_regs cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_unseal cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_ccall cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_seal cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_local_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_execute cap) + :: 1 Word.word)) + ((bool_to_bits(CapStruct_global cap) :: 1 Word.word)) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 8 Word.word)) + :: 9 Word.word)) + :: 10 Word.word)) + :: 11 Word.word)) + :: 15 Word.word)) + :: 31 Word.word))" + + +(*val capStructToMemBits256 : CapStruct -> mword ty256*) + +definition capStructToMemBits256 :: " CapStruct \(256)Word.word " where + " capStructToMemBits256 cap = ( + (concat_vec(CapStruct_padding cap) + ((concat_vec(CapStruct_otype cap) + ((concat_vec ((getCapPerms cap :: 31 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_sealed cap) :: 1 Word.word)) + ((concat_vec(CapStruct_address cap) + ((concat_vec(CapStruct_base cap)(CapStruct_length cap) :: 128 Word.word)) + :: 192 Word.word)) + :: 193 Word.word)) + :: 224 Word.word)) + :: 248 Word.word)) + :: 256 Word.word))" + + +(*val capStructToCapReg : CapStruct -> mword ty257*) + +definition capStructToCapReg :: " CapStruct \(257)Word.word " where + " capStructToCapReg cap = ( + (concat_vec ((bool_to_bits(CapStruct_tag cap) :: 1 Word.word)) + ((capStructToMemBits256 cap :: 256 Word.word)) + :: 257 Word.word))" + + +(*val getCapBase : CapStruct -> integer*) + +definition getCapBase :: " CapStruct \ int " where + " getCapBase c = ( Word.uint(CapStruct_base c))" + + +definition null_cap :: " CapStruct " where + " null_cap = ( + (| CapStruct_tag = False, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((zeros0 (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = False, + CapStruct_permit_unseal = False, + CapStruct_permit_ccall = False, + CapStruct_permit_seal = False, + CapStruct_permit_store_local_cap = False, + CapStruct_permit_store_cap = False, + CapStruct_permit_load_cap = False, + CapStruct_permit_store = False, + CapStruct_permit_load = False, + CapStruct_permit_execute = False, + CapStruct_global = False, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +(*val int_to_cap : mword ty64 -> CapStruct*) + +definition int_to_cap :: "(64)Word.word \ CapStruct " where + " int_to_cap address = ( (null_cap (| CapStruct_address := address |)))" + + +(* +Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). + *) +(*val setCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition setCapOffset :: " CapStruct \(64)Word.word \ bool*CapStruct " where + " setCapOffset c offset = ( + (True, (c (| CapStruct_address := ((add_vec(CapStruct_base c) offset :: 64 Word.word))|))))" + + +definition SignalException :: " Exception \((register_value),'o,(exception))monad " where + " SignalException ex = ( + read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + ((if ((\ ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ pc . + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (let (success, epcc) = (setCapOffset pcc pc) in + if success then write_reg C31_ref ((capStructToCapReg epcc :: 257 Word.word)) + else + write_reg + C31_ref + ((capStructToCapReg + ((int_to_cap + ((add_vec_int + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase pcc)) + :: 64 Word.word)) ((Word.uint pc)) + :: 64 Word.word)))) + :: 257 Word.word)))))) + else return () ) \ + (read_reg C29_ref :: ( 257 Word.word) M)) \ (\ (w__2 :: CapReg) . + (write_reg nextPCC_ref w__2 \ + (read_reg C29_ref :: ( 257 Word.word) M)) \ (\ (w__3 :: CapReg) . + (write_reg delayedPCC_ref w__3 \ + (read_reg C29_ref :: ( 257 Word.word) M)) \ (\ (w__4 :: 257 Word.word) . + (let base = (getCapBase ((capRegToCapStruct w__4))) in + SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) base :: 64 Word.word))))))))" + + +definition SignalExceptionBadAddr :: " Exception \(64)Word.word \((register_value),'o,(exception))monad " where + " SignalExceptionBadAddr ex badAddr = ( write_reg CP0BadVAddr_ref badAddr \ SignalException ex )" + + +(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionTLB :: " Exception \(64)Word.word \((register_value),'o,(exception))monad " where + " SignalExceptionTLB ex badAddr = ( + (((((write_reg CP0BadVAddr_ref badAddr \ + set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 :: int)::ii) (( 13 :: int)::ii) :: 19 Word.word))) \ + set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \ + set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \ + set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \ + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \ + SignalException ex )" + + +(*val MemAccessType_of_num : integer -> MemAccessType*) + +definition MemAccessType_of_num :: " int \ MemAccessType " where + " MemAccessType_of_num arg0 = ( + (let l__79 = arg0 in + if (((l__79 = (( 0 :: int)::ii)))) then Instruction + else if (((l__79 = (( 1 :: int)::ii)))) then LoadData + else StoreData))" + + +(*val num_of_MemAccessType : MemAccessType -> integer*) + +fun num_of_MemAccessType :: " MemAccessType \ int " where + " num_of_MemAccessType Instruction = ( (( 0 :: int)::ii))" +|" num_of_MemAccessType LoadData = ( (( 1 :: int)::ii))" +|" num_of_MemAccessType StoreData = ( (( 2 :: int)::ii))" + + +(*val undefined_MemAccessType : unit -> M MemAccessType*) + +definition undefined_MemAccessType :: " unit \((register_value),(MemAccessType),(exception))monad " where + " undefined_MemAccessType _ = ( internal_pick [Instruction,LoadData,StoreData])" + + +(*val AccessLevel_of_num : integer -> AccessLevel*) + +definition AccessLevel_of_num :: " int \ AccessLevel " where + " AccessLevel_of_num arg0 = ( + (let l__77 = arg0 in + if (((l__77 = (( 0 :: int)::ii)))) then User + else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + else Kernel))" + + +(*val num_of_AccessLevel : AccessLevel -> integer*) + +fun num_of_AccessLevel :: " AccessLevel \ int " where + " num_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" num_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" num_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(*val undefined_AccessLevel : unit -> M AccessLevel*) + +definition undefined_AccessLevel :: " unit \((register_value),(AccessLevel),(exception))monad " where + " undefined_AccessLevel _ = ( internal_pick [User,Supervisor,Kernel])" + + +(*val int_of_AccessLevel : AccessLevel -> ii*) + +fun int_of_AccessLevel :: " AccessLevel \ int " where + " int_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" int_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" int_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(* +Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + *) +(*val grantsAccess : AccessLevel -> AccessLevel -> bool*) + +definition grantsAccess :: " AccessLevel \ AccessLevel \ bool " where + " grantsAccess currentLevel requiredLevel = ( + ((int_of_AccessLevel currentLevel)) \ ((int_of_AccessLevel requiredLevel)))" + + +(* +Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. + *) +(*val getAccessLevel : unit -> M AccessLevel*) + +definition getAccessLevel :: " unit \((register_value),(AccessLevel),(exception))monad " where + " getAccessLevel _ = ( + or_boolM + (read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) + (read_reg CP0Status_ref \ (\ (w__1 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_ERL w__1 :: 1 Word.word)))))) \ (\ (w__2 :: bool) . + if w__2 then return Kernel + else + read_reg CP0Status_ref \ (\ (w__3 :: StatusReg) . + (let p__133 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in + (let b__0 = p__133 in + return (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then User + else User))))))" + + +(*val checkCP0Access : unit -> M unit*) + +definition checkCP0Access :: " unit \((register_value),(unit),(exception))monad " where + " checkCP0Access _ = ( + getAccessLevel () \ (\ accessLevel . + and_boolM (return (((accessLevel \ Kernel)))) + (read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + return ((\ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii))))))))) \ (\ (w__1 :: + bool) . + if w__1 then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0,B0] :: 2 Word.word) \ SignalException CpU + else return () )))" + + +(*val incrementCP0Count : unit -> M unit*) + +definition incrementCP0Count :: " unit \((register_value),(unit),(exception))monad " where + " incrementCP0Count _ = ( + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \ (\ (w__0 :: TLBIndexT) . + (read_reg TLBWired_ref :: ( 6 Word.word) M) \ (\ (w__1 :: 6 Word.word) . + (if (((w__0 = w__1))) then return TLBIndexMax + else + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \ (\ (w__2 :: 6 Word.word) . + return ((sub_vec_int w__2 (( 1 :: int)::ii) :: 6 Word.word)))) \ (\ (w__3 :: 6 Word.word) . + (write_reg TLBRandom_ref w__3 \ + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \ (\ (w__4 :: 32 Word.word) . + (write_reg CP0Count_ref ((add_vec_int w__4 (( 1 :: int)::ii) :: 32 Word.word)) \ + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \ (\ (w__5 :: 32 bits) . + (read_reg CP0Compare_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + ((if (((w__5 = w__6))) then + read_reg CP0Cause_ref \ (\ (w__7 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 :: 8 Word.word)) + (vec_of_bits [B1,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + :: 8 Word.word))) + else return () ) \ + read_reg CP0Status_ref) \ (\ (w__8 :: StatusReg) . + (let ims = ((get_StatusReg_IM w__8 :: 8 Word.word)) in + read_reg CP0Cause_ref \ (\ (w__9 :: CauseReg) . + (let ips = ((get_CauseReg_IP w__9 :: 8 Word.word)) in + read_reg CP0Status_ref \ (\ (w__10 :: StatusReg) . + (let ie = ((get_StatusReg_IE w__10 :: 1 Word.word)) in + read_reg CP0Status_ref \ (\ (w__11 :: StatusReg) . + (let exl = ((get_StatusReg_EXL w__11 :: 1 Word.word)) in + read_reg CP0Status_ref \ (\ (w__12 :: StatusReg) . + (let erl = ((get_StatusReg_ERL w__12 :: 1 Word.word)) in + if (((((\ ((bits_to_bool exl)))) \ (((((\ ((bits_to_bool erl)))) \ (((((bits_to_bool ie)) \ (((((and_vec ips ims :: 8 Word.word)) \ (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))))))))) then + SignalException Interrupt + else return () )))))))))))))))))" + + +(*val decode_failure_of_num : integer -> decode_failure*) + +definition decode_failure_of_num :: " int \ decode_failure " where + " decode_failure_of_num arg0 = ( + (let l__74 = arg0 in + if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern + else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction + else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction + else Internal_error))" + + +(*val num_of_decode_failure : decode_failure -> integer*) + +definition num_of_decode_failure :: " decode_failure \ int " where + " num_of_decode_failure no_matching_pattern = ( (( 0 :: int)::ii))" + + +(*val undefined_decode_failure : unit -> M decode_failure*) + +definition undefined_decode_failure :: " unit \((register_value),(decode_failure),(exception))monad " where + " undefined_decode_failure _ = ( + internal_pick [No_matching_pattern,Unsupported_instruction,Illegal_instruction,Internal_error])" + + +(*val Comparison_of_num : integer -> Comparison*) + +definition Comparison_of_num :: " int \ Comparison " where + " Comparison_of_num arg0 = ( + (let l__67 = arg0 in + if (((l__67 = (( 0 :: int)::ii)))) then EQ' + else if (((l__67 = (( 1 :: int)::ii)))) then NE + else if (((l__67 = (( 2 :: int)::ii)))) then GE + else if (((l__67 = (( 3 :: int)::ii)))) then GEU + else if (((l__67 = (( 4 :: int)::ii)))) then GT' + else if (((l__67 = (( 5 :: int)::ii)))) then LE + else if (((l__67 = (( 6 :: int)::ii)))) then LT' + else LTU))" + + +(*val num_of_Comparison : Comparison -> integer*) + +fun num_of_Comparison :: " Comparison \ int " where + " num_of_Comparison EQ' = ( (( 0 :: int)::ii))" +|" num_of_Comparison NE = ( (( 1 :: int)::ii))" +|" num_of_Comparison GE = ( (( 2 :: int)::ii))" +|" num_of_Comparison GEU = ( (( 3 :: int)::ii))" +|" num_of_Comparison GT' = ( (( 4 :: int)::ii))" +|" num_of_Comparison LE = ( (( 5 :: int)::ii))" +|" num_of_Comparison LT' = ( (( 6 :: int)::ii))" +|" num_of_Comparison LTU = ( (( 7 :: int)::ii))" + + +(*val undefined_Comparison : unit -> M Comparison*) + +definition undefined_Comparison :: " unit \((register_value),(Comparison),(exception))monad " where + " undefined_Comparison _ = ( internal_pick [EQ',NE,GE,GEU,GT',LE,LT',LTU])" + + +(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) + +fun compare :: " Comparison \(64)Word.word \(64)Word.word \ bool " where + " compare EQ' valA valB = ( (valA = valB))" +|" compare NE valA valB = ( (valA \ valB))" +|" compare GE valA valB = ( zopz0zKzJ_s valA valB )" +|" compare GEU valA valB = ( zopz0zKzJ_u valA valB )" +|" compare GT' valA valB = ( zopz0zI_s valB valA )" +|" compare LE valA valB = ( zopz0zKzJ_s valB valA )" +|" compare LT' valA valB = ( zopz0zI_s valA valB )" +|" compare LTU valA valB = ( zopz0zI_u valA valB )" + + +(*val WordType_of_num : integer -> WordType*) + +definition WordType_of_num :: " int \ WordType " where + " WordType_of_num arg0 = ( + (let l__64 = arg0 in + if (((l__64 = (( 0 :: int)::ii)))) then B + else if (((l__64 = (( 1 :: int)::ii)))) then H + else if (((l__64 = (( 2 :: int)::ii)))) then W + else D))" + + +(*val num_of_WordType : WordType -> integer*) + +fun num_of_WordType :: " WordType \ int " where + " num_of_WordType B = ( (( 0 :: int)::ii))" +|" num_of_WordType H = ( (( 1 :: int)::ii))" +|" num_of_WordType W = ( (( 2 :: int)::ii))" +|" num_of_WordType D = ( (( 3 :: int)::ii))" + + +(*val undefined_WordType : unit -> M WordType*) + +definition undefined_WordType :: " unit \((register_value),(WordType),(exception))monad " where + " undefined_WordType _ = ( internal_pick [B,H,W,D])" + + +(*val wordWidthBytes : WordType -> integer*) + +fun wordWidthBytes :: " WordType \ int " where + " wordWidthBytes B = ( (( 1 :: int)::ii))" +|" wordWidthBytes H = ( (( 2 :: int)::ii))" +|" wordWidthBytes W = ( (( 4 :: int)::ii))" +|" wordWidthBytes D = ( (( 8 :: int)::ii))" + + +definition alignment_width :: " int " where + " alignment_width = ( (( 16 :: int)::ii))" + + +(*val isAddressAligned : mword ty64 -> WordType -> bool*) + +definition isAddressAligned :: "(64)Word.word \ WordType \ bool " where + " isAddressAligned addr wordType = ( + (let a = (Word.uint addr) in + (((a div alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 :: int)::ii))) div + alignment_width)))))" + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_wrapper :: "(64)Word.word \ int \((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_wrapper addr size1 = ( + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \ (\ w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_reserve_wrapper :: "(64)Word.word \ int \((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_reserve_wrapper addr size1 = ( + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \ (\ w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val init_cp0_state : unit -> M unit*) + +definition init_cp0_state :: " unit \((register_value),(unit),(exception))monad " where + " init_cp0_state _ = ( set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 :: 1 Word.word)))" + + +(*val init_cp2_state : unit -> M unit*) + +(*val cp2_next_pc : unit -> M unit*) + +(*val dump_cp2_state : unit -> M unit*) + +(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) + +definition tlbEntryMatch :: "(2)Word.word \(27)Word.word \(8)Word.word \ TLBEntry \ bool " where + " tlbEntryMatch r vpn2 asid entry = ( + (let entryValid = ((get_TLBEntry_valid entry :: 1 Word.word)) in + (let entryR = ((get_TLBEntry_r entry :: 2 Word.word)) in + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let entryVPN = ((get_TLBEntry_vpn2 entry :: 27 Word.word)) in + (let entryASID = ((get_TLBEntry_asid entry :: 8 Word.word)) in + (let entryG = ((get_TLBEntry_g entry :: 1 Word.word)) in + (let (vpnMask :: 27 bits) = + ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in + (((bits_to_bool entryValid)) \ ((((((r = entryR))) \ ((((((((and_vec vpn2 vpnMask :: 27 Word.word)) = ((and_vec entryVPN vpnMask :: 27 Word.word))))) \ ((((((asid = entryASID))) \ ((bits_to_bool entryG))))))))))))))))))))" + + +(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) + +definition tlbSearch :: "(64)Word.word \((register_value),(((6)Word.word)option),(exception))monad " where + " tlbSearch VAddr = ( + catch_early_return + ((let r = ((subrange_vec_dec VAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let vpn2 = ((subrange_vec_dec VAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word)) in + liftR (read_reg TLBEntryHi_ref) \ (\ (w__0 :: TLBEntryHiReg) . + (let asid = ((get_TLBEntryHiReg_ASID w__0 :: 8 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) (( 63 :: int)::ii) (( 1 :: int)::ii)) () + (\ idx unit_var . + liftR (reg_deref ((access_list_dec TLBEntries idx))) \ (\ (w__1 :: TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return (Some ((to_bits ((make_the_value (( 6 :: int)::ii) :: 6 itself)) idx :: 6 Word.word))) :: (unit, ( ( 6 Word.word)option)) + MR) + else return () ))) \ + return None))))))" + + +(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslate2 :: "(64)Word.word \ MemAccessType \((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslate2 vAddr accessType = ( + (tlbSearch vAddr :: ( ( 6 Word.word)option) M) \ (\ idx . + (case idx of + Some (idx) => + (let i = (Word.uint idx) in + reg_deref ((access_list_dec TLBEntries i)) \ (\ entry . + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let b__0 = entryMask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + return (( 12 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) + then + return (( 14 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 16 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 18 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 20 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 22 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 24 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 26 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 28 :: int)::ii) + else undefined_range (( 12 :: int)::ii) (( 28 :: int)::ii)) \ (\ (evenOddBit :: int) . + (let isOdd = (access_vec_dec vAddr evenOddBit) in + (let ((caps :: 1 bits), (capl :: 1 bits), (pfn :: 24 bits), (d :: 1 bits), (v :: 1 bits)) = + (if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry :: 1 Word.word), + (get_TLBEntry_capl1 entry :: 1 Word.word), + (get_TLBEntry_pfn1 entry :: 24 Word.word), + (get_TLBEntry_d1 entry :: 1 Word.word), + (get_TLBEntry_v1 entry :: 1 Word.word)) + else + ((get_TLBEntry_caps0 entry :: 1 Word.word), + (get_TLBEntry_capl0 entry :: 1 Word.word), + (get_TLBEntry_pfn0 entry :: 24 Word.word), + (get_TLBEntry_d0 entry :: 1 Word.word), + (get_TLBEntry_v0 entry :: 1 Word.word))) in + if ((\ ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + :: (( 64 Word.word * bool)) M) + else if ((((((accessType = StoreData))) \ ((\ ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr :: (( 64 Word.word * bool)) M) + else + (let (res :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) + ((subrange_subrange_concat + (((((((( 23 :: int)::ii) - + ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii))))) + + + ((evenOddBit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) pfn + (( 23 :: int)::ii) ((evenOddBit - (( 12 :: int)::ii))) vAddr + ((evenOddBit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 36 Word.word)) + :: 64 Word.word)) in + return (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))))))))) + | None => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + :: (( 64 Word.word * bool)) M) + )))" + + +(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslateC :: "(64)Word.word \ MemAccessType \((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslateC vAddr accessType = ( + getAccessLevel () \ (\ currentAccessLevel . + (let compat32 = + (((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 31 :: int)::ii) :: 31 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1] + :: 31 Word.word)) in + (let b__0 = ((subrange_vec_dec vAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let ((requiredLevel :: AccessLevel), (addr :: ( 64 bits)option)) = + (if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) of + (True, b__1) => + if (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then (Kernel, None) + else if (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then (Supervisor, None) + else if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + else + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + | (g__131, g__132) => (Kernel, None) + ) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((subrange_vec_dec vAddr (( 58 :: int)::ii) (( 0 :: int)::ii) :: 59 Word.word)) + :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then (Supervisor, None) + else (User, None)) in + if ((\ ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else + (case addr of + Some (a) => return (a, False) + | None => + if (((((\ compat32)) \ ((((Word.uint ((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else (TLBTranslate2 vAddr accessType :: (( 64 Word.word * bool)) M) + ) \ (\ varstup . (let ((pa :: 64 bits), (c :: bool)) = varstup in + if ((((Word.uint pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else return (pa, c))))))))" + + +(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) + +definition TLBTranslate :: "(64)Word.word \ MemAccessType \((register_value),((64)Word.word),(exception))monad " where + " TLBTranslate vAddr accessType = ( + (TLBTranslateC vAddr accessType :: (( 64 Word.word * bool)) M) \ (\ varstup . (let (addr, c) = varstup in + return addr)))" + + +(*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*) + +definition CPtrCmpOp_of_num :: " int \ CPtrCmpOp " where + " CPtrCmpOp_of_num arg0 = ( + (let l__57 = arg0 in + if (((l__57 = (( 0 :: int)::ii)))) then CEQ + else if (((l__57 = (( 1 :: int)::ii)))) then CNE + else if (((l__57 = (( 2 :: int)::ii)))) then CLT + else if (((l__57 = (( 3 :: int)::ii)))) then CLE + else if (((l__57 = (( 4 :: int)::ii)))) then CLTU + else if (((l__57 = (( 5 :: int)::ii)))) then CLEU + else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ + else CNEXEQ))" + + +(*val num_of_CPtrCmpOp : CPtrCmpOp -> integer*) + +fun num_of_CPtrCmpOp :: " CPtrCmpOp \ int " where + " num_of_CPtrCmpOp CEQ = ( (( 0 :: int)::ii))" +|" num_of_CPtrCmpOp CNE = ( (( 1 :: int)::ii))" +|" num_of_CPtrCmpOp CLT = ( (( 2 :: int)::ii))" +|" num_of_CPtrCmpOp CLE = ( (( 3 :: int)::ii))" +|" num_of_CPtrCmpOp CLTU = ( (( 4 :: int)::ii))" +|" num_of_CPtrCmpOp CLEU = ( (( 5 :: int)::ii))" +|" num_of_CPtrCmpOp CEXEQ = ( (( 6 :: int)::ii))" +|" num_of_CPtrCmpOp CNEXEQ = ( (( 7 :: int)::ii))" + + +(*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*) + +definition undefined_CPtrCmpOp :: " unit \((register_value),(CPtrCmpOp),(exception))monad " where + " undefined_CPtrCmpOp _ = ( internal_pick [CEQ,CNE,CLT,CLE,CLTU,CLEU,CEXEQ,CNEXEQ])" + + +(*val ClearRegSet_of_num : integer -> ClearRegSet*) + +definition ClearRegSet_of_num :: " int \ ClearRegSet " where + " ClearRegSet_of_num arg0 = ( + (let l__54 = arg0 in + if (((l__54 = (( 0 :: int)::ii)))) then GPLo + else if (((l__54 = (( 1 :: int)::ii)))) then GPHi + else if (((l__54 = (( 2 :: int)::ii)))) then CLo + else CHi))" + + +(*val num_of_ClearRegSet : ClearRegSet -> integer*) + +fun num_of_ClearRegSet :: " ClearRegSet \ int " where + " num_of_ClearRegSet GPLo = ( (( 0 :: int)::ii))" +|" num_of_ClearRegSet GPHi = ( (( 1 :: int)::ii))" +|" num_of_ClearRegSet CLo = ( (( 2 :: int)::ii))" +|" num_of_ClearRegSet CHi = ( (( 3 :: int)::ii))" + + +(*val undefined_ClearRegSet : unit -> M ClearRegSet*) + +definition undefined_ClearRegSet :: " unit \((register_value),(ClearRegSet),(exception))monad " where + " undefined_ClearRegSet _ = ( internal_pick [GPLo,GPHi,CLo,CHi])" + + +(*val undefined_CapStruct : unit -> M CapStruct*) + +definition undefined_CapStruct :: " unit \((register_value),(CapStruct),(exception))monad " where + " undefined_CapStruct _ = ( + undefined_bool () \ (\ (w__0 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__1 :: 8 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \ (\ (w__2 :: 24 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__3 :: 16 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__4 :: 4 bits) . + undefined_bool () \ (\ (w__5 :: bool) . + undefined_bool () \ (\ (w__6 :: bool) . + undefined_bool () \ (\ (w__7 :: bool) . + undefined_bool () \ (\ (w__8 :: bool) . + undefined_bool () \ (\ (w__9 :: bool) . + undefined_bool () \ (\ (w__10 :: bool) . + undefined_bool () \ (\ (w__11 :: bool) . + undefined_bool () \ (\ (w__12 :: bool) . + undefined_bool () \ (\ (w__13 :: bool) . + undefined_bool () \ (\ (w__14 :: bool) . + undefined_bool () \ (\ (w__15 :: bool) . + undefined_bool () \ (\ (w__16 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__17 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__18 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__19 :: 64 bits) . + return ((| CapStruct_tag = w__0, + CapStruct_padding = w__1, + CapStruct_otype = w__2, + CapStruct_uperms = w__3, + CapStruct_perm_reserved11_14 = w__4, + CapStruct_access_system_regs = w__5, + CapStruct_permit_unseal = w__6, + CapStruct_permit_ccall = w__7, + CapStruct_permit_seal = w__8, + CapStruct_permit_store_local_cap = w__9, + CapStruct_permit_store_cap = w__10, + CapStruct_permit_load_cap = w__11, + CapStruct_permit_store = w__12, + CapStruct_permit_load = w__13, + CapStruct_permit_execute = w__14, + CapStruct_global = w__15, + CapStruct_sealed = w__16, + CapStruct_address = w__17, + CapStruct_base = w__18, + CapStruct_length = w__19 |)))))))))))))))))))))))" + + +definition default_cap :: " CapStruct " where + " default_cap = ( + (| CapStruct_tag = True, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((ones (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = True, + CapStruct_permit_unseal = True, + CapStruct_permit_ccall = True, + CapStruct_permit_seal = True, + CapStruct_permit_store_local_cap = True, + CapStruct_permit_store_cap = True, + CapStruct_permit_load_cap = True, + CapStruct_permit_store = True, + CapStruct_permit_load = True, + CapStruct_permit_execute = True, + CapStruct_global = True, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +definition null_cap_bits :: "(256)Word.word " where + " null_cap_bits = ( (capStructToMemBits256 null_cap :: 256 Word.word))" + + +(*val capStructToMemBits : CapStruct -> mword ty256*) + +definition capStructToMemBits :: " CapStruct \(256)Word.word " where + " capStructToMemBits cap = ( + (xor_vec ((capStructToMemBits256 cap :: 256 Word.word)) null_cap_bits :: 256 Word.word))" + + +(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*) + +definition memBitsToCapBits :: " bool \(256)Word.word \(257)Word.word " where + " memBitsToCapBits tag b = ( + (concat_vec ((bool_to_bits tag :: 1 Word.word)) ((xor_vec b null_cap_bits :: 256 Word.word)) + :: 257 Word.word))" + + +(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*) + +definition setCapPerms :: " CapStruct \(31)Word.word \ CapStruct " where + " setCapPerms cap perms = ( + (cap (| + CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_perm_reserved11_14 := + ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii) :: 4 Word.word)), CapStruct_access_system_regs := + ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal := + ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall := + ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal := + ((bit_to_bool ((access_vec_dec perms (( 7 :: int)::ii))))), CapStruct_permit_store_local_cap := + ((bit_to_bool ((access_vec_dec perms (( 6 :: int)::ii))))), CapStruct_permit_store_cap := + ((bit_to_bool ((access_vec_dec perms (( 5 :: int)::ii))))), CapStruct_permit_load_cap := + ((bit_to_bool ((access_vec_dec perms (( 4 :: int)::ii))))), CapStruct_permit_store := + ((bit_to_bool ((access_vec_dec perms (( 3 :: int)::ii))))), CapStruct_permit_load := + ((bit_to_bool ((access_vec_dec perms (( 2 :: int)::ii))))), CapStruct_permit_execute := + ((bit_to_bool ((access_vec_dec perms (( 1 :: int)::ii))))), CapStruct_global := + ((bit_to_bool ((access_vec_dec perms (( 0 :: int)::ii)))))|)))" + + +(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*) + +definition sealCap :: " CapStruct \(24)Word.word \ bool*CapStruct " where + " sealCap cap otype = ( (True, (cap (| CapStruct_sealed := True, CapStruct_otype := otype |))))" + + +(*val getCapTop : CapStruct -> integer*) + +definition getCapTop :: " CapStruct \ int " where + " getCapTop c = ( ((Word.uint(CapStruct_base c))) + ((Word.uint(CapStruct_length c))))" + + +(*val getCapOffset : CapStruct -> integer*) + +definition getCapOffset :: " CapStruct \ int " where + " getCapOffset c = ( + hardware_mod ((((Word.uint(CapStruct_address c))) - ((Word.uint(CapStruct_base c))))) + ((pow2 (( 64 :: int)::ii))))" + + +(*val getCapLength : CapStruct -> integer*) + +definition getCapLength :: " CapStruct \ int " where + " getCapLength c = ( Word.uint(CapStruct_length c))" + + +(*val getCapCursor : CapStruct -> integer*) + +definition getCapCursor :: " CapStruct \ int " where + " getCapCursor c = ( Word.uint(CapStruct_address c))" + + +(* +function{incCapOffset} is the same as function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). + *) +(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition incCapOffset :: " CapStruct \(64)Word.word \ bool*CapStruct " where + " incCapOffset c delta = ( + (let (newAddr :: 64 bits) = ((add_vec(CapStruct_address c) delta :: 64 Word.word)) in + (True, (c (| CapStruct_address := newAddr |)))))" + + +(* +Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. + *) +(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*) + +definition setCapBounds :: " CapStruct \(64)Word.word \(65)Word.word \ bool*CapStruct " where + " setCapBounds cap base top1 = ( + (let (length1 :: 65 bits) = + ((sub_vec top1 ((concat_vec (vec_of_bits [B0] :: 1 Word.word) base :: 65 Word.word)) :: 65 Word.word)) in + (True, + (cap (| + CapStruct_base := base, CapStruct_length := + ((subrange_vec_dec length1 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)), CapStruct_address := base |)))))" + + +(*val undefined_ast : unit -> M ast*) + +definition undefined_ast :: " unit \((register_value),(ast),(exception))monad " where + " undefined_ast _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__0 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__1 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__2 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__3 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__4 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__5 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__6 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__7 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__8 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__9 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__10 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__11 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__12 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__13 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__14 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__15 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__16 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__17 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__18 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__19 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__20 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__21 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__22 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__23 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__24 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__25 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__26 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__27 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__28 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__29 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__30 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__31 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__32 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__33 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__34 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__35 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__36 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__37 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__38 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__39 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__40 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__41 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__42 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__43 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__44 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__45 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__46 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__47 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__48 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__49 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__50 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__51 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__52 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__53 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__54 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__55 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__56 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__57 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__58 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__59 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__60 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__61 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__62 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__63 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__64 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__65 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__66 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__67 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__68 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__69 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__70 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__71 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__72 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__73 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__74 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__75 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__76 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__77 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__78 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__79 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__80 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__81 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__82 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__83 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__84 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__85 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__86 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__87 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__88 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__89 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__90 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__91 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__92 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__93 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__94 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__95 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__96 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__97 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__98 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__99 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__100 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__101 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__102 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__103 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__104 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__105 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__106 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__107 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__108 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__109 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__110 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__111 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__112 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__113 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__114 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__115 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__116 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__117 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__118 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__119 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__120 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__121 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__122 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__123 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__124 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__125 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__126 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__127 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__128 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__129 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__130 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__131 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__132 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__133 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__134 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__135 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__136 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__137 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__138 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__139 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__140 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__141 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__142 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__143 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__144 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__145 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__146 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__147 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__148 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__149 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__150 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__151 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__152 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \ (\ (w__153 :: 26 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \ (\ (w__154 :: 26 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__155 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__156 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__157 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__158 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__159 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__160 :: 16 Word.word) . + undefined_bool () \ (\ (w__161 :: bool) . + undefined_bool () \ (\ (w__162 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__163 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__164 :: 16 Word.word) . + undefined_Comparison () \ (\ (w__165 :: Comparison) . + undefined_bool () \ (\ (w__166 :: bool) . + undefined_bool () \ (\ (w__167 :: bool) . + (((((undefined_unit () \ + undefined_unit () ) \ + undefined_unit () ) \ + undefined_unit () ) \ + undefined_unit () ) \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__168 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__169 :: 5 Word.word) . + undefined_Comparison () \ (\ (w__170 :: Comparison) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__171 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__172 :: 16 Word.word) . + undefined_Comparison () \ (\ (w__173 :: Comparison) . + undefined_WordType () \ (\ (w__174 :: WordType) . + undefined_bool () \ (\ (w__175 :: bool) . + undefined_bool () \ (\ (w__176 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__177 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__178 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__179 :: 16 Word.word) . + undefined_WordType () \ (\ (w__180 :: WordType) . + undefined_bool () \ (\ (w__181 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__182 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__183 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__184 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__185 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__186 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__187 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__188 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__189 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__190 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__191 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__192 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__193 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__194 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__195 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__196 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__197 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__198 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__199 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__200 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__201 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__202 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__203 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__204 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__205 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__206 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__207 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__208 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__209 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__210 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__211 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__212 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__213 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__214 :: 16 Word.word) . + (undefined_unit () \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__215 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__216 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (w__217 :: 3 Word.word) . + undefined_bool () \ (\ (w__218 :: bool) . + (undefined_unit () \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__219 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__220 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (w__221 :: 3 Word.word) . + undefined_bool () \ (\ (w__222 :: bool) . + ((((undefined_unit () \ + undefined_unit () ) \ + undefined_unit () ) \ + undefined_unit () ) \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__223 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__224 :: 5 Word.word) . + (undefined_unit () \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__225 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__226 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__227 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__228 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__229 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__230 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__231 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__232 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__233 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__234 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__235 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__236 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__237 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__238 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__239 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__240 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__241 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__242 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__243 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__244 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__245 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__246 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__247 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__248 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__249 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__250 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__251 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__252 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__253 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__254 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__255 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__256 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__257 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__258 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__259 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__260 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__261 :: 5 Word.word) . + undefined_CPtrCmpOp () \ (\ (w__262 :: CPtrCmpOp) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__263 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__264 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__265 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__266 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__267 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (w__268 :: 11 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__269 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__270 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__271 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__272 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__273 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__274 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__275 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__276 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (w__277 :: 11 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__278 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__279 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__280 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__281 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__282 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__283 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__284 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__285 :: 5 Word.word) . + undefined_bool () \ (\ (w__286 :: bool) . + undefined_ClearRegSet () \ (\ (w__287 :: ClearRegSet) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__288 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__289 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__290 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__291 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__292 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__293 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__294 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__295 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__296 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__297 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__298 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__299 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__300 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__301 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__302 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__303 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__304 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__305 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__306 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__307 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__308 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__309 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__310 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__311 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__312 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__313 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__314 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__315 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (w__316 :: 11 Word.word) . + (undefined_unit () \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (w__317 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__318 :: 16 Word.word) . + undefined_bool () \ (\ (w__319 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__320 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__321 :: 16 Word.word) . + undefined_bool () \ (\ (w__322 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__323 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__324 :: 5 Word.word) . + undefined_bool () \ (\ (w__325 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__326 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__327 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__328 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__329 :: 8 Word.word) . + undefined_bool () \ (\ (w__330 :: bool) . + undefined_WordType () \ (\ (w__331 :: WordType) . + undefined_bool () \ (\ (w__332 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__333 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__334 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__335 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__336 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__337 :: 8 Word.word) . + undefined_WordType () \ (\ (w__338 :: WordType) . + undefined_bool () \ (\ (w__339 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__340 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__341 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__342 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__343 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (w__344 :: 11 Word.word) . + undefined_bool () \ (\ (w__345 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__346 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__347 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__348 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (w__349 :: 11 Word.word) . + undefined_bool () \ (\ (w__350 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__351 :: 5 Word.word) . + undefined_unit () \ + internal_pick + [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL (w__86,w__87,w__88),SLLV (w__89,w__90,w__91),SRA (w__92,w__93,w__94),SRAV (w__95,w__96,w__97),SRL (w__98,w__99,w__100),SRLV (w__101,w__102,w__103),SLT (w__104,w__105,w__106),SLTI (w__107,w__108,w__109),SLTU (w__110,w__111,w__112),SLTIU (w__113,w__114,w__115),MOVN (w__116,w__117,w__118),MOVZ (w__119,w__120,w__121),MFHI w__122,MFLO w__123,MTHI w__124,MTLO w__125,MUL (w__126,w__127,w__128),MULT (w__129,w__130),MULTU (w__131,w__132),DMULT (w__133,w__134),DMULTU (w__135,w__136),MADD (w__137,w__138),MADDU (w__139,w__140),MSUB (w__141,w__142),MSUBU (w__143,w__144),DIV (w__145,w__146),DIVU (w__147,w__148),DDIV (w__149,w__150),DDIVU (w__151,w__152),J w__153,JAL w__154,JR w__155,JALR (w__156,w__157),BEQ (w__158,w__159,w__160,w__161,w__162),BCMPZ (w__163,w__164,w__165,w__166,w__167),SYSCALL_THREAD_START () ,ImplementationDefinedStopFetching () ,SYSCALL () ,BREAK () ,WAIT () ,TRAPREG (w__168,w__169,w__170),TRAPIMM (w__171,w__172,w__173),Load (w__174,w__175,w__176,w__177,w__178,w__179),Store (w__180,w__181,w__182,w__183,w__184),LWL (w__185,w__186,w__187),LWR (w__188,w__189,w__190),SWL (w__191,w__192,w__193),SWR (w__194,w__195,w__196),LDL (w__197,w__198,w__199),LDR (w__200,w__201,w__202),SDL (w__203,w__204,w__205),SDR (w__206,w__207,w__208),CACHE (w__209,w__210,w__211),PREF (w__212,w__213,w__214),SYNC () ,MFC0 (w__215,w__216,w__217,w__218),HCF () ,MTC0 (w__219,w__220,w__221,w__222),TLBWI () ,TLBWR () ,TLBR () ,TLBP () ,RDHWR (w__223,w__224),ERET () ,CGetPerm (w__225,w__226),CGetType (w__227,w__228),CGetBase (w__229,w__230),CGetLen (w__231,w__232),CGetTag (w__233,w__234),CGetSealed (w__235,w__236),CGetOffset (w__237,w__238),CGetAddr (w__239,w__240),CGetPCC w__241,CGetPCCSetOffset (w__242,w__243),CGetCause w__244,CSetCause w__245,CReadHwr (w__246,w__247),CWriteHwr (w__248,w__249),CAndPerm (w__250,w__251,w__252),CToPtr (w__253,w__254,w__255),CSub (w__256,w__257,w__258),CPtrCmp (w__259,w__260,w__261,w__262),CIncOffset (w__263,w__264,w__265),CIncOffsetImmediate (w__266,w__267,w__268),CSetOffset (w__269,w__270,w__271),CSetBounds (w__272,w__273,w__274),CSetBoundsImmediate (w__275,w__276,w__277),CSetBoundsExact (w__278,w__279,w__280),CClearTag (w__281,w__282),CMOVX (w__283,w__284,w__285,w__286),ClearRegs (w__287,w__288),CFromPtr (w__289,w__290,w__291),CBuildCap (w__292,w__293,w__294),CCopyType (w__295,w__296,w__297),CCheckPerm (w__298,w__299),CCheckType (w__300,w__301),CTestSubset (w__302,w__303,w__304),CSeal (w__305,w__306,w__307),CCSeal (w__308,w__309,w__310),CUnseal (w__311,w__312,w__313),CCall (w__314,w__315,w__316),CReturn () ,CBX (w__317,w__318,w__319),CBZ (w__320,w__321,w__322),CJALR (w__323,w__324,w__325),CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332),CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339),CSC (w__340,w__341,w__342,w__343,w__344,w__345),CLC (w__346,w__347,w__348,w__349,w__350),C2Dump w__351,RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val execute : ast -> M unit*) + +(*val decode : mword ty32 -> maybe ast*) + +definition DDC :: "(5)Word.word " where + " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" + + +definition IDC :: "(5)Word.word " where + " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" + + +definition KR1C :: "(5)Word.word " where + " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" + + +definition KR2C :: "(5)Word.word " where + " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" + + +definition KCC :: "(5)Word.word " where + " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" + + +definition KDC :: "(5)Word.word " where + " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" + + +definition EPCC :: "(5)Word.word " where + " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" + + +definition CapRegs :: "(((regstate),(register_value),((257)Word.word))register_ref)list " where + " CapRegs = ( + [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref, + C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref, + C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])" + + +definition max_otype :: " int " where + " max_otype = ( MAX (( 24 :: int)::ii))" + + +definition have_cp2 :: " bool " where + " have_cp2 = ( True )" + + +(* +This function reads a given capability register and returns its contents converted to a CapStruct. +*) +(*val readCapReg : mword ty5 -> M CapStruct*) + +definition readCapReg :: "(5)Word.word \((register_value),(CapStruct),(exception))monad " where + " readCapReg n = ( + (let i = (Word.uint n) in + (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + :: ( 257 Word.word) M) \ (\ (w__0 :: 257 Word.word) . + return ((capRegToCapStruct w__0)))))" + + +(*val writeCapReg : mword ty5 -> CapStruct -> M unit*) + +definition writeCapReg :: "(5)Word.word \ CapStruct \((register_value),(unit),(exception))monad " where + " writeCapReg n cap = ( + (let i = (Word.uint n) in + write_reg + ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((capStructToCapReg cap :: 257 Word.word))))" + + +(*val CapEx_of_num : integer -> CapEx*) + +definition CapEx_of_num :: " int \ CapEx " where + " CapEx_of_num arg0 = ( + (let l__32 = arg0 in + if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None + else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation + else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation + else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation + else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation + else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap + else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap + else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow + else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation + else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap + else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds + else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation + else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation + else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation + else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation + else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation + else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation + else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation + else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation + else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation + else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation + else CapEx_PermitUnsealViolation))" + + +(*val num_of_CapEx : CapEx -> integer*) + +fun num_of_CapEx :: " CapEx \ int " where + " num_of_CapEx CapEx_None = ( (( 0 :: int)::ii))" +|" num_of_CapEx CapEx_LengthViolation = ( (( 1 :: int)::ii))" +|" num_of_CapEx CapEx_TagViolation = ( (( 2 :: int)::ii))" +|" num_of_CapEx CapEx_SealViolation = ( (( 3 :: int)::ii))" +|" num_of_CapEx CapEx_TypeViolation = ( (( 4 :: int)::ii))" +|" num_of_CapEx CapEx_CallTrap = ( (( 5 :: int)::ii))" +|" num_of_CapEx CapEx_ReturnTrap = ( (( 6 :: int)::ii))" +|" num_of_CapEx CapEx_TSSUnderFlow = ( (( 7 :: int)::ii))" +|" num_of_CapEx CapEx_UserDefViolation = ( (( 8 :: int)::ii))" +|" num_of_CapEx CapEx_TLBNoStoreCap = ( (( 9 :: int)::ii))" +|" num_of_CapEx CapEx_InexactBounds = ( (( 10 :: int)::ii))" +|" num_of_CapEx CapEx_GlobalViolation = ( (( 11 :: int)::ii))" +|" num_of_CapEx CapEx_PermitExecuteViolation = ( (( 12 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadViolation = ( (( 13 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreViolation = ( (( 14 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadCapViolation = ( (( 15 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreCapViolation = ( (( 16 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreLocalCapViolation = ( (( 17 :: int)::ii))" +|" num_of_CapEx CapEx_PermitSealViolation = ( (( 18 :: int)::ii))" +|" num_of_CapEx CapEx_AccessSystemRegsViolation = ( (( 19 :: int)::ii))" +|" num_of_CapEx CapEx_PermitCCallViolation = ( (( 20 :: int)::ii))" +|" num_of_CapEx CapEx_AccessCCallIDCViolation = ( (( 21 :: int)::ii))" +|" num_of_CapEx CapEx_PermitUnsealViolation = ( (( 22 :: int)::ii))" + + +(*val undefined_CapEx : unit -> M CapEx*) + +definition undefined_CapEx :: " unit \((register_value),(CapEx),(exception))monad " where + " undefined_CapEx _ = ( + internal_pick + [CapEx_None,CapEx_LengthViolation,CapEx_TagViolation,CapEx_SealViolation,CapEx_TypeViolation,CapEx_CallTrap,CapEx_ReturnTrap,CapEx_TSSUnderFlow,CapEx_UserDefViolation,CapEx_TLBNoStoreCap,CapEx_InexactBounds,CapEx_GlobalViolation,CapEx_PermitExecuteViolation,CapEx_PermitLoadViolation,CapEx_PermitStoreViolation,CapEx_PermitLoadCapViolation,CapEx_PermitStoreCapViolation,CapEx_PermitStoreLocalCapViolation,CapEx_PermitSealViolation,CapEx_AccessSystemRegsViolation,CapEx_PermitCCallViolation,CapEx_AccessCCallIDCViolation,CapEx_PermitUnsealViolation])" + + +(*val CapExCode : CapEx -> mword ty8*) + +fun CapExCode :: " CapEx \(8)Word.word " where + " CapExCode CapEx_None = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_LengthViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_TagViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_SealViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_TypeViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_CallTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_ReturnTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_TSSUnderFlow = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_UserDefViolation = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_TLBNoStoreCap = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_InexactBounds = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_GlobalViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitExecuteViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreLocalCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitSealViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessSystemRegsViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitCCallViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessCCallIDCViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitUnsealViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B1] :: 8 Word.word))" + + +(*val undefined_CapCauseReg : unit -> M CapCauseReg*) + +definition undefined_CapCauseReg :: " unit \((register_value),(CapCauseReg),(exception))monad " where + " undefined_CapCauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__0 :: 16 Word.word) . + internal_pick [Mk_CapCauseReg w__0]))" + + +fun get_CapCauseReg :: " CapCauseReg \(16)Word.word " where + " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )" + + +definition set_CapCauseReg :: "((regstate),(register_value),(CapCauseReg))register_ref \(16)Word.word \((register_value),(unit),(exception))monad " where + " set_CapCauseReg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_CapCauseReg v) in + write_reg r_ref r)))" + + +fun get_CapCauseReg_ExcCode :: " CapCauseReg \(8)Word.word " where + " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +definition set_CapCauseReg_ExcCode :: "((regstate),(register_value),(CapCauseReg))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_CapCauseReg_ExcCode r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +fun update_CapCauseReg_ExcCode :: " CapCauseReg \(8)Word.word \ CapCauseReg " where + " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 16 Word.word)))" + + +(*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) + +fun get_CapCauseReg_RegNum :: " CapCauseReg \(8)Word.word " where + " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +definition set_CapCauseReg_RegNum :: "((regstate),(register_value),(CapCauseReg))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_CapCauseReg_RegNum r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +(*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) + +fun update_CapCauseReg_RegNum :: " CapCauseReg \(8)Word.word \ CapCauseReg " where + " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 16 Word.word)))" + + +(*val execute_branch_pcc : CapStruct -> M unit*) + +definition execute_branch_pcc :: " CapStruct \((register_value),(unit),(exception))monad " where + " execute_branch_pcc newPCC = ( + (write_reg + delayedPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset newPCC)) :: 64 Word.word)) \ + write_reg delayedPCC_ref ((capStructToCapReg newPCC :: 257 Word.word))) \ + write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val ERETHook : unit -> M unit*) + +definition ERETHook :: " unit \((register_value),(unit),(exception))monad " where + " ERETHook _ = ( + (read_reg C31_ref :: ( 257 Word.word) M) \ (\ (w__0 :: CapReg) . + (write_reg nextPCC_ref w__0 \ + (read_reg C31_ref :: ( 257 Word.word) M)) \ (\ (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" + + +(*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) + +definition raise_c2_exception8 :: " CapEx \(8)Word.word \((register_value),'o,(exception))monad " where + " raise_c2_exception8 capEx regnum = ( + (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx :: 8 Word.word)) \ + set_CapCauseReg_RegNum CapCause_ref regnum) \ + ((let mipsEx = + (if ((((((capEx = CapEx_CallTrap))) \ (((capEx = CapEx_ReturnTrap)))))) then C2Trap + else C2E) in + SignalException mipsEx)))" + + +(*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*) + +definition raise_c2_exception :: " CapEx \(5)Word.word \((register_value),'o,(exception))monad " where + " raise_c2_exception capEx regnum = ( + (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) regnum :: 8 Word.word)) in + if ((((((capEx = CapEx_AccessSystemRegsViolation))) \ (((regnum = IDC)))))) then + raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 + else raise_c2_exception8 capEx reg8))" + + +(*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*) + +definition raise_c2_exception_noreg :: " CapEx \((register_value),'o,(exception))monad " where + " raise_c2_exception_noreg capEx = ( + raise_c2_exception8 capEx (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word))" + + +(*val pcc_access_system_regs : unit -> M bool*) + +definition pcc_access_system_regs :: " unit \((register_value),(bool),(exception))monad " where + " pcc_access_system_regs _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + return(CapStruct_access_system_regs pcc))))" + + +(* +The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. + *) +(*val register_inaccessible : mword ty5 -> M bool*) + +definition register_inaccessible :: "(5)Word.word \((register_value),(bool),(exception))monad " where + " register_inaccessible r = ( + or_boolM + (and_boolM (return (((r = IDC)))) + ((read_reg inCCallDelay_ref :: ( 1 Word.word) M) \ (\ (w__0 :: 1 Word.word) . + return ((bits_to_bool w__0))))) + (and_boolM + (return ((((((r = KR1C))) \ ((((((r = KR2C))) \ ((((((r = KDC))) \ ((((((r = KCC))) \ (((r = EPCC)))))))))))))))) + (pcc_access_system_regs () \ (\ (w__2 :: bool) . return ((\ w__2))))))" + + +(*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged :: "(64)Word.word \((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \ + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \ (\ tag . + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \ (\ data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged_reserve :: "(64)Word.word \((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged_reserve addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \ + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \ (\ tag . + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \ (\ data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) + +definition MEMw_tagged :: "(64)Word.word \ bool \(256)Word.word \((register_value),(unit),(exception))monad " where + " MEMw_tagged addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \ + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \ + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \ write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )" + + +(*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) + +definition MEMw_tagged_conditional :: "(64)Word.word \ bool \(256)Word.word \((register_value),(bool),(exception))monad " where + " MEMw_tagged_conditional addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \ + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \ + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \ (\ success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \ return success))" + + +definition cap_addr_mask :: "(64)Word.word " where + " cap_addr_mask = ( + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((((pow2 (( 64 :: int)::ii))) - cap_size)) + :: 64 Word.word))" + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MEMw_wrapper :: "(64)Word.word \ int \('p8_times_n_::len)Word.word \((register_value),(unit),(exception))monad " where + " MEMw_wrapper addr size1 data = ( + (let ledata = ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word)) in + if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + write_reg UART_WDATA_ref ((subrange_vec_dec ledata (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) \ + write_reg UART_WRITTEN_ref (vec_of_bits [B1] :: 1 Word.word) + else + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \ + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \ + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \ write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) + +definition MEMw_conditional_wrapper :: "(64)Word.word \ int \('p8_times_n_::len)Word.word \((register_value),(bool),(exception))monad " where + " MEMw_conditional_wrapper addr size1 data = ( + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \ + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \ + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \ (\ success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False + else return () ) \ + return success))" + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +definition addrWrapper :: "(64)Word.word \ MemAccessType \ WordType \((register_value),((64)Word.word),(exception))monad " where + " addrWrapper addr accessType width = ( + (let capno = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) in + readCapReg capno \ (\ cap . + ((if ((\(CapStruct_tag cap))) then raise_c2_exception CapEx_TagViolation capno + else if(CapStruct_sealed cap) then raise_c2_exception CapEx_SealViolation capno + else return () ) \ + (case accessType of + Instruction => + if ((\(CapStruct_permit_execute cap))) then + raise_c2_exception CapEx_PermitExecuteViolation capno + else return () + | LoadData => + if ((\(CapStruct_permit_load cap))) then raise_c2_exception CapEx_PermitLoadViolation capno + else return () + | StoreData => + if ((\(CapStruct_permit_store cap))) then raise_c2_exception CapEx_PermitStoreViolation capno + else return () + )) \ + ((let cursor = (getCapCursor cap) in + (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in + (let size1 = (wordWidthBytes width) in + (let base = (getCapBase cap) in + (let top1 = (getCapTop cap) in + if ((((vAddr + size1)) > top1)) then + (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))" + + +(*val TranslatePC : mword ty64 -> M (mword ty64)*) + +definition TranslatePC :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " TranslatePC vAddr = ( + (incrementCP0Count () \ + (read_reg PCC_ref :: ( 257 Word.word) M)) \ (\ (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + (let base = (getCapBase pcc) in + (let top1 = (getCapTop pcc) in + (let absPC = (base + ((Word.uint vAddr))) in + if (((((absPC mod (( 4 :: int)::ii))) \ (( 0 :: int)::ii)))) then + (SignalExceptionBadAddr AdEL + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + :: ( 64 Word.word) M) + else if ((\(CapStruct_tag pcc))) then + (raise_c2_exception_noreg CapEx_TagViolation :: ( 64 Word.word) M) + else if ((((absPC + (( 4 :: int)::ii))) > top1)) then + (raise_c2_exception_noreg CapEx_LengthViolation :: ( 64 Word.word) M) + else + (TLBTranslate ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + Instruction + :: ( 64 Word.word) M)))))))" + + +(* +All capability instrucitons must first check that the capability +co-processor is enabled using the following function that raises a +co-processor unusable exception if a CP0Status.CU2 is not set. This +allows the operating system to only save and restore the full +capability context for processes that use capabilities. +*) +(*val checkCP2usable : unit -> M unit*) + +definition checkCP2usable :: " unit \((register_value),(unit),(exception))monad " where + " checkCP2usable _ = ( + read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + if ((\ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 2 :: int)::ii))))))) then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1,B0] :: 2 Word.word) \ SignalException CpU + else return () ))" + + +definition init_cp2_state :: " unit \((register_value),(unit),(exception))monad " where + " init_cp2_state _ = ( + (let defaultBits = ((capStructToCapReg default_cap :: 257 Word.word)) in + ((write_reg PCC_ref defaultBits \ + write_reg nextPCC_ref defaultBits) \ + write_reg delayedPCC_ref defaultBits) \ + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) in + writeCapReg idx default_cap)))))" + + +definition cp2_next_pc :: " unit \((register_value),(unit),(exception))monad " where + " cp2_next_pc _ = ( + (read_reg nextPCC_ref :: ( 257 Word.word) M) \ (\ (w__0 :: CapReg) . + (write_reg PCC_ref w__0 \ + (read_reg inBranchDelay_ref :: ( 1 Word.word) M)) \ (\ (w__1 :: 1 Word.word) . + if ((bits_to_bool w__1)) then + (read_reg delayedPCC_ref :: ( 257 Word.word) M) \ (\ (w__2 :: CapReg) . + write_reg nextPCC_ref w__2) + else write_reg inCCallDelay_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val capToString : CapStruct -> M string*) + +definition capToString :: " CapStruct \((register_value),(string),(exception))monad " where + " capToString cap = ( + skip () \ + return (((op@) ('' t:'') + (((op@) (if(CapStruct_tag cap) then (''1'') else (''0'')) + (((op@) ('' s:'') + (((op@) (if(CapStruct_sealed cap) then (''1'') else (''0'')) + (((op@) ('' perms:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((getCapPerms cap :: 31 Word.word)) + :: 32 Word.word)))) + (((op@) ('' type:'') + (((op@) ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype cap))) + (((op@) ('' offset:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((getCapOffset cap)) + :: 64 Word.word)))) + (((op@) ('' base:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((getCapBase cap)) + :: 64 Word.word)))) + (((op@) ('' length:'') + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((min ((getCapLength cap)) + ((MAX (( 64 :: int)::ii))))) + :: 64 Word.word)))))))))))))))))))))))))))))))" + + +definition dump_cp2_state :: " unit \((register_value),(unit),(exception))monad " where + " dump_cp2_state _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__0 :: 257 Word.word) . + capToString ((capRegToCapStruct w__0)) \ (\ (w__1 :: string) . + (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) \ (\ (w__2 :: + CapStruct) . + capToString w__2 \ (\ (w__3 :: string) . + return ((let _ = + (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict i)) w__3))))) in + () ))))))))))" + + +(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) + +definition extendLoad :: "('sz::len)Word.word \ bool \(64)Word.word " where + " extendLoad memResult sign = ( + if sign then (sign_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word) + else (zero_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word))" + + +(*val TLBWriteEntry : mword ty6 -> M unit*) + +definition TLBWriteEntry :: "(6)Word.word \((register_value),(unit),(exception))monad " where + " TLBWriteEntry idx = ( + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \ (\ pagemask . + (let b__0 = pagemask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) + then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else SignalException MCheck) \ + ((let i = (Word.uint idx) in + (let entry = (access_list_dec TLBEntries i) in + (set_TLBEntry_pagemask entry pagemask \ + read_reg TLBEntryHi_ref) \ (\ (w__0 :: TLBEntryHiReg) . + (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 :: 2 Word.word)) \ + read_reg TLBEntryHi_ref) \ (\ (w__1 :: TLBEntryHiReg) . + (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 :: 27 Word.word)) \ + read_reg TLBEntryHi_ref) \ (\ (w__2 :: TLBEntryHiReg) . + (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 :: 8 Word.word)) \ + and_boolM + (read_reg TLBEntryLo0_ref \ (\ (w__3 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__3 :: 1 Word.word)))))) + (read_reg TLBEntryLo1_ref \ (\ (w__4 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__4 :: 1 Word.word))))))) \ (\ (w__5 :: bool) . + ((set_TLBEntry_g entry ((bool_to_bits w__5 :: 1 Word.word)) \ + set_TLBEntry_valid entry ((cast_unit_vec0 B1 :: 1 Word.word))) \ + read_reg TLBEntryLo0_ref) \ (\ (w__6 :: TLBEntryLoReg) . + (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 :: 1 Word.word)) \ + read_reg TLBEntryLo0_ref) \ (\ (w__7 :: TLBEntryLoReg) . + (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 :: 1 Word.word)) \ + read_reg TLBEntryLo0_ref) \ (\ (w__8 :: TLBEntryLoReg) . + (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 :: 24 Word.word)) \ + read_reg TLBEntryLo0_ref) \ (\ (w__9 :: TLBEntryLoReg) . + (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 :: 3 Word.word)) \ + read_reg TLBEntryLo0_ref) \ (\ (w__10 :: TLBEntryLoReg) . + (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 :: 1 Word.word)) \ + read_reg TLBEntryLo0_ref) \ (\ (w__11 :: TLBEntryLoReg) . + (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 :: 1 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__12 :: TLBEntryLoReg) . + (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 :: 1 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__13 :: TLBEntryLoReg) . + (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 :: 1 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__14 :: TLBEntryLoReg) . + (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 :: 24 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__15 :: TLBEntryLoReg) . + (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 :: 3 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__16 :: TLBEntryLoReg) . + (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 :: 1 Word.word)) \ + read_reg TLBEntryLo1_ref) \ (\ (w__17 :: TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 :: 1 Word.word))))))))))))))))))))))))" + + +definition decode :: "(32)Word.word \(ast)option " where + " decode v__0 = ( + if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADD (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADD (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (AND0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ANDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (OR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ORI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (NOR (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (XOR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (XORI (rs,rt,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LUI (rt,imm)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLT (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLTU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVN (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVZ (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFHI rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFLO rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTHI rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTLO rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADD (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADDU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUB (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUBU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIVU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIVU (rs,rt)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (J offset)) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (JAL offset)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 11 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 10 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (JR rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (JALR (rs,rd)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,True)))) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B0,B0,B1,B1,B0,B0] + :: 32 Word.word)))) then + Some (SYSCALL_THREAD_START () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + Some (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + Some (BREAK () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LTU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LTU)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (B,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (H,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CACHE (base,op1,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (PREF (base,op1,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + Some (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,True))))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B1,B0] + :: 32 Word.word)))) then + Some (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B1,B1,B0] + :: 32 Word.word)))) then + Some (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B1] + :: 32 Word.word)))) then + Some (TLBR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (RDHWR (rt,rd)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B1,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (ERET () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (CReturn () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCC cd1)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCCSetOffset (cd1,rs)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CReadHwr (cd1,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CWriteHwr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetAddr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBoundsExact (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CBuildCap (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCopyType (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSub (rt,cb,cs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CTestSubset (rd,cb,ct))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,True)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,True)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1] + :: 32 Word.word)))) then + Some (CReturn () ) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (selector :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CCall (cs,cb,selector))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CIncOffsetImmediate (cd1,cb,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B1,B0,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSetBoundsImmediate (cd1,cb,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,D,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),B,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),H,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),W,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),D,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSC (cs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSC (cs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 11 Word.word),True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CLC (cd1,cb,rt,offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 11 Word.word),True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (C2Dump rt)) + else Some (RI () ))" + + +(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_XORI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_XORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_XOR :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_XOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((xor_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_WAIT : unit -> M unit*) + +definition execute_WAIT :: " unit \((register_value),(unit),(exception))monad " where + " execute_WAIT g__121 = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . write_reg nextPC_ref w__0))" + + +(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) + +definition execute_TRAPREG :: "(5)Word.word \(5)Word.word \ Comparison \((register_value),(unit),(exception))monad " where + " execute_TRAPREG rs rt cmp = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + (let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) + +definition execute_TRAPIMM :: "(5)Word.word \(16)Word.word \ Comparison \((register_value),(unit),(exception))monad " where + " execute_TRAPIMM rs imm cmp = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TLBWR : unit -> M unit*) + +definition execute_TLBWR :: " unit \((register_value),(unit),(exception))monad " where + " execute_TLBWR g__125 = ( + (checkCP0Access () \ + (read_reg TLBRandom_ref :: ( 6 Word.word) M)) \ (\ (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBWI : unit -> M unit*) + +definition execute_TLBWI :: " unit \((register_value),(unit),(exception))monad " where + " execute_TLBWI g__124 = ( + (checkCP0Access () \ + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \ (\ (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBR : unit -> M unit*) + +definition execute_TLBR :: " unit \((register_value),(unit),(exception))monad " where + " execute_TLBR g__126 = ( + (checkCP0Access () \ + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \ (\ (w__0 :: TLBIndexT) . + (let i = (Word.uint w__0) in + reg_deref ((access_list_dec TLBEntries i)) \ (\ entry . + ((((((((((((((((write_reg TLBPageMask_ref ((get_TLBEntry_pagemask entry :: 16 Word.word)) \ + set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry :: 2 Word.word))) \ + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry :: 27 Word.word))) \ + set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry :: 8 Word.word))) \ + set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry :: 24 Word.word))) \ + set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry :: 3 Word.word))) \ + set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry :: 1 Word.word))) \ + set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry :: 24 Word.word))) \ + set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry :: 3 Word.word))) \ + set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry :: 1 Word.word))) \ + set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry :: 1 Word.word))))))" + + +(*val execute_TLBP : unit -> M unit*) + +definition execute_TLBP :: " unit \((register_value),(unit),(exception))monad " where + " execute_TLBP g__127 = ( + (checkCP0Access () \ + read_reg TLBEntryHi_ref) \ (\ (w__0 :: TLBEntryHiReg) . + (tlbSearch ((get_TLBEntryHiReg w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \ (\ result . + (case result of + Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] :: 1 Word.word) \ write_reg TLBIndex_ref idx + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg TLBIndex_ref (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word) + ))))" + + +(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Store :: " WordType \ bool \(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_Store width conditional base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData width + :: ( 64 Word.word) M) \ (\ (vAddr :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + if ((\ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val + ) + else return False) \ (\ (success :: bool) . + wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rt_val + ))))))" + + +(*val execute_SYSCALL_THREAD_START : unit -> unit*) + +definition execute_SYSCALL_THREAD_START :: " unit \ unit " where + " execute_SYSCALL_THREAD_START g__117 = ( () )" + + +(*val execute_SYSCALL : unit -> M unit*) + +definition execute_SYSCALL :: " unit \((register_value),(unit),(exception))monad " where + " execute_SYSCALL g__119 = ( SignalException Sys )" + + +(*val execute_SYNC : unit -> M unit*) + +definition execute_SYNC :: " unit \((register_value),(unit),(exception))monad " where + " execute_SYNC g__122 = ( MEM_sync () )" + + +(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWR :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__12 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__12 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__12 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__12 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))))))))" + + +(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWL :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__8 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__8 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__8 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + else if (((b__8 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUBU :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ opA . + (rGPR rt :: ( 64 Word.word) M) \ (\ opB . + if (((((NotWordVal opA)) \ ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUB :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ opA . + (rGPR rt :: ( 64 Word.word) M) \ (\ opB . + if (((((NotWordVal opA)) \ ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (temp33 :: 33 bits) = + ((sub_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRLV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRL :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRAV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRA :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLTU :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLTU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTIU :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLTIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLTI rs rt imm = ( + (let imm_val = (Word.sint imm) in + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs_val = (Word.sint w__0) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLT :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLT rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLLV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLLV rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLL :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDR :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) in + (let b__40 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__40 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + else MEMw_wrapper wordAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))))))" + + +(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDL :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_SDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__32 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__32 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_RI : unit -> M unit*) + +definition execute_RI :: " unit \((register_value),(unit),(exception))monad " where + " execute_RI g__130 = ( SignalException ResI )" + + +(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_RDHWR :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_RDHWR rt rd = ( + getAccessLevel () \ (\ accessLevel . + (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in + read_reg CP0Status_ref \ (\ (w__0 :: StatusReg) . + (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in + (let rdi = (Word.uint rd) in + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in + (if ((\ (((haveAccessLevel \ (((haveCU0 \ haveHWREna)))))))) then SignalException ResI + else return () ) \ + ((let b__146 = rd in + (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + return ((zero_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) + else (SignalException ResI :: ( 64 Word.word) M)) \ (\ (temp :: 64 bits) . + wGPR rt temp)))))))))))" + + +(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) + +definition execute_PREF :: "(5)Word.word \(5)Word.word \(16)Word.word \ unit " where + " execute_PREF base op1 imm = ( () )" + + +(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ORI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_ORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_OR :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_OR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((or_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_NOR :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_NOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 :: 64 Word.word)) :: 64 Word.word)))))" + + +(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULTU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULT :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MUL :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MUL rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (let (result :: 64 bits) = + ((sign_extend1 (( 64 :: int)::ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (w__1 :: 64 Word.word) . + wGPR rd w__1)))))" + + +(*val execute_MTLO : mword ty5 -> M unit*) + +definition execute_MTLO :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MTLO rs = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . write_reg LO_ref w__0))" + + +(*val execute_MTHI : mword ty5 -> M unit*) + +definition execute_MTHI :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MTHI rs = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . write_reg HI_ref w__0))" + + +(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MTC0 :: "(5)Word.word \(5)Word.word \(3)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_MTC0 rt rd sel double = ( + (checkCP0Access () \ + (rGPR rt :: ( 64 Word.word) M)) \ (\ reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBIndex_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \ (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo0_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \ (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo1_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 23 :: int):: ii) :: 41 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + write_reg CP0UserLocal_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBPageMask_ref + ((subrange_vec_dec reg_val (( 28 :: int):: ii) + (( 13 :: int):: ii) :: 16 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBWired_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) + \ write_reg TLBRandom_ref TLBIndexMax else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \ + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0HWREna_ref + ((concat_vec + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 29 :: int):: ii) :: 3 Word.word)) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0] :: 25 Word.word) + ((subrange_vec_dec reg_val (( 3 :: int):: ii) + (( 0 :: int):: ii) :: 4 Word.word)) + :: 29 Word.word)) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0Count_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 62 :: int):: ii) :: 2 Word.word)) \ + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 :: int):: ii) + (( 13 :: int):: ii) :: 27 Word.word))) + \ + set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 :: int):: ii) + (( 0 :: int):: ii) :: 8 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (write_reg CP0Compare_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) + \ read_reg CP0Cause_ref) \ + (\ (w__0 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec + ((get_CauseReg_IP w__0 :: 8 Word.word)) + (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) + :: 8 Word.word))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + ((((((((set_StatusReg_CU CP0Status_ref + ((subrange_vec_dec reg_val + (( 31 :: int):: ii) + (( 28 :: int):: ii) :: 4 Word.word)) + \ + set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 22 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_IM CP0Status_ref + ((subrange_vec_dec reg_val + (( 15 :: int):: ii) + (( 8 :: int):: ii) :: 8 Word.word))) + \ + set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 7 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 6 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 5 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_KSU CP0Status_ref + ((subrange_vec_dec reg_val + (( 4 :: int):: ii) + (( 3 :: int):: ii) :: 2 Word.word))) + \ + set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 2 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 1 :: int):: ii))) :: 1 Word.word))) + \ + set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 0 :: int):: ii))) :: 1 Word.word)) + else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 23 :: int):: ii))) :: 1 Word.word)) + \ read_reg CP0Cause_ref) \ + (\ (w__1 :: CauseReg) . + (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec + ((subrange_vec_dec ip + (( 7 :: int):: ii) + (( 2 :: int):: ii) :: 6 Word.word)) + ((subrange_vec_dec reg_val + (( 9 :: int):: ii) + (( 8 :: int):: ii) :: 2 Word.word)) + :: 8 Word.word)))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0EPC_ref reg_val else + if ((((((b__108 = + (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_XContextReg_XPTEBase + TLBXContext_ref + ((subrange_vec_dec reg_val + (( 63 :: int):: ii) + (( 33 :: int):: ii) :: 31 Word.word)) + else write_reg CP0ErrorEPC_ref reg_val + )))" + + +(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUBU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MSUBU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUB :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MSUB rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVZ :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MOVZ rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + if (((w__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVN :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MOVN rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + if (((w__0 \ (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MFLO : mword ty5 -> M unit*) + +definition execute_MFLO :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MFLO rd = ( + (read_reg LO_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFHI : mword ty5 -> M unit*) + +definition execute_MFHI :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MFHI rd = ( + (read_reg HI_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MFC0 :: "(5)Word.word \(5)Word.word \(3)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_MFC0 rt rd sel double = ( + (checkCP0Access () \ + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBIndex_ref :: ( 6 Word.word) M) \ + (\ (w__0 :: TLBIndexT) . + (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in + (read_reg TLBProbe_ref :: ( 1 Word.word) M) \ + (\ (w__1 :: 1 bits) . + return + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word) + ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word))))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \ + (\ (w__2 :: TLBIndexT) . + return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \ (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo0_ref \ + (\ (w__3 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \ (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo1_ref \ + (\ (w__4 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBContext_ref \ + (\ (w__5 :: ContextReg) . + return ((get_ContextReg w__5 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \ + (\ (w__7 :: 16 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((concat_vec w__7 + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 28 Word.word)) :: 64 Word.word))) else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBWired_ref :: ( 6 Word.word) M) \ + (\ (w__8 :: TLBIndexT) . + return + ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \ + (\ (w__9 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) + \ + (\ (w__11 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryHi_ref \ + (\ (w__12 :: TLBEntryHiReg) . + return + ((get_TLBEntryHiReg w__12 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Compare_ref :: ( 32 Word.word) M) + \ + (\ (w__13 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Status_ref \ + (\ (w__14 :: StatusReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Cause_ref \ + (\ (w__15 :: CauseReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0EPC_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) + ((concat_vec + (vec_of_bits + [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B1,B0] :: 2 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B1] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 16 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + TLBIndexMax + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + ( + bool_to_bits + have_cp2 :: 1 Word.word)) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + vec_of_bits + [B0] + :: 1 Word.word) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 16 Word.word)) + :: 19 Word.word)) + :: 22 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 16 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B1,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B1,B0,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B1] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B0] :: 5 Word.word)))) + \ + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B1] :: 5 Word.word)))) + \ + (((b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + ( + vec_of_bits + [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \ + ((( + b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + read_reg + TLBXContext_ref + \ + (\ (w__18 :: XContextReg) . + return + ((get_XContextReg + w__18 :: 64 Word.word))) + else + (read_reg + CP0ErrorEPC_ref :: ( 64 Word.word) M) + )) \ (\ (result :: 64 bits) . + wGPR rt + (if double then result + else + (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))" + + +(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADDU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MADDU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADD :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MADD rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \ (\ (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \ + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Load :: " WordType \ bool \ bool \(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_Load width sign linked base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + width + :: ( 64 Word.word) M) \ (\ (vAddr :: 64 bits) . + if ((\ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (if linked then + (write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (case width of + B => + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__1 :: 8 Word.word) . + return ((extendLoad w__1 sign :: 64 Word.word))) + | H => + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__2 :: 16 Word.word) . + return ((extendLoad w__2 sign :: 64 Word.word))) + | W => + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + return ((extendLoad w__3 sign :: 64 Word.word))) + | D => + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + return ((extendLoad w__4 sign :: 64 Word.word))) + ) + else + (case width of + B => + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__6 :: 8 Word.word) . + return ((extendLoad w__6 sign :: 64 Word.word))) + | H => + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__7 :: 16 Word.word) . + return ((extendLoad w__7 sign :: 64 Word.word))) + | W => + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + return ((extendLoad w__8 sign :: 64 Word.word))) + | D => + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__9 :: 64 Word.word) . + return ((extendLoad w__9 sign :: 64 Word.word))) + )) \ (\ (memResult :: 64 bits) . + wGPR rt memResult)))))" + + +(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWR :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_LWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \ (\ mem_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__4 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word) + else mem_val) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWL :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_LWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \ (\ mem_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__0 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word)) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) + +definition execute_LUI :: "(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_LUI rt imm = ( + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) + :: 32 Word.word)) + :: 64 Word.word)))" + + +(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDR :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_LDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \ (\ mem_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__24 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word) + else mem_val))))))))" + + +(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDL :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_LDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \ (\ vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \ (\ mem_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ reg_val . + (let b__16 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word)))))))))" + + +(*val execute_JR : mword ty5 -> M unit*) + +definition execute_JR :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_JR rs = ( (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . execute_branch w__0))" + + +(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_JALR :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_JALR rs rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (execute_branch w__0 \ + (read_reg PC_ref :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_JAL : mword ty26 -> M unit*) + +definition execute_JAL :: "(26)Word.word \((register_value),(unit),(exception))monad " where + " execute_JAL offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word)) \ + (read_reg PC_ref :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 Word.word) . + wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_J : mword ty26 -> M unit*) + +definition execute_J :: "(26)Word.word \((register_value),(unit),(exception))monad " where + " execute_J offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ImplementationDefinedStopFetching : unit -> unit*) + +definition execute_ImplementationDefinedStopFetching :: " unit \ unit " where + " execute_ImplementationDefinedStopFetching g__118 = ( () )" + + +(*val execute_HCF : unit -> unit*) + +definition execute_HCF :: " unit \ unit " where + " execute_HCF g__123 = ( () )" + + +(*val execute_ERET : unit -> M unit*) + +definition execute_ERET :: " unit \((register_value),(unit),(exception))monad " where + " execute_ERET g__128 = ( + (((checkCP0Access () \ + ERETHook () ) \ + write_reg CP0LLBit_ref (vec_of_bits [B0] :: 1 Word.word)) \ + read_reg CP0Status_ref) \ (\ (w__0 :: StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 :: 1 Word.word)))) = ((bit_to_bool B1))))) then + (read_reg CP0ErrorEPC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + write_reg nextPC_ref w__1 \ set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word)) + else + (read_reg CP0EPC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + write_reg nextPC_ref w__2 \ set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUBU :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((sub_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUB :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let (temp65 :: 65 bits) = + ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRLV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL32 :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRAV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA32 :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRA32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ temp . + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLLV :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSLLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + wGPR rd w__2))))" + + +(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL32 :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSLL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) + :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd w__1)))" + + +(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DSLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . wGPR rd w__1)))" + + +(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULTU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DMULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let result = ((mult_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \ + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULT :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DMULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let result = ((mults_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \ + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIVU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ (((((NotWordVal rtVal)) \ (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.uint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (hardware_mod si ti) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \ (\ varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \ + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIV :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ rsVal . + (rGPR rt :: ( 64 Word.word) M) \ (\ rtVal . + (if (((((NotWordVal rsVal)) \ (((((NotWordVal rtVal)) \ (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.sint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (si - ((ti * qi))) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \ (\ varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \ + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIVU :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DDIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rsVal = (Word.uint w__0) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rtVal = (Word.uint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (hardware_mod rsVal rtVal) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \ (\ varstup . (let (q, r) = varstup in + write_reg LO_ref q \ write_reg HI_ref r)))))))" + + +(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIV :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DDIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rsVal = (Word.sint w__0) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rtVal = (Word.sint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (rsVal - ((qi * rtVal))) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \ (\ varstup . (let (q, r) = varstup in + write_reg LO_ref q \ write_reg HI_ref r)))))))" + + +(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADDU :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((add_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDIU :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_DADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_DADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADD :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_DADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*) + +definition execute_ClearRegs :: " ClearRegSet \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_ClearRegs regset m = ( + ((if ((((((regset = CLo))) \ (((regset = CHi)))))) then checkCP2usable () + else return () ) \ + (if (((regset = CHi))) then + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + (let r = + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) :: 5 Word.word)) in + and_boolM (return ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r)) \ (\ (w__1 :: + bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r + else return () )))) + else return () )) \ + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + if ((bit_to_bool ((access_vec_dec m i)))) then + (case regset of + GPLo => + wGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) + ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | GPHi => + wGPR + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | CLo => + writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) null_cap + | CHi => + writeCapReg + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) null_cap + ) + else return () )))" + + +(*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CWriteHwr :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CWriteHwr cb sel = ( + checkCP2usable () \ + ((let l__24 = (Word.uint sel) in + (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \ (\ varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cb \ (\ (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \ (\ (w__9 :: bool) . return ((\ w__9)))) \ (\ (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \ (\ (w__11 :: AccessLevel) . + return ((\ ((grantsAccess w__11 Supervisor)))))) \ (\ (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + readCapReg cb \ (\ capVal . + (let l__16 = (Word.uint sel) in + if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal + else if (((l__16 = (( 1 :: int)::ii)))) then + write_reg CTLSU_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 8 :: int)::ii)))) then + write_reg CTLSP_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal + else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal + else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal + else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal + else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal + else assert_exp False (''should be unreachable code'')))))))))))" + + +(*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CUnseal :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CUnseal cd1 cs ct = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg ct \ (\ ct_val . + (let ct_cursor = (getCapCursor ct_val) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((\(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if (((ct_cursor \ ((Word.uint(CapStruct_otype cs_val)))))) then + raise_c2_exception CapEx_TypeViolation ct + else if ((\(CapStruct_permit_unseal ct_val))) then + raise_c2_exception CapEx_PermitUnsealViolation ct + else if ((ct_cursor < ((getCapBase ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \ ((getCapTop ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else + writeCapReg cd1 + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), CapStruct_global := + ((((CapStruct_global cs_val) \(CapStruct_global ct_val))))|)))))))))" + + +(*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CToPtr :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CToPtr rd cb ct = ( + (checkCP2usable () \ + readCapReg ct) \ (\ ct_val . + readCapReg cb \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((((CapStruct_tag cb_val) \(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let cbBase = (getCapBase cb_val) in + (let cbTop = (getCapTop cb_val) in + (let ctBase = (getCapBase ct_val) in + (let ctTop = (getCapTop ct_val) in + wGPR rd + (if (((((\(CapStruct_tag cb_val))) \ (((((cbBase < ctBase)) \ ((cbTop > ctTop)))))))) then + (zeros0 (( 64 :: int)::ii) () :: 64 Word.word) + else + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ctBase)) + :: 64 Word.word)))))))))))" + + +(*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CTestSubset :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CTestSubset rd cb ct = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + readCapReg ct \ (\ ct_val . + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + (let (result :: 1 bits) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_base < cb_base)) then (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_top > cb_top)) then (vec_of_bits [B0] :: 1 Word.word) + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \ ct_perms))) then + (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" + + +(*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSub :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSub rd cb ct = ( + (checkCP2usable () \ + readCapReg ct) \ (\ ct_val . + readCapReg cb \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) + :: 64 Word.word)))))))" + + +(*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*) + +definition execute_CStore :: "(5)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \(8)Word.word \ WordType \ bool \((register_value),(unit),(exception))monad " where + " execute_CStore rs cb rt rd offset width conditional = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else + (let size1 = (wordWidthBytes width) in + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + size1)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslate vAddr64 StoreData :: ( 64 Word.word) M) \ (\ pAddr . + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \ (\ (w__2 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__2 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val + ) + else return False) \ (\ (success :: bool) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rs_val + )))))))))))" + + +(*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetOffset :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSetOffset cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CSetCause : mword ty5 -> M unit*) + +definition execute_CSetCause :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSetCause rt = ( + (checkCP2usable () \ + pcc_access_system_regs () ) \ (\ (w__0 :: bool) . + if ((\ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) \ + set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))))" + + +(*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CSetBoundsImmediate :: "(5)Word.word \(5)Word.word \(11)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSetBoundsImmediate cd1 cb imm = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (let immU = (Word.uint imm) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + immU) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBoundsExact :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSetBoundsExact cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (exact, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + if ((\ exact)) then raise_c2_exception CapEx_InexactBounds cb + else writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBounds :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSetBounds cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSeal :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CSeal cd1 cs ct = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg ct \ (\ ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \ ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CSC :: "(5)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \(11)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CSC cs cb rt rd offset conditional = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg cb \ (\ cb_val . + register_inaccessible cs \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else if ((\(CapStruct_permit_store_cap cb_val))) then + raise_c2_exception CapEx_PermitStoreCapViolation cb + else if (((((\(CapStruct_permit_store_local_cap cb_val))) \ ((((CapStruct_tag cs_val) \ ((\(CapStruct_global cs_val))))))))) then + raise_c2_exception CapEx_PermitStoreLocalCapViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \ (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslateC vAddr64 StoreData :: (( 64 Word.word * bool)) M) \ (\ varstup . (let (pAddr, noStoreCap) = varstup in + if ((((CapStruct_tag cs_val) \ noStoreCap))) then + raise_c2_exception CapEx_TLBNoStoreCap cs + else if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \ (\ (w__3 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__3 (( 0 :: int)::ii))))) then + MEMw_tagged_conditional pAddr(CapStruct_tag cs_val) + ((capStructToMemBits cs_val :: 256 Word.word)) + else return False) \ (\ success . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else MEMw_tagged pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)))))))))))))" + + +(*val execute_CReturn : unit -> M unit*) + +definition execute_CReturn :: " unit \((register_value),(unit),(exception))monad " where + " execute_CReturn g__129 = ( checkCP2usable () \ raise_c2_exception_noreg CapEx_ReturnTrap )" + + +(*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CReadHwr :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CReadHwr cd1 sel = ( + checkCP2usable () \ + ((let l__8 = (Word.uint sel) in + (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \ (\ varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cd1 \ (\ (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \ (\ (w__9 :: bool) . return ((\ w__9)))) \ (\ (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \ (\ (w__11 :: AccessLevel) . + return ((\ ((grantsAccess w__11 Supervisor)))))) \ (\ (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + (let l__0 = (Word.uint sel) in + (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC + else if (((l__0 = (( 1 :: int)::ii)))) then + (read_reg CTLSU_ref :: ( 257 Word.word) M) \ (\ (w__14 :: 257 Word.word) . + return ((capRegToCapStruct w__14))) + else if (((l__0 = (( 8 :: int)::ii)))) then + (read_reg CTLSP_ref :: ( 257 Word.word) M) \ (\ (w__15 :: 257 Word.word) . + return ((capRegToCapStruct w__15))) + else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C + else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C + else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC + else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC + else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC + else assert_exp False (''should be unreachable code'') \ undefined_CapStruct () ) \ (\ (capVal :: + CapStruct) . + writeCapReg cd1 capVal))))))))))" + + +(*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*) + +definition execute_CPtrCmp :: "(5)Word.word \(5)Word.word \(5)Word.word \ CPtrCmpOp \((register_value),(unit),(exception))monad " where + " execute_CPtrCmp rd cb ct op1 = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + readCapReg cb \ (\ cb_val . + readCapReg ct \ (\ ct_val . + (let equal = False in + (let ltu = False in + (let lts = False in + (let ((equal :: bool), (lts :: bool), (ltu :: bool)) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (let ((lts :: bool), (ltu :: bool)) = + (if ((\(CapStruct_tag cb_val))) then + (let (ltu :: bool) = True in + (let (lts :: bool) = True in + (lts, ltu))) + else (lts, ltu)) in + (equal, lts, ltu)) + else + (let cursor1 = (getCapCursor cb_val) in + (let cursor2 = (getCapCursor ct_val) in + (let (equal :: bool) = (cursor1 = cursor2) in + (let (ltu :: bool) = (cursor1 < cursor2) in + (let (lts :: bool) = + (zopz0zI_s ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor1 :: 64 Word.word)) + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor2 :: 64 Word.word))) in + (equal, lts, ltu))))))) in + (let (cmp :: bool) = + ((case op1 of + CEQ => equal + | CNE => \ equal + | CLT => lts + | CLE => (lts \ equal) + | CLTU => ltu + | CLEU => (ltu \ equal) + | CEXEQ => (cb_val = ct_val) + | CNEXEQ => (cb_val \ ct_val) + )) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" + + +(*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CMOVX :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CMOVX cd1 cb rt ismovn = ( + (checkCP2usable () \ + register_inaccessible cd1) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec + ((bool_to_bits (((w__2 = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word))))) :: 1 Word.word)) + ((bool_to_bits ismovn :: 1 Word.word)) + :: 1 Word.word)))) then + readCapReg cb \ (\ (w__3 :: CapStruct) . writeCapReg cd1 w__3) + else return () ))))" + + +(*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*) + +definition execute_CLoad :: "(5)Word.word \(5)Word.word \(5)Word.word \(8)Word.word \ bool \ WordType \ bool \((register_value),(unit),(exception))monad " where + " execute_CLoad arg0 arg1 arg2 arg3 arg4 arg5 arg6 = ( + (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in + (case merge_var of + (rd, cb, rt, offset, signext, B, linked) => + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (w__2 :: 8 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__3 :: 8 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \ (\ (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, D, linked) => + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__2 :: 64 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \ (\ (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, H, linked) => + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (w__2 :: 16 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__3 :: 16 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \ (\ (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, W, linked) => + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cb \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\ ((isAddressAligned vAddr64 W)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \ (\ pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__2 :: 32 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \ (\ (memResult :: 64 bits) . + wGPR rd memResult)))))))) + )))" + + +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CLC :: "(5)Word.word \(5)Word.word \(5)Word.word \(11)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CLC cd1 cb rt offset linked = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \ (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslateC vAddr64 LoadData :: (( 64 Word.word * bool)) M) \ (\ varstup . (let (pAddr, suppressTag) = varstup in + (let cd1 = (Word.uint cd1) in + if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \ + write_reg CP0LLAddr_ref pAddr) \ + (MEMr_tagged_reserve pAddr :: ((bool * 256 Word.word)) M)) \ (\ varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \ ((((CapStruct_permit_load_cap cb_val) \ ((\ suppressTag)))))))) + mem + :: 257 Word.word)))) + else + (MEMr_tagged pAddr :: ((bool * 256 Word.word)) M) \ (\ varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \ ((((CapStruct_permit_load_cap cb_val) \ ((\ suppressTag)))))))) + mem + :: 257 Word.word)))))))))))))))" + + +(*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CJALR :: "(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CJALR cd1 cb link = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (let cb_ptr = (getCapCursor cb_val) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + and_boolM (return link) ((register_inaccessible cd1)) \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\(CapStruct_permit_execute cb_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then + raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \ (( 0 :: int)::ii)))) then SignalException AdEL + else + (if link then + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__3 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__3) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 :: int)::ii) :: 64 Word.word))) in + if success then writeCapReg cd1 linkCap + else assert_exp False (''''))))) + else return () ) \ + execute_branch_pcc cb_val)))))))" + + +(*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CIncOffsetImmediate :: "(5)Word.word \(5)Word.word \(11)Word.word \((register_value),(unit),(exception))monad " where + " execute_CIncOffsetImmediate cd1 cb imm = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val imm64) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) imm64 + :: 64 Word.word))))))))))" + + +(*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CIncOffset :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CIncOffset cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \ ((((CapStruct_sealed cb_val) \ (((rt_val \ (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetType :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetType rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + (if(CapStruct_sealed capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) + else (replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetTag :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetTag rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetSealed :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetSealed rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPerm :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetPerm rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPCCSetOffset :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetPCCSetOffset cd1 rs = ( + (checkCP2usable () \ + register_inaccessible cd1) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (rGPR rs :: ( 64 Word.word) M) \ (\ rs_val . + (let (success, newPCC) = (setCapOffset pcc rs_val) in + if success then writeCapReg cd1 newPCC + else writeCapReg cd1 ((int_to_cap rs_val))))))))" + + +(*val execute_CGetPCC : mword ty5 -> M unit*) + +definition execute_CGetPCC :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetPCC cd1 = ( + (checkCP2usable () \ + register_inaccessible cd1) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \ (\ (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (let (success, pcc2) = (setCapOffset pcc w__2) in + assert_exp success ('''') \ writeCapReg cd1 pcc2))))))" + + +(*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetOffset :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetOffset rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetLen :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetLen rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + (let len65 = (getCapLength capVal) in + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + (if ((len65 > MAX_U64)) then MAX_U64 + else len65) + :: 64 Word.word))))))" + + +(*val execute_CGetCause : mword ty5 -> M unit*) + +definition execute_CGetCause :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetCause rd = ( + (checkCP2usable () \ + pcc_access_system_regs () ) \ (\ (w__0 :: bool) . + if ((\ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + read_reg CapCause_ref \ (\ (w__1 :: CapCauseReg) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1 :: 16 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetBase :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetBase rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetAddr :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CGetAddr rd cb = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapCursor capVal)) :: 64 Word.word)))))" + + +(*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CFromPtr :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CFromPtr cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then writeCapReg cd1 null_cap + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCopyType :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CCopyType cd1 cb ct = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + readCapReg ct \ (\ ct_val . + (let cb_base = (getCapBase cb_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_otype = (Word.uint(CapStruct_otype ct_val)) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if(CapStruct_sealed ct_val) then + if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_otype \ cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (success, cap) = + (setCapOffset cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((ct_otype - cb_base)) + :: 64 Word.word))) in + assert_exp success ('''') \ writeCapReg cd1 cap) + else + writeCapReg cd1 + ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))))))" + + +(*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CClearTag :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CClearTag cd1 cb = ( + (checkCP2usable () \ + register_inaccessible cd1) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else readCapReg cb \ (\ cb_val . writeCapReg cd1 (cb_val (| CapStruct_tag := False |))))))" + + +(*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckType :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CCheckType cs cb = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg cb \ (\ cb_val . + register_inaccessible cs \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else return () )))))" + + +(*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckPerm :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CCheckPerm cs rt = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + (let (cs_perms :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_perms . + register_inaccessible cs \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((and_vec cs_perms rt_perms :: 64 Word.word)) \ rt_perms))) then + raise_c2_exception CapEx_UserDefViolation cs + else return () )))))" + + +(*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CCall :: "(5)Word.word \(5)Word.word \(11)Word.word \((register_value),(unit),(exception))monad " where + " execute_CCall cs cb b__151 = ( + if (((b__151 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg cb \ (\ cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \ ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else raise_c2_exception CapEx_CallTrap cs))))) + else + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg cb \ (\ cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \ (\ (w__3 :: bool) . + if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\(CapStruct_permit_ccall cs_val))) then + raise_c2_exception CapEx_PermitCCallViolation cs + else if ((\(CapStruct_permit_ccall cb_val))) then + raise_c2_exception CapEx_PermitCCallViolation cb + else if ((\(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \ ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else + (execute_branch_pcc + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) \ + write_reg inCCallDelay_ref (vec_of_bits [B1] :: 1 Word.word)) \ + write_reg + C26_ref + ((capStructToCapReg + (cb_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) + :: 257 Word.word))))))))" + + +(*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCSeal :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CCSeal cd1 cs ct = ( + (checkCP2usable () \ + readCapReg cs) \ (\ cs_val . + readCapReg ct \ (\ ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((\(CapStruct_tag ct_val))) \ (((((getCapCursor ct_val)) = ((Word.uint ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))) + then + writeCapReg cd1 cs_val + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \ ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CBuildCap :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CBuildCap cd1 cb ct = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + readCapReg ct \ (\ ct_val . + (let cb_base = (getCapBase cb_val) in + (let ct_base = (getCapBase ct_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_top = (getCapTop ct_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let ct_offset = (getCapOffset ct_val) in + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \ (\ (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \ ct_perms))) then + raise_c2_exception CapEx_UserDefViolation cb + else + (let (exact, cd11) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_base :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) ct_top :: 65 Word.word))) in + (let (representable, cd2) = + (setCapOffset cd11 + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_offset :: 64 Word.word))) in + (let cd3 = (setCapPerms cd2 ct_perms) in + (assert_exp exact ('''') \ assert_exp representable ('''')) \ writeCapReg cd1 cd3))))))))))))))))" + + +(*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBZ :: "(5)Word.word \(16)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CBZ cb imm notzero = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__1 = null_cap))) :: 1 Word.word)) + ((bool_to_bits notzero :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBX :: "(5)Word.word \(16)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_CBX cb imm notset = ( + (checkCP2usable () \ + register_inaccessible cb) \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \ (\ (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits(CapStruct_tag w__1) :: 1 Word.word)) + ((bool_to_bits notset :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CAndPerm :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_CAndPerm cd1 cb rt = ( + (checkCP2usable () \ + readCapReg cb) \ (\ cb_val . + (rGPR rt :: ( 64 Word.word) M) \ (\ rt_val . + register_inaccessible cd1 \ (\ (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \ (\ (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let newCap = + (setCapPerms cb_val + ((and_vec perms ((subrange_vec_dec rt_val (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) :: 31 Word.word))) in + writeCapReg cd1 newCap)))))))" + + +(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_CACHE :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_CACHE base op1 imm = ( checkCP0Access () )" + + +(*val execute_C2Dump : mword ty5 -> unit*) + +definition execute_C2Dump :: "(5)Word.word \ unit " where + " execute_C2Dump rt = ( () )" + + +(*val execute_BREAK : unit -> M unit*) + +definition execute_BREAK :: " unit \((register_value),(unit),(exception))monad " where + " execute_BREAK g__120 = ( SignalException Bp )" + + +(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) + +definition execute_BEQ :: "(5)Word.word \(5)Word.word \(16)Word.word \ bool \ bool \((register_value),(unit),(exception))monad " where + " execute_BEQ rs rd imm ne likely = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rd :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) :: 1 Word.word)) + ((bool_to_bits ne :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__3 (( 8 :: int)::ii) :: 64 Word.word))) + else return () )))" + + +(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) + +definition execute_BCMPZ :: "(5)Word.word \(16)Word.word \ Comparison \ bool \ bool \((register_value),(unit),(exception))monad " where + " execute_BCMPZ rs imm cmp link likely = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii) :: 64 Word.word)) in + (rGPR rs :: ( 64 Word.word) M) \ (\ regVal . + (let condition = + (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (if condition then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + execute_branch ((add_vec w__1 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__2 (( 8 :: int)::ii) :: 64 Word.word))) + else return () ) \ + (if link then wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) linkVal + else return () ))))))" + + +(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ANDI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_ANDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_AND :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_AND rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + wGPR rd ((and_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADDU :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_ADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ opA . + (rGPR rt :: ( 64 Word.word) M) \ (\ opB . + if (((((NotWordVal opA)) \ ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDIU :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_ADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rt w__0) + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((sign_extend1 (( 32 :: int)::ii) imm :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDI :: "(5)Word.word \(5)Word.word \(16)Word.word \((register_value),(unit),(exception))monad " where + " execute_ADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rt w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) imm :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + + +(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADD :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_ADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \ (\ (opA :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \ (\ (opB :: 64 bits) . + if (((((NotWordVal opA)) \ ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +fun execute :: " ast \((register_value),(unit),(exception))monad " where + " execute (DADDIU (rs,rt,imm)) = ( execute_DADDIU rs rt imm )" +|" execute (DADDU (rs,rt,rd)) = ( execute_DADDU rs rt rd )" +|" execute (DADDI (rs,rt,imm)) = ( execute_DADDI rs rt imm )" +|" execute (DADD (rs,rt,rd)) = ( execute_DADD rs rt rd )" +|" execute (ADD (rs,rt,rd)) = ( execute_ADD rs rt rd )" +|" execute (ADDI (rs,rt,imm)) = ( execute_ADDI rs rt imm )" +|" execute (ADDU (rs,rt,rd)) = ( execute_ADDU rs rt rd )" +|" execute (ADDIU (rs,rt,imm)) = ( execute_ADDIU rs rt imm )" +|" execute (DSUBU (rs,rt,rd)) = ( execute_DSUBU rs rt rd )" +|" execute (DSUB (rs,rt,rd)) = ( execute_DSUB rs rt rd )" +|" execute (SUB (rs,rt,rd)) = ( execute_SUB rs rt rd )" +|" execute (SUBU (rs,rt,rd)) = ( execute_SUBU rs rt rd )" +|" execute (AND0 (rs,rt,rd)) = ( execute_AND rs rt rd )" +|" execute (ANDI (rs,rt,imm)) = ( execute_ANDI rs rt imm )" +|" execute (OR0 (rs,rt,rd)) = ( execute_OR rs rt rd )" +|" execute (ORI (rs,rt,imm)) = ( execute_ORI rs rt imm )" +|" execute (NOR (rs,rt,rd)) = ( execute_NOR rs rt rd )" +|" execute (XOR0 (rs,rt,rd)) = ( execute_XOR rs rt rd )" +|" execute (XORI (rs,rt,imm)) = ( execute_XORI rs rt imm )" +|" execute (LUI (rt,imm)) = ( execute_LUI rt imm )" +|" execute (DSLL (rt,rd,sa)) = ( execute_DSLL rt rd sa )" +|" execute (DSLL32 (rt,rd,sa)) = ( execute_DSLL32 rt rd sa )" +|" execute (DSLLV (rs,rt,rd)) = ( execute_DSLLV rs rt rd )" +|" execute (DSRA (rt,rd,sa)) = ( execute_DSRA rt rd sa )" +|" execute (DSRA32 (rt,rd,sa)) = ( execute_DSRA32 rt rd sa )" +|" execute (DSRAV (rs,rt,rd)) = ( execute_DSRAV rs rt rd )" +|" execute (DSRL (rt,rd,sa)) = ( execute_DSRL rt rd sa )" +|" execute (DSRL32 (rt,rd,sa)) = ( execute_DSRL32 rt rd sa )" +|" execute (DSRLV (rs,rt,rd)) = ( execute_DSRLV rs rt rd )" +|" execute (SLL (rt,rd,sa)) = ( execute_SLL rt rd sa )" +|" execute (SLLV (rs,rt,rd)) = ( execute_SLLV rs rt rd )" +|" execute (SRA (rt,rd,sa)) = ( execute_SRA rt rd sa )" +|" execute (SRAV (rs,rt,rd)) = ( execute_SRAV rs rt rd )" +|" execute (SRL (rt,rd,sa)) = ( execute_SRL rt rd sa )" +|" execute (SRLV (rs,rt,rd)) = ( execute_SRLV rs rt rd )" +|" execute (SLT (rs,rt,rd)) = ( execute_SLT rs rt rd )" +|" execute (SLTI (rs,rt,imm)) = ( execute_SLTI rs rt imm )" +|" execute (SLTU (rs,rt,rd)) = ( execute_SLTU rs rt rd )" +|" execute (SLTIU (rs,rt,imm)) = ( execute_SLTIU rs rt imm )" +|" execute (MOVN (rs,rt,rd)) = ( execute_MOVN rs rt rd )" +|" execute (MOVZ (rs,rt,rd)) = ( execute_MOVZ rs rt rd )" +|" execute (MFHI (rd)) = ( execute_MFHI rd )" +|" execute (MFLO (rd)) = ( execute_MFLO rd )" +|" execute (MTHI (rs)) = ( execute_MTHI rs )" +|" execute (MTLO (rs)) = ( execute_MTLO rs )" +|" execute (MUL (rs,rt,rd)) = ( execute_MUL rs rt rd )" +|" execute (MULT (rs,rt)) = ( execute_MULT rs rt )" +|" execute (MULTU (rs,rt)) = ( execute_MULTU rs rt )" +|" execute (DMULT (rs,rt)) = ( execute_DMULT rs rt )" +|" execute (DMULTU (rs,rt)) = ( execute_DMULTU rs rt )" +|" execute (MADD (rs,rt)) = ( execute_MADD rs rt )" +|" execute (MADDU (rs,rt)) = ( execute_MADDU rs rt )" +|" execute (MSUB (rs,rt)) = ( execute_MSUB rs rt )" +|" execute (MSUBU (rs,rt)) = ( execute_MSUBU rs rt )" +|" execute (DIV (rs,rt)) = ( execute_DIV rs rt )" +|" execute (DIVU (rs,rt)) = ( execute_DIVU rs rt )" +|" execute (DDIV (rs,rt)) = ( execute_DDIV rs rt )" +|" execute (DDIVU (rs,rt)) = ( execute_DDIVU rs rt )" +|" execute (J (offset)) = ( execute_J offset )" +|" execute (JAL (offset)) = ( execute_JAL offset )" +|" execute (JR (rs)) = ( execute_JR rs )" +|" execute (JALR (rs,rd)) = ( execute_JALR rs rd )" +|" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )" +|" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )" +|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))" +|" execute (ImplementationDefinedStopFetching (g__118)) = ( + return ((execute_ImplementationDefinedStopFetching g__118)))" +|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )" +|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )" +|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )" +|" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )" +|" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )" +|" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )" +|" execute (Store (width,conditional,base,rt,offset)) = ( execute_Store width conditional base rt offset )" +|" execute (LWL (base,rt,offset)) = ( execute_LWL base rt offset )" +|" execute (LWR (base,rt,offset)) = ( execute_LWR base rt offset )" +|" execute (SWL (base,rt,offset)) = ( execute_SWL base rt offset )" +|" execute (SWR (base,rt,offset)) = ( execute_SWR base rt offset )" +|" execute (LDL (base,rt,offset)) = ( execute_LDL base rt offset )" +|" execute (LDR (base,rt,offset)) = ( execute_LDR base rt offset )" +|" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )" +|" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )" +|" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )" +|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))" +|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )" +|" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )" +|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))" +|" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )" +|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )" +|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )" +|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )" +|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )" +|" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )" +|" execute (ERET (g__128)) = ( execute_ERET g__128 )" +|" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )" +|" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )" +|" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )" +|" execute (CGetOffset (rd,cb)) = ( execute_CGetOffset rd cb )" +|" execute (CGetLen (rd,cb)) = ( execute_CGetLen rd cb )" +|" execute (CGetTag (rd,cb)) = ( execute_CGetTag rd cb )" +|" execute (CGetSealed (rd,cb)) = ( execute_CGetSealed rd cb )" +|" execute (CGetAddr (rd,cb)) = ( execute_CGetAddr rd cb )" +|" execute (CGetPCC (cd1)) = ( execute_CGetPCC cd1 )" +|" execute (CGetPCCSetOffset (cd1,rs)) = ( execute_CGetPCCSetOffset cd1 rs )" +|" execute (CGetCause (rd)) = ( execute_CGetCause rd )" +|" execute (CSetCause (rt)) = ( execute_CSetCause rt )" +|" execute (CReadHwr (cd1,sel)) = ( execute_CReadHwr cd1 sel )" +|" execute (CWriteHwr (cb,sel)) = ( execute_CWriteHwr cb sel )" +|" execute (CAndPerm (cd1,cb,rt)) = ( execute_CAndPerm cd1 cb rt )" +|" execute (CToPtr (rd,cb,ct)) = ( execute_CToPtr rd cb ct )" +|" execute (CSub (rd,cb,ct)) = ( execute_CSub rd cb ct )" +|" execute (CPtrCmp (rd,cb,ct,op1)) = ( execute_CPtrCmp rd cb ct op1 )" +|" execute (CIncOffset (cd1,cb,rt)) = ( execute_CIncOffset cd1 cb rt )" +|" execute (CIncOffsetImmediate (cd1,cb,imm)) = ( execute_CIncOffsetImmediate cd1 cb imm )" +|" execute (CSetOffset (cd1,cb,rt)) = ( execute_CSetOffset cd1 cb rt )" +|" execute (CSetBounds (cd1,cb,rt)) = ( execute_CSetBounds cd1 cb rt )" +|" execute (CSetBoundsImmediate (cd1,cb,imm)) = ( execute_CSetBoundsImmediate cd1 cb imm )" +|" execute (CSetBoundsExact (cd1,cb,rt)) = ( execute_CSetBoundsExact cd1 cb rt )" +|" execute (CClearTag (cd1,cb)) = ( execute_CClearTag cd1 cb )" +|" execute (CMOVX (cd1,cb,rt,ismovn)) = ( execute_CMOVX cd1 cb rt ismovn )" +|" execute (ClearRegs (regset,m)) = ( execute_ClearRegs regset m )" +|" execute (CFromPtr (cd1,cb,rt)) = ( execute_CFromPtr cd1 cb rt )" +|" execute (CBuildCap (cd1,cb,ct)) = ( execute_CBuildCap cd1 cb ct )" +|" execute (CCopyType (cd1,cb,ct)) = ( execute_CCopyType cd1 cb ct )" +|" execute (CCheckPerm (cs,rt)) = ( execute_CCheckPerm cs rt )" +|" execute (CCheckType (cs,cb)) = ( execute_CCheckType cs cb )" +|" execute (CTestSubset (rd,cb,ct)) = ( execute_CTestSubset rd cb ct )" +|" execute (CSeal (cd1,cs,ct)) = ( execute_CSeal cd1 cs ct )" +|" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )" +|" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )" +|" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )" +|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )" +|" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )" +|" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )" +|" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )" +|" execute (CLoad (rd,cb,rt,offset,signext,arg5,linked)) = ( + execute_CLoad rd cb rt offset signext arg5 linked )" +|" execute (CStore (rs,cb,rt,rd,offset,width,conditional)) = ( + execute_CStore rs cb rt rd offset width conditional )" +|" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )" +|" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )" +|" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))" +|" execute (RI (g__130)) = ( execute_RI g__130 )" + + +(*val supported_instructions : ast -> maybe ast*) + +definition supported_instructions :: " ast \(ast)option " where + " supported_instructions instr = ( Some instr )" + + +(*val fetch_and_execute : unit -> M unit*) + +definition fetch_and_execute :: " unit \((register_value),(unit),(exception))monad " where + " fetch_and_execute _ = ( + catch_early_return + (((whileM () + (\ unit_var . return True) + (\ unit_var . + liftR ((read_reg nextPC_ref :: ( 64 Word.word) M)) \ (\ (w__0 :: 64 bits) . + (liftR (write_reg PC_ref w__0) \ + liftR ((read_reg branchPending_ref :: ( 1 Word.word) M))) \ (\ (w__1 :: 1 bits) . + ((liftR (write_reg inBranchDelay_ref w__1) \ + liftR (write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word))) \ + liftR ((read_reg inBranchDelay_ref :: ( 1 Word.word) M))) \ (\ (w__2 :: 1 Word.word) . + (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref :: ( 64 Word.word) M)) + else + liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \ (\ (w__4 :: 64 Word.word) . + return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \ (\ (w__5 :: 64 Word.word) . + ((liftR (write_reg nextPC_ref w__5) \ + liftR (cp2_next_pc () )) \ + liftR (read_reg instCount_ref)) \ (\ (w__6 :: ii) . + (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \ + liftR ((read_reg PC_ref :: ( 64 Word.word) M))) \ (\ (w__7 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in + try_catchR (liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \ (\ (w__8 :: 64 Word.word) . + liftR ((TranslatePC w__8 :: ( 64 Word.word) M)) \ (\ pc_pa . + liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M)) \ (\ instr . + (let instr_ast = (decode instr) in + (case instr_ast of + Some ((HCF (_))) => + (let (_ :: unit) = + (prerr_endline (''simulation stopped due to halt instruction.'')) in + (early_return () :: (unit, unit) MR)) + | Some (ast) => liftR (execute ast) + | None => + (let (_ :: unit) = (prerr_endline (''Decode failed'')) in + liftR (exit0 () )) + )))))) (\x . + (case x of ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \ + liftR (skip () )) \ liftR (skip () )))" + + +(*val main : unit -> M unit*) + +(*val dump_mips_state : unit -> M unit*) + +definition dump_mips_state :: " unit \((register_value),(unit),(exception))monad " where + " dump_mips_state _ = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\ idx unit_var . + (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) idx :: 5 Word.word)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + return ((let _ = + (prerr_endline + (((op@) (''DEBUG MIPS REG '') + (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + () ))))))))" + + +definition main :: " unit \((register_value),(unit),(exception))monad " where + " main _ = ( + ((init_cp0_state () \ + init_cp2_state () ) \ + write_reg + nextPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word))) \ + ((let startTime = (get_time_ns () ) in + fetch_and_execute () \ + ((let endTime = (get_time_ns () ) in + (let elapsed = (endTime - startTime) in + read_reg instCount_ref \ (\ (w__0 :: ii) . + (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in + (let ips = (inst_1e9 div elapsed) in + ((dump_mips_state () \ + dump_cp2_state () ) \ + read_reg instCount_ref) \ (\ (w__1 :: ii) . + (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in + (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in + return ((print_int (''Instructions per second: '') ips))))))))))))))" + + +(*val initialize_registers : unit -> M unit*) + +definition initialize_registers :: " unit \((register_value),(unit),(exception))monad " where + " initialize_registers _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (write_reg PC_ref w__0 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 bits) . + (write_reg nextPC_ref w__1 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__2 :: 1 bits) . + (write_reg TLBProbe_ref w__2 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \ (\ (w__3 :: TLBIndexT) . + (write_reg TLBIndex_ref w__3 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \ (\ (w__4 :: TLBIndexT) . + (write_reg TLBRandom_ref w__4 \ + undefined_TLBEntryLoReg () ) \ (\ (w__5 :: TLBEntryLoReg) . + (write_reg TLBEntryLo0_ref w__5 \ + undefined_TLBEntryLoReg () ) \ (\ (w__6 :: TLBEntryLoReg) . + (write_reg TLBEntryLo1_ref w__6 \ + undefined_ContextReg () ) \ (\ (w__7 :: ContextReg) . + (write_reg TLBContext_ref w__7 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (w__8 :: 16 bits) . + (write_reg TLBPageMask_ref w__8 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \ (\ (w__9 :: TLBIndexT) . + (write_reg TLBWired_ref w__9 \ + undefined_TLBEntryHiReg () ) \ (\ (w__10 :: TLBEntryHiReg) . + (write_reg TLBEntryHi_ref w__10 \ + undefined_XContextReg () ) \ (\ (w__11 :: XContextReg) . + (write_reg TLBXContext_ref w__11 \ + undefined_TLBEntry () ) \ (\ (w__12 :: TLBEntry) . + (write_reg TLBEntry00_ref w__12 \ + undefined_TLBEntry () ) \ (\ (w__13 :: TLBEntry) . + (write_reg TLBEntry01_ref w__13 \ + undefined_TLBEntry () ) \ (\ (w__14 :: TLBEntry) . + (write_reg TLBEntry02_ref w__14 \ + undefined_TLBEntry () ) \ (\ (w__15 :: TLBEntry) . + (write_reg TLBEntry03_ref w__15 \ + undefined_TLBEntry () ) \ (\ (w__16 :: TLBEntry) . + (write_reg TLBEntry04_ref w__16 \ + undefined_TLBEntry () ) \ (\ (w__17 :: TLBEntry) . + (write_reg TLBEntry05_ref w__17 \ + undefined_TLBEntry () ) \ (\ (w__18 :: TLBEntry) . + (write_reg TLBEntry06_ref w__18 \ + undefined_TLBEntry () ) \ (\ (w__19 :: TLBEntry) . + (write_reg TLBEntry07_ref w__19 \ + undefined_TLBEntry () ) \ (\ (w__20 :: TLBEntry) . + (write_reg TLBEntry08_ref w__20 \ + undefined_TLBEntry () ) \ (\ (w__21 :: TLBEntry) . + (write_reg TLBEntry09_ref w__21 \ + undefined_TLBEntry () ) \ (\ (w__22 :: TLBEntry) . + (write_reg TLBEntry10_ref w__22 \ + undefined_TLBEntry () ) \ (\ (w__23 :: TLBEntry) . + (write_reg TLBEntry11_ref w__23 \ + undefined_TLBEntry () ) \ (\ (w__24 :: TLBEntry) . + (write_reg TLBEntry12_ref w__24 \ + undefined_TLBEntry () ) \ (\ (w__25 :: TLBEntry) . + (write_reg TLBEntry13_ref w__25 \ + undefined_TLBEntry () ) \ (\ (w__26 :: TLBEntry) . + (write_reg TLBEntry14_ref w__26 \ + undefined_TLBEntry () ) \ (\ (w__27 :: TLBEntry) . + (write_reg TLBEntry15_ref w__27 \ + undefined_TLBEntry () ) \ (\ (w__28 :: TLBEntry) . + (write_reg TLBEntry16_ref w__28 \ + undefined_TLBEntry () ) \ (\ (w__29 :: TLBEntry) . + (write_reg TLBEntry17_ref w__29 \ + undefined_TLBEntry () ) \ (\ (w__30 :: TLBEntry) . + (write_reg TLBEntry18_ref w__30 \ + undefined_TLBEntry () ) \ (\ (w__31 :: TLBEntry) . + (write_reg TLBEntry19_ref w__31 \ + undefined_TLBEntry () ) \ (\ (w__32 :: TLBEntry) . + (write_reg TLBEntry20_ref w__32 \ + undefined_TLBEntry () ) \ (\ (w__33 :: TLBEntry) . + (write_reg TLBEntry21_ref w__33 \ + undefined_TLBEntry () ) \ (\ (w__34 :: TLBEntry) . + (write_reg TLBEntry22_ref w__34 \ + undefined_TLBEntry () ) \ (\ (w__35 :: TLBEntry) . + (write_reg TLBEntry23_ref w__35 \ + undefined_TLBEntry () ) \ (\ (w__36 :: TLBEntry) . + (write_reg TLBEntry24_ref w__36 \ + undefined_TLBEntry () ) \ (\ (w__37 :: TLBEntry) . + (write_reg TLBEntry25_ref w__37 \ + undefined_TLBEntry () ) \ (\ (w__38 :: TLBEntry) . + (write_reg TLBEntry26_ref w__38 \ + undefined_TLBEntry () ) \ (\ (w__39 :: TLBEntry) . + (write_reg TLBEntry27_ref w__39 \ + undefined_TLBEntry () ) \ (\ (w__40 :: TLBEntry) . + (write_reg TLBEntry28_ref w__40 \ + undefined_TLBEntry () ) \ (\ (w__41 :: TLBEntry) . + (write_reg TLBEntry29_ref w__41 \ + undefined_TLBEntry () ) \ (\ (w__42 :: TLBEntry) . + (write_reg TLBEntry30_ref w__42 \ + undefined_TLBEntry () ) \ (\ (w__43 :: TLBEntry) . + (write_reg TLBEntry31_ref w__43 \ + undefined_TLBEntry () ) \ (\ (w__44 :: TLBEntry) . + (write_reg TLBEntry32_ref w__44 \ + undefined_TLBEntry () ) \ (\ (w__45 :: TLBEntry) . + (write_reg TLBEntry33_ref w__45 \ + undefined_TLBEntry () ) \ (\ (w__46 :: TLBEntry) . + (write_reg TLBEntry34_ref w__46 \ + undefined_TLBEntry () ) \ (\ (w__47 :: TLBEntry) . + (write_reg TLBEntry35_ref w__47 \ + undefined_TLBEntry () ) \ (\ (w__48 :: TLBEntry) . + (write_reg TLBEntry36_ref w__48 \ + undefined_TLBEntry () ) \ (\ (w__49 :: TLBEntry) . + (write_reg TLBEntry37_ref w__49 \ + undefined_TLBEntry () ) \ (\ (w__50 :: TLBEntry) . + (write_reg TLBEntry38_ref w__50 \ + undefined_TLBEntry () ) \ (\ (w__51 :: TLBEntry) . + (write_reg TLBEntry39_ref w__51 \ + undefined_TLBEntry () ) \ (\ (w__52 :: TLBEntry) . + (write_reg TLBEntry40_ref w__52 \ + undefined_TLBEntry () ) \ (\ (w__53 :: TLBEntry) . + (write_reg TLBEntry41_ref w__53 \ + undefined_TLBEntry () ) \ (\ (w__54 :: TLBEntry) . + (write_reg TLBEntry42_ref w__54 \ + undefined_TLBEntry () ) \ (\ (w__55 :: TLBEntry) . + (write_reg TLBEntry43_ref w__55 \ + undefined_TLBEntry () ) \ (\ (w__56 :: TLBEntry) . + (write_reg TLBEntry44_ref w__56 \ + undefined_TLBEntry () ) \ (\ (w__57 :: TLBEntry) . + (write_reg TLBEntry45_ref w__57 \ + undefined_TLBEntry () ) \ (\ (w__58 :: TLBEntry) . + (write_reg TLBEntry46_ref w__58 \ + undefined_TLBEntry () ) \ (\ (w__59 :: TLBEntry) . + (write_reg TLBEntry47_ref w__59 \ + undefined_TLBEntry () ) \ (\ (w__60 :: TLBEntry) . + (write_reg TLBEntry48_ref w__60 \ + undefined_TLBEntry () ) \ (\ (w__61 :: TLBEntry) . + (write_reg TLBEntry49_ref w__61 \ + undefined_TLBEntry () ) \ (\ (w__62 :: TLBEntry) . + (write_reg TLBEntry50_ref w__62 \ + undefined_TLBEntry () ) \ (\ (w__63 :: TLBEntry) . + (write_reg TLBEntry51_ref w__63 \ + undefined_TLBEntry () ) \ (\ (w__64 :: TLBEntry) . + (write_reg TLBEntry52_ref w__64 \ + undefined_TLBEntry () ) \ (\ (w__65 :: TLBEntry) . + (write_reg TLBEntry53_ref w__65 \ + undefined_TLBEntry () ) \ (\ (w__66 :: TLBEntry) . + (write_reg TLBEntry54_ref w__66 \ + undefined_TLBEntry () ) \ (\ (w__67 :: TLBEntry) . + (write_reg TLBEntry55_ref w__67 \ + undefined_TLBEntry () ) \ (\ (w__68 :: TLBEntry) . + (write_reg TLBEntry56_ref w__68 \ + undefined_TLBEntry () ) \ (\ (w__69 :: TLBEntry) . + (write_reg TLBEntry57_ref w__69 \ + undefined_TLBEntry () ) \ (\ (w__70 :: TLBEntry) . + (write_reg TLBEntry58_ref w__70 \ + undefined_TLBEntry () ) \ (\ (w__71 :: TLBEntry) . + (write_reg TLBEntry59_ref w__71 \ + undefined_TLBEntry () ) \ (\ (w__72 :: TLBEntry) . + (write_reg TLBEntry60_ref w__72 \ + undefined_TLBEntry () ) \ (\ (w__73 :: TLBEntry) . + (write_reg TLBEntry61_ref w__73 \ + undefined_TLBEntry () ) \ (\ (w__74 :: TLBEntry) . + (write_reg TLBEntry62_ref w__74 \ + undefined_TLBEntry () ) \ (\ (w__75 :: TLBEntry) . + (write_reg TLBEntry63_ref w__75 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__76 :: 32 bits) . + (write_reg CP0Compare_ref w__76 \ + undefined_CauseReg () ) \ (\ (w__77 :: CauseReg) . + (write_reg CP0Cause_ref w__77 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__78 :: 64 bits) . + (write_reg CP0EPC_ref w__78 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__79 :: 64 bits) . + (write_reg CP0ErrorEPC_ref w__79 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__80 :: 1 bits) . + (write_reg CP0LLBit_ref w__80 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__81 :: 64 bits) . + (write_reg CP0LLAddr_ref w__81 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__82 :: 64 bits) . + (write_reg CP0BadVAddr_ref w__82 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__83 :: 32 bits) . + (write_reg CP0Count_ref w__83 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__84 :: 32 bits) . + (write_reg CP0HWREna_ref w__84 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__85 :: 64 bits) . + (write_reg CP0UserLocal_ref w__85 \ + undefined_StatusReg () ) \ (\ (w__86 :: StatusReg) . + (write_reg CP0Status_ref w__86 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__87 :: 1 bits) . + (write_reg branchPending_ref w__87 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__88 :: 1 bits) . + (write_reg inBranchDelay_ref w__88 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__89 :: 64 bits) . + (write_reg delayedPC_ref w__89 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__90 :: 64 bits) . + (write_reg HI_ref w__90 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__91 :: 64 bits) . + (write_reg LO_ref w__91 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__92 :: 64 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__92 :: ( ( 64 Word.word)list) M) \ (\ (w__93 :: ( 64 bits) list) . + (write_reg GPR_ref w__93 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (w__94 :: 8 bits) . + (write_reg UART_WDATA_ref w__94 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__95 :: 1 bits) . + (write_reg UART_WRITTEN_ref w__95 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (w__96 :: 8 bits) . + (write_reg UART_RDATA_ref w__96 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__97 :: 1 bits) . + (write_reg UART_RVALID_ref w__97 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__98 :: CapReg) . + (write_reg PCC_ref w__98 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__99 :: CapReg) . + (write_reg nextPCC_ref w__99 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__100 :: CapReg) . + (write_reg delayedPCC_ref w__100 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__101 :: 1 bits) . + (write_reg inCCallDelay_ref w__101 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__102 :: CapReg) . + (write_reg C00_ref w__102 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__103 :: CapReg) . + (write_reg C01_ref w__103 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__104 :: CapReg) . + (write_reg C02_ref w__104 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__105 :: CapReg) . + (write_reg C03_ref w__105 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__106 :: CapReg) . + (write_reg C04_ref w__106 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__107 :: CapReg) . + (write_reg C05_ref w__107 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__108 :: CapReg) . + (write_reg C06_ref w__108 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__109 :: CapReg) . + (write_reg C07_ref w__109 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__110 :: CapReg) . + (write_reg C08_ref w__110 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__111 :: CapReg) . + (write_reg C09_ref w__111 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__112 :: CapReg) . + (write_reg C10_ref w__112 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__113 :: CapReg) . + (write_reg C11_ref w__113 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__114 :: CapReg) . + (write_reg C12_ref w__114 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__115 :: CapReg) . + (write_reg C13_ref w__115 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__116 :: CapReg) . + (write_reg C14_ref w__116 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__117 :: CapReg) . + (write_reg C15_ref w__117 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__118 :: CapReg) . + (write_reg C16_ref w__118 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__119 :: CapReg) . + (write_reg C17_ref w__119 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__120 :: CapReg) . + (write_reg C18_ref w__120 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__121 :: CapReg) . + (write_reg C19_ref w__121 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__122 :: CapReg) . + (write_reg C20_ref w__122 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__123 :: CapReg) . + (write_reg C21_ref w__123 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__124 :: CapReg) . + (write_reg C22_ref w__124 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__125 :: CapReg) . + (write_reg C23_ref w__125 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__126 :: CapReg) . + (write_reg C24_ref w__126 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__127 :: CapReg) . + (write_reg C25_ref w__127 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__128 :: CapReg) . + (write_reg C26_ref w__128 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__129 :: CapReg) . + (write_reg C27_ref w__129 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__130 :: CapReg) . + (write_reg C28_ref w__130 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__131 :: CapReg) . + (write_reg C29_ref w__131 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__132 :: CapReg) . + (write_reg C30_ref w__132 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__133 :: CapReg) . + (write_reg C31_ref w__133 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__134 :: CapReg) . + (write_reg CTLSU_ref w__134 \ + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \ (\ (w__135 :: CapReg) . + (write_reg CTLSP_ref w__135 \ + undefined_CapCauseReg () ) \ (\ (w__136 :: CapCauseReg) . + (write_reg CapCause_ref w__136 \ + undefined_int () ) \ (\ (w__137 :: ii) . write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| instCount = ((( 0 :: int)::ii)), + CapCause = + (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + CTLSP = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + CTLSU = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C31 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C30 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C29 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C28 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C27 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C26 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C25 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C24 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C23 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C22 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C21 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C20 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C19 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C18 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C17 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C16 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C15 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C14 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C13 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C12 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C11 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C10 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C09 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C08 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C07 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C06 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C05 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C04 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C03 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C02 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C01 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C00 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + inCCallDelay = ((vec_of_bits [B0] :: 1 Word.word)), + delayedPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + nextPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + PCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + UART_RVALID = ((vec_of_bits [B0] :: 1 Word.word)), + UART_RDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + UART_WRITTEN = ((vec_of_bits [B0] :: 1 Word.word)), + UART_WDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + GPR = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + LO = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + HI = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + delayedPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + inBranchDelay = ((vec_of_bits [B0] :: 1 Word.word)), + branchPending = ((vec_of_bits [B0] :: 1 Word.word)), + CP0Status = + (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0UserLocal = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0HWREna = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Count = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0BadVAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLBit = ((vec_of_bits [B0] :: 1 Word.word)), + CP0ErrorEPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0EPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0Cause = + (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Compare = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TLBEntry63 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry62 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry61 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry60 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry59 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry58 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry57 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry56 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry55 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry54 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry53 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry52 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry51 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry50 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry49 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry48 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry47 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry46 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry45 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry44 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry43 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry42 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry41 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry40 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry39 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry38 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry37 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry36 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry35 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry34 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry33 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry32 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry31 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry30 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry29 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry28 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry27 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry26 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry25 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry24 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry23 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry22 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry21 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry20 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry19 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry18 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry17 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry16 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry15 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry14 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry13 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry12 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry11 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry10 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry09 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry08 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry07 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry06 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry05 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry04 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry03 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry02 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry01 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry00 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBXContext = + (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryHi = + (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + TLBContext = + (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryLo1 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBEntryLo0 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBProbe = ((vec_of_bits [B0] :: 1 Word.word)), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/cheri/Cheri_lemmas.thy b/snapshots/isabelle/cheri/Cheri_lemmas.thy new file mode 100644 index 00000000..6dbee433 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_lemmas.thy @@ -0,0 +1,1205 @@ +theory Cheri_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Cheri +begin + +abbreviation "liftS \ liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def + CTLSP_ref_def CTLSU_ref_def C30_ref_def C28_ref_def C27_ref_def C26_ref_def C25_ref_def + C24_ref_def C23_ref_def C22_ref_def C21_ref_def C20_ref_def C19_ref_def C18_ref_def C17_ref_def + C16_ref_def C15_ref_def C14_ref_def C13_ref_def C12_ref_def C11_ref_def C10_ref_def C09_ref_def + C08_ref_def C07_ref_def C06_ref_def C05_ref_def C04_ref_def C03_ref_def C02_ref_def C01_ref_def + C00_ref_def inCCallDelay_ref_def nextPCC_ref_def delayedPCC_ref_def PCC_ref_def C31_ref_def + C29_ref_def UART_RVALID_ref_def UART_RDATA_ref_def UART_WRITTEN_ref_def UART_WDATA_ref_def + GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def inBranchDelay_ref_def branchPending_ref_def + CP0Status_ref_def CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def + CP0LLAddr_ref_def CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def + CP0Compare_ref_def TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def + TLBEntry59_ref_def TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def + TLBEntry54_ref_def TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def + TLBEntry49_ref_def TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def + TLBEntry44_ref_def TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def + TLBEntry39_ref_def TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def + TLBEntry34_ref_def TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def + TLBEntry29_ref_def TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def + TLBEntry24_ref_def TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def + TLBEntry19_ref_def TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def + TLBEntry14_ref_def TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def + TLBEntry09_ref_def TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def + TLBEntry04_ref_def TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def + TLBXContext_ref_def TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def + TLBEntryLo1_ref_def TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def + nextPC_ref_def PC_ref_def + +lemma regval_CapCauseReg[simp]: + "CapCauseReg_of_regval (regval_of_CapCauseReg v) = Some v" + by (auto simp: regval_of_CapCauseReg_def) + +lemma regval_CauseReg[simp]: + "CauseReg_of_regval (regval_of_CauseReg v) = Some v" + by (auto simp: regval_of_CauseReg_def) + +lemma regval_ContextReg[simp]: + "ContextReg_of_regval (regval_of_ContextReg v) = Some v" + by (auto simp: regval_of_ContextReg_def) + +lemma regval_StatusReg[simp]: + "StatusReg_of_regval (regval_of_StatusReg v) = Some v" + by (auto simp: regval_of_StatusReg_def) + +lemma regval_TLBEntry[simp]: + "TLBEntry_of_regval (regval_of_TLBEntry v) = Some v" + by (auto simp: regval_of_TLBEntry_def) + +lemma regval_TLBEntryHiReg[simp]: + "TLBEntryHiReg_of_regval (regval_of_TLBEntryHiReg v) = Some v" + by (auto simp: regval_of_TLBEntryHiReg_def) + +lemma regval_TLBEntryLoReg[simp]: + "TLBEntryLoReg_of_regval (regval_of_TLBEntryLoReg v) = Some v" + by (auto simp: regval_of_TLBEntryLoReg_def) + +lemma regval_XContextReg[simp]: + "XContextReg_of_regval (regval_of_XContextReg v) = Some v" + by (auto simp: regval_of_XContextReg_def) + +lemma regval_int[simp]: + "int_of_regval (regval_of_int v) = Some v" + by (auto simp: regval_of_int_def) + +lemma regval_vector_16_dec_bit[simp]: + "vector_16_dec_bit_of_regval (regval_of_vector_16_dec_bit v) = Some v" + by (auto simp: regval_of_vector_16_dec_bit_def) + +lemma regval_vector_1_dec_bit[simp]: + "vector_1_dec_bit_of_regval (regval_of_vector_1_dec_bit v) = Some v" + by (auto simp: regval_of_vector_1_dec_bit_def) + +lemma regval_vector_257_dec_bit[simp]: + "vector_257_dec_bit_of_regval (regval_of_vector_257_dec_bit v) = Some v" + by (auto simp: regval_of_vector_257_dec_bit_def) + +lemma regval_vector_32_dec_bit[simp]: + "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v" + by (auto simp: regval_of_vector_32_dec_bit_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma regval_vector_6_dec_bit[simp]: + "vector_6_dec_bit_of_regval (regval_of_vector_6_dec_bit v) = Some v" + by (auto simp: regval_of_vector_6_dec_bit_def) + +lemma regval_vector_8_dec_bit[simp]: + "vector_8_dec_bit_of_regval (regval_of_vector_8_dec_bit v) = Some v" + by (auto simp: regval_of_vector_8_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \ rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_instCount[simp]: + "liftS (read_reg instCount_ref) = readS (instCount \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_instCount[simp]: + "liftS (write_reg instCount_ref v) = updateS (regstate_update (instCount_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CapCause[simp]: + "liftS (read_reg CapCause_ref) = readS (CapCause \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CapCause[simp]: + "liftS (write_reg CapCause_ref v) = updateS (regstate_update (CapCause_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSP[simp]: + "liftS (read_reg CTLSP_ref) = readS (CTLSP \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSP[simp]: + "liftS (write_reg CTLSP_ref v) = updateS (regstate_update (CTLSP_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSU[simp]: + "liftS (read_reg CTLSU_ref) = readS (CTLSU \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSU[simp]: + "liftS (write_reg CTLSU_ref v) = updateS (regstate_update (CTLSU_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C30[simp]: + "liftS (read_reg C30_ref) = readS (C30 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C30[simp]: + "liftS (write_reg C30_ref v) = updateS (regstate_update (C30_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C28[simp]: + "liftS (read_reg C28_ref) = readS (C28 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C28[simp]: + "liftS (write_reg C28_ref v) = updateS (regstate_update (C28_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C27[simp]: + "liftS (read_reg C27_ref) = readS (C27 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C27[simp]: + "liftS (write_reg C27_ref v) = updateS (regstate_update (C27_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C26[simp]: + "liftS (read_reg C26_ref) = readS (C26 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C26[simp]: + "liftS (write_reg C26_ref v) = updateS (regstate_update (C26_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C25[simp]: + "liftS (read_reg C25_ref) = readS (C25 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C25[simp]: + "liftS (write_reg C25_ref v) = updateS (regstate_update (C25_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C24[simp]: + "liftS (read_reg C24_ref) = readS (C24 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C24[simp]: + "liftS (write_reg C24_ref v) = updateS (regstate_update (C24_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C23[simp]: + "liftS (read_reg C23_ref) = readS (C23 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C23[simp]: + "liftS (write_reg C23_ref v) = updateS (regstate_update (C23_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C22[simp]: + "liftS (read_reg C22_ref) = readS (C22 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C22[simp]: + "liftS (write_reg C22_ref v) = updateS (regstate_update (C22_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C21[simp]: + "liftS (read_reg C21_ref) = readS (C21 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C21[simp]: + "liftS (write_reg C21_ref v) = updateS (regstate_update (C21_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C20[simp]: + "liftS (read_reg C20_ref) = readS (C20 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C20[simp]: + "liftS (write_reg C20_ref v) = updateS (regstate_update (C20_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C19[simp]: + "liftS (read_reg C19_ref) = readS (C19 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C19[simp]: + "liftS (write_reg C19_ref v) = updateS (regstate_update (C19_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C18[simp]: + "liftS (read_reg C18_ref) = readS (C18 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C18[simp]: + "liftS (write_reg C18_ref v) = updateS (regstate_update (C18_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C17[simp]: + "liftS (read_reg C17_ref) = readS (C17 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C17[simp]: + "liftS (write_reg C17_ref v) = updateS (regstate_update (C17_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C16[simp]: + "liftS (read_reg C16_ref) = readS (C16 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C16[simp]: + "liftS (write_reg C16_ref v) = updateS (regstate_update (C16_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C15[simp]: + "liftS (read_reg C15_ref) = readS (C15 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C15[simp]: + "liftS (write_reg C15_ref v) = updateS (regstate_update (C15_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C14[simp]: + "liftS (read_reg C14_ref) = readS (C14 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C14[simp]: + "liftS (write_reg C14_ref v) = updateS (regstate_update (C14_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C13[simp]: + "liftS (read_reg C13_ref) = readS (C13 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C13[simp]: + "liftS (write_reg C13_ref v) = updateS (regstate_update (C13_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C12[simp]: + "liftS (read_reg C12_ref) = readS (C12 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C12[simp]: + "liftS (write_reg C12_ref v) = updateS (regstate_update (C12_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C11[simp]: + "liftS (read_reg C11_ref) = readS (C11 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C11[simp]: + "liftS (write_reg C11_ref v) = updateS (regstate_update (C11_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C10[simp]: + "liftS (read_reg C10_ref) = readS (C10 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C10[simp]: + "liftS (write_reg C10_ref v) = updateS (regstate_update (C10_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C09[simp]: + "liftS (read_reg C09_ref) = readS (C09 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C09[simp]: + "liftS (write_reg C09_ref v) = updateS (regstate_update (C09_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C08[simp]: + "liftS (read_reg C08_ref) = readS (C08 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C08[simp]: + "liftS (write_reg C08_ref v) = updateS (regstate_update (C08_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C07[simp]: + "liftS (read_reg C07_ref) = readS (C07 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C07[simp]: + "liftS (write_reg C07_ref v) = updateS (regstate_update (C07_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C06[simp]: + "liftS (read_reg C06_ref) = readS (C06 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C06[simp]: + "liftS (write_reg C06_ref v) = updateS (regstate_update (C06_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C05[simp]: + "liftS (read_reg C05_ref) = readS (C05 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C05[simp]: + "liftS (write_reg C05_ref v) = updateS (regstate_update (C05_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C04[simp]: + "liftS (read_reg C04_ref) = readS (C04 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C04[simp]: + "liftS (write_reg C04_ref v) = updateS (regstate_update (C04_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C03[simp]: + "liftS (read_reg C03_ref) = readS (C03 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C03[simp]: + "liftS (write_reg C03_ref v) = updateS (regstate_update (C03_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C02[simp]: + "liftS (read_reg C02_ref) = readS (C02 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C02[simp]: + "liftS (write_reg C02_ref v) = updateS (regstate_update (C02_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C01[simp]: + "liftS (read_reg C01_ref) = readS (C01 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C01[simp]: + "liftS (write_reg C01_ref v) = updateS (regstate_update (C01_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C00[simp]: + "liftS (read_reg C00_ref) = readS (C00 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C00[simp]: + "liftS (write_reg C00_ref v) = updateS (regstate_update (C00_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inCCallDelay[simp]: + "liftS (read_reg inCCallDelay_ref) = readS (inCCallDelay \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inCCallDelay[simp]: + "liftS (write_reg inCCallDelay_ref v) = updateS (regstate_update (inCCallDelay_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPCC[simp]: + "liftS (read_reg nextPCC_ref) = readS (nextPCC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPCC[simp]: + "liftS (write_reg nextPCC_ref v) = updateS (regstate_update (nextPCC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPCC[simp]: + "liftS (read_reg delayedPCC_ref) = readS (delayedPCC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPCC[simp]: + "liftS (write_reg delayedPCC_ref v) = updateS (regstate_update (delayedPCC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PCC[simp]: + "liftS (read_reg PCC_ref) = readS (PCC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PCC[simp]: + "liftS (write_reg PCC_ref v) = updateS (regstate_update (PCC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C31[simp]: + "liftS (read_reg C31_ref) = readS (C31 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C31[simp]: + "liftS (write_reg C31_ref v) = updateS (regstate_update (C31_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C29[simp]: + "liftS (read_reg C29_ref) = readS (C29 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C29[simp]: + "liftS (write_reg C29_ref v) = updateS (regstate_update (C29_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RVALID[simp]: + "liftS (read_reg UART_RVALID_ref) = readS (UART_RVALID \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RVALID[simp]: + "liftS (write_reg UART_RVALID_ref v) = updateS (regstate_update (UART_RVALID_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RDATA[simp]: + "liftS (read_reg UART_RDATA_ref) = readS (UART_RDATA \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RDATA[simp]: + "liftS (write_reg UART_RDATA_ref v) = updateS (regstate_update (UART_RDATA_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WRITTEN[simp]: + "liftS (read_reg UART_WRITTEN_ref) = readS (UART_WRITTEN \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WRITTEN[simp]: + "liftS (write_reg UART_WRITTEN_ref v) = updateS (regstate_update (UART_WRITTEN_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WDATA[simp]: + "liftS (read_reg UART_WDATA_ref) = readS (UART_WDATA \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WDATA[simp]: + "liftS (write_reg UART_WDATA_ref v) = updateS (regstate_update (UART_WDATA_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_GPR[simp]: + "liftS (read_reg GPR_ref) = readS (GPR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_GPR[simp]: + "liftS (write_reg GPR_ref v) = updateS (regstate_update (GPR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_LO[simp]: + "liftS (read_reg LO_ref) = readS (LO \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_LO[simp]: + "liftS (write_reg LO_ref v) = updateS (regstate_update (LO_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HI[simp]: + "liftS (read_reg HI_ref) = readS (HI \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HI[simp]: + "liftS (write_reg HI_ref v) = updateS (regstate_update (HI_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPC[simp]: + "liftS (read_reg delayedPC_ref) = readS (delayedPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPC[simp]: + "liftS (write_reg delayedPC_ref v) = updateS (regstate_update (delayedPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inBranchDelay[simp]: + "liftS (read_reg inBranchDelay_ref) = readS (inBranchDelay \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inBranchDelay[simp]: + "liftS (write_reg inBranchDelay_ref v) = updateS (regstate_update (inBranchDelay_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_branchPending[simp]: + "liftS (read_reg branchPending_ref) = readS (branchPending \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_branchPending[simp]: + "liftS (write_reg branchPending_ref v) = updateS (regstate_update (branchPending_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Status[simp]: + "liftS (read_reg CP0Status_ref) = readS (CP0Status \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Status[simp]: + "liftS (write_reg CP0Status_ref v) = updateS (regstate_update (CP0Status_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0UserLocal[simp]: + "liftS (read_reg CP0UserLocal_ref) = readS (CP0UserLocal \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0UserLocal[simp]: + "liftS (write_reg CP0UserLocal_ref v) = updateS (regstate_update (CP0UserLocal_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0HWREna[simp]: + "liftS (read_reg CP0HWREna_ref) = readS (CP0HWREna \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0HWREna[simp]: + "liftS (write_reg CP0HWREna_ref v) = updateS (regstate_update (CP0HWREna_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Count[simp]: + "liftS (read_reg CP0Count_ref) = readS (CP0Count \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Count[simp]: + "liftS (write_reg CP0Count_ref v) = updateS (regstate_update (CP0Count_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0BadVAddr[simp]: + "liftS (read_reg CP0BadVAddr_ref) = readS (CP0BadVAddr \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0BadVAddr[simp]: + "liftS (write_reg CP0BadVAddr_ref v) = updateS (regstate_update (CP0BadVAddr_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLAddr[simp]: + "liftS (read_reg CP0LLAddr_ref) = readS (CP0LLAddr \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLAddr[simp]: + "liftS (write_reg CP0LLAddr_ref v) = updateS (regstate_update (CP0LLAddr_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLBit[simp]: + "liftS (read_reg CP0LLBit_ref) = readS (CP0LLBit \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLBit[simp]: + "liftS (write_reg CP0LLBit_ref v) = updateS (regstate_update (CP0LLBit_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0ErrorEPC[simp]: + "liftS (read_reg CP0ErrorEPC_ref) = readS (CP0ErrorEPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0ErrorEPC[simp]: + "liftS (write_reg CP0ErrorEPC_ref v) = updateS (regstate_update (CP0ErrorEPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0EPC[simp]: + "liftS (read_reg CP0EPC_ref) = readS (CP0EPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0EPC[simp]: + "liftS (write_reg CP0EPC_ref v) = updateS (regstate_update (CP0EPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Cause[simp]: + "liftS (read_reg CP0Cause_ref) = readS (CP0Cause \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Cause[simp]: + "liftS (write_reg CP0Cause_ref v) = updateS (regstate_update (CP0Cause_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Compare[simp]: + "liftS (read_reg CP0Compare_ref) = readS (CP0Compare \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Compare[simp]: + "liftS (write_reg CP0Compare_ref v) = updateS (regstate_update (CP0Compare_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry63[simp]: + "liftS (read_reg TLBEntry63_ref) = readS (TLBEntry63 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry63[simp]: + "liftS (write_reg TLBEntry63_ref v) = updateS (regstate_update (TLBEntry63_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry62[simp]: + "liftS (read_reg TLBEntry62_ref) = readS (TLBEntry62 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry62[simp]: + "liftS (write_reg TLBEntry62_ref v) = updateS (regstate_update (TLBEntry62_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry61[simp]: + "liftS (read_reg TLBEntry61_ref) = readS (TLBEntry61 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry61[simp]: + "liftS (write_reg TLBEntry61_ref v) = updateS (regstate_update (TLBEntry61_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry60[simp]: + "liftS (read_reg TLBEntry60_ref) = readS (TLBEntry60 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry60[simp]: + "liftS (write_reg TLBEntry60_ref v) = updateS (regstate_update (TLBEntry60_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry59[simp]: + "liftS (read_reg TLBEntry59_ref) = readS (TLBEntry59 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry59[simp]: + "liftS (write_reg TLBEntry59_ref v) = updateS (regstate_update (TLBEntry59_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry58[simp]: + "liftS (read_reg TLBEntry58_ref) = readS (TLBEntry58 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry58[simp]: + "liftS (write_reg TLBEntry58_ref v) = updateS (regstate_update (TLBEntry58_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry57[simp]: + "liftS (read_reg TLBEntry57_ref) = readS (TLBEntry57 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry57[simp]: + "liftS (write_reg TLBEntry57_ref v) = updateS (regstate_update (TLBEntry57_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry56[simp]: + "liftS (read_reg TLBEntry56_ref) = readS (TLBEntry56 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry56[simp]: + "liftS (write_reg TLBEntry56_ref v) = updateS (regstate_update (TLBEntry56_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry55[simp]: + "liftS (read_reg TLBEntry55_ref) = readS (TLBEntry55 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry55[simp]: + "liftS (write_reg TLBEntry55_ref v) = updateS (regstate_update (TLBEntry55_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry54[simp]: + "liftS (read_reg TLBEntry54_ref) = readS (TLBEntry54 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry54[simp]: + "liftS (write_reg TLBEntry54_ref v) = updateS (regstate_update (TLBEntry54_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry53[simp]: + "liftS (read_reg TLBEntry53_ref) = readS (TLBEntry53 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry53[simp]: + "liftS (write_reg TLBEntry53_ref v) = updateS (regstate_update (TLBEntry53_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry52[simp]: + "liftS (read_reg TLBEntry52_ref) = readS (TLBEntry52 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry52[simp]: + "liftS (write_reg TLBEntry52_ref v) = updateS (regstate_update (TLBEntry52_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry51[simp]: + "liftS (read_reg TLBEntry51_ref) = readS (TLBEntry51 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry51[simp]: + "liftS (write_reg TLBEntry51_ref v) = updateS (regstate_update (TLBEntry51_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry50[simp]: + "liftS (read_reg TLBEntry50_ref) = readS (TLBEntry50 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry50[simp]: + "liftS (write_reg TLBEntry50_ref v) = updateS (regstate_update (TLBEntry50_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry49[simp]: + "liftS (read_reg TLBEntry49_ref) = readS (TLBEntry49 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry49[simp]: + "liftS (write_reg TLBEntry49_ref v) = updateS (regstate_update (TLBEntry49_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry48[simp]: + "liftS (read_reg TLBEntry48_ref) = readS (TLBEntry48 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry48[simp]: + "liftS (write_reg TLBEntry48_ref v) = updateS (regstate_update (TLBEntry48_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry47[simp]: + "liftS (read_reg TLBEntry47_ref) = readS (TLBEntry47 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry47[simp]: + "liftS (write_reg TLBEntry47_ref v) = updateS (regstate_update (TLBEntry47_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry46[simp]: + "liftS (read_reg TLBEntry46_ref) = readS (TLBEntry46 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry46[simp]: + "liftS (write_reg TLBEntry46_ref v) = updateS (regstate_update (TLBEntry46_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry45[simp]: + "liftS (read_reg TLBEntry45_ref) = readS (TLBEntry45 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry45[simp]: + "liftS (write_reg TLBEntry45_ref v) = updateS (regstate_update (TLBEntry45_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry44[simp]: + "liftS (read_reg TLBEntry44_ref) = readS (TLBEntry44 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry44[simp]: + "liftS (write_reg TLBEntry44_ref v) = updateS (regstate_update (TLBEntry44_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry43[simp]: + "liftS (read_reg TLBEntry43_ref) = readS (TLBEntry43 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry43[simp]: + "liftS (write_reg TLBEntry43_ref v) = updateS (regstate_update (TLBEntry43_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry42[simp]: + "liftS (read_reg TLBEntry42_ref) = readS (TLBEntry42 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry42[simp]: + "liftS (write_reg TLBEntry42_ref v) = updateS (regstate_update (TLBEntry42_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry41[simp]: + "liftS (read_reg TLBEntry41_ref) = readS (TLBEntry41 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry41[simp]: + "liftS (write_reg TLBEntry41_ref v) = updateS (regstate_update (TLBEntry41_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry40[simp]: + "liftS (read_reg TLBEntry40_ref) = readS (TLBEntry40 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry40[simp]: + "liftS (write_reg TLBEntry40_ref v) = updateS (regstate_update (TLBEntry40_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry39[simp]: + "liftS (read_reg TLBEntry39_ref) = readS (TLBEntry39 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry39[simp]: + "liftS (write_reg TLBEntry39_ref v) = updateS (regstate_update (TLBEntry39_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry38[simp]: + "liftS (read_reg TLBEntry38_ref) = readS (TLBEntry38 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry38[simp]: + "liftS (write_reg TLBEntry38_ref v) = updateS (regstate_update (TLBEntry38_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry37[simp]: + "liftS (read_reg TLBEntry37_ref) = readS (TLBEntry37 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry37[simp]: + "liftS (write_reg TLBEntry37_ref v) = updateS (regstate_update (TLBEntry37_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry36[simp]: + "liftS (read_reg TLBEntry36_ref) = readS (TLBEntry36 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry36[simp]: + "liftS (write_reg TLBEntry36_ref v) = updateS (regstate_update (TLBEntry36_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry35[simp]: + "liftS (read_reg TLBEntry35_ref) = readS (TLBEntry35 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry35[simp]: + "liftS (write_reg TLBEntry35_ref v) = updateS (regstate_update (TLBEntry35_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry34[simp]: + "liftS (read_reg TLBEntry34_ref) = readS (TLBEntry34 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry34[simp]: + "liftS (write_reg TLBEntry34_ref v) = updateS (regstate_update (TLBEntry34_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry33[simp]: + "liftS (read_reg TLBEntry33_ref) = readS (TLBEntry33 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry33[simp]: + "liftS (write_reg TLBEntry33_ref v) = updateS (regstate_update (TLBEntry33_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry32[simp]: + "liftS (read_reg TLBEntry32_ref) = readS (TLBEntry32 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry32[simp]: + "liftS (write_reg TLBEntry32_ref v) = updateS (regstate_update (TLBEntry32_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry31[simp]: + "liftS (read_reg TLBEntry31_ref) = readS (TLBEntry31 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry31[simp]: + "liftS (write_reg TLBEntry31_ref v) = updateS (regstate_update (TLBEntry31_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry30[simp]: + "liftS (read_reg TLBEntry30_ref) = readS (TLBEntry30 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry30[simp]: + "liftS (write_reg TLBEntry30_ref v) = updateS (regstate_update (TLBEntry30_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry29[simp]: + "liftS (read_reg TLBEntry29_ref) = readS (TLBEntry29 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry29[simp]: + "liftS (write_reg TLBEntry29_ref v) = updateS (regstate_update (TLBEntry29_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry28[simp]: + "liftS (read_reg TLBEntry28_ref) = readS (TLBEntry28 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry28[simp]: + "liftS (write_reg TLBEntry28_ref v) = updateS (regstate_update (TLBEntry28_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry27[simp]: + "liftS (read_reg TLBEntry27_ref) = readS (TLBEntry27 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry27[simp]: + "liftS (write_reg TLBEntry27_ref v) = updateS (regstate_update (TLBEntry27_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry26[simp]: + "liftS (read_reg TLBEntry26_ref) = readS (TLBEntry26 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry26[simp]: + "liftS (write_reg TLBEntry26_ref v) = updateS (regstate_update (TLBEntry26_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry25[simp]: + "liftS (read_reg TLBEntry25_ref) = readS (TLBEntry25 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry25[simp]: + "liftS (write_reg TLBEntry25_ref v) = updateS (regstate_update (TLBEntry25_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry24[simp]: + "liftS (read_reg TLBEntry24_ref) = readS (TLBEntry24 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry24[simp]: + "liftS (write_reg TLBEntry24_ref v) = updateS (regstate_update (TLBEntry24_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry23[simp]: + "liftS (read_reg TLBEntry23_ref) = readS (TLBEntry23 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry23[simp]: + "liftS (write_reg TLBEntry23_ref v) = updateS (regstate_update (TLBEntry23_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry22[simp]: + "liftS (read_reg TLBEntry22_ref) = readS (TLBEntry22 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry22[simp]: + "liftS (write_reg TLBEntry22_ref v) = updateS (regstate_update (TLBEntry22_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry21[simp]: + "liftS (read_reg TLBEntry21_ref) = readS (TLBEntry21 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry21[simp]: + "liftS (write_reg TLBEntry21_ref v) = updateS (regstate_update (TLBEntry21_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry20[simp]: + "liftS (read_reg TLBEntry20_ref) = readS (TLBEntry20 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry20[simp]: + "liftS (write_reg TLBEntry20_ref v) = updateS (regstate_update (TLBEntry20_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry19[simp]: + "liftS (read_reg TLBEntry19_ref) = readS (TLBEntry19 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry19[simp]: + "liftS (write_reg TLBEntry19_ref v) = updateS (regstate_update (TLBEntry19_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry18[simp]: + "liftS (read_reg TLBEntry18_ref) = readS (TLBEntry18 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry18[simp]: + "liftS (write_reg TLBEntry18_ref v) = updateS (regstate_update (TLBEntry18_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry17[simp]: + "liftS (read_reg TLBEntry17_ref) = readS (TLBEntry17 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry17[simp]: + "liftS (write_reg TLBEntry17_ref v) = updateS (regstate_update (TLBEntry17_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry16[simp]: + "liftS (read_reg TLBEntry16_ref) = readS (TLBEntry16 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry16[simp]: + "liftS (write_reg TLBEntry16_ref v) = updateS (regstate_update (TLBEntry16_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry15[simp]: + "liftS (read_reg TLBEntry15_ref) = readS (TLBEntry15 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry15[simp]: + "liftS (write_reg TLBEntry15_ref v) = updateS (regstate_update (TLBEntry15_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry14[simp]: + "liftS (read_reg TLBEntry14_ref) = readS (TLBEntry14 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry14[simp]: + "liftS (write_reg TLBEntry14_ref v) = updateS (regstate_update (TLBEntry14_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry13[simp]: + "liftS (read_reg TLBEntry13_ref) = readS (TLBEntry13 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry13[simp]: + "liftS (write_reg TLBEntry13_ref v) = updateS (regstate_update (TLBEntry13_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry12[simp]: + "liftS (read_reg TLBEntry12_ref) = readS (TLBEntry12 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry12[simp]: + "liftS (write_reg TLBEntry12_ref v) = updateS (regstate_update (TLBEntry12_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry11[simp]: + "liftS (read_reg TLBEntry11_ref) = readS (TLBEntry11 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry11[simp]: + "liftS (write_reg TLBEntry11_ref v) = updateS (regstate_update (TLBEntry11_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry10[simp]: + "liftS (read_reg TLBEntry10_ref) = readS (TLBEntry10 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry10[simp]: + "liftS (write_reg TLBEntry10_ref v) = updateS (regstate_update (TLBEntry10_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry09[simp]: + "liftS (read_reg TLBEntry09_ref) = readS (TLBEntry09 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry09[simp]: + "liftS (write_reg TLBEntry09_ref v) = updateS (regstate_update (TLBEntry09_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry08[simp]: + "liftS (read_reg TLBEntry08_ref) = readS (TLBEntry08 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry08[simp]: + "liftS (write_reg TLBEntry08_ref v) = updateS (regstate_update (TLBEntry08_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry07[simp]: + "liftS (read_reg TLBEntry07_ref) = readS (TLBEntry07 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry07[simp]: + "liftS (write_reg TLBEntry07_ref v) = updateS (regstate_update (TLBEntry07_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry06[simp]: + "liftS (read_reg TLBEntry06_ref) = readS (TLBEntry06 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry06[simp]: + "liftS (write_reg TLBEntry06_ref v) = updateS (regstate_update (TLBEntry06_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry05[simp]: + "liftS (read_reg TLBEntry05_ref) = readS (TLBEntry05 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry05[simp]: + "liftS (write_reg TLBEntry05_ref v) = updateS (regstate_update (TLBEntry05_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry04[simp]: + "liftS (read_reg TLBEntry04_ref) = readS (TLBEntry04 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry04[simp]: + "liftS (write_reg TLBEntry04_ref v) = updateS (regstate_update (TLBEntry04_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry03[simp]: + "liftS (read_reg TLBEntry03_ref) = readS (TLBEntry03 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry03[simp]: + "liftS (write_reg TLBEntry03_ref v) = updateS (regstate_update (TLBEntry03_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry02[simp]: + "liftS (read_reg TLBEntry02_ref) = readS (TLBEntry02 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry02[simp]: + "liftS (write_reg TLBEntry02_ref v) = updateS (regstate_update (TLBEntry02_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry01[simp]: + "liftS (read_reg TLBEntry01_ref) = readS (TLBEntry01 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry01[simp]: + "liftS (write_reg TLBEntry01_ref v) = updateS (regstate_update (TLBEntry01_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry00[simp]: + "liftS (read_reg TLBEntry00_ref) = readS (TLBEntry00 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry00[simp]: + "liftS (write_reg TLBEntry00_ref v) = updateS (regstate_update (TLBEntry00_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBXContext[simp]: + "liftS (read_reg TLBXContext_ref) = readS (TLBXContext \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBXContext[simp]: + "liftS (write_reg TLBXContext_ref v) = updateS (regstate_update (TLBXContext_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryHi[simp]: + "liftS (read_reg TLBEntryHi_ref) = readS (TLBEntryHi \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryHi[simp]: + "liftS (write_reg TLBEntryHi_ref v) = updateS (regstate_update (TLBEntryHi_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBWired[simp]: + "liftS (read_reg TLBWired_ref) = readS (TLBWired \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBWired[simp]: + "liftS (write_reg TLBWired_ref v) = updateS (regstate_update (TLBWired_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBPageMask[simp]: + "liftS (read_reg TLBPageMask_ref) = readS (TLBPageMask \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBPageMask[simp]: + "liftS (write_reg TLBPageMask_ref v) = updateS (regstate_update (TLBPageMask_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBContext[simp]: + "liftS (read_reg TLBContext_ref) = readS (TLBContext \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBContext[simp]: + "liftS (write_reg TLBContext_ref v) = updateS (regstate_update (TLBContext_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo1[simp]: + "liftS (read_reg TLBEntryLo1_ref) = readS (TLBEntryLo1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo1[simp]: + "liftS (write_reg TLBEntryLo1_ref v) = updateS (regstate_update (TLBEntryLo1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo0[simp]: + "liftS (read_reg TLBEntryLo0_ref) = readS (TLBEntryLo0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo0[simp]: + "liftS (write_reg TLBEntryLo0_ref v) = updateS (regstate_update (TLBEntryLo0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBRandom[simp]: + "liftS (read_reg TLBRandom_ref) = readS (TLBRandom \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBRandom[simp]: + "liftS (write_reg TLBRandom_ref v) = updateS (regstate_update (TLBRandom_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBIndex[simp]: + "liftS (read_reg TLBIndex_ref) = readS (TLBIndex \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBIndex[simp]: + "liftS (write_reg TLBIndex_ref v) = updateS (regstate_update (TLBIndex_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBProbe[simp]: + "liftS (read_reg TLBProbe_ref) = readS (TLBProbe \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBProbe[simp]: + "liftS (write_reg TLBProbe_ref v) = updateS (regstate_update (TLBProbe_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/cheri/Cheri_types.thy b/snapshots/isabelle/cheri/Cheri_types.thy new file mode 100644 index 00000000..4139164a --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_types.thy @@ -0,0 +1,2432 @@ +chapter \Generated by Lem from cheri_types.lem.\ + +theory "Cheri_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +datatype exception = + ISAException " (unit)" + | Error_not_implemented " (string)" + | Error_misaligned_access " (unit)" + | Error_EBREAK " (unit)" + | Error_internal_error " (unit)" + + + +datatype CauseReg = Mk_CauseReg " ( 32 Word.word)" + + + +datatype CapCauseReg = Mk_CapCauseReg " ( 16 Word.word)" + + + +datatype TLBEntryLoReg = Mk_TLBEntryLoReg " ( 64 Word.word)" + + + +datatype TLBEntryHiReg = Mk_TLBEntryHiReg " ( 64 Word.word)" + + + +datatype ContextReg = Mk_ContextReg " ( 64 Word.word)" + + + +datatype XContextReg = Mk_XContextReg " ( 64 Word.word)" + + + +type_synonym TLBIndexT =" 6 bits " + +datatype TLBEntry = Mk_TLBEntry " ( 117 Word.word)" + + + +datatype StatusReg = Mk_StatusReg " ( 32 Word.word)" + + + +datatype Exception = + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck + + + +type_synonym CapReg =" 257 bits " + +record CapStruct = + + CapStruct_tag ::" bool " + + CapStruct_padding ::" 8 bits " + + CapStruct_otype ::" 24 bits " + + CapStruct_uperms ::" 16 bits " + + CapStruct_perm_reserved11_14 ::" 4 bits " + + CapStruct_access_system_regs ::" bool " + + CapStruct_permit_unseal ::" bool " + + CapStruct_permit_ccall ::" bool " + + CapStruct_permit_seal ::" bool " + + CapStruct_permit_store_local_cap ::" bool " + + CapStruct_permit_store_cap ::" bool " + + CapStruct_permit_load_cap ::" bool " + + CapStruct_permit_store ::" bool " + + CapStruct_permit_load ::" bool " + + CapStruct_permit_execute ::" bool " + + CapStruct_global ::" bool " + + CapStruct_sealed ::" bool " + + CapStruct_address ::" 64 bits " + + CapStruct_base ::" 64 bits " + + CapStruct_length ::" 64 bits " + + + +datatype MemAccessType = Instruction | LoadData | StoreData + + + +datatype AccessLevel = User | Supervisor | Kernel + + + +type_synonym regno =" 5 bits " + +type_synonym imm16 =" 16 bits " + +type_synonym regregreg =" (regno * regno * regno)" + +type_synonym regregimm16 =" (regno * regno * imm16)" + +datatype decode_failure = + No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error + + + +datatype Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU + + + +datatype WordType = B | H | W | D + + + +type_synonym CapLen =" int " + +type_synonym uint64 =" int " + +datatype CPtrCmpOp = CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ + + + +datatype ClearRegSet = GPLo | GPHi | CLo | CHi + + + +datatype (plugins only: size) ast = + DADDIU " ((regno * regno * imm16))" + | DADDU " ((regno * regno * regno))" + | DADDI " ((regno * regno * 16 bits))" + | DADD " ((regno * regno * regno))" + | ADD " ((regno * regno * regno))" + | ADDI " ((regno * regno * 16 bits))" + | ADDU " ((regno * regno * regno))" + | ADDIU " ((regno * regno * 16 bits))" + | DSUBU " ((regno * regno * regno))" + | DSUB " ((regno * regno * regno))" + | SUB " ((regno * regno * regno))" + | SUBU " ((regno * regno * regno))" + | AND0 " ((regno * regno * regno))" + | ANDI " ((regno * regno * 16 bits))" + | OR0 " ((regno * regno * regno))" + | ORI " ((regno * regno * 16 bits))" + | NOR " ((regno * regno * regno))" + | XOR0 " ((regno * regno * regno))" + | XORI " ((regno * regno * 16 bits))" + | LUI " ((regno * imm16))" + | DSLL " ((regno * regno * regno))" + | DSLL32 " ((regno * regno * regno))" + | DSLLV " ((regno * regno * regno))" + | DSRA " ((regno * regno * regno))" + | DSRA32 " ((regno * regno * regno))" + | DSRAV " ((regno * regno * regno))" + | DSRL " ((regno * regno * regno))" + | DSRL32 " ((regno * regno * regno))" + | DSRLV " ((regno * regno * regno))" + | SLL " ((regno * regno * regno))" + | SLLV " ((regno * regno * regno))" + | SRA " ((regno * regno * regno))" + | SRAV " ((regno * regno * regno))" + | SRL " ((regno * regno * regno))" + | SRLV " ((regno * regno * regno))" + | SLT " ((regno * regno * regno))" + | SLTI " ((regno * regno * 16 bits))" + | SLTU " ((regno * regno * regno))" + | SLTIU " ((regno * regno * 16 bits))" + | MOVN " ((regno * regno * regno))" + | MOVZ " ((regno * regno * regno))" + | MFHI " (regno)" + | MFLO " (regno)" + | MTHI " (regno)" + | MTLO " (regno)" + | MUL " ((regno * regno * regno))" + | MULT " ((regno * regno))" + | MULTU " ((regno * regno))" + | DMULT " ((regno * regno))" + | DMULTU " ((regno * regno))" + | MADD " ((regno * regno))" + | MADDU " ((regno * regno))" + | MSUB " ((regno * regno))" + | MSUBU " ((regno * regno))" + | DIV " ((regno * regno))" + | DIVU " ((regno * regno))" + | DDIV " ((regno * regno))" + | DDIVU " ((regno * regno))" + | J " ( 26 bits)" + | JAL " ( 26 bits)" + | JR " (regno)" + | JALR " ((regno * regno))" + | BEQ " ((regno * regno * imm16 * bool * bool))" + | BCMPZ " ((regno * imm16 * Comparison * bool * bool))" + | SYSCALL_THREAD_START " (unit)" + | ImplementationDefinedStopFetching " (unit)" + | SYSCALL " (unit)" + | BREAK " (unit)" + | WAIT " (unit)" + | TRAPREG " ((regno * regno * Comparison))" + | TRAPIMM " ((regno * imm16 * Comparison))" + | Load " ((WordType * bool * bool * regno * regno * imm16))" + | Store " ((WordType * bool * regno * regno * imm16))" + | LWL " ((regno * regno * 16 bits))" + | LWR " ((regno * regno * 16 bits))" + | SWL " ((regno * regno * 16 bits))" + | SWR " ((regno * regno * 16 bits))" + | LDL " ((regno * regno * 16 bits))" + | LDR " ((regno * regno * 16 bits))" + | SDL " ((regno * regno * 16 bits))" + | SDR " ((regno * regno * 16 bits))" + | CACHE " ((regno * regno * 16 bits))" + | PREF " ((regno * regno * 16 bits))" + | SYNC " (unit)" + | MFC0 " ((regno * regno * 3 bits * bool))" + | HCF " (unit)" + | MTC0 " ((regno * regno * 3 bits * bool))" + | TLBWI " (unit)" + | TLBWR " (unit)" + | TLBR " (unit)" + | TLBP " (unit)" + | RDHWR " ((regno * regno))" + | ERET " (unit)" + | CGetPerm " ((regno * regno))" + | CGetType " ((regno * regno))" + | CGetBase " ((regno * regno))" + | CGetLen " ((regno * regno))" + | CGetTag " ((regno * regno))" + | CGetSealed " ((regno * regno))" + | CGetOffset " ((regno * regno))" + | CGetAddr " ((regno * regno))" + | CGetPCC " (regno)" + | CGetPCCSetOffset " ((regno * regno))" + | CGetCause " (regno)" + | CSetCause " (regno)" + | CReadHwr " ((regno * regno))" + | CWriteHwr " ((regno * regno))" + | CAndPerm " ((regno * regno * regno))" + | CToPtr " ((regno * regno * regno))" + | CSub " ((regno * regno * regno))" + | CPtrCmp " ((regno * regno * regno * CPtrCmpOp))" + | CIncOffset " ((regno * regno * regno))" + | CIncOffsetImmediate " ((regno * regno * 11 bits))" + | CSetOffset " ((regno * regno * regno))" + | CSetBounds " ((regno * regno * regno))" + | CSetBoundsImmediate " ((regno * regno * 11 bits))" + | CSetBoundsExact " ((regno * regno * regno))" + | CClearTag " ((regno * regno))" + | CMOVX " ((regno * regno * regno * bool))" + | ClearRegs " ((ClearRegSet * 16 bits))" + | CFromPtr " ((regno * regno * regno))" + | CBuildCap " ((regno * regno * regno))" + | CCopyType " ((regno * regno * regno))" + | CCheckPerm " ((regno * regno))" + | CCheckType " ((regno * regno))" + | CTestSubset " ((regno * regno * regno))" + | CSeal " ((regno * regno * regno))" + | CCSeal " ((regno * regno * regno))" + | CUnseal " ((regno * regno * regno))" + | CCall " ((regno * regno * 11 bits))" + | CReturn " (unit)" + | CBX " ((regno * 16 bits * bool))" + | CBZ " ((regno * 16 bits * bool))" + | CJALR " ((regno * regno * bool))" + | CLoad " ((regno * regno * regno * 8 bits * bool * WordType * bool))" + | CStore " ((regno * regno * regno * regno * 8 bits * WordType * bool))" + | CSC " ((regno * regno * regno * regno * 11 bits * bool))" + | CLC " ((regno * regno * regno * 11 bits * bool))" + | C2Dump " (regno)" + | RI " (unit)" + + + +datatype CapEx = + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_CapCauseReg " (CapCauseReg)" + | Regval_CauseReg " (CauseReg)" + | Regval_ContextReg " (ContextReg)" + | Regval_StatusReg " (StatusReg)" + | Regval_TLBEntry " (TLBEntry)" + | Regval_TLBEntryHiReg " (TLBEntryHiReg)" + | Regval_TLBEntryLoReg " (TLBEntryLoReg)" + | Regval_XContextReg " (XContextReg)" + | Regval_int " (ii)" + | Regval_vector_16_dec_bit " ( 16 Word.word)" + | Regval_vector_1_dec_bit " ( 1 Word.word)" + | Regval_vector_257_dec_bit " ( 257 Word.word)" + | Regval_vector_32_dec_bit " ( 32 Word.word)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + | Regval_vector_6_dec_bit " ( 6 Word.word)" + | Regval_vector_8_dec_bit " ( 8 Word.word)" + + + +record regstate = + + instCount ::" ii " + + CapCause ::" CapCauseReg " + + CTLSP ::" 257 Word.word " + + CTLSU ::" 257 Word.word " + + C31 ::" 257 Word.word " + + C30 ::" 257 Word.word " + + C29 ::" 257 Word.word " + + C28 ::" 257 Word.word " + + C27 ::" 257 Word.word " + + C26 ::" 257 Word.word " + + C25 ::" 257 Word.word " + + C24 ::" 257 Word.word " + + C23 ::" 257 Word.word " + + C22 ::" 257 Word.word " + + C21 ::" 257 Word.word " + + C20 ::" 257 Word.word " + + C19 ::" 257 Word.word " + + C18 ::" 257 Word.word " + + C17 ::" 257 Word.word " + + C16 ::" 257 Word.word " + + C15 ::" 257 Word.word " + + C14 ::" 257 Word.word " + + C13 ::" 257 Word.word " + + C12 ::" 257 Word.word " + + C11 ::" 257 Word.word " + + C10 ::" 257 Word.word " + + C09 ::" 257 Word.word " + + C08 ::" 257 Word.word " + + C07 ::" 257 Word.word " + + C06 ::" 257 Word.word " + + C05 ::" 257 Word.word " + + C04 ::" 257 Word.word " + + C03 ::" 257 Word.word " + + C02 ::" 257 Word.word " + + C01 ::" 257 Word.word " + + C00 ::" 257 Word.word " + + inCCallDelay ::" 1 Word.word " + + delayedPCC ::" 257 Word.word " + + nextPCC ::" 257 Word.word " + + PCC ::" 257 Word.word " + + UART_RVALID ::" 1 Word.word " + + UART_RDATA ::" 8 Word.word " + + UART_WRITTEN ::" 1 Word.word " + + UART_WDATA ::" 8 Word.word " + + GPR ::" ( 64 Word.word) list " + + LO ::" 64 Word.word " + + HI ::" 64 Word.word " + + delayedPC ::" 64 Word.word " + + inBranchDelay ::" 1 Word.word " + + branchPending ::" 1 Word.word " + + CP0Status ::" StatusReg " + + CP0UserLocal ::" 64 Word.word " + + CP0HWREna ::" 32 Word.word " + + CP0Count ::" 32 Word.word " + + CP0BadVAddr ::" 64 Word.word " + + CP0LLAddr ::" 64 Word.word " + + CP0LLBit ::" 1 Word.word " + + CP0ErrorEPC ::" 64 Word.word " + + CP0EPC ::" 64 Word.word " + + CP0Cause ::" CauseReg " + + CP0Compare ::" 32 Word.word " + + TLBEntry63 ::" TLBEntry " + + TLBEntry62 ::" TLBEntry " + + TLBEntry61 ::" TLBEntry " + + TLBEntry60 ::" TLBEntry " + + TLBEntry59 ::" TLBEntry " + + TLBEntry58 ::" TLBEntry " + + TLBEntry57 ::" TLBEntry " + + TLBEntry56 ::" TLBEntry " + + TLBEntry55 ::" TLBEntry " + + TLBEntry54 ::" TLBEntry " + + TLBEntry53 ::" TLBEntry " + + TLBEntry52 ::" TLBEntry " + + TLBEntry51 ::" TLBEntry " + + TLBEntry50 ::" TLBEntry " + + TLBEntry49 ::" TLBEntry " + + TLBEntry48 ::" TLBEntry " + + TLBEntry47 ::" TLBEntry " + + TLBEntry46 ::" TLBEntry " + + TLBEntry45 ::" TLBEntry " + + TLBEntry44 ::" TLBEntry " + + TLBEntry43 ::" TLBEntry " + + TLBEntry42 ::" TLBEntry " + + TLBEntry41 ::" TLBEntry " + + TLBEntry40 ::" TLBEntry " + + TLBEntry39 ::" TLBEntry " + + TLBEntry38 ::" TLBEntry " + + TLBEntry37 ::" TLBEntry " + + TLBEntry36 ::" TLBEntry " + + TLBEntry35 ::" TLBEntry " + + TLBEntry34 ::" TLBEntry " + + TLBEntry33 ::" TLBEntry " + + TLBEntry32 ::" TLBEntry " + + TLBEntry31 ::" TLBEntry " + + TLBEntry30 ::" TLBEntry " + + TLBEntry29 ::" TLBEntry " + + TLBEntry28 ::" TLBEntry " + + TLBEntry27 ::" TLBEntry " + + TLBEntry26 ::" TLBEntry " + + TLBEntry25 ::" TLBEntry " + + TLBEntry24 ::" TLBEntry " + + TLBEntry23 ::" TLBEntry " + + TLBEntry22 ::" TLBEntry " + + TLBEntry21 ::" TLBEntry " + + TLBEntry20 ::" TLBEntry " + + TLBEntry19 ::" TLBEntry " + + TLBEntry18 ::" TLBEntry " + + TLBEntry17 ::" TLBEntry " + + TLBEntry16 ::" TLBEntry " + + TLBEntry15 ::" TLBEntry " + + TLBEntry14 ::" TLBEntry " + + TLBEntry13 ::" TLBEntry " + + TLBEntry12 ::" TLBEntry " + + TLBEntry11 ::" TLBEntry " + + TLBEntry10 ::" TLBEntry " + + TLBEntry09 ::" TLBEntry " + + TLBEntry08 ::" TLBEntry " + + TLBEntry07 ::" TLBEntry " + + TLBEntry06 ::" TLBEntry " + + TLBEntry05 ::" TLBEntry " + + TLBEntry04 ::" TLBEntry " + + TLBEntry03 ::" TLBEntry " + + TLBEntry02 ::" TLBEntry " + + TLBEntry01 ::" TLBEntry " + + TLBEntry00 ::" TLBEntry " + + TLBXContext ::" XContextReg " + + TLBEntryHi ::" TLBEntryHiReg " + + TLBWired ::" 6 Word.word " + + TLBPageMask ::" 16 Word.word " + + TLBContext ::" ContextReg " + + TLBEntryLo1 ::" TLBEntryLoReg " + + TLBEntryLo0 ::" TLBEntryLoReg " + + TLBRandom ::" 6 Word.word " + + TLBIndex ::" 6 Word.word " + + TLBProbe ::" 1 Word.word " + + nextPC ::" 64 Word.word " + + PC ::" 64 Word.word " + + + + + +(*val CapCauseReg_of_regval : register_value -> maybe CapCauseReg*) + +fun CapCauseReg_of_regval :: " register_value \(CapCauseReg)option " where + " CapCauseReg_of_regval (Regval_CapCauseReg (v)) = ( Some v )" +|" CapCauseReg_of_regval g__114 = ( None )" + + +(*val regval_of_CapCauseReg : CapCauseReg -> register_value*) + +definition regval_of_CapCauseReg :: " CapCauseReg \ register_value " where + " regval_of_CapCauseReg v = ( Regval_CapCauseReg v )" + + +(*val CauseReg_of_regval : register_value -> maybe CauseReg*) + +fun CauseReg_of_regval :: " register_value \(CauseReg)option " where + " CauseReg_of_regval (Regval_CauseReg (v)) = ( Some v )" +|" CauseReg_of_regval g__113 = ( None )" + + +(*val regval_of_CauseReg : CauseReg -> register_value*) + +definition regval_of_CauseReg :: " CauseReg \ register_value " where + " regval_of_CauseReg v = ( Regval_CauseReg v )" + + +(*val ContextReg_of_regval : register_value -> maybe ContextReg*) + +fun ContextReg_of_regval :: " register_value \(ContextReg)option " where + " ContextReg_of_regval (Regval_ContextReg (v)) = ( Some v )" +|" ContextReg_of_regval g__112 = ( None )" + + +(*val regval_of_ContextReg : ContextReg -> register_value*) + +definition regval_of_ContextReg :: " ContextReg \ register_value " where + " regval_of_ContextReg v = ( Regval_ContextReg v )" + + +(*val StatusReg_of_regval : register_value -> maybe StatusReg*) + +fun StatusReg_of_regval :: " register_value \(StatusReg)option " where + " StatusReg_of_regval (Regval_StatusReg (v)) = ( Some v )" +|" StatusReg_of_regval g__111 = ( None )" + + +(*val regval_of_StatusReg : StatusReg -> register_value*) + +definition regval_of_StatusReg :: " StatusReg \ register_value " where + " regval_of_StatusReg v = ( Regval_StatusReg v )" + + +(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*) + +fun TLBEntry_of_regval :: " register_value \(TLBEntry)option " where + " TLBEntry_of_regval (Regval_TLBEntry (v)) = ( Some v )" +|" TLBEntry_of_regval g__110 = ( None )" + + +(*val regval_of_TLBEntry : TLBEntry -> register_value*) + +definition regval_of_TLBEntry :: " TLBEntry \ register_value " where + " regval_of_TLBEntry v = ( Regval_TLBEntry v )" + + +(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*) + +fun TLBEntryHiReg_of_regval :: " register_value \(TLBEntryHiReg)option " where + " TLBEntryHiReg_of_regval (Regval_TLBEntryHiReg (v)) = ( Some v )" +|" TLBEntryHiReg_of_regval g__109 = ( None )" + + +(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) + +definition regval_of_TLBEntryHiReg :: " TLBEntryHiReg \ register_value " where + " regval_of_TLBEntryHiReg v = ( Regval_TLBEntryHiReg v )" + + +(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*) + +fun TLBEntryLoReg_of_regval :: " register_value \(TLBEntryLoReg)option " where + " TLBEntryLoReg_of_regval (Regval_TLBEntryLoReg (v)) = ( Some v )" +|" TLBEntryLoReg_of_regval g__108 = ( None )" + + +(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) + +definition regval_of_TLBEntryLoReg :: " TLBEntryLoReg \ register_value " where + " regval_of_TLBEntryLoReg v = ( Regval_TLBEntryLoReg v )" + + +(*val XContextReg_of_regval : register_value -> maybe XContextReg*) + +fun XContextReg_of_regval :: " register_value \(XContextReg)option " where + " XContextReg_of_regval (Regval_XContextReg (v)) = ( Some v )" +|" XContextReg_of_regval g__107 = ( None )" + + +(*val regval_of_XContextReg : XContextReg -> register_value*) + +definition regval_of_XContextReg :: " XContextReg \ register_value " where + " regval_of_XContextReg v = ( Regval_XContextReg v )" + + +(*val int_of_regval : register_value -> maybe ii*) + +fun int_of_regval :: " register_value \(int)option " where + " int_of_regval (Regval_int (v)) = ( Some v )" +|" int_of_regval g__106 = ( None )" + + +(*val regval_of_int : ii -> register_value*) + +definition regval_of_int :: " int \ register_value " where + " regval_of_int v = ( Regval_int v )" + + +(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*) + +fun vector_16_dec_bit_of_regval :: " register_value \((16)Word.word)option " where + " vector_16_dec_bit_of_regval (Regval_vector_16_dec_bit (v)) = ( Some v )" +|" vector_16_dec_bit_of_regval g__105 = ( None )" + + +(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) + +definition regval_of_vector_16_dec_bit :: "(16)Word.word \ register_value " where + " regval_of_vector_16_dec_bit v = ( Regval_vector_16_dec_bit v )" + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +fun vector_1_dec_bit_of_regval :: " register_value \((1)Word.word)option " where + " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" +|" vector_1_dec_bit_of_regval g__104 = ( None )" + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +definition regval_of_vector_1_dec_bit :: "(1)Word.word \ register_value " where + " regval_of_vector_1_dec_bit v = ( Regval_vector_1_dec_bit v )" + + +(*val vector_257_dec_bit_of_regval : register_value -> maybe (mword ty257)*) + +fun vector_257_dec_bit_of_regval :: " register_value \((257)Word.word)option " where + " vector_257_dec_bit_of_regval (Regval_vector_257_dec_bit (v)) = ( Some v )" +|" vector_257_dec_bit_of_regval g__103 = ( None )" + + +(*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) + +definition regval_of_vector_257_dec_bit :: "(257)Word.word \ register_value " where + " regval_of_vector_257_dec_bit v = ( Regval_vector_257_dec_bit v )" + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +fun vector_32_dec_bit_of_regval :: " register_value \((32)Word.word)option " where + " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" +|" vector_32_dec_bit_of_regval g__102 = ( None )" + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +definition regval_of_vector_32_dec_bit :: "(32)Word.word \ register_value " where + " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__101 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \ register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + +(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*) + +fun vector_6_dec_bit_of_regval :: " register_value \((6)Word.word)option " where + " vector_6_dec_bit_of_regval (Regval_vector_6_dec_bit (v)) = ( Some v )" +|" vector_6_dec_bit_of_regval g__100 = ( None )" + + +(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) + +definition regval_of_vector_6_dec_bit :: "(6)Word.word \ register_value " where + " regval_of_vector_6_dec_bit v = ( Regval_vector_6_dec_bit v )" + + +(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*) + +fun vector_8_dec_bit_of_regval :: " register_value \((8)Word.word)option " where + " vector_8_dec_bit_of_regval (Regval_vector_8_dec_bit (v)) = ( Some v )" +|" vector_8_dec_bit_of_regval g__99 = ( None )" + + +(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) + +definition regval_of_vector_8_dec_bit :: "(8)Word.word \ register_value " where + " regval_of_vector_8_dec_bit v = ( Regval_vector_8_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " vector_of_regval of_regval1 = ( \x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \ register_value)\ int \ bool \ 'a list \ register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " list_of_regval of_regval1 = ( \x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \ register_value)\ 'a list \ register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \ 'a option)\ register_value \('a option)option " where + " option_of_regval of_regval1 = ( \x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \ register_value)\ 'a option \ register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition instCount_ref :: "((regstate),(register_value),(int))register_ref " where + " instCount_ref = ( (| + name = (''instCount''), + read_from = (\ s . (instCount s)), + write_to = (\ v s . (( s (| instCount := v |)))), + of_regval = (\ v . int_of_regval v), + regval_of = (\ v . regval_of_int v) |) )" + + +definition CapCause_ref :: "((regstate),(register_value),(CapCauseReg))register_ref " where + " CapCause_ref = ( (| + name = (''CapCause''), + read_from = (\ s . (CapCause s)), + write_to = (\ v s . (( s (| CapCause := v |)))), + of_regval = (\ v . CapCauseReg_of_regval v), + regval_of = (\ v . regval_of_CapCauseReg v) |) )" + + +definition CTLSP_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSP_ref = ( (| + name = (''CTLSP''), + read_from = (\ s . (CTLSP s)), + write_to = (\ v s . (( s (| CTLSP := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition CTLSU_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSU_ref = ( (| + name = (''CTLSU''), + read_from = (\ s . (CTLSU s)), + write_to = (\ v s . (( s (| CTLSU := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C30_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C30_ref = ( (| + name = (''C30''), + read_from = (\ s . (C30 s)), + write_to = (\ v s . (( s (| C30 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C28_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C28_ref = ( (| + name = (''C28''), + read_from = (\ s . (C28 s)), + write_to = (\ v s . (( s (| C28 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C27_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C27_ref = ( (| + name = (''C27''), + read_from = (\ s . (C27 s)), + write_to = (\ v s . (( s (| C27 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C26_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C26_ref = ( (| + name = (''C26''), + read_from = (\ s . (C26 s)), + write_to = (\ v s . (( s (| C26 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C25_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C25_ref = ( (| + name = (''C25''), + read_from = (\ s . (C25 s)), + write_to = (\ v s . (( s (| C25 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C24_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C24_ref = ( (| + name = (''C24''), + read_from = (\ s . (C24 s)), + write_to = (\ v s . (( s (| C24 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C23_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C23_ref = ( (| + name = (''C23''), + read_from = (\ s . (C23 s)), + write_to = (\ v s . (( s (| C23 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C22_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C22_ref = ( (| + name = (''C22''), + read_from = (\ s . (C22 s)), + write_to = (\ v s . (( s (| C22 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C21_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C21_ref = ( (| + name = (''C21''), + read_from = (\ s . (C21 s)), + write_to = (\ v s . (( s (| C21 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C20_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C20_ref = ( (| + name = (''C20''), + read_from = (\ s . (C20 s)), + write_to = (\ v s . (( s (| C20 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C19_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C19_ref = ( (| + name = (''C19''), + read_from = (\ s . (C19 s)), + write_to = (\ v s . (( s (| C19 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C18_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C18_ref = ( (| + name = (''C18''), + read_from = (\ s . (C18 s)), + write_to = (\ v s . (( s (| C18 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C17_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C17_ref = ( (| + name = (''C17''), + read_from = (\ s . (C17 s)), + write_to = (\ v s . (( s (| C17 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C16_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C16_ref = ( (| + name = (''C16''), + read_from = (\ s . (C16 s)), + write_to = (\ v s . (( s (| C16 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C15_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C15_ref = ( (| + name = (''C15''), + read_from = (\ s . (C15 s)), + write_to = (\ v s . (( s (| C15 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C14_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C14_ref = ( (| + name = (''C14''), + read_from = (\ s . (C14 s)), + write_to = (\ v s . (( s (| C14 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C13_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C13_ref = ( (| + name = (''C13''), + read_from = (\ s . (C13 s)), + write_to = (\ v s . (( s (| C13 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C12_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C12_ref = ( (| + name = (''C12''), + read_from = (\ s . (C12 s)), + write_to = (\ v s . (( s (| C12 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C11_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C11_ref = ( (| + name = (''C11''), + read_from = (\ s . (C11 s)), + write_to = (\ v s . (( s (| C11 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C10_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C10_ref = ( (| + name = (''C10''), + read_from = (\ s . (C10 s)), + write_to = (\ v s . (( s (| C10 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C09_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C09_ref = ( (| + name = (''C09''), + read_from = (\ s . (C09 s)), + write_to = (\ v s . (( s (| C09 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C08_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C08_ref = ( (| + name = (''C08''), + read_from = (\ s . (C08 s)), + write_to = (\ v s . (( s (| C08 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C07_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C07_ref = ( (| + name = (''C07''), + read_from = (\ s . (C07 s)), + write_to = (\ v s . (( s (| C07 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C06_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C06_ref = ( (| + name = (''C06''), + read_from = (\ s . (C06 s)), + write_to = (\ v s . (( s (| C06 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C05_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C05_ref = ( (| + name = (''C05''), + read_from = (\ s . (C05 s)), + write_to = (\ v s . (( s (| C05 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C04_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C04_ref = ( (| + name = (''C04''), + read_from = (\ s . (C04 s)), + write_to = (\ v s . (( s (| C04 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C03_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C03_ref = ( (| + name = (''C03''), + read_from = (\ s . (C03 s)), + write_to = (\ v s . (( s (| C03 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C02_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C02_ref = ( (| + name = (''C02''), + read_from = (\ s . (C02 s)), + write_to = (\ v s . (( s (| C02 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C01_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C01_ref = ( (| + name = (''C01''), + read_from = (\ s . (C01 s)), + write_to = (\ v s . (( s (| C01 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C00_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C00_ref = ( (| + name = (''C00''), + read_from = (\ s . (C00 s)), + write_to = (\ v s . (( s (| C00 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition inCCallDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inCCallDelay_ref = ( (| + name = (''inCCallDelay''), + read_from = (\ s . (inCCallDelay s)), + write_to = (\ v s . (( s (| inCCallDelay := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " nextPCC_ref = ( (| + name = (''nextPCC''), + read_from = (\ s . (nextPCC s)), + write_to = (\ v s . (( s (| nextPCC := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition delayedPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " delayedPCC_ref = ( (| + name = (''delayedPCC''), + read_from = (\ s . (delayedPCC s)), + write_to = (\ v s . (( s (| delayedPCC := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition PCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " PCC_ref = ( (| + name = (''PCC''), + read_from = (\ s . (PCC s)), + write_to = (\ v s . (( s (| PCC := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C31_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C31_ref = ( (| + name = (''C31''), + read_from = (\ s . (C31 s)), + write_to = (\ v s . (( s (| C31 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition C29_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C29_ref = ( (| + name = (''C29''), + read_from = (\ s . (C29 s)), + write_to = (\ v s . (( s (| C29 := v |)))), + of_regval = (\ v . vector_257_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_257_dec_bit v) |) )" + + +definition UART_RVALID_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_RVALID_ref = ( (| + name = (''UART_RVALID''), + read_from = (\ s . (UART_RVALID s)), + write_to = (\ v s . (( s (| UART_RVALID := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_RDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_RDATA_ref = ( (| + name = (''UART_RDATA''), + read_from = (\ s . (UART_RDATA s)), + write_to = (\ v s . (( s (| UART_RDATA := v |)))), + of_regval = (\ v . vector_8_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_8_dec_bit v) |) )" + + +definition UART_WRITTEN_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_WRITTEN_ref = ( (| + name = (''UART_WRITTEN''), + read_from = (\ s . (UART_WRITTEN s)), + write_to = (\ v s . (( s (| UART_WRITTEN := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_WDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_WDATA_ref = ( (| + name = (''UART_WDATA''), + read_from = (\ s . (UART_WDATA s)), + write_to = (\ v s . (( s (| UART_WDATA := v |)))), + of_regval = (\ v . vector_8_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_8_dec_bit v) |) )" + + +definition GPR_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " GPR_ref = ( (| + name = (''GPR''), + read_from = (\ s . (GPR s)), + write_to = (\ v s . (( s (| GPR := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition LO_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " LO_ref = ( (| + name = (''LO''), + read_from = (\ s . (LO s)), + write_to = (\ v s . (( s (| LO := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition HI_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " HI_ref = ( (| + name = (''HI''), + read_from = (\ s . (HI s)), + write_to = (\ v s . (( s (| HI := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition delayedPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " delayedPC_ref = ( (| + name = (''delayedPC''), + read_from = (\ s . (delayedPC s)), + write_to = (\ v s . (( s (| delayedPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition inBranchDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inBranchDelay_ref = ( (| + name = (''inBranchDelay''), + read_from = (\ s . (inBranchDelay s)), + write_to = (\ v s . (( s (| inBranchDelay := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition branchPending_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " branchPending_ref = ( (| + name = (''branchPending''), + read_from = (\ s . (branchPending s)), + write_to = (\ v s . (( s (| branchPending := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0Status_ref :: "((regstate),(register_value),(StatusReg))register_ref " where + " CP0Status_ref = ( (| + name = (''CP0Status''), + read_from = (\ s . (CP0Status s)), + write_to = (\ v s . (( s (| CP0Status := v |)))), + of_regval = (\ v . StatusReg_of_regval v), + regval_of = (\ v . regval_of_StatusReg v) |) )" + + +definition CP0UserLocal_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0UserLocal_ref = ( (| + name = (''CP0UserLocal''), + read_from = (\ s . (CP0UserLocal s)), + write_to = (\ v s . (( s (| CP0UserLocal := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0HWREna_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0HWREna_ref = ( (| + name = (''CP0HWREna''), + read_from = (\ s . (CP0HWREna s)), + write_to = (\ v s . (( s (| CP0HWREna := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0Count_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Count_ref = ( (| + name = (''CP0Count''), + read_from = (\ s . (CP0Count s)), + write_to = (\ v s . (( s (| CP0Count := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0BadVAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0BadVAddr_ref = ( (| + name = (''CP0BadVAddr''), + read_from = (\ s . (CP0BadVAddr s)), + write_to = (\ v s . (( s (| CP0BadVAddr := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0LLAddr_ref = ( (| + name = (''CP0LLAddr''), + read_from = (\ s . (CP0LLAddr s)), + write_to = (\ v s . (( s (| CP0LLAddr := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLBit_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " CP0LLBit_ref = ( (| + name = (''CP0LLBit''), + read_from = (\ s . (CP0LLBit s)), + write_to = (\ v s . (( s (| CP0LLBit := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0ErrorEPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0ErrorEPC_ref = ( (| + name = (''CP0ErrorEPC''), + read_from = (\ s . (CP0ErrorEPC s)), + write_to = (\ v s . (( s (| CP0ErrorEPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0EPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0EPC_ref = ( (| + name = (''CP0EPC''), + read_from = (\ s . (CP0EPC s)), + write_to = (\ v s . (( s (| CP0EPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0Cause_ref :: "((regstate),(register_value),(CauseReg))register_ref " where + " CP0Cause_ref = ( (| + name = (''CP0Cause''), + read_from = (\ s . (CP0Cause s)), + write_to = (\ v s . (( s (| CP0Cause := v |)))), + of_regval = (\ v . CauseReg_of_regval v), + regval_of = (\ v . regval_of_CauseReg v) |) )" + + +definition CP0Compare_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Compare_ref = ( (| + name = (''CP0Compare''), + read_from = (\ s . (CP0Compare s)), + write_to = (\ v s . (( s (| CP0Compare := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition TLBEntry63_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry63_ref = ( (| + name = (''TLBEntry63''), + read_from = (\ s . (TLBEntry63 s)), + write_to = (\ v s . (( s (| TLBEntry63 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry62_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry62_ref = ( (| + name = (''TLBEntry62''), + read_from = (\ s . (TLBEntry62 s)), + write_to = (\ v s . (( s (| TLBEntry62 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry61_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry61_ref = ( (| + name = (''TLBEntry61''), + read_from = (\ s . (TLBEntry61 s)), + write_to = (\ v s . (( s (| TLBEntry61 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry60_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry60_ref = ( (| + name = (''TLBEntry60''), + read_from = (\ s . (TLBEntry60 s)), + write_to = (\ v s . (( s (| TLBEntry60 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry59_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry59_ref = ( (| + name = (''TLBEntry59''), + read_from = (\ s . (TLBEntry59 s)), + write_to = (\ v s . (( s (| TLBEntry59 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry58_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry58_ref = ( (| + name = (''TLBEntry58''), + read_from = (\ s . (TLBEntry58 s)), + write_to = (\ v s . (( s (| TLBEntry58 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry57_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry57_ref = ( (| + name = (''TLBEntry57''), + read_from = (\ s . (TLBEntry57 s)), + write_to = (\ v s . (( s (| TLBEntry57 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry56_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry56_ref = ( (| + name = (''TLBEntry56''), + read_from = (\ s . (TLBEntry56 s)), + write_to = (\ v s . (( s (| TLBEntry56 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry55_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry55_ref = ( (| + name = (''TLBEntry55''), + read_from = (\ s . (TLBEntry55 s)), + write_to = (\ v s . (( s (| TLBEntry55 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry54_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry54_ref = ( (| + name = (''TLBEntry54''), + read_from = (\ s . (TLBEntry54 s)), + write_to = (\ v s . (( s (| TLBEntry54 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry53_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry53_ref = ( (| + name = (''TLBEntry53''), + read_from = (\ s . (TLBEntry53 s)), + write_to = (\ v s . (( s (| TLBEntry53 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry52_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry52_ref = ( (| + name = (''TLBEntry52''), + read_from = (\ s . (TLBEntry52 s)), + write_to = (\ v s . (( s (| TLBEntry52 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry51_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry51_ref = ( (| + name = (''TLBEntry51''), + read_from = (\ s . (TLBEntry51 s)), + write_to = (\ v s . (( s (| TLBEntry51 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry50_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry50_ref = ( (| + name = (''TLBEntry50''), + read_from = (\ s . (TLBEntry50 s)), + write_to = (\ v s . (( s (| TLBEntry50 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry49_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry49_ref = ( (| + name = (''TLBEntry49''), + read_from = (\ s . (TLBEntry49 s)), + write_to = (\ v s . (( s (| TLBEntry49 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry48_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry48_ref = ( (| + name = (''TLBEntry48''), + read_from = (\ s . (TLBEntry48 s)), + write_to = (\ v s . (( s (| TLBEntry48 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry47_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry47_ref = ( (| + name = (''TLBEntry47''), + read_from = (\ s . (TLBEntry47 s)), + write_to = (\ v s . (( s (| TLBEntry47 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry46_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry46_ref = ( (| + name = (''TLBEntry46''), + read_from = (\ s . (TLBEntry46 s)), + write_to = (\ v s . (( s (| TLBEntry46 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry45_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry45_ref = ( (| + name = (''TLBEntry45''), + read_from = (\ s . (TLBEntry45 s)), + write_to = (\ v s . (( s (| TLBEntry45 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry44_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry44_ref = ( (| + name = (''TLBEntry44''), + read_from = (\ s . (TLBEntry44 s)), + write_to = (\ v s . (( s (| TLBEntry44 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry43_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry43_ref = ( (| + name = (''TLBEntry43''), + read_from = (\ s . (TLBEntry43 s)), + write_to = (\ v s . (( s (| TLBEntry43 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry42_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry42_ref = ( (| + name = (''TLBEntry42''), + read_from = (\ s . (TLBEntry42 s)), + write_to = (\ v s . (( s (| TLBEntry42 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry41_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry41_ref = ( (| + name = (''TLBEntry41''), + read_from = (\ s . (TLBEntry41 s)), + write_to = (\ v s . (( s (| TLBEntry41 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry40_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry40_ref = ( (| + name = (''TLBEntry40''), + read_from = (\ s . (TLBEntry40 s)), + write_to = (\ v s . (( s (| TLBEntry40 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry39_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry39_ref = ( (| + name = (''TLBEntry39''), + read_from = (\ s . (TLBEntry39 s)), + write_to = (\ v s . (( s (| TLBEntry39 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry38_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry38_ref = ( (| + name = (''TLBEntry38''), + read_from = (\ s . (TLBEntry38 s)), + write_to = (\ v s . (( s (| TLBEntry38 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry37_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry37_ref = ( (| + name = (''TLBEntry37''), + read_from = (\ s . (TLBEntry37 s)), + write_to = (\ v s . (( s (| TLBEntry37 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry36_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry36_ref = ( (| + name = (''TLBEntry36''), + read_from = (\ s . (TLBEntry36 s)), + write_to = (\ v s . (( s (| TLBEntry36 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry35_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry35_ref = ( (| + name = (''TLBEntry35''), + read_from = (\ s . (TLBEntry35 s)), + write_to = (\ v s . (( s (| TLBEntry35 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry34_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry34_ref = ( (| + name = (''TLBEntry34''), + read_from = (\ s . (TLBEntry34 s)), + write_to = (\ v s . (( s (| TLBEntry34 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry33_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry33_ref = ( (| + name = (''TLBEntry33''), + read_from = (\ s . (TLBEntry33 s)), + write_to = (\ v s . (( s (| TLBEntry33 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry32_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry32_ref = ( (| + name = (''TLBEntry32''), + read_from = (\ s . (TLBEntry32 s)), + write_to = (\ v s . (( s (| TLBEntry32 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry31_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry31_ref = ( (| + name = (''TLBEntry31''), + read_from = (\ s . (TLBEntry31 s)), + write_to = (\ v s . (( s (| TLBEntry31 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry30_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry30_ref = ( (| + name = (''TLBEntry30''), + read_from = (\ s . (TLBEntry30 s)), + write_to = (\ v s . (( s (| TLBEntry30 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry29_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry29_ref = ( (| + name = (''TLBEntry29''), + read_from = (\ s . (TLBEntry29 s)), + write_to = (\ v s . (( s (| TLBEntry29 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry28_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry28_ref = ( (| + name = (''TLBEntry28''), + read_from = (\ s . (TLBEntry28 s)), + write_to = (\ v s . (( s (| TLBEntry28 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry27_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry27_ref = ( (| + name = (''TLBEntry27''), + read_from = (\ s . (TLBEntry27 s)), + write_to = (\ v s . (( s (| TLBEntry27 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry26_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry26_ref = ( (| + name = (''TLBEntry26''), + read_from = (\ s . (TLBEntry26 s)), + write_to = (\ v s . (( s (| TLBEntry26 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry25_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry25_ref = ( (| + name = (''TLBEntry25''), + read_from = (\ s . (TLBEntry25 s)), + write_to = (\ v s . (( s (| TLBEntry25 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry24_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry24_ref = ( (| + name = (''TLBEntry24''), + read_from = (\ s . (TLBEntry24 s)), + write_to = (\ v s . (( s (| TLBEntry24 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry23_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry23_ref = ( (| + name = (''TLBEntry23''), + read_from = (\ s . (TLBEntry23 s)), + write_to = (\ v s . (( s (| TLBEntry23 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry22_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry22_ref = ( (| + name = (''TLBEntry22''), + read_from = (\ s . (TLBEntry22 s)), + write_to = (\ v s . (( s (| TLBEntry22 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry21_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry21_ref = ( (| + name = (''TLBEntry21''), + read_from = (\ s . (TLBEntry21 s)), + write_to = (\ v s . (( s (| TLBEntry21 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry20_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry20_ref = ( (| + name = (''TLBEntry20''), + read_from = (\ s . (TLBEntry20 s)), + write_to = (\ v s . (( s (| TLBEntry20 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry19_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry19_ref = ( (| + name = (''TLBEntry19''), + read_from = (\ s . (TLBEntry19 s)), + write_to = (\ v s . (( s (| TLBEntry19 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry18_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry18_ref = ( (| + name = (''TLBEntry18''), + read_from = (\ s . (TLBEntry18 s)), + write_to = (\ v s . (( s (| TLBEntry18 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry17_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry17_ref = ( (| + name = (''TLBEntry17''), + read_from = (\ s . (TLBEntry17 s)), + write_to = (\ v s . (( s (| TLBEntry17 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry16_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry16_ref = ( (| + name = (''TLBEntry16''), + read_from = (\ s . (TLBEntry16 s)), + write_to = (\ v s . (( s (| TLBEntry16 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry15_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry15_ref = ( (| + name = (''TLBEntry15''), + read_from = (\ s . (TLBEntry15 s)), + write_to = (\ v s . (( s (| TLBEntry15 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry14_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry14_ref = ( (| + name = (''TLBEntry14''), + read_from = (\ s . (TLBEntry14 s)), + write_to = (\ v s . (( s (| TLBEntry14 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry13_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry13_ref = ( (| + name = (''TLBEntry13''), + read_from = (\ s . (TLBEntry13 s)), + write_to = (\ v s . (( s (| TLBEntry13 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry12_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry12_ref = ( (| + name = (''TLBEntry12''), + read_from = (\ s . (TLBEntry12 s)), + write_to = (\ v s . (( s (| TLBEntry12 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry11_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry11_ref = ( (| + name = (''TLBEntry11''), + read_from = (\ s . (TLBEntry11 s)), + write_to = (\ v s . (( s (| TLBEntry11 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry10_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry10_ref = ( (| + name = (''TLBEntry10''), + read_from = (\ s . (TLBEntry10 s)), + write_to = (\ v s . (( s (| TLBEntry10 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry09_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry09_ref = ( (| + name = (''TLBEntry09''), + read_from = (\ s . (TLBEntry09 s)), + write_to = (\ v s . (( s (| TLBEntry09 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry08_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry08_ref = ( (| + name = (''TLBEntry08''), + read_from = (\ s . (TLBEntry08 s)), + write_to = (\ v s . (( s (| TLBEntry08 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry07_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry07_ref = ( (| + name = (''TLBEntry07''), + read_from = (\ s . (TLBEntry07 s)), + write_to = (\ v s . (( s (| TLBEntry07 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry06_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry06_ref = ( (| + name = (''TLBEntry06''), + read_from = (\ s . (TLBEntry06 s)), + write_to = (\ v s . (( s (| TLBEntry06 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry05_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry05_ref = ( (| + name = (''TLBEntry05''), + read_from = (\ s . (TLBEntry05 s)), + write_to = (\ v s . (( s (| TLBEntry05 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry04_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry04_ref = ( (| + name = (''TLBEntry04''), + read_from = (\ s . (TLBEntry04 s)), + write_to = (\ v s . (( s (| TLBEntry04 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry03_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry03_ref = ( (| + name = (''TLBEntry03''), + read_from = (\ s . (TLBEntry03 s)), + write_to = (\ v s . (( s (| TLBEntry03 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry02_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry02_ref = ( (| + name = (''TLBEntry02''), + read_from = (\ s . (TLBEntry02 s)), + write_to = (\ v s . (( s (| TLBEntry02 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry01_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry01_ref = ( (| + name = (''TLBEntry01''), + read_from = (\ s . (TLBEntry01 s)), + write_to = (\ v s . (( s (| TLBEntry01 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry00_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry00_ref = ( (| + name = (''TLBEntry00''), + read_from = (\ s . (TLBEntry00 s)), + write_to = (\ v s . (( s (| TLBEntry00 := v |)))), + of_regval = (\ v . TLBEntry_of_regval v), + regval_of = (\ v . regval_of_TLBEntry v) |) )" + + +definition TLBXContext_ref :: "((regstate),(register_value),(XContextReg))register_ref " where + " TLBXContext_ref = ( (| + name = (''TLBXContext''), + read_from = (\ s . (TLBXContext s)), + write_to = (\ v s . (( s (| TLBXContext := v |)))), + of_regval = (\ v . XContextReg_of_regval v), + regval_of = (\ v . regval_of_XContextReg v) |) )" + + +definition TLBEntryHi_ref :: "((regstate),(register_value),(TLBEntryHiReg))register_ref " where + " TLBEntryHi_ref = ( (| + name = (''TLBEntryHi''), + read_from = (\ s . (TLBEntryHi s)), + write_to = (\ v s . (( s (| TLBEntryHi := v |)))), + of_regval = (\ v . TLBEntryHiReg_of_regval v), + regval_of = (\ v . regval_of_TLBEntryHiReg v) |) )" + + +definition TLBWired_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBWired_ref = ( (| + name = (''TLBWired''), + read_from = (\ s . (TLBWired s)), + write_to = (\ v s . (( s (| TLBWired := v |)))), + of_regval = (\ v . vector_6_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBPageMask_ref :: "((regstate),(register_value),((16)Word.word))register_ref " where + " TLBPageMask_ref = ( (| + name = (''TLBPageMask''), + read_from = (\ s . (TLBPageMask s)), + write_to = (\ v s . (( s (| TLBPageMask := v |)))), + of_regval = (\ v . vector_16_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_16_dec_bit v) |) )" + + +definition TLBContext_ref :: "((regstate),(register_value),(ContextReg))register_ref " where + " TLBContext_ref = ( (| + name = (''TLBContext''), + read_from = (\ s . (TLBContext s)), + write_to = (\ v s . (( s (| TLBContext := v |)))), + of_regval = (\ v . ContextReg_of_regval v), + regval_of = (\ v . regval_of_ContextReg v) |) )" + + +definition TLBEntryLo1_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo1_ref = ( (| + name = (''TLBEntryLo1''), + read_from = (\ s . (TLBEntryLo1 s)), + write_to = (\ v s . (( s (| TLBEntryLo1 := v |)))), + of_regval = (\ v . TLBEntryLoReg_of_regval v), + regval_of = (\ v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBEntryLo0_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo0_ref = ( (| + name = (''TLBEntryLo0''), + read_from = (\ s . (TLBEntryLo0 s)), + write_to = (\ v s . (( s (| TLBEntryLo0 := v |)))), + of_regval = (\ v . TLBEntryLoReg_of_regval v), + regval_of = (\ v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBRandom_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBRandom_ref = ( (| + name = (''TLBRandom''), + read_from = (\ s . (TLBRandom s)), + write_to = (\ v s . (( s (| TLBRandom := v |)))), + of_regval = (\ v . vector_6_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBIndex_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBIndex_ref = ( (| + name = (''TLBIndex''), + read_from = (\ s . (TLBIndex s)), + write_to = (\ v s . (( s (| TLBIndex := v |)))), + of_regval = (\ v . vector_6_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBProbe_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " TLBProbe_ref = ( (| + name = (''TLBProbe''), + read_from = (\ s . (TLBProbe s)), + write_to = (\ v s . (( s (| TLBProbe := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\ s . (nextPC s)), + write_to = (\ v s . (( s (| nextPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\ s . (PC s)), + write_to = (\ v s . (( s (| PC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \ regstate \(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''instCount'') then Some ((regval_of instCount_ref) ((read_from instCount_ref) s)) else + if reg_name = (''CapCause'') then Some ((regval_of CapCause_ref) ((read_from CapCause_ref) s)) else + if reg_name = (''CTLSP'') then Some ((regval_of CTLSP_ref) ((read_from CTLSP_ref) s)) else + if reg_name = (''CTLSU'') then Some ((regval_of CTLSU_ref) ((read_from CTLSU_ref) s)) else + if reg_name = (''C30'') then Some ((regval_of C30_ref) ((read_from C30_ref) s)) else + if reg_name = (''C28'') then Some ((regval_of C28_ref) ((read_from C28_ref) s)) else + if reg_name = (''C27'') then Some ((regval_of C27_ref) ((read_from C27_ref) s)) else + if reg_name = (''C26'') then Some ((regval_of C26_ref) ((read_from C26_ref) s)) else + if reg_name = (''C25'') then Some ((regval_of C25_ref) ((read_from C25_ref) s)) else + if reg_name = (''C24'') then Some ((regval_of C24_ref) ((read_from C24_ref) s)) else + if reg_name = (''C23'') then Some ((regval_of C23_ref) ((read_from C23_ref) s)) else + if reg_name = (''C22'') then Some ((regval_of C22_ref) ((read_from C22_ref) s)) else + if reg_name = (''C21'') then Some ((regval_of C21_ref) ((read_from C21_ref) s)) else + if reg_name = (''C20'') then Some ((regval_of C20_ref) ((read_from C20_ref) s)) else + if reg_name = (''C19'') then Some ((regval_of C19_ref) ((read_from C19_ref) s)) else + if reg_name = (''C18'') then Some ((regval_of C18_ref) ((read_from C18_ref) s)) else + if reg_name = (''C17'') then Some ((regval_of C17_ref) ((read_from C17_ref) s)) else + if reg_name = (''C16'') then Some ((regval_of C16_ref) ((read_from C16_ref) s)) else + if reg_name = (''C15'') then Some ((regval_of C15_ref) ((read_from C15_ref) s)) else + if reg_name = (''C14'') then Some ((regval_of C14_ref) ((read_from C14_ref) s)) else + if reg_name = (''C13'') then Some ((regval_of C13_ref) ((read_from C13_ref) s)) else + if reg_name = (''C12'') then Some ((regval_of C12_ref) ((read_from C12_ref) s)) else + if reg_name = (''C11'') then Some ((regval_of C11_ref) ((read_from C11_ref) s)) else + if reg_name = (''C10'') then Some ((regval_of C10_ref) ((read_from C10_ref) s)) else + if reg_name = (''C09'') then Some ((regval_of C09_ref) ((read_from C09_ref) s)) else + if reg_name = (''C08'') then Some ((regval_of C08_ref) ((read_from C08_ref) s)) else + if reg_name = (''C07'') then Some ((regval_of C07_ref) ((read_from C07_ref) s)) else + if reg_name = (''C06'') then Some ((regval_of C06_ref) ((read_from C06_ref) s)) else + if reg_name = (''C05'') then Some ((regval_of C05_ref) ((read_from C05_ref) s)) else + if reg_name = (''C04'') then Some ((regval_of C04_ref) ((read_from C04_ref) s)) else + if reg_name = (''C03'') then Some ((regval_of C03_ref) ((read_from C03_ref) s)) else + if reg_name = (''C02'') then Some ((regval_of C02_ref) ((read_from C02_ref) s)) else + if reg_name = (''C01'') then Some ((regval_of C01_ref) ((read_from C01_ref) s)) else + if reg_name = (''C00'') then Some ((regval_of C00_ref) ((read_from C00_ref) s)) else + if reg_name = (''inCCallDelay'') then Some ((regval_of inCCallDelay_ref) ((read_from inCCallDelay_ref) s)) else + if reg_name = (''nextPCC'') then Some ((regval_of nextPCC_ref) ((read_from nextPCC_ref) s)) else + if reg_name = (''delayedPCC'') then Some ((regval_of delayedPCC_ref) ((read_from delayedPCC_ref) s)) else + if reg_name = (''PCC'') then Some ((regval_of PCC_ref) ((read_from PCC_ref) s)) else + if reg_name = (''C31'') then Some ((regval_of C31_ref) ((read_from C31_ref) s)) else + if reg_name = (''C29'') then Some ((regval_of C29_ref) ((read_from C29_ref) s)) else + if reg_name = (''UART_RVALID'') then Some ((regval_of UART_RVALID_ref) ((read_from UART_RVALID_ref) s)) else + if reg_name = (''UART_RDATA'') then Some ((regval_of UART_RDATA_ref) ((read_from UART_RDATA_ref) s)) else + if reg_name = (''UART_WRITTEN'') then Some ((regval_of UART_WRITTEN_ref) ((read_from UART_WRITTEN_ref) s)) else + if reg_name = (''UART_WDATA'') then Some ((regval_of UART_WDATA_ref) ((read_from UART_WDATA_ref) s)) else + if reg_name = (''GPR'') then Some ((regval_of GPR_ref) ((read_from GPR_ref) s)) else + if reg_name = (''LO'') then Some ((regval_of LO_ref) ((read_from LO_ref) s)) else + if reg_name = (''HI'') then Some ((regval_of HI_ref) ((read_from HI_ref) s)) else + if reg_name = (''delayedPC'') then Some ((regval_of delayedPC_ref) ((read_from delayedPC_ref) s)) else + if reg_name = (''inBranchDelay'') then Some ((regval_of inBranchDelay_ref) ((read_from inBranchDelay_ref) s)) else + if reg_name = (''branchPending'') then Some ((regval_of branchPending_ref) ((read_from branchPending_ref) s)) else + if reg_name = (''CP0Status'') then Some ((regval_of CP0Status_ref) ((read_from CP0Status_ref) s)) else + if reg_name = (''CP0UserLocal'') then Some ((regval_of CP0UserLocal_ref) ((read_from CP0UserLocal_ref) s)) else + if reg_name = (''CP0HWREna'') then Some ((regval_of CP0HWREna_ref) ((read_from CP0HWREna_ref) s)) else + if reg_name = (''CP0Count'') then Some ((regval_of CP0Count_ref) ((read_from CP0Count_ref) s)) else + if reg_name = (''CP0BadVAddr'') then Some ((regval_of CP0BadVAddr_ref) ((read_from CP0BadVAddr_ref) s)) else + if reg_name = (''CP0LLAddr'') then Some ((regval_of CP0LLAddr_ref) ((read_from CP0LLAddr_ref) s)) else + if reg_name = (''CP0LLBit'') then Some ((regval_of CP0LLBit_ref) ((read_from CP0LLBit_ref) s)) else + if reg_name = (''CP0ErrorEPC'') then Some ((regval_of CP0ErrorEPC_ref) ((read_from CP0ErrorEPC_ref) s)) else + if reg_name = (''CP0EPC'') then Some ((regval_of CP0EPC_ref) ((read_from CP0EPC_ref) s)) else + if reg_name = (''CP0Cause'') then Some ((regval_of CP0Cause_ref) ((read_from CP0Cause_ref) s)) else + if reg_name = (''CP0Compare'') then Some ((regval_of CP0Compare_ref) ((read_from CP0Compare_ref) s)) else + if reg_name = (''TLBEntry63'') then Some ((regval_of TLBEntry63_ref) ((read_from TLBEntry63_ref) s)) else + if reg_name = (''TLBEntry62'') then Some ((regval_of TLBEntry62_ref) ((read_from TLBEntry62_ref) s)) else + if reg_name = (''TLBEntry61'') then Some ((regval_of TLBEntry61_ref) ((read_from TLBEntry61_ref) s)) else + if reg_name = (''TLBEntry60'') then Some ((regval_of TLBEntry60_ref) ((read_from TLBEntry60_ref) s)) else + if reg_name = (''TLBEntry59'') then Some ((regval_of TLBEntry59_ref) ((read_from TLBEntry59_ref) s)) else + if reg_name = (''TLBEntry58'') then Some ((regval_of TLBEntry58_ref) ((read_from TLBEntry58_ref) s)) else + if reg_name = (''TLBEntry57'') then Some ((regval_of TLBEntry57_ref) ((read_from TLBEntry57_ref) s)) else + if reg_name = (''TLBEntry56'') then Some ((regval_of TLBEntry56_ref) ((read_from TLBEntry56_ref) s)) else + if reg_name = (''TLBEntry55'') then Some ((regval_of TLBEntry55_ref) ((read_from TLBEntry55_ref) s)) else + if reg_name = (''TLBEntry54'') then Some ((regval_of TLBEntry54_ref) ((read_from TLBEntry54_ref) s)) else + if reg_name = (''TLBEntry53'') then Some ((regval_of TLBEntry53_ref) ((read_from TLBEntry53_ref) s)) else + if reg_name = (''TLBEntry52'') then Some ((regval_of TLBEntry52_ref) ((read_from TLBEntry52_ref) s)) else + if reg_name = (''TLBEntry51'') then Some ((regval_of TLBEntry51_ref) ((read_from TLBEntry51_ref) s)) else + if reg_name = (''TLBEntry50'') then Some ((regval_of TLBEntry50_ref) ((read_from TLBEntry50_ref) s)) else + if reg_name = (''TLBEntry49'') then Some ((regval_of TLBEntry49_ref) ((read_from TLBEntry49_ref) s)) else + if reg_name = (''TLBEntry48'') then Some ((regval_of TLBEntry48_ref) ((read_from TLBEntry48_ref) s)) else + if reg_name = (''TLBEntry47'') then Some ((regval_of TLBEntry47_ref) ((read_from TLBEntry47_ref) s)) else + if reg_name = (''TLBEntry46'') then Some ((regval_of TLBEntry46_ref) ((read_from TLBEntry46_ref) s)) else + if reg_name = (''TLBEntry45'') then Some ((regval_of TLBEntry45_ref) ((read_from TLBEntry45_ref) s)) else + if reg_name = (''TLBEntry44'') then Some ((regval_of TLBEntry44_ref) ((read_from TLBEntry44_ref) s)) else + if reg_name = (''TLBEntry43'') then Some ((regval_of TLBEntry43_ref) ((read_from TLBEntry43_ref) s)) else + if reg_name = (''TLBEntry42'') then Some ((regval_of TLBEntry42_ref) ((read_from TLBEntry42_ref) s)) else + if reg_name = (''TLBEntry41'') then Some ((regval_of TLBEntry41_ref) ((read_from TLBEntry41_ref) s)) else + if reg_name = (''TLBEntry40'') then Some ((regval_of TLBEntry40_ref) ((read_from TLBEntry40_ref) s)) else + if reg_name = (''TLBEntry39'') then Some ((regval_of TLBEntry39_ref) ((read_from TLBEntry39_ref) s)) else + if reg_name = (''TLBEntry38'') then Some ((regval_of TLBEntry38_ref) ((read_from TLBEntry38_ref) s)) else + if reg_name = (''TLBEntry37'') then Some ((regval_of TLBEntry37_ref) ((read_from TLBEntry37_ref) s)) else + if reg_name = (''TLBEntry36'') then Some ((regval_of TLBEntry36_ref) ((read_from TLBEntry36_ref) s)) else + if reg_name = (''TLBEntry35'') then Some ((regval_of TLBEntry35_ref) ((read_from TLBEntry35_ref) s)) else + if reg_name = (''TLBEntry34'') then Some ((regval_of TLBEntry34_ref) ((read_from TLBEntry34_ref) s)) else + if reg_name = (''TLBEntry33'') then Some ((regval_of TLBEntry33_ref) ((read_from TLBEntry33_ref) s)) else + if reg_name = (''TLBEntry32'') then Some ((regval_of TLBEntry32_ref) ((read_from TLBEntry32_ref) s)) else + if reg_name = (''TLBEntry31'') then Some ((regval_of TLBEntry31_ref) ((read_from TLBEntry31_ref) s)) else + if reg_name = (''TLBEntry30'') then Some ((regval_of TLBEntry30_ref) ((read_from TLBEntry30_ref) s)) else + if reg_name = (''TLBEntry29'') then Some ((regval_of TLBEntry29_ref) ((read_from TLBEntry29_ref) s)) else + if reg_name = (''TLBEntry28'') then Some ((regval_of TLBEntry28_ref) ((read_from TLBEntry28_ref) s)) else + if reg_name = (''TLBEntry27'') then Some ((regval_of TLBEntry27_ref) ((read_from TLBEntry27_ref) s)) else + if reg_name = (''TLBEntry26'') then Some ((regval_of TLBEntry26_ref) ((read_from TLBEntry26_ref) s)) else + if reg_name = (''TLBEntry25'') then Some ((regval_of TLBEntry25_ref) ((read_from TLBEntry25_ref) s)) else + if reg_name = (''TLBEntry24'') then Some ((regval_of TLBEntry24_ref) ((read_from TLBEntry24_ref) s)) else + if reg_name = (''TLBEntry23'') then Some ((regval_of TLBEntry23_ref) ((read_from TLBEntry23_ref) s)) else + if reg_name = (''TLBEntry22'') then Some ((regval_of TLBEntry22_ref) ((read_from TLBEntry22_ref) s)) else + if reg_name = (''TLBEntry21'') then Some ((regval_of TLBEntry21_ref) ((read_from TLBEntry21_ref) s)) else + if reg_name = (''TLBEntry20'') then Some ((regval_of TLBEntry20_ref) ((read_from TLBEntry20_ref) s)) else + if reg_name = (''TLBEntry19'') then Some ((regval_of TLBEntry19_ref) ((read_from TLBEntry19_ref) s)) else + if reg_name = (''TLBEntry18'') then Some ((regval_of TLBEntry18_ref) ((read_from TLBEntry18_ref) s)) else + if reg_name = (''TLBEntry17'') then Some ((regval_of TLBEntry17_ref) ((read_from TLBEntry17_ref) s)) else + if reg_name = (''TLBEntry16'') then Some ((regval_of TLBEntry16_ref) ((read_from TLBEntry16_ref) s)) else + if reg_name = (''TLBEntry15'') then Some ((regval_of TLBEntry15_ref) ((read_from TLBEntry15_ref) s)) else + if reg_name = (''TLBEntry14'') then Some ((regval_of TLBEntry14_ref) ((read_from TLBEntry14_ref) s)) else + if reg_name = (''TLBEntry13'') then Some ((regval_of TLBEntry13_ref) ((read_from TLBEntry13_ref) s)) else + if reg_name = (''TLBEntry12'') then Some ((regval_of TLBEntry12_ref) ((read_from TLBEntry12_ref) s)) else + if reg_name = (''TLBEntry11'') then Some ((regval_of TLBEntry11_ref) ((read_from TLBEntry11_ref) s)) else + if reg_name = (''TLBEntry10'') then Some ((regval_of TLBEntry10_ref) ((read_from TLBEntry10_ref) s)) else + if reg_name = (''TLBEntry09'') then Some ((regval_of TLBEntry09_ref) ((read_from TLBEntry09_ref) s)) else + if reg_name = (''TLBEntry08'') then Some ((regval_of TLBEntry08_ref) ((read_from TLBEntry08_ref) s)) else + if reg_name = (''TLBEntry07'') then Some ((regval_of TLBEntry07_ref) ((read_from TLBEntry07_ref) s)) else + if reg_name = (''TLBEntry06'') then Some ((regval_of TLBEntry06_ref) ((read_from TLBEntry06_ref) s)) else + if reg_name = (''TLBEntry05'') then Some ((regval_of TLBEntry05_ref) ((read_from TLBEntry05_ref) s)) else + if reg_name = (''TLBEntry04'') then Some ((regval_of TLBEntry04_ref) ((read_from TLBEntry04_ref) s)) else + if reg_name = (''TLBEntry03'') then Some ((regval_of TLBEntry03_ref) ((read_from TLBEntry03_ref) s)) else + if reg_name = (''TLBEntry02'') then Some ((regval_of TLBEntry02_ref) ((read_from TLBEntry02_ref) s)) else + if reg_name = (''TLBEntry01'') then Some ((regval_of TLBEntry01_ref) ((read_from TLBEntry01_ref) s)) else + if reg_name = (''TLBEntry00'') then Some ((regval_of TLBEntry00_ref) ((read_from TLBEntry00_ref) s)) else + if reg_name = (''TLBXContext'') then Some ((regval_of TLBXContext_ref) ((read_from TLBXContext_ref) s)) else + if reg_name = (''TLBEntryHi'') then Some ((regval_of TLBEntryHi_ref) ((read_from TLBEntryHi_ref) s)) else + if reg_name = (''TLBWired'') then Some ((regval_of TLBWired_ref) ((read_from TLBWired_ref) s)) else + if reg_name = (''TLBPageMask'') then Some ((regval_of TLBPageMask_ref) ((read_from TLBPageMask_ref) s)) else + if reg_name = (''TLBContext'') then Some ((regval_of TLBContext_ref) ((read_from TLBContext_ref) s)) else + if reg_name = (''TLBEntryLo1'') then Some ((regval_of TLBEntryLo1_ref) ((read_from TLBEntryLo1_ref) s)) else + if reg_name = (''TLBEntryLo0'') then Some ((regval_of TLBEntryLo0_ref) ((read_from TLBEntryLo0_ref) s)) else + if reg_name = (''TLBRandom'') then Some ((regval_of TLBRandom_ref) ((read_from TLBRandom_ref) s)) else + if reg_name = (''TLBIndex'') then Some ((regval_of TLBIndex_ref) ((read_from TLBIndex_ref) s)) else + if reg_name = (''TLBProbe'') then Some ((regval_of TLBProbe_ref) ((read_from TLBProbe_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \ register_value \ regstate \(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''instCount'') then map_option (\ v . (write_to instCount_ref) v s) ((of_regval instCount_ref) v) else + if reg_name = (''CapCause'') then map_option (\ v . (write_to CapCause_ref) v s) ((of_regval CapCause_ref) v) else + if reg_name = (''CTLSP'') then map_option (\ v . (write_to CTLSP_ref) v s) ((of_regval CTLSP_ref) v) else + if reg_name = (''CTLSU'') then map_option (\ v . (write_to CTLSU_ref) v s) ((of_regval CTLSU_ref) v) else + if reg_name = (''C30'') then map_option (\ v . (write_to C30_ref) v s) ((of_regval C30_ref) v) else + if reg_name = (''C28'') then map_option (\ v . (write_to C28_ref) v s) ((of_regval C28_ref) v) else + if reg_name = (''C27'') then map_option (\ v . (write_to C27_ref) v s) ((of_regval C27_ref) v) else + if reg_name = (''C26'') then map_option (\ v . (write_to C26_ref) v s) ((of_regval C26_ref) v) else + if reg_name = (''C25'') then map_option (\ v . (write_to C25_ref) v s) ((of_regval C25_ref) v) else + if reg_name = (''C24'') then map_option (\ v . (write_to C24_ref) v s) ((of_regval C24_ref) v) else + if reg_name = (''C23'') then map_option (\ v . (write_to C23_ref) v s) ((of_regval C23_ref) v) else + if reg_name = (''C22'') then map_option (\ v . (write_to C22_ref) v s) ((of_regval C22_ref) v) else + if reg_name = (''C21'') then map_option (\ v . (write_to C21_ref) v s) ((of_regval C21_ref) v) else + if reg_name = (''C20'') then map_option (\ v . (write_to C20_ref) v s) ((of_regval C20_ref) v) else + if reg_name = (''C19'') then map_option (\ v . (write_to C19_ref) v s) ((of_regval C19_ref) v) else + if reg_name = (''C18'') then map_option (\ v . (write_to C18_ref) v s) ((of_regval C18_ref) v) else + if reg_name = (''C17'') then map_option (\ v . (write_to C17_ref) v s) ((of_regval C17_ref) v) else + if reg_name = (''C16'') then map_option (\ v . (write_to C16_ref) v s) ((of_regval C16_ref) v) else + if reg_name = (''C15'') then map_option (\ v . (write_to C15_ref) v s) ((of_regval C15_ref) v) else + if reg_name = (''C14'') then map_option (\ v . (write_to C14_ref) v s) ((of_regval C14_ref) v) else + if reg_name = (''C13'') then map_option (\ v . (write_to C13_ref) v s) ((of_regval C13_ref) v) else + if reg_name = (''C12'') then map_option (\ v . (write_to C12_ref) v s) ((of_regval C12_ref) v) else + if reg_name = (''C11'') then map_option (\ v . (write_to C11_ref) v s) ((of_regval C11_ref) v) else + if reg_name = (''C10'') then map_option (\ v . (write_to C10_ref) v s) ((of_regval C10_ref) v) else + if reg_name = (''C09'') then map_option (\ v . (write_to C09_ref) v s) ((of_regval C09_ref) v) else + if reg_name = (''C08'') then map_option (\ v . (write_to C08_ref) v s) ((of_regval C08_ref) v) else + if reg_name = (''C07'') then map_option (\ v . (write_to C07_ref) v s) ((of_regval C07_ref) v) else + if reg_name = (''C06'') then map_option (\ v . (write_to C06_ref) v s) ((of_regval C06_ref) v) else + if reg_name = (''C05'') then map_option (\ v . (write_to C05_ref) v s) ((of_regval C05_ref) v) else + if reg_name = (''C04'') then map_option (\ v . (write_to C04_ref) v s) ((of_regval C04_ref) v) else + if reg_name = (''C03'') then map_option (\ v . (write_to C03_ref) v s) ((of_regval C03_ref) v) else + if reg_name = (''C02'') then map_option (\ v . (write_to C02_ref) v s) ((of_regval C02_ref) v) else + if reg_name = (''C01'') then map_option (\ v . (write_to C01_ref) v s) ((of_regval C01_ref) v) else + if reg_name = (''C00'') then map_option (\ v . (write_to C00_ref) v s) ((of_regval C00_ref) v) else + if reg_name = (''inCCallDelay'') then map_option (\ v . (write_to inCCallDelay_ref) v s) ((of_regval inCCallDelay_ref) v) else + if reg_name = (''nextPCC'') then map_option (\ v . (write_to nextPCC_ref) v s) ((of_regval nextPCC_ref) v) else + if reg_name = (''delayedPCC'') then map_option (\ v . (write_to delayedPCC_ref) v s) ((of_regval delayedPCC_ref) v) else + if reg_name = (''PCC'') then map_option (\ v . (write_to PCC_ref) v s) ((of_regval PCC_ref) v) else + if reg_name = (''C31'') then map_option (\ v . (write_to C31_ref) v s) ((of_regval C31_ref) v) else + if reg_name = (''C29'') then map_option (\ v . (write_to C29_ref) v s) ((of_regval C29_ref) v) else + if reg_name = (''UART_RVALID'') then map_option (\ v . (write_to UART_RVALID_ref) v s) ((of_regval UART_RVALID_ref) v) else + if reg_name = (''UART_RDATA'') then map_option (\ v . (write_to UART_RDATA_ref) v s) ((of_regval UART_RDATA_ref) v) else + if reg_name = (''UART_WRITTEN'') then map_option (\ v . (write_to UART_WRITTEN_ref) v s) ((of_regval UART_WRITTEN_ref) v) else + if reg_name = (''UART_WDATA'') then map_option (\ v . (write_to UART_WDATA_ref) v s) ((of_regval UART_WDATA_ref) v) else + if reg_name = (''GPR'') then map_option (\ v . (write_to GPR_ref) v s) ((of_regval GPR_ref) v) else + if reg_name = (''LO'') then map_option (\ v . (write_to LO_ref) v s) ((of_regval LO_ref) v) else + if reg_name = (''HI'') then map_option (\ v . (write_to HI_ref) v s) ((of_regval HI_ref) v) else + if reg_name = (''delayedPC'') then map_option (\ v . (write_to delayedPC_ref) v s) ((of_regval delayedPC_ref) v) else + if reg_name = (''inBranchDelay'') then map_option (\ v . (write_to inBranchDelay_ref) v s) ((of_regval inBranchDelay_ref) v) else + if reg_name = (''branchPending'') then map_option (\ v . (write_to branchPending_ref) v s) ((of_regval branchPending_ref) v) else + if reg_name = (''CP0Status'') then map_option (\ v . (write_to CP0Status_ref) v s) ((of_regval CP0Status_ref) v) else + if reg_name = (''CP0UserLocal'') then map_option (\ v . (write_to CP0UserLocal_ref) v s) ((of_regval CP0UserLocal_ref) v) else + if reg_name = (''CP0HWREna'') then map_option (\ v . (write_to CP0HWREna_ref) v s) ((of_regval CP0HWREna_ref) v) else + if reg_name = (''CP0Count'') then map_option (\ v . (write_to CP0Count_ref) v s) ((of_regval CP0Count_ref) v) else + if reg_name = (''CP0BadVAddr'') then map_option (\ v . (write_to CP0BadVAddr_ref) v s) ((of_regval CP0BadVAddr_ref) v) else + if reg_name = (''CP0LLAddr'') then map_option (\ v . (write_to CP0LLAddr_ref) v s) ((of_regval CP0LLAddr_ref) v) else + if reg_name = (''CP0LLBit'') then map_option (\ v . (write_to CP0LLBit_ref) v s) ((of_regval CP0LLBit_ref) v) else + if reg_name = (''CP0ErrorEPC'') then map_option (\ v . (write_to CP0ErrorEPC_ref) v s) ((of_regval CP0ErrorEPC_ref) v) else + if reg_name = (''CP0EPC'') then map_option (\ v . (write_to CP0EPC_ref) v s) ((of_regval CP0EPC_ref) v) else + if reg_name = (''CP0Cause'') then map_option (\ v . (write_to CP0Cause_ref) v s) ((of_regval CP0Cause_ref) v) else + if reg_name = (''CP0Compare'') then map_option (\ v . (write_to CP0Compare_ref) v s) ((of_regval CP0Compare_ref) v) else + if reg_name = (''TLBEntry63'') then map_option (\ v . (write_to TLBEntry63_ref) v s) ((of_regval TLBEntry63_ref) v) else + if reg_name = (''TLBEntry62'') then map_option (\ v . (write_to TLBEntry62_ref) v s) ((of_regval TLBEntry62_ref) v) else + if reg_name = (''TLBEntry61'') then map_option (\ v . (write_to TLBEntry61_ref) v s) ((of_regval TLBEntry61_ref) v) else + if reg_name = (''TLBEntry60'') then map_option (\ v . (write_to TLBEntry60_ref) v s) ((of_regval TLBEntry60_ref) v) else + if reg_name = (''TLBEntry59'') then map_option (\ v . (write_to TLBEntry59_ref) v s) ((of_regval TLBEntry59_ref) v) else + if reg_name = (''TLBEntry58'') then map_option (\ v . (write_to TLBEntry58_ref) v s) ((of_regval TLBEntry58_ref) v) else + if reg_name = (''TLBEntry57'') then map_option (\ v . (write_to TLBEntry57_ref) v s) ((of_regval TLBEntry57_ref) v) else + if reg_name = (''TLBEntry56'') then map_option (\ v . (write_to TLBEntry56_ref) v s) ((of_regval TLBEntry56_ref) v) else + if reg_name = (''TLBEntry55'') then map_option (\ v . (write_to TLBEntry55_ref) v s) ((of_regval TLBEntry55_ref) v) else + if reg_name = (''TLBEntry54'') then map_option (\ v . (write_to TLBEntry54_ref) v s) ((of_regval TLBEntry54_ref) v) else + if reg_name = (''TLBEntry53'') then map_option (\ v . (write_to TLBEntry53_ref) v s) ((of_regval TLBEntry53_ref) v) else + if reg_name = (''TLBEntry52'') then map_option (\ v . (write_to TLBEntry52_ref) v s) ((of_regval TLBEntry52_ref) v) else + if reg_name = (''TLBEntry51'') then map_option (\ v . (write_to TLBEntry51_ref) v s) ((of_regval TLBEntry51_ref) v) else + if reg_name = (''TLBEntry50'') then map_option (\ v . (write_to TLBEntry50_ref) v s) ((of_regval TLBEntry50_ref) v) else + if reg_name = (''TLBEntry49'') then map_option (\ v . (write_to TLBEntry49_ref) v s) ((of_regval TLBEntry49_ref) v) else + if reg_name = (''TLBEntry48'') then map_option (\ v . (write_to TLBEntry48_ref) v s) ((of_regval TLBEntry48_ref) v) else + if reg_name = (''TLBEntry47'') then map_option (\ v . (write_to TLBEntry47_ref) v s) ((of_regval TLBEntry47_ref) v) else + if reg_name = (''TLBEntry46'') then map_option (\ v . (write_to TLBEntry46_ref) v s) ((of_regval TLBEntry46_ref) v) else + if reg_name = (''TLBEntry45'') then map_option (\ v . (write_to TLBEntry45_ref) v s) ((of_regval TLBEntry45_ref) v) else + if reg_name = (''TLBEntry44'') then map_option (\ v . (write_to TLBEntry44_ref) v s) ((of_regval TLBEntry44_ref) v) else + if reg_name = (''TLBEntry43'') then map_option (\ v . (write_to TLBEntry43_ref) v s) ((of_regval TLBEntry43_ref) v) else + if reg_name = (''TLBEntry42'') then map_option (\ v . (write_to TLBEntry42_ref) v s) ((of_regval TLBEntry42_ref) v) else + if reg_name = (''TLBEntry41'') then map_option (\ v . (write_to TLBEntry41_ref) v s) ((of_regval TLBEntry41_ref) v) else + if reg_name = (''TLBEntry40'') then map_option (\ v . (write_to TLBEntry40_ref) v s) ((of_regval TLBEntry40_ref) v) else + if reg_name = (''TLBEntry39'') then map_option (\ v . (write_to TLBEntry39_ref) v s) ((of_regval TLBEntry39_ref) v) else + if reg_name = (''TLBEntry38'') then map_option (\ v . (write_to TLBEntry38_ref) v s) ((of_regval TLBEntry38_ref) v) else + if reg_name = (''TLBEntry37'') then map_option (\ v . (write_to TLBEntry37_ref) v s) ((of_regval TLBEntry37_ref) v) else + if reg_name = (''TLBEntry36'') then map_option (\ v . (write_to TLBEntry36_ref) v s) ((of_regval TLBEntry36_ref) v) else + if reg_name = (''TLBEntry35'') then map_option (\ v . (write_to TLBEntry35_ref) v s) ((of_regval TLBEntry35_ref) v) else + if reg_name = (''TLBEntry34'') then map_option (\ v . (write_to TLBEntry34_ref) v s) ((of_regval TLBEntry34_ref) v) else + if reg_name = (''TLBEntry33'') then map_option (\ v . (write_to TLBEntry33_ref) v s) ((of_regval TLBEntry33_ref) v) else + if reg_name = (''TLBEntry32'') then map_option (\ v . (write_to TLBEntry32_ref) v s) ((of_regval TLBEntry32_ref) v) else + if reg_name = (''TLBEntry31'') then map_option (\ v . (write_to TLBEntry31_ref) v s) ((of_regval TLBEntry31_ref) v) else + if reg_name = (''TLBEntry30'') then map_option (\ v . (write_to TLBEntry30_ref) v s) ((of_regval TLBEntry30_ref) v) else + if reg_name = (''TLBEntry29'') then map_option (\ v . (write_to TLBEntry29_ref) v s) ((of_regval TLBEntry29_ref) v) else + if reg_name = (''TLBEntry28'') then map_option (\ v . (write_to TLBEntry28_ref) v s) ((of_regval TLBEntry28_ref) v) else + if reg_name = (''TLBEntry27'') then map_option (\ v . (write_to TLBEntry27_ref) v s) ((of_regval TLBEntry27_ref) v) else + if reg_name = (''TLBEntry26'') then map_option (\ v . (write_to TLBEntry26_ref) v s) ((of_regval TLBEntry26_ref) v) else + if reg_name = (''TLBEntry25'') then map_option (\ v . (write_to TLBEntry25_ref) v s) ((of_regval TLBEntry25_ref) v) else + if reg_name = (''TLBEntry24'') then map_option (\ v . (write_to TLBEntry24_ref) v s) ((of_regval TLBEntry24_ref) v) else + if reg_name = (''TLBEntry23'') then map_option (\ v . (write_to TLBEntry23_ref) v s) ((of_regval TLBEntry23_ref) v) else + if reg_name = (''TLBEntry22'') then map_option (\ v . (write_to TLBEntry22_ref) v s) ((of_regval TLBEntry22_ref) v) else + if reg_name = (''TLBEntry21'') then map_option (\ v . (write_to TLBEntry21_ref) v s) ((of_regval TLBEntry21_ref) v) else + if reg_name = (''TLBEntry20'') then map_option (\ v . (write_to TLBEntry20_ref) v s) ((of_regval TLBEntry20_ref) v) else + if reg_name = (''TLBEntry19'') then map_option (\ v . (write_to TLBEntry19_ref) v s) ((of_regval TLBEntry19_ref) v) else + if reg_name = (''TLBEntry18'') then map_option (\ v . (write_to TLBEntry18_ref) v s) ((of_regval TLBEntry18_ref) v) else + if reg_name = (''TLBEntry17'') then map_option (\ v . (write_to TLBEntry17_ref) v s) ((of_regval TLBEntry17_ref) v) else + if reg_name = (''TLBEntry16'') then map_option (\ v . (write_to TLBEntry16_ref) v s) ((of_regval TLBEntry16_ref) v) else + if reg_name = (''TLBEntry15'') then map_option (\ v . (write_to TLBEntry15_ref) v s) ((of_regval TLBEntry15_ref) v) else + if reg_name = (''TLBEntry14'') then map_option (\ v . (write_to TLBEntry14_ref) v s) ((of_regval TLBEntry14_ref) v) else + if reg_name = (''TLBEntry13'') then map_option (\ v . (write_to TLBEntry13_ref) v s) ((of_regval TLBEntry13_ref) v) else + if reg_name = (''TLBEntry12'') then map_option (\ v . (write_to TLBEntry12_ref) v s) ((of_regval TLBEntry12_ref) v) else + if reg_name = (''TLBEntry11'') then map_option (\ v . (write_to TLBEntry11_ref) v s) ((of_regval TLBEntry11_ref) v) else + if reg_name = (''TLBEntry10'') then map_option (\ v . (write_to TLBEntry10_ref) v s) ((of_regval TLBEntry10_ref) v) else + if reg_name = (''TLBEntry09'') then map_option (\ v . (write_to TLBEntry09_ref) v s) ((of_regval TLBEntry09_ref) v) else + if reg_name = (''TLBEntry08'') then map_option (\ v . (write_to TLBEntry08_ref) v s) ((of_regval TLBEntry08_ref) v) else + if reg_name = (''TLBEntry07'') then map_option (\ v . (write_to TLBEntry07_ref) v s) ((of_regval TLBEntry07_ref) v) else + if reg_name = (''TLBEntry06'') then map_option (\ v . (write_to TLBEntry06_ref) v s) ((of_regval TLBEntry06_ref) v) else + if reg_name = (''TLBEntry05'') then map_option (\ v . (write_to TLBEntry05_ref) v s) ((of_regval TLBEntry05_ref) v) else + if reg_name = (''TLBEntry04'') then map_option (\ v . (write_to TLBEntry04_ref) v s) ((of_regval TLBEntry04_ref) v) else + if reg_name = (''TLBEntry03'') then map_option (\ v . (write_to TLBEntry03_ref) v s) ((of_regval TLBEntry03_ref) v) else + if reg_name = (''TLBEntry02'') then map_option (\ v . (write_to TLBEntry02_ref) v s) ((of_regval TLBEntry02_ref) v) else + if reg_name = (''TLBEntry01'') then map_option (\ v . (write_to TLBEntry01_ref) v s) ((of_regval TLBEntry01_ref) v) else + if reg_name = (''TLBEntry00'') then map_option (\ v . (write_to TLBEntry00_ref) v s) ((of_regval TLBEntry00_ref) v) else + if reg_name = (''TLBXContext'') then map_option (\ v . (write_to TLBXContext_ref) v s) ((of_regval TLBXContext_ref) v) else + if reg_name = (''TLBEntryHi'') then map_option (\ v . (write_to TLBEntryHi_ref) v s) ((of_regval TLBEntryHi_ref) v) else + if reg_name = (''TLBWired'') then map_option (\ v . (write_to TLBWired_ref) v s) ((of_regval TLBWired_ref) v) else + if reg_name = (''TLBPageMask'') then map_option (\ v . (write_to TLBPageMask_ref) v s) ((of_regval TLBPageMask_ref) v) else + if reg_name = (''TLBContext'') then map_option (\ v . (write_to TLBContext_ref) v s) ((of_regval TLBContext_ref) v) else + if reg_name = (''TLBEntryLo1'') then map_option (\ v . (write_to TLBEntryLo1_ref) v s) ((of_regval TLBEntryLo1_ref) v) else + if reg_name = (''TLBEntryLo0'') then map_option (\ v . (write_to TLBEntryLo0_ref) v s) ((of_regval TLBEntryLo0_ref) v) else + if reg_name = (''TLBRandom'') then map_option (\ v . (write_to TLBRandom_ref) v s) ((of_regval TLBRandom_ref) v) else + if reg_name = (''TLBIndex'') then map_option (\ v . (write_to TLBIndex_ref) v s) ((of_regval TLBIndex_ref) v) else + if reg_name = (''TLBProbe'') then map_option (\ v . (write_to TLBProbe_ref) v s) ((of_regval TLBProbe_ref) v) else + if reg_name = (''nextPC'') then map_option (\ v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\ v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \ regstate \(register_value)option)*(string \ register_value \ regstate \(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end diff --git a/snapshots/isabelle/cheri/Mips_extras.thy b/snapshots/isabelle/cheri/Mips_extras.thy new file mode 100644 index 00000000..c0379d3a --- /dev/null +++ b/snapshots/isabelle/cheri/Mips_extras.thy @@ -0,0 +1,251 @@ +chapter \Generated by Lem from /auto/homes/tb592/REMS/rems/sail/mips/mips_extras.lem.\ + +theory "Mips_extras" + +imports + Main + "Lem_pervasives" + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Prompt_monad" + "Prompt" + "Sail_operators" + +begin + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) + +definition MEMr :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \('regval,'b,'e)monad " where + " MEMr dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 )" + +definition MEMr_reserve :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \('regval,'b,'e)monad " where + " MEMr_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1 )" + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +definition read_tag_bool :: " 'a Bitvector_class \ 'a \('regval,(bool),'e)monad " where + " read_tag_bool dict_Sail_values_Bitvector_a addr = ( + read_tag dict_Sail_values_Bitvector_a addr \ (\ t . + maybe_fail (''read_tag_bool'') (bool_of_bitU t)))" + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +definition write_tag_bool :: " 'a Bitvector_class \ 'a \ bool \('regval,(unit),'e)monad " where + " write_tag_bool dict_Sail_values_Bitvector_a addr t = ( write_tag + dict_Sail_values_Bitvector_a addr (bitU_of_bool t) \ + (\x . (case x of _ => return () )) )" + + +definition MEMr_tag :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \('regval,(bool*'b),'e)monad " where + " MEMr_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \ (\ v . + read_tag_bool dict_Sail_values_Bitvector_a addr \ (\ t . + return (t, v))))" + + +definition MEMr_tag_reserve :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \('regval,(bool*'b),'e)monad " where + " MEMr_tag_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \ (\ v . + read_tag_bool dict_Sail_values_Bitvector_a addr \ (\ t . + return (t, v))))" + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) + +definition MEMea :: " 'a Bitvector_class \ 'a \ int \('regval,(unit),'e)monad " where + " MEMea dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_conditional :: " 'a Bitvector_class \ 'a \ int \('regval,(unit),'e)monad " where + " MEMea_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + +definition MEMea_tag :: " 'a Bitvector_class \ 'a \ int \('regval,(unit),'e)monad " where + " MEMea_tag dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_tag_conditional :: " 'a Bitvector_class \ 'a \ int \('regval,(unit),'e)monad " where + " MEMea_tag_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) + +definition MEMval :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ 'b \('regval,(unit),'e)monad " where + " MEMval dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \ (\x . (case x of _ => return () )) )" + +definition MEMval_conditional :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ 'b \('regval,(bool),'e)monad " where + " MEMval_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \ (\ b . return (if b then True else False)))" + +definition MEMval_tag :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ bool \ 'b \('regval,(unit),'e)monad " where + " MEMval_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \ (\x . (case x of + _ => write_tag_bool dict_Sail_values_Bitvector_a addr t + \ + (\x . (case x of _ => return () )) + )) )" + +definition MEMval_tag_conditional :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ bool \ 'b \('regval,(bool),'e)monad " where + " MEMval_tag_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \ (\ b . write_tag_bool + dict_Sail_values_Bitvector_a addr t \ (\x . (case x of _ => return (if b then True else False) ))))" + + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +definition MEM_sync :: " unit \('regval,(unit),'e)monad " where + " MEM_sync _ = ( barrier Barrier_MIPS_SYNC )" + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +definition get_slice_int_bl :: " int \ int \ int \(bool)list " where + " get_slice_int_bl len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + subrange_list False bs hi lo)))" + + +(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +definition get_slice_int0 :: " 'a Bitvector_class \ int \ int \ int \ 'a " where + " get_slice_int0 dict_Sail_values_Bitvector_a len n lo = ( + (of_bools_method dict_Sail_values_Bitvector_a) (get_slice_int_bl len n lo))" + + +definition write_ram :: " 'a Bitvector_class \ 'b Bitvector_class \ 'e \ int \ 'f \ 'b \ 'a \('d,(unit),'c)monad " where + " write_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data = ( + MEMea dict_Sail_values_Bitvector_b addr size1 \ + MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data )" + + +definition read_ram :: " 'a Bitvector_class \ 'c Bitvector_class \ 'e \ int \ 'f \ 'a \('d,'c,'b)monad " where + " read_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr = ( MEMr + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1 )" + + +definition string_of_bits :: " 'a Bitvector_class \ 'a \ string " where + " string_of_bits dict_Sail_values_Bitvector_a bs = ( string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ((bits_of_method dict_Sail_values_Bitvector_a) bs))" + +definition string_of_int :: " 'a Show_class \ 'a \ string " where + " string_of_int dict_Show_Show_a = ((show_method dict_Show_Show_a))" + + +definition sign_extend0 :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ 'b " where + " sign_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (exts_bv dict_Sail_values_Bitvector_a len bits)))" + +definition zero_extend0 :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ int \ 'b " where + " zero_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (extz_bv dict_Sail_values_Bitvector_a len bits)))" + + +definition shift_bits_left :: " 'b Bitvector_class \ 'd Bitvector_class \ 'e Bitvector_class \ 'd \ 'e \('c,'b,'a)monad " where + " shift_bits_left dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\ n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_left'') r))" + +definition shift_bits_right :: " 'b Bitvector_class \ 'd Bitvector_class \ 'e Bitvector_class \ 'd \ 'e \('c,'b,'a)monad " where + " shift_bits_right dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\ n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right'') r))" + +definition shift_bits_right_arith :: " 'b Bitvector_class \ 'd Bitvector_class \ 'e Bitvector_class \ 'd \ 'e \('c,'b,'a)monad " where + " shift_bits_right_arith dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\ n . (of_bits_method dict_Sail_values_Bitvector_b) (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right_arith'') r))" + + +(* Use constants for undefined values for now *) +definition internal_pick :: " 'a list \('c,'a,'b)monad " where + " internal_pick vs = ( return (List.hd vs))" + +definition undefined_string :: " unit \('b,(string),'a)monad " where + " undefined_string _ = ( return (''''))" + +definition undefined_unit :: " unit \('b,(unit),'a)monad " where + " undefined_unit _ = ( return () )" + +definition undefined_int :: " unit \('b,(int),'a)monad " where + " undefined_int _ = ( return (( 0 :: int)::ii))" + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +definition undefined_vector :: " int \ 'a \('rv,('a list),'e)monad " where + " undefined_vector len u = ( return (repeat [u] len))" + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bitvector :: " 'a Bitvector_class \ int \('rv,'a,'e)monad " where + " undefined_bitvector dict_Sail_values_Bitvector_a len = ( return ( + (of_bools_method dict_Sail_values_Bitvector_a) (repeat [False] len)))" + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bits :: " 'a Bitvector_class \ int \('rv,'a,'e)monad " where + " undefined_bits dict_Sail_values_Bitvector_a = ( + undefined_bitvector dict_Sail_values_Bitvector_a )" + +definition undefined_bit :: " unit \('b,(bitU),'a)monad " where + " undefined_bit _ = ( return B0 )" + +definition undefined_real :: " unit \('b,(real),'a)monad " where + " undefined_real _ = ( return (realFromFrac(( 0 :: int))(( 1 :: int))))" + +definition undefined_range :: " 'a \ 'd \('c,'a,'b)monad " where + " undefined_range i j = ( return i )" + +definition undefined_atom :: " 'a \('c,'a,'b)monad " where + " undefined_atom i = ( return i )" + +definition undefined_nat :: " unit \('b,(int),'a)monad " where + " undefined_nat _ = ( return (( 0 :: int)::ii))" + + +definition skip :: " unit \('b,(unit),'a)monad " where + " skip _ = ( return () )" + + +(*val elf_entry : unit -> integer*) +definition elf_entry :: " unit \ int " where + " elf_entry _ = (( 0 :: int))" + + +definition print_bits :: " 'a Bitvector_class \ string \ 'a \ unit " where + " print_bits dict_Sail_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bits + dict_Sail_values_Bitvector_a bs)))" + + +(*val get_time_ns : unit -> integer*) +definition get_time_ns :: " unit \ int " where + " get_time_ns _ = (( 0 :: int))" + +end diff --git a/snapshots/isabelle/lib/lem/LICENSE b/snapshots/isabelle/lib/lem/LICENSE new file mode 100644 index 00000000..06f7abfe --- /dev/null +++ b/snapshots/isabelle/lib/lem/LICENSE @@ -0,0 +1,524 @@ + Lem + +All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} +are distributed under the following license: + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. +3. The names of the authors may not be used to endorse or promote +products derived from this software without specific prior written +permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + + + +The following files are modified versions of map and set from the +Objective Caml library and are distributed under the GNU LIBRARY GENERAL +PUBLIC LICENSE Version 2 as below. + +ocaml-lib/pmap.mli +ocaml-lib/pmap.ml +ocaml-lib/pset.mli +ocaml-lib/pset.ml + + + GNU LIBRARY GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1991 Free Software Foundation, Inc. + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +[This is the first released version of the library GPL. It is + numbered 2 because it goes with version 2 of the ordinary GPL.] + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +Licenses are intended to guarantee your freedom to share and change +free software--to make sure the software is free for all its users. + + This license, the Library General Public License, applies to some +specially designated Free Software Foundation software, and to any +other libraries whose authors decide to use it. You can use it for +your libraries, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if +you distribute copies of the library, or if you modify it. + + For example, if you distribute copies of the library, whether gratis +or for a fee, you must give the recipients all the rights that we gave +you. You must make sure that they, too, receive or can get the source +code. If you link a program with the library, you must provide +complete object files to the recipients so that they can relink them +with the library, after making changes to the library and recompiling +it. And you must show them these terms so they know their rights. + + Our method of protecting your rights has two steps: (1) copyright +the library, and (2) offer you this license which gives you legal +permission to copy, distribute and/or modify the library. + + Also, for each distributor's protection, we want to make certain +that everyone understands that there is no warranty for this free +library. If the library is modified by someone else and passed on, we +want its recipients to know that what they have is not the original +version, so that any problems introduced by others will not reflect on +the original authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that companies distributing free +software will individually obtain patent licenses, thus in effect +transforming the program into proprietary software. To prevent this, +we have made it clear that any patent must be licensed for everyone's +free use or not licensed at all. + + Most GNU software, including some libraries, is covered by the ordinary +GNU General Public License, which was designed for utility programs. This +license, the GNU Library General Public License, applies to certain +designated libraries. This license is quite different from the ordinary +one; be sure to read it in full, and don't assume that anything in it is +the same as in the ordinary license. + + The reason we have a separate public license for some libraries is that +they blur the distinction we usually make between modifying or adding to a +program and simply using it. Linking a program with a library, without +changing the library, is in some sense simply using the library, and is +analogous to running a utility program or application program. However, in +a textual and legal sense, the linked executable is a combined work, a +derivative of the original library, and the ordinary General Public License +treats it as such. + + Because of this blurred distinction, using the ordinary General +Public License for libraries did not effectively promote software +sharing, because most developers did not use the libraries. We +concluded that weaker conditions might promote sharing better. + + However, unrestricted linking of non-free programs would deprive the +users of those programs of all benefit from the free status of the +libraries themselves. This Library General Public License is intended to +permit developers of non-free programs to use free libraries, while +preserving your freedom as a user of such programs to change the free +libraries that are incorporated in them. (We have not seen how to achieve +this as regards changes in header files, but we have achieved it as regards +changes in the actual functions of the Library.) The hope is that this +will lead to faster development of free libraries. + + The precise terms and conditions for copying, distribution and +modification follow. Pay close attention to the difference between a +"work based on the library" and a "work that uses the library". The +former contains code derived from the library, while the latter only +works together with the library. + + Note that it is possible for a library to be covered by the ordinary +General Public License rather than by this special one. + + GNU LIBRARY GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License Agreement applies to any software library which +contains a notice placed by the copyright holder or other authorized +party saying it may be distributed under the terms of this Library +General Public License (also called "this License"). Each licensee is +addressed as "you". + + A "library" means a collection of software functions and/or data +prepared so as to be conveniently linked with application programs +(which use some of those functions and data) to form executables. + + The "Library", below, refers to any such software library or work +which has been distributed under these terms. A "work based on the +Library" means either the Library or any derivative work under +copyright law: that is to say, a work containing the Library or a +portion of it, either verbatim or with modifications and/or translated +straightforwardly into another language. (Hereinafter, translation is +included without limitation in the term "modification".) + + "Source code" for a work means the preferred form of the work for +making modifications to it. For a library, complete source code means +all the source code for all modules it contains, plus any associated +interface definition files, plus the scripts used to control compilation +and installation of the library. + + Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running a program using the Library is not restricted, and output from +such a program is covered only if its contents constitute a work based +on the Library (independent of the use of the Library in a tool for +writing it). Whether that is true depends on what the Library does +and what the program that uses the Library does. + + 1. You may copy and distribute verbatim copies of the Library's +complete source code as you receive it, in any medium, provided that +you conspicuously and appropriately publish on each copy an +appropriate copyright notice and disclaimer of warranty; keep intact +all the notices that refer to this License and to the absence of any +warranty; and distribute a copy of this License along with the +Library. + + You may charge a fee for the physical act of transferring a copy, +and you may at your option offer warranty protection in exchange for a +fee. + + 2. You may modify your copy or copies of the Library or any portion +of it, thus forming a work based on the Library, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) The modified work must itself be a software library. + + b) You must cause the files modified to carry prominent notices + stating that you changed the files and the date of any change. + + c) You must cause the whole of the work to be licensed at no + charge to all third parties under the terms of this License. + + d) If a facility in the modified Library refers to a function or a + table of data to be supplied by an application program that uses + the facility, other than as an argument passed when the facility + is invoked, then you must make a good faith effort to ensure that, + in the event an application does not supply such function or + table, the facility still operates, and performs whatever part of + its purpose remains meaningful. + + (For example, a function in a library to compute square roots has + a purpose that is entirely well-defined independent of the + application. Therefore, Subsection 2d requires that any + application-supplied function or table used by this function must + be optional: if the application does not supply it, the square + root function must still compute square roots.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Library, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Library, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote +it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Library. + +In addition, mere aggregation of another work not based on the Library +with the Library (or with a work based on the Library) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may opt to apply the terms of the ordinary GNU General Public +License instead of this License to a given copy of the Library. To do +this, you must alter all the notices that refer to this License, so +that they refer to the ordinary GNU General Public License, version 2, +instead of to this License. (If a newer version than version 2 of the +ordinary GNU General Public License has appeared, then you can specify +that version instead if you wish.) Do not make any other change in +these notices. + + Once this change is made in a given copy, it is irreversible for +that copy, so the ordinary GNU General Public License applies to all +subsequent copies and derivative works made from that copy. + + This option is useful when you wish to copy part of the code of +the Library into a program that is not a library. + + 4. You may copy and distribute the Library (or a portion or +derivative of it, under Section 2) in object code or executable form +under the terms of Sections 1 and 2 above provided that you accompany +it with the complete corresponding machine-readable source code, which +must be distributed under the terms of Sections 1 and 2 above on a +medium customarily used for software interchange. + + If distribution of object code is made by offering access to copy +from a designated place, then offering equivalent access to copy the +source code from the same place satisfies the requirement to +distribute the source code, even though third parties are not +compelled to copy the source along with the object code. + + 5. A program that contains no derivative of any portion of the +Library, but is designed to work with the Library by being compiled or +linked with it, is called a "work that uses the Library". Such a +work, in isolation, is not a derivative work of the Library, and +therefore falls outside the scope of this License. + + However, linking a "work that uses the Library" with the Library +creates an executable that is a derivative of the Library (because it +contains portions of the Library), rather than a "work that uses the +library". The executable is therefore covered by this License. +Section 6 states terms for distribution of such executables. + + When a "work that uses the Library" uses material from a header file +that is part of the Library, the object code for the work may be a +derivative work of the Library even though the source code is not. +Whether this is true is especially significant if the work can be +linked without the Library, or if the work is itself a library. The +threshold for this to be true is not precisely defined by law. + + If such an object file uses only numerical parameters, data +structure layouts and accessors, and small macros and small inline +functions (ten lines or less in length), then the use of the object +file is unrestricted, regardless of whether it is legally a derivative +work. (Executables containing this object code plus portions of the +Library will still fall under Section 6.) + + Otherwise, if the work is a derivative of the Library, you may +distribute the object code for the work under the terms of Section 6. +Any executables containing that work also fall under Section 6, +whether or not they are linked directly with the Library itself. + + 6. As an exception to the Sections above, you may also compile or +link a "work that uses the Library" with the Library to produce a +work containing portions of the Library, and distribute that work +under terms of your choice, provided that the terms permit +modification of the work for the customer's own use and reverse +engineering for debugging such modifications. + + You must give prominent notice with each copy of the work that the +Library is used in it and that the Library and its use are covered by +this License. You must supply a copy of this License. If the work +during execution displays copyright notices, you must include the +copyright notice for the Library among them, as well as a reference +directing the user to the copy of this License. Also, you must do one +of these things: + + a) Accompany the work with the complete corresponding + machine-readable source code for the Library including whatever + changes were used in the work (which must be distributed under + Sections 1 and 2 above); and, if the work is an executable linked + with the Library, with the complete machine-readable "work that + uses the Library", as object code and/or source code, so that the + user can modify the Library and then relink to produce a modified + executable containing the modified Library. (It is understood + that the user who changes the contents of definitions files in the + Library will not necessarily be able to recompile the application + to use the modified definitions.) + + b) Accompany the work with a written offer, valid for at + least three years, to give the same user the materials + specified in Subsection 6a, above, for a charge no more + than the cost of performing this distribution. + + c) If distribution of the work is made by offering access to copy + from a designated place, offer equivalent access to copy the above + specified materials from the same place. + + d) Verify that the user has already received a copy of these + materials or that you have already sent this user a copy. + + For an executable, the required form of the "work that uses the +Library" must include any data and utility programs needed for +reproducing the executable from it. However, as a special exception, +the source code distributed need not include anything that is normally +distributed (in either source or binary form) with the major +components (compiler, kernel, and so on) of the operating system on +which the executable runs, unless that component itself accompanies +the executable. + + It may happen that this requirement contradicts the license +restrictions of other proprietary libraries that do not normally +accompany the operating system. Such a contradiction means you cannot +use both them and the Library together in an executable that you +distribute. + + 7. You may place library facilities that are a work based on the +Library side-by-side in a single library together with other library +facilities not covered by this License, and distribute such a combined +library, provided that the separate distribution of the work based on +the Library and of the other library facilities is otherwise +permitted, and provided that you do these two things: + + a) Accompany the combined library with a copy of the same work + based on the Library, uncombined with any other library + facilities. This must be distributed under the terms of the + Sections above. + + b) Give prominent notice with the combined library of the fact + that part of it is a work based on the Library, and explaining + where to find the accompanying uncombined form of the same work. + + 8. You may not copy, modify, sublicense, link with, or distribute +the Library except as expressly provided under this License. Any +attempt otherwise to copy, modify, sublicense, link with, or +distribute the Library is void, and will automatically terminate your +rights under this License. However, parties who have received copies, +or rights, from you under this License will not have their licenses +terminated so long as such parties remain in full compliance. + + 9. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Library or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Library (or any work based on the +Library), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Library or works based on it. + + 10. Each time you redistribute the Library (or any work based on the +Library), the recipient automatically receives a license from the +original licensor to copy, distribute, link with or modify the Library +subject to these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 11. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Library at all. For example, if a patent +license would not permit royalty-free redistribution of the Library by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Library. + +If any portion of this section is held invalid or unenforceable under any +particular circumstance, the balance of the section is intended to apply, +and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 12. If the distribution and/or use of the Library is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Library under this License may add +an explicit geographical distribution limitation excluding those countries, +so that distribution is permitted only in or among countries not thus +excluded. In such case, this License incorporates the limitation as if +written in the body of this License. + + 13. The Free Software Foundation may publish revised and/or new +versions of the Library General Public License from time to time. +Such new versions will be similar in spirit to the present version, +but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Library +specifies a version number of this License which applies to it and +"any later version", you have the option of following the terms and +conditions either of that version or of any later version published by +the Free Software Foundation. If the Library does not specify a +license version number, you may choose any version ever published by +the Free Software Foundation. + + 14. If you wish to incorporate parts of the Library into other free +programs whose distribution conditions are incompatible with these, +write to the author to ask for permission. For software which is +copyrighted by the Free Software Foundation, write to the Free +Software Foundation; we sometimes make exceptions for this. Our +decision will be guided by the two goals of preserving the free status +of all derivatives of our free software and of promoting the sharing +and reuse of software generally. + + NO WARRANTY + + 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO +WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. +EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR +OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY +KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE +LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME +THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN +WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY +AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU +FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR +CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE +LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING +RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A +FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF +SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +DAMAGES. + + END OF TERMS AND CONDITIONS + + Appendix: How to Apply These Terms to Your New Libraries + + If you develop a new library, and you want it to be of the greatest +possible use to the public, we recommend making it free software that +everyone can redistribute and change. You can do so by permitting +redistribution under these terms (or, alternatively, under the terms of the +ordinary General Public License). + + To apply these terms, attach the following notices to the library. It is +safest to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least the +"copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with this library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, + MA 02111-1307, USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/snapshots/isabelle/lib/lem/Lem.thy b/snapshots/isabelle/lib/lem/Lem.thy new file mode 100644 index 00000000..c6a2a883 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem.thy @@ -0,0 +1,108 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* Brian Campbell, University of Edinburgh *) +(* Shaked Flur, University of Cambridge *) +(* Thomas Bauereiss, University of Cambridge *) +(* Stephen Kell, University of Cambridge *) +(* Thomas Williams *) +(* Lars Hupel *) +(* Basile Clement *) +(* *) +(* The Lem sources are copyright 2010-2018 *) +(* by the authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + +chapter\Mappings of Syntax needed by Lem\ + +theory "Lem" + +imports + LemExtraDefs + "~~/src/HOL/Word/Word" +begin + +type_synonym numeral = nat + +subsection \Finite Maps\ + +abbreviation (input) "map_find k m \ the (m k)" +abbreviation (input) "map_update k v m \ m (k \ v)" +abbreviation (input) "map_remove k m \ m |` (- {k})" +abbreviation (input) "map_any P m \ \ (k, v) \ map_to_set m. P k v" +abbreviation (input) "map_all P m \ \ (k, v) \ map_to_set m. P k v" + +subsection \Lists\ + +abbreviation (input) "list_mem e l \ (e \ set l)" +abbreviation (input) "list_forall P l \ (\e\set l. P e)" +abbreviation (input) "list_exists P l \ (\e\set l. P e)" +abbreviation (input) "list_unzip l \ (map fst l, map snd l)" + +subsection \Sets\ + +abbreviation (input) "set_filter P (s::'a set) \ {x \ s. P x}" +abbreviation (input) "set_bigunion S \ \ S" +abbreviation (input) "set_biginter S \ \ S" + +subsection \Natural numbers\ + +subsection \Integers\ + + +subsection \Dummy\ + +consts + bitwise_xor :: "nat \ nat \ nat" + num_asr :: "nat \ nat \ nat" + num_lsl :: "nat \ nat \ nat" + bitwise_or :: "nat \ nat \ nat" + bitwise_not :: "nat \ nat" + bitwise_and :: "nat \ nat \ nat" + +subsection \Machine words\ + +definition word_update :: "'a::len word \ nat \ nat \ 'b::len word \ 'a word" where + "word_update v lo hi w = + (let sz = size v in + of_bl (take (sz-hi-1) (to_bl v) @ to_bl w @ drop (sz-lo) (to_bl v)))" + +end diff --git a/snapshots/isabelle/lib/lem/LemExtraDefs.thy b/snapshots/isabelle/lib/lem/LemExtraDefs.thy new file mode 100644 index 00000000..c14a669f --- /dev/null +++ b/snapshots/isabelle/lib/lem/LemExtraDefs.thy @@ -0,0 +1,1259 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* Brian Campbell, University of Edinburgh *) +(* Shaked Flur, University of Cambridge *) +(* Thomas Bauereiss, University of Cambridge *) +(* Stephen Kell, University of Cambridge *) +(* Thomas Williams *) +(* Lars Hupel *) +(* Basile Clement *) +(* *) +(* The Lem sources are copyright 2010-2018 *) +(* by the authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + +chapter \Auxiliary Definitions needed by Lem\ + +theory "LemExtraDefs" + +imports + Main + "~~/src/HOL/Library/Permutation" + "~~/src/HOL/Library/While_Combinator" +begin + +subsection \General\ + +consts failwith :: " 'a \ 'b" + +subsection \Lists\ + +fun index :: " 'a list \ nat \ 'a option " where + "index [] n = None" + | "index (x # xs) 0 = Some x" + | "index (x # xs) (Suc n) = index xs n" + +lemma index_eq_some [simp]: + "index l n = Some x \ (n < length l \ (x = l ! n))" +proof (induct l arbitrary: n x) + case Nil thus ?case by simp +next + case (Cons e es n x) + note ind_hyp = this + + show ?case + proof (cases n) + case 0 thus ?thesis by auto + next + case (Suc n') + with ind_hyp show ?thesis by simp + qed +qed + +lemma index_eq_none [simp]: + "index l n = None \ length l \ n" +by (rule iffD1[OF Not_eq_iff]) auto + + +lemma index_simps [simp]: + "length l \ n \ index l n = None" + "n < length l \ index l n = Some (l ! n)" +by (simp_all) + +fun find_indices :: "('a \ bool) \ 'a list \ nat list" where + "find_indices P [] = []" + | "find_indices P (x # xs) = (if P x then 0 # (map Suc (find_indices P xs)) else (map Suc (find_indices P xs)))" + +lemma length_find_indices : + "length (find_indices P l) \ length l" +by (induct l) auto + +lemma sorted_map_suc : + "sorted l \ sorted (map Suc l)" +by (induct l) (simp_all add: sorted_Cons) + +lemma sorted_find_indices : + "sorted (find_indices P xs)" +proof (induct xs) + case Nil thus ?case by simp +next + case (Cons x xs) + from sorted_map_suc[OF this] + show ?case + by (simp add: sorted_Cons) +qed + +lemma find_indices_set [simp] : + "set (find_indices P l) = {i. i < length l \ P (l ! i)}" +proof (intro set_eqI) + fix i + show "i \ set (find_indices P l) \ (i \ {i. i < length l \ P (l ! i)})" + proof (induct l arbitrary: i) + case Nil thus ?case by simp + next + case (Cons x l' i) + note ind_hyp = this + show ?case + proof (cases i) + case 0 thus ?thesis by auto + next + case (Suc i') with ind_hyp[of i'] show ?thesis by auto + qed + qed +qed + +definition find_index where + "find_index P xs = (case find_indices P xs of + [] \ None + | i # _ \ Some i)" + +lemma find_index_eq_some [simp] : + "(find_index P xs = Some ii) \ (ii < length xs \ P (xs ! ii) \ (\i' < ii. \(P (xs ! i'))))" + (is "?lhs = ?rhs") +proof (cases "find_indices P xs") + case Nil + with find_indices_set[of P xs] + show ?thesis + unfolding find_index_def by auto +next + case (Cons i il) note find_indices_eq = this + + from sorted_find_indices[of P xs] find_indices_eq + have "sorted (i # il)" by simp + hence i_leq: "\i'. i' \ set (i # il) \ i \ i'" unfolding sorted_Cons by auto + + from find_indices_set[of P xs, unfolded find_indices_eq] + have set_i_il_eq:"\i'. i' \ set (i # il) = (i' < length xs \ P (xs ! i'))" + by simp + + have lhs_eq: "find_index P xs = Some i" + unfolding find_index_def find_indices_eq by simp + + show ?thesis + proof (intro iffI) + assume ?lhs + with lhs_eq have ii_eq[simp]: "ii = i" by simp + + from set_i_il_eq[of i] i_leq[unfolded set_i_il_eq] + show ?rhs by auto (metis leD less_trans) + next + assume ?rhs + with set_i_il_eq[of ii] + have "ii \ set (i # il) \ (ii \ i)" + by (metis leI length_pos_if_in_set nth_Cons_0 nth_mem set_i_il_eq) + + with i_leq [of ii] have "i = ii" by simp + thus ?lhs unfolding lhs_eq by simp + qed +qed + +lemma find_index_eq_none [simp] : + "(find_index P xs = None) \ (\x \ set xs. \(P x))" (is "?lhs = ?rhs") +proof (rule iffD1[OF Not_eq_iff], intro iffI) + assume "\ ?lhs" + then obtain i where "find_index P xs = Some i" by auto + hence "i < length xs \ P (xs ! i)" by simp + thus "\ ?rhs" by auto +next + let ?p = "(\i. i < length xs \ P(xs ! i))" + + assume "\ ?rhs" + then obtain i where "?p i" + by (metis in_set_conv_nth) + + from LeastI [of ?p, OF \?p i\] + have "?p (Least ?p)" . + + hence "find_index P xs = Some (Least ?p)" + by (subst find_index_eq_some) (metis (mono_tags) less_trans not_less_Least) + + thus "\ ?lhs" by blast +qed + +definition genlist where + "genlist f n = map f (upt 0 n)" + +lemma genlist_length [simp] : + "length (genlist f n) = n" +unfolding genlist_def by simp + +lemma genlist_simps [simp]: + "genlist f 0 = []" + "genlist f (Suc n) = genlist f n @ [f n]" +unfolding genlist_def by auto + +definition split_at where + "split_at n l = (take n l, drop n l)" + +fun delete_first :: "('a \ bool) \ 'a list \ ('a list) option " where + "delete_first P [] = None" + | "delete_first P (x # xs) = + (if (P x) then Some xs else + map_option (\xs'. x # xs') (delete_first P xs))" +declare delete_first.simps [simp del] + +lemma delete_first_simps [simp] : + "delete_first P [] = None" + "P x \ delete_first P (x # xs) = Some xs" + "\(P x) \ delete_first P (x # xs) = map_option (\xs'. x # xs') (delete_first P xs)" +unfolding delete_first.simps by auto + +lemmas delete_first_unroll = delete_first.simps(2) + + +lemma delete_first_eq_none [simp] : + "delete_first P l = None \ (\x \ set l. \ (P x))" +by (induct l) (auto simp add: delete_first_unroll) + +lemma delete_first_eq_some : + "delete_first P l = (Some l') \ (\l1 x l2. P x \ (\x \ set l1. \(P x)) \ (l = l1 @ (x # l2)) \ (l' = l1 @ l2))" + (is "?lhs l l' = (\l1 x l2. ?rhs_body l1 x l2 l l')") +proof (induct l arbitrary: l') + case Nil thus ?case by simp +next + case (Cons e l l') + note ind_hyp = this + + show ?case + proof (cases "P e") + case True + show ?thesis + proof (rule iffI) + assume "?lhs (e # l) l'" + with \P e\ have "l = l'" by simp + with \P e\ have "?rhs_body [] e l' (e # l) l'" by simp + thus "\l1 x l2. ?rhs_body l1 x l2 (e # l) l'" by blast + next + assume "\l1 x l2. ?rhs_body l1 x l2 (e # l) l'" + then obtain l1 x l2 where body_ok: "?rhs_body l1 x l2 (e # l) l'" by blast + + from body_ok \P e\ have l1_eq[simp]: "l = l'" + by (cases l1) (simp_all) + with \P e\ show "?lhs (e # l) l'" by simp + qed + next + case False + define rhs_pred where "rhs_pred \ \l1 x l2 l l'. ?rhs_body l1 x l2 l l'" + have rhs_fold: "\l1 x l2 l l'. ?rhs_body l1 x l2 l l' = rhs_pred l1 x l2 l l'" + unfolding rhs_pred_def by simp + + have "(\z l1 x l2. rhs_pred l1 x l2 l z \ e # z = l') = (\l1 x l2. rhs_pred l1 x l2 (e # l) l')" + proof (intro iffI) + assume "\z l1 x l2. rhs_pred l1 x l2 l z \ e # z = l'" + then obtain z l1 x l2 where "rhs_pred l1 x l2 l z" and l'_eq: "l' = e # z" by auto + with \\(P e)\ have "rhs_pred (e # l1) x l2 (e # l) l'" + unfolding rhs_pred_def by simp + thus "\l1 x l2. rhs_pred l1 x l2 (e # l) l'" by blast + next + assume "\l1 x l2. rhs_pred l1 x l2 (e # l) l'" + then obtain l1 x l2 where "rhs_pred l1 x l2 (e # l) l'" by blast + with \\ (P e)\ obtain l1' where l1_eq[simp]: "l1 = e # l1'" + unfolding rhs_pred_def by (cases l1) (auto) + + with \rhs_pred l1 x l2 (e # l) l'\ + have "rhs_pred l1' x l2 l (l1' @ l2) \ e # (l1' @ l2) = l'" + unfolding rhs_pred_def by (simp) + thus "\z l1 x l2. rhs_pred l1 x l2 l z \ e # z = l'" by blast + qed + with \\ P e\ show ?thesis + unfolding rhs_fold + by (simp add: ind_hyp[unfolded rhs_fold]) + qed +qed + + +lemma perm_eval [code] : + "perm [] l \ l = []" (is ?g1) + "perm (x # xs) l \ (case delete_first (\e. e = x) l of + None => False + | Some l' => perm xs l')" (is ?g2) +proof - + show ?g1 by auto +next + show ?g2 + proof (cases "delete_first (\e. e = x) l") + case None note del_eq = this + hence "x \ set l" by auto + with perm_set_eq [of "x # xs" l] + have "\ perm (x # xs) l" by auto + thus ?thesis unfolding del_eq by simp + next + case (Some l') note del_eq = this + + from del_eq[unfolded delete_first_eq_some] + obtain l1 l2 where l_eq: "l = l1 @ [x] @ l2" and l'_eq: "l' = l1 @ l2" by auto + + have "(x # xs <~~> l1 @ x # l2) = (xs <~~> l1 @ l2)" + proof - + from perm_append_swap [of l1 "[x]"] + perm_append2 [of "l1 @ [x]" "x # l1" l2] + have "l1 @ x # l2 <~~> x # (l1 @ l2)" by simp + hence "x # xs <~~> l1 @ x # l2 \ x # xs <~~> x # (l1 @ l2)" + by (metis perm.trans perm_sym) + thus ?thesis by simp + qed + with del_eq l_eq l'_eq show ?thesis by simp + qed +qed + + +fun sorted_by :: "('a \ 'a \ bool)\ 'a list \ bool " where + "sorted_by cmp [] = True" + | "sorted_by cmp [_] = True" + | "sorted_by cmp (x1 # x2 # xs) = ((cmp x1 x2) \ sorted_by cmp (x2 # xs))" + +lemma sorted_by_lesseq [simp] : + "sorted_by ((op \) :: ('a::{linorder}) => 'a => bool) = sorted" +proof (rule ext) + fix l :: "'a list" + show "sorted_by (op \) l = sorted l" + proof (induct l) + case Nil thus ?case by simp + next + case (Cons x xs) + thus ?case by (cases xs) (simp_all) + qed +qed + +lemma sorted_by_cons_imp : + "sorted_by cmp (x # xs) \ sorted_by cmp xs" +by (cases xs) simp_all + +lemma sorted_by_cons_trans : + assumes trans_cmp: "transp cmp" + shows "sorted_by cmp (x # xs) = ((\x' \ set xs . cmp x x') \ sorted_by cmp xs)" +proof (induct xs arbitrary: x) + case Nil thus ?case by simp +next + case (Cons x2 xs x1) + note ind_hyp = this + + from trans_cmp + show ?case + by (auto simp add: ind_hyp transp_def) +qed + + +fun insert_sort_insert_by :: "('a \ 'a \ bool)\ 'a \ 'a list \ 'a list " where + "insert_sort_insert_by cmp e ([]) = ( [e])" +| "insert_sort_insert_by cmp e (x # xs) = ( if cmp e x then (e # (x # xs)) else x # (insert_sort_insert_by cmp e xs))" + + +lemma insert_sort_insert_by_length [simp] : + "length (insert_sort_insert_by cmp e l) = Suc (length l)" +by (induct l) auto + +lemma insert_sort_insert_by_set [simp] : + "set (insert_sort_insert_by cmp e l) = insert e (set l)" +by (induct l) auto + +lemma insert_sort_insert_by_perm : + "(insert_sort_insert_by cmp e l) <~~> (e # l)" +proof (induct l) + case Nil thus ?case by simp +next + case (Cons e2 l') + note ind_hyp = this + + have "e2 # e # l' <~~> e # e2 # l'" by (rule perm.swap) + hence "e2 # insert_sort_insert_by cmp e l' <~~> e # e2 # l'" + using ind_hyp by (metis cons_perm_eq perm.trans) + thus ?case by simp +qed + + +lemma insert_sort_insert_by_sorted_by : +assumes cmp_cases: "\y. y \ set l \ \ (cmp e y) \ cmp y e" +assumes cmp_trans: "transp cmp" +shows "sorted_by cmp l \ sorted_by cmp (insert_sort_insert_by cmp e l)" +using cmp_cases +proof (induct l) + case Nil thus ?case by simp +next + case (Cons x1 l') + note ind_hyp = Cons(1) + note sorted_x1_l' = Cons(2) + note cmp_cases = Cons(3) + + show ?case + proof (cases l') + case Nil with cmp_cases show ?thesis by simp + next + case (Cons x2 l'') note l'_eq = this + + from l'_eq sorted_x1_l' have "cmp x1 x2" "sorted_by cmp l'" by simp_all + + show ?thesis + proof (cases "cmp e x1") + case True + with \cmp x1 x2\ \sorted_by cmp l'\ + have "sorted_by cmp (x1 # l')" + unfolding l'_eq by (simp) + with \cmp e x1\ + show ?thesis by simp + next + case False + + with cmp_cases have "cmp x1 e" by simp + have "\x'. x' \ set l' \ cmp x1 x'" + proof - + fix x' + assume "x' \ set l'" + hence "x' = x2 \ cmp x2 x'" + using \sorted_by cmp l'\ l'_eq sorted_by_cons_trans [OF cmp_trans, of x2 l''] + by auto + with transpD[OF cmp_trans, of x1 x2 x'] \cmp x1 x2\ + show "cmp x1 x'" by blast + qed + hence "sorted_by cmp (x1 # insert_sort_insert_by cmp e l')" + using ind_hyp [OF \sorted_by cmp l'\] \cmp x1 e\ cmp_cases + unfolding sorted_by_cons_trans[OF cmp_trans] + by simp + with \\(cmp e x1)\ + show ?thesis by simp + qed + qed +qed + + + +fun insert_sort_by :: "('a \ 'a \ bool) \ 'a list \ 'a list " where + "insert_sort_by cmp [] = []" + | "insert_sort_by cmp (x # xs) = insert_sort_insert_by cmp x (insert_sort_by cmp xs)" + + +lemma insert_sort_by_perm : + "(insert_sort_by cmp l) <~~> l" +proof (induct l) + case Nil thus ?case by simp +next + case (Cons x l) + thus ?case + by simp (metis cons_perm_eq insert_sort_insert_by_perm perm.trans) +qed + +lemma insert_sort_by_length [simp]: + "length (insert_sort_by cmp l) = length l" +by (induct l) auto + +lemma insert_sort_by_set [simp]: + "set (insert_sort_by cmp l) = set l" +by (induct l) auto + +definition sort_by where + "sort_by = insert_sort_by" + +lemma sort_by_simps [simp]: + "length (sort_by cmp l) = length l" + "set (sort_by cmp l) = set l" +unfolding sort_by_def by simp_all + +lemma sort_by_perm : + "sort_by cmp l <~~> l" +unfolding sort_by_def +by (simp add: insert_sort_by_perm) + +subsection \Maps\ + +definition map_image :: "('v \ 'w) \ ('k, 'v) map \ ('k, 'w) map" where + "map_image f m = (\k. map_option f (m k))" + +definition map_domain_image :: "('k \ 'v \ 'w) \ ('k, 'v) map \ ('k, 'w) map" where + "map_domain_image f m = (\k. map_option (f k) (m k))" + + +lemma map_image_simps [simp]: + "(map_image f m) k = None \ m k = None" + "(map_image f m) k = Some x \ (\x'. (m k = Some x') \ (x = f x'))" + "(map_image f Map.empty) = Map.empty" + "(map_image f (m (k \ v)) = (map_image f m) (k \ f v))" +unfolding map_image_def by auto + +lemma map_image_dom_ran [simp]: + "dom (map_image f m) = dom m" + "ran (map_image f m) = f ` (ran m)" +unfolding dom_def ran_def by auto + +definition map_to_set :: "('k, 'v) map \ ('k * 'v) set" where + "map_to_set m = { (k, v) . m k = Some v }" + +lemma map_to_set_simps [simp] : + "map_to_set Map.empty = {}" (is ?g1) + "map_to_set (m ((k::'k) \ (v::'v))) = (insert (k, v) (map_to_set (m |` (- {k}))))" (is ?g2) +proof - + show ?g1 unfolding map_to_set_def by simp +next + show ?g2 + proof (rule set_eqI) + fix kv :: "('k * 'v)" + obtain k' v' where kv_eq[simp]: "kv = (k', v')" by (rule prod.exhaust) + + show "(kv \ map_to_set (m(k \ v))) = (kv \ insert (k, v) (map_to_set (m |` (- {k}))))" + by (auto simp add: map_to_set_def) + qed +qed + + +subsection \Sets\ + +definition "set_choose s \ (SOME x. (x \ s))" + +definition without_trans_edges :: "('a \ 'a) set \ ('a \ 'a) set" where + "without_trans_edges S \ + let ts = trancl S in + { (x, y) \ S. \z \ snd ` S. x \ z \ y \ z \ \ ((x, z) \ ts \ (z, y) \ ts)}" + +definition unbounded_lfp :: "'a set \ ('a set \ 'a set) \ 'a set" where + "unbounded_lfp S f \ + while (\x. x \ S) f S" + +definition unbounded_gfp :: "'a set \ ('a set \ 'a set) \ 'a set" where + "unbounded_gfp S f \ + while (\x. S \ x) f S" + +lemma set_choose_thm[simp]: + "s \ {} \ (set_choose s) \ s" +unfolding set_choose_def +by (rule someI_ex) auto + +lemma set_choose_sing [simp]: + "set_choose {x} = x" + unfolding set_choose_def + by auto + +lemma set_choose_code [code]: + "set_choose (set [x]) = x" +by auto + +lemma set_choose_in [intro] : + assumes "s \ {}" + shows "set_choose s \ s" +proof - + from \s \ {}\ + obtain x where "x \ s" by auto + thus ?thesis + unfolding set_choose_def + by (rule someI) +qed + + +definition set_case where + "set_case s c_empty c_sing c_else = + (if (s = {}) then c_empty else + (if (card s = 1) then c_sing (set_choose s) else + c_else))" + +lemma set_case_simps [simp] : + "set_case {} c_empty c_sing c_else = c_empty" + "set_case {x} c_empty c_sing c_else = c_sing x" + "card s > 1 \ set_case s c_empty c_sing c_else = c_else" + "\(finite s) \ set_case s c_empty c_sing c_else = c_else" +unfolding set_case_def by auto + +lemma set_case_simp_insert2 [simp] : +assumes x12_neq: "x1 \ x2" +shows "set_case (insert x1 (insert x2 xs)) c_empty c_sing c_else = c_else" +proof (cases "finite xs") + case False thus ?thesis by (simp) +next + case True note fin_xs = this + + have "card {x1,x2} \ card (insert x1 (insert x2 xs))" + by (rule card_mono) (auto simp add: fin_xs) + with x12_neq have "1 < card (insert x1 (insert x2 xs))" by simp + thus ?thesis by auto +qed + +lemma set_case_code [code] : + "set_case (set []) c_empty c_sing c_else = c_empty" + "set_case (set [x]) c_empty c_sing c_else = c_sing x" + "set_case (set (x1 # x2 # xs)) c_empty c_sing c_else = + (if (x1 = x2) then + set_case (set (x2 # xs)) c_empty c_sing c_else + else + c_else)" +by auto + +definition set_lfp:: "'a set \ ('a set \ 'a set) \ 'a set" where + "set_lfp s f = lfp (\s'. f s' \ s)" + +lemma set_lfp_tail_rec_def : +assumes mono_f: "mono f" +shows "set_lfp s f = (if (f s) \ s then s else (set_lfp (s \ f s) f))" (is "?ls = ?rs") +proof (cases "f s \ s") + case True note fs_sub_s = this + + from fs_sub_s have "\{u. f u \ s \ u} = s" by auto + hence "?ls = s" unfolding set_lfp_def lfp_def . + with fs_sub_s show "?ls = ?rs" by simp +next + case False note not_fs_sub_s = this + + from mono_f have mono_f': "mono (\s'. f s' \ s)" + unfolding mono_def by auto + + have "\{u. f u \ s \ u} = \{u. f u \ (s \ f s) \ u}" (is "\?S1 = \?S2") + proof + have "?S2 \ ?S1" by auto + thus "\?S1 \ \?S2" by (rule Inf_superset_mono) + next + { fix e + assume "e \ \?S2" + hence S2_prop: "\s'. f s' \ s' \ s \ s' \ f s \ s' \ e \ s'" by simp + + { fix s' + assume "f s' \ s'" "s \ s'" + + from mono_f \s \ s'\ + have "f s \ f s'" unfolding mono_def by simp + with \f s' \ s'\ have "f s \ s'" by simp + with \f s' \ s'\ \s \ s'\ S2_prop + have "e \ s'" by simp + } + hence "e \ \?S1" by simp + } + thus "\?S2 \ \?S1" by auto + qed + hence "?ls = (set_lfp (s \ f s) f)" + unfolding set_lfp_def lfp_def . + with not_fs_sub_s show "?ls = ?rs" by simp +qed + +lemma set_lfp_simps [simp] : +"mono f \ f s \ s \ set_lfp s f = s" +"mono f \ \(f s \ s) \ set_lfp s f = (set_lfp (s \ f s) f)" +by (metis set_lfp_tail_rec_def)+ + + +fun insert_in_list_at_arbitrary_pos where + "insert_in_list_at_arbitrary_pos x [] = {[x]}" + | "insert_in_list_at_arbitrary_pos x (y # ys) = + insert (x # y # ys) ((\l. y # l) ` (insert_in_list_at_arbitrary_pos x ys))" + +lemma insert_in_list_at_arbitrary_pos_thm : + "xl \ insert_in_list_at_arbitrary_pos x l \ + (\l1 l2. l = l1 @ l2 \ xl = l1 @ [x] @ l2)" +proof (induct l arbitrary: xl) + case Nil thus ?case by simp +next + case (Cons y l xyl) + note ind_hyp = this + + show ?case + proof (rule iffI) + assume xyl_in: "xyl \ insert_in_list_at_arbitrary_pos x (y # l)" + show "\l1 l2. y # l = l1 @ l2 \ xyl = l1 @ [x] @ l2" + proof (cases "xyl = x # y # l") + case True + hence "y # l = [] @ (y # l) \ xyl = [] @ [x] @ (y # l)" by simp + thus ?thesis by blast + next + case False + with xyl_in have "xyl \ op # y ` insert_in_list_at_arbitrary_pos x l" by simp + with ind_hyp obtain l1 l2 where "l = l1 @ l2 \ xyl = y # l1 @ x # l2" + by (auto simp add: image_def Bex_def) + hence "y # l = (y # l1) @ l2 \ xyl = (y # l1) @ [x] @ l2" by simp + thus ?thesis by blast + qed + next + assume "\l1 l2. y # l = l1 @ l2 \ xyl = l1 @ [x] @ l2" + then obtain l1 l2 where yl_eq: "y # l = l1 @ l2" and xyl_eq: "xyl = l1 @ [x] @ l2" by blast + show "xyl \ insert_in_list_at_arbitrary_pos x (y # l)" + proof (cases l1) + case Nil + with yl_eq xyl_eq + have "xyl = x # y # l" by simp + thus ?thesis by simp + next + case (Cons y' l1') + with yl_eq have l1_eq: "l1 = y # l1'" and l_eq: "l = l1' @ l2" by simp_all + + have "\l1'' l2''. l = l1'' @ l2'' \ l1' @ [x] @ l2 = l1'' @ [x] @ l2''" + apply (rule_tac exI[where x = l1']) + apply (rule_tac exI [where x = l2]) + apply (simp add: l_eq) + done + hence "(l1' @ [x] @ l2) \ insert_in_list_at_arbitrary_pos x l" + unfolding ind_hyp by blast + hence "\l'. l' \ insert_in_list_at_arbitrary_pos x l \ l1 @ x # l2 = y # l'" + by (rule_tac exI [where x = "l1' @ [x] @ l2"]) (simp add: l1_eq) + thus ?thesis + by (simp add: image_def Bex_def xyl_eq) + qed + qed +qed + +definition list_of_set_set :: "'a set \ ('a list) set" where +"list_of_set_set s = { l . (set l = s) \ distinct l }" + +lemma list_of_set_set_empty [simp]: + "list_of_set_set {} = {[]}" +unfolding list_of_set_set_def by auto + +lemma list_of_set_set_insert [simp] : + "list_of_set_set (insert x s) = + \ ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x})))" + (is "?lhs = ?rhs") +proof (intro set_eqI) + fix l + + have "(set l = insert x s \ distinct l) \ (\l1 l2. set (l1 @ l2) = s - {x} \ distinct (l1 @ l2) \ l = l1 @ x # l2)" + proof (intro iffI) + assume "set l = insert x s \ distinct l" + hence set_l_eq: "set l = insert x s" and "distinct l" by simp_all + + from \set l = insert x s\ + have "x \ set l" by simp + then obtain l1 l2 where l_eq: "l = l1 @ x # l2" + unfolding in_set_conv_decomp by blast + + from \distinct l\ l_eq + have "distinct (l1 @ l2)" and x_nin: "x \ set (l1 @ l2)" + by auto + + from x_nin set_l_eq[unfolded l_eq] + have set_l12_eq: "set (l1 @ l2) = s - {x}" + by auto + + from \distinct (l1 @ l2)\ l_eq set_l12_eq + show "\l1 l2. set (l1 @ l2) = s - {x} \ distinct (l1 @ l2) \ l = l1 @ x # l2" + by blast + next + assume "\l1 l2. set (l1 @ l2) = s - {x} \ distinct (l1 @ l2) \ l = l1 @ x # l2" + then obtain l1 l2 where "set (l1 @ l2) = s - {x}" "distinct (l1 @ l2)" "l = l1 @ x # l2" + by blast + thus "set l = insert x s \ distinct l" + by auto + qed + + thus "l \ list_of_set_set (insert x s) \ l \ (\ ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x}))))" + unfolding list_of_set_set_def + by (simp add: insert_in_list_at_arbitrary_pos_thm ex_simps[symmetric] del: ex_simps) +qed + +lemma list_of_set_set_code [code]: + "list_of_set_set (set []) = {[]}" + "list_of_set_set (set (x # xs)) = + \ ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set ((set xs) - {x})))" +by simp_all + +lemma list_of_set_set_is_empty : + "list_of_set_set s = {} \ \ (finite s)" +proof - + have "finite s \ (\l. set l = s \ distinct l)" + proof (rule iffI) + assume "\l. set l = s \ distinct l" then + obtain l where "s = set l" by blast + thus "finite s" by simp + next + assume "finite s" + thus "\l. set l = s \ distinct l" + proof (induct s) + case empty + show ?case by auto + next + case (insert e s) + note e_nin_s = insert(2) + from insert(3) obtain l where set_l: "set l = s" and dist_l: "distinct l" by blast + + from set_l have set_el: "set (e # l) = insert e s" by auto + from dist_l set_l e_nin_s have dist_el: "distinct (e # l)" by simp + + from set_el dist_el show ?case by blast + qed + qed + thus ?thesis + unfolding list_of_set_set_def by simp +qed + +definition list_of_set :: "'a set \ 'a list" where + "list_of_set s = set_choose (list_of_set_set s)" + +lemma list_of_set [simp] : + assumes fin_s: "finite s" + shows "set (list_of_set s) = s" + "distinct (list_of_set s)" +proof - + from fin_s list_of_set_set_is_empty[of s] + have "\ (list_of_set_set s = {})" by simp + hence "list_of_set s \ list_of_set_set s" + unfolding list_of_set_def + by (rule set_choose_thm) + thus "set (list_of_set s) = s" + "distinct (list_of_set s)" unfolding list_of_set_set_def + by simp_all +qed + +lemma list_of_set_in: + "finite s \ list_of_set s \ list_of_set_set s" +unfolding list_of_set_def +by (metis list_of_set_set_is_empty set_choose_thm) + +definition ordered_list_of_set where + "ordered_list_of_set cmp s = set_choose (sort_by cmp ` list_of_set_set s)" + +subsection \sum\ + +find_consts "'a list => ('a list * _)" + +fun sum_partition :: "('a + 'b) list \ 'a list * 'b list" where + "sum_partition [] = ([], [])" +| "sum_partition ((Inl l) # lrs) = + (let (ll, rl) = sum_partition lrs in + (l # ll, rl))" +| "sum_partition ((Inr r) # lrs) = + (let (ll, rl) = sum_partition lrs in + (ll, r # rl))" + +lemma sum_partition_length : + "List.length lrs = List.length (fst (sum_partition lrs)) + List.length (snd (sum_partition lrs))" +proof (induct lrs) + case Nil thus ?case by simp +next + case (Cons lr lrs) thus ?case + by (cases lr) (auto split: prod.split) +qed + +subsection \sorting\ + +subsection \Strings\ + +lemma explode_str_simp [simp] : + "String.explode (STR l) = l" +by (metis STR_inverse UNIV_I) + +declare String.literal.explode_inverse [simp] + +subsection \num to string conversions\ + +definition nat_list_to_string :: "nat list \ string" where + "nat_list_to_string nl = map char_of_nat nl" + +definition is_digit where + "is_digit (n::nat) = (n < 10)" + +lemma is_digit_simps[simp] : + "n < 10 \ is_digit n" + "\(n < 10) \ \(is_digit n)" +unfolding is_digit_def by simp_all + +lemma is_digit_expand : + "is_digit n \ + (n = 0) \ (n = 1) \ (n = 2) \ (n = 3) \ (n = 4) \ + (n = 5) \ (n = 6) \ (n = 7) \ (n = 8) \ (n = 9)" +unfolding is_digit_def by auto + +lemmas is_digitE = is_digit_expand[THEN iffD1,elim_format] +lemmas is_digitI = is_digit_expand[THEN iffD2,rule_format] + +definition is_digit_char where + "is_digit_char c \ + (c = CHR ''0'') \ (c = CHR ''5'') \ + (c = CHR ''1'') \ (c = CHR ''6'') \ + (c = CHR ''2'') \ (c = CHR ''7'') \ + (c = CHR ''3'') \ (c = CHR ''8'') \ + (c = CHR ''4'') \ (c = CHR ''9'')" + +lemma is_digit_char_simps[simp] : + "is_digit_char (CHR ''0'')" + "is_digit_char (CHR ''1'')" + "is_digit_char (CHR ''2'')" + "is_digit_char (CHR ''3'')" + "is_digit_char (CHR ''4'')" + "is_digit_char (CHR ''5'')" + "is_digit_char (CHR ''6'')" + "is_digit_char (CHR ''7'')" + "is_digit_char (CHR ''8'')" + "is_digit_char (CHR ''9'')" +unfolding is_digit_char_def by simp_all + +lemmas is_digit_charE = is_digit_char_def[THEN iffD1,elim_format] +lemmas is_digit_charI = is_digit_char_def[THEN iffD2,rule_format] + +definition digit_to_char :: "nat \ char" where + "digit_to_char n = ( + if n = 0 then CHR ''0'' + else if n = 1 then CHR ''1'' + else if n = 2 then CHR ''2'' + else if n = 3 then CHR ''3'' + else if n = 4 then CHR ''4'' + else if n = 5 then CHR ''5'' + else if n = 6 then CHR ''6'' + else if n = 7 then CHR ''7'' + else if n = 8 then CHR ''8'' + else if n = 9 then CHR ''9'' + else CHR ''X'')" + +lemma digit_to_char_simps [simp]: + "digit_to_char 0 = CHR ''0''" + "digit_to_char (Suc 0) = CHR ''1''" + "digit_to_char 2 = CHR ''2''" + "digit_to_char 3 = CHR ''3''" + "digit_to_char 4 = CHR ''4''" + "digit_to_char 5 = CHR ''5''" + "digit_to_char 6 = CHR ''6''" + "digit_to_char 7 = CHR ''7''" + "digit_to_char 8 = CHR ''8''" + "digit_to_char 9 = CHR ''9''" + "n > 9 \ digit_to_char n = CHR ''X''" +unfolding digit_to_char_def +by simp_all + +definition char_to_digit :: "char \ nat" where + "char_to_digit c = ( + if c = CHR ''0'' then 0 + else if c = CHR ''1'' then 1 + else if c = CHR ''2'' then 2 + else if c = CHR ''3'' then 3 + else if c = CHR ''4'' then 4 + else if c = CHR ''5'' then 5 + else if c = CHR ''6'' then 6 + else if c = CHR ''7'' then 7 + else if c = CHR ''8'' then 8 + else if c = CHR ''9'' then 9 + else 10)" + +lemma char_to_digit_simps [simp]: + "char_to_digit (CHR ''0'') = 0" + "char_to_digit (CHR ''1'') = 1" + "char_to_digit (CHR ''2'') = 2" + "char_to_digit (CHR ''3'') = 3" + "char_to_digit (CHR ''4'') = 4" + "char_to_digit (CHR ''5'') = 5" + "char_to_digit (CHR ''6'') = 6" + "char_to_digit (CHR ''7'') = 7" + "char_to_digit (CHR ''8'') = 8" + "char_to_digit (CHR ''9'') = 9" +unfolding char_to_digit_def by simp_all + + +lemma diget_to_char_inv[simp]: +assumes is_digit: "is_digit n" +shows "char_to_digit (digit_to_char n) = n" +using is_digit unfolding is_digit_expand by auto + +lemma char_to_diget_inv[simp]: +assumes is_digit: "is_digit_char c" +shows "digit_to_char (char_to_digit c) = c" +using is_digit +unfolding char_to_digit_def is_digit_char_def +by auto + +lemma char_to_digit_div_mod [simp]: +assumes is_digit: "is_digit_char c" +shows "char_to_digit c < 10" +using is_digit +unfolding char_to_digit_def is_digit_char_def +by auto + + +lemma is_digit_char_intro[simp]: + "is_digit (char_to_digit c) = is_digit_char c" +unfolding char_to_digit_def is_digit_char_def is_digit_expand +by auto + +lemma is_digit_intro[simp]: + "is_digit_char (digit_to_char n) = is_digit n" +unfolding digit_to_char_def is_digit_char_def is_digit_expand +by auto + +lemma digit_to_char_11: +"digit_to_char n1 = digit_to_char n2 \ + (is_digit n1 = is_digit n2) \ (is_digit n1 \ (n1 = n2))" +by (metis diget_to_char_inv is_digit_intro) + +lemma char_to_digit_11: +"char_to_digit c1 = char_to_digit c2 \ + (is_digit_char c1 = is_digit_char c2) \ (is_digit_char c1 \ (c1 = c2))" +by (metis char_to_diget_inv is_digit_char_intro) + +function nat_to_string :: "nat \ string" where + "nat_to_string n = + (if (is_digit n) then [digit_to_char n] else + nat_to_string (n div 10) @ [digit_to_char (n mod 10)])" +by auto +termination + by (relation "measure id") (auto simp add: is_digit_def) + +definition int_to_string :: "int \ string" where + "int_to_string i \ + if i < 0 then + ''-'' @ nat_to_string (nat (abs i)) + else + nat_to_string (nat i)" + +lemma nat_to_string_simps[simp]: + "is_digit n \ nat_to_string n = [digit_to_char n]" + "\(is_digit n) \ nat_to_string n = nat_to_string (n div 10) @ [digit_to_char (n mod 10)]" +by simp_all +declare nat_to_string.simps[simp del] + +lemma nat_to_string_neq_nil[simp]: + "nat_to_string n \ []" + by (cases "is_digit n") simp_all + +lemmas nat_to_string_neq_nil2[simp] = nat_to_string_neq_nil[symmetric] + +lemma nat_to_string_char_to_digit [simp]: + "is_digit_char c \ nat_to_string (char_to_digit c) = [c]" +by auto + +lemma nat_to_string_11[simp] : + "(nat_to_string n1 = nat_to_string n2) \ n1 = n2" +proof (rule iffI) + assume "n1 = n2" + thus "nat_to_string n1 = nat_to_string n2" by simp +next + assume "nat_to_string n1 = nat_to_string n2" + thus "n1 = n2" + proof (induct n2 arbitrary: n1 rule: less_induct) + case (less n2') + note ind_hyp = this(1) + note n2s_eq = less(2) + + have is_dig_eq: "is_digit n2' = is_digit n1" using n2s_eq + apply (cases "is_digit n2'") + apply (case_tac [!] "is_digit n1") + apply (simp_all) + done + + show ?case + proof (cases "is_digit n2'") + case True with n2s_eq is_dig_eq show ?thesis by simp (metis digit_to_char_11) + next + case False + with is_dig_eq have not_digs : "\ (is_digit n1)" "\ (is_digit n2')" by simp_all + + from not_digs(2) have "n2' div 10 < n2'" unfolding is_digit_def by auto + note ind_hyp' = ind_hyp [OF this, of "n1 div 10"] + + from not_digs n2s_eq ind_hyp' digit_to_char_11[of "n1 mod 10" "n2' mod 10"] + have "(n1 mod 10) = (n2' mod 10)" "n1 div 10 = n2' div 10" by simp_all + thus "n1 = n2'" by (metis div_mult_mod_eq) + qed + qed +qed + +definition "is_nat_string s \ (\c\set s. is_digit_char c)" +definition "is_strong_nat_string s \ is_nat_string s \ (s \ []) \ (hd s = CHR ''0'' \ length s = 1)" + +lemma is_nat_string_simps[simp]: + "is_nat_string []" + "is_nat_string (c # s) \ is_digit_char c \ is_nat_string s" +unfolding is_nat_string_def by simp_all + +lemma is_strong_nat_string_simps[simp]: + "\(is_strong_nat_string [])" + "is_strong_nat_string (c # s) \ is_digit_char c \ is_nat_string s \ + (c = CHR ''0'' \ s = [])" +unfolding is_strong_nat_string_def by simp_all + +fun string_to_nat_aux :: "nat \ string \ nat" where + "string_to_nat_aux n [] = n" + | "string_to_nat_aux n (d#ds) = + string_to_nat_aux (n*10 + char_to_digit d) ds" + +definition string_to_nat :: "string \ nat option" where + "string_to_nat s \ + (if is_nat_string s then Some (string_to_nat_aux 0 s) else None)" + +definition string_to_nat' :: "string \ nat" where + "string_to_nat' s \ the (string_to_nat s)" + +lemma string_to_nat_aux_inv : +assumes "is_nat_string s" +assumes "n > 0 \ is_strong_nat_string s" +shows "nat_to_string (string_to_nat_aux n s) = +(if n = 0 then '''' else nat_to_string n) @ s" +using assms +proof (induct s arbitrary: n) + case Nil + thus ?case + by (simp add: is_strong_nat_string_def) +next + case (Cons c s n) + from Cons(2) have "is_digit_char c" "is_nat_string s" by simp_all + note cs_ok = Cons(3) + let ?m = "n*10 + char_to_digit c" + note ind_hyp = Cons(1)[OF \is_nat_string s\, of ?m] + + from \is_digit_char c\ have m_div: "?m div 10 = n" and + m_mod: "?m mod 10 = char_to_digit c" + unfolding is_digit_char_def + by auto + + show ?case + proof (cases "?m = 0") + case True + with \is_digit_char c\ + have "n = 0" "c = CHR ''0''" unfolding is_digit_char_def by auto + moreover with cs_ok have "s = []" by simp + ultimately show ?thesis by simp + next + case False note m_neq_0 = this + with ind_hyp have ind_hyp': + "nat_to_string (string_to_nat_aux ?m s) = (nat_to_string ?m) @ s" by auto + + hence "nat_to_string (string_to_nat_aux n (c # s)) = (nat_to_string ?m) @ s" + by simp + + with \is_digit_char c\ m_div show ?thesis by simp + qed +qed + +lemma string_to_nat_inv : +assumes strong_nat_s: "is_strong_nat_string s" +assumes s2n_s: "string_to_nat s = Some n" +shows "nat_to_string n = s" +proof - + from strong_nat_s have nat_s: "is_nat_string s" unfolding is_strong_nat_string_def by simp + with s2n_s have n_eq: "n = string_to_nat_aux 0 s" unfolding string_to_nat_def by simp + + from string_to_nat_aux_inv[of s 0, folded n_eq] nat_s strong_nat_s + show ?thesis by simp +qed + +lemma nat_to_string_induct [case_names "digit" "non_digit"]: +assumes digit: "\d. is_digit d \ P d" +assumes not_digit: "\n. \(is_digit n) \ P (n div 10) \ P (n mod 10) \ P n" +shows "P n" +proof (induct n rule: less_induct) + case (less n) + note ind_hyp = this + + show ?case + proof (cases "is_digit n") + case True with digit show ?thesis by simp + next + case False note not_dig = this + hence "n div 10 < n" "n mod 10 < n" unfolding is_digit_def by auto + with not_dig ind_hyp not_digit show ?thesis by simp + qed +qed + +lemma nat_to_string___is_nat_string [simp]: + "is_nat_string (nat_to_string n)" +unfolding is_nat_string_def +proof (induct n rule: nat_to_string_induct) + case (digit d) + thus ?case by simp +next + case (non_digit n) + thus ?case by simp +qed + +lemma nat_to_string___eq_0 [simp]: + "(nat_to_string n = (CHR ''0'')#s) \ (n = 0 \ s = [])" +unfolding is_nat_string_def +proof (induct n arbitrary: s rule: nat_to_string_induct) + case (digit d) thus ?case unfolding is_digit_expand by auto +next + case (non_digit n) + + obtain c s' where ns_eq: "nat_to_string (n div 10) = c # s'" + by (cases "nat_to_string (n div 10)") auto + + from non_digit(1) have "n div 10 \ 0" unfolding is_digit_def by auto + with non_digit(2) ns_eq have c_neq: "c \ CHR ''0''" by auto + + from \\ (is_digit n)\ c_neq ns_eq + show ?case by auto +qed + +lemma nat_to_string___is_strong_nat_string: + "is_strong_nat_string (nat_to_string n)" +proof (cases "is_digit n") + case True thus ?thesis by simp +next + case False note not_digit = this + + obtain c s' where ns_eq: "nat_to_string n = c # s'" + by (cases "nat_to_string n") auto + + from not_digit have "0 < n" unfolding is_digit_def by simp + with ns_eq have c_neq: "c \ CHR ''0''" by auto + hence "hd (nat_to_string n) \ CHR ''0''" unfolding ns_eq by simp + + thus ?thesis unfolding is_strong_nat_string_def + by simp +qed + +lemma nat_to_string_inv : + "string_to_nat (nat_to_string n) = Some n" +by (metis nat_to_string_11 + nat_to_string___is_nat_string + nat_to_string___is_strong_nat_string + string_to_nat_def + string_to_nat_inv) + +definition The_opt where + "The_opt p = (if (\!x. p x) then Some (The p) else None)" + +lemma The_opt_eq_some [simp] : +"((The_opt p) = (Some x)) \ ((p x) \ ((\ y. p y \ (x = y))))" + (is "?lhs = ?rhs") +proof (cases "\!x. p x") + case True + note exists_unique = this + then obtain x where p_x: "p x" by auto + + from the1_equality[of p x] exists_unique p_x + have the_opt_eq: "The_opt p = Some x" + unfolding The_opt_def by simp + + from exists_unique the_opt_eq p_x show ?thesis + by auto +next + case False + note not_unique = this + + hence "The_opt p = None" + unfolding The_opt_def by simp + with not_unique show ?thesis by auto +qed + +lemma The_opt_eq_none [simp] : +"((The_opt p) = None) \ \(\!x. p x)" +unfolding The_opt_def by auto + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_assert_extra.thy b/snapshots/isabelle/lib/lem/Lem_assert_extra.thy new file mode 100644 index 00000000..b56e5a19 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_assert_extra.thy @@ -0,0 +1,45 @@ +chapter \Generated by Lem from assert_extra.lem.\ + +theory "Lem_assert_extra" + +imports + Main + "Lem" + +begin + + +(*open import {ocaml} `Xstring`*) +(*open import {hol} `stringTheory` `lemTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------------------ *) +(* failing with a proper error message *) +(* ------------------------------------ *) + +(*val failwith: forall 'a. string -> 'a*) + +(* ------------------------------------ *) +(* failing without an error message *) +(* ------------------------------------ *) + +(*val fail : forall 'a. 'a*) +definition fail :: " 'a " where + " fail = ( failwith (''fail''))" + + +(* ------------------------------------- *) +(* assertions *) +(* ------------------------------------- *) + +(*val ensure : bool -> string -> unit*) +definition ensure :: " bool \ string \ unit " where + " ensure test msg = ( + if test then + () + else + failwith msg )" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy new file mode 100644 index 00000000..c2032dc1 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy @@ -0,0 +1,500 @@ +chapter \Generated by Lem from basic_classes.lem.\ + +theory "Lem_basic_classes" + +imports + Main + "Lem_bool" + +begin + +(******************************************************************************) +(* Basic Type Classes *) +(******************************************************************************) + +(*open import Bool*) + +(*open import {coq} `Coq.Strings.Ascii`*) + +(* ========================================================================== *) +(* Equality *) +(* ========================================================================== *) + +(* Lem`s default equality (=) is defined by the following type-class Eq. + This typeclass should define equality on an abstract datatype 'a. It should + always coincide with the default equality of Coq, HOL and Isabelle. + For OCaml, it might be different, since abstract datatypes like sets + might have fancy equalities. *) + +(*class ( Eq 'a ) + val = [isEqual] : 'a -> 'a -> bool + val <> [isInequal] : 'a -> 'a -> bool +end*) + + +(* (=) should for all instances be an equivalence relation + The isEquivalence predicate of relations could be used here. + However, this would lead to a cyclic dependency. *) + +(* TODO: add later, once lemmata can be assigned to classes +lemma eq_equiv: ((forall x. (x = x)) && + (forall x y. (x = y) <-> (y = x)) && + (forall x y z. ((x = y) && (y = z)) --> (x = z))) +*) + +(* Structural equality *) + +(* Sometimes, it is also handy to be able to use structural equality. + This equality is mapped to the build-in equality of backends. This equality + differs significantly for each backend. For example, OCaml can`t check equality + of function types, whereas HOL can. When using structural equality, one should + know what one is doing. The only guarentee is that is behaves like + the native backend equality. + + A lengthy name for structural equality is used to discourage its direct use. + It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions + for equality *) +(*val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool*) + +(*val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool*) +(*let unsafe_structural_inequality x y= not (unsafe_structural_equality x y)*) + + +(* ========================================================================== *) +(* Orderings *) +(* ========================================================================== *) + +(* The type-class Ord represents total orders (also called linear orders) *) +datatype ordering = LT | EQ | GT + +fun orderingIsLess :: " ordering \ bool " where + " orderingIsLess LT = ( True )" +|" orderingIsLess _ = ( False )" + +fun orderingIsGreater :: " ordering \ bool " where + " orderingIsGreater GT = ( True )" +|" orderingIsGreater _ = ( False )" + +fun orderingIsEqual :: " ordering \ bool " where + " orderingIsEqual EQ = ( True )" +|" orderingIsEqual _ = ( False )" + + +definition ordering_cases :: " ordering \ 'a \ 'a \ 'a \ 'a " where + " ordering_cases r lt eq gt = ( + if orderingIsLess r then lt else + if orderingIsEqual r then eq else gt )" + + + +(*val orderingEqual : ordering -> ordering -> bool*) + +record 'a Ord_class= + + compare_method ::" 'a \ 'a \ ordering " + + isLess_method ::" 'a \ 'a \ bool " + + isLessEqual_method ::" 'a \ 'a \ bool " + + isGreater_method ::" 'a \ 'a \ bool " + + isGreaterEqual_method ::" 'a \ 'a \ bool " + + + + +(* Ocaml provides default, polymorphic compare functions. Let's use them + as the default. However, because used perhaps in a typeclass they must be + defined for all targets. So, explicitly declare them as undefined for + all other targets. If explictly declare undefined, the type-checker won't complain and + an error will only be raised when trying to actually output the function for a certain + target. *) +(*val defaultCompare : forall 'a. 'a -> 'a -> ordering*) +(*val defaultLess : forall 'a. 'a -> 'a -> bool*) +(*val defaultLessEq : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreater : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreaterEq : forall 'a. 'a -> 'a -> bool*) + + +definition genericCompare :: "('a \ 'a \ bool)\('a \ 'a \ bool)\ 'a \ 'a \ ordering " where + " genericCompare (less1:: 'a \ 'a \ bool) (equal:: 'a \ 'a \ bool) (x :: 'a) (y :: 'a) = ( + if less1 x y then + LT + else if equal x y then + EQ + else + GT )" + + + +(* +(* compare should really be a total order *) +lemma ord_OK_1: ( + (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) && + (forall x y. (compare x y = LT) <-> (compare y x = GT))) + +lemma ord_OK_2: ( + (forall x y z. (x <= y) && (y <= z) --> (x <= z)) && + (forall x y. (x <= y) || (y <= x)) +) +*) + +(* let's derive a compare function from the Ord type-class *) +(*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*) +definition ordCompare :: " 'a Ord_class \ 'a \ 'a \ ordering " where + " ordCompare dict_Basic_classes_Ord_a x y = ( + if ((isLess_method dict_Basic_classes_Ord_a) x y) then LT else + if (x = y) then EQ else GT )" + + +record 'a OrdMaxMin_class= + + max_method ::" 'a \ 'a \ 'a " + + min_method ::" 'a \ 'a \ 'a " + + + +(*val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) + +(*val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) + +(*val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +(*val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +definition instance_Basic_classes_OrdMaxMin_var_dict :: " 'a Ord_class \ 'a OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_var_dict dict_Basic_classes_Ord_a = ((| + + max_method = ((\ x y. if ( + (isLessEqual_method dict_Basic_classes_Ord_a) y x) then x else y)), + + min_method = ((\ x y. if ( + (isLessEqual_method dict_Basic_classes_Ord_a) x y) then x else y))|) )" + + + +(* ========================================================================== *) +(* SetTypes *) +(* ========================================================================== *) + +(* Set implementations use often an order on the elements. This allows the OCaml implementation + to use trees for implementing them. At least, one needs to be able to check equality on sets. + One could use the Ord type-class for sets. However, defining a special typeclass is cleaner + and allows more flexibility. One can make e.g. sure, that this type-class is ignored for + backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate + the functions <, <= ... *) + +(*class ( SetType 'a ) + val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering +end*) + +fun boolCompare :: " bool \ bool \ ordering " where + " boolCompare True True = ( EQ )" +|" boolCompare True False = ( GT )" +|" boolCompare False True = ( LT )" +|" boolCompare False False = ( EQ )" + + +(* strings *) + +(*val charEqual : char -> char -> bool*) + +(*val stringEquality : string -> string -> bool*) + +(* pairs *) + +(*val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool*) +(*let pairEqual (a1, b1) (a2, b2)= (a1 = a2) && (b1 = b2)*) + +(*val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool*) + +(*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*) +fun pairCompare :: "('a \ 'a \ ordering)\('b \ 'b \ ordering)\ 'a*'b \ 'a*'b \ ordering " where + " pairCompare cmpa cmpb (a1, b1) (a2, b2) = ( + (case cmpa a1 a2 of + LT => LT + | GT => GT + | EQ => cmpb b1 b2 + ))" + + +fun pairLess :: " 'a Ord_class \ 'b Ord_class \ 'b*'a \ 'b*'a \ bool " where + " pairLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( ( + (isLess_method dict_Basic_classes_Ord_b) x1 y1) \ (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \ ((isLess_method dict_Basic_classes_Ord_a) x2 y2)))" + +fun pairLessEq :: " 'a Ord_class \ 'b Ord_class \ 'b*'a \ 'b*'a \ bool " where + " pairLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( ( + (isLess_method dict_Basic_classes_Ord_b) x1 y1) \ (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \ ((isLessEqual_method dict_Basic_classes_Ord_a) x2 y2)))" + + +definition pairGreater :: " 'a Ord_class \ 'b Ord_class \ 'a*'b \ 'a*'b \ bool " where + " pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLess + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )" + +definition pairGreaterEq :: " 'a Ord_class \ 'b Ord_class \ 'a*'b \ 'a*'b \ bool " where + " pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLessEq + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )" + + +definition instance_Basic_classes_Ord_tup2_dict :: " 'a Ord_class \ 'b Ord_class \('a*'b)Ord_class " where + " instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b = ((| + + compare_method = (pairCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b)), + + isLess_method = + (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isLessEqual_method = + (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreater_method = + (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b), + + isGreaterEqual_method = + (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b) |) )" + + + +(* triples *) + +(*val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool*) +(*let tripleEqual (x1, x2, x3) (y1, y2, y3)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))*) + +(*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*) +fun tripleCompare :: "('a \ 'a \ ordering)\('b \ 'b \ ordering)\('c \ 'c \ ordering)\ 'a*'b*'c \ 'a*'b*'c \ ordering " where + " tripleCompare cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2) = ( + pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2)))" + + +fun tripleLess :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'a*'b*'c \ 'a*'b*'c \ bool " where + " tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))" + +fun tripleLessEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'a*'b*'c \ 'a*'b*'c \ bool " where + " tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))" + + +definition tripleGreater :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'c*'b*'a \ 'c*'b*'a \ bool " where + " tripleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLess + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )" + +definition tripleGreaterEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'c*'b*'a \ 'c*'b*'a \ bool " where + " tripleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLessEq + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )" + + +definition instance_Basic_classes_Ord_tup3_dict :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \('a*'b*'c)Ord_class " where + " instance_Basic_classes_Ord_tup3_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c = ((| + + compare_method = (tripleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c)), + + isLess_method = + (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c), + + isLessEqual_method = + (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c), + + isGreater_method = + (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a) |) )" + + +(* quadruples *) + +(*val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool*) +(*let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))*) + +(*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*) +fun quadrupleCompare :: "('a \ 'a \ ordering)\('b \ 'b \ ordering)\('c \ 'c \ ordering)\('d \ 'd \ ordering)\ 'a*'b*'c*'d \ 'a*'b*'c*'d \ ordering " where + " quadrupleCompare cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2))))" + + +fun quadrupleLess :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'a*'b*'c*'d \ 'a*'b*'c*'d \ bool " where + " quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))" + +fun quadrupleLessEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'a*'b*'c*'d \ 'a*'b*'c*'d \ bool " where + " quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))" + + +definition quadrupleGreater :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'd*'c*'b*'a \ 'd*'c*'b*'a \ bool " where + " quadrupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLess + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )" + +definition quadrupleGreaterEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'd*'c*'b*'a \ 'd*'c*'b*'a \ bool " where + " quadrupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLessEq + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )" + + +definition instance_Basic_classes_Ord_tup4_dict :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \('a*'b*'c*'d)Ord_class " where + " instance_Basic_classes_Ord_tup4_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d = ((| + + compare_method = (quadrupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d)), + + isLess_method = + (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d), + + isLessEqual_method = + (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d), + + isGreater_method = + (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )" + + +(* quintuples *) + +(*val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool*) +(*let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))*) + +(*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*) +fun quintupleCompare :: "('a \ 'a \ ordering)\('b \ 'b \ ordering)\('c \ 'c \ ordering)\('d \ 'd \ ordering)\('e \ 'e \ ordering)\ 'a*'b*'c*'d*'e \ 'a*'b*'c*'d*'e \ ordering " where + " quintupleCompare cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2)))))" + + +fun quintupleLess :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'a*'b*'c*'d*'e \ 'a*'b*'c*'d*'e \ bool " where + " quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))" + +fun quintupleLessEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'a*'b*'c*'d*'e \ 'a*'b*'c*'d*'e \ bool " where + " quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))" + + +definition quintupleGreater :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'e*'d*'c*'b*'a \ 'e*'d*'c*'b*'a \ bool " where + " quintupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLess + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )" + +definition quintupleGreaterEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'e*'d*'c*'b*'a \ 'e*'d*'c*'b*'a \ bool " where + " quintupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLessEq + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )" + + +definition instance_Basic_classes_Ord_tup5_dict :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \('a*'b*'c*'d*'e)Ord_class " where + " instance_Basic_classes_Ord_tup5_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e = ((| + + compare_method = (quintupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e)), + + isLess_method = + (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e), + + isLessEqual_method = + (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e), + + isGreater_method = + (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a) |) )" + + +(* sextuples *) + +(*val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool*) +(*let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))*) + +(*val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) -> + ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*) +fun sextupleCompare :: "('a \ 'a \ ordering)\('b \ 'b \ ordering)\('c \ 'c \ ordering)\('d \ 'd \ ordering)\('e \ 'e \ ordering)\('f \ 'f \ ordering)\ 'a*'b*'c*'d*'e*'f \ 'a*'b*'c*'d*'e*'f \ ordering " where + " sextupleCompare cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2))))))" + + +fun sextupleLess :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'f Ord_class \ 'a*'b*'c*'d*'e*'f \ 'a*'b*'c*'d*'e*'f \ bool " where + " sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))" + +fun sextupleLessEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'f Ord_class \ 'a*'b*'c*'d*'e*'f \ 'a*'b*'c*'d*'e*'f \ bool " where + " sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))" + + +definition sextupleGreater :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'f Ord_class \ 'f*'e*'d*'c*'b*'a \ 'f*'e*'d*'c*'b*'a \ bool " where + " sextupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLess + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )" + +definition sextupleGreaterEq :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'f Ord_class \ 'f*'e*'d*'c*'b*'a \ 'f*'e*'d*'c*'b*'a \ bool " where + " sextupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLessEq + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )" + + +definition instance_Basic_classes_Ord_tup6_dict :: " 'a Ord_class \ 'b Ord_class \ 'c Ord_class \ 'd Ord_class \ 'e Ord_class \ 'f Ord_class \('a*'b*'c*'d*'e*'f)Ord_class " where + " instance_Basic_classes_Ord_tup6_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f = ((| + + compare_method = (sextupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e) (compare_method dict_Basic_classes_Ord_f)), + + isLess_method = + (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f), + + isLessEqual_method = + (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f), + + isGreater_method = + (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_bool.thy b/snapshots/isabelle/lib/lem/Lem_bool.thy new file mode 100644 index 00000000..75142160 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_bool.thy @@ -0,0 +1,75 @@ +chapter \Generated by Lem from bool.lem.\ + +theory "Lem_bool" + +imports + Main + +begin + + + +(* The type bool is hard-coded, so are true and false *) + +(* ----------------------- *) +(* not *) +(* ----------------------- *) + +(*val not : bool -> bool*) +(*let not b= match b with + | true -> false + | false -> true +end*) + +(* ----------------------- *) +(* and *) +(* ----------------------- *) + +(*val && [and] : bool -> bool -> bool*) +(*let && b1 b2= match (b1, b2) with + | (true, true) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* or *) +(* ----------------------- *) + +(*val || [or] : bool -> bool -> bool*) +(*let || b1 b2= match (b1, b2) with + | (false, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* implication *) +(* ----------------------- *) + +(*val --> [imp] : bool -> bool -> bool*) +(*let --> b1 b2= match (b1, b2) with + | (true, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* equivalence *) +(* ----------------------- *) + +(*val <-> [equiv] : bool -> bool -> bool*) +(*let <-> b1 b2= match (b1, b2) with + | (true, true) -> true + | (false, false) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* xor *) +(* ----------------------- *) + +(*val xor : bool -> bool -> bool*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_either.thy b/snapshots/isabelle/lib/lem/Lem_either.thy new file mode 100644 index 00000000..e181f823 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_either.thy @@ -0,0 +1,85 @@ +chapter \Generated by Lem from either.lem.\ + +theory "Lem_either" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_list" + "Lem_tuple" + +begin + + + +(*open import Bool Basic_classes List Tuple*) +(*open import {hol} `sumTheory`*) +(*open import {ocaml} `Either`*) + +(*type either 'a 'b + = Left of 'a + | Right of 'b*) + + +(* -------------------------------------------------------------------------- *) +(* Equality. *) +(* -------------------------------------------------------------------------- *) + +(*val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool*) +(*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*) + +definition eitherEqualBy :: "('a \ 'a \ bool)\('b \ 'b \ bool)\('a,'b)sum \('a,'b)sum \ bool " where + " eitherEqualBy eql eqr (left:: ('a, 'b) sum) (right:: ('a, 'b) sum) = ( + (case (left, right) of + (Inl l, Inl l') => eql l l' + | (Inr r, Inr r') => eqr r r' + | _ => False + ))" + +(*let eitherEqual= eitherEqualBy (=) (=)*) + +fun either_setElemCompare :: "('d \ 'b \ ordering)\('c \ 'a \ ordering)\('d,'c)sum \('b,'a)sum \ ordering " where + " either_setElemCompare cmpa cmpb (Inl x') (Inl y') = ( cmpa x' y' )" +|" either_setElemCompare cmpa cmpb (Inr x') (Inr y') = ( cmpb x' y' )" +|" either_setElemCompare cmpa cmpb (Inl _) (Inr _) = ( LT )" +|" either_setElemCompare cmpa cmpb (Inr _) (Inl _) = ( GT )" + + + +(* -------------------------------------------------------------------------- *) +(* Utility functions. *) +(* -------------------------------------------------------------------------- *) + +(*val isLeft : forall 'a 'b. either 'a 'b -> bool*) + +(*val isRight : forall 'a 'b. either 'a 'b -> bool*) + + +(*val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c*) +(*let either fa fb x= match x with + | Left a -> fa a + | Right b -> fb b +end*) + + +(*val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)*) +(*let rec partitionEither l= match l with + | [] -> ([], []) + | x :: xs -> begin + let (ll, rl) = partitionEither xs in + match x with + | Left l -> (l::ll, rl) + | Right r -> (ll, r::rl) + end + end +end*) + + +(*val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a*) + + +(*val rights : forall 'a 'b. list (either 'a 'b) -> list 'b*) + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_function.thy b/snapshots/isabelle/lib/lem/Lem_function.thy new file mode 100644 index 00000000..29c1fb04 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_function.thy @@ -0,0 +1,72 @@ +chapter \Generated by Lem from function.lem.\ + +theory "Lem_function" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + +begin + +(******************************************************************************) +(* A library for common operations on functions *) +(******************************************************************************) + +(*open import Bool Basic_classes*) + +(*open import {coq} `Program.Basics`*) + +(* ----------------------- *) +(* identity function *) +(* ----------------------- *) + +(*val id : forall 'a. 'a -> 'a*) +(*let id x= x*) + + +(* ----------------------- *) +(* constant function *) +(* ----------------------- *) + +(*val const : forall 'a 'b. 'a -> 'b -> 'a*) + + +(* ----------------------- *) +(* function composition *) +(* ----------------------- *) + +(*val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)*) +(*let comb f g= (fun x -> f (g x))*) + + +(* ----------------------- *) +(* function application *) +(* ----------------------- *) + +(*val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)*) +(*let $ f= (fun x -> f x)*) + +(*val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b*) +(*let $> x f= f x*) + +(* ----------------------- *) +(* flipping argument order *) +(* ----------------------- *) + +(*val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)*) +(*let flip f= (fun x y -> f y x)*) + + +(* currying / uncurrying *) + +(*val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c*) +definition curry :: "('a*'b \ 'c)\ 'a \ 'b \ 'c " where + " curry f = ( (\ a b . f (a, b)))" + + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) +fun uncurry :: "('a \ 'b \ 'c)\ 'a*'b \ 'c " where + " uncurry f (a,b) = ( f a b )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_function_extra.thy b/snapshots/isabelle/lib/lem/Lem_function_extra.thy new file mode 100644 index 00000000..f742e1e6 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_function_extra.thy @@ -0,0 +1,29 @@ +chapter \Generated by Lem from function_extra.lem.\ + +theory "Lem_function_extra" + +imports + Main + "Lem_maybe" + "Lem_bool" + "Lem_basic_classes" + "Lem_num" + "Lem_function" + "Lem" + +begin + + + +(*open import Maybe Bool Basic_classes Num Function*) + +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* getting a unique value *) +(* ----------------------- *) + +(*val THE : forall 'a. ('a -> bool) -> maybe 'a*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_list.thy b/snapshots/isabelle/lib/lem/Lem_list.thy new file mode 100644 index 00000000..3bdef057 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_list.thy @@ -0,0 +1,776 @@ +chapter \Generated by Lem from list.lem.\ + +theory "Lem_list" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_basic_classes" + "Lem_function" + "Lem_tuple" + "Lem_num" + "Lem" + +begin + + + +(*open import Bool Maybe Basic_classes Function Tuple Num*) + +(*open import {coq} `Coq.Lists.List`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) +(*open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`*) + +(* ========================================================================== *) +(* Basic list functions *) +(* ========================================================================== *) + +(* The type of lists as well as list literals like [], [1;2], ... are hardcoded. + Thus, we can directly dive into derived definitions. *) + + +(* ----------------------- *) +(* cons *) +(* ----------------------- *) + +(*val :: : forall 'a. 'a -> list 'a -> list 'a*) + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. list 'a -> bool*) +(*let null l= match l with [] -> true | _ -> false end*) + +(* ----------------------- *) +(* Length *) +(* ----------------------- *) + +(*val length : forall 'a. list 'a -> nat*) +(*let rec length l= + match l with + | [] -> 0 + | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1 + end*) + +(* ----------------------- *) +(* Equality *) +(* ----------------------- *) + +(*val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + +fun listEqualBy :: "('a \ 'a \ bool)\ 'a list \ 'a list \ bool " where + " listEqualBy eq ([]) ([]) = ( True )" +|" listEqualBy eq ([]) (_ # _) = ( False )" +|" listEqualBy eq (_ # _) ([]) = ( False )" +|" listEqualBy eq (x # xs) (y # ys) = ( (eq x y \ listEqualBy eq xs ys))" + + + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> ordering*) +(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a -> ordering*) + +fun lexicographicCompareBy :: "('a \ 'a \ ordering)\ 'a list \ 'a list \ ordering " where + " lexicographicCompareBy cmp ([]) ([]) = ( EQ )" +|" lexicographicCompareBy cmp ([]) (_ # _) = ( LT )" +|" lexicographicCompareBy cmp (_ # _) ([]) = ( GT )" +|" lexicographicCompareBy cmp (x # xs) (y # ys) = ( ( + (case cmp x y of + LT => LT + | GT => GT + | EQ => lexicographicCompareBy cmp xs ys + ) + ))" + + +(*val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) +fun lexicographicLessBy :: "('a \ 'a \ bool)\('a \ 'a \ bool)\ 'a list \ 'a list \ bool " where + " lexicographicLessBy less1 less_eq1 ([]) ([]) = ( False )" +|" lexicographicLessBy less1 less_eq1 ([]) (_ # _) = ( True )" +|" lexicographicLessBy less1 less_eq1 (_ # _) ([]) = ( False )" +|" lexicographicLessBy less1 less_eq1 (x # xs) (y # ys) = ( ((less1 x y) \ ((less_eq1 x y) \ (lexicographicLessBy less1 less_eq1 xs ys))))" + + +(*val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) +fun lexicographicLessEqBy :: "('a \ 'a \ bool)\('a \ 'a \ bool)\ 'a list \ 'a list \ bool " where + " lexicographicLessEqBy less1 less_eq1 ([]) ([]) = ( True )" +|" lexicographicLessEqBy less1 less_eq1 ([]) (_ # _) = ( True )" +|" lexicographicLessEqBy less1 less_eq1 (_ # _) ([]) = ( False )" +|" lexicographicLessEqBy less1 less_eq1 (x # xs) (y # ys) = ( (less1 x y \ (less_eq1 x y \ lexicographicLessEqBy less1 less_eq1 xs ys)))" + + + +definition instance_Basic_classes_Ord_list_dict :: " 'a Ord_class \('a list)Ord_class " where + " instance_Basic_classes_Ord_list_dict dict_Basic_classes_Ord_a = ((| + + compare_method = (lexicographicCompareBy + (compare_method dict_Basic_classes_Ord_a)), + + isLess_method = (lexicographicLessBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)), + + isLessEqual_method = (lexicographicLessEqBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)), + + isGreater_method = (\ x y. (lexicographicLessBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x)), + + isGreaterEqual_method = (\ x y. (lexicographicLessEqBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x))|) )" + + + +(* ----------------------- *) +(* Append *) +(* ----------------------- *) + +(*val ++ : forall 'a. list 'a -> list 'a -> list 'a*) (* originally append *) +(*let rec ++ xs ys= match xs with + | [] -> ys + | x :: xs' -> x :: (xs' ++ ys) + end*) + +(* ----------------------- *) +(* snoc *) +(* ----------------------- *) + +(*val snoc : forall 'a. 'a -> list 'a -> list 'a*) +(*let snoc e l= l ++ [e]*) + + +(* ----------------------- *) +(* Reverse *) +(* ----------------------- *) + +(* First lets define the function [reverse_append], which is + closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1]. + This can be implemented more efficienctly than appending and is + used to implement reverse. *) + +(*val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a*) (* originally named rev_append *) +(*let rec reverseAppend l1 l2= match l1 with + | [] -> l2 + | x :: xs -> reverseAppend xs (x :: l2) + end*) + +(* Reversing a list *) +(*val reverse : forall 'a. list 'a -> list 'a*) (* originally named rev *) +(*let reverse l= reverseAppend l []*) + +(* ----------------------- *) +(* Map *) +(* ----------------------- *) + +(*val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b*) +function (sequential,domintros) map_tr :: " 'b list \('a \ 'b)\ 'a list \ 'b list " where + " map_tr rev_acc f ([]) = ( List.rev rev_acc )" +|" map_tr rev_acc f (x # xs) = ( map_tr ((f x) # rev_acc) f xs )" +by pat_completeness auto + + +(* taken from: https://blogs.janestreet.com/optimizing-list-map/ *) +(*val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b*) +function (sequential,domintros) count_map :: "('a \ 'b)\ 'a list \ nat \ 'b list " where + " count_map f ([]) ctr = ( [])" +|" count_map f (hd1 # tl1) ctr = ( f hd1 # + (if ctr <( 5000 :: nat) then count_map f tl1 (ctr +( 1 :: nat)) + else map_tr [] f tl1))" +by pat_completeness auto + + +(*val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) +(*let map f l= count_map f l 0*) + +(* ----------------------- *) +(* Reverse Map *) +(* ----------------------- *) + +(*val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) + + +(* ========================================================================== *) +(* Folding *) +(* ========================================================================== *) + +(* ----------------------- *) +(* fold left *) +(* ----------------------- *) + +(*val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a*) (* originally foldl *) + +(*let rec foldl f b l= match l with + | [] -> b + | x :: xs -> foldl f (f b x) xs +end*) + + +(* ----------------------- *) +(* fold right *) +(* ----------------------- *) + +(*val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b*) (* originally foldr with different argument order *) +(*let rec foldr f b l= match l with + | [] -> b + | x :: xs -> f x (foldr f b xs) +end*) + + +(* ----------------------- *) +(* concatenating lists *) +(* ----------------------- *) + +(*val concat : forall 'a. list (list 'a) -> list 'a*) (* before also called flatten *) +(*let concat= foldr (++) []*) + + +(* -------------------------- *) +(* concatenating with mapping *) +(* -------------------------- *) + +(*val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b*) + + +(* ------------------------- *) +(* universal qualification *) +(* ------------------------- *) + +(*val all : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally for_all *) +(*let all P l= foldl (fun r e -> P e && r) true l*) + + + +(* ------------------------- *) +(* existential qualification *) +(* ------------------------- *) + +(*val any : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally exist *) +(*let any P l= foldl (fun r e -> P e || r) false l*) + + +(* ------------------------- *) +(* dest_init *) +(* ------------------------- *) + +(* get the initial part and the last element of the list in a safe way *) + +(*val dest_init : forall 'a. list 'a -> maybe (list 'a * 'a)*) + +fun dest_init_aux :: " 'a list \ 'a \ 'a list \ 'a list*'a " where + " dest_init_aux rev_init last_elem_seen ([]) = ( (List.rev rev_init, last_elem_seen))" +|" dest_init_aux rev_init last_elem_seen (x # xs) = ( dest_init_aux (last_elem_seen # rev_init) x xs )" + + +fun dest_init :: " 'a list \('a list*'a)option " where + " dest_init ([]) = ( None )" +|" dest_init (x # xs) = ( Some (dest_init_aux [] x xs))" + + + +(* ========================================================================== *) +(* Indexing lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* index / nth with maybe *) +(* ------------------------- *) + +(*val index : forall 'a. list 'a -> nat -> maybe 'a*) + +(*let rec index l n= match l with + | [] -> Nothing + | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then Just x else index xs ((Instance_Num_NumMinus_nat.-)n 1) +end*) + +(* ------------------------- *) +(* findIndices *) +(* ------------------------- *) + +(* [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P]. + Counting starts with 0, the result list is sorted ascendingly *) +(*val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat*) + +fun findIndices_aux :: " nat \('a \ bool)\ 'a list \(nat)list " where + " findIndices_aux (i::nat) P ([]) = ( [])" +|" findIndices_aux (i::nat) P (x # xs) = ( if P x then i # findIndices_aux (i +( 1 :: nat)) P xs else findIndices_aux (i +( 1 :: nat)) P xs )" + +(*let findIndices P l= findIndices_aux 0 P l*) + + + +(* ------------------------- *) +(* findIndex *) +(* ------------------------- *) + +(* findIndex returns the first index of a list that satisfies a given predicate. *) +(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> maybe nat*) +(*let findIndex P l= match findIndices P l with + | [] -> Nothing + | x :: _ -> Just x +end*) + +(* ------------------------- *) +(* elemIndices *) +(* ------------------------- *) + +(*val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat*) + +(* ------------------------- *) +(* elemIndex *) +(* ------------------------- *) + +(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> maybe nat*) + + +(* ========================================================================== *) +(* Creating lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* genlist *) +(* ------------------------- *) + +(* [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] *) +(*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*) + + +(*let rec genlist f n= + match n with + | 0 -> [] + | n' + 1 -> snoc (f n') (genlist f n') + end*) + + +(* ------------------------- *) +(* replicate *) +(* ------------------------- *) + +(*val replicate : forall 'a. nat -> 'a -> list 'a*) +(*let rec replicate n x= + match n with + | 0 -> [] + | n' + 1 -> x :: replicate n' x + end*) + + +(* ========================================================================== *) +(* Sublists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* splitAt *) +(* ------------------------- *) + +(* [splitAt n xs] returns a tuple (xs1, xs2), with append xs1 xs2 = xs and + length xs1 = n. If there are not enough elements + in [xs], the original list and the empty one are returned. *) +(*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*) +function (sequential,domintros) splitAtAcc :: " 'a list \ nat \ 'a list \ 'a list*'a list " where + " splitAtAcc revAcc n l = ( + (case l of + [] => (List.rev revAcc, []) + | x # xs => if n \( 0 :: nat) then (List.rev revAcc, l) else splitAtAcc (x # revAcc) (n-( 1 :: nat)) xs + ))" +by pat_completeness auto + + +(*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*) +(*let rec splitAt n l= + splitAtAcc [] n l*) + + +(* ------------------------- *) +(* take *) +(* ------------------------- *) + +(* take n xs returns the prefix of xs of length n, or xs itself if n > length xs *) +(*val take : forall 'a. nat -> list 'a -> list 'a*) +(*let take n l= fst (splitAt n l)*) + +(* ------------------------- *) +(* drop *) +(* ------------------------- *) + +(* [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. *) +(*val drop : forall 'a. nat -> list 'a -> list 'a*) +(*let drop n l= snd (splitAt n l)*) + +(* ------------------------------------ *) +(* splitWhile, takeWhile, and dropWhile *) +(* ------------------------------------ *) + +(*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*) +fun splitWhile_tr :: "('a \ bool)\ 'a list \ 'a list \ 'a list*'a list " where + " splitWhile_tr p ([]) acc1 = ( + (List.rev acc1, []))" +|" splitWhile_tr p (x # xs) acc1 = ( + if p x then + splitWhile_tr p xs (x # acc1) + else + (List.rev acc1, (x # xs)))" + + +(*val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)*) +definition splitWhile :: "('a \ bool)\ 'a list \ 'a list*'a list " where + " splitWhile p xs = ( splitWhile_tr p xs [])" + + +(* [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. *) +(*val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +definition takeWhile :: "('a \ bool)\ 'a list \ 'a list " where + " takeWhile p l = ( fst (splitWhile p l))" + + +(* [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. *) +(*val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +definition dropWhile :: "('a \ bool)\ 'a list \ 'a list " where + " dropWhile p l = ( snd (splitWhile p l))" + + +(* ------------------------- *) +(* isPrefixOf *) +(* ------------------------- *) + +(*val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +fun isPrefixOf :: " 'a list \ 'a list \ bool " where + " isPrefixOf ([]) _ = ( True )" +|" isPrefixOf (_ # _) ([]) = ( False )" +|" isPrefixOf (x # xs) (y # ys) = ( (x = y) \ isPrefixOf xs ys )" + + +(* ------------------------- *) +(* update *) +(* ------------------------- *) +(*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*) +(*let rec update l n e= + match l with + | [] -> [] + | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e) +end*) + + + +(* ========================================================================== *) +(* Searching lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* Membership test *) +(* ------------------------- *) + +(* The membership test, one of the basic list functions, is actually tricky for + Lem, because it is tricky, which equality to use. From Lem`s point of + perspective, we want to use the equality provided by the equality type - class. + This allows for example to check whether a set is in a list of sets. + + However, in order to use the equality type class, elem essentially becomes + existential quantification over lists. For types, which implement semantic + equality (=) with syntactic equality, this is overly complicated. In + our theorem prover backend, we would end up with overly complicated, harder + to read definitions and some of the automation would be harder to apply. + Moreover, nearly all the old Lem generated code would change and require + (hopefully minor) adaptions of proofs. + + For now, we ignore this problem and just demand, that all instances of + the equality type class do the right thing for the theorem prover backends. +*) + +(*val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool*) +(*val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool*) + +definition elemBy :: "('a \ 'a \ bool)\ 'a \ 'a list \ bool " where + " elemBy eq e l = ( ((\ x \ (set l). (eq e) x)))" + +(*let elem= elemBy (=)*) + +(* ------------------------- *) +(* Find *) +(* ------------------------- *) +(*val find : forall 'a. ('a -> bool) -> list 'a -> maybe 'a*) (* previously not of maybe type *) +(*let rec find P l= match l with + | [] -> Nothing + | x :: xs -> if P x then Just x else find P xs +end*) + + +(* ----------------------------- *) +(* Lookup in an associative list *) +(* ----------------------------- *) +(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> maybe 'b*) +(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> maybe 'b*) + +(* DPM: eta-expansion for Coq backend type-inference. *) +definition lookupBy :: "('a \ 'a \ bool)\ 'a \('a*'b)list \ 'b option " where + " lookupBy eq k m = ( map_option (\ x . snd x) (List.find ( \x . + (case x of (k', _) => eq k k' )) m))" + + +(* ------------------------- *) +(* filter *) +(* ------------------------- *) +(*val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +(*let rec filter P l= match l with + | [] -> [] + | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs + end*) + + +(* ------------------------- *) +(* partition *) +(* ------------------------- *) +(*val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +(*let partition P l= (filter P l, filter (fun x -> not (P x)) l)*) + +(*val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +definition reversePartition :: "('a \ bool)\ 'a list \ 'a list*'a list " where + " reversePartition P l = ( List.partition P (List.rev l))" + + + +(* ------------------------- *) +(* delete first element *) +(* with certain property *) +(* ------------------------- *) + +(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> maybe (list 'a)*) +(*let rec deleteFirst P l= match l with + | [] -> Nothing + | x :: xs -> if (P x) then Just xs else Maybe.map (fun xs' -> x :: xs') (deleteFirst P xs) + end*) + + +(*val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a*) +(*val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +definition deleteBy :: "('a \ 'a \ bool)\ 'a \ 'a list \ 'a list " where + " deleteBy eq x l = ( case_option l id (delete_first (eq x) l))" + + + +(* ========================================================================== *) +(* Zipping and unzipping lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* zip *) +(* ------------------------- *) + +(* zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. *) +(*val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) (* before combine *) +(*let rec zip l1 l2= match (l1, l2) with + | (x :: xs, y :: ys) -> (x, y) :: zip xs ys + | _ -> [] +end*) + +(* ------------------------- *) +(* unzip *) +(* ------------------------- *) + +(*val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)*) +(*let rec unzip l= match l with + | [] -> ([], []) + | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys) +end*) + +(* ------------------------- *) +(* distinct elements *) +(* ------------------------- *) + +(*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*) +fun allDistinct :: " 'a list \ bool " where + " allDistinct ([]) = ( True )" +|" allDistinct (x # l') = ( \ (Set.member x (set l')) \ allDistinct l' )" + + +(* some more useful functions *) +(*val mapMaybe : forall 'a 'b. ('a -> maybe 'b) -> list 'a -> list 'b*) +function (sequential,domintros) mapMaybe :: "('a \ 'b option)\ 'a list \ 'b list " where + " mapMaybe f ([]) = ( [])" +|" mapMaybe f (x # xs) = ( + (case f x of + None => mapMaybe f xs + | Some y => y # (mapMaybe f xs) + ))" +by pat_completeness auto + + +(*val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b*) +function (sequential,domintros) mapiAux :: "(nat \ 'b \ 'a)\ nat \ 'b list \ 'a list " where + " mapiAux f (n :: nat) ([]) = ( [])" +|" mapiAux f (n :: nat) (x # xs) = ( (f n x) # mapiAux f (n +( 1 :: nat)) xs )" +by pat_completeness auto + +definition mapi :: "(nat \ 'a \ 'b)\ 'a list \ 'b list " where + " mapi f l = ( mapiAux f(( 0 :: nat)) l )" + + +(*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*) +definition deletes :: " 'a list \ 'a list \ 'a list " where + " deletes xs ys = ( + List.foldl ((\ x y. remove1 y x)) xs ys )" + + +(* ========================================================================== *) +(* Comments (not clean yet, please ignore the rest of the file) *) +(* ========================================================================== *) + +(* ----------------------- *) +(* skipped from Haskell Lib*) +(* ----------------------- + +intersperse :: a -> [a] -> [a] +intercalate :: [a] -> [[a]] -> [a] +transpose :: [[a]] -> [[a]] +subsequences :: [a] -> [[a]] +permutations :: [a] -> [[a]] +foldl` :: (a -> b -> a) -> a -> [b] -> aSource +foldl1` :: (a -> a -> a) -> [a] -> aSource + +and +or +sum +product +maximum +minimum +scanl +scanr +scanl1 +scanr1 +Accumulating maps + +mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source +mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source + +iterate :: (a -> a) -> a -> [a] +repeat :: a -> [a] +cycle :: [a] -> [a] +unfoldr + + +takeWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source +span :: (a -> Bool) -> [a] -> ([a], [a])Source +break :: (a -> Bool) -> [a] -> ([a], [a])Source +break p is equivalent to span (not . p). +stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source +group :: Eq a => [a] -> [[a]]Source +inits :: [a] -> [[a]]Source +tails :: [a] -> [[a]]Source + + +isPrefixOf :: Eq a => [a] -> [a] -> BoolSource +isSuffixOf :: Eq a => [a] -> [a] -> BoolSource +isInfixOf :: Eq a => [a] -> [a] -> BoolSource + + + +notElem :: Eq a => a -> [a] -> BoolSource + +zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source +zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source +zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source +zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source +zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source + +zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source +zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source +zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source +zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source +zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source +zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source + + +unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source +unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source +unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source +unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source +unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source + + +lines :: String -> [String]Source +words :: String -> [String]Source +unlines :: [String] -> StringSource +unwords :: [String] -> StringSource +nub :: Eq a => [a] -> [a]Source +delete :: Eq a => a -> [a] -> [a]Source + +() :: Eq a => [a] -> [a] -> [a]Source +union :: Eq a => [a] -> [a] -> [a]Source +intersect :: Eq a => [a] -> [a] -> [a]Source +sort :: Ord a => [a] -> [a]Source +insert :: Ord a => a -> [a] -> [a]Source + + +nubBy :: (a -> a -> Bool) -> [a] -> [a]Source +deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source +deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source +sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source +insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source +maximumBy :: (a -> a -> Ordering) -> [a] -> aSource +minimumBy :: (a -> a -> Ordering) -> [a] -> aSource +genericLength :: Num i => [b] -> iSource +genericTake :: Integral i => i -> [a] -> [a]Source +genericDrop :: Integral i => i -> [a] -> [a]Source +genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source +genericIndex :: Integral a => [b] -> a -> bSource +genericReplicate :: Integral i => i -> a -> [a]Source + + +*) + + +(* ----------------------- *) +(* skipped from Lem Lib *) +(* ----------------------- + + +val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a +val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c + + +(* now maybe result and called lookup *) +val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b +let inline {ocaml} assoc = Ocaml.List.assoc + + +val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool +val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b) + + + +val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a +val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a + +val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a +val intersect : forall 'a. list 'a -> list 'a -> list 'a + + +*) + +(*val catMaybes : forall 'a. list (maybe 'a) -> list 'a*) +function (sequential,domintros) catMaybes :: "('a option)list \ 'a list " where + " catMaybes ([]) = ( + [])" +|" catMaybes (None # xs') = ( + catMaybes xs' )" +|" catMaybes (Some x # xs') = ( + x # catMaybes xs' )" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/lem/Lem_list_extra.thy b/snapshots/isabelle/lib/lem/Lem_list_extra.thy new file mode 100644 index 00000000..9caf32fc --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_list_extra.thy @@ -0,0 +1,117 @@ +chapter \Generated by Lem from list_extra.lem.\ + +theory "Lem_list_extra" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_basic_classes" + "Lem_tuple" + "Lem_num" + "Lem_list" + "Lem_assert_extra" + +begin + + + +(*open import Bool Maybe Basic_classes Tuple Num List Assert_extra*) + +(* ------------------------- *) +(* head of non-empty list *) +(* ------------------------- *) +(*val head : forall 'a. list 'a -> 'a*) +(*let head l= match l with | x::xs -> x | [] -> failwith List_extra.head of empty list end*) + + +(* ------------------------- *) +(* tail of non-empty list *) +(* ------------------------- *) +(*val tail : forall 'a. list 'a -> list 'a*) +(*let tail l= match l with | x::xs -> xs | [] -> failwith List_extra.tail of empty list end*) + + +(* ------------------------- *) +(* last *) +(* ------------------------- *) +(*val last : forall 'a. list 'a -> 'a*) +(*let rec last l= match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith List_extra.last of empty list end*) + + +(* ------------------------- *) +(* init *) +(* ------------------------- *) + +(* All elements of a non-empty list except the last one. *) +(*val init : forall 'a. list 'a -> list 'a*) +(*let rec init l= match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith List_extra.init of empty list end*) + + +(* ------------------------- *) +(* foldl1 / foldr1 *) +(* ------------------------- *) + +(* folding functions for non-empty lists, + which don`t take the base case *) +(*val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +fun foldl1 :: "('a \ 'a \ 'a)\ 'a list \ 'a " where + " foldl1 f (x # xs) = ( List.foldl f x xs )" +|" foldl1 f ([]) = ( failwith (''List_extra.foldl1 of empty list''))" + + +(*val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +fun foldr1 :: "('a \ 'a \ 'a)\ 'a list \ 'a " where + " foldr1 f (x # xs) = ( List.foldr f xs x )" +|" foldr1 f ([]) = ( failwith (''List_extra.foldr1 of empty list''))" + + + +(* ------------------------- *) +(* nth element *) +(* ------------------------- *) + +(* get the nth element of a list *) +(*val nth : forall 'a. list 'a -> nat -> 'a*) +(*let nth l n= match index l n with Just e -> e | Nothing -> failwith List_extra.nth end*) + + +(* ------------------------- *) +(* Find_non_pure *) +(* ------------------------- *) +(*val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a*) +definition findNonPure :: "('a \ bool)\ 'a list \ 'a " where + " findNonPure P l = ( (case (List.find P l) of + Some e => e + | None => failwith (''List_extra.findNonPure'') +))" + + + +(* ------------------------- *) +(* zip same length *) +(* ------------------------- *) + +(*val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) +fun zipSameLength :: " 'a list \ 'b list \('a*'b)list " where + " zipSameLength l1 l2 = ( (case (l1, l2) of + (x # xs, y # ys) => (x, y) # zipSameLength xs ys + | ([], []) => [] + | _ => failwith (''List_extra.zipSameLength of different length lists'') + +))" + + +(*val unfoldr: forall 'a 'b. ('a -> maybe ('b * 'a)) -> 'a -> list 'b*) +function (sequential,domintros) unfoldr :: "('a \('b*'a)option)\ 'a \ 'b list " where + " unfoldr f x = ( + (case f x of + Some (y, x') => + y # unfoldr f x' + | None => + [] + ))" +by pat_completeness auto + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_machine_word.thy b/snapshots/isabelle/lib/lem/Lem_machine_word.thy new file mode 100644 index 00000000..3f83789c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_machine_word.thy @@ -0,0 +1,450 @@ +chapter \Generated by Lem from machine_word.lem.\ + +theory "Lem_machine_word" + +imports + Main + "Lem_bool" + "Lem_num" + "Lem_basic_classes" + "Lem_show" + "~~/src/HOL/Word/Word" + +begin + + + +(*open import Bool Num Basic_classes Show*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*) + +(*type mword 'a*) + +(*class (Size 'a) + val size : nat +end*) + +(*val native_size : forall 'a. nat*) + +(*val ocaml_inject : forall 'a. nat * natural -> mword 'a*) + +(* A singleton type family that can be used to carry a size as the type parameter *) + +(*type itself 'a*) + +(*val the_value : forall 'a. itself 'a*) + +(*val size_itself : forall 'a. Size 'a => itself 'a -> nat*) +definition size_itself :: "('a::len)itself \ nat " where + " size_itself x = ( (len_of (TYPE(_) :: 'a itself)))" + + +(*******************************************************************) +(* Fixed bitwidths extracted from Anthony's models. *) +(* *) +(* If you need a size N that is not included here, put the lines *) +(* *) +(* type tyN *) +(* instance (Size tyN) let size = N end *) +(* declare isabelle target_rep type tyN = `N` *) +(* declare hol target_rep type tyN = `N` *) +(* *) +(* in your project, replacing N in each line. *) +(*******************************************************************) + +(*type ty1*) +(*type ty2*) +(*type ty3*) +(*type ty4*) +(*type ty5*) +(*type ty6*) +(*type ty7*) +(*type ty8*) +(*type ty9*) +(*type ty10*) +(*type ty11*) +(*type ty12*) +(*type ty13*) +(*type ty14*) +(*type ty15*) +(*type ty16*) +(*type ty17*) +(*type ty18*) +(*type ty19*) +(*type ty20*) +(*type ty21*) +(*type ty22*) +(*type ty23*) +(*type ty24*) +(*type ty25*) +(*type ty26*) +(*type ty27*) +(*type ty28*) +(*type ty29*) +(*type ty30*) +(*type ty31*) +(*type ty32*) +(*type ty33*) +(*type ty34*) +(*type ty35*) +(*type ty36*) +(*type ty37*) +(*type ty38*) +(*type ty39*) +(*type ty40*) +(*type ty41*) +(*type ty42*) +(*type ty43*) +(*type ty44*) +(*type ty45*) +(*type ty46*) +(*type ty47*) +(*type ty48*) +(*type ty49*) +(*type ty50*) +(*type ty51*) +(*type ty52*) +(*type ty53*) +(*type ty54*) +(*type ty55*) +(*type ty56*) +(*type ty57*) +(*type ty58*) +(*type ty59*) +(*type ty60*) +(*type ty61*) +(*type ty62*) +(*type ty63*) +(*type ty64*) +(*type ty65*) +(*type ty66*) +(*type ty67*) +(*type ty68*) +(*type ty69*) +(*type ty70*) +(*type ty71*) +(*type ty72*) +(*type ty73*) +(*type ty74*) +(*type ty75*) +(*type ty76*) +(*type ty77*) +(*type ty78*) +(*type ty79*) +(*type ty80*) +(*type ty81*) +(*type ty82*) +(*type ty83*) +(*type ty84*) +(*type ty85*) +(*type ty86*) +(*type ty87*) +(*type ty88*) +(*type ty89*) +(*type ty90*) +(*type ty91*) +(*type ty92*) +(*type ty93*) +(*type ty94*) +(*type ty95*) +(*type ty96*) +(*type ty97*) +(*type ty98*) +(*type ty99*) +(*type ty100*) +(*type ty101*) +(*type ty102*) +(*type ty103*) +(*type ty104*) +(*type ty105*) +(*type ty106*) +(*type ty107*) +(*type ty108*) +(*type ty109*) +(*type ty110*) +(*type ty111*) +(*type ty112*) +(*type ty113*) +(*type ty114*) +(*type ty115*) +(*type ty116*) +(*type ty117*) +(*type ty118*) +(*type ty119*) +(*type ty120*) +(*type ty121*) +(*type ty122*) +(*type ty123*) +(*type ty124*) +(*type ty125*) +(*type ty126*) +(*type ty127*) +(*type ty128*) +(*type ty129*) +(*type ty130*) +(*type ty131*) +(*type ty132*) +(*type ty133*) +(*type ty134*) +(*type ty135*) +(*type ty136*) +(*type ty137*) +(*type ty138*) +(*type ty139*) +(*type ty140*) +(*type ty141*) +(*type ty142*) +(*type ty143*) +(*type ty144*) +(*type ty145*) +(*type ty146*) +(*type ty147*) +(*type ty148*) +(*type ty149*) +(*type ty150*) +(*type ty151*) +(*type ty152*) +(*type ty153*) +(*type ty154*) +(*type ty155*) +(*type ty156*) +(*type ty157*) +(*type ty158*) +(*type ty159*) +(*type ty160*) +(*type ty161*) +(*type ty162*) +(*type ty163*) +(*type ty164*) +(*type ty165*) +(*type ty166*) +(*type ty167*) +(*type ty168*) +(*type ty169*) +(*type ty170*) +(*type ty171*) +(*type ty172*) +(*type ty173*) +(*type ty174*) +(*type ty175*) +(*type ty176*) +(*type ty177*) +(*type ty178*) +(*type ty179*) +(*type ty180*) +(*type ty181*) +(*type ty182*) +(*type ty183*) +(*type ty184*) +(*type ty185*) +(*type ty186*) +(*type ty187*) +(*type ty188*) +(*type ty189*) +(*type ty190*) +(*type ty191*) +(*type ty192*) +(*type ty193*) +(*type ty194*) +(*type ty195*) +(*type ty196*) +(*type ty197*) +(*type ty198*) +(*type ty199*) +(*type ty200*) +(*type ty201*) +(*type ty202*) +(*type ty203*) +(*type ty204*) +(*type ty205*) +(*type ty206*) +(*type ty207*) +(*type ty208*) +(*type ty209*) +(*type ty210*) +(*type ty211*) +(*type ty212*) +(*type ty213*) +(*type ty214*) +(*type ty215*) +(*type ty216*) +(*type ty217*) +(*type ty218*) +(*type ty219*) +(*type ty220*) +(*type ty221*) +(*type ty222*) +(*type ty223*) +(*type ty224*) +(*type ty225*) +(*type ty226*) +(*type ty227*) +(*type ty228*) +(*type ty229*) +(*type ty230*) +(*type ty231*) +(*type ty232*) +(*type ty233*) +(*type ty234*) +(*type ty235*) +(*type ty236*) +(*type ty237*) +(*type ty238*) +(*type ty239*) +(*type ty240*) +(*type ty241*) +(*type ty242*) +(*type ty243*) +(*type ty244*) +(*type ty245*) +(*type ty246*) +(*type ty247*) +(*type ty248*) +(*type ty249*) +(*type ty250*) +(*type ty251*) +(*type ty252*) +(*type ty253*) +(*type ty254*) +(*type ty255*) +(*type ty256*) +(*type ty257*) + +(*val word_length : forall 'a. mword 'a -> nat*) + +(******************************************************************) +(* Conversions *) +(******************************************************************) + +(*val signedIntegerFromWord : forall 'a. mword 'a -> integer*) + +(*val unsignedIntegerFromWord : forall 'a. mword 'a -> integer*) + +(* Version without typeclass constraint so that we can derive operations + in Lem for one of the theorem provers without requiring it. *) +(*val proverWordFromInteger : forall 'a. integer -> mword 'a*) + +(*val wordFromInteger : forall 'a. Size 'a => integer -> mword 'a*) +(* The OCaml version is defined after the arithmetic operations, below. *) + +(*val naturalFromWord : forall 'a. mword 'a -> natural*) + +(*val wordFromNatural : forall 'a. Size 'a => natural -> mword 'a*) + +(*val wordToHex : forall 'a. mword 'a -> string*) +(* Building libraries fails if we don't provide implementations for the + type class. *) +definition wordToHex :: "('a::len)Word.word \ string " where + " wordToHex w = ( (''wordToHex not yet implemented''))" + + +definition instance_Show_Show_Machine_word_mword_dict :: "(('a::len)Word.word)Show_class " where + " instance_Show_Show_Machine_word_mword_dict = ((| + + show_method = wordToHex |) )" + + +(*val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a*) + +(*val bitlistFromWord : forall 'a. mword 'a -> list bool*) + + +(*val size_test_fn : forall 'a. Size 'a => mword 'a -> nat*) +definition size_test_fn :: "('a::len)Word.word \ nat " where + " size_test_fn _ = ( (len_of (TYPE(_) :: 'a itself)))" + + +(******************************************************************) +(* Comparisons *) +(******************************************************************) + +(*val mwordEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(* Comparison tests are below, after the definition of wordFromInteger *) + +(******************************************************************) +(* Appending, splitting and probing words *) +(******************************************************************) + +(*val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c*) + +(* Note that we assume the result type has the correct size, especially + for Isabelle. *) +(*val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b*) + +(* Needs to be in the prover because we'd end up with unknown sizes in the + types in Lem. +*) +(*val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a*) + +(*val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a*) + +(*val getBit : forall 'a. mword 'a -> nat -> bool*) + +(*val msb : forall 'a. mword 'a -> bool*) + +(*val lsb : forall 'a. mword 'a -> bool*) + +(******************************************************************) +(* Bitwise operations, shifts, etc. *) +(******************************************************************) + +(*val shiftLeft : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val shiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val lAnd : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lOr : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lXor : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lNot : forall 'a. mword 'a -> mword 'a*) + +(*val rotateRight : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(*val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(* Sign extension tests are below, after the definition of wordFromInteger *) + +(*****************************************************************) +(* Arithmetic *) +(*****************************************************************) + +(*val plus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val minus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val uminus : forall 'a. mword 'a -> mword 'a*) + +(*val times : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) +(*val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +definition signedDivide :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " signedDivide x y = ( + if Bits.msb x then + if Bits.msb y then (- x) div (- y) + else - ((- x) div y) + else if Bits.msb y then - (x div (- y)) + else x div y )" + + +(*val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_map.thy b/snapshots/isabelle/lib/lem/Lem_map.thy new file mode 100644 index 00000000..fbaed71a --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_map.thy @@ -0,0 +1,159 @@ +chapter \Generated by Lem from map.lem.\ + +theory "Lem_map" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + "Lem_maybe" + "Lem_list" + "Lem_tuple" + "Lem_set" + "Lem_num" + +begin + + + +(*open import Bool Basic_classes Function Maybe List Tuple Set Num*) +(*open import {hol} `finite_mapTheory` `finite_mapLib`*) + +(*type map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Map equality. *) +(* -------------------------------------------------------------------------- *) + +(*val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool*) +(*val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* Map type class *) +(* -------------------------------------------------------------------------- *) + +(*class ( MapKeyType 'a ) + val {ocaml;coq} mapKeyCompare : 'a -> 'a -> ordering +end*) + +(* -------------------------------------------------------------------------- *) +(* Empty maps *) +(* -------------------------------------------------------------------------- *) + +(*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*) +(*val emptyBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Insertion *) +(* -------------------------------------------------------------------------- *) + +(*val insert : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Singleton *) +(* -------------------------------------------------------------------------- *) + +(*val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Emptyness check *) +(* -------------------------------------------------------------------------- *) + +(*val null : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* lookup *) +(* -------------------------------------------------------------------------- *) + +(*val lookupBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> maybe 'v*) + +(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> maybe 'v*) + +(* -------------------------------------------------------------------------- *) +(* findWithDefault *) +(* -------------------------------------------------------------------------- *) + +(*val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v*) + +(* -------------------------------------------------------------------------- *) +(* from lists *) +(* -------------------------------------------------------------------------- *) + +(*val fromList : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v*) +(*let fromList l= foldl (fun m (k,v) -> insert k v m) empty l*) + + +(* -------------------------------------------------------------------------- *) +(* to sets / domain / range *) +(* -------------------------------------------------------------------------- *) + +(*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*) +(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> ordering) -> map 'k 'v -> set ('k * 'v)*) + + +(*val domainBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v -> set 'k*) +(*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*) + + +(*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*) +(*val rangeBy : forall 'k 'v. ('v -> 'v -> ordering) -> map 'k 'v -> set 'v*) + + +(* -------------------------------------------------------------------------- *) +(* member *) +(* -------------------------------------------------------------------------- *) + +(*val member : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(*val notMember : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(* -------------------------------------------------------------------------- *) +(* Quantification *) +(* -------------------------------------------------------------------------- *) + +(*val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) +(*val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) + +(*let all P m= (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))*) + + +(* -------------------------------------------------------------------------- *) +(* Set-like operations. *) +(* -------------------------------------------------------------------------- *) +(*val deleteBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> map 'k 'v*) +(*val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*) +(*val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*) + +(*val union : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v*) + +(*val unions : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Maps (in the functor sense). *) +(* -------------------------------------------------------------------------- *) + +(*val map : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(*val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(* -------------------------------------------------------------------------- *) +(* Cardinality *) +(* -------------------------------------------------------------------------- *) +(*val size : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat*) + +(* instance of SetType *) +definition map_setElemCompare :: "(('d*'c)set \('b*'a)set \ 'e)\('d,'c)Map.map \('b,'a)Map.map \ 'e " where + " map_setElemCompare cmp x y = ( + cmp (map_to_set x) (map_to_set y))" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_map_extra.thy b/snapshots/isabelle/lib/lem/Lem_map_extra.thy new file mode 100644 index 00000000..4117fe81 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_map_extra.thy @@ -0,0 +1,82 @@ +chapter \Generated by Lem from map_extra.lem.\ + +theory "Lem_map_extra" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + "Lem_assert_extra" + "Lem_maybe" + "Lem_list" + "Lem_num" + "Lem_set" + "Lem_map" + +begin + + + +(*open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map*) + +(* -------------------------------------------------------------------------- *) +(* find *) +(* -------------------------------------------------------------------------- *) + +(*val find : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> 'v*) +(*let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith Map_extra.find end*) + + + +(* -------------------------------------------------------------------------- *) +(* from sets / domain / range *) +(* -------------------------------------------------------------------------- *) + + +(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> map 'k 'v*) +definition fromSet :: "('k \ 'v)\ 'k set \('k,'v)Map.map " where + " fromSet f s = ( Finite_Set.fold (\ k m . map_update k (f k) m) Map.empty s )" + + +(* +assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty) +assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)] +*) + +(* -------------------------------------------------------------------------- *) +(* fold *) +(* -------------------------------------------------------------------------- *) + +(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> map 'k 'v -> 'r -> 'r*) +definition fold :: "('k \ 'v \ 'r \ 'r)\('k,'v)Map.map \ 'r \ 'r " where + " fold f m v = ( Finite_Set.fold ( \x . + (case x of (k, v) => \ r . f k v r )) v (map_to_set m))" + + +(* +assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9) +assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12) +*) + +(*val toList: forall 'k 'v. MapKeyType 'k => map 'k 'v -> list ('k * 'v)*) +(* declare compile_message toList = Map_extra.toList is only defined for the ocaml, isabelle and coq backend *) + +(* more 'map' functions *) + +(* TODO: this function is in map_extra rather than map just for implementation reasons *) +(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> maybe 'c) -> map 'a 'b -> map 'a 'c*) +(* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *) +definition option_map :: "('a \ 'b \ 'c option)\('a,'b)Map.map \('a,'c)Map.map " where + " option_map f m = ( + List.foldl + (\ m' . \x . + (case x of + (k, v) => + (case f k v of None => m' | Some v' => map_update k v' m' ) + )) + Map.empty + (list_of_set (LemExtraDefs.map_to_set m)))" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_maybe.thy b/snapshots/isabelle/lib/lem/Lem_maybe.thy new file mode 100644 index 00000000..da0bde92 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_maybe.thy @@ -0,0 +1,113 @@ +chapter \Generated by Lem from maybe.lem.\ + +theory "Lem_maybe" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + +begin + + + +(*open import Bool Basic_classes Function*) + +(* ========================================================================== *) +(* Basic stuff *) +(* ========================================================================== *) + +(*type maybe 'a = + | Nothing + | Just of 'a*) + + +(*val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool*) +(*val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool*) + +fun maybeEqualBy :: "('a \ 'a \ bool)\ 'a option \ 'a option \ bool " where + " maybeEqualBy eq None None = ( True )" +|" maybeEqualBy eq None (Some _) = ( False )" +|" maybeEqualBy eq (Some _) None = ( False )" +|" maybeEqualBy eq (Some x') (Some y') = ( (eq x' y'))" + + + +fun maybeCompare :: "('b \ 'a \ ordering)\ 'b option \ 'a option \ ordering " where + " maybeCompare cmp None None = ( EQ )" +|" maybeCompare cmp None (Some _) = ( LT )" +|" maybeCompare cmp (Some _) None = ( GT )" +|" maybeCompare cmp (Some x') (Some y') = ( cmp x' y' )" + + +definition instance_Basic_classes_Ord_Maybe_maybe_dict :: " 'a Ord_class \('a option)Ord_class " where + " instance_Basic_classes_Ord_Maybe_maybe_dict dict_Basic_classes_Ord_a = ((| + + compare_method = (maybeCompare + (compare_method dict_Basic_classes_Ord_a)), + + isLess_method = (\ m1 . (\ m2 . maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2 = LT)), + + isLessEqual_method = (\ m1 . (\ m2 . ((let r = (maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = LT) \ (r = EQ))))), + + isGreater_method = (\ m1 . (\ m2 . maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2 = GT)), + + isGreaterEqual_method = (\ m1 . (\ m2 . ((let r = (maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = GT) \ (r = EQ)))))|) )" + + +(* ----------------------- *) +(* maybe *) +(* ----------------------- *) + +(*val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b*) +(*let maybe d f mb= match mb with + | Just a -> f a + | Nothing -> d +end*) + +(* ----------------------- *) +(* isJust / isNothing *) +(* ----------------------- *) + +(*val isJust : forall 'a. maybe 'a -> bool*) +(*let isJust mb= match mb with + | Just _ -> true + | Nothing -> false +end*) + +(*val isNothing : forall 'a. maybe 'a -> bool*) +(*let isNothing mb= match mb with + | Just _ -> false + | Nothing -> true +end*) + +(* ----------------------- *) +(* fromMaybe *) +(* ----------------------- *) + +(*val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a*) +(*let fromMaybe d mb= match mb with + | Just v -> v + | Nothing -> d +end*) + +(* ----------------------- *) +(* map *) +(* ----------------------- *) + +(*val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b*) +(*let map f= maybe Nothing (fun v -> Just (f v))*) + + +(* ----------------------- *) +(* bind *) +(* ----------------------- *) + +(*val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b*) +(*let bind mb f= maybe Nothing f mb*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy b/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy new file mode 100644 index 00000000..0a57814c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy @@ -0,0 +1,24 @@ +chapter \Generated by Lem from maybe_extra.lem.\ + +theory "Lem_maybe_extra" + +imports + Main + "Lem_basic_classes" + "Lem_maybe" + "Lem_assert_extra" + +begin + + + +(*open import Basic_classes Maybe Assert_extra*) + +(* ----------------------- *) +(* fromJust *) +(* ----------------------- *) + +(*val fromJust : forall 'a. maybe 'a -> 'a*) +(*let fromJust op= match op with | Just v -> v | Nothing -> failwith fromJust of Nothing end*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_num.thy b/snapshots/isabelle/lib/lem/Lem_num.thy new file mode 100644 index 00000000..0d7a72ea --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_num.thy @@ -0,0 +1,1302 @@ +chapter \Generated by Lem from num.lem.\ + +theory "Lem_num" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "~~/src/HOL/Word/Word" + "Real" + "~~/src/HOL/NthRoot" + +begin + + + +(*open import Bool Basic_classes*) +(*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*) +(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*) +(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) + +(*class inline ( Numeral 'a ) + val fromNumeral : numeral -> 'a +end*) + +(* ========================================================================== *) +(* Syntactic type-classes for common operations *) +(* ========================================================================== *) + +(* Typeclasses can be used as a mean to overload constants like +, -, etc *) + +record 'a NumNegate_class= + + numNegate_method ::" 'a \ 'a " + + + +record 'a NumAbs_class= + + abs_method ::" 'a \ 'a " + + + +record 'a NumAdd_class= + + numAdd_method ::" 'a \ 'a \ 'a " + + + +record 'a NumMinus_class= + + numMinus_method ::" 'a \ 'a \ 'a " + + + +record 'a NumMult_class= + + numMult_method ::" 'a \ 'a \ 'a " + + + +record 'a NumPow_class= + + numPow_method ::" 'a \ nat \ 'a " + + + +record 'a NumDivision_class= + + numDivision_method ::" 'a \ 'a \ 'a " + + + +record 'a NumIntegerDivision_class= + + div_method ::" 'a \ 'a \ 'a " + + + + +record 'a NumRemainder_class= + + mod_method ::" 'a \ 'a \ 'a " + + + +record 'a NumSucc_class= + + succ_method ::" 'a \ 'a " + + + +record 'a NumPred_class= + + pred_method ::" 'a \ 'a " + + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* unbounded size natural numbers *) +(*type natural*) + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* bounded size integers with uncertain length *) + +(*type int*) + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(* unbounded size integers *) + +(*type integer*) + +(* ----------------------- *) +(* bint *) +(* ----------------------- *) + +(* TODO the bounded ints are only partially implemented, use with care. *) + +(* 32 bit integers *) +(*type int32*) + +(* 64 bit integers *) +(*type int64*) + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(* unbounded size and precision rational numbers *) + +(*type rational*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(* real numbers *) +(* Note that for OCaml, this is mapped to floats with 64 bits. *) + +(*type real*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* double *) +(* ----------------------- *) + +(* double precision floating point (64 bits) *) + +(*type float64*) (* ???: better type for this in HOL? *) + +(*type float32*) (* ???: better type for this in HOL? *) + + +(* ========================================================================== *) +(* Binding the standard operations for the number types *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(*val natFromNumeral : numeral -> nat*) + +(*val natEq : nat -> nat -> bool*) + +(*val natLess : nat -> nat -> bool*) +(*val natLessEqual : nat -> nat -> bool*) +(*val natGreater : nat -> nat -> bool*) +(*val natGreaterEqual : nat -> nat -> bool*) + +(*val natCompare : nat -> nat -> ordering*) + +definition instance_Basic_classes_Ord_nat_dict :: "(nat)Ord_class " where + " instance_Basic_classes_Ord_nat_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val natAdd : nat -> nat -> nat*) + +definition instance_Num_NumAdd_nat_dict :: "(nat)NumAdd_class " where + " instance_Num_NumAdd_nat_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val natMinus : nat -> nat -> nat*) + +definition instance_Num_NumMinus_nat_dict :: "(nat)NumMinus_class " where + " instance_Num_NumMinus_nat_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val natSucc : nat -> nat*) +(*let natSucc n= (Instance_Num_NumAdd_nat.+) n 1*) +definition instance_Num_NumSucc_nat_dict :: "(nat)NumSucc_class " where + " instance_Num_NumSucc_nat_dict = ((| + + succ_method = Suc |) )" + + +(*val natPred : nat -> nat*) +definition instance_Num_NumPred_nat_dict :: "(nat)NumPred_class " where + " instance_Num_NumPred_nat_dict = ((| + + pred_method = (\ n. n -( 1 :: nat))|) )" + + +(*val natMult : nat -> nat -> nat*) + +definition instance_Num_NumMult_nat_dict :: "(nat)NumMult_class " where + " instance_Num_NumMult_nat_dict = ((| + + numMult_method = (op*)|) )" + + +(*val natDiv : nat -> nat -> nat*) + +definition instance_Num_NumIntegerDivision_nat_dict :: "(nat)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_nat_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_nat_dict :: "(nat)NumDivision_class " where + " instance_Num_NumDivision_nat_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val natMod : nat -> nat -> nat*) + +definition instance_Num_NumRemainder_nat_dict :: "(nat)NumRemainder_class " where + " instance_Num_NumRemainder_nat_dict = ((| + + mod_method = (op mod)|) )" + + + +(*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*) +fun gen_pow_aux :: "('a \ 'a \ 'a)\ 'a \ 'a \ nat \ 'a " where + " gen_pow_aux (mul :: 'a \ 'a \ 'a) (a :: 'a) (b :: 'a) (e :: nat) = ( + (case e of + 0 => a (* cannot happen, call discipline guarentees e >= 1 *) + | (Suc 0) => mul a b + | ( (Suc(Suc e'))) => (let e'' = (e div( 2 :: nat)) in + (let a' = (if (e mod( 2 :: nat)) =( 0 :: nat) then a else mul a b) in + gen_pow_aux mul a' (mul b b) e'')) + ))" + + +definition gen_pow :: " 'a \('a \ 'a \ 'a)\ 'a \ nat \ 'a " where + " gen_pow (one :: 'a) (mul :: 'a \ 'a \ 'a) (b :: 'a) (e :: nat) = ( + if e <( 0 :: nat) then one else + if (e =( 0 :: nat)) then one else gen_pow_aux mul one b e )" + + +(*val natPow : nat -> nat -> nat*) + +definition instance_Num_NumPow_nat_dict :: "(nat)NumPow_class " where + " instance_Num_NumPow_nat_dict = ((| + + numPow_method = (op^)|) )" + + +(*val natMin : nat -> nat -> nat*) + +(*val natMax : nat -> nat -> nat*) + +definition instance_Basic_classes_OrdMaxMin_nat_dict :: "(nat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_nat_dict = ((| + + max_method = max, + + min_method = min |) )" + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(*val naturalFromNumeral : numeral -> natural*) + +(*val naturalEq : natural -> natural -> bool*) + +(*val naturalLess : natural -> natural -> bool*) +(*val naturalLessEqual : natural -> natural -> bool*) +(*val naturalGreater : natural -> natural -> bool*) +(*val naturalGreaterEqual : natural -> natural -> bool*) + +(*val naturalCompare : natural -> natural -> ordering*) + +definition instance_Basic_classes_Ord_Num_natural_dict :: "(nat)Ord_class " where + " instance_Basic_classes_Ord_Num_natural_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val naturalAdd : natural -> natural -> natural*) + +definition instance_Num_NumAdd_Num_natural_dict :: "(nat)NumAdd_class " where + " instance_Num_NumAdd_Num_natural_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val naturalMinus : natural -> natural -> natural*) + +definition instance_Num_NumMinus_Num_natural_dict :: "(nat)NumMinus_class " where + " instance_Num_NumMinus_Num_natural_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val naturalSucc : natural -> natural*) +(*let naturalSucc n= (Instance_Num_NumAdd_Num_natural.+) n 1*) +definition instance_Num_NumSucc_Num_natural_dict :: "(nat)NumSucc_class " where + " instance_Num_NumSucc_Num_natural_dict = ((| + + succ_method = Suc |) )" + + +(*val naturalPred : natural -> natural*) +definition instance_Num_NumPred_Num_natural_dict :: "(nat)NumPred_class " where + " instance_Num_NumPred_Num_natural_dict = ((| + + pred_method = (\ n. n -( 1 :: nat))|) )" + + +(*val naturalMult : natural -> natural -> natural*) + +definition instance_Num_NumMult_Num_natural_dict :: "(nat)NumMult_class " where + " instance_Num_NumMult_Num_natural_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val naturalPow : natural -> nat -> natural*) + +definition instance_Num_NumPow_Num_natural_dict :: "(nat)NumPow_class " where + " instance_Num_NumPow_Num_natural_dict = ((| + + numPow_method = (op^)|) )" + + +(*val naturalDiv : natural -> natural -> natural*) + +definition instance_Num_NumIntegerDivision_Num_natural_dict :: "(nat)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_natural_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_natural_dict :: "(nat)NumDivision_class " where + " instance_Num_NumDivision_Num_natural_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val naturalMod : natural -> natural -> natural*) + +definition instance_Num_NumRemainder_Num_natural_dict :: "(nat)NumRemainder_class " where + " instance_Num_NumRemainder_Num_natural_dict = ((| + + mod_method = (op mod)|) )" + + +(*val naturalMin : natural -> natural -> natural*) + +(*val naturalMax : natural -> natural -> natural*) + +definition instance_Basic_classes_OrdMaxMin_Num_natural_dict :: "(nat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_natural_dict = ((| + + max_method = max, + + min_method = min |) )" + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(*val intFromNumeral : numeral -> int*) + +(*val intEq : int -> int -> bool*) + +(*val intLess : int -> int -> bool*) +(*val intLessEqual : int -> int -> bool*) +(*val intGreater : int -> int -> bool*) +(*val intGreaterEqual : int -> int -> bool*) + +(*val intCompare : int -> int -> ordering*) + +definition instance_Basic_classes_Ord_Num_int_dict :: "(int)Ord_class " where + " instance_Basic_classes_Ord_Num_int_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val intNegate : int -> int*) + +definition instance_Num_NumNegate_Num_int_dict :: "(int)NumNegate_class " where + " instance_Num_NumNegate_Num_int_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val intAbs : int -> int*) (* TODO: check *) + +definition instance_Num_NumAbs_Num_int_dict :: "(int)NumAbs_class " where + " instance_Num_NumAbs_Num_int_dict = ((| + + abs_method = abs |) )" + + +(*val intAdd : int -> int -> int*) + +definition instance_Num_NumAdd_Num_int_dict :: "(int)NumAdd_class " where + " instance_Num_NumAdd_Num_int_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val intMinus : int -> int -> int*) + +definition instance_Num_NumMinus_Num_int_dict :: "(int)NumMinus_class " where + " instance_Num_NumMinus_Num_int_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val intSucc : int -> int*) +definition instance_Num_NumSucc_Num_int_dict :: "(int)NumSucc_class " where + " instance_Num_NumSucc_Num_int_dict = ((| + + succ_method = (\ n. n +( 1 :: int))|) )" + + +(*val intPred : int -> int*) +definition instance_Num_NumPred_Num_int_dict :: "(int)NumPred_class " where + " instance_Num_NumPred_Num_int_dict = ((| + + pred_method = (\ n. n -( 1 :: int))|) )" + + +(*val intMult : int -> int -> int*) + +definition instance_Num_NumMult_Num_int_dict :: "(int)NumMult_class " where + " instance_Num_NumMult_Num_int_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val intPow : int -> nat -> int*) + +definition instance_Num_NumPow_Num_int_dict :: "(int)NumPow_class " where + " instance_Num_NumPow_Num_int_dict = ((| + + numPow_method = (op^)|) )" + + +(*val intDiv : int -> int -> int*) + +definition instance_Num_NumIntegerDivision_Num_int_dict :: "(int)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int_dict :: "(int)NumDivision_class " where + " instance_Num_NumDivision_Num_int_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val intMod : int -> int -> int*) + +definition instance_Num_NumRemainder_Num_int_dict :: "(int)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int_dict = ((| + + mod_method = (op mod)|) )" + + +(*val intMin : int -> int -> int*) + +(*val intMax : int -> int -> int*) + +definition instance_Basic_classes_OrdMaxMin_Num_int_dict :: "(int)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int_dict = ((| + + max_method = max, + + min_method = min |) )" + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) +(*val int32FromNumeral : numeral -> int32*) + +(*val int32Eq : int32 -> int32 -> bool*) + +(*val int32Less : int32 -> int32 -> bool*) +(*val int32LessEqual : int32 -> int32 -> bool*) +(*val int32Greater : int32 -> int32 -> bool*) +(*val int32GreaterEqual : int32 -> int32 -> bool*) + +(*val int32Compare : int32 -> int32 -> ordering*) + +definition instance_Basic_classes_Ord_Num_int32_dict :: "( 32 word)Ord_class " where + " instance_Basic_classes_Ord_Num_int32_dict = ((| + + compare_method = (genericCompare word_sless (op=)), + + isLess_method = word_sless, + + isLessEqual_method = word_sle, + + isGreater_method = (\ x y. word_sless y x), + + isGreaterEqual_method = (\ x y. word_sle y x)|) )" + + +(*val int32Negate : int32 -> int32*) + +definition instance_Num_NumNegate_Num_int32_dict :: "( 32 word)NumNegate_class " where + " instance_Num_NumNegate_Num_int32_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val int32Abs : int32 -> int32*) +definition int32Abs :: " 32 word \ 32 word " where + " int32Abs i = ( (if word_sle(((word_of_int 0) :: 32 word)) i then i else - i))" + + +definition instance_Num_NumAbs_Num_int32_dict :: "( 32 word)NumAbs_class " where + " instance_Num_NumAbs_Num_int32_dict = ((| + + abs_method = int32Abs |) )" + + + +(*val int32Add : int32 -> int32 -> int32*) + +definition instance_Num_NumAdd_Num_int32_dict :: "( 32 word)NumAdd_class " where + " instance_Num_NumAdd_Num_int32_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val int32Minus : int32 -> int32 -> int32*) + +definition instance_Num_NumMinus_Num_int32_dict :: "( 32 word)NumMinus_class " where + " instance_Num_NumMinus_Num_int32_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val int32Succ : int32 -> int32*) + +definition instance_Num_NumSucc_Num_int32_dict :: "( 32 word)NumSucc_class " where + " instance_Num_NumSucc_Num_int32_dict = ((| + + succ_method = (\ n. n +((word_of_int 1) :: 32 word))|) )" + + +(*val int32Pred : int32 -> int32*) +definition instance_Num_NumPred_Num_int32_dict :: "( 32 word)NumPred_class " where + " instance_Num_NumPred_Num_int32_dict = ((| + + pred_method = (\ n. n -((word_of_int 1) :: 32 word))|) )" + + +(*val int32Mult : int32 -> int32 -> int32*) + +definition instance_Num_NumMult_Num_int32_dict :: "( 32 word)NumMult_class " where + " instance_Num_NumMult_Num_int32_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val int32Pow : int32 -> nat -> int32*) + +definition instance_Num_NumPow_Num_int32_dict :: "( 32 word)NumPow_class " where + " instance_Num_NumPow_Num_int32_dict = ((| + + numPow_method = (op^)|) )" + + +(*val int32Div : int32 -> int32 -> int32*) + +definition instance_Num_NumIntegerDivision_Num_int32_dict :: "( 32 word)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int32_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int32_dict :: "( 32 word)NumDivision_class " where + " instance_Num_NumDivision_Num_int32_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val int32Mod : int32 -> int32 -> int32*) + +definition instance_Num_NumRemainder_Num_int32_dict :: "( 32 word)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int32_dict = ((| + + mod_method = (op mod)|) )" + + +(*val int32Min : int32 -> int32 -> int32*) + +(*val int32Max : int32 -> int32 -> int32*) + +definition instance_Basic_classes_OrdMaxMin_Num_int32_dict :: "( 32 word)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int32_dict = ((| + + max_method = ((\ x y. if (word_sle y x) then x else y)), + + min_method = ((\ x y. if (word_sle x y) then x else y))|) )" + + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) +(*val int64FromNumeral : numeral -> int64*) + +(*val int64Eq : int64 -> int64 -> bool*) + +(*val int64Less : int64 -> int64 -> bool*) +(*val int64LessEqual : int64 -> int64 -> bool*) +(*val int64Greater : int64 -> int64 -> bool*) +(*val int64GreaterEqual : int64 -> int64 -> bool*) + +(*val int64Compare : int64 -> int64 -> ordering*) + +definition instance_Basic_classes_Ord_Num_int64_dict :: "( 64 word)Ord_class " where + " instance_Basic_classes_Ord_Num_int64_dict = ((| + + compare_method = (genericCompare word_sless (op=)), + + isLess_method = word_sless, + + isLessEqual_method = word_sle, + + isGreater_method = (\ x y. word_sless y x), + + isGreaterEqual_method = (\ x y. word_sle y x)|) )" + + +(*val int64Negate : int64 -> int64*) + +definition instance_Num_NumNegate_Num_int64_dict :: "( 64 word)NumNegate_class " where + " instance_Num_NumNegate_Num_int64_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val int64Abs : int64 -> int64*) +definition int64Abs :: " 64 word \ 64 word " where + " int64Abs i = ( (if word_sle(((word_of_int 0) :: 64 word)) i then i else - i))" + + +definition instance_Num_NumAbs_Num_int64_dict :: "( 64 word)NumAbs_class " where + " instance_Num_NumAbs_Num_int64_dict = ((| + + abs_method = int64Abs |) )" + + + +(*val int64Add : int64 -> int64 -> int64*) + +definition instance_Num_NumAdd_Num_int64_dict :: "( 64 word)NumAdd_class " where + " instance_Num_NumAdd_Num_int64_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val int64Minus : int64 -> int64 -> int64*) + +definition instance_Num_NumMinus_Num_int64_dict :: "( 64 word)NumMinus_class " where + " instance_Num_NumMinus_Num_int64_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val int64Succ : int64 -> int64*) + +definition instance_Num_NumSucc_Num_int64_dict :: "( 64 word)NumSucc_class " where + " instance_Num_NumSucc_Num_int64_dict = ((| + + succ_method = (\ n. n +((word_of_int 1) :: 64 word))|) )" + + +(*val int64Pred : int64 -> int64*) +definition instance_Num_NumPred_Num_int64_dict :: "( 64 word)NumPred_class " where + " instance_Num_NumPred_Num_int64_dict = ((| + + pred_method = (\ n. n -((word_of_int 1) :: 64 word))|) )" + + +(*val int64Mult : int64 -> int64 -> int64*) + +definition instance_Num_NumMult_Num_int64_dict :: "( 64 word)NumMult_class " where + " instance_Num_NumMult_Num_int64_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val int64Pow : int64 -> nat -> int64*) + +definition instance_Num_NumPow_Num_int64_dict :: "( 64 word)NumPow_class " where + " instance_Num_NumPow_Num_int64_dict = ((| + + numPow_method = (op^)|) )" + + +(*val int64Div : int64 -> int64 -> int64*) + +definition instance_Num_NumIntegerDivision_Num_int64_dict :: "( 64 word)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int64_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int64_dict :: "( 64 word)NumDivision_class " where + " instance_Num_NumDivision_Num_int64_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val int64Mod : int64 -> int64 -> int64*) + +definition instance_Num_NumRemainder_Num_int64_dict :: "( 64 word)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int64_dict = ((| + + mod_method = (op mod)|) )" + + +(*val int64Min : int64 -> int64 -> int64*) + +(*val int64Max : int64 -> int64 -> int64*) + +definition instance_Basic_classes_OrdMaxMin_Num_int64_dict :: "( 64 word)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int64_dict = ((| + + max_method = ((\ x y. if (word_sle y x) then x else y)), + + min_method = ((\ x y. if (word_sle x y) then x else y))|) )" + + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerFromNumeral : numeral -> integer*) + +(*val integerFromNat : nat -> integer*) (* TODO: check *) + +(*val integerEq : integer -> integer -> bool*) + +(*val integerLess : integer -> integer -> bool*) +(*val integerLessEqual : integer -> integer -> bool*) +(*val integerGreater : integer -> integer -> bool*) +(*val integerGreaterEqual : integer -> integer -> bool*) + +(*val integerCompare : integer -> integer -> ordering*) + +definition instance_Basic_classes_Ord_Num_integer_dict :: "(int)Ord_class " where + " instance_Basic_classes_Ord_Num_integer_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val integerNegate : integer -> integer*) + +definition instance_Num_NumNegate_Num_integer_dict :: "(int)NumNegate_class " where + " instance_Num_NumNegate_Num_integer_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val integerAbs : integer -> integer*) (* TODO: check *) + +definition instance_Num_NumAbs_Num_integer_dict :: "(int)NumAbs_class " where + " instance_Num_NumAbs_Num_integer_dict = ((| + + abs_method = abs |) )" + + +(*val integerAdd : integer -> integer -> integer*) + +definition instance_Num_NumAdd_Num_integer_dict :: "(int)NumAdd_class " where + " instance_Num_NumAdd_Num_integer_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val integerMinus : integer -> integer -> integer*) + +definition instance_Num_NumMinus_Num_integer_dict :: "(int)NumMinus_class " where + " instance_Num_NumMinus_Num_integer_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val integerSucc : integer -> integer*) +definition instance_Num_NumSucc_Num_integer_dict :: "(int)NumSucc_class " where + " instance_Num_NumSucc_Num_integer_dict = ((| + + succ_method = (\ n. n +( 1 :: int))|) )" + + +(*val integerPred : integer -> integer*) +definition instance_Num_NumPred_Num_integer_dict :: "(int)NumPred_class " where + " instance_Num_NumPred_Num_integer_dict = ((| + + pred_method = (\ n. n -( 1 :: int))|) )" + + +(*val integerMult : integer -> integer -> integer*) + +definition instance_Num_NumMult_Num_integer_dict :: "(int)NumMult_class " where + " instance_Num_NumMult_Num_integer_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val integerPow : integer -> nat -> integer*) + +definition instance_Num_NumPow_Num_integer_dict :: "(int)NumPow_class " where + " instance_Num_NumPow_Num_integer_dict = ((| + + numPow_method = (op^)|) )" + + +(*val integerDiv : integer -> integer -> integer*) + +definition instance_Num_NumIntegerDivision_Num_integer_dict :: "(int)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_integer_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_integer_dict :: "(int)NumDivision_class " where + " instance_Num_NumDivision_Num_integer_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val integerMod : integer -> integer -> integer*) + +definition instance_Num_NumRemainder_Num_integer_dict :: "(int)NumRemainder_class " where + " instance_Num_NumRemainder_Num_integer_dict = ((| + + mod_method = (op mod)|) )" + + +(*val integerMin : integer -> integer -> integer*) + +(*val integerMax : integer -> integer -> integer*) + +definition instance_Basic_classes_OrdMaxMin_Num_integer_dict :: "(int)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_integer_dict = ((| + + max_method = max, + + min_method = min |) )" + + + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(*val rationalFromNumeral : numeral -> rational*) + +(*val rationalFromInt : int -> rational*) + +(*val rationalEq : rational -> rational -> bool*) + +(*val rationalLess : rational -> rational -> bool*) +(*val rationalLessEqual : rational -> rational -> bool*) +(*val rationalGreater : rational -> rational -> bool*) +(*val rationalGreaterEqual : rational -> rational -> bool*) + +(*val rationalCompare : rational -> rational -> ordering*) + +definition instance_Basic_classes_Ord_Num_rational_dict :: "(rat)Ord_class " where + " instance_Basic_classes_Ord_Num_rational_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val rationalAdd : rational -> rational -> rational*) + +definition instance_Num_NumAdd_Num_rational_dict :: "(rat)NumAdd_class " where + " instance_Num_NumAdd_Num_rational_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val rationalMinus : rational -> rational -> rational*) + +definition instance_Num_NumMinus_Num_rational_dict :: "(rat)NumMinus_class " where + " instance_Num_NumMinus_Num_rational_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val rationalNegate : rational -> rational*) + +definition instance_Num_NumNegate_Num_rational_dict :: "(rat)NumNegate_class " where + " instance_Num_NumNegate_Num_rational_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val rationalAbs : rational -> rational*) + +definition instance_Num_NumAbs_Num_rational_dict :: "(rat)NumAbs_class " where + " instance_Num_NumAbs_Num_rational_dict = ((| + + abs_method = abs |) )" + + +(*val rationalSucc : rational -> rational*) +definition instance_Num_NumSucc_Num_rational_dict :: "(rat)NumSucc_class " where + " instance_Num_NumSucc_Num_rational_dict = ((| + + succ_method = (\ n. n +(Fract ( 1 :: int) (1 :: int)))|) )" + + +(*val rationalPred : rational -> rational*) +definition instance_Num_NumPred_Num_rational_dict :: "(rat)NumPred_class " where + " instance_Num_NumPred_Num_rational_dict = ((| + + pred_method = (\ n. n -(Fract ( 1 :: int) (1 :: int)))|) )" + + +(*val rationalMult : rational -> rational -> rational*) + +definition instance_Num_NumMult_Num_rational_dict :: "(rat)NumMult_class " where + " instance_Num_NumMult_Num_rational_dict = ((| + + numMult_method = (op*)|) )" + + +(*val rationalDiv : rational -> rational -> rational*) + +definition instance_Num_NumDivision_Num_rational_dict :: "(rat)NumDivision_class " where + " instance_Num_NumDivision_Num_rational_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val rationalFromFrac : int -> int -> rational*) +(*let rationalFromFrac n d= (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)*) + +(*val rationalPowInteger : rational -> integer -> rational*) +fun rationalPowInteger :: " rat \ int \ rat " where + " rationalPowInteger b e = ( + if e =( 0 :: int) then(Fract ( 1 :: int) (1 :: int)) else + if e >( 0 :: int) then rationalPowInteger b (e -( 1 :: int)) * b else + rationalPowInteger b (e +( 1 :: int)) div b )" + + +(*val rationalPowNat : rational -> nat -> rational*) +(*let rationalPowNat r e= rationalPowInteger r (integerFromNat e)*) + +definition instance_Num_NumPow_Num_rational_dict :: "(rat)NumPow_class " where + " instance_Num_NumPow_Num_rational_dict = ((| + + numPow_method = power |) )" + + +(*val rationalMin : rational -> rational -> rational*) + +(*val rationalMax : rational -> rational -> rational*) + +definition instance_Basic_classes_OrdMaxMin_Num_rational_dict :: "(rat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_rational_dict = ((| + + max_method = max, + + min_method = min |) )" + + + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(*val realFromNumeral : numeral -> real*) + +(*val realFromInteger : integer -> real*) + +(*val realEq : real -> real -> bool*) + +(*val realLess : real -> real -> bool*) +(*val realLessEqual : real -> real -> bool*) +(*val realGreater : real -> real -> bool*) +(*val realGreaterEqual : real -> real -> bool*) + +(*val realCompare : real -> real -> ordering*) + +definition instance_Basic_classes_Ord_Num_real_dict :: "(real)Ord_class " where + " instance_Basic_classes_Ord_Num_real_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \)|) )" + + +(*val realAdd : real -> real -> real*) + +definition instance_Num_NumAdd_Num_real_dict :: "(real)NumAdd_class " where + " instance_Num_NumAdd_Num_real_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val realMinus : real -> real -> real*) + +definition instance_Num_NumMinus_Num_real_dict :: "(real)NumMinus_class " where + " instance_Num_NumMinus_Num_real_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val realNegate : real -> real*) + +definition instance_Num_NumNegate_Num_real_dict :: "(real)NumNegate_class " where + " instance_Num_NumNegate_Num_real_dict = ((| + + numNegate_method = (\ i. - i)|) )" + + +(*val realAbs : real -> real*) + +definition instance_Num_NumAbs_Num_real_dict :: "(real)NumAbs_class " where + " instance_Num_NumAbs_Num_real_dict = ((| + + abs_method = abs |) )" + + +(*val realSucc : real -> real*) +definition instance_Num_NumSucc_Num_real_dict :: "(real)NumSucc_class " where + " instance_Num_NumSucc_Num_real_dict = ((| + + succ_method = (\ n. n +( 1 :: real))|) )" + + +(*val realPred : real -> real*) +definition instance_Num_NumPred_Num_real_dict :: "(real)NumPred_class " where + " instance_Num_NumPred_Num_real_dict = ((| + + pred_method = (\ n. n -( 1 :: real))|) )" + + +(*val realMult : real -> real -> real*) + +definition instance_Num_NumMult_Num_real_dict :: "(real)NumMult_class " where + " instance_Num_NumMult_Num_real_dict = ((| + + numMult_method = (op*)|) )" + + +(*val realDiv : real -> real -> real*) + +definition instance_Num_NumDivision_Num_real_dict :: "(real)NumDivision_class " where + " instance_Num_NumDivision_Num_real_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val realFromFrac : integer -> integer -> real*) +definition realFromFrac :: " int \ int \ real " where + " realFromFrac n d = ( ((real_of_int n)) div ((real_of_int d)))" + + +(*val realPowInteger : real -> integer -> real*) +fun realPowInteger :: " real \ int \ real " where + " realPowInteger b e = ( + if e =( 0 :: int) then( 1 :: real) else + if e >( 0 :: int) then realPowInteger b (e -( 1 :: int)) * b else + realPowInteger b (e +( 1 :: int)) div b )" + + +(*val realPowNat : real -> nat -> real*) +(*let realPowNat r e= realPowInteger r (integerFromNat e)*) + +definition instance_Num_NumPow_Num_real_dict :: "(real)NumPow_class " where + " instance_Num_NumPow_Num_real_dict = ((| + + numPow_method = power |) )" + + +(*val realSqrt : real -> real*) + +(*val realMin : real -> real -> real*) + +(*val realMax : real -> real -> real*) + +definition instance_Basic_classes_OrdMaxMin_Num_real_dict :: "(real)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_real_dict = ((| + + max_method = max, + + min_method = min |) )" + + +(*val realCeiling : real -> integer*) + +(*val realFloor : real -> integer*) + +(* ========================================================================== *) +(* Translation between number types *) +(* ========================================================================== *) + +(******************) +(* integerFrom... *) +(******************) + +(*val integerFromInt : int -> integer*) + +(*val integerFromNatural : natural -> integer*) + + +(*val integerFromInt32 : int32 -> integer*) + + +(*val integerFromInt64 : int64 -> integer*) + + +(******************) +(* naturalFrom... *) +(******************) + +(*val naturalFromNat : nat -> natural*) + +(*val naturalFromInteger : integer -> natural*) + + +(******************) +(* intFrom ... *) +(******************) + +(*val intFromInteger : integer -> int*) + +(*val intFromNat : nat -> int*) + + +(******************) +(* natFrom ... *) +(******************) + +(*val natFromNatural : natural -> nat*) + +(*val natFromInt : int -> nat*) + + +(******************) +(* int32From ... *) +(******************) + +(*val int32FromNat : nat -> int32*) + +(*val int32FromNatural : natural -> int32*) + +(*val int32FromInteger : integer -> int32*) +(*let int32FromInteger i= ( + let abs_int32 = int32FromNatural (naturalFromInteger i) in + if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int32.~ abs_int32) else abs_int32 +)*) + +(*val int32FromInt : int -> int32*) +(*let int32FromInt i= int32FromInteger (integerFromInt i)*) + + +(*val int32FromInt64 : int64 -> int32*) +(*let int32FromInt64 i= int32FromInteger (integerFromInt64 i)*) + + + + +(******************) +(* int64From ... *) +(******************) + +(*val int64FromNat : nat -> int64*) + +(*val int64FromNatural : natural -> int64*) + +(*val int64FromInteger : integer -> int64*) +(*let int64FromInteger i= ( + let abs_int64 = int64FromNatural (naturalFromInteger i) in + if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int64.~ abs_int64) else abs_int64 +)*) + +(*val int64FromInt : int -> int64*) +(*let int64FromInt i= int64FromInteger (integerFromInt i)*) + + +(*val int64FromInt32 : int32 -> int64*) +(*let int64FromInt32 i= int64FromInteger (integerFromInt32 i)*) + + +(******************) +(* what's missing *) +(******************) + +(*val naturalFromInt : int -> natural*) +(*val naturalFromInt32 : int32 -> natural*) +(*val naturalFromInt64 : int64 -> natural*) + + +(*val intFromNatural : natural -> int*) +(*val intFromInt32 : int32 -> int*) +(*val intFromInt64 : int64 -> int*) + +(*val natFromInteger : integer -> nat*) +(*val natFromInt32 : int32 -> nat*) +(*val natFromInt64 : int64 -> nat*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_num_extra.thy b/snapshots/isabelle/lib/lem/Lem_num_extra.thy new file mode 100644 index 00000000..0611862e --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_num_extra.thy @@ -0,0 +1,34 @@ +chapter \Generated by Lem from num_extra.lem.\ + +theory "Lem_num_extra" + +imports + Main + "Lem_num" + "Lem_string" + +begin + +(* **************************************************** *) +(* *) +(* A library of additional functions on numbers *) +(* *) +(* **************************************************** *) + +(*open import Num*) +(*open import String*) + +(*val naturalOfString : string -> natural*) + +(*val integerOfString : string -> integer*) + + +(* Truncation integer division (round toward zero) *) +(*val integerDiv_t: integer -> integer -> integer*) + +(* Truncation modulo *) +(*val integerRem_t: integer -> integer -> integer*) + +(* Flooring modulo *) +(*val integerRem_f: integer -> integer -> integer*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_pervasives.thy b/snapshots/isabelle/lib/lem/Lem_pervasives.thy new file mode 100644 index 00000000..37da1224 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_pervasives.thy @@ -0,0 +1,31 @@ +chapter \Generated by Lem from pervasives.lem.\ + +theory "Lem_pervasives" + +imports + Main + "Lem_basic_classes" + "Lem_bool" + "Lem_tuple" + "Lem_maybe" + "Lem_either" + "Lem_function" + "Lem_num" + "Lem_map" + "Lem_set" + "Lem_list" + "Lem_string" + "Lem_word" + "Lem_show" + "Lem_sorting" + "Lem_relation" + +begin + + + +(*include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show*) + +(*import Sorting Relation*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy b/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy new file mode 100644 index 00000000..0e3e5a88 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy @@ -0,0 +1,26 @@ +chapter \Generated by Lem from pervasives_extra.lem.\ + +theory "Lem_pervasives_extra" + +imports + Main + "Lem_pervasives" + "Lem_function_extra" + "Lem_maybe_extra" + "Lem_map_extra" + "Lem_num_extra" + "Lem_set_extra" + "Lem_set_helpers" + "Lem_list_extra" + "Lem_string_extra" + "Lem_assert_extra" + "Lem_show_extra" + "Lem_machine_word" + +begin + + + +(*include import Pervasives*) +(*include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_relation.thy b/snapshots/isabelle/lib/lem/Lem_relation.thy new file mode 100644 index 00000000..23e7d707 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_relation.thy @@ -0,0 +1,449 @@ +chapter \Generated by Lem from relation.lem.\ + +theory "Lem_relation" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_tuple" + "Lem_set" + "Lem_num" + +begin + + + +(*open import Bool Basic_classes Tuple Set Num*) +(*open import {hol} `set_relationTheory`*) + +(* ========================================================================== *) +(* The type of relations *) +(* ========================================================================== *) + +type_synonym( 'a, 'b) rel_pred =" 'a \ 'b \ bool " +type_synonym( 'a, 'b) rel_set =" ('a * 'b) set " + +(* Binary relations are usually represented as either + sets of pairs (rel_set) or as curried functions (rel_pred). + + The choice depends on taste and the backend. Lem should not take a + decision, but supports both representations. There is an abstract type + pred, which can be converted to both representations. The representation + of pred itself then depends on the backend. However, for the time beeing, + let's implement relations as sets to get them working more quickly. *) + +type_synonym( 'a, 'b) rel =" ('a, 'b) rel_set " + +(*val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b*) +(*val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b*) + +(*val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool*) +definition relEq :: "('a*'b)set \('a*'b)set \ bool " where + " relEq r1 r2 = ( (r1 = r2))" + + +(*val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b*) +(*val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b*) + +definition relToPred :: "('a*'b)set \ 'a \ 'b \ bool " where + " relToPred r = ( (\ x y . (x, y) \ r))" + +definition relFromPred :: " 'a set \ 'b set \('a \ 'b \ bool)\('a*'b)set " where + " relFromPred xs ys p = ( set_filter ( \x . + (case x of (x,y) => p x y )) (xs \ ys))" + + + +(* ========================================================================== *) +(* Basic Operations *) +(* ========================================================================== *) + +(* ----------------------- *) +(* membership test *) +(* ----------------------- *) + +(*val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool*) + + +(* ----------------------- *) +(* empty relation *) +(* ----------------------- *) + +(*val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b*) + +(* ----------------------- *) +(* Insertion *) +(* ----------------------- *) + +(*val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b*) + + +(* ----------------------- *) +(* Identity relation *) +(* ----------------------- *) + +(*val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a*) +definition relIdOn :: " 'a set \('a*'a)set " where + " relIdOn s = ( relFromPred s s (op=))" + + +(*val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a*) + +(* ----------------------- *) +(* relation union *) +(* ----------------------- *) + +(*val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* relation intersection *) +(* ----------------------- *) + +(*val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* Relation Composition *) +(* ----------------------- *) + +(*val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c*) +(*let relComp r1 r2= relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}*) + +(* ----------------------- *) +(* restrict *) +(* ----------------------- *) + +(*val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +definition relRestrict :: "('a*'a)set \ 'a set \('a*'a)set " where + " relRestrict r s = ( ((let x2 = + ({}) in Finite_Set.fold + (\a x2 . Finite_Set.fold + (\b x2 . + if (a, b) \ r then Set.insert (a, b) x2 else x2) + x2 s) x2 s)))" + + + +(* ----------------------- *) +(* Converse *) +(* ----------------------- *) + +(*val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a*) +(*let relConverse r= relFromSet (Set.map swap (relToSet r))*) + + +(* ----------------------- *) +(* domain *) +(* ----------------------- *) + +(*val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a*) +(*let relDomain r= Set.map (fun x -> fst x) (relToSet r)*) + +(* ----------------------- *) +(* range *) +(* ----------------------- *) + +(*val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b*) +(*let relRange r= Set.map (fun x -> snd x) (relToSet r)*) + + +(* ----------------------- *) +(* field / definedOn *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a*) + +(* ----------------------- *) +(* relOver *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool*) +definition relOver :: "('a*'a)set \ 'a set \ bool " where + " relOver r s = ( ((((Domain r) \ (Range r))) \ s))" + + + +(* ----------------------- *) +(* apply a relation *) +(* ----------------------- *) + +(* Given a relation r and a set s, relApply r s applies s to r, i.e. + it returns the set of all value reachable via r from a value in s. + This operation can be seen as a generalisation of function application. *) + +(*val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b*) +(*let relApply r s= { y | forall ((x, y) IN (relToSet r)) | x IN s }*) + + +(* ========================================================================== *) +(* Properties *) +(* ========================================================================== *) + +(* ----------------------- *) +(* subrel *) +(* ----------------------- *) + +(*val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool*) + +(* ----------------------- *) +(* reflexivity *) +(* ----------------------- *) + +(*val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isReflexiveOn :: "('a*'a)set \ 'a set \ bool " where + " isReflexiveOn r s = ( ((\ e \ s. (e, e) \ r)))" + + +(*val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let ~{ocaml;coq} isReflexive r= (forall e. inRel e e r)*) + + +(* ----------------------- *) +(* irreflexivity *) +(* ----------------------- *) + +(*val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isIrreflexiveOn :: "('a*'a)set \ 'a set \ bool " where + " isIrreflexiveOn r s = ( ((\ e \ s. \ ((e, e) \ r))))" + + +(*val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isIrreflexive r= (forall ((e1, e2) IN (relToSet r)). not (e1 = e2))*) + + +(* ----------------------- *) +(* symmetry *) +(* ----------------------- *) + +(*val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isSymmetricOn :: "('a*'a)set \ 'a set \ bool " where + " isSymmetricOn r s = ( ((\ e1 \ s. \ e2 \ s. ((e1, e2) \ r) \ ((e2, e1) \ r))))" + + +(*val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isSymmetric r= (forall ((e1, e2) IN relToSet r). inRel e2 e1 r)*) + + +(* ----------------------- *) +(* antisymmetry *) +(* ----------------------- *) + +(*val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isAntisymmetricOn :: "('a*'a)set \ 'a set \ bool " where + " isAntisymmetricOn r s = ( ((\ e1 \ s. \ e2 \ s. ((e1, e2) \ r) \ (((e2, e1) \ r) \ (e1 = e2)))))" + + +(*val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isAntisymmetric r= (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))*) + + +(* ----------------------- *) +(* transitivity *) +(* ----------------------- *) + +(*val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTransitiveOn :: "('a*'a)set \ 'a set \ bool " where + " isTransitiveOn r s = ( ((\ e1 \ s. \ e2 \ s. \ e3 \ s. ((e1, e2) \ r) \ (((e2, e3) \ r) \ ((e1, e3) \ r)))))" + + +(*val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isTransitive r= (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)*) + +(* ----------------------- *) +(* total *) +(* ----------------------- *) + +(*val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTotalOn :: "('a*'a)set \ 'a set \ bool " where + " isTotalOn r s = ( ((\ e1 \ s. \ e2 \ s. ((e1, e2) \ r) \ ((e2, e1) \ r))))" + + + +(*val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let ~{ocaml;coq} isTotal r= (forall e1 e2. (inRel e1 e2 r) || (inRel e2 e1 r))*) + +(*val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTrichotomousOn :: "('a*'a)set \ 'a set \ bool " where + " isTrichotomousOn r s = ( ((\ e1 \ s. \ e2 \ s. ((e1, e2) \ r) \ ((e1 = e2) \ ((e2, e1) \ r)))))" + + +(*val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isTrichotomous :: "('a*'a)set \ bool " where + " isTrichotomous r = ( ((\ e1. \ e2. ((e1, e2) \ r) \ ((e1 = e2) \ ((e2, e1) \ r)))))" + + + +(* ----------------------- *) +(* is_single_valued *) +(* ----------------------- *) + +(*val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool*) +definition isSingleValued :: "('a*'b)set \ bool " where + " isSingleValued r = ( ((\ (e1, e2a) \ r. \ e2b \ Image r {e1}. e2a = e2b)))" + + + +(* ----------------------- *) +(* equivalence relation *) +(* ----------------------- *) + +(*val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isEquivalenceOn :: "('a*'a)set \ 'a set \ bool " where + " isEquivalenceOn r s = ( isReflexiveOn r s \ (isSymmetricOn r s \ isTransitiveOn r s))" + + + +(*val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isEquivalence :: "('a*'a)set \ bool " where + " isEquivalence r = ( refl r \ (sym r \ trans r))" + + + +(* ----------------------- *) +(* well founded *) +(* ----------------------- *) + +(*val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isWellFounded :: "('a*'a)set \ bool " where + " isWellFounded r = ( ((\ P. ((\ x. ((\ y. ((y, x) \ r) \ P x)) \ P x)) \ ((\ x. P x)))))" + + + +(* ========================================================================== *) +(* Orders *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* pre- or quasiorders *) +(* ----------------------- *) + +(*val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isPreorderOn :: "('a*'a)set \ 'a set \ bool " where + " isPreorderOn r s = ( isReflexiveOn r s \ isTransitiveOn r s )" + + +(*val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isPreorder :: "('a*'a)set \ bool " where + " isPreorder r = ( refl r \ trans r )" + + + +(* ----------------------- *) +(* partial orders *) +(* ----------------------- *) + +(*val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isPartialOrderOn :: "('a*'a)set \ 'a set \ bool " where + " isPartialOrderOn r s = ( isReflexiveOn r s \ (isTransitiveOn r s \ isAntisymmetricOn r s))" + + + +(*val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isStrictPartialOrderOn :: "('a*'a)set \ 'a set \ bool " where + " isStrictPartialOrderOn r s = ( isIrreflexiveOn r s \ isTransitiveOn r s )" + + + +(*val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isStrictPartialOrder :: "('a*'a)set \ bool " where + " isStrictPartialOrder r = ( irrefl r \ trans r )" + + +(*val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isPartialOrder :: "('a*'a)set \ bool " where + " isPartialOrder r = ( refl r \ (trans r \ antisym r))" + + +(* ----------------------- *) +(* total / linear orders *) +(* ----------------------- *) + +(*val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTotalOrderOn :: "('a*'a)set \ 'a set \ bool " where + " isTotalOrderOn r s = ( isPartialOrderOn r s \ isTotalOn r s )" + + +(*val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isStrictTotalOrderOn :: "('a*'a)set \ 'a set \ bool " where + " isStrictTotalOrderOn r s = ( isStrictPartialOrderOn r s \ isTrichotomousOn r s )" + + +(*val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isTotalOrder :: "('a*'a)set \ bool " where + " isTotalOrder r = ( isPartialOrder r \ total r )" + + +(*val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isStrictTotalOrder :: "('a*'a)set \ bool " where + " isStrictTotalOrder r = ( isStrictPartialOrder r \ isTrichotomous r )" + + + + +(* ========================================================================== *) +(* closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* transitive closure *) +(* ----------------------- *) + +(*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> ordering) -> rel 'a 'a -> rel 'a 'a*) + + +(* ----------------------- *) +(* transitive closure step *) +(* ----------------------- *) + +(*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*) + +definition transitiveClosureAdd :: " 'a \ 'a \('a*'a)set \('a*'a)set " where + " transitiveClosureAdd x y r = ( + (((((Set.insert (x,y) (r)))) \ ((((((let x2 = + ({}) in Finite_Set.fold + (\z x2 . if (y, z) \ r then Set.insert (x, z) x2 else x2) + x2 (Range r)))) \ (((let x2 = + ({}) in Finite_Set.fold + (\z x2 . if (z, x) \ r then Set.insert (z, y) x2 else x2) + x2 (Domain r))))))))))" + + + +(* ========================================================================== *) +(* reflexive closure *) +(* ========================================================================== *) + +(*val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +definition reflexiveTransitiveClosureOn :: "('a*'a)set \ 'a set \('a*'a)set " where + " reflexiveTransitiveClosureOn r s = ( trancl (((r) \ ((relIdOn s)))))" + + + +(*val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +definition reflexiveTransitiveClosure :: "('a*'a)set \('a*'a)set " where + " reflexiveTransitiveClosure r = ( trancl (((r) \ (Id))))" + + + + +(* ========================================================================== *) +(* inverse of closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* without transitve edges *) +(* ----------------------- *) + +(*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +(*let withoutTransitiveEdges r= + let tc = transitiveClosure r in + {(a, c) | forall ((a, c) IN r) + | forall (b IN relRange r). a <> b && b <> c --> not ((a, b) IN tc && (b, c) IN tc)}*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_set.thy b/snapshots/isabelle/lib/lem/Lem_set.thy new file mode 100644 index 00000000..f77d4d98 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set.thy @@ -0,0 +1,325 @@ +chapter \Generated by Lem from set.lem.\ + +theory "Lem_set" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + "Lem_list" + "Lem_set_helpers" + "Lem" + +begin + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets. + OCaml and Haskell both represent sets by some kind of balancing trees. This means + that sets are finite and an order on the element type is required. + Such sets are constructed by simple, executable operations like inserting or + deleting elements, union, intersection, filtering etc. + + On the other hand, we want to use sets for specifications. This leads often + infinite sets, which are specificied in complicated, perhaps even undecidable + ways. + + The set library in this file, chooses the first approach. It describes + *finite* sets with an underlying order. Infinite sets should in the medium + run be represented by a separate type. Since this would require some significant + changes to Lem, for the moment also infinite sets are represented using this + class. However, a run-time exception might occour when using these sets. + This problem needs adressing in the future. *) + + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Set_helpers*) + +(* DPM: sets currently implemented as lists due to mismatch between Coq type + * class hierarchy and the hierarchy implemented in Lem. + *) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* Equality check *) +(* ----------------------- *) + +(*val setEqualBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) + +(*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* Empty set *) +(* ----------------------- *) + +(*val empty : forall 'a. SetType 'a => set 'a*) +(*val emptyBy : forall 'a. ('a -> 'a -> ordering) -> set 'a*) + +(* ----------------------- *) +(* any / all *) +(* ----------------------- *) + +(*val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + +(*val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + + +(* ----------------------- *) +(* (IN) *) +(* ----------------------- *) + +(*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) +(*val memberBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* not (IN) *) +(* ----------------------- *) + +(*val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) + + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ------------------------ *) +(* singleton *) +(* ------------------------ *) + +(*val singletonBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a*) +(*val singleton : forall 'a. SetType 'a => 'a -> set 'a*) + + +(* ----------------------- *) +(* size *) +(* ----------------------- *) + +(*val size : forall 'a. SetType 'a => set 'a -> nat*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b*) + + +(* ------------------------ *) +(* union *) +(* ------------------------ *) + +(*val unionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) +(*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* insert *) +(* ----------------------- *) + +(*val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* filter *) +(* ----------------------- *) + +(*val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a*) +(*let filter P s= {e | forall (e IN s) | P e}*) + + +(* ----------------------- *) +(* partition *) +(* ----------------------- *) + +(*val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a*) +definition partition :: "('a \ bool)\ 'a set \ 'a set*'a set " where + " partition P s = ( (set_filter P s, set_filter (\ e . \ (P e)) s))" + + + +(* ----------------------- *) +(* split *) +(* ----------------------- *) + +(*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*) +definition split :: " 'a Ord_class \ 'a \ 'a set \ 'a set*'a set " where + " split dict_Basic_classes_Ord_a p s = ( (set_filter ( + (isGreater_method dict_Basic_classes_Ord_a) p) s, set_filter ((isLess_method dict_Basic_classes_Ord_a) p) s))" + + +(*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*) +definition splitMember :: " 'a Ord_class \ 'a \ 'a set \ 'a set*bool*'a set " where + " splitMember dict_Basic_classes_Ord_a p s = ( (set_filter ( + (isLess_method dict_Basic_classes_Ord_a) p) s, (p \ s), set_filter ( + (isGreater_method dict_Basic_classes_Ord_a) p) s))" + + +(* ------------------------ *) +(* subset and proper subset *) +(* ------------------------ *) + +(*val isSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) +(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) + +(*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) +(*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + + +(* ------------------------ *) +(* delete *) +(* ------------------------ *) + +(*val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a*) +(*val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* bigunion *) +(* ------------------------ *) + +(*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +(*val bigunionBy : forall 'a. ('a -> 'a -> ordering) -> set (set 'a) -> set 'a*) + +(*let bigunion bs= {x | forall (s IN bs) (x IN s) | true}*) + +(* ------------------------ *) +(* big intersection *) +(* ------------------------ *) + +(* Shaked's addition, for which he is now forever responsible as a de facto + * Lem maintainer... + *) +(*val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +definition bigintersection :: "('a set)set \ 'a set " where + " bigintersection bs = ( (let x2 = + ({}) in Finite_Set.fold + (\x x2 . + if( \ s \ bs. x \ s) then Set.insert x x2 else x2) + x2 (\ bs)))" + + +(* ------------------------ *) +(* difference *) +(* ------------------------ *) + +(*val differenceBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) +(*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ------------------------ *) +(* intersection *) +(* ------------------------ *) + +(*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) +(*val intersectionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* map *) +(* ------------------------ *) + +(*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *) +(*let map f s= { f e | forall (e IN s) | true }*) + +(*val mapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> 'b) -> set 'a -> set 'b*) + + +(* ------------------------ *) +(* bigunionMap *) +(* ------------------------ *) + +(* In order to avoid providing an comparison function for sets of sets, + it might be better to combine bigunion and map sometimes into a single operation. *) + +(*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*) +(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> set 'b) -> set 'a -> set 'b*) + +(* ------------------------ *) +(* mapMaybe and fromMaybe *) +(* ------------------------ *) + +(* If the mapping function returns Just x, x is added to the result + set. If it returns Nothing, no element is added. *) + +(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> maybe 'b) -> set 'a -> set 'b*) +definition setMapMaybe :: "('a \ 'b option)\ 'a set \ 'b set " where + " setMapMaybe f s = ( + \ (Set.image (\ x . (case f x of + Some y => {y} + | None => {} + )) s))" + + +(*val removeMaybe : forall 'a. SetType 'a => set (maybe 'a) -> set 'a*) +definition removeMaybe :: "('a option)set \ 'a set " where + " removeMaybe s = ( setMapMaybe (\ x . x) s )" + + +(* ------------------------ *) +(* min and max *) +(* ------------------------ *) + +(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) +(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) + +(* ------------------------ *) +(* fromList *) +(* ------------------------ *) + +(*val fromList : forall 'a. SetType 'a => list 'a -> set 'a*) (* before from_list *) +(*val fromListBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> set 'a*) + + +(* ------------------------ *) +(* Sigma *) +(* ------------------------ *) + +(*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*) +(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*) + +(*let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }*) + + +(* ------------------------ *) +(* cross product *) +(* ------------------------ *) + +(*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*) +(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> set 'b -> set ('a * 'b)*) + +(*let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*) + + +(* ------------------------ *) +(* finite *) +(* ------------------------ *) + +(*val finite : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ----------------------------*) +(* fixed point *) +(* --------------------------- *) + +(*val leastFixedPoint : forall 'a. SetType 'a + => nat -> (set 'a -> set 'a) -> set 'a -> set 'a*) +fun leastFixedPoint :: " nat \('a set \ 'a set)\ 'a set \ 'a set " where + " leastFixedPoint 0 f x = ( x )" +|" leastFixedPoint ((Suc bound')) f x = ( (let fx = (f x) in + if fx \ x then x + else leastFixedPoint bound' f (fx \ x)))" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_set_extra.thy b/snapshots/isabelle/lib/lem/Lem_set_extra.thy new file mode 100644 index 00000000..33516be7 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set_extra.thy @@ -0,0 +1,121 @@ +chapter \Generated by Lem from set_extra.lem.\ + +theory "Lem_set_extra" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + "Lem_list" + "Lem_sorting" + "Lem_set" + +begin + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Sorting Set*) + + +(* ----------------------------*) +(* set choose (be careful !) *) +(* --------------------------- *) + +(*val choose : forall 'a. SetType 'a => set 'a -> 'a*) + +(* ------------------------ *) +(* chooseAndSplit *) +(* ------------------------ *) +(* The idea here is to provide a simple primitive that Lem code can use + * to perform its own custom searches within the set -- likely using a + * search criterion related to the element ordering, but not necessarily). + * For example, sometimes we don't necessarily want to search for a specific + * element, but want to search for elements greater than or less than some other. + * Someties we'd like to use split but don't know a good value to split at. + * This function lets the set implementation decide that value. + * + * The contract of chooseAndSplit is simply to select an element nondeterministically + * and return that element, together with the subsets of elements less than and + * greater than it. In this way, we can recursively traverse the set with any + * search criterion, and we avoid baking in the tree representation (although that + * is the obvious choice). + *) +(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> maybe (set 'a * 'a * set 'a)*) +definition chooseAndSplit :: " 'a Ord_class \ 'a set \('a set*'a*'a set)option " where + " chooseAndSplit dict_Basic_classes_Ord_a s = ( + if s = {} then + None + else + (let element = (set_choose s) in + (let (lt, gt) = (Lem_set.split + dict_Basic_classes_Ord_a element s) in + Some (lt, element, gt))))" + + +(* ----------------------------*) +(* universal set *) +(* --------------------------- *) + +(*val universal : forall 'a. SetType 'a => set 'a*) + + +(* ----------------------------*) +(* toList *) +(* --------------------------- *) + +(*val toList : forall 'a. SetType 'a => set 'a -> list 'a*) + + +(* ----------------------------*) +(* toOrderedList *) +(* --------------------------- *) + +(* toOrderedList returns a sorted list. Therefore the result is (given a suitable order) deterministic. + Therefore, it is much preferred to toList. However, it still is only defined for finite sets. So, please + use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations + and then transforming back to sets. *) + +(*val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a*) + +(*val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a*) + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val setCompareBy: forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> ordering*) +definition setCompareBy :: "('a \ 'a \ ordering)\ 'a set \ 'a set \ ordering " where + " setCompareBy cmp ss ts = ( + (let ss' = (ordered_list_of_set (\ x y . cmp x y = LT) ss) in + (let ts' = (ordered_list_of_set (\ x y . cmp x y = LT) ts) in + lexicographicCompareBy cmp ss' ts')))" + + +(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> ordering*) +definition setCompare :: " 'a Ord_class \ 'a set \ 'a set \ ordering " where + " setCompare dict_Basic_classes_Ord_a = ( setCompareBy + (compare_method dict_Basic_classes_Ord_a) )" + + +(* ----------------------------*) +(* unbounded fixed point *) +(* --------------------------- *) + +(* Is NOT supported by the coq backend! *) +(*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*) +(*let rec leastFixedPointUnbounded f x= + let fx = f x in + if fx subset x then x + else leastFixedPointUnbounded f (fx union x)*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_set_helpers.thy b/snapshots/isabelle/lib/lem/Lem_set_helpers.thy new file mode 100644 index 00000000..1a2f5f50 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set_helpers.thy @@ -0,0 +1,50 @@ +chapter \Generated by Lem from set_helpers.lem.\ + +theory "Lem_set_helpers" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + +begin + +(******************************************************************************) +(* Helper functions for sets *) +(******************************************************************************) + +(* Usually there is a something.lem file containing the main definitions and a + something_extra.lem one containing functions that might cause problems for + some backends or are just seldomly used. + + For sets the situation is different. folding is not well defined, since it + is only sensibly defined for finite sets and the traversal + order is underspecified. *) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num*) + +(*open import {coq} `Coq.Lists.List`*) + +(* ------------------------ *) +(* fold *) +(* ------------------------ *) + +(* fold is suspicious, because if given a function, for which + the order, in which the arguments are given, matters, its + results are undefined. On the other hand, it is very handy to + define other - non suspicious functions. + + Moreover, fold is central for OCaml, since it is used to + compile set comprehensions *) + +(*val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b*) + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_show.thy b/snapshots/isabelle/lib/lem/Lem_show.thy new file mode 100644 index 00000000..fced534d --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_show.thy @@ -0,0 +1,87 @@ +chapter \Generated by Lem from show.lem.\ + +theory "Lem_show" + +imports + Main + "Lem_string" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + +begin + + + +(*open import String Maybe Num Basic_classes*) + +(*open import {hol} `lemTheory`*) + +record 'a Show_class= + + show_method::" 'a \ string " + + + +definition instance_Show_Show_string_dict :: "(string)Show_class " where + " instance_Show_Show_string_dict = ((| + + show_method = (\ s. ([(char_of_nat 34)]) @ (s @ ([(char_of_nat 34)])))|) )" + + +(*val stringFromMaybe : forall 'a. ('a -> string) -> maybe 'a -> string*) +fun stringFromMaybe :: "('a \ string)\ 'a option \ string " where + " stringFromMaybe showX (Some x) = ( (''Just ('') @ (showX x @ ('')'')))" +|" stringFromMaybe showX None = ( (''Nothing''))" + + +definition instance_Show_Show_Maybe_maybe_dict :: " 'a Show_class \('a option)Show_class " where + " instance_Show_Show_Maybe_maybe_dict dict_Show_Show_a = ((| + + show_method = (\ x_opt. stringFromMaybe + (show_method dict_Show_Show_a) x_opt)|) )" + + +(*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*) +function (sequential,domintros) stringFromListAux :: "('a \ string)\ 'a list \ string " where + " stringFromListAux showX ([]) = ( (''''))" +|" stringFromListAux showX (x # xs') = ( + (case xs' of + [] => showX x + | _ => showX x @ ((''; '') @ stringFromListAux showX xs') + ))" +by pat_completeness auto + + +(*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*) +definition stringFromList :: "('a \ string)\ 'a list \ string " where + " stringFromList showX xs = ( + (''['') @ (stringFromListAux showX xs @ ('']'')))" + + +definition instance_Show_Show_list_dict :: " 'a Show_class \('a list)Show_class " where + " instance_Show_Show_list_dict dict_Show_Show_a = ((| + + show_method = (\ xs. stringFromList + (show_method dict_Show_Show_a) xs)|) )" + + +(*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*) +fun stringFromPair :: "('a \ string)\('b \ string)\ 'a*'b \ string " where + " stringFromPair showX showY (x,y) = ( + (''('') @ (showX x @ (('', '') @ (showY y @ ('')'')))))" + + +definition instance_Show_Show_tup2_dict :: " 'a Show_class \ 'b Show_class \('a*'b)Show_class " where + " instance_Show_Show_tup2_dict dict_Show_Show_a dict_Show_Show_b = ((| + + show_method = (stringFromPair + (show_method dict_Show_Show_a) (show_method dict_Show_Show_b))|) )" + + +definition instance_Show_Show_bool_dict :: "(bool)Show_class " where + " instance_Show_Show_bool_dict = ((| + + show_method = (\ b. if b then (''true'') else (''false''))|) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_show_extra.thy b/snapshots/isabelle/lib/lem/Lem_show_extra.thy new file mode 100644 index 00000000..25ab2570 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_show_extra.thy @@ -0,0 +1,74 @@ +chapter \Generated by Lem from show_extra.lem.\ + +theory "Lem_show_extra" + +imports + Main + "Lem_string" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + "Lem_set" + "Lem_relation" + "Lem_show" + "Lem_set_extra" + "Lem_string_extra" + +begin + + + +(*open import String Maybe Num Basic_classes Set Relation Show*) +(*import Set_extra String_extra*) + +definition instance_Show_Show_nat_dict :: "(nat)Show_class " where + " instance_Show_Show_nat_dict = ((| + + show_method = Lem_string_extra.stringFromNat |) )" + + +definition instance_Show_Show_Num_natural_dict :: "(nat)Show_class " where + " instance_Show_Show_Num_natural_dict = ((| + + show_method = Lem_string_extra.stringFromNatural |) )" + + +definition instance_Show_Show_Num_int_dict :: "(int)Show_class " where + " instance_Show_Show_Num_int_dict = ((| + + show_method = Lem_string_extra.stringFromInt |) )" + + +definition instance_Show_Show_Num_integer_dict :: "(int)Show_class " where + " instance_Show_Show_Num_integer_dict = ((| + + show_method = Lem_string_extra.stringFromInteger |) )" + + +definition stringFromSet :: "('a \ string)\ 'a set \ string " where + " stringFromSet showX xs = ( + (''{'') @ (Lem_show.stringFromListAux showX (list_of_set xs) @ (''}'')))" + + +(* Abbreviates the representation if the relation is transitive. *) +definition stringFromRelation :: "('a*'a \ string)\('a*'a)set \ string " where + " stringFromRelation showX rel = ( + if trans rel then + (let pruned_rel = (LemExtraDefs.without_trans_edges rel) in + if ((\ e \ rel. (e \ pruned_rel))) then + (* The relations are the same (there are no transitive edges), + so we can just as well print the original one. *) + stringFromSet showX rel + else + (''trancl of '') @ stringFromSet showX pruned_rel) + else + stringFromSet showX rel )" + + +definition instance_Show_Show_set_dict :: " 'a Show_class \('a set)Show_class " where + " instance_Show_Show_set_dict dict_Show_Show_a = ((| + + show_method = (\ xs. stringFromSet + (show_method dict_Show_Show_a) xs)|) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_sorting.thy b/snapshots/isabelle/lib/lem/Lem_sorting.thy new file mode 100644 index 00000000..d42425a2 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_sorting.thy @@ -0,0 +1,110 @@ +chapter \Generated by Lem from sorting.lem.\ + +theory "Lem_sorting" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_list" + "Lem_num" + "Lem" + "~~/src/HOL/Library/Permutation" + +begin + + + +(*open import Bool Basic_classes Maybe List Num*) + +(*open import {isabelle} `~~/src/HOL/Library/Permutation`*) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `sortingTheory` `permLib`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------- *) +(* permutations *) +(* ------------------------- *) + +(*val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + +fun isPermutationBy :: "('a \ 'a \ bool)\ 'a list \ 'a list \ bool " where + " isPermutationBy eq ([]) l2 = ( (l2 = []))" +|" isPermutationBy eq (x # xs) l2 = ( ( + (case delete_first (eq x) l2 of + None => False + | Some ys => isPermutationBy eq xs ys + ) + ))" + + + + +(* ------------------------- *) +(* isSorted *) +(* ------------------------- *) + +(* isSortedBy R l + checks, whether the list l is sorted by ordering R. + R should represent an order, i.e. it should be transitive. + Different backends defined isSorted slightly differently. However, + the definitions coincide for transitive R. Therefore there is the + following restriction: + + WARNING: Use isSorted and isSortedBy only with transitive relations! +*) + +(*val isSorted : forall 'a. Ord 'a => list 'a -> bool*) +(*val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool*) + +(* DPM: rejigged the definition with a nested match to get past Coq's termination checker. *) +(*let rec isSortedBy cmp l= match l with + | [] -> true + | x1 :: xs -> + match xs with + | [] -> true + | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs) + end +end*) + + +(* ----------------------- *) +(* insertion sort *) +(* ----------------------- *) + +(*val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a*) +(*val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +(*val insertSort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) + +(*let rec insertBy cmp e l= match l with + | [] -> [e] + | x :: xs -> if cmp x e then x :: (insertBy cmp e xs) else (e :: x :: xs) +end*) + +(*let insertSortBy cmp l= List.foldl (fun l e -> insertBy cmp e l) [] l*) + + +(* ----------------------- *) +(* general sorting *) +(* ----------------------- *) + +(*val sort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) +(*val sortByOrd: forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a*) + +(*val predicate_of_ord : forall 'a. ('a -> 'a -> ordering) -> 'a -> 'a -> bool*) +definition predicate_of_ord :: "('a \ 'a \ ordering)\ 'a \ 'a \ bool " where + " predicate_of_ord f x y = ( + (case f x y of + LT => True + | EQ => True + | GT => False + ))" + + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_string.thy b/snapshots/isabelle/lib/lem/Lem_string.thy new file mode 100644 index 00000000..9df246c4 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_string.thy @@ -0,0 +1,75 @@ +chapter \Generated by Lem from string.lem.\ + +theory "Lem_string" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_list" + +begin + + + +(*open import Bool Basic_classes List*) +(*open import {ocaml} `Xstring`*) +(*open import {hol} `lemTheory` `stringTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) + +(* ------------------------------------------- *) +(* translations between strings and char lists *) +(* ------------------------------------------- *) + +(*val toCharList : string -> list char*) + +(*val toString : list char -> string*) + + +(* ----------------------- *) +(* generating strings *) +(* ----------------------- *) + +(*val makeString : nat -> char -> string*) +(*let makeString len c= toString (replicate len c)*) + +(* ----------------------- *) +(* length *) +(* ----------------------- *) + +(*val stringLength : string -> nat*) + +(* ----------------------- *) +(* string concatenation *) +(* ----------------------- *) + +(*val ^ [stringAppend] : string -> string -> string*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*) + +(*let string_case s c_empty c_cons= + match (toCharList s) with + | [] -> c_empty + | c :: cs -> c_cons c (toString cs) + end*) + +(*val empty_string : string*) + +(*val cons_string : char -> string -> string*) + +(*val concat : string -> list string -> string*) +function (sequential,domintros) concat :: " string \(string)list \ string " where + " concat sep ([]) = ( (''''))" +|" concat sep (s # ss') = ( + (case ss' of + [] => s + | _ => s @ (sep @ concat sep ss') + ))" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/lem/Lem_string_extra.thy b/snapshots/isabelle/lib/lem/Lem_string_extra.thy new file mode 100644 index 00000000..bd8317ba --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_string_extra.thy @@ -0,0 +1,137 @@ +chapter \Generated by Lem from string_extra.lem.\ + +theory "Lem_string_extra" + +imports + Main + "Lem_num" + "Lem_list" + "Lem_basic_classes" + "Lem_string" + "Lem_list_extra" + +begin + +(******************************************************************************) +(* String functions *) +(******************************************************************************) + +(*open import Basic_classes*) +(*open import Num*) +(*open import List*) +(*open import String*) +(*open import List_extra*) +(*open import {hol} `stringLib`*) +(*open import {hol} `ASCIInumbersTheory`*) + + +(******************************************************************************) +(* Character's to numbers *) +(******************************************************************************) + +(*val ord : char -> nat*) + +(*val chr : nat -> char*) + +(******************************************************************************) +(* Converting to strings *) +(******************************************************************************) + +(*val stringFromNatHelper : nat -> list char -> list char*) +fun stringFromNatHelper :: " nat \(char)list \(char)list " where + " stringFromNatHelper n acc1 = ( + if n =( 0 :: nat) then + acc1 + else + stringFromNatHelper (n div( 10 :: nat)) (char_of_nat ((n mod( 10 :: nat)) +( 48 :: nat)) # acc1))" + + +(*val stringFromNat : nat -> string*) +definition stringFromNat :: " nat \ string " where + " stringFromNat n = ( + if n =( 0 :: nat) then (''0'') else (stringFromNatHelper n []))" + + +(*val stringFromNaturalHelper : natural -> list char -> list char*) +fun stringFromNaturalHelper :: " nat \(char)list \(char)list " where + " stringFromNaturalHelper n acc1 = ( + if n =( 0 :: nat) then + acc1 + else + stringFromNaturalHelper (n div( 10 :: nat)) (char_of_nat ( ((n mod( 10 :: nat)) +( 48 :: nat))) # acc1))" + + +(*val stringFromNatural : natural -> string*) +definition stringFromNatural :: " nat \ string " where + " stringFromNatural n = ( + if n =( 0 :: nat) then (''0'') else (stringFromNaturalHelper n []))" + + +(*val stringFromInt : int -> string*) +definition stringFromInt :: " int \ string " where + " stringFromInt i = ( + if i <( 0 :: int) then + (''-'') @ stringFromNat (nat (abs i)) + else + stringFromNat (nat (abs i)))" + + +(*val stringFromInteger : integer -> string*) +definition stringFromInteger :: " int \ string " where + " stringFromInteger i = ( + if i <( 0 :: int) then + (''-'') @ stringFromNatural (nat (abs i)) + else + stringFromNatural (nat (abs i)))" + + + +(******************************************************************************) +(* List-like operations *) +(******************************************************************************) + +(*val nth : string -> nat -> char*) +definition nth :: " string \ nat \ char " where + " nth s n = ( List.nth ( s) n )" + + +(*val stringConcat : list string -> string*) +definition stringConcat :: "(string)list \ string " where + " stringConcat s = ( + List.foldr (op@) s (''''))" + + +(******************************************************************************) +(* String comparison *) +(******************************************************************************) + +(*val stringCompare : string -> string -> ordering*) + +definition stringLess :: " string \ string \ bool " where + " stringLess x y = ( orderingIsLess (EQ))" + +definition stringLessEq :: " string \ string \ bool " where + " stringLessEq x y = ( \ (orderingIsGreater (EQ)))" + +definition stringGreater :: " string \ string \ bool " where + " stringGreater x y = ( stringLess y x )" + +definition stringGreaterEq :: " string \ string \ bool " where + " stringGreaterEq x y = ( stringLessEq y x )" + + +definition instance_Basic_classes_Ord_string_dict :: "(string)Ord_class " where + " instance_Basic_classes_Ord_string_dict = ((| + + compare_method = (\ x y. EQ), + + isLess_method = stringLess, + + isLessEqual_method = stringLessEq, + + isGreater_method = stringGreater, + + isGreaterEqual_method = stringGreaterEq |) )" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_tuple.thy b/snapshots/isabelle/lib/lem/Lem_tuple.thy new file mode 100644 index 00000000..66f1a209 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_tuple.thy @@ -0,0 +1,51 @@ +chapter \Generated by Lem from tuple.lem.\ + +theory "Lem_tuple" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + +begin + + + +(*open import Bool Basic_classes*) + +(* ----------------------- *) +(* fst *) +(* ----------------------- *) + +(*val fst : forall 'a 'b. 'a * 'b -> 'a*) +(*let fst (v1, v2)= v1*) + +(* ----------------------- *) +(* snd *) +(* ----------------------- *) + +(*val snd : forall 'a 'b. 'a * 'b -> 'b*) +(*let snd (v1, v2)= v2*) + + +(* ----------------------- *) +(* curry *) +(* ----------------------- *) + +(*val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)*) + +(* ----------------------- *) +(* uncurry *) +(* ----------------------- *) + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) + + +(* ----------------------- *) +(* swap *) +(* ----------------------- *) + +(*val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)*) +(*let swap (v1, v2)= (v2, v1)*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_word.thy b/snapshots/isabelle/lib/lem/Lem_word.thy new file mode 100644 index 00000000..bc56da3c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_word.thy @@ -0,0 +1,1024 @@ +chapter \Generated by Lem from word.lem.\ + +theory "Lem_word" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + "Lem_list" + "~~/src/HOL/Word/Word" + +begin + + + +(*open import Bool Maybe Num Basic_classes List*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib`*) + + +(* ========================================================================== *) +(* Define general purpose word, i.e. sequences of bits of arbitrary length *) +(* ========================================================================== *) + +datatype bitSequence = BitSeq " + nat option " " (* length of the sequence, Nothing means infinite length *) + bool " " bool (* sign of the word, used to fill up after concrete value is exhausted *) + list " (* the initial part of the sequence, least significant bit first *) + +(*val bitSeqEq : bitSequence -> bitSequence -> bool*) + +(*val boolListFrombitSeq : nat -> bitSequence -> list bool*) + +fun boolListFrombitSeqAux :: " nat \ 'a \ 'a list \ 'a list " where + " boolListFrombitSeqAux n s bl = ( + if n =( 0 :: nat) then [] else + (case bl of + [] => List.replicate n s + | b # bl' => b # (boolListFrombitSeqAux (n-( 1 :: nat)) s bl') + ))" + + +fun boolListFrombitSeq :: " nat \ bitSequence \(bool)list " where + " boolListFrombitSeq n (BitSeq _ s bl) = ( boolListFrombitSeqAux n s bl )" + + + +(*val bitSeqFromBoolList : list bool -> maybe bitSequence*) +definition bitSeqFromBoolList :: "(bool)list \(bitSequence)option " where + " bitSeqFromBoolList bl = ( + (case dest_init bl of + None => None + | Some (bl', s) => Some (BitSeq (Some (List.length bl)) s bl') + ))" + + + +(* cleans up the representation of a bitSequence without changing its semantics *) +(*val cleanBitSeq : bitSequence -> bitSequence*) +fun cleanBitSeq :: " bitSequence \ bitSequence " where + " cleanBitSeq (BitSeq len s bl) = ( (case len of + None => (BitSeq len s (List.rev (dropWhile ((op \) s) (List.rev bl)))) + | Some n => (BitSeq len s (List.rev (dropWhile ((op \) s) (List.rev (List.take (n-( 1 :: nat)) bl))))) +))" + + + +(*val bitSeqTestBit : bitSequence -> nat -> maybe bool*) +fun bitSeqTestBit :: " bitSequence \ nat \(bool)option " where + " bitSeqTestBit (BitSeq None s bl) pos = ( if pos < List.length bl then index bl pos else Some s )" +|" bitSeqTestBit (BitSeq(Some l) s bl) pos = ( if (pos \ l) then None else + if ((pos = (l -( 1 :: nat))) \ (pos \ List.length bl)) then Some s else + index bl pos )" + + +(*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*) +fun bitSeqSetBit :: " bitSequence \ nat \ bool \ bitSequence " where + " bitSeqSetBit (BitSeq len s bl) pos v = ( + (let bl' = (if (pos < List.length bl) then bl else bl @ List.replicate pos s) in + (let bl'' = (List.list_update bl' pos v) in + (let bs' = (BitSeq len s bl'') in + cleanBitSeq bs'))))" + + + +(*val resizeBitSeq : maybe nat -> bitSequence -> bitSequence*) +definition resizeBitSeq :: "(nat)option \ bitSequence \ bitSequence " where + " resizeBitSeq new_len bs = ( + (case cleanBitSeq bs of + (BitSeq len s bl) => + (let shorten_opt = ((case (new_len, len) of + (None, _) => None + | (Some l1, None) => Some l1 + | (Some l1, Some l2) => + if (l1 < l2) then Some l1 else None + )) in + (case shorten_opt of + None => BitSeq new_len s bl + | Some l1 => ( + (let bl' = (List.take l1 (bl @ [s])) in + (case dest_init bl' of + None => (BitSeq len s bl) (* do nothing if size 0 is requested *) + | Some (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'') + ))) + )) + ) )" + + +(*val bitSeqNot : bitSequence -> bitSequence*) +fun bitSeqNot :: " bitSequence \ bitSequence " where + " bitSeqNot (BitSeq len s bl) = ( BitSeq len (\ s) (List.map (\ x. \ x) bl))" + + +(*val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence*) + +(*val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool*) +fun bitSeqBinopAux :: "(bool \ bool \ bool)\ bool \(bool)list \ bool \(bool)list \(bool)list " where + " bitSeqBinopAux binop s1 ([]) s2 ([]) = ( [])" +|" bitSeqBinopAux binop s1 (b1 # bl1') s2 ([]) = ( (binop b1 s2) # bitSeqBinopAux binop s1 bl1' s2 [])" +|" bitSeqBinopAux binop s1 ([]) s2 (b2 # bl2') = ( (binop s1 b2) # bitSeqBinopAux binop s1 [] s2 bl2' )" +|" bitSeqBinopAux binop s1 (b1 # bl1') s2 (b2 # bl2') = ( (binop b1 b2) # bitSeqBinopAux binop s1 bl1' s2 bl2' )" + + +definition bitSeqBinop :: "(bool \ bool \ bool)\ bitSequence \ bitSequence \ bitSequence " where + " bitSeqBinop binop bs1 bs2 = ( ( + (case cleanBitSeq bs1 of + (BitSeq len1 s1 bl1) => + (case cleanBitSeq bs2 of + (BitSeq len2 s2 bl2) => + (let len = ((case (len1, len2) of + (Some l1, Some l2) => Some (max l1 l2) + | _ => None + )) in + (let s = (binop s1 s2) in + (let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in + cleanBitSeq (BitSeq len s bl)))) + ) + ) +))" + + +definition bitSeqAnd :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqAnd = ( bitSeqBinop (op \))" + +definition bitSeqOr :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqOr = ( bitSeqBinop (op \))" + +definition bitSeqXor :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqXor = ( bitSeqBinop (\ b1 b2. \ (b1 \ b2)))" + + +(*val bitSeqShiftLeft : bitSequence -> nat -> bitSequence*) +fun bitSeqShiftLeft :: " bitSequence \ nat \ bitSequence " where + " bitSeqShiftLeft (BitSeq len s bl) n = ( cleanBitSeq (BitSeq len s (List.replicate n False @ bl)))" + + +(*val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence*) +definition bitSeqArithmeticShiftRight :: " bitSequence \ nat \ bitSequence " where + " bitSeqArithmeticShiftRight bs n = ( + (case cleanBitSeq bs of + (BitSeq len s bl) => + cleanBitSeq (BitSeq len s (List.drop n bl)) + ) )" + + +(*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*) +definition bitSeqLogicalShiftRight :: " bitSequence \ nat \ bitSequence " where + " bitSeqLogicalShiftRight bs n = ( + if (n =( 0 :: nat)) then cleanBitSeq bs else + (case cleanBitSeq bs of + (BitSeq len s bl) => + (case len of + None => cleanBitSeq (BitSeq len s (List.drop n bl)) + | Some l => cleanBitSeq + (BitSeq len False ((List.drop n bl) @ List.replicate l s)) + ) + ) )" + + + +(* integerFromBoolList sign bl creates an integer from a list of bits + (least significant bit first) and an explicitly given sign bit. + It uses two's complement encoding. *) +(*val integerFromBoolList : (bool * list bool) -> integer*) + +fun integerFromBoolListAux :: " int \(bool)list \ int " where + " integerFromBoolListAux (acc1 :: int) (([]) :: bool list) = ( acc1 )" +|" integerFromBoolListAux (acc1 :: int) ((True # bl') :: bool list) = ( integerFromBoolListAux ((acc1 *( 2 :: int)) +( 1 :: int)) bl' )" +|" integerFromBoolListAux (acc1 :: int) ((False # bl') :: bool list) = ( integerFromBoolListAux (acc1 *( 2 :: int)) bl' )" + + +fun integerFromBoolList :: " bool*(bool)list \ int " where + " integerFromBoolList (sign, bl) = ( + if sign then + - (integerFromBoolListAux(( 0 :: int)) (List.rev (List.map (\ x. \ x) bl)) +( 1 :: int)) + else integerFromBoolListAux(( 0 :: int)) (List.rev bl))" + + +(* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*) +(*val boolListFromInteger : integer -> bool * list bool*) + +fun boolListFromNatural :: "(bool)list \ nat \(bool)list " where + " boolListFromNatural acc1 (remainder :: nat) = ( + if (remainder >( 0 :: nat)) then + (boolListFromNatural (((remainder mod( 2 :: nat)) =( 1 :: nat)) # acc1) + (remainder div( 2 :: nat))) + else + List.rev acc1 )" + + +definition boolListFromInteger :: " int \ bool*(bool)list " where + " boolListFromInteger (i :: int) = ( + if (i <( 0 :: int)) then + (True, List.map (\ x. \ x) (boolListFromNatural [] (nat (abs (- (i +( 1 :: int))))))) + else + (False, boolListFromNatural [] (nat (abs i))))" + + + +(* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough + bits, truncation happens *) +(*val bitSeqFromInteger : maybe nat -> integer -> bitSequence*) +definition bitSeqFromInteger :: "(nat)option \ int \ bitSequence " where + " bitSeqFromInteger len_opt i = ( + (let (s, bl) = (boolListFromInteger i) in + resizeBitSeq len_opt (BitSeq None s bl)))" + + + +(*val integerFromBitSeq : bitSequence -> integer*) +definition integerFromBitSeq :: " bitSequence \ int " where + " integerFromBitSeq bs = ( + (case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) ) )" + + + +(* Now we can via translation to integers map arithmetic operations to bitSequences *) + +(*val bitSeqArithUnaryOp : (integer -> integer) -> bitSequence -> bitSequence*) +definition bitSeqArithUnaryOp :: "(int \ int)\ bitSequence \ bitSequence " where + " bitSeqArithUnaryOp uop bs = ( + (case bs of + (BitSeq len _ _) => + bitSeqFromInteger len (uop (integerFromBitSeq bs)) + ) )" + + +(*val bitSeqArithBinOp : (integer -> integer -> integer) -> bitSequence -> bitSequence -> bitSequence*) +definition bitSeqArithBinOp :: "(int \ int \ int)\ bitSequence \ bitSequence \ bitSequence " where + " bitSeqArithBinOp binop bs1 bs2 = ( + (case bs1 of + (BitSeq len1 _ _) => + (case bs2 of + (BitSeq len2 _ _) => + (let len = ((case (len1, len2) of + (Some l1, Some l2) => Some (max l1 l2) + | _ => None + )) in + bitSeqFromInteger len + (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))) + ) + ) )" + + +(*val bitSeqArithBinTest : forall 'a. (integer -> integer -> 'a) -> bitSequence -> bitSequence -> 'a*) +definition bitSeqArithBinTest :: "(int \ int \ 'a)\ bitSequence \ bitSequence \ 'a " where + " bitSeqArithBinTest binop bs1 bs2 = ( binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))" + + + +(* now instantiate the number interface for bit-sequences *) + +(*val bitSeqFromNumeral : numeral -> bitSequence*) + +(*val bitSeqLess : bitSequence -> bitSequence -> bool*) +definition bitSeqLess :: " bitSequence \ bitSequence \ bool " where + " bitSeqLess bs1 bs2 = ( bitSeqArithBinTest (op<) bs1 bs2 )" + + +(*val bitSeqLessEqual : bitSequence -> bitSequence -> bool*) +definition bitSeqLessEqual :: " bitSequence \ bitSequence \ bool " where + " bitSeqLessEqual bs1 bs2 = ( bitSeqArithBinTest (op \) bs1 bs2 )" + + +(*val bitSeqGreater : bitSequence -> bitSequence -> bool*) +definition bitSeqGreater :: " bitSequence \ bitSequence \ bool " where + " bitSeqGreater bs1 bs2 = ( bitSeqArithBinTest (op>) bs1 bs2 )" + + +(*val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool*) +definition bitSeqGreaterEqual :: " bitSequence \ bitSequence \ bool " where + " bitSeqGreaterEqual bs1 bs2 = ( bitSeqArithBinTest (op \) bs1 bs2 )" + + +(*val bitSeqCompare : bitSequence -> bitSequence -> ordering*) +definition bitSeqCompare :: " bitSequence \ bitSequence \ ordering " where + " bitSeqCompare bs1 bs2 = ( bitSeqArithBinTest (genericCompare (op<) (op=)) bs1 bs2 )" + + +definition instance_Basic_classes_Ord_Word_bitSequence_dict :: "(bitSequence)Ord_class " where + " instance_Basic_classes_Ord_Word_bitSequence_dict = ((| + + compare_method = bitSeqCompare, + + isLess_method = bitSeqLess, + + isLessEqual_method = bitSeqLessEqual, + + isGreater_method = bitSeqGreater, + + isGreaterEqual_method = bitSeqGreaterEqual |) )" + + +(* arithmetic negation, don't mix up with bitwise negation *) +(*val bitSeqNegate : bitSequence -> bitSequence*) +definition bitSeqNegate :: " bitSequence \ bitSequence " where + " bitSeqNegate bs = ( bitSeqArithUnaryOp (\ i. - i) bs )" + + +definition instance_Num_NumNegate_Word_bitSequence_dict :: "(bitSequence)NumNegate_class " where + " instance_Num_NumNegate_Word_bitSequence_dict = ((| + + numNegate_method = bitSeqNegate |) )" + + + +(*val bitSeqAdd : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqAdd :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqAdd bs1 bs2 = ( bitSeqArithBinOp (op+) bs1 bs2 )" + + +definition instance_Num_NumAdd_Word_bitSequence_dict :: "(bitSequence)NumAdd_class " where + " instance_Num_NumAdd_Word_bitSequence_dict = ((| + + numAdd_method = bitSeqAdd |) )" + + +(*val bitSeqMinus : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMinus :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqMinus bs1 bs2 = ( bitSeqArithBinOp (op-) bs1 bs2 )" + + +definition instance_Num_NumMinus_Word_bitSequence_dict :: "(bitSequence)NumMinus_class " where + " instance_Num_NumMinus_Word_bitSequence_dict = ((| + + numMinus_method = bitSeqMinus |) )" + + +(*val bitSeqSucc : bitSequence -> bitSequence*) +definition bitSeqSucc :: " bitSequence \ bitSequence " where + " bitSeqSucc bs = ( bitSeqArithUnaryOp (\ n. n +( 1 :: int)) bs )" + + +definition instance_Num_NumSucc_Word_bitSequence_dict :: "(bitSequence)NumSucc_class " where + " instance_Num_NumSucc_Word_bitSequence_dict = ((| + + succ_method = bitSeqSucc |) )" + + +(*val bitSeqPred : bitSequence -> bitSequence*) +definition bitSeqPred :: " bitSequence \ bitSequence " where + " bitSeqPred bs = ( bitSeqArithUnaryOp (\ n. n -( 1 :: int)) bs )" + + +definition instance_Num_NumPred_Word_bitSequence_dict :: "(bitSequence)NumPred_class " where + " instance_Num_NumPred_Word_bitSequence_dict = ((| + + pred_method = bitSeqPred |) )" + + +(*val bitSeqMult : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMult :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqMult bs1 bs2 = ( bitSeqArithBinOp (op*) bs1 bs2 )" + + +definition instance_Num_NumMult_Word_bitSequence_dict :: "(bitSequence)NumMult_class " where + " instance_Num_NumMult_Word_bitSequence_dict = ((| + + numMult_method = bitSeqMult |) )" + + + +(*val bitSeqPow : bitSequence -> nat -> bitSequence*) +definition bitSeqPow :: " bitSequence \ nat \ bitSequence " where + " bitSeqPow bs n = ( bitSeqArithUnaryOp (\ i . i ^ n) bs )" + + +definition instance_Num_NumPow_Word_bitSequence_dict :: "(bitSequence)NumPow_class " where + " instance_Num_NumPow_Word_bitSequence_dict = ((| + + numPow_method = bitSeqPow |) )" + + +(*val bitSeqDiv : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqDiv :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqDiv bs1 bs2 = ( bitSeqArithBinOp (op div) bs1 bs2 )" + + +definition instance_Num_NumIntegerDivision_Word_bitSequence_dict :: "(bitSequence)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Word_bitSequence_dict = ((| + + div_method = bitSeqDiv |) )" + + +definition instance_Num_NumDivision_Word_bitSequence_dict :: "(bitSequence)NumDivision_class " where + " instance_Num_NumDivision_Word_bitSequence_dict = ((| + + numDivision_method = bitSeqDiv |) )" + + +(*val bitSeqMod : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMod :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqMod bs1 bs2 = ( bitSeqArithBinOp (op mod) bs1 bs2 )" + + +definition instance_Num_NumRemainder_Word_bitSequence_dict :: "(bitSequence)NumRemainder_class " where + " instance_Num_NumRemainder_Word_bitSequence_dict = ((| + + mod_method = bitSeqMod |) )" + + +(*val bitSeqMin : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMin :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqMin bs1 bs2 = ( bitSeqArithBinOp min bs1 bs2 )" + + +(*val bitSeqMax : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMax :: " bitSequence \ bitSequence \ bitSequence " where + " bitSeqMax bs1 bs2 = ( bitSeqArithBinOp max bs1 bs2 )" + + +definition instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict :: "(bitSequence)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict = ((| + + max_method = bitSeqMax, + + min_method = bitSeqMin |) )" + + + + + +(* ========================================================================== *) +(* Interface for bitoperations *) +(* ========================================================================== *) + +record 'a WordNot_class= + + lnot_method ::" 'a \ 'a " + + + +record 'a WordAnd_class= + + land_method ::" 'a \ 'a \ 'a " + + + +record 'a WordOr_class= + + lor_method ::" 'a \ 'a \ 'a " + + + + +record 'a WordXor_class= + + lxor_method ::" 'a \ 'a \ 'a " + + + +record 'a WordLsl_class= + + lsl_method ::" 'a \ nat \ 'a " + + + +record 'a WordLsr_class= + + lsr_method ::" 'a \ nat \ 'a " + + + +record 'a WordAsr_class= + + asr_method ::" 'a \ nat \ 'a " + + + +(* ----------------------- *) +(* bitSequence *) +(* ----------------------- *) + +definition instance_Word_WordNot_Word_bitSequence_dict :: "(bitSequence)WordNot_class " where + " instance_Word_WordNot_Word_bitSequence_dict = ((| + + lnot_method = bitSeqNot |) )" + + +definition instance_Word_WordAnd_Word_bitSequence_dict :: "(bitSequence)WordAnd_class " where + " instance_Word_WordAnd_Word_bitSequence_dict = ((| + + land_method = bitSeqAnd |) )" + + +definition instance_Word_WordOr_Word_bitSequence_dict :: "(bitSequence)WordOr_class " where + " instance_Word_WordOr_Word_bitSequence_dict = ((| + + lor_method = bitSeqOr |) )" + + +definition instance_Word_WordXor_Word_bitSequence_dict :: "(bitSequence)WordXor_class " where + " instance_Word_WordXor_Word_bitSequence_dict = ((| + + lxor_method = bitSeqXor |) )" + + +definition instance_Word_WordLsl_Word_bitSequence_dict :: "(bitSequence)WordLsl_class " where + " instance_Word_WordLsl_Word_bitSequence_dict = ((| + + lsl_method = bitSeqShiftLeft |) )" + + +definition instance_Word_WordLsr_Word_bitSequence_dict :: "(bitSequence)WordLsr_class " where + " instance_Word_WordLsr_Word_bitSequence_dict = ((| + + lsr_method = bitSeqLogicalShiftRight |) )" + + +definition instance_Word_WordAsr_Word_bitSequence_dict :: "(bitSequence)WordAsr_class " where + " instance_Word_WordAsr_Word_bitSequence_dict = ((| + + asr_method = bitSeqArithmeticShiftRight |) )" + + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) + +(*val int32Lnot : int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordNot_Num_int32_dict :: "( 32 word)WordNot_class " where + " instance_Word_WordNot_Num_int32_dict = ((| + + lnot_method = (\ w. (NOT w))|) )" + + + +(*val int32Lor : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordOr_Num_int32_dict :: "( 32 word)WordOr_class " where + " instance_Word_WordOr_Num_int32_dict = ((| + + lor_method = (op OR)|) )" + + +(*val int32Lxor : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordXor_Num_int32_dict :: "( 32 word)WordXor_class " where + " instance_Word_WordXor_Num_int32_dict = ((| + + lxor_method = (op XOR)|) )" + + +(*val int32Land : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordAnd_Num_int32_dict :: "( 32 word)WordAnd_class " where + " instance_Word_WordAnd_Num_int32_dict = ((| + + land_method = (op AND)|) )" + + +(*val int32Lsl : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordLsl_Num_int32_dict :: "( 32 word)WordLsl_class " where + " instance_Word_WordLsl_Num_int32_dict = ((| + + lsl_method = (op<<)|) )" + + +(*val int32Lsr : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordLsr_Num_int32_dict :: "( 32 word)WordLsr_class " where + " instance_Word_WordLsr_Num_int32_dict = ((| + + lsr_method = (op>>)|) )" + + + +(*val int32Asr : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordAsr_Num_int32_dict :: "( 32 word)WordAsr_class " where + " instance_Word_WordAsr_Num_int32_dict = ((| + + asr_method = (op>>>)|) )" + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) + +(*val int64Lnot : int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordNot_Num_int64_dict :: "( 64 word)WordNot_class " where + " instance_Word_WordNot_Num_int64_dict = ((| + + lnot_method = (\ w. (NOT w))|) )" + + +(*val int64Lor : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordOr_Num_int64_dict :: "( 64 word)WordOr_class " where + " instance_Word_WordOr_Num_int64_dict = ((| + + lor_method = (op OR)|) )" + + +(*val int64Lxor : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordXor_Num_int64_dict :: "( 64 word)WordXor_class " where + " instance_Word_WordXor_Num_int64_dict = ((| + + lxor_method = (op XOR)|) )" + + +(*val int64Land : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordAnd_Num_int64_dict :: "( 64 word)WordAnd_class " where + " instance_Word_WordAnd_Num_int64_dict = ((| + + land_method = (op AND)|) )" + + +(*val int64Lsl : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordLsl_Num_int64_dict :: "( 64 word)WordLsl_class " where + " instance_Word_WordLsl_Num_int64_dict = ((| + + lsl_method = (op<<)|) )" + + +(*val int64Lsr : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordLsr_Num_int64_dict :: "( 64 word)WordLsr_class " where + " instance_Word_WordLsr_Num_int64_dict = ((| + + lsr_method = (op>>)|) )" + + +(*val int64Asr : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordAsr_Num_int64_dict :: "( 64 word)WordAsr_class " where + " instance_Word_WordAsr_Num_int64_dict = ((| + + asr_method = (op>>>)|) )" + + + +(* ----------------------- *) +(* Words via bit sequences *) +(* ----------------------- *) + +(*val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a*) +definition defaultLnot :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ 'a " where + " defaultLnot fromBitSeq toBitSeq x = ( fromBitSeq (bitSeqNegate (toBitSeq x)))" + + +(*val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLand :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ 'a \ 'a " where + " defaultLand fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLor :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ 'a \ 'a " where + " defaultLor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLxor :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ 'a \ 'a " where + " defaultLxor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultLsl :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ nat \ 'a " where + " defaultLsl fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqShiftLeft (toBitSeq x) n))" + + +(*val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultLsr :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ nat \ 'a " where + " defaultLsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n))" + + +(*val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultAsr :: "(bitSequence \ 'a)\('a \ bitSequence)\ 'a \ nat \ 'a " where + " defaultAsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n))" + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerLnot : integer -> integer*) +definition integerLnot :: " int \ int " where + " integerLnot i = ( - (i +( 1 :: int)))" + + +definition instance_Word_WordNot_Num_integer_dict :: "(int)WordNot_class " where + " instance_Word_WordNot_Num_integer_dict = ((| + + lnot_method = integerLnot |) )" + + + +(*val integerLor : integer -> integer -> integer*) +definition integerLor :: " int \ int \ int " where + " integerLor i1 i2 = ( defaultLor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordOr_Num_integer_dict :: "(int)WordOr_class " where + " instance_Word_WordOr_Num_integer_dict = ((| + + lor_method = integerLor |) )" + + +(*val integerLxor : integer -> integer -> integer*) +definition integerLxor :: " int \ int \ int " where + " integerLxor i1 i2 = ( defaultLxor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordXor_Num_integer_dict :: "(int)WordXor_class " where + " instance_Word_WordXor_Num_integer_dict = ((| + + lxor_method = integerLxor |) )" + + +(*val integerLand : integer -> integer -> integer*) +definition integerLand :: " int \ int \ int " where + " integerLand i1 i2 = ( defaultLand integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordAnd_Num_integer_dict :: "(int)WordAnd_class " where + " instance_Word_WordAnd_Num_integer_dict = ((| + + land_method = integerLand |) )" + + +(*val integerLsl : integer -> nat -> integer*) +definition integerLsl :: " int \ nat \ int " where + " integerLsl i n = ( defaultLsl integerFromBitSeq (bitSeqFromInteger None) i n )" + + +definition instance_Word_WordLsl_Num_integer_dict :: "(int)WordLsl_class " where + " instance_Word_WordLsl_Num_integer_dict = ((| + + lsl_method = integerLsl |) )" + + +(*val integerAsr : integer -> nat -> integer*) +definition integerAsr :: " int \ nat \ int " where + " integerAsr i n = ( defaultAsr integerFromBitSeq (bitSeqFromInteger None) i n )" + + +definition instance_Word_WordLsr_Num_integer_dict :: "(int)WordLsr_class " where + " instance_Word_WordLsr_Num_integer_dict = ((| + + lsr_method = integerAsr |) )" + + +definition instance_Word_WordAsr_Num_integer_dict :: "(int)WordAsr_class " where + " instance_Word_WordAsr_Num_integer_dict = ((| + + asr_method = integerAsr |) )" + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on ints. + However, since int is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of int *) + +(*val intFromBitSeq : bitSequence -> int*) +definition intFromBitSeq :: " bitSequence \ int " where + " intFromBitSeq bs = ( (integerFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))" + + + +(*val bitSeqFromInt : int -> bitSequence*) +definition bitSeqFromInt :: " int \ bitSequence " where + " bitSeqFromInt i = ( bitSeqFromInteger (Some(( 31 :: nat))) ( i))" + + + +(*val intLnot : int -> int*) +definition intLnot :: " int \ int " where + " intLnot i = ( - (i +( 1 :: int)))" + + +definition instance_Word_WordNot_Num_int_dict :: "(int)WordNot_class " where + " instance_Word_WordNot_Num_int_dict = ((| + + lnot_method = intLnot |) )" + + +(*val intLor : int -> int -> int*) +definition intLor :: " int \ int \ int " where + " intLor i1 i2 = ( defaultLor intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordOr_Num_int_dict :: "(int)WordOr_class " where + " instance_Word_WordOr_Num_int_dict = ((| + + lor_method = intLor |) )" + + +(*val intLxor : int -> int -> int*) +definition intLxor :: " int \ int \ int " where + " intLxor i1 i2 = ( defaultLxor intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordXor_Num_int_dict :: "(int)WordXor_class " where + " instance_Word_WordXor_Num_int_dict = ((| + + lxor_method = intLxor |) )" + + +(*val intLand : int -> int -> int*) +definition intLand :: " int \ int \ int " where + " intLand i1 i2 = ( defaultLand intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordAnd_Num_int_dict :: "(int)WordAnd_class " where + " instance_Word_WordAnd_Num_int_dict = ((| + + land_method = intLand |) )" + + +(*val intLsl : int -> nat -> int*) +definition intLsl :: " int \ nat \ int " where + " intLsl i n = ( defaultLsl intFromBitSeq bitSeqFromInt i n )" + + +definition instance_Word_WordLsl_Num_int_dict :: "(int)WordLsl_class " where + " instance_Word_WordLsl_Num_int_dict = ((| + + lsl_method = intLsl |) )" + + +(*val intAsr : int -> nat -> int*) +definition intAsr :: " int \ nat \ int " where + " intAsr i n = ( defaultAsr intFromBitSeq bitSeqFromInt i n )" + + +definition instance_Word_WordAsr_Num_int_dict :: "(int)WordAsr_class " where + " instance_Word_WordAsr_Num_int_dict = ((| + + asr_method = intAsr |) )" + + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* some operations work also on positive numbers *) + +(*val naturalFromBitSeq : bitSequence -> natural*) +definition naturalFromBitSeq :: " bitSequence \ nat " where + " naturalFromBitSeq bs = ( nat (abs (integerFromBitSeq bs)))" + + +(*val bitSeqFromNatural : maybe nat -> natural -> bitSequence*) +definition bitSeqFromNatural :: "(nat)option \ nat \ bitSequence " where + " bitSeqFromNatural len n = ( bitSeqFromInteger len (int n))" + + +(*val naturalLor : natural -> natural -> natural*) +definition naturalLor :: " nat \ nat \ nat " where + " naturalLor i1 i2 = ( defaultLor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordOr_Num_natural_dict :: "(nat)WordOr_class " where + " instance_Word_WordOr_Num_natural_dict = ((| + + lor_method = naturalLor |) )" + + +(*val naturalLxor : natural -> natural -> natural*) +definition naturalLxor :: " nat \ nat \ nat " where + " naturalLxor i1 i2 = ( defaultLxor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordXor_Num_natural_dict :: "(nat)WordXor_class " where + " instance_Word_WordXor_Num_natural_dict = ((| + + lxor_method = naturalLxor |) )" + + +(*val naturalLand : natural -> natural -> natural*) +definition naturalLand :: " nat \ nat \ nat " where + " naturalLand i1 i2 = ( defaultLand naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordAnd_Num_natural_dict :: "(nat)WordAnd_class " where + " instance_Word_WordAnd_Num_natural_dict = ((| + + land_method = naturalLand |) )" + + +(*val naturalLsl : natural -> nat -> natural*) +definition naturalLsl :: " nat \ nat \ nat " where + " naturalLsl i n = ( defaultLsl naturalFromBitSeq (bitSeqFromNatural None) i n )" + + +definition instance_Word_WordLsl_Num_natural_dict :: "(nat)WordLsl_class " where + " instance_Word_WordLsl_Num_natural_dict = ((| + + lsl_method = naturalLsl |) )" + + +(*val naturalAsr : natural -> nat -> natural*) +definition naturalAsr :: " nat \ nat \ nat " where + " naturalAsr i n = ( defaultAsr naturalFromBitSeq (bitSeqFromNatural None) i n )" + + +definition instance_Word_WordLsr_Num_natural_dict :: "(nat)WordLsr_class " where + " instance_Word_WordLsr_Num_natural_dict = ((| + + lsr_method = naturalAsr |) )" + + +definition instance_Word_WordAsr_Num_natural_dict :: "(nat)WordAsr_class " where + " instance_Word_WordAsr_Num_natural_dict = ((| + + asr_method = naturalAsr |) )" + + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on nats. + However, since nat is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of nat *) + +(*val natFromBitSeq : bitSequence -> nat*) +definition natFromBitSeq :: " bitSequence \ nat " where + " natFromBitSeq bs = ( (naturalFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))" + + + +(*val bitSeqFromNat : nat -> bitSequence*) +definition bitSeqFromNat :: " nat \ bitSequence " where + " bitSeqFromNat i = ( bitSeqFromNatural (Some(( 31 :: nat))) ( i))" + + + +(*val natLor : nat -> nat -> nat*) +definition natLor :: " nat \ nat \ nat " where + " natLor i1 i2 = ( defaultLor natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordOr_nat_dict :: "(nat)WordOr_class " where + " instance_Word_WordOr_nat_dict = ((| + + lor_method = natLor |) )" + + +(*val natLxor : nat -> nat -> nat*) +definition natLxor :: " nat \ nat \ nat " where + " natLxor i1 i2 = ( defaultLxor natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordXor_nat_dict :: "(nat)WordXor_class " where + " instance_Word_WordXor_nat_dict = ((| + + lxor_method = natLxor |) )" + + +(*val natLand : nat -> nat -> nat*) +definition natLand :: " nat \ nat \ nat " where + " natLand i1 i2 = ( defaultLand natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordAnd_nat_dict :: "(nat)WordAnd_class " where + " instance_Word_WordAnd_nat_dict = ((| + + land_method = natLand |) )" + + +(*val natLsl : nat -> nat -> nat*) +definition natLsl :: " nat \ nat \ nat " where + " natLsl i n = ( defaultLsl natFromBitSeq bitSeqFromNat i n )" + + +definition instance_Word_WordLsl_nat_dict :: "(nat)WordLsl_class " where + " instance_Word_WordLsl_nat_dict = ((| + + lsl_method = natLsl |) )" + + +(*val natAsr : nat -> nat -> nat*) +definition natAsr :: " nat \ nat \ nat " where + " natAsr i n = ( defaultAsr natFromBitSeq bitSeqFromNat i n )" + + +definition instance_Word_WordAsr_nat_dict :: "(nat)WordAsr_class " where + " instance_Word_WordAsr_nat_dict = ((| + + asr_method = natAsr |) )" + + +end diff --git a/snapshots/isabelle/lib/lem/ROOT b/snapshots/isabelle/lib/lem/ROOT new file mode 100644 index 00000000..443687f9 --- /dev/null +++ b/snapshots/isabelle/lib/lem/ROOT @@ -0,0 +1,7 @@ +session LEM = "HOL-Word" + + description {* + HOL + LEM specific theories + *} + theories Lem_pervasives Lem_pervasives_extra + + diff --git a/snapshots/isabelle/lib/sail/Hoare.thy b/snapshots/isabelle/lib/sail/Hoare.thy new file mode 100644 index 00000000..ee7a5fa6 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Hoare.thy @@ -0,0 +1,320 @@ +theory Hoare + imports + State_lemmas + "HOL-Eisbach.Eisbach_Tools" +begin + +(*adhoc_overloading + Monad_Syntax.bind State_monad.bindS*) + +section \Hoare logic for the state, exception and nondeterminism monad\ + +subsection \Hoare triples\ + +type_synonym 'regs predS = "'regs sequential_state \ bool" + +definition PrePost :: "'regs predS \ ('regs, 'a, 'e) monadS \ (('a, 'e) result \ 'regs predS) \ bool" + where "PrePost P f Q \ (\s. P s \ (\(r, s') \ f s. Q r s'))" + +lemma PrePostI: + assumes "\s r s'. P s \ (r, s') \ f s \ Q r s'" + shows "PrePost P f Q" + using assms unfolding PrePost_def by auto + +lemma PrePost_elim: + assumes "PrePost P f Q" and "P s" and "(r, s') \ f s" + obtains "Q r s'" + using assms by (fastforce simp: PrePost_def) + +lemma PrePost_consequence: + assumes "PrePost A f B" + and "\s. P s \ A s" and "\v s. B v s \ Q v s" + shows "PrePost P f Q" + using assms unfolding PrePost_def by (blast intro: list.pred_mono_strong) + +lemma PrePost_strengthen_pre: + assumes "PrePost A f C" and "\s. B s \ A s" + shows "PrePost B f C" + using assms by (rule PrePost_consequence) + +lemma PrePost_weaken_post: + assumes "PrePost A f B" and "\v s. B v s \ C v s" + shows "PrePost A f C" + using assms by (blast intro: PrePost_consequence) + +named_theorems PrePost_intro + +lemma PrePost_True_post[PrePost_intro, intro, simp]: + "PrePost P m (\_ _. True)" + unfolding PrePost_def by auto + +lemma PrePost_any: "PrePost (\s. \(r, s') \ m s. Q r s') m Q" + unfolding PrePost_def by auto + +lemma PrePost_returnS[intro, PrePost_intro]: "PrePost (P (Value x)) (returnS x) P" + unfolding PrePost_def returnS_def by auto + +lemma PrePost_bindS[intro, PrePost_intro]: + assumes f: "\s a s'. (Value a, s') \ m s \ PrePost (R a) (f a) Q" + and m: "PrePost P m (\r. case r of Value a \ R a | Ex e \ Q (Ex e))" + shows "PrePost P (bindS m f) Q" +proof (intro PrePostI) + fix s r s' + assume P: "P s" and bind: "(r, s') \ bindS m f s" + from bind show "Q r s'" + proof (cases r s' m f s rule: bindS_cases) + case (Value a a' s'') + then have "R a' s''" using P m by (auto elim: PrePost_elim) + then show ?thesis using Value f by (auto elim: PrePost_elim) + next + case (Ex_Left e) + then show ?thesis using P m by (auto elim: PrePost_elim) + next + case (Ex_Right e a s'') + then have "R a s''" using P m by (auto elim: PrePost_elim) + then show ?thesis using Ex_Right f by (auto elim: PrePost_elim) + qed +qed + +lemma PrePost_bindS_ignore: + assumes f: "PrePost R f Q" + and m : "PrePost P m (\r. case r of Value a \ R | Ex e \ Q (Ex e))" + shows "PrePost P (bindS m (\_. f)) Q" + using assms by auto + +lemma PrePost_bindS_unit: + fixes m :: "('regs, unit, 'e) monadS" + assumes f: "PrePost R (f ()) Q" + and m: "PrePost P m (\r. case r of Value a \ R | Ex e \ Q (Ex e))" + shows "PrePost P (bindS m f) Q" + using assms by auto + +lemma PrePost_readS[intro, PrePost_intro]: "PrePost (\s. P (Value (f s)) s) (readS f) P" + unfolding PrePost_def readS_def returnS_def by auto + +lemma PrePost_updateS[intro, PrePost_intro]: "PrePost (\s. P (Value ()) (f s)) (updateS f) P" + unfolding PrePost_def updateS_def returnS_def by auto + +lemma PrePost_if: + assumes "b \ PrePost P f Q" and "\b \ PrePost P g Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_branch[PrePost_intro]: + assumes "b \ PrePost Pf f Q" and "\b \ PrePost Pg g Q" + shows "PrePost (if b then Pf else Pg) (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_then: + assumes "b" and "PrePost P f Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_else: + assumes "\b" and "PrePost P g Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_prod_cases[PrePost_intro]: + assumes "PrePost P (f (fst x) (snd x)) Q" + shows "PrePost P (case x of (a, b) \ f a b) Q" + using assms by (auto split: prod.splits) + +lemma PrePost_option_cases[PrePost_intro]: + assumes "\a. PrePost (PS a) (s a) Q" and "PrePost PN n Q" + shows "PrePost (case x of Some a \ PS a | None \ PN) (case x of Some a \ s a | None \ n) Q" + using assms by (auto split: option.splits) + +lemma PrePost_let[intro, PrePost_intro]: + assumes "PrePost P (m y) Q" + shows "PrePost P (let x = y in m x) Q" + using assms by auto + +lemma PrePost_assert_expS[intro, PrePost_intro]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P" + unfolding PrePost_def assert_expS_def by (auto simp: returnS_def failS_def) + +lemma PrePost_chooseS[intro, PrePost_intro]: "PrePost (\s. \x \ xs. Q (Value x) s) (chooseS xs) Q" + by (auto simp: PrePost_def chooseS_def) + +lemma PrePost_failS[intro, PrePost_intro]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q" + by (auto simp: PrePost_def failS_def) + +lemma case_result_combine[simp]: + "(case r of Value a \ Q (Value a) | Ex e \ Q (Ex e)) = Q r" + by (auto split: result.splits) + +lemma PrePost_foreachS_Nil[intro, simp, PrePost_intro]: + "PrePost (Q (Value vars)) (foreachS [] vars body) Q" + by auto + +lemma PrePost_foreachS_Cons: + assumes "\s vars' s'. (Value vars', s') \ body x vars s \ PrePost (Q (Value vars')) (foreachS xs vars' body) Q" + and "PrePost (Q (Value vars)) (body x vars) Q" + shows "PrePost (Q (Value vars)) (foreachS (x # xs) vars body) Q" + using assms by fastforce + +lemma PrePost_foreachS_invariant: + assumes "\x vars. x \ set xs \ PrePost (Q (Value vars)) (body x vars) Q" + shows "PrePost (Q (Value vars)) (foreachS xs vars body) Q" +proof (use assms in \induction xs arbitrary: vars\) + case (Cons x xs) + have "PrePost (Q (Value vars)) (bindS (body x vars) (\vars. foreachS xs vars body)) Q" + proof (rule PrePost_bindS) + fix vars' + show "PrePost (Q (Value vars')) (foreachS xs vars' body) Q" + using Cons by auto + show "PrePost (Q (Value vars)) (body x vars) (\r. case r of Value a \ Q (Value a) | result.Ex e \ Q (result.Ex e))" + unfolding case_result_combine + using Cons by auto + qed + then show ?case by auto +qed auto + +subsection \Hoare quadruples\ + +text \It is often convenient to treat the exception case separately. For this purpose, we use +a Hoare logic similar to the one used in [1]. It features not only Hoare triples, but also quadruples +with two postconditions: one for the case where the computation succeeds, and one for the case where +there is an exception. + +[1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’, +in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\ + +definition PrePostE :: "'regs predS \ ('regs, 'a, 'e) monadS \ ('a \ 'regs predS) \ ('e ex \ 'regs predS) \ bool" + where "PrePostE P f Q E \ PrePost P f (\v. case v of Value a \ Q a | Ex e \ E e)" + +lemmas PrePost_defs = PrePost_def PrePostE_def + +lemma PrePostE_I[case_names Val Err]: + assumes "\s a s'. P s \ (Value a, s') \ f s \ Q a s'" + and "\s e s'. P s \ (Ex e, s') \ f s \ E e s'" + shows "PrePostE P f Q E" + using assms unfolding PrePostE_def by (intro PrePostI) (auto split: result.splits) + +lemma PrePostE_PrePost: + assumes "PrePost P m (\v. case v of Value a \ Q a | Ex e \ E e)" + shows "PrePostE P m Q E" + using assms unfolding PrePostE_def by auto + +lemma PrePostE_elim: + assumes "PrePostE P f Q E" and "P s" and "(r, s') \ f s" + obtains + (Val) v where "r = Value v" "Q v s'" + | (Ex) e where "r = Ex e" "E e s'" + using assms by (cases r; fastforce simp: PrePost_defs) + +lemma PrePostE_consequence: + assumes "PrePostE A f B C" + and "\s. P s \ A s" and "\v s. B v s \ Q v s" and "\e s. C e s \ E e s" + shows "PrePostE P f Q E" + using assms unfolding PrePostE_def by (auto elim: PrePost_consequence split: result.splits) + +lemma PrePostE_strengthen_pre: + assumes "PrePostE R f Q E" and "\s. P s \ R s" + shows "PrePostE P f Q E" + using assms PrePostE_consequence by blast + +lemma PrePostE_weaken_post: + assumes "PrePostE A f B E" and "\v s. B v s \ C v s" + shows "PrePostE A f C E" + using assms by (blast intro: PrePostE_consequence) + +named_theorems PrePostE_intro + +lemma PrePostE_True_post[PrePost_intro, intro, simp]: + "PrePostE P m (\_ _. True) (\_ _. True)" + unfolding PrePost_defs by (auto split: result.splits) + +lemma PrePostE_any: "PrePostE (\s. \(r, s') \ m s. case r of Value a \ Q a s' | Ex e \ E e s') m Q E" + by (intro PrePostE_I) auto + +lemma PrePostE_returnS[PrePostE_intro, intro, simp]: + "PrePostE (P x) (returnS x) P Q" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_bindS[intro, PrePostE_intro]: + assumes f: "\s a s'. (Value a, s') \ m s \ PrePostE (R a) (f a) Q E" + and m: "PrePostE P m R E" + shows "PrePostE P (bindS m f) Q E" + using assms + by (fastforce simp: PrePostE_def cong: result.case_cong) + +lemma PrePostE_bindS_ignore: + assumes f: "PrePostE R f Q E" + and m : "PrePostE P m (\_. R) E" + shows "PrePostE P (bindS m (\_. f)) Q E" + using assms by auto + +lemma PrePostE_bindS_unit: + fixes m :: "('regs, unit, 'e) monadS" + assumes f: "PrePostE R (f ()) Q E" + and m: "PrePostE P m (\_. R) E" + shows "PrePostE P (bindS m f) Q E" + using assms by auto + +lemma PrePostE_readS[PrePostE_intro, intro]: "PrePostE (\s. Q (f s) s) (readS f) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_updateS[PrePostE_intro, intro]: "PrePostE (\s. Q () (f s)) (updateS f) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_if_branch[PrePostE_intro]: + assumes "b \ PrePostE Pf f Q E" and "\b \ PrePostE Pg g Q E" + shows "PrePostE (if b then Pf else Pg) (if b then f else g) Q E" + using assms by (auto) + +lemma PrePostE_if: + assumes "b \ PrePostE P f Q E" and "\b \ PrePostE P g Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_if_then: + assumes "b" and "PrePostE P f Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_if_else: + assumes "\ b" and "PrePostE P g Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_prod_cases[PrePostE_intro]: + assumes "PrePostE P (f (fst x) (snd x)) Q E" + shows "PrePostE P (case x of (a, b) \ f a b) Q E" + using assms by (auto split: prod.splits) + +lemma PrePostE_option_cases[PrePostE_intro]: + assumes "\a. PrePostE (PS a) (s a) Q E" and "PrePostE PN n Q E" + shows "PrePostE (case x of Some a \ PS a | None \ PN) (case x of Some a \ s a | None \ n) Q E" + using assms by (auto split: option.splits) + +lemma PrePostE_let[PrePostE_intro]: + assumes "PrePostE P (m y) Q E" + shows "PrePostE P (let x = y in m x) Q E" + using assms by auto + +lemma PrePostE_assert_expS[PrePostE_intro, intro]: + "PrePostE (if c then P () else Q (Failure m)) (assert_expS c m) P Q" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_failS[PrePost_intro, intro]: + "PrePostE (E (Failure msg)) (failS msg) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_chooseS[intro, PrePostE_intro]: + "PrePostE (\s. \x \ xs. Q x s) (chooseS xs) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_foreachS_Cons: + assumes "\s vars' s'. (Value vars', s') \ body x vars s \ PrePostE (Q vars') (foreachS xs vars' body) Q E" + and "PrePostE (Q vars) (body x vars) Q E" + shows "PrePostE (Q vars) (foreachS (x # xs) vars body) Q E" + using assms by fastforce + +lemma PrePostE_foreachS_invariant: + assumes "\x vars. x \ set xs \ PrePostE (Q vars) (body x vars) Q E" + shows "PrePostE (Q vars) (foreachS xs vars body) Q E" + using assms unfolding PrePostE_def + by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto + +end diff --git a/snapshots/isabelle/lib/sail/Prompt.thy b/snapshots/isabelle/lib/sail/Prompt.thy new file mode 100644 index 00000000..5792e575 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt.thy @@ -0,0 +1,150 @@ +chapter \Generated by Lem from ../../src/gen_lib/prompt.lem.\ + +theory "Prompt" + +imports + Main + "Lem_pervasives_extra" + "Sail_values" + "Prompt_monad" + "Prompt_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_values*) +(*open import Prompt_monad*) +(*open import {isabelle} `Prompt_monad_lemmas`*) + +(*val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*) + +(*val >> : forall 'rv 'b 'e. monad 'rv unit 'e -> monad 'rv 'b 'e -> monad 'rv 'b 'e*) + +(*val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +fun iter_aux :: " int \(int \ 'a \('rv,(unit),'e)monad)\ 'a list \('rv,(unit),'e)monad " where + " iter_aux i f (x # xs) = ( f i x \ iter_aux (i +( 1 :: int)) f xs )" +|" iter_aux i f ([]) = ( return () )" + + +(*val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +definition iteri :: "(int \ 'a \('rv,(unit),'e)monad)\ 'a list \('rv,(unit),'e)monad " where + " iteri f xs = ( iter_aux(( 0 :: int)) f xs )" + + +(*val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +definition iter :: "('a \('rv,(unit),'e)monad)\ 'a list \('rv,(unit),'e)monad " where + " iter f xs = ( iteri ( \x . + (case x of _ => \ x . f x )) xs )" + + +(*val foreachM : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +fun foreachM :: " 'a list \ 'vars \('a \ 'vars \('rv,'vars,'e)monad)\('rv,'vars,'e)monad " where + " foreachM ([]) vars body = ( return vars )" +|" foreachM (x # xs) vars body = ( + body x vars \ (\ vars . + foreachM xs vars body))" + + +(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) +definition and_boolM :: "('rv,(bool),'e)monad \('rv,(bool),'e)monad \('rv,(bool),'e)monad " where + " and_boolM l r = ( l \ (\ l . if l then r else return False))" + + +(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) +definition or_boolM :: "('rv,(bool),'e)monad \('rv,(bool),'e)monad \('rv,(bool),'e)monad " where + " or_boolM l r = ( l \ (\ l . if l then return True else r))" + + +(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*) +definition bool_of_bitU_fail :: " bitU \('rv,(bool),'e)monad " where + " bool_of_bitU_fail = ( \x . + (case x of + B0 => return False + | B1 => return True + | BU => Fail (''bool_of_bitU'') + ) )" + + +(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*) +definition bool_of_bitU_oracle :: " bitU \('rv,(bool),'e)monad " where + " bool_of_bitU_oracle = ( \x . + (case x of + B0 => return False + | B1 => return True + | BU => undefined_bool () + ) )" + + +(*val bools_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*) +definition bools_of_bits_oracle :: "(bitU)list \('rv,((bool)list),'e)monad " where + " bools_of_bits_oracle bits = ( + foreachM bits [] + (\ b bools . + bool_of_bitU_oracle b \ (\ b . + return (bools @ [b]))))" + + +(*val of_bits_oracle : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) +definition of_bits_oracle :: " 'a Bitvector_class \(bitU)list \('rv,'a,'e)monad " where + " of_bits_oracle dict_Sail_values_Bitvector_a bits = ( + bools_of_bits_oracle bits \ (\ bs . + return ((of_bools_method dict_Sail_values_Bitvector_a) bs)))" + + +(*val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) +definition of_bits_fail :: " 'a Bitvector_class \(bitU)list \('rv,'a,'e)monad " where + " of_bits_fail dict_Sail_values_Bitvector_a bits = ( maybe_fail (''of_bits'') ( + (of_bits_method dict_Sail_values_Bitvector_a) bits))" + + +(*val mword_oracle : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*) +definition mword_oracle :: " unit \('rv,(('a::len)Word.word),'e)monad " where + " mword_oracle _ = ( + bools_of_bits_oracle (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \ (\ bs . + return (Word.of_bl bs)))" + + +(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> + ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +function (sequential,domintros) whileM :: " 'vars \('vars \('rv,(bool),'e)monad)\('vars \('rv,'vars,'e)monad)\('rv,'vars,'e)monad " where + " whileM vars cond body = ( + cond vars \ (\ cond_val . + if cond_val then + body vars \ (\ vars . whileM vars cond body) + else return vars))" +by pat_completeness auto + + +(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> + ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +function (sequential,domintros) untilM :: " 'vars \('vars \('rv,(bool),'e)monad)\('vars \('rv,'vars,'e)monad)\('rv,'vars,'e)monad " where + " untilM vars cond body = ( + body vars \ (\ vars . + cond vars \ (\ cond_val . + if cond_val then return vars else untilM vars cond body)))" +by pat_completeness auto + + +(*let write_two_regs r1 r2 vec = + let is_inc = + let is_inc_r1 = is_inc_of_reg r1 in + let is_inc_r2 = is_inc_of_reg r2 in + let () = ensure (is_inc_r1 = is_inc_r2) + write_two_regs called with vectors of different direction in + is_inc_r1 in + + let (size_r1 : integer) = size_of_reg r1 in + let (start_vec : integer) = get_start vec in + let size_vec = length vec in + let r1_v = + if is_inc + then slice vec start_vec (size_r1 - start_vec - 1) + else slice vec start_vec (start_vec - size_r1 - 1) in + let r2_v = + if is_inc + then slice vec (size_r1 - start_vec) (size_vec - start_vec) + else slice vec (start_vec - size_r1) (start_vec - size_vec) in + write_reg r1 r1_v >> write_reg r2 r2_v*) +end diff --git a/snapshots/isabelle/lib/sail/Prompt_monad.thy b/snapshots/isabelle/lib/sail/Prompt_monad.thy new file mode 100644 index 00000000..e4aecfba --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt_monad.thy @@ -0,0 +1,267 @@ +chapter \Generated by Lem from ../../src/gen_lib/prompt_monad.lem.\ + +theory "Prompt_monad" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) + +type_synonym register_name =" string " +type_synonym address =" bitU list " + +datatype( 'regval, 'a, 'e) monad = + Done " 'a " + (* Read a number of bytes from memory, returned in little endian order *) + | Read_mem " read_kind " " address " " nat " " ( memory_byte list \ ('regval, 'a, 'e) monad)" + (* Read the tag of a memory address *) + | Read_tag " address " " (bitU \ ('regval, 'a, 'e) monad)" + (* Tell the system a write is imminent, at address lifted, of size nat *) + | Write_ea " write_kind " " address " " nat " " ('regval, 'a, 'e) monad " + (* Request the result of store-exclusive *) + | Excl_res " (bool \ ('regval, 'a, 'e) monad)" + (* Request to write memory at last signalled address. Memory value should be 8 + times the size given in ea signal, given in little endian order *) + | Write_memv " memory_byte list " " (bool \ ('regval, 'a, 'e) monad)" + (* Request to write the tag at given address. *) + | Write_tag " address " " bitU " " (bool \ ('regval, 'a, 'e) monad)" + (* Tell the system to dynamically recalculate dependency footprint *) + | Footprint " ('regval, 'a, 'e) monad " + (* Request a memory barrier *) + | Barrier " barrier_kind " " ('regval, 'a, 'e) monad " + (* Request to read register, will track dependency when mode.track_values *) + | Read_reg " register_name " " ('regval \ ('regval, 'a, 'e) monad)" + (* Request to write register *) + | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad " + | Undefined " (bool \ ('regval, 'a, 'e) monad)" + (* Print debugging or tracing information *) + | Print " string " " ('regval, 'a, 'e) monad " + (*Result of a failed assert with possible error message to report*) + | Fail " string " + (* Exception of type 'e *) + | Exception " 'e " + +(*val return : forall 'rv 'a 'e. 'a -> monad 'rv 'a 'e*) +definition return :: " 'a \('rv,'a,'e)monad " where + " return a = ( Done a )" + + +(*val bind : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*) +function (sequential,domintros) bind :: "('rv,'a,'e)monad \('a \('rv,'b,'e)monad)\('rv,'b,'e)monad " where + " bind (Done a) f = ( f a )" +|" bind (Read_mem rk a sz k) f = ( Read_mem rk a sz (\ v . bind (k v) f))" +|" bind (Read_tag a k) f = ( Read_tag a (\ v . bind (k v) f))" +|" bind (Write_memv descr k) f = ( Write_memv descr (\ v . bind (k v) f))" +|" bind (Write_tag a t k) f = ( Write_tag a t (\ v . bind (k v) f))" +|" bind (Read_reg descr k) f = ( Read_reg descr (\ v . bind (k v) f))" +|" bind (Excl_res k) f = ( Excl_res (\ v . bind (k v) f))" +|" bind (Undefined k) f = ( Undefined (\ v . bind (k v) f))" +|" bind (Write_ea wk a sz k) f = ( Write_ea wk a sz (bind k f))" +|" bind (Footprint k) f = ( Footprint (bind k f))" +|" bind (Barrier bk k) f = ( Barrier bk (bind k f))" +|" bind (Write_reg r v k) f = ( Write_reg r v (bind k f))" +|" bind (Print msg k) f = ( Print msg (bind k f))" +|" bind (Fail descr) f = ( Fail descr )" +|" bind (Exception e) f = ( Exception e )" +by pat_completeness auto + + +(*val exit : forall 'rv 'a 'e. unit -> monad 'rv 'a 'e*) +definition exit0 :: " unit \('rv,'a,'e)monad " where + " exit0 _ = ( Fail (''exit''))" + + +(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*) +definition undefined_bool :: " unit \('rv,(bool),'e)monad " where + " undefined_bool _ = ( Undefined return )" + + +(*val assert_exp : forall 'rv 'e. bool -> string -> monad 'rv unit 'e*) +definition assert_exp :: " bool \ string \('rv,(unit),'e)monad " where + " assert_exp exp msg = ( if exp then Done () else Fail msg )" + + +(*val throw : forall 'rv 'a 'e. 'e -> monad 'rv 'a 'e*) +definition throw :: " 'e \('rv,'a,'e)monad " where + " throw e = ( Exception e )" + + +(*val try_catch : forall 'rv 'a 'e1 'e2. monad 'rv 'a 'e1 -> ('e1 -> monad 'rv 'a 'e2) -> monad 'rv 'a 'e2*) +function (sequential,domintros) try_catch :: "('rv,'a,'e1)monad \('e1 \('rv,'a,'e2)monad)\('rv,'a,'e2)monad " where + " try_catch (Done a) h = ( Done a )" +|" try_catch (Read_mem rk a sz k) h = ( Read_mem rk a sz (\ v . try_catch (k v) h))" +|" try_catch (Read_tag a k) h = ( Read_tag a (\ v . try_catch (k v) h))" +|" try_catch (Write_memv descr k) h = ( Write_memv descr (\ v . try_catch (k v) h))" +|" try_catch (Write_tag a t k) h = ( Write_tag a t (\ v . try_catch (k v) h))" +|" try_catch (Read_reg descr k) h = ( Read_reg descr (\ v . try_catch (k v) h))" +|" try_catch (Excl_res k) h = ( Excl_res (\ v . try_catch (k v) h))" +|" try_catch (Undefined k) h = ( Undefined (\ v . try_catch (k v) h))" +|" try_catch (Write_ea wk a sz k) h = ( Write_ea wk a sz (try_catch k h))" +|" try_catch (Footprint k) h = ( Footprint (try_catch k h))" +|" try_catch (Barrier bk k) h = ( Barrier bk (try_catch k h))" +|" try_catch (Write_reg r v k) h = ( Write_reg r v (try_catch k h))" +|" try_catch (Print msg k) h = ( Print msg (try_catch k h))" +|" try_catch (Fail descr) h = ( Fail descr )" +|" try_catch (Exception e) h = ( h e )" +by pat_completeness auto + + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is either 'r 'e, where Right e + represents a proper exception and Left r an early return of value r. *) +type_synonym( 'rv, 'a, 'r, 'e) monadR =" ('rv, 'a, ( ('r, 'e)sum)) monad " + +(*val early_return : forall 'rv 'a 'r 'e. 'r -> monadR 'rv 'a 'r 'e*) +definition early_return :: " 'r \('rv,'a,(('r,'e)sum))monad " where + " early_return r = ( throw (Inl r))" + + +(*val catch_early_return : forall 'rv 'a 'e. monadR 'rv 'a 'a 'e -> monad 'rv 'a 'e*) +definition catch_early_return :: "('rv,'a,(('a,'e)sum))monad \('rv,'a,'e)monad " where + " catch_early_return m = ( + try_catch m + (\x . (case x of Inl a => return a | Inr e => throw e )))" + + +(* Lift to monad with early return by wrapping exceptions *) +(*val liftR : forall 'rv 'a 'r 'e. monad 'rv 'a 'e -> monadR 'rv 'a 'r 'e*) +definition liftR :: "('rv,'a,'e)monad \('rv,'a,(('r,'e)sum))monad " where + " liftR m = ( try_catch m (\ e . throw (Inr e)))" + + +(* Catch exceptions in the presence of early returns *) +(*val try_catchR : forall 'rv 'a 'r 'e1 'e2. monadR 'rv 'a 'r 'e1 -> ('e1 -> monadR 'rv 'a 'r 'e2) -> monadR 'rv 'a 'r 'e2*) +definition try_catchR :: "('rv,'a,(('r,'e1)sum))monad \('e1 \('rv,'a,(('r,'e2)sum))monad)\('rv,'a,(('r,'e2)sum))monad " where + " try_catchR m h = ( + try_catch m + (\x . (case x of Inl r => throw (Inl r) | Inr e => h e )))" + + +(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*) +definition maybe_fail :: " string \ 'a option \('rv,'a,'e)monad " where + " maybe_fail msg = ( \x . + (case x of Some a => return a | None => Fail msg ) )" + + +(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*) +definition read_mem_bytes :: " 'a Bitvector_class \ 'b Bitvector_class \ read_kind \ 'a \ int \('rv,((memory_byte)list),'e)monad " where + " read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( + Read_mem rk ((bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) return )" + + +(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*) +definition read_mem :: " 'a Bitvector_class \ 'b Bitvector_class \ read_kind \ 'a \ int \('rv,'b,'e)monad " where + " read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( + bind + (read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_a rk addr sz) + (\ bytes . + maybe_fail (''bits_of_mem_bytes'') ( + (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + + +(*val read_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bitU 'e*) +definition read_tag :: " 'a Bitvector_class \ 'a \('rv,(bitU),'e)monad " where + " read_tag dict_Sail_values_Bitvector_a addr = ( Read_tag ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) return )" + + +(*val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e*) +definition excl_result :: " unit \('rv,(bool),'e)monad " where + " excl_result _ = ( + (let k = (\ successful . (return successful)) in Excl_res k) )" + + +(*val write_mem_ea : forall 'rv 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> monad 'rv unit 'e*) +definition write_mem_ea :: " 'a Bitvector_class \ write_kind \ 'a \ int \('rv,(unit),'e)monad " where + " write_mem_ea dict_Sail_values_Bitvector_a wk addr sz = ( Write_ea wk ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))" + + +(*val write_mem_val : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bool 'e*) +definition write_mem_val :: " 'a Bitvector_class \ 'a \('rv,(bool),'e)monad " where + " write_mem_val dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail_values_Bitvector_a v of + Some v => Write_memv v return + | None => Fail (''write_mem_val'') +))" + + +(*val write_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> bitU -> monad 'rv bool 'e*) +definition write_tag :: " 'a Bitvector_class \ 'a \ bitU \('rv,(bool),'e)monad " where + " write_tag dict_Sail_values_Bitvector_a addr b = ( Write_tag ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) b return )" + + +(*val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e*) +definition read_reg :: "('s,'rv,'a)register_ref \('rv,'a,'e)monad " where + " read_reg reg = ( + (let k = (\ v . + (case (of_regval reg) v of + Some v => Done v + | None => Fail (''read_reg: unrecognised value'') + )) in Read_reg (name reg) k) )" + + +(* TODO +val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e +let read_reg_range reg i j = + read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j)) + +let read_reg_bit reg i = + read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v -> + return (extract_only_element v) + +let read_reg_field reg regfield = + read_reg_aux (external_reg_field_whole reg regfield) + +let read_reg_bitfield reg regfield = + read_reg_aux (external_reg_field_whole reg regfield) >>= fun v -> + return (extract_only_element v)*) + +definition reg_deref :: "('d,'c,'b)register_ref \('c,'b,'a)monad " where + " reg_deref = ( read_reg )" + + +(*val write_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> 'a -> monad 'rv unit 'e*) +definition write_reg :: "('s,'rv,'a)register_ref \ 'a \('rv,(unit),'e)monad " where + " write_reg reg v = ( Write_reg(name reg) ((regval_of reg) v) (Done () ))" + + +(* TODO +let write_reg reg v = + write_reg_aux (external_reg_whole reg) v +let write_reg_range reg i j v = + write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v +let write_reg_pos reg i v = + let iN = nat_of_int i in + write_reg_aux (external_reg_slice reg (iN,iN)) [v] +let write_reg_bit = write_reg_pos +let write_reg_field reg regfield v = + write_reg_aux (external_reg_field_whole reg regfield.field_name) v +let write_reg_field_bit reg regfield bit = + write_reg_aux (external_reg_field_whole reg regfield.field_name) + (Vector [bit] 0 (is_inc_of_reg reg)) +let write_reg_field_range reg regfield i j v = + write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v +let write_reg_field_pos reg regfield i v = + write_reg_field_range reg regfield i i [v] +let write_reg_field_bit = write_reg_field_pos*) + +(*val barrier : forall 'rv 'e. barrier_kind -> monad 'rv unit 'e*) +definition barrier :: " barrier_kind \('rv,(unit),'e)monad " where + " barrier bk = ( Barrier bk (Done () ))" + + +(*val footprint : forall 'rv 'e. unit -> monad 'rv unit 'e*) +definition footprint :: " unit \('rv,(unit),'e)monad " where + " footprint _ = ( Footprint (Done () ))" + +end diff --git a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy new file mode 100644 index 00000000..e883c2a0 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy @@ -0,0 +1,170 @@ +theory Prompt_monad_lemmas + imports + Prompt_monad + Sail_values_lemmas +begin + +notation bind (infixr "\" 54) + +abbreviation seq :: "('rv,unit,'e)monad \ ('rv,'b,'e)monad \('rv,'b,'e)monad" (infixr "\" 54) where + "m \ n \ m \ (\_. n)" + +lemma All_bind_dom: "bind_dom (m, f)" + by (induction m) (auto intro: bind.domintros) + +termination bind using All_bind_dom by auto +lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = bind.induct + +lemma bind_return[simp]: "bind (return a) f = f a" + by (auto simp: return_def) + +lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\x. bind (f x) g)" + by (induction m f arbitrary: g rule: bind.induct) auto + +lemma bind_assert_True[simp]: "bind (assert_exp True msg) f = f ()" + by (auto simp: assert_exp_def) + +lemma All_try_catch_dom: "try_catch_dom (m, h)" + by (induction m) (auto intro: try_catch.domintros) +termination try_catch using All_try_catch_dom by auto +lemmas try_catch_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = try_catch.induct + +datatype 'regval event = + (* Request to read memory *) + e_read_mem read_kind "bitU list" nat "memory_byte list" + | e_read_tag "bitU list" bitU + (* Write is imminent, at address lifted, of size nat *) + | e_write_ea write_kind "bitU list" nat + (* Request the result of store-exclusive *) + | e_excl_res bool + (* Request to write memory at last signalled address. Memory value should be 8 + times the size given in ea signal *) + | e_write_memv "memory_byte list" bool + | e_write_tag "bitU list" bitU bool + (* Tell the system to dynamically recalculate dependency footprint *) + | e_footprint + (* Request a memory barrier *) + | e_barrier " barrier_kind " + (* Request to read register *) + | e_read_reg string 'regval + (* Request to write register *) + | e_write_reg string 'regval + | e_undefined bool + | e_print string + +inductive_set T :: "(('rv, 'a, 'e) monad \ 'rv event \ ('rv, 'a, 'e) monad) set" where + Read_mem: "((Read_mem rk addr sz k), e_read_mem rk addr sz v, k v) \ T" +| Read_tag: "((Read_tag addr k), e_read_tag addr v, k v) \ T" +| Write_ea: "((Write_ea wk addr sz k), e_write_ea wk addr sz, k) \ T" +| Excl_res: "((Excl_res k), e_excl_res r, k r) \ T" +| Write_memv: "((Write_memv v k), e_write_memv v r, k r) \ T" +| Write_tag: "((Write_tag a v k), e_write_tag a v r, k r) \ T" +| Footprint: "((Footprint k), e_footprint, k) \ T" +| Barrier: "((Barrier bk k), e_barrier bk, k) \ T" +| Read_reg: "((Read_reg r k), e_read_reg r v, k v) \ T" +| Write_reg: "((Write_reg r v k), e_write_reg r v, k) \ T" +| Undefined : "((Undefined k), e_undefined v, k v) \ T" +| Print: "((Print msg k), e_print msg, k) \ T" + +inductive_set Traces :: "(('rv, 'a, 'e) monad \ 'rv event list \ ('rv, 'a, 'e) monad) set" where + Nil: "(s, [], s) \ Traces" +| Step: "\(s, e, s'') \ T; (s'', t, s') \ Traces\ \ (s, e # t, s') \ Traces" + +declare Traces.intros[intro] +declare T.intros[intro] + +declare prod.splits[split] + +lemmas Traces_ConsI = T.intros[THEN Step, rotated] + +inductive_cases Traces_NilE[elim]: "(s, [], s') \ Traces" +inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \ Traces" + +lemma Traces_cases: + fixes m :: "('rv, 'a, 'e) monad" + assumes Run: "(m, t, m') \ Traces" + obtains (Nil) a where "m = m'" and "t = []" + | (Read_mem) rk addr s k t' v where "m = Read_mem rk addr s k" and "t = e_read_mem rk addr s v # t'" and "(k v, t', m') \ Traces" + | (Read_tag) addr k t' v where "m = Read_tag addr k" and "t = e_read_tag addr v # t'" and "(k v, t', m') \ Traces" + | (Write_memv) val k t' v where "m = Write_memv val k" and "t = e_write_memv val v # t'" and "(k v, t', m') \ Traces" + | (Write_tag) a val k t' v where "m = Write_tag a val k" and "t = e_write_tag a val v # t'" and "(k v, t', m') \ Traces" + | (Barrier) bk k t' v where "m = Barrier bk k" and "t = e_barrier bk # t'" and "(k, t', m') \ Traces" + | (Read_reg) reg k t' v where "m = Read_reg reg k" and "t = e_read_reg reg v # t'" and "(k v, t', m') \ Traces" + | (Excl_res) k t' v where "m = Excl_res k" and "t = e_excl_res v # t'" and "(k v, t', m') \ Traces" + | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \ Traces" + | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \ Traces" + | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \ Traces" + | (Undefined) v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \ Traces" + | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \ Traces" +proof (use Run in \cases m t m' set: Traces\) + case Nil + then show ?thesis by (auto intro: that(1)) +next + case (Step e m'' t') + from \(m, e, m'') \ T\ and \t = e # t'\ and \(m'', t', m') \ Traces\ + show ?thesis by (cases m e m'' rule: T.cases; elim that; blast) +qed + +abbreviation Run :: "('rv, 'a, 'e) monad \ 'rv event list \ 'a \ bool" + where "Run s t a \ (s, t, Done a) \ Traces" + +lemma Run_appendI: + assumes "(s, t1, s') \ Traces" + and "Run s' t2 a" + shows "Run s (t1 @ t2) a" +proof (use assms in \induction t1 arbitrary: s\) + case (Cons e t1) + then show ?case by (elim Traces_ConsE) auto +qed auto + +lemma bind_DoneE: + assumes "bind m f = Done a" + obtains a' where "m = Done a'" and "f a' = Done a" + using assms by (auto elim: bind.elims) + +lemma bind_T_cases: + assumes "(bind m f, e, s') \ T" + obtains (Done) a where "m = Done a" + | (Bind) m' where "s' = bind m' f" and "(m, e, m') \ T" + using assms by (cases; blast elim: bind.elims) + +lemma Run_bindE: + fixes m :: "('rv, 'b, 'e) monad" and a :: 'a + assumes "Run (bind m f) t a" + obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a" +proof (use assms in \induction "bind m f" t "Done a :: ('rv, 'a, 'e) monad" arbitrary: m rule: Traces.induct\) + case Nil + obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE) + then show ?case by (intro Nil(2)) auto +next + case (Step e s'' t m) + show thesis using Step(1) + proof (cases rule: bind_T_cases) + case (Done am) + then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto + next + case (Bind m') + show ?thesis proof (rule Step(3)[OF Bind(1)]) + fix tm tf am + assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a" + then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto + qed + qed +qed + +lemma Run_DoneE: + assumes "Run (Done a) t a'" + obtains "t = []" and "a' = a" + using assms by (auto elim: Traces.cases T.cases) + +lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \ t = [] \ a' = a" + by (auto elim: Run_DoneE) + +lemma bind_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\t a. Run m2 t a \ f1 a = f2 a" + shows "bind m1 f1 = bind m2 f2" + unfolding m using f + by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast) + +end diff --git a/snapshots/isabelle/lib/sail/ROOT b/snapshots/isabelle/lib/sail/ROOT new file mode 100644 index 00000000..3189f216 --- /dev/null +++ b/snapshots/isabelle/lib/sail/ROOT @@ -0,0 +1,11 @@ +session "Sail" = "LEM" + + options [document = false] + sessions + "HOL-Eisbach" + theories + Sail_values_lemmas + Prompt + State_lemmas + Sail_operators_mwords_lemmas + Sail_operators_bitlists + Hoare diff --git a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy new file mode 100644 index 00000000..088ff4a8 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy @@ -0,0 +1,494 @@ +chapter \Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.\ + +theory "Sail_instr_kinds" + +imports + Main + "Lem_pervasives_extra" + +begin + +(*========================================================================*) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(*open import Pervasives_extra*) + + +record 'a EnumerationType_class= + + toNat_method ::" 'a \ nat " + + + + +(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*) +definition enumeration_typeCompare :: " 'a EnumerationType_class \ 'a \ 'a \ ordering " where + " enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a e1 e2 = ( + (genericCompare (op<) (op=) ( + (toNat_method dict_Sail_instr_kinds_EnumerationType_a) e1) ((toNat_method dict_Sail_instr_kinds_EnumerationType_a) e2)))" + + + +definition instance_Basic_classes_Ord_var_dict :: " 'a EnumerationType_class \ 'a Ord_class " where + " instance_Basic_classes_Ord_var_dict dict_Sail_instr_kinds_EnumerationType_a = ((| + + compare_method = + (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a), + + isLess_method = (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT), + + isLessEqual_method = (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) \ GT), + + isGreater_method = (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT), + + isGreaterEqual_method = (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) \ LT)|) )" + + + +(* Data structures for building up instructions *) + +(* careful: changes in the read/write/barrier kinds have to be + reflected in deep_shallow_convert *) +datatype read_kind = + (* common reads *) + Read_plain + (* Power reads *) + | Read_reserve + (* AArch64 reads *) + | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream + (* RISC-V reads *) + | Read_RISCV_acquire | Read_RISCV_strong_acquire + | Read_RISCV_reserved | Read_RISCV_reserved_acquire + | Read_RISCV_reserved_strong_acquire + (* x86 reads *) + | Read_X86_locked (* the read part of a lock'd instruction (rmw) *) + +definition instance_Show_Show_Sail_instr_kinds_read_kind_dict :: "(read_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_read_kind_dict = ((| + + show_method = (\x . + (case x of + Read_plain => (''Read_plain'') + | Read_reserve => (''Read_reserve'') + | Read_acquire => (''Read_acquire'') + | Read_exclusive => (''Read_exclusive'') + | Read_exclusive_acquire => (''Read_exclusive_acquire'') + | Read_stream => (''Read_stream'') + | Read_RISCV_acquire => (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => (''Read_X86_locked'') + ))|) )" + + +datatype write_kind = + (* common writes *) + Write_plain + (* Power writes *) + | Write_conditional + (* AArch64 writes *) + | Write_release | Write_exclusive | Write_exclusive_release + (* RISC-V *) + | Write_RISCV_release | Write_RISCV_strong_release + | Write_RISCV_conditional | Write_RISCV_conditional_release + | Write_RISCV_conditional_strong_release + (* x86 writes *) + | Write_X86_locked (* the write part of a lock'd instruction (rmw) *) + +definition instance_Show_Show_Sail_instr_kinds_write_kind_dict :: "(write_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_write_kind_dict = ((| + + show_method = (\x . + (case x of + Write_plain => (''Write_plain'') + | Write_conditional => (''Write_conditional'') + | Write_release => (''Write_release'') + | Write_exclusive => (''Write_exclusive'') + | Write_exclusive_release => (''Write_exclusive_release'') + | Write_RISCV_release => (''Write_RISCV_release'') + | Write_RISCV_strong_release => (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => (''Write_X86_locked'') + ))|) )" + + +datatype barrier_kind = + (* Power barriers *) + Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync + (* AArch64 barriers *) + | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB + | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB + | Barrier_TM_COMMIT + (* MIPS barriers *) + | Barrier_MIPS_SYNC + (* RISC-V barriers *) + | Barrier_RISCV_rw_rw + | Barrier_RISCV_r_rw + | Barrier_RISCV_r_r + | Barrier_RISCV_rw_w + | Barrier_RISCV_w_w + | Barrier_RISCV_i + (* X86 *) + | Barrier_x86_MFENCE + + +definition instance_Show_Show_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_barrier_kind_dict = ((| + + show_method = (\x . + (case x of + Barrier_Sync => (''Barrier_Sync'') + | Barrier_LwSync => (''Barrier_LwSync'') + | Barrier_Eieio => (''Barrier_Eieio'') + | Barrier_Isync => (''Barrier_Isync'') + | Barrier_DMB => (''Barrier_DMB'') + | Barrier_DMB_ST => (''Barrier_DMB_ST'') + | Barrier_DMB_LD => (''Barrier_DMB_LD'') + | Barrier_DSB => (''Barrier_DSB'') + | Barrier_DSB_ST => (''Barrier_DSB_ST'') + | Barrier_DSB_LD => (''Barrier_DSB_LD'') + | Barrier_ISB => (''Barrier_ISB'') + | Barrier_TM_COMMIT => (''Barrier_TM_COMMIT'') + | Barrier_MIPS_SYNC => (''Barrier_MIPS_SYNC'') + | Barrier_RISCV_rw_rw => (''Barrier_RISCV_rw_rw'') + | Barrier_RISCV_r_rw => (''Barrier_RISCV_r_rw'') + | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'') + | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'') + | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'') + | Barrier_RISCV_i => (''Barrier_RISCV_i'') + | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'') + ))|) )" + + +datatype trans_kind = + (* AArch64 *) + Transaction_start | Transaction_commit | Transaction_abort + +definition instance_Show_Show_Sail_instr_kinds_trans_kind_dict :: "(trans_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_trans_kind_dict = ((| + + show_method = (\x . + (case x of + Transaction_start => (''Transaction_start'') + | Transaction_commit => (''Transaction_commit'') + | Transaction_abort => (''Transaction_abort'') + ))|) )" + + +datatype instruction_kind = + IK_barrier " barrier_kind " + | IK_mem_read " read_kind " + | IK_mem_write " write_kind " + | IK_mem_rmw " (read_kind * write_kind)" + | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + indirect/computed-branch (single nia of kind NIA_indirect_address) + and branch/jump (single nia of kind NIA_concrete_address) *) + | IK_trans " trans_kind " + | IK_simple + + +definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instruction_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_instruction_kind_dict = ((| + + show_method = (\x . + (case x of + IK_barrier barrier_kind => (''IK_barrier '') @ + (((\x . (case x of + Barrier_Sync => + (''Barrier_Sync'') + | Barrier_LwSync => + (''Barrier_LwSync'') + | Barrier_Eieio => + (''Barrier_Eieio'') + | Barrier_Isync => + (''Barrier_Isync'') + | Barrier_DMB => + (''Barrier_DMB'') + | Barrier_DMB_ST => + (''Barrier_DMB_ST'') + | Barrier_DMB_LD => + (''Barrier_DMB_LD'') + | Barrier_DSB => + (''Barrier_DSB'') + | Barrier_DSB_ST => + (''Barrier_DSB_ST'') + | Barrier_DSB_LD => + (''Barrier_DSB_LD'') + | Barrier_ISB => + (''Barrier_ISB'') + | Barrier_TM_COMMIT => + (''Barrier_TM_COMMIT'') + | Barrier_MIPS_SYNC => + (''Barrier_MIPS_SYNC'') + | Barrier_RISCV_rw_rw => + (''Barrier_RISCV_rw_rw'') + | Barrier_RISCV_r_rw => + (''Barrier_RISCV_r_rw'') + | Barrier_RISCV_r_r => + (''Barrier_RISCV_r_r'') + | Barrier_RISCV_rw_w => + (''Barrier_RISCV_rw_w'') + | Barrier_RISCV_w_w => + (''Barrier_RISCV_w_w'') + | Barrier_RISCV_i => + (''Barrier_RISCV_i'') + | Barrier_x86_MFENCE => + (''Barrier_x86_MFENCE'') + )) barrier_kind)) + | IK_mem_read read_kind => (''IK_mem_read '') @ + (((\x . (case x of + Read_plain => + (''Read_plain'') + | Read_reserve => + (''Read_reserve'') + | Read_acquire => + (''Read_acquire'') + | Read_exclusive => + (''Read_exclusive'') + | Read_exclusive_acquire => + (''Read_exclusive_acquire'') + | Read_stream => + (''Read_stream'') + | Read_RISCV_acquire => + (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => + (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => + (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => + (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => + (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => + (''Read_X86_locked'') + )) read_kind)) + | IK_mem_write write_kind => (''IK_mem_write '') @ + (((\x . (case x of + Write_plain => + (''Write_plain'') + | Write_conditional => + (''Write_conditional'') + | Write_release => + (''Write_release'') + | Write_exclusive => + (''Write_exclusive'') + | Write_exclusive_release => + (''Write_exclusive_release'') + | Write_RISCV_release => + (''Write_RISCV_release'') + | Write_RISCV_strong_release => + (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => + (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => + (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => + (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => + (''Write_X86_locked'') + )) write_kind)) + | IK_mem_rmw (r, w) => (''IK_mem_rmw '') @ + ((((\x . (case x of + Read_plain => (''Read_plain'') + | Read_reserve => (''Read_reserve'') + | Read_acquire => (''Read_acquire'') + | Read_exclusive => + (''Read_exclusive'') + | Read_exclusive_acquire => + (''Read_exclusive_acquire'') + | Read_stream => (''Read_stream'') + | Read_RISCV_acquire => + (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => + (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => + (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => + (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => + (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => + (''Read_X86_locked'') + )) r)) @ + (('' '') @ + (((\x . (case x of + Write_plain => + (''Write_plain'') + | Write_conditional => + (''Write_conditional'') + | Write_release => + (''Write_release'') + | Write_exclusive => + (''Write_exclusive'') + | Write_exclusive_release => + (''Write_exclusive_release'') + | Write_RISCV_release => + (''Write_RISCV_release'') + | Write_RISCV_strong_release => + (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => + (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => + (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => + (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => + (''Write_X86_locked'') + )) w)))) + | IK_branch => (''IK_branch'') + | IK_trans trans_kind => (''IK_trans '') @ + (((\x . (case x of + Transaction_start => + (''Transaction_start'') + | Transaction_commit => + (''Transaction_commit'') + | Transaction_abort => + (''Transaction_abort'') + )) trans_kind)) + | IK_simple => (''IK_simple'') + ))|) )" + + + +definition read_is_exclusive :: " read_kind \ bool " where + " read_is_exclusive = ( \x . + (case x of + Read_plain => False + | Read_reserve => True + | Read_acquire => False + | Read_exclusive => True + | Read_exclusive_acquire => True + | Read_stream => False + | Read_RISCV_acquire => False + | Read_RISCV_strong_acquire => False + | Read_RISCV_reserved => True + | Read_RISCV_reserved_acquire => True + | Read_RISCV_reserved_strong_acquire => True + | Read_X86_locked => True + ) )" + + + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict :: "(read_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict = ((| + + toNat_method = (\x . + (case x of + Read_plain =>( 0 :: nat) + | Read_reserve =>( 1 :: nat) + | Read_acquire =>( 2 :: nat) + | Read_exclusive =>( 3 :: nat) + | Read_exclusive_acquire =>( 4 :: nat) + | Read_stream =>( 5 :: nat) + | Read_RISCV_acquire =>( 6 :: nat) + | Read_RISCV_strong_acquire =>( 7 :: nat) + | Read_RISCV_reserved =>( 8 :: nat) + | Read_RISCV_reserved_acquire =>( 9 :: nat) + | Read_RISCV_reserved_strong_acquire =>( 10 :: nat) + | Read_X86_locked =>( 11 :: nat) + ))|) )" + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict :: "(write_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict = ((| + + toNat_method = (\x . + (case x of + Write_plain =>( 0 :: nat) + | Write_conditional =>( 1 :: nat) + | Write_release =>( 2 :: nat) + | Write_exclusive =>( 3 :: nat) + | Write_exclusive_release =>( 4 :: nat) + | Write_RISCV_release =>( 5 :: nat) + | Write_RISCV_strong_release =>( 6 :: nat) + | Write_RISCV_conditional =>( 7 :: nat) + | Write_RISCV_conditional_release =>( 8 :: nat) + | Write_RISCV_conditional_strong_release =>( 9 :: nat) + | Write_X86_locked =>( 10 :: nat) + ))|) )" + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict = ((| + + toNat_method = (\x . + (case x of + Barrier_Sync =>( 0 :: nat) + | Barrier_LwSync =>( 1 :: nat) + | Barrier_Eieio =>( 2 :: nat) + | Barrier_Isync =>( 3 :: nat) + | Barrier_DMB =>( 4 :: nat) + | Barrier_DMB_ST =>( 5 :: nat) + | Barrier_DMB_LD =>( 6 :: nat) + | Barrier_DSB =>( 7 :: nat) + | Barrier_DSB_ST =>( 8 :: nat) + | Barrier_DSB_LD =>( 9 :: nat) + | Barrier_ISB =>( 10 :: nat) + | Barrier_TM_COMMIT =>( 11 :: nat) + | Barrier_MIPS_SYNC =>( 12 :: nat) + | Barrier_RISCV_rw_rw =>( 13 :: nat) + | Barrier_RISCV_r_rw =>( 14 :: nat) + | Barrier_RISCV_r_r =>( 15 :: nat) + | Barrier_RISCV_rw_w =>( 16 :: nat) + | Barrier_RISCV_w_w =>( 17 :: nat) + | Barrier_RISCV_i =>( 18 :: nat) + | Barrier_x86_MFENCE =>( 19 :: nat) + ))|) )" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators.thy b/snapshots/isabelle/lib/sail/Sail_operators.thy new file mode 100644 index 00000000..00b32a85 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators.thy @@ -0,0 +1,326 @@ +chapter \Generated by Lem from ../../src/gen_lib/sail_operators.lem.\ + +theory "Sail_operators" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) + +(*** Bit vector operations *) + +(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*) +definition concat_bv :: " 'a Bitvector_class \ 'b Bitvector_class \ 'a \ 'b \(bitU)list " where + " concat_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r = ( ( + (bits_of_method dict_Sail_values_Bitvector_a) l @(bits_of_method dict_Sail_values_Bitvector_b) r))" + + +(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*) +definition cons_bv :: " 'a Bitvector_class \ bitU \ 'a \(bitU)list " where + " cons_bv dict_Sail_values_Bitvector_a b v = ( b # + (bits_of_method dict_Sail_values_Bitvector_a) v )" + + +(*val cast_unit_bv : bitU -> list bitU*) +definition cast_unit_bv :: " bitU \(bitU)list " where + " cast_unit_bv b = ( [b])" + + +(*val bv_of_bit : integer -> bitU -> list bitU*) +definition bv_of_bit :: " int \ bitU \(bitU)list " where + " bv_of_bit len b = ( extz_bits len [b])" + + +definition most_significant :: " 'a Bitvector_class \ 'a \ bitU " where + " most_significant dict_Sail_values_Bitvector_a v = ( (case + (bits_of_method dict_Sail_values_Bitvector_a) v of + b # _ => b + | _ => B0 (* Treat empty bitvector as all zeros *) + ))" + + +definition get_max_representable_in :: " bool \ int \ int " where + " get_max_representable_in sign (n :: int) = ( + if (n =( 64 :: int)) then (case sign of True => max_64 | False => max_64u ) + else if (n=( 32 :: int)) then (case sign of True => max_32 | False => max_32u ) + else if (n=( 8 :: int)) then max_8 + else if (n=( 5 :: int)) then max_5 + else (case sign of True => (( 2 :: int))^ ((nat (abs ( n))) -( 1 :: nat)) + | False => (( 2 :: int))^ (nat (abs ( n))) + ))" + + +definition get_min_representable_in :: " 'a \ int \ int " where + " get_min_representable_in _ (n :: int) = ( + if n =( 64 :: int) then min_64 + else if n =( 32 :: int) then min_32 + else if n =( 8 :: int) then min_8 + else if n =( 5 :: int) then min_5 + else( 0 :: int) - ((( 2 :: int))^ (nat (abs ( n)))))" + + +(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) +definition arith_op_bv_int :: " 'a Bitvector_class \(int \ int \ int)\ bool \ 'a \ int \ 'a " where + " arith_op_bv_int dict_Sail_values_Bitvector_a op1 sign l r = ( + (let r' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l r'))" + + +(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) +definition arith_op_int_bv :: " 'a Bitvector_class \(int \ int \ int)\ bool \ int \ 'a \ 'a " where + " arith_op_int_bv dict_Sail_values_Bitvector_a op1 sign l r = ( + (let l' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) r) l) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l' r))" + + +definition arith_op_bv_bool :: " 'a Bitvector_class \(int \ int \ int)\ bool \ 'a \ bool \ 'a " where + " arith_op_bv_bool dict_Sail_values_Bitvector_a op1 sign l r = ( arith_op_bv_int + dict_Sail_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))" + +definition arith_op_bv_bit :: " 'a Bitvector_class \(int \ int \ int)\ bool \ 'a \ bitU \ 'a option " where + " arith_op_bv_bit dict_Sail_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool + dict_Sail_values_Bitvector_a op1 sign l) (bool_of_bitU r))" + + +(* TODO (or just omit and define it per spec if needed) +val arith_op_overflow_bv : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU) +let arith_op_overflow_bv op sign size l r = + let len = length l in + let act_size = len * size in + match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with + | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) -> + let n = op l_sign r_sign in + let n_unsign = op l_unsign r_unsign in + let correct_size = of_int act_size n in + let one_more_size_u = bits_of_int (act_size + 1) n_unsign in + let overflow = + if n <= get_max_representable_in sign len && + n >= get_min_representable_in sign len + then B0 else B1 in + let c_out = most_significant one_more_size_u in + (correct_size,overflow,c_out) + | (_, _, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv = arith_op_overflow_bv integerAdd false 1 +let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1 +let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1 +let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1 +let mult_overflow_bv = arith_op_overflow_bv integerMult false 2 +let mults_overflow_bv = arith_op_overflow_bv integerMult true 2 + +val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU) +let arith_op_overflow_bv_bit op sign size l r_bit = + let act_size = length l * size in + match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with + | (Just l', Just l_u, false) -> + let (n, nu, changed) = match r_bit with + | B1 -> (op l' 1, op l_u 1, true) + | B0 -> (l', l_u, false) + | BU -> (* unreachable due to check above *) + failwith arith_op_overflow_bv_bit applied to undefined bit + end in + let correct_size = of_int act_size n in + let one_larger = bits_of_int (act_size + 1) nu in + let overflow = + if changed + then + if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size + then B0 else B1 + else B0 in + (correct_size, overflow, most_significant one_larger) + | (_, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1 +let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1 +let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1 +let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*) + +datatype shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot + +definition invert_shift :: " shift \ shift " where + " invert_shift = ( \x . + (case x of + LL_shift => RR_shift + | RR_shift => LL_shift + | RR_shift_arith => LL_shift + | LL_rot => RR_rot + | RR_rot => LL_rot + ) )" + + +(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*) +definition shift_op_bv :: " 'a Bitvector_class \ shift \ 'a \ int \(bitU)list " where + " shift_op_bv dict_Sail_values_Bitvector_a op1 v n = ( + (let v = ((bits_of_method dict_Sail_values_Bitvector_a) v) in + if n =( 0 :: int) then v else + (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in + (case op1 of + LL_shift => + subrange_list True v n (int (List.length v) -( 1 :: int)) @ repeat [B0] n + | RR_shift => + repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) + | RR_shift_arith => + repeat [most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) + | LL_rot => + subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int)) + | RR_rot => + subrange_list False v(( 0 :: int)) (n -( 1 :: int)) @ subrange_list False v n (int (List.length v) -( 1 :: int)) + ))))" + + +definition shiftl_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " shiftl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_shift )" + (*<<*) +definition shiftr_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a RR_shift )" + (*>>*) +definition arith_shiftr_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " arith_shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a RR_shift_arith )" + +definition rotl_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " rotl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_rot )" + (*<<<*) +definition rotr_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " rotr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_rot )" + (*>>>*) + +definition shiftl_mword :: "('a::len)Word.word \ int \('a::len)Word.word " where + " shiftl_mword w n = ( w << (nat_of_int n))" + +definition shiftr_mword :: "('a::len)Word.word \ int \('a::len)Word.word " where + " shiftr_mword w n = ( w >> (nat_of_int n))" + +definition arith_shiftr_mword :: "('a::len)Word.word \ int \('a::len)Word.word " where + " arith_shiftr_mword w n = ( w >>> (nat_of_int n))" + +definition rotl_mword :: "('a::len)Word.word \ int \('a::len)Word.word " where + " rotl_mword w n = ( Word.word_rotl (nat_of_int n) w )" + +definition rotr_mword :: "('a::len)Word.word \ int \('a::len)Word.word " where + " rotr_mword w n = ( Word.word_rotr (nat_of_int n) w )" + + +fun arith_op_no0 :: "(int \ int \ int)\ int \ int \(int)option " where + " arith_op_no0 (op1 :: int \ int \ int) l r = ( + if r =( 0 :: int) + then None + else Some (op1 l r))" + + +(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*) +definition arith_op_bv_no0 :: " 'a Bitvector_class \ 'b Bitvector_class \(int \ int \ int)\ bool \ int \ 'a \ 'a \ 'b option " where + " arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( + Option.bind (int_of_bv + dict_Sail_values_Bitvector_a sign l) (\ l' . + Option.bind (int_of_bv + dict_Sail_values_Bitvector_a sign r) (\ r' . + if r' =( 0 :: int) then None else Some ( + (of_int_method dict_Sail_values_Bitvector_b) ((length_method dict_Sail_values_Bitvector_a) l * size1) (op1 l' r')))))" + + +definition mod_bv :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ 'b \ 'a option " where + " mod_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + +definition quot_bv :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ 'b \ 'a option " where + " quot_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + +definition quots_bv :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ 'b \ 'a option " where + " quots_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot True(( 1 :: int)))" + + +definition mod_mword :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " mod_mword = ( (op mod))" + +definition quot_mword :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " quot_mword = ( (op div))" + +definition quots_mword :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " quots_mword = ( Lem_machine_word.signedDivide )" + + +definition arith_op_bv_int_no0 :: " 'a Bitvector_class \ 'b Bitvector_class \(int \ int \ int)\ bool \ int \ 'a \ int \ 'b option " where + " arith_op_bv_int_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( + arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r))" + + +definition quot_bv_int :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ int \ 'a option " where + " quot_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + +definition mod_bv_int :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ int \ 'a option " where + " mod_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + + +definition mod_mword_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " mod_mword_int l r = ( l mod (Word.word_of_int r))" + +definition quot_mword_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " quot_mword_int l r = ( l div (Word.word_of_int r))" + +definition quots_mword_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " quots_mword_int l r = ( Lem_machine_word.signedDivide l (Word.word_of_int r))" + + +definition replicate_bits_bv :: " 'a Bitvector_class \ 'a \ int \(bitU)list " where + " replicate_bits_bv dict_Sail_values_Bitvector_a v count1 = ( repeat ( + (bits_of_method dict_Sail_values_Bitvector_a) v) count1 )" + +definition duplicate_bit_bv :: " 'a BitU_class \ 'a \ int \(bitU)list " where + " duplicate_bit_bv dict_Sail_values_BitU_a bit len = ( replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len )" + + +(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +definition eq_bv :: " 'a Bitvector_class \ 'a \ 'a \ bool " where + " eq_bv dict_Sail_values_Bitvector_a l r = ( ( + (bits_of_method dict_Sail_values_Bitvector_a) l =(bits_of_method dict_Sail_values_Bitvector_a) r))" + + +(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +definition neq_bv :: " 'a Bitvector_class \ 'a \ 'a \ bool " where + " neq_bv dict_Sail_values_Bitvector_a l r = ( \ (eq_bv + dict_Sail_values_Bitvector_a l r))" + + +(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +definition get_slice_int_bv :: " 'a Bitvector_class \ int \ int \ int \ 'a " where + " get_slice_int_bv dict_Sail_values_Bitvector_a len n lo = ( + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + (of_bools_method dict_Sail_values_Bitvector_a) (subrange_list False bs hi lo))))" + + +(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*) +definition set_slice_int_bv :: " 'a Bitvector_class \ int \ int \ int \ 'a \ int " where + " set_slice_int_bv dict_Sail_values_Bitvector_a len n lo v = ( + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bits_of_int (hi +( 1 :: int)) n) in + maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo ( + (bits_of_method dict_Sail_values_Bitvector_a) v))))))" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy new file mode 100644 index 00000000..d3d886ed --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy @@ -0,0 +1,773 @@ +chapter \Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.\ + +theory "Sail_operators_bitlists" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + "Sail_operators" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(* Specialisation of operators to bit lists *) + +(*val uint_maybe : list bitU -> maybe integer*) +definition uint_maybe :: "(bitU)list \(int)option " where + " uint_maybe v = ( unsigned_of_bits (List.map (\ b. b) v))" + +definition uint_fail :: " 'a Bitvector_class \ 'a \('c,(int),'b)monad " where + " uint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''uint'') ( + (unsigned_method dict_Sail_values_Bitvector_a) v))" + +definition uint_oracle :: "(bitU)list \('b,(int),'a)monad " where + " uint_oracle v = ( + bools_of_bits_oracle v \ (\ bs . + return (int_of_bools False bs)))" + +definition uint :: "(bitU)list \ int " where + " uint v = ( maybe_failwith (uint_maybe v))" + + +(*val sint_maybe : list bitU -> maybe integer*) +definition sint_maybe :: "(bitU)list \(int)option " where + " sint_maybe v = ( signed_of_bits (List.map (\ b. b) v))" + +definition sint_fail :: " 'a Bitvector_class \ 'a \('c,(int),'b)monad " where + " sint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''sint'') ( + (signed_method dict_Sail_values_Bitvector_a) v))" + +definition sint_oracle :: "(bitU)list \('b,(int),'a)monad " where + " sint_oracle v = ( + bools_of_bits_oracle v \ (\ bs . + return (int_of_bools True bs)))" + +definition sint :: "(bitU)list \ int " where + " sint v = ( maybe_failwith (sint_maybe v))" + + +(*val extz_vec : integer -> list bitU -> list bitU*) +definition extz_vec :: " int \(bitU)list \(bitU)list " where + " extz_vec = ( + extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val exts_vec : integer -> list bitU -> list bitU*) +definition exts_vec :: " int \(bitU)list \(bitU)list " where + " exts_vec = ( + exts_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val zero_extend : list bitU -> integer -> list bitU*) +definition zero_extend :: "(bitU)list \ int \(bitU)list " where + " zero_extend bits len = ( extz_bits len bits )" + + +(*val sign_extend : list bitU -> integer -> list bitU*) +definition sign_extend :: "(bitU)list \ int \(bitU)list " where + " sign_extend bits len = ( exts_bits len bits )" + + +(*val zeros : integer -> list bitU*) +definition zeros :: " int \(bitU)list " where + " zeros len = ( repeat [B0] len )" + + +(*val vector_truncate : list bitU -> integer -> list bitU*) +definition vector_truncate :: "(bitU)list \ int \(bitU)list " where + " vector_truncate bs len = ( extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) len bs )" + + +(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) +(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_failwith : list bitU -> list bitU*) +(*val vec_of_bits : list bitU -> list bitU*) + +(*val access_vec_inc : list bitU -> integer -> bitU*) +definition access_vec_inc :: "(bitU)list \ int \ bitU " where + " access_vec_inc = ( + access_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val access_vec_dec : list bitU -> integer -> bitU*) +definition access_vec_dec :: "(bitU)list \ int \ bitU " where + " access_vec_dec = ( + access_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) +definition update_vec_inc :: "(bitU)list \ int \ bitU \(bitU)list " where + " update_vec_inc = ( + update_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition update_vec_inc_maybe :: "(bitU)list \ int \ bitU \((bitU)list)option " where + " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))" + +definition update_vec_inc_fail :: "(bitU)list \ int \ bitU \('b,((bitU)list),'a)monad " where + " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))" + +definition update_vec_inc_oracle :: "(bitU)list \ int \ bitU \('b,((bitU)list),'a)monad " where + " update_vec_inc_oracle v i b = ( return (update_vec_inc v i b))" + + +(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) +definition update_vec_dec :: "(bitU)list \ int \ bitU \(bitU)list " where + " update_vec_dec = ( + update_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition update_vec_dec_maybe :: "(bitU)list \ int \ bitU \((bitU)list)option " where + " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))" + +definition update_vec_dec_fail :: "(bitU)list \ int \ bitU \('b,((bitU)list),'a)monad " where + " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))" + +definition update_vec_dec_oracle :: "(bitU)list \ int \ bitU \('b,((bitU)list),'a)monad " where + " update_vec_dec_oracle v i b = ( return (update_vec_dec v i b))" + + +(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) +definition subrange_vec_inc :: "(bitU)list \ int \ int \(bitU)list " where + " subrange_vec_inc = ( + subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) +definition subrange_vec_dec :: "(bitU)list \ int \ int \(bitU)list " where + " subrange_vec_dec = ( + subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) +definition update_subrange_vec_inc :: "(bitU)list \ int \ int \(bitU)list \(bitU)list " where + " update_subrange_vec_inc = ( + update_subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) +definition update_subrange_vec_dec :: "(bitU)list \ int \ int \(bitU)list \(bitU)list " where + " update_subrange_vec_dec = ( + update_subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val concat_vec : list bitU -> list bitU -> list bitU*) +definition concat_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " concat_vec = ( + concat_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val cons_vec : bitU -> list bitU -> list bitU*) +definition cons_vec :: " bitU \(bitU)list \(bitU)list " where + " cons_vec = ( + cons_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition cons_vec_maybe :: " bitU \(bitU)list \((bitU)list)option " where + " cons_vec_maybe b v = ( Some (cons_vec b v))" + +definition cons_vec_fail :: " bitU \(bitU)list \('b,((bitU)list),'a)monad " where + " cons_vec_fail b v = ( return (cons_vec b v))" + +definition cons_vec_oracle :: " bitU \(bitU)list \('b,((bitU)list),'a)monad " where + " cons_vec_oracle b v = ( return (cons_vec b v))" + + +(*val cast_unit_vec : bitU -> list bitU*) +definition cast_unit_vec :: " bitU \(bitU)list " where + " cast_unit_vec = ( cast_unit_bv )" + +definition cast_unit_vec_maybe :: " bitU \((bitU)list)option " where + " cast_unit_vec_maybe b = ( Some (cast_unit_vec b))" + +definition cast_unit_vec_fail :: " bitU \('b,((bitU)list),'a)monad " where + " cast_unit_vec_fail b = ( return (cast_unit_vec b))" + +definition cast_unit_vec_oracle :: " bitU \('b,((bitU)list),'a)monad " where + " cast_unit_vec_oracle b = ( return (cast_unit_vec b))" + + +(*val vec_of_bit : integer -> bitU -> list bitU*) +definition vec_of_bit :: " int \ bitU \(bitU)list " where + " vec_of_bit = ( bv_of_bit )" + +definition vec_of_bit_maybe :: " int \ bitU \((bitU)list)option " where + " vec_of_bit_maybe len b = ( Some (vec_of_bit len b))" + +definition vec_of_bit_fail :: " int \ bitU \('b,((bitU)list),'a)monad " where + " vec_of_bit_fail len b = ( return (vec_of_bit len b))" + +definition vec_of_bit_oracle :: " int \ bitU \('b,((bitU)list),'a)monad " where + " vec_of_bit_oracle len b = ( return (vec_of_bit len b))" + + +(*val msb : list bitU -> bitU*) +definition msb :: "(bitU)list \ bitU " where + " msb = ( + most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) +definition int_of_vec_maybe :: " bool \(bitU)list \(int)option " where + " int_of_vec_maybe = ( + int_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition int_of_vec_fail :: " bool \(bitU)list \('b,(int),'a)monad " where + " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))" + +definition int_of_vec_oracle :: " bool \(bitU)list \('b,(int),'a)monad " where + " int_of_vec_oracle sign v = ( bools_of_bits_oracle v \ (\ v . return (int_of_bools sign v)))" + +definition int_of_vec :: " bool \(bitU)list \ int " where + " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))" + + +(*val string_of_vec : list bitU -> string*) +definition string_of_vec :: "(bitU)list \ string " where + " string_of_vec = ( + string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val and_vec : list bitU -> list bitU -> list bitU*) +(*val or_vec : list bitU -> list bitU -> list bitU*) +(*val xor_vec : list bitU -> list bitU -> list bitU*) +(*val not_vec : list bitU -> list bitU*) +definition and_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " and_vec = ( binop_list and_bit )" + +definition or_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " or_vec = ( binop_list or_bit )" + +definition xor_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " xor_vec = ( binop_list xor_bit )" + +definition not_vec :: "(bitU)list \(bitU)list " where + " not_vec = ( List.map not_bit )" + + +(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) +definition arith_op_double_bl :: " 'a Bitvector_class \(int \ int \ int)\ bool \ 'a \ 'a \(bitU)list " where + " arith_op_double_bl dict_Sail_values_Bitvector_a op1 sign l r = ( + (let len =(( 2 :: int) * + (length_method dict_Sail_values_Bitvector_a) l) in + (let l' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in + (let r' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in + List.map (\ b. b) (arith_op_bits op1 sign (List.map (\ b. b) l') (List.map (\ b. b) r'))))))" + + +(*val add_vec : list bitU -> list bitU -> list bitU*) +(*val adds_vec : list bitU -> list bitU -> list bitU*) +(*val sub_vec : list bitU -> list bitU -> list bitU*) +(*val subs_vec : list bitU -> list bitU -> list bitU*) +(*val mult_vec : list bitU -> list bitU -> list bitU*) +(*val mults_vec : list bitU -> list bitU -> list bitU*) +definition add_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " add_vec = ( (\ l r. List.map (\ b. b) (arith_op_bits (op+) False (List.map (\ b. b) l) (List.map (\ b. b) r))))" + +definition adds_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " adds_vec = ( (\ l r. List.map (\ b. b) (arith_op_bits (op+) True (List.map (\ b. b) l) (List.map (\ b. b) r))))" + +definition sub_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " sub_vec = ( (\ l r. List.map (\ b. b) (arith_op_bits (op-) False (List.map (\ b. b) l) (List.map (\ b. b) r))))" + +definition subs_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " subs_vec = ( (\ l r. List.map (\ b. b) (arith_op_bits (op-) True (List.map (\ b. b) l) (List.map (\ b. b) r))))" + +definition mult_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " mult_vec = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False )" + +definition mults_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " mults_vec = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True )" + + +(*val add_vec_int : list bitU -> integer -> list bitU*) +(*val adds_vec_int : list bitU -> integer -> list bitU*) +(*val sub_vec_int : list bitU -> integer -> list bitU*) +(*val subs_vec_int : list bitU -> integer -> list bitU*) +(*val mult_vec_int : list bitU -> integer -> list bitU*) +(*val mults_vec_int : list bitU -> integer -> list bitU*) +definition add_vec_int :: "(bitU)list \ int \(bitU)list " where + " add_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" + +definition adds_vec_int :: "(bitU)list \ int \(bitU)list " where + " adds_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" + +definition sub_vec_int :: "(bitU)list \ int \(bitU)list " where + " sub_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" + +definition subs_vec_int :: "(bitU)list \ int \(bitU)list " where + " subs_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" + +definition mult_vec_int :: "(bitU)list \ int \(bitU)list " where + " mult_vec_int l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False l (List.map (\ b. b) (bits_of_int (int (List.length l)) r)))" + +definition mults_vec_int :: "(bitU)list \ int \(bitU)list " where + " mults_vec_int l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True l (List.map (\ b. b) (bits_of_int (int (List.length l)) r)))" + + +(*val add_int_vec : integer -> list bitU -> list bitU*) +(*val adds_int_vec : integer -> list bitU -> list bitU*) +(*val sub_int_vec : integer -> list bitU -> list bitU*) +(*val subs_int_vec : integer -> list bitU -> list bitU*) +(*val mult_int_vec : integer -> list bitU -> list bitU*) +(*val mults_int_vec : integer -> list bitU -> list bitU*) +definition add_int_vec :: " int \(bitU)list \(bitU)list " where + " add_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" + +definition adds_int_vec :: " int \(bitU)list \(bitU)list " where + " adds_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" + +definition sub_int_vec :: " int \(bitU)list \(bitU)list " where + " sub_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" + +definition subs_int_vec :: " int \(bitU)list \(bitU)list " where + " subs_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" + +definition mult_int_vec :: " int \(bitU)list \(bitU)list " where + " mult_int_vec l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False (List.map (\ b. b) (bits_of_int (int (List.length r)) l)) r )" + +definition mults_int_vec :: " int \(bitU)list \(bitU)list " where + " mults_int_vec l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True (List.map (\ b. b) (bits_of_int (int (List.length r)) l)) r )" + + +(*val add_vec_bit : list bitU -> bitU -> list bitU*) +(*val adds_vec_bit : list bitU -> bitU -> list bitU*) +(*val sub_vec_bit : list bitU -> bitU -> list bitU*) +(*val subs_vec_bit : list bitU -> bitU -> list bitU*) + +definition add_vec_bool :: " 'a Bitvector_class \ 'a \ bool \ 'a " where + " add_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op+) False l r )" + +definition add_vec_bit_maybe :: " 'a Bitvector_class \ 'a \ bitU \ 'a option " where + " add_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op+) False l r )" + +definition add_vec_bit_fail :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " add_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition add_vec_bit_oracle :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " add_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \ (\ r . return (add_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition add_vec_bit :: "(bitU)list \ bitU \(bitU)list " where + " add_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition adds_vec_bool :: " 'a Bitvector_class \ 'a \ bool \ 'a " where + " adds_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op+) True l r )" + +definition adds_vec_bit_maybe :: " 'a Bitvector_class \ 'a \ bitU \ 'a option " where + " adds_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op+) True l r )" + +definition adds_vec_bit_fail :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " adds_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition adds_vec_bit_oracle :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " adds_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \ (\ r . return (adds_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition adds_vec_bit :: "(bitU)list \ bitU \(bitU)list " where + " adds_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition sub_vec_bool :: " 'a Bitvector_class \ 'a \ bool \ 'a " where + " sub_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op-) False l r )" + +definition sub_vec_bit_maybe :: " 'a Bitvector_class \ 'a \ bitU \ 'a option " where + " sub_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op-) False l r )" + +definition sub_vec_bit_fail :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " sub_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition sub_vec_bit_oracle :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " sub_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \ (\ r . return (sub_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition sub_vec_bit :: "(bitU)list \ bitU \(bitU)list " where + " sub_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition subs_vec_bool :: " 'a Bitvector_class \ 'a \ bool \ 'a " where + " subs_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op-) True l r )" + +definition subs_vec_bit_maybe :: " 'a Bitvector_class \ 'a \ bitU \ 'a option " where + " subs_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op-) True l r )" + +definition subs_vec_bit_fail :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " subs_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition subs_vec_bit_oracle :: " 'a Bitvector_class \ 'a \ bitU \('d,'a,'c)monad " where + " subs_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \ (\ r . return (subs_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition subs_vec_bit :: "(bitU)list \ bitU \(bitU)list " where + " subs_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : list bitU -> integer -> list bitU*) +(*val shiftr : list bitU -> integer -> list bitU*) +(*val arith_shiftr : list bitU -> integer -> list bitU*) +(*val rotl : list bitU -> integer -> list bitU*) +(*val rotr : list bitU -> integer -> list bitU*) +definition shiftl :: "(bitU)list \ int \(bitU)list " where + " shiftl = ( + shiftl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition shiftr :: "(bitU)list \ int \(bitU)list " where + " shiftr = ( + shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition arith_shiftr :: "(bitU)list \ int \(bitU)list " where + " arith_shiftr = ( + arith_shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition rotl :: "(bitU)list \ int \(bitU)list " where + " rotl = ( + rotl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition rotr :: "(bitU)list \ int \(bitU)list " where + " rotr = ( + rotr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val mod_vec : list bitU -> list bitU -> list bitU*) +(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition mod_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " mod_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_maybe :: "(bitU)list \(bitU)list \((bitU)list)option " where + " mod_vec_maybe l r = ( mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition mod_vec_fail :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_oracle :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " mod_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec l r))" + + +(*val quot_vec : list bitU -> list bitU -> list bitU*) +(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition quot_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " quot_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_maybe :: "(bitU)list \(bitU)list \((bitU)list)option " where + " quot_vec_maybe l r = ( quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quot_vec_fail :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_oracle :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " quot_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec l r))" + + +(*val quots_vec : list bitU -> list bitU -> list bitU*) +(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition quots_vec :: "(bitU)list \(bitU)list \(bitU)list " where + " quots_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quots_vec_maybe :: "(bitU)list \(bitU)list \((bitU)list)option " where + " quots_vec_maybe l r = ( quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quots_vec_fail :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quots_vec_oracle :: "(bitU)list \(bitU)list \('rv,((bitU)list),'e)monad " where + " quots_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec l r))" + + +(*val mod_vec_int : list bitU -> integer -> list bitU*) +(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +definition mod_vec_int :: "(bitU)list \ int \(bitU)list " where + " mod_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_int_maybe :: "(bitU)list \ int \((bitU)list)option " where + " mod_vec_int_maybe l r = ( mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition mod_vec_int_fail :: "(bitU)list \ int \('rv,((bitU)list),'e)monad " where + " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_int_oracle :: "(bitU)list \ int \('rv,((bitU)list),'e)monad " where + " mod_vec_int_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int l r))" + + +(*val quot_vec_int : list bitU -> integer -> list bitU*) +(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +definition quot_vec_int :: "(bitU)list \ int \(bitU)list " where + " quot_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_int_maybe :: "(bitU)list \ int \((bitU)list)option " where + " quot_vec_int_maybe l r = ( quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quot_vec_int_fail :: "(bitU)list \ int \('rv,((bitU)list),'e)monad " where + " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_int_oracle :: "(bitU)list \ int \('rv,((bitU)list),'e)monad " where + " quot_vec_int_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int l r))" + + +(*val replicate_bits : list bitU -> integer -> list bitU*) +definition replicate_bits :: "(bitU)list \ int \(bitU)list " where + " replicate_bits = ( + replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val duplicate : bitU -> integer -> list bitU*) +definition duplicate :: " bitU \ int \(bitU)list " where + " duplicate = ( + duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict )" + +definition duplicate_maybe :: " bitU \ int \((bitU)list)option " where + " duplicate_maybe b n = ( Some (duplicate b n))" + +definition duplicate_fail :: " bitU \ int \('b,((bitU)list),'a)monad " where + " duplicate_fail b n = ( return (duplicate b n))" + +definition duplicate_oracle :: " bitU \ int \('b,((bitU)list),'a)monad " where + " duplicate_oracle b n = ( + bool_of_bitU_oracle b \ (\ b . + return (duplicate (bitU_of_bool b) n)))" + + +(*val reverse_endianness : list bitU -> list bitU*) +definition reverse_endianness :: "(bitU)list \(bitU)list " where + " reverse_endianness v = ( reverse_endianness_list v )" + + +(*val get_slice_int : integer -> integer -> integer -> list bitU*) +definition get_slice_int :: " int \ int \ int \(bitU)list " where + " get_slice_int = ( + get_slice_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) +definition set_slice_int :: " int \ int \ int \(bitU)list \ int " where + " set_slice_int = ( + set_slice_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val slice : list bitU -> integer -> integer -> list bitU*) +definition slice :: "(bitU)list \ int \ int \(bitU)list " where + " slice v lo len = ( + subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )" + + +(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*) +definition set_slice :: " int \ int \(bitU)list \ int \(bitU)list \(bitU)list " where + " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = ( + update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )" + + +(*val eq_vec : list bitU -> list bitU -> bool*) +(*val neq_vec : list bitU -> list bitU -> bool*) +definition eq_vec :: "(bitU)list \(bitU)list \ bool " where + " eq_vec = ( + eq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition neq_vec :: "(bitU)list \(bitU)list \ bool " where + " neq_vec = ( + neq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy new file mode 100644 index 00000000..edaec4e3 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy @@ -0,0 +1,638 @@ +chapter \Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.\ + +theory "Sail_operators_mwords" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + "Sail_operators" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) +definition uint_maybe :: "('a::len)Word.word \(int)option " where + " uint_maybe v = ( Some (Word.uint v))" + +definition uint_fail :: "('a::len)Word.word \('c,(int),'b)monad " where + " uint_fail v = ( return (Word.uint v))" + +definition uint_oracle :: "('a::len)Word.word \('c,(int),'b)monad " where + " uint_oracle v = ( return (Word.uint v))" + +definition sint_maybe :: "('a::len)Word.word \(int)option " where + " sint_maybe v = ( Some (Word.sint v))" + +definition sint_fail :: "('a::len)Word.word \('c,(int),'b)monad " where + " sint_fail v = ( return (Word.sint v))" + +definition sint_oracle :: "('a::len)Word.word \('c,(int),'b)monad " where + " sint_oracle v = ( return (Word.sint v))" + + +(*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*) +(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*) +(*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*) +definition vec_of_bits_maybe :: "(bitU)list \(('a::len)Word.word)option " where + " vec_of_bits_maybe bits = ( map_option Word.of_bl (just_list (List.map bool_of_bitU bits)))" + +definition vec_of_bits_fail :: "(bitU)list \('rv,(('a::len)Word.word),'e)monad " where + " vec_of_bits_fail bits = ( of_bits_fail + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits_oracle :: "(bitU)list \('rv,(('a::len)Word.word),'e)monad " where + " vec_of_bits_oracle bits = ( of_bits_oracle + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits_failwith :: "(bitU)list \('a::len)Word.word " where + " vec_of_bits_failwith bits = ( of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits :: "(bitU)list \('a::len)Word.word " where + " vec_of_bits bits = ( of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + + +(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) +definition access_vec_inc :: "('a::len)Word.word \ int \ bitU " where + " access_vec_inc = ( + access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) +definition access_vec_dec :: "('a::len)Word.word \ int \ bitU " where + " access_vec_dec = ( + access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +definition update_vec_dec_maybe :: "('a::len)Word.word \ int \ bitU \(('a::len)Word.word)option " where + " update_vec_dec_maybe w i b = ( update_mword_dec w i b )" + +definition update_vec_dec_fail :: "('a::len)Word.word \ int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " update_vec_dec_fail w i b = ( + bool_of_bitU_fail b \ (\ b . + return (update_mword_bool_dec w i b)))" + +definition update_vec_dec_oracle :: "('a::len)Word.word \ int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " update_vec_dec_oracle w i b = ( + bool_of_bitU_oracle b \ (\ b . + return (update_mword_bool_dec w i b)))" + +definition update_vec_dec :: "('a::len)Word.word \ int \ bitU \('a::len)Word.word " where + " update_vec_dec w i b = ( maybe_failwith (update_vec_dec_maybe w i b))" + + +definition update_vec_inc_maybe :: "('a::len)Word.word \ int \ bitU \(('a::len)Word.word)option " where + " update_vec_inc_maybe w i b = ( update_mword_inc w i b )" + +definition update_vec_inc_fail :: "('a::len)Word.word \ int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " update_vec_inc_fail w i b = ( + bool_of_bitU_fail b \ (\ b . + return (update_mword_bool_inc w i b)))" + +definition update_vec_inc_oracle :: "('a::len)Word.word \ int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " update_vec_inc_oracle w i b = ( + bool_of_bitU_oracle b \ (\ b . + return (update_mword_bool_inc w i b)))" + +definition update_vec_inc :: "('a::len)Word.word \ int \ bitU \('a::len)Word.word " where + " update_vec_inc w i b = ( maybe_failwith (update_vec_inc_maybe w i b))" + + +(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition subrange_vec_dec :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " subrange_vec_dec w i j = ( Word.slice (nat_of_int j) w )" + + +(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition subrange_vec_inc :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " subrange_vec_inc w i j = ( subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j))" + + +(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_subrange_vec_dec :: "('a::len)Word.word \ int \ int \('b::len)Word.word \('a::len)Word.word " where + " update_subrange_vec_dec w i j w' = ( Lem.word_update w (nat_of_int j) (nat_of_int i) w' )" + + +(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_subrange_vec_inc :: "('a::len)Word.word \ int \ int \('b::len)Word.word \('a::len)Word.word " where + " update_subrange_vec_inc w i j w' = ( update_subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j) w' )" + + +(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition extz_vec :: " int \('a::len)Word.word \('b::len)Word.word " where + " extz_vec _ w = ( Word.ucast w )" + + +(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition exts_vec :: " int \('a::len)Word.word \('b::len)Word.word " where + " exts_vec _ w = ( Word.scast w )" + + +(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition zero_extend :: "('a::len)Word.word \ int \('b::len)Word.word " where + " zero_extend w _ = ( Word.ucast w )" + + +(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition sign_extend :: "('a::len)Word.word \ int \('b::len)Word.word " where + " sign_extend w _ = ( Word.scast w )" + + +(*val zeros : forall 'a. Size 'a => integer -> mword 'a*) +definition zeros :: " int \('a::len)Word.word " where + " zeros _ = ( Word.word_of_int (int(( 0 :: nat))))" + + +(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition vector_truncate :: "('a::len)Word.word \ int \('b::len)Word.word " where + " vector_truncate w _ = ( Word.ucast w )" + + +(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*) +definition concat_vec :: "('a::len)Word.word \('b::len)Word.word \('c::len)Word.word " where + " concat_vec = ( Word.word_cat )" + + +(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*) +definition cons_vec_bool :: " bool \('a::len)Word.word \('b::len)Word.word " where + " cons_vec_bool b w = ( Word.of_bl (b # Word.to_bl w))" + +definition cons_vec_maybe :: " bitU \('c::len)Word.word \(('b::len)Word.word)option " where + " cons_vec_maybe b w = ( map_option (\ b . cons_vec_bool b w) (bool_of_bitU b))" + +definition cons_vec_fail :: " bitU \('c::len)Word.word \('e,(('b::len)Word.word),'d)monad " where + " cons_vec_fail b w = ( bool_of_bitU_fail b \ (\ b . return (cons_vec_bool b w)))" + +definition cons_vec_oracle :: " bitU \('c::len)Word.word \('e,(('b::len)Word.word),'d)monad " where + " cons_vec_oracle b w = ( bool_of_bitU_oracle b \ (\ b . return (cons_vec_bool b w)))" + +definition cons_vec :: " bitU \('a::len)Word.word \('b::len)Word.word " where + " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))" + + +(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*) +definition vec_of_bool :: " int \ bool \('a::len)Word.word " where + " vec_of_bool _ b = ( Word.of_bl [b])" + +definition vec_of_bit_maybe :: " int \ bitU \(('a::len)Word.word)option " where + " vec_of_bit_maybe len b = ( map_option (vec_of_bool len) (bool_of_bitU b))" + +definition vec_of_bit_fail :: " int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " vec_of_bit_fail len b = ( bool_of_bitU_fail b \ (\ b . return (vec_of_bool len b)))" + +definition vec_of_bit_oracle :: " int \ bitU \('c,(('a::len)Word.word),'b)monad " where + " vec_of_bit_oracle len b = ( bool_of_bitU_oracle b \ (\ b . return (vec_of_bool len b)))" + +definition vec_of_bit :: " int \ bitU \('a::len)Word.word " where + " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))" + + +(*val cast_bool_vec : bool -> mword ty1*) +definition cast_bool_vec :: " bool \(1)Word.word " where + " cast_bool_vec b = ( vec_of_bool(( 1 :: int)) b )" + +definition cast_unit_vec_maybe :: " bitU \(('a::len)Word.word)option " where + " cast_unit_vec_maybe b = ( vec_of_bit_maybe(( 1 :: int)) b )" + +definition cast_unit_vec_fail :: " bitU \('b,((1)Word.word),'a)monad " where + " cast_unit_vec_fail b = ( bool_of_bitU_fail b \ (\ b . return (cast_bool_vec b)))" + +definition cast_unit_vec_oracle :: " bitU \('b,((1)Word.word),'a)monad " where + " cast_unit_vec_oracle b = ( bool_of_bitU_oracle b \ (\ b . return (cast_bool_vec b)))" + +definition cast_unit_vec :: " bitU \('a::len)Word.word " where + " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))" + + +(*val msb : forall 'a. Size 'a => mword 'a -> bitU*) +definition msb :: "('a::len)Word.word \ bitU " where + " msb = ( + most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*) +definition int_of_vec :: " bool \('a::len)Word.word \ int " where + " int_of_vec sign w = ( + if sign + then Word.sint w + else Word.uint w )" + +definition int_of_vec_maybe :: " bool \('a::len)Word.word \(int)option " where + " int_of_vec_maybe sign w = ( Some (int_of_vec sign w))" + +definition int_of_vec_fail :: " bool \('a::len)Word.word \('c,(int),'b)monad " where + " int_of_vec_fail sign w = ( return (int_of_vec sign w))" + + +(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) +definition string_of_vec :: "('a::len)Word.word \ string " where + " string_of_vec = ( + string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*) +definition and_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " and_vec = ( Bits.bitAND )" + +definition or_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " or_vec = ( Bits.bitOR )" + +definition xor_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " xor_vec = ( Bits.bitXOR )" + +definition not_vec :: "('a::len)Word.word \('a::len)Word.word " where + " not_vec = ( Bits.bitNOT )" + + +(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val adds_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val subs_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) +(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) +definition add_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " add_vec l r = ( Word.word_of_int ((int_of_mword False l) + (int_of_mword False r)))" + +definition adds_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " adds_vec l r = ( Word.word_of_int ((int_of_mword True l) + (int_of_mword True r)))" + +definition sub_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " sub_vec l r = ( Word.word_of_int ((int_of_mword False l) - (int_of_mword False r)))" + +definition subs_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " subs_vec l r = ( Word.word_of_int ((int_of_mword True l) - (int_of_mword True r)))" + +definition mult_vec :: "('a::len)Word.word \('a::len)Word.word \('b::len)Word.word " where + " mult_vec l r = ( Word.word_of_int ((int_of_mword False (Word.ucast l :: ( 'b::len)Word.word)) * (int_of_mword False (Word.ucast r :: ( 'b::len)Word.word))))" + +definition mults_vec :: "('a::len)Word.word \('a::len)Word.word \('b::len)Word.word " where + " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))" + + +(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val adds_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val subs_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition add_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " add_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition adds_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " adds_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition sub_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " sub_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition subs_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " subs_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition mult_vec_int :: "('a::len)Word.word \ int \('b::len)Word.word " where + " mult_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False (Word.ucast l :: ( 'b::len)Word.word) r )" + +definition mults_vec_int :: "('a::len)Word.word \ int \('b::len)Word.word " where + " mults_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True (Word.scast l :: ( 'b::len)Word.word) r )" + + +(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val adds_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val subs_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition add_int_vec :: " int \('a::len)Word.word \('a::len)Word.word " where + " add_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition adds_int_vec :: " int \('a::len)Word.word \('a::len)Word.word " where + " adds_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition sub_int_vec :: " int \('a::len)Word.word \('a::len)Word.word " where + " sub_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition subs_int_vec :: " int \('a::len)Word.word \('a::len)Word.word " where + " subs_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition mult_int_vec :: " int \('a::len)Word.word \('b::len)Word.word " where + " mult_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False l (Word.ucast r :: ( 'b::len)Word.word))" + +definition mults_int_vec :: " int \('a::len)Word.word \('b::len)Word.word " where + " mults_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True l (Word.scast r :: ( 'b::len)Word.word))" + + +(*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val sub_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) + +definition add_vec_bool :: "('a::len)Word.word \ bool \('a::len)Word.word " where + " add_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition add_vec_bit_maybe :: "('a::len)Word.word \ bitU \(('a::len)Word.word)option " where + " add_vec_bit_maybe l r = ( map_option (add_vec_bool l) (bool_of_bitU r))" + +definition add_vec_bit_fail :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " add_vec_bit_fail l r = ( bool_of_bitU_fail r \ (\ r . return (add_vec_bool l r)))" + +definition add_vec_bit_oracle :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " add_vec_bit_oracle l r = ( bool_of_bitU_oracle r \ (\ r . return (add_vec_bool l r)))" + +definition add_vec_bit :: "('a::len)Word.word \ bitU \('a::len)Word.word " where + " add_vec_bit l r = ( maybe_failwith (add_vec_bit_maybe l r))" + + +definition adds_vec_bool :: "('a::len)Word.word \ bool \('a::len)Word.word " where + " adds_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition adds_vec_bit_maybe :: "('a::len)Word.word \ bitU \(('a::len)Word.word)option " where + " adds_vec_bit_maybe l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))" + +definition adds_vec_bit_fail :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " adds_vec_bit_fail l r = ( bool_of_bitU_fail r \ (\ r . return (adds_vec_bool l r)))" + +definition adds_vec_bit_oracle :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " adds_vec_bit_oracle l r = ( bool_of_bitU_oracle r \ (\ r . return (adds_vec_bool l r)))" + +definition adds_vec_bit :: "('a::len)Word.word \ bitU \('a::len)Word.word " where + " adds_vec_bit l r = ( maybe_failwith (adds_vec_bit_maybe l r))" + + +definition sub_vec_bool :: "('a::len)Word.word \ bool \('a::len)Word.word " where + " sub_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition sub_vec_bit_maybe :: "('a::len)Word.word \ bitU \(('a::len)Word.word)option " where + " sub_vec_bit_maybe l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))" + +definition sub_vec_bit_fail :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " sub_vec_bit_fail l r = ( bool_of_bitU_fail r \ (\ r . return (sub_vec_bool l r)))" + +definition sub_vec_bit_oracle :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " sub_vec_bit_oracle l r = ( bool_of_bitU_oracle r \ (\ r . return (sub_vec_bool l r)))" + +definition sub_vec_bit :: "('a::len)Word.word \ bitU \('a::len)Word.word " where + " sub_vec_bit l r = ( maybe_failwith (sub_vec_bit_maybe l r))" + + +definition subs_vec_bool :: "('a::len)Word.word \ bool \('a::len)Word.word " where + " subs_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition subs_vec_bit_maybe :: "('a::len)Word.word \ bitU \(('a::len)Word.word)option " where + " subs_vec_bit_maybe l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))" + +definition subs_vec_bit_fail :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " subs_vec_bit_fail l r = ( bool_of_bitU_fail r \ (\ r . return (subs_vec_bool l r)))" + +definition subs_vec_bit_oracle :: "('a::len)Word.word \ bitU \('c,(('a::len)Word.word),'b)monad " where + " subs_vec_bit_oracle l r = ( bool_of_bitU_oracle r \ (\ r . return (subs_vec_bool l r)))" + +definition subs_vec_bit :: "('a::len)Word.word \ bitU \('a::len)Word.word " where + " subs_vec_bit l r = ( maybe_failwith (subs_vec_bit_maybe l r))" + + +(* TODO +val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU) +let maybe_mword_of_bits_overflow (bits, overflow, carry) = + Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits) + +val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val adds_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val subs_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +let add_overflow_vec l r = maybe_mword_of_bits_overflow (add_overflow_bv l r) +let adds_overflow_vec l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r) +let sub_overflow_vec l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r) +let subs_overflow_vec l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r) +let mult_overflow_vec l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r) +let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r) + +val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +definition shiftl :: "('a::len)Word.word \ int \('a::len)Word.word " where + " shiftl = ( shiftl_mword )" + +definition shiftr :: "('a::len)Word.word \ int \('a::len)Word.word " where + " shiftr = ( shiftr_mword )" + +definition arith_shiftr :: "('a::len)Word.word \ int \('a::len)Word.word " where + " arith_shiftr = ( arith_shiftr_mword )" + +definition rotl :: "('a::len)Word.word \ int \('a::len)Word.word " where + " rotl = ( rotl_mword )" + +definition rotr :: "('a::len)Word.word \ int \('a::len)Word.word " where + " rotr = ( rotr_mword )" + + +(*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition mod_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " mod_vec l r = ( mod_mword l r )" + +definition mod_vec_maybe :: "('a::len)Word.word \('a::len)Word.word \(('a::len)Word.word)option " where + " mod_vec_maybe l r = ( mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition mod_vec_fail :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition mod_vec_oracle :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_oracle l r = ( + (case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition quot_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " quot_vec l r = ( quot_mword l r )" + +definition quot_vec_maybe :: "('a::len)Word.word \('a::len)Word.word \(('a::len)Word.word)option " where + " quot_vec_maybe l r = ( quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quot_vec_fail :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quot_vec_oracle :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_oracle l r = ( + (case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition quots_vec :: "('a::len)Word.word \('a::len)Word.word \('a::len)Word.word " where + " quots_vec l r = ( quots_mword l r )" + +definition quots_vec_maybe :: "('a::len)Word.word \('a::len)Word.word \(('a::len)Word.word)option " where + " quots_vec_maybe l r = ( quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quots_vec_fail :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quots_vec_oracle :: "('a::len)Word.word \('a::len)Word.word \('rv,(('a::len)Word.word),'e)monad " where + " quots_vec_oracle l r = ( + (case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +definition mod_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " mod_vec_int l r = ( mod_mword_int l r )" + +definition mod_vec_int_maybe :: "('a::len)Word.word \ int \(('a::len)Word.word)option " where + " mod_vec_int_maybe l r = ( mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition mod_vec_int_fail :: "('a::len)Word.word \ int \('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition mod_vec_int_oracle :: "('a::len)Word.word \ int \('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_int_oracle l r = ( + (case (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +definition quot_vec_int :: "('a::len)Word.word \ int \('a::len)Word.word " where + " quot_vec_int l r = ( quot_mword_int l r )" + +definition quot_vec_int_maybe :: "('a::len)Word.word \ int \(('a::len)Word.word)option " where + " quot_vec_int_maybe l r = ( quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quot_vec_int_fail :: "('a::len)Word.word \ int \('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quot_vec_int_oracle :: "('a::len)Word.word \ int \('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_int_oracle l r = ( + (case (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition replicate_bits :: "('a::len)Word.word \ int \('b::len)Word.word " where + " replicate_bits v count1 = ( Word.of_bl (repeat (Word.to_bl v) count1))" + + +(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*) +definition duplicate_bool :: " bool \ int \('a::len)Word.word " where + " duplicate_bool b n = ( Word.of_bl (repeat [b] n))" + +definition duplicate_maybe :: " bitU \ int \(('a::len)Word.word)option " where + " duplicate_maybe b n = ( map_option (\ b . duplicate_bool b n) (bool_of_bitU b))" + +definition duplicate_fail :: " bitU \ int \('c,(('a::len)Word.word),'b)monad " where + " duplicate_fail b n = ( bool_of_bitU_fail b \ (\ b . return (duplicate_bool b n)))" + +definition duplicate_oracle :: " bitU \ int \('c,(('a::len)Word.word),'b)monad " where + " duplicate_oracle b n = ( bool_of_bitU_oracle b \ (\ b . return (duplicate_bool b n)))" + +definition duplicate :: " bitU \ int \('a::len)Word.word " where + " duplicate b n = ( maybe_failwith (duplicate_maybe b n))" + + +(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*) +definition reverse_endianness :: "('a::len)Word.word \('a::len)Word.word " where + " reverse_endianness v = ( Word.of_bl (reverse_endianness_list (Word.to_bl v)))" + + +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) +definition get_slice_int :: " int \ int \ int \('a::len)Word.word " where + " get_slice_int = ( + get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) +definition set_slice_int :: " int \ int \ int \('a::len)Word.word \ int " where + " set_slice_int = ( + set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition slice :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " slice v lo len = ( + subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )" + + +(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*) +definition set_slice :: " int \ int \('a::len)Word.word \ int \('b::len)Word.word \('a::len)Word.word " where + " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = ( + update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )" + + +(*val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) +(*val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy new file mode 100644 index 00000000..22c35e1f --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy @@ -0,0 +1,112 @@ +theory "Sail_operators_mwords_lemmas" + imports Sail_operators_mwords +begin + +lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_oracle_def +lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_oracle_def + +lemma bools_of_bits_oracle_just_list[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "bools_of_bits_oracle bus = return bs" +proof - + have f: "foreachM bus bools (\b bools. bool_of_bitU_oracle b \ (\b. return (bools @ [b]))) = return (bools @ bs)" + if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools + proof (use that in \induction bus arbitrary: bs bools\) + case (Cons bu bus bs) + obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b" + using Cons.prems by (cases bu) (auto split: option.splits) + then show ?case + using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"] + by (cases bu) (auto simp: bool_of_bitU_oracle_def split: option.splits) + qed auto + then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_oracle_def + by auto +qed + +lemma of_bits_mword_return_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "of_bits_oracle BC_mword bus = return (of_bl bs)" + and "of_bits_fail BC_mword bus = return (of_bl bs)" + by (auto simp: of_bits_oracle_def of_bits_fail_def maybe_fail_def assms BC_mword_defs) + +lemma vec_of_bits_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "vec_of_bits_maybe bus = Some (of_bl bs)" + and "vec_of_bits_fail bus = return (of_bl bs)" + and "vec_of_bits_oracle bus = return (of_bl bs)" + and "vec_of_bits_failwith bus = of_bl bs" + and "vec_of_bits bus = of_bl bs" + unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_oracle_def + vec_of_bits_failwith_def vec_of_bits_def + by (auto simp: assms) + +lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def] + +lemma access_vec_inc_test_bit[simp]: + fixes w :: "('a::len) word" + assumes "n \ 0" and "nat n < LENGTH('a)" + shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))" + using assms + by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl) + +lemma bool_of_bitU_monadic_simps[simp]: + "bool_of_bitU_fail B0 = return False" + "bool_of_bitU_fail B1 = return True" + "bool_of_bitU_fail BU = Fail ''bool_of_bitU''" + "bool_of_bitU_oracle B0 = return False" + "bool_of_bitU_oracle B1 = return True" + "bool_of_bitU_oracle BU = undefined_bool ()" + unfolding bool_of_bitU_fail_def bool_of_bitU_oracle_def + by auto + +lemma update_vec_dec_simps[simp]: + "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)" + "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)" + "update_vec_dec_maybe w i BU = None" + "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''" + "update_vec_dec_oracle w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_oracle w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_oracle w i BU = undefined_bool () \ (\b. return (set_bit w (nat i) b))" + "update_vec_dec w i B0 = set_bit w (nat i) False" + "update_vec_dec w i B1 = set_bit w (nat i) True" + unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_oracle_def update_vec_dec_def + by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def) + +lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]: + "n \ 0 \ nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)" + by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq) + +declare extz_vec_def[simp] +declare exts_vec_def[simp] +declare concat_vec_def[simp] + +lemma msb_Bits_msb[simp]: + "msb w = bitU_of_bool (Bits.msb w)" + by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits) + +declare and_vec_def[simp] +declare or_vec_def[simp] +declare xor_vec_def[simp] +declare not_vec_def[simp] + +lemma arith_vec_simps[simp]: + "add_vec l r = l + r" + "sub_vec l r = l - r" + "mult_vec l r = (ucast l) * (ucast r)" + unfolding add_vec_def sub_vec_def mult_vec_def + by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def) + +declare adds_vec_def[simp] +declare subs_vec_def[simp] +declare mults_vec_def[simp] + +lemma arith_vec_int_simps[simp]: + "add_vec_int l r = l + (word_of_int r)" + "sub_vec_int l r = l - (word_of_int r)" + "mult_vec_int l r = (ucast l) * (word_of_int r)" + unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def + by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def) + +end diff --git a/snapshots/isabelle/lib/sail/Sail_values.thy b/snapshots/isabelle/lib/sail/Sail_values.thy new file mode 100644 index 00000000..7338ac40 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_values.thy @@ -0,0 +1,1215 @@ +chapter \Generated by Lem from ../../src/gen_lib/sail_values.lem.\ + +theory "Sail_values" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_impl_base*) + + +type_synonym ii =" int " +type_synonym nn =" nat " + +(*val nat_of_int : integer -> nat*) +definition nat_of_int :: " int \ nat " where + " nat_of_int i = ( if i <( 0 :: int) then( 0 :: nat) else nat (abs ( i)))" + + +(*val pow : integer -> integer -> integer*) +definition pow :: " int \ int \ int " where + " pow m n = ( m ^ (nat_of_int n))" + + +definition pow2 :: " int \ int " where + " pow2 n = ( pow(( 2 :: int)) n )" + + +(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*let add_int l r = integerAdd l r +let add_signed l r = integerAdd l r +let sub_int l r = integerMinus l r +let mult_int l r = integerMult l r +let div_int l r = integerDiv l r +let div_nat l r = natDiv l r +let power_int_nat l r = integerPow l r +let power_int_int l r = integerPow l (nat_of_int r) +let negate_int i = integerNegate i +let min_int l r = integerMin l r +let max_int l r = integerMax l r + +let add_real l r = realAdd l r +let sub_real l r = realMinus l r +let mult_real l r = realMult l r +let div_real l r = realDiv l r +let negate_real r = realNegate r +let abs_real r = realAbs r +let power_real b e = realPowInteger b e*) + +(*val prerr_endline : string -> unit*) +definition prerr_endline :: " string \ unit " where + " prerr_endline _ = ( () )" + + +(*val print_int : string -> integer -> unit*) +definition print_int :: " string \ int \ unit " where + " print_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))" + + +(*val putchar : integer -> unit*) +definition putchar :: " int \ unit " where + " putchar _ = ( () )" + + +(*val shr_int : ii -> ii -> ii*) +function (sequential,domintros) shr_int :: " int \ int \ int " where + " shr_int x s = ( if s >( 0 :: int) then shr_int (x div( 2 :: int)) (s -( 1 :: int)) else x )" +by pat_completeness auto + + +(*val shl_int : integer -> integer -> integer*) +function (sequential,domintros) shl_int :: " int \ int \ int " where + " shl_int i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int i (shift -( 1 :: int)) else i )" +by pat_completeness auto + +definition take_list :: " int \ 'a list \ 'a list " where + " take_list n xs = ( List.take (nat_of_int n) xs )" + +definition drop_list :: " int \ 'a list \ 'a list " where + " drop_list n xs = ( List.drop (nat_of_int n) xs )" + + +(*val repeat : forall 'a. list 'a -> integer -> list 'a*) +fun repeat :: " 'a list \ int \ 'a list " where + " repeat xs n = ( + if n \( 0 :: int) then [] + else xs @ repeat xs (n-( 1 :: int)))" + + +definition duplicate_to_list :: " 'a \ int \ 'a list " where + " duplicate_to_list bit length1 = ( repeat [bit] length1 )" + + +fun replace :: " 'a list \ int \ 'a \ 'a list " where + " replace ([]) (n :: int) b' = ( [])" +|" replace (b # bs) (n :: int) b' = ( + if n =( 0 :: int) then b' # bs + else b # replace bs (n -( 1 :: int)) b' )" + + +definition upper :: " 'a \ 'a " where + " upper n = ( n )" + + +(* Modulus operation corresponding to quot below -- result + has sign of dividend. *) +definition hardware_mod :: " int \ int \ int " where + " hardware_mod (a:: int) (b::int) = ( + (let m = ((abs a) mod (abs b)) in + if a <( 0 :: int) then - m else m))" + + +(* There are different possible answers for integer divide regarding +rounding behaviour on negative operands. Positive operands always +round down so derive the one we want (trucation towards zero) from +that *) +definition hardware_quot :: " int \ int \ int " where + " hardware_quot (a::int) (b::int) = ( + (let q = ((abs a) div (abs b)) in + if ((a<( 0 :: int)) \ (b<( 0 :: int))) then + q (* same sign -- result positive *) + else + - q))" + (* different sign -- result negative *) + +definition max_64u :: " int " where + " max_64u = ( ((( 2 :: int))^(( 64 :: nat))) -( 1 :: int))" + +definition max_64 :: " int " where + " max_64 = ( ((( 2 :: int))^(( 63 :: nat))) -( 1 :: int))" + +definition min_64 :: " int " where + " min_64 = (( 0 :: int) - ((( 2 :: int))^(( 63 :: nat))))" + +definition max_32u :: " int " where + " max_32u = ( (( 4294967295 :: int) :: int))" + +definition max_32 :: " int " where + " max_32 = ( (( 2147483647 :: int) :: int))" + +definition min_32 :: " int " where + " min_32 = ( (( 0 :: int) -( 2147483648 :: int) :: int))" + +definition max_8 :: " int " where + " max_8 = ( (( 127 :: int) :: int))" + +definition min_8 :: " int " where + " min_8 = ( (( 0 :: int) -( 128 :: int) :: int))" + +definition max_5 :: " int " where + " max_5 = ( (( 31 :: int) :: int))" + +definition min_5 :: " int " where + " min_5 = ( (( 0 :: int) -( 32 :: int) :: int))" + + +(* just_list takes a list of maybes and returns Just xs if all elements have + a value, and Nothing if one of the elements is Nothing. *) +(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*) +fun just_list :: "('a option)list \('a list)option " where + " just_list ([]) = ( Some [])" +|" just_list (x # xs) = ( + (case (x, just_list xs) of + (Some x, Some xs) => Some (x # xs) + | (_, _) => None + ))" + + +(*val maybe_failwith : forall 'a. maybe 'a -> 'a*) +definition maybe_failwith :: " 'a option \ 'a " where + " maybe_failwith = ( \x . + (case x of Some a => a | None => failwith (''maybe_failwith'') ) )" + + +(*** Bits *) +datatype bitU = B0 | B1 | BU + +definition showBitU :: " bitU \ string " where + " showBitU = ( \x . + (case x of B0 => (''O'') | B1 => (''I'') | BU => (''U'') ) )" + + +definition bitU_char :: " bitU \ char " where + " bitU_char = ( \x . + (case x of B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )" + + +definition instance_Show_Show_Sail_values_bitU_dict :: "(bitU)Show_class " where + " instance_Show_Show_Sail_values_bitU_dict = ((| + + show_method = showBitU |) )" + + +(*val compare_bitU : bitU -> bitU -> ordering*) +fun compare_bitU :: " bitU \ bitU \ ordering " where + " compare_bitU BU BU = ( EQ )" +|" compare_bitU B0 B0 = ( EQ )" +|" compare_bitU B1 B1 = ( EQ )" +|" compare_bitU BU _ = ( LT )" +|" compare_bitU _ BU = ( GT )" +|" compare_bitU B0 _ = ( LT )" +|" compare_bitU _ _ = ( GT )" + + +definition instance_Basic_classes_Ord_Sail_values_bitU_dict :: "(bitU)Ord_class " where + " instance_Basic_classes_Ord_Sail_values_bitU_dict = ((| + + compare_method = compare_bitU, + + isLess_method = (\ l r. (compare_bitU l r) = LT), + + isLessEqual_method = (\ l r. (compare_bitU l r) \ GT), + + isGreater_method = (\ l r. (compare_bitU l r) = GT), + + isGreaterEqual_method = (\ l r. (compare_bitU l r) \ LT)|) )" + + +record 'a BitU_class= + + to_bitU_method ::" 'a \ bitU " + + of_bitU_method ::" bitU \ 'a " + + + +definition instance_Sail_values_BitU_Sail_values_bitU_dict :: "(bitU)BitU_class " where + " instance_Sail_values_BitU_Sail_values_bitU_dict = ((| + + to_bitU_method = (\ b. b), + + of_bitU_method = (\ b. b)|) )" + + +definition bool_of_bitU :: " bitU \(bool)option " where + " bool_of_bitU = ( \x . + (case x of B0 => Some False | B1 => Some True | BU => None ) )" + + +definition bitU_of_bool :: " bool \ bitU " where + " bitU_of_bool b = ( if b then B1 else B0 )" + + +(*instance (BitU bool) + let to_bitU = bitU_of_bool + let of_bitU = bool_of_bitU +end*) + +definition cast_bit_bool :: " bitU \(bool)option " where + " cast_bit_bool = ( bool_of_bitU )" + + +definition not_bit :: " bitU \ bitU " where + " not_bit = ( \x . + (case x of B1 => B0 | B0 => B1 | BU => BU ) )" + + +(*val is_one : integer -> bitU*) +definition is_one :: " int \ bitU " where + " is_one i = ( + if i =( 1 :: int) then B1 else B0 )" + + +(*val and_bit : bitU -> bitU -> bitU*) +fun and_bit :: " bitU \ bitU \ bitU " where + " and_bit B0 _ = ( B0 )" +|" and_bit _ B0 = ( B0 )" +|" and_bit B1 B1 = ( B1 )" +|" and_bit _ _ = ( BU )" + + +(*val or_bit : bitU -> bitU -> bitU*) +fun or_bit :: " bitU \ bitU \ bitU " where + " or_bit B1 _ = ( B1 )" +|" or_bit _ B1 = ( B1 )" +|" or_bit B0 B0 = ( B0 )" +|" or_bit _ _ = ( BU )" + + +(*val xor_bit : bitU -> bitU -> bitU*) +fun xor_bit :: " bitU \ bitU \ bitU " where + " xor_bit B0 B0 = ( B0 )" +|" xor_bit B0 B1 = ( B1 )" +|" xor_bit B1 B0 = ( B1 )" +|" xor_bit B1 B1 = ( B0 )" +|" xor_bit _ _ = ( BU )" + + +(*val &. : bitU -> bitU -> bitU*) + +(*val |. : bitU -> bitU -> bitU*) + +(*val +. : bitU -> bitU -> bitU*) + + +(*** Bool lists ***) + +(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*) +fun bools_of_nat_aux :: " int \ nat \(bool)list \(bool)list " where + " bools_of_nat_aux len x acc1 = ( + if len \( 0 :: int) then acc1 + else bools_of_nat_aux (len -( 1 :: int)) (x div( 2 :: nat)) ((if (x mod( 2 :: nat)) =( 1 :: nat) then True else False) # acc1))" + +definition bools_of_nat :: " int \ nat \(bool)list " where + " bools_of_nat len n = ( bools_of_nat_aux len n [])" + (*List.reverse (bools_of_nat_aux n)*) + +(*val nat_of_bools_aux : natural -> list bool -> natural*) +fun nat_of_bools_aux :: " nat \(bool)list \ nat " where + " nat_of_bools_aux acc1 ([]) = ( acc1 )" +|" nat_of_bools_aux acc1 (True # bs) = ( nat_of_bools_aux ((( 2 :: nat) * acc1) +( 1 :: nat)) bs )" +|" nat_of_bools_aux acc1 (False # bs) = ( nat_of_bools_aux (( 2 :: nat) * acc1) bs )" + +definition nat_of_bools :: "(bool)list \ nat " where + " nat_of_bools bs = ( nat_of_bools_aux(( 0 :: nat)) bs )" + + +(*val unsigned_of_bools : list bool -> integer*) +definition unsigned_of_bools :: "(bool)list \ int " where + " unsigned_of_bools bs = ( int (nat_of_bools bs))" + + +(*val signed_of_bools : list bool -> integer*) +definition signed_of_bools :: "(bool)list \ int " where + " signed_of_bools bs = ( + (case bs of + True # _ =>( 0 :: int) - (( 1 :: int) + (unsigned_of_bools (List.map (\ x. \ x) bs))) + | False # _ => unsigned_of_bools bs + | [] =>( 0 :: int) (* Treat empty list as all zeros *) + ))" + + +(*val int_of_bools : bool -> list bool -> integer*) +definition int_of_bools :: " bool \(bool)list \ int " where + " int_of_bools sign bs = ( if sign then signed_of_bools bs else unsigned_of_bools bs )" + + +(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*) +fun pad_list :: " 'a \ 'a list \ int \ 'a list " where + " pad_list x xs n = ( + if n \( 0 :: int) then xs else pad_list x (x # xs) (n -( 1 :: int)))" + + +definition ext_list :: " 'a \ int \ 'a list \ 'a list " where + " ext_list pad len xs = ( + (let longer = (len - (int (List.length xs))) in + if longer <( 0 :: int) then List.drop (nat_of_int (abs (longer))) xs + else pad_list pad xs longer))" + + +definition extz_bools :: " int \(bool)list \(bool)list " where + " extz_bools len bs = ( ext_list False len bs )" + +definition exts_bools :: " int \(bool)list \(bool)list " where + " exts_bools len bs = ( + (case bs of + True # _ => ext_list True len bs + | _ => ext_list False len bs + ))" + + +fun add_one_bool_ignore_overflow_aux :: "(bool)list \(bool)list " where + " add_one_bool_ignore_overflow_aux ([]) = ( [])" +|" add_one_bool_ignore_overflow_aux (False # bits) = ( True # bits )" +|" add_one_bool_ignore_overflow_aux (True # bits) = ( False # add_one_bool_ignore_overflow_aux bits )" + + +definition add_one_bool_ignore_overflow :: "(bool)list \(bool)list " where + " add_one_bool_ignore_overflow bits = ( + List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)))" + + +(*let bool_list_of_int n = + let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in + if n >= (0 : integer) then bs_abs + else add_one_bool_ignore_overflow (List.map not bs_abs) +let bools_of_int len n = exts_bools len (bool_list_of_int n)*) +definition bools_of_int :: " int \ int \(bool)list " where + " bools_of_int len n = ( + (let bs_abs = (bools_of_nat len (nat (abs (abs n)))) in + if n \ (( 0 :: int) :: int) then bs_abs + else add_one_bool_ignore_overflow (List.map (\ x. \ x) bs_abs)))" + + +(*** Bit lists ***) + +(*val has_undefined_bits : list bitU -> bool*) +definition has_undefined_bits :: "(bitU)list \ bool " where + " has_undefined_bits bs = ( ((\ x \ (set bs). (\x . + (case x of BU => True | _ => False )) x)))" + + +definition bits_of_nat :: " int \ nat \(bitU)list " where + " bits_of_nat len n = ( List.map bitU_of_bool (bools_of_nat len n))" + + +definition nat_of_bits :: "(bitU)list \(nat)option " where + " nat_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (nat_of_bools bs) + | None => None + ))" + + +definition not_bits :: "(bitU)list \(bitU)list " where + " not_bits = ( List.map not_bit )" + + +(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*) +definition binop_list :: "('a \ 'a \ 'a)\ 'a list \ 'a list \ 'a list " where + " binop_list op1 xs ys = ( + List.foldr ( \x . + (case x of (x, y) => \ acc1 . op1 x y # acc1 )) (List.zip xs ys) [])" + + +definition unsigned_of_bits :: "(bitU)list \(int)option " where + " unsigned_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (unsigned_of_bools bs) + | None => None + ))" + + +definition signed_of_bits :: "(bitU)list \(int)option " where + " signed_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (signed_of_bools bs) + | None => None + ))" + + +(*val int_of_bits : bool -> list bitU -> maybe integer*) +definition int_of_bits :: " bool \(bitU)list \(int)option " where + " int_of_bits sign bs = ( if sign then signed_of_bits bs else unsigned_of_bits bs )" + + +definition extz_bits :: " int \(bitU)list \(bitU)list " where + " extz_bits len bits = ( ext_list B0 len bits )" + +definition exts_bits :: " int \(bitU)list \(bitU)list " where + " exts_bits len bits = ( + (case bits of + BU # _ => ext_list BU len bits + | B1 # _ => ext_list B1 len bits + | _ => ext_list B0 len bits + ))" + + +fun add_one_bit_ignore_overflow_aux :: "(bitU)list \(bitU)list " where + " add_one_bit_ignore_overflow_aux ([]) = ( [])" +|" add_one_bit_ignore_overflow_aux (B0 # bits) = ( B1 # bits )" +|" add_one_bit_ignore_overflow_aux (B1 # bits) = ( B0 # add_one_bit_ignore_overflow_aux bits )" +|" add_one_bit_ignore_overflow_aux (BU # bits) = ( BU # List.map ( \x . + (case x of _ => BU )) bits )" + + +definition add_one_bit_ignore_overflow :: "(bitU)list \(bitU)list " where + " add_one_bit_ignore_overflow bits = ( + List.rev (add_one_bit_ignore_overflow_aux (List.rev bits)))" + + +(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n) +let bits_of_int len n = exts_bits len (bit_list_of_int n)*) +definition bits_of_int :: " int \ int \(bitU)list " where + " bits_of_int len n = ( List.map bitU_of_bool (bools_of_int len n))" + + +(*val arith_op_bits : + (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*) +definition arith_op_bits :: "(int \ int \ int)\ bool \(bitU)list \(bitU)list \(bitU)list " where + " arith_op_bits op1 sign l r = ( + (case (int_of_bits sign l, int_of_bits sign r) of + (Some li, Some ri) => bits_of_int (int (List.length l)) (op1 li ri) + | (_, _) => repeat [BU] (int (List.length l)) + ))" + + +definition char_of_nibble :: " bitU*bitU*bitU*bitU \(char)option " where + " char_of_nibble = ( \x . + (case x of + (B0, B0, B0, B0) => Some (CHR ''0'') + | (B0, B0, B0, B1) => Some (CHR ''1'') + | (B0, B0, B1, B0) => Some (CHR ''2'') + | (B0, B0, B1, B1) => Some (CHR ''3'') + | (B0, B1, B0, B0) => Some (CHR ''4'') + | (B0, B1, B0, B1) => Some (CHR ''5'') + | (B0, B1, B1, B0) => Some (CHR ''6'') + | (B0, B1, B1, B1) => Some (CHR ''7'') + | (B1, B0, B0, B0) => Some (CHR ''8'') + | (B1, B0, B0, B1) => Some (CHR ''9'') + | (B1, B0, B1, B0) => Some (CHR ''A'') + | (B1, B0, B1, B1) => Some (CHR ''B'') + | (B1, B1, B0, B0) => Some (CHR ''C'') + | (B1, B1, B0, B1) => Some (CHR ''D'') + | (B1, B1, B1, B0) => Some (CHR ''E'') + | (B1, B1, B1, B1) => Some (CHR ''F'') + | _ => None + ) )" + + +fun hexstring_of_bits :: "(bitU)list \((char)list)option " where + " hexstring_of_bits (b1 # b2 # b3 # b4 # bs) = ( + (let n = (char_of_nibble (b1, b2, b3, b4)) in + (let s = (hexstring_of_bits bs) in + (case (n, s) of + (Some n, Some s) => Some (n # s) + | _ => None + ))))" +|" hexstring_of_bits ([]) = ( Some [])" +|" hexstring_of_bits _ = ( None )" + + +definition show_bitlist :: "(bitU)list \ string " where + " show_bitlist bs = ( + (case hexstring_of_bits bs of + Some s => ((CHR ''0'') # ((CHR ''x'') # s)) + | None => ((CHR ''0'') # ((CHR ''b'') # List.map bitU_char bs)) + ))" + + +(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*) +definition subrange_list_inc :: " 'a list \ int \ int \ 'a list " where + " subrange_list_inc xs i j = ( + (let (toJ,suffix0) = (split_at (nat_of_int (j +( 1 :: int))) xs) in + (let (prefix0,fromItoJ) = (split_at (nat_of_int i) toJ) in + fromItoJ)))" + + +(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*) +definition subrange_list_dec :: " 'a list \ int \ int \ 'a list " where + " subrange_list_dec xs i j = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + subrange_list_inc xs (top1 - i) (top1 - j)))" + + +(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*) +definition subrange_list :: " bool \ 'a list \ int \ int \ 'a list " where + " subrange_list is_inc xs i j = ( if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j )" + + +(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list_inc :: " 'a list \ int \ int \ 'a list \ 'a list " where + " update_subrange_list_inc xs i j xs' = ( + (let (toJ,suffix) = (split_at (nat_of_int (j +( 1 :: int))) xs) in + (let (prefix,fromItoJ0) = (split_at (nat_of_int i) toJ) in + (prefix @ xs') @ suffix)))" + + +(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list_dec :: " 'a list \ int \ int \ 'a list \ 'a list " where + " update_subrange_list_dec xs i j xs' = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + update_subrange_list_inc xs (top1 - i) (top1 - j) xs'))" + + +(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list :: " bool \ 'a list \ int \ int \ 'a list \ 'a list " where + " update_subrange_list is_inc xs i j xs' = ( + if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' )" + + +(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*) +definition access_list_inc :: " 'a list \ int \ 'a " where + " access_list_inc xs n = ( List.nth xs (nat_of_int n))" + + +(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*) +definition access_list_dec :: " 'a list \ int \ 'a " where + " access_list_dec xs n = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + access_list_inc xs (top1 - n)))" + + +(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*) +definition access_list :: " bool \ 'a list \ int \ 'a " where + " access_list is_inc xs n = ( + if is_inc then access_list_inc xs n else access_list_dec xs n )" + + +(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*) +definition update_list_inc :: " 'a list \ int \ 'a \ 'a list " where + " update_list_inc xs n x = ( List.list_update xs (nat_of_int n) x )" + + +(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*) +definition update_list_dec :: " 'a list \ int \ 'a \ 'a list " where + " update_list_dec xs n x = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + update_list_inc xs (top1 - n) x))" + + +(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*) +definition update_list :: " bool \ 'a list \ int \ 'a \ 'a list " where + " update_list is_inc xs n x = ( + if is_inc then update_list_inc xs n x else update_list_dec xs n x )" + + +definition extract_only_bit :: "(bitU)list \ bitU " where + " extract_only_bit = ( \x . + (case x of [] => BU | [e] => e | _ => BU ) )" + + +(*** Machine words *) + +(*val length_mword : forall 'a. mword 'a -> integer*) + +(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword_dec :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " slice_mword_dec w i j = ( Word.slice (nat_of_int i) w )" + + +(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword_inc :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " slice_mword_inc w i j = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + slice_mword_dec w (top1 - i) (top1 - j)))" + + +(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword :: " bool \('a::len)Word.word \ int \ int \('b::len)Word.word " where + " slice_mword is_inc w i j = ( if is_inc then slice_mword_inc w i j else slice_mword_dec w i j )" + + +(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword_dec :: "('a::len)Word.word \ int \ int \('b::len)Word.word \('a::len)Word.word " where + " update_slice_mword_dec w i j w' = ( Lem.word_update w (nat_of_int i) (nat_of_int j) w' )" + + +(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword_inc :: "('a::len)Word.word \ int \ int \('b::len)Word.word \('a::len)Word.word " where + " update_slice_mword_inc w i j w' = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + update_slice_mword_dec w (top1 - i) (top1 - j) w'))" + + +(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword :: " bool \('a::len)Word.word \ int \ int \('b::len)Word.word \('a::len)Word.word " where + " update_slice_mword is_inc w i j w' = ( + if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' )" + + +(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*) +definition access_mword_dec :: "('a::len)Word.word \ int \ bitU " where + " access_mword_dec w n = ( bitU_of_bool (Bits.test_bit w (nat_of_int n)))" + + +(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*) +definition access_mword_inc :: "('a::len)Word.word \ int \ bitU " where + " access_mword_inc w n = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + access_mword_dec w (top1 - n)))" + + +(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*) +definition access_mword :: " bool \('a::len)Word.word \ int \ bitU " where + " access_mword is_inc w n = ( + if is_inc then access_mword_inc w n else access_mword_dec w n )" + + +(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*) +definition update_mword_bool_dec :: "('a::len)Word.word \ int \ bool \('a::len)Word.word " where + " update_mword_bool_dec w n b = ( Bits.set_bit w (nat_of_int n) b )" + +definition update_mword_dec :: "('a::len)Word.word \ int \ bitU \(('a::len)Word.word)option " where + " update_mword_dec w n b = ( map_option (update_mword_bool_dec w n) (bool_of_bitU b))" + + +(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*) +definition update_mword_bool_inc :: "('a::len)Word.word \ int \ bool \('a::len)Word.word " where + " update_mword_bool_inc w n b = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + update_mword_bool_dec w (top1 - n) b))" + +definition update_mword_inc :: "('a::len)Word.word \ int \ bitU \(('a::len)Word.word)option " where + " update_mword_inc w n b = ( map_option (update_mword_bool_inc w n) (bool_of_bitU b))" + + +(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*) +definition int_of_mword :: " bool \('a::len)Word.word \ int " where + " int_of_mword sign w = ( + if sign then Word.sint w else Word.uint w )" + + +(* Translating between a type level number (itself 'n) and an integer *) + +definition size_itself_int :: "('a::len)itself \ int " where + " size_itself_int x = ( int (size_itself x))" + + +(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), + the actual integer is ignored. *) + +(*val make_the_value : forall 'n. integer -> itself 'n*) +definition make_the_value :: " int \('n::len)itself " where + " make_the_value _ = ( TYPE(_) )" + + +(*** Bitvectors *) + +record 'a Bitvector_class= + + bits_of_method ::" 'a \ bitU list " + + (* We allow of_bits to be partial, as not all bitvector representations + support undefined bits *) + of_bits_method ::" bitU list \ 'a option " + + of_bools_method ::" bool list \ 'a " + + length_method ::" 'a \ int " + + (* of_int: the first parameter specifies the desired length of the bitvector *) + of_int_method ::" int \ int \ 'a " + + (* Conversion to integers is undefined if any bit is undefined *) + unsigned_method ::" 'a \ int option " + + signed_method ::" 'a \ int option " + + (* Lifting of integer operations to bitvectors: The boolean flag indicates + whether to treat the bitvectors as signed (true) or not (false). *) + arith_op_bv_method ::" (int \ int \ int) \ bool \ 'a \ 'a \ 'a " + + + +(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*) +definition of_bits_failwith :: " 'a Bitvector_class \(bitU)list \ 'a " where + " of_bits_failwith dict_Sail_values_Bitvector_a bits = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_a) bits))" + + +definition int_of_bv :: " 'a Bitvector_class \ bool \ 'a \(int)option " where + " int_of_bv dict_Sail_values_Bitvector_a sign = ( if sign then + (signed_method dict_Sail_values_Bitvector_a) else (unsigned_method dict_Sail_values_Bitvector_a) )" + + +definition instance_Sail_values_Bitvector_list_dict :: " 'a BitU_class \('a list)Bitvector_class " where + " instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a = ((| + + bits_of_method = (\ v. List.map + (to_bitU_method dict_Sail_values_BitU_a) v), + + of_bits_method = (\ v. Some (List.map + (of_bitU_method dict_Sail_values_BitU_a) v)), + + of_bools_method = (\ v. List.map + (of_bitU_method dict_Sail_values_BitU_a) (List.map bitU_of_bool v)), + + length_method = (\ xs. int (List.length xs)), + + of_int_method = (\ len n. List.map + (of_bitU_method dict_Sail_values_BitU_a) (bits_of_int len n)), + + unsigned_method = (\ v. unsigned_of_bits (List.map + (to_bitU_method dict_Sail_values_BitU_a) v)), + + signed_method = (\ v. signed_of_bits (List.map + (to_bitU_method dict_Sail_values_BitU_a) v)), + + arith_op_bv_method = (\ op1 sign l r. List.map + (of_bitU_method dict_Sail_values_BitU_a) (arith_op_bits op1 sign (List.map + (to_bitU_method dict_Sail_values_BitU_a) l) (List.map (to_bitU_method dict_Sail_values_BitU_a) r)))|) )" + + +definition instance_Sail_values_Bitvector_Machine_word_mword_dict :: "(('a::len)Word.word)Bitvector_class " where + " instance_Sail_values_Bitvector_Machine_word_mword_dict = ((| + + bits_of_method = (\ v. List.map bitU_of_bool (Word.to_bl v)), + + of_bits_method = (\ v. map_option Word.of_bl (just_list (List.map bool_of_bitU v))), + + of_bools_method = (\ v. Word.of_bl v), + + length_method = (\ v. int (size v)), + + of_int_method = ( \x . + (case x of _ => \ n . Word.word_of_int n )), + + unsigned_method = (\ v. Some (Word.uint v)), + + signed_method = (\ v. Some (Word.sint v)), + + arith_op_bv_method = (\ op1 sign l r. Word.word_of_int (op1 (int_of_mword sign l) (int_of_mword sign r)))|) )" + + +definition access_bv_inc :: " 'a Bitvector_class \ 'a \ int \ bitU " where + " access_bv_inc dict_Sail_values_Bitvector_a v n = ( access_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + +definition access_bv_dec :: " 'a Bitvector_class \ 'a \ int \ bitU " where + " access_bv_dec dict_Sail_values_Bitvector_a v n = ( access_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + + +definition update_bv_inc :: " 'a Bitvector_class \ 'a \ int \ bitU \(bitU)list " where + " update_bv_inc dict_Sail_values_Bitvector_a v n b = ( update_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + +definition update_bv_dec :: " 'a Bitvector_class \ 'a \ int \ bitU \(bitU)list " where + " update_bv_dec dict_Sail_values_Bitvector_a v n b = ( update_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + + +definition subrange_bv_inc :: " 'a Bitvector_class \ 'a \ int \ int \(bitU)list " where + " subrange_bv_inc dict_Sail_values_Bitvector_a v i j = ( subrange_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + +definition subrange_bv_dec :: " 'a Bitvector_class \ 'a \ int \ int \(bitU)list " where + " subrange_bv_dec dict_Sail_values_Bitvector_a v i j = ( subrange_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + + +definition update_subrange_bv_inc :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ int \ int \ 'a \(bitU)list " where + " update_subrange_bv_inc dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list True ( + (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + +definition update_subrange_bv_dec :: " 'a Bitvector_class \ 'b Bitvector_class \ 'b \ int \ int \ 'a \(bitU)list " where + " update_subrange_bv_dec dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list False ( + (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + + +(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) +definition extz_bv :: " 'a Bitvector_class \ int \ 'a \(bitU)list " where + " extz_bv dict_Sail_values_Bitvector_a n v = ( extz_bits n ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) +definition exts_bv :: " 'a Bitvector_class \ int \ 'a \(bitU)list " where + " exts_bv dict_Sail_values_Bitvector_a n v = ( exts_bits n ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*) +definition string_of_bv :: " 'a Bitvector_class \ 'a \ string " where + " string_of_bv dict_Sail_values_Bitvector_a v = ( show_bitlist ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*** Bytes and addresses *) + +type_synonym memory_byte =" bitU list " + +(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*) +fun byte_chunks :: " 'a list \(('a list)list)option " where + " byte_chunks ([]) = ( Some [])" +|" byte_chunks (a # b # c # d # e # f # g # h # rest) = ( + Option.bind (byte_chunks rest) (\ rest . Some ([a,b,c,d,e,f,g,h] # rest)))" +|" byte_chunks _ = ( None )" + + +(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*) +definition bytes_of_bits :: " 'a Bitvector_class \ 'a \(((bitU)list)list)option " where + " bytes_of_bits dict_Sail_values_Bitvector_a bs = ( byte_chunks ( + (bits_of_method dict_Sail_values_Bitvector_a) bs))" + + +(*val bits_of_bytes : list memory_byte -> list bitU*) +definition bits_of_bytes :: "((bitU)list)list \(bitU)list " where + " bits_of_bytes bs = ( List.concat (List.map (\ v. List.map (\ b. b) v) bs))" + + +definition mem_bytes_of_bits :: " 'a Bitvector_class \ 'a \(((bitU)list)list)option " where + " mem_bytes_of_bits dict_Sail_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits + dict_Sail_values_Bitvector_a bs))" + +definition bits_of_mem_bytes :: "((bitU)list)list \(bitU)list " where + " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))" + + +(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU +let bitv_of_byte_lifteds v = + foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v + +val bitv_of_bytes : list Sail_impl_base.byte -> list bitU +let bitv_of_bytes v = + foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v + +val byte_lifteds_of_bitv : list bitU -> list byte_lifted +let byte_lifteds_of_bitv bits = + let bits = List.map bit_lifted_of_bitU bits in + byte_lifteds_of_bit_lifteds bits + +val bytes_of_bitv : list bitU -> list byte +let bytes_of_bitv bits = + let bits = List.map bit_of_bitU bits in + bytes_of_bits bits + +val bit_lifteds_of_bitUs : list bitU -> list bit_lifted +let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits + +val bit_lifteds_of_bitv : list bitU -> list bit_lifted +let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v + + +val address_lifted_of_bitv : list bitU -> address_lifted +let address_lifted_of_bitv v = + let byte_lifteds = byte_lifteds_of_bitv v in + let maybe_address_integer = + match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with + | Just bs -> Just (integer_of_byte_list bs) + | _ -> Nothing + end in + Address_lifted byte_lifteds maybe_address_integer + +val bitv_of_address_lifted : address_lifted -> list bitU +let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs + +val address_of_bitv : list bitU -> address +let address_of_bitv v = + let bytes = bytes_of_bitv v in + address_of_byte_list bytes*) + +function (sequential,domintros) reverse_endianness_list :: " 'a list \ 'a list " where + " reverse_endianness_list bits = ( + if List.length bits \( 8 :: nat) then bits else + reverse_endianness_list (drop_list(( 8 :: int)) bits) @ take_list(( 8 :: int)) bits )" +by pat_completeness auto + + + +(*** Registers *) + +(*type register_field = string +type register_field_index = string * (integer * integer) (* name, start and end *) + +type register = + | Register of string * (* name *) + integer * (* length *) + integer * (* start index *) + bool * (* is increasing *) + list register_field_index + | UndefinedRegister of integer (* length *) + | RegisterPair of register * register*) + +record( 'regstate, 'regval, 'a) register_ref = + + name ::" string " + + (*is_inc : bool;*) + read_from ::" 'regstate \ 'a " + + write_to ::" 'a \ 'regstate \ 'regstate " + + of_regval ::" 'regval \ 'a option " + + regval_of ::" 'a \ 'regval " + + +(* Register accessors: pair of functions for reading and writing register values *) +type_synonym( 'regstate, 'regval) register_accessors =" + ((string \ 'regstate \ 'regval option) * + (string \ 'regval \ 'regstate \ 'regstate option))" + +record( 'regtype, 'a) field_ref = + + field_name ::" string " + + field_start ::" int " + + field_is_inc ::" bool " + + get_field ::" 'regtype \ 'a " + + set_field ::" 'regtype \ 'a \ 'regtype " + + +(*let name_of_reg = function + | Register name _ _ _ _ -> name + | UndefinedRegister _ -> failwith name_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith name_of_reg RegisterPair +end + +let size_of_reg = function + | Register _ size _ _ _ -> size + | UndefinedRegister size -> size + | RegisterPair _ _ -> failwith size_of_reg RegisterPair +end + +let start_of_reg = function + | Register _ _ start _ _ -> start + | UndefinedRegister _ -> failwith start_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith start_of_reg RegisterPair +end + +let is_inc_of_reg = function + | Register _ _ _ is_inc _ -> is_inc + | UndefinedRegister _ -> failwith is_inc_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith in_inc_of_reg RegisterPair +end + +let dir_of_reg = function + | Register _ _ _ is_inc _ -> dir_of_bool is_inc + | UndefinedRegister _ -> failwith dir_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith dir_of_reg RegisterPair +end + +let size_of_reg_nat reg = natFromInteger (size_of_reg reg) +let start_of_reg_nat reg = natFromInteger (start_of_reg reg) + +val register_field_indices_aux : register -> register_field -> maybe (integer * integer) +let rec register_field_indices_aux register rfield = + match register with + | Register _ _ _ _ rfields -> List.lookup rfield rfields + | RegisterPair r1 r2 -> + let m_indices = register_field_indices_aux r1 rfield in + if isJust m_indices then m_indices else register_field_indices_aux r2 rfield + | UndefinedRegister _ -> Nothing + end + +val register_field_indices : register -> register_field -> integer * integer +let register_field_indices register rfield = + match register_field_indices_aux register rfield with + | Just indices -> indices + | Nothing -> failwith Invalid register/register-field combination + end + +let register_field_indices_nat reg regfield= + let (i,j) = register_field_indices reg regfield in + (natFromInteger i,natFromInteger j)*) + +(*let rec external_reg_value reg_name v = + let (internal_start, external_start, direction) = + match reg_name with + | Reg _ start size dir -> + (start, (if dir = D_increasing then start else (start - (size +1))), dir) + | Reg_slice _ reg_start dir (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_field _ reg_start dir _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_f_slice _ reg_start dir _ _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + end in + let bits = bit_lifteds_of_bitv v in + <| rv_bits = bits; + rv_dir = direction; + rv_start = external_start; + rv_start_internal = internal_start |> + +val internal_reg_value : register_value -> list bitU +let internal_reg_value v = + List.map bitU_of_bit_lifted v.rv_bits + (*(integerFromNat v.rv_start_internal) + (v.rv_dir = D_increasing)*) + + +let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) = + match d with + (*This is the case the thread/concurrecny model expects, so no change needed*) + | D_increasing -> (i,j) + | D_decreasing -> let slice_i = start - i in + let slice_j = (i - j) + slice_i in + (slice_i,slice_j) + end *) + +(* TODO +let external_reg_whole r = + Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc) + +let external_reg_slice r (i,j) = + let start = natFromInteger r.start in + let dir = dir_of_bool r.is_inc in + Reg_slice (r.name) start dir (external_slice dir start (i,j)) + +let external_reg_field_whole reg rfield = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n)) + +let external_reg_field_slice reg rfield (i,j) = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_f_slice (name_of_reg reg) start dir rfield + (external_slice dir start (m,n)) + (external_slice dir start (i,j))*) + +(*val external_mem_value : list bitU -> memory_value +let external_mem_value v = + byte_lifteds_of_bitv v $> List.reverse + +val internal_mem_value : memory_value -> list bitU +let internal_mem_value bytes = + List.reverse bytes $> bitv_of_byte_lifteds*) + + +(*val foreach : forall 'a 'vars. + (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*) +fun foreach :: " 'a list \ 'vars \('a \ 'vars \ 'vars)\ 'vars " where + " foreach ([]) vars body = ( vars )" +|" foreach (x # xs) vars body = ( foreach xs (body x vars) body )" + + +(*val index_list : integer -> integer -> integer -> list integer*) +function (sequential,domintros) index_list :: " int \ int \ int \(int)list " where + " index_list from1 to1 step = ( + if ((step >( 0 :: int)) \ (from1 \ to1)) \ ((step <( 0 :: int)) \ (to1 \ from1)) then + from1 # index_list (from1 + step) to1 step + else [])" +by pat_completeness auto + + +(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) +function (sequential,domintros) while :: " 'vars \('vars \ bool)\('vars \ 'vars)\ 'vars " where + " while vars cond body = ( + if cond vars then while (body vars) cond body else vars )" +by pat_completeness auto + + +(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) +function (sequential,domintros) until :: " 'vars \('vars \ bool)\('vars \ 'vars)\ 'vars " where + " until vars cond body = ( + (let vars = (body vars) in + if cond vars then vars else until (body vars) cond body))" +by pat_completeness auto + + + +(* convert numbers unsafely to naturals *) + +record 'a ToNatural_class= + toNatural_method ::" 'a \ nat " + +(* eta-expanded for Isabelle output, otherwise it breaks *) +definition instance_Sail_values_ToNatural_Num_integer_dict :: "(int)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_integer_dict = ((| + + toNatural_method = (\ n . nat (abs n))|) )" + +definition instance_Sail_values_ToNatural_Num_int_dict :: "(int)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_int_dict = ((| + + toNatural_method = (\ n . (nat (abs n)))|) )" + +definition instance_Sail_values_ToNatural_nat_dict :: "(nat)ToNatural_class " where + " instance_Sail_values_ToNatural_nat_dict = ((| + + toNatural_method = (\ n . n)|) )" + +definition instance_Sail_values_ToNatural_Num_natural_dict :: "(nat)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_natural_dict = ((| + + toNatural_method = (\ n . n)|) )" + + +fun toNaturalFiveTup :: " 'a ToNatural_class \ 'b ToNatural_class \ 'c ToNatural_class \ 'd ToNatural_class \ 'e ToNatural_class \ 'd*'c*'b*'a*'e \ nat*nat*nat*nat*nat " where + " toNaturalFiveTup dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5) = ( + ((toNatural_method dict_Sail_values_ToNatural_d) n1,(toNatural_method dict_Sail_values_ToNatural_c) n2,(toNatural_method dict_Sail_values_ToNatural_b) n3,(toNatural_method dict_Sail_values_ToNatural_a) n4,(toNatural_method dict_Sail_values_ToNatural_e) n5))" + + +(* Let the following types be generated by Sail per spec, using either bitlists + or machine words as bitvector representation *) +(*type regfp = + | RFull of (string) + | RSlice of (string * integer * integer) + | RSliceBit of (string * integer) + | RField of (string * string) + +type niafp = + | NIAFP_successor + | NIAFP_concrete_address of vector bitU + | NIAFP_indirect_address + +(* only for MIPS *) +type diafp = + | DIAFP_none + | DIAFP_concrete of vector bitU + | DIAFP_reg of regfp + +let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function + | RFull name -> + let (start,length,direction,_) = reg_info name Nothing in + Reg name start length direction + | RSlice (name,i,j) -> + let i = natFromInteger i in + let j = natFromInteger j in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,j) in + Reg_slice name start direction slice + | RSliceBit (name,i) -> + let i = natFromInteger i in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,i) in + Reg_slice name start direction slice + | RField (name,field_name) -> + let (start,length,direction,span) = reg_info name (Just field_name) in + let slice = external_slice direction start span in + Reg_field name start direction field_name slice +end + +let niafp_to_nia reginfo = function + | NIAFP_successor -> NIA_successor + | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v) + | NIAFP_indirect_address -> NIA_indirect_address +end + +let diafp_to_dia reginfo = function + | DIAFP_none -> DIA_none + | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v) + | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r) +end +*) +end diff --git a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy new file mode 100644 index 00000000..dd008695 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy @@ -0,0 +1,206 @@ +theory Sail_values_lemmas + imports Sail_values +begin + +lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def) + +termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def) + +termination index_list + by (relation "measure (\(i, j, step). nat ((j - i + step) * sgn step))") auto + +lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto + +lemma just_list_None_iff[simp]: "just_list xs = None \ None \ set xs" + by (induction xs) (auto split: option.splits) + +lemma just_list_Some_iff[simp]: "just_list xs = Some ys \ xs = map Some ys" + by (induction xs arbitrary: ys) (auto split: option.splits) + +lemma just_list_cases: + assumes "just_list xs = y" + obtains (None) "None \ set xs" and "y = None" + | (Some) ys where "xs = map Some ys" and "y = Some ys" + using assms by (cases y) auto + +lemma repeat_singleton_replicate[simp]: + "repeat [x] n = replicate (nat n) x" +proof (induction n) + case (nonneg n) + have "nat (1 + int m) = Suc m" for m by auto + then show ?case by (induction n) auto +next + case (neg n) + then show ?case by auto +qed + +lemma bool_of_bitU_simps[simp]: + "bool_of_bitU B0 = Some False" + "bool_of_bitU B1 = Some True" + "bool_of_bitU BU = None" + by (auto simp: bool_of_bitU_def) + +lemma bitops_bitU_of_bool[simp]: + "and_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \ y)" + "or_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \ y)" + "xor_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool ((x \ y) \ \(x \ y))" + "not_bit (bitU_of_bool x) = bitU_of_bool (\x)" + "not_bit \ bitU_of_bool = bitU_of_bool \ Not" + by (auto simp: bitU_of_bool_def not_bit_def) + +lemma image_bitU_of_bool_B0_B1: "bitU_of_bool ` bs \ {B0, B1}" + by (auto simp: bitU_of_bool_def split: if_splits) + +lemma bool_of_bitU_bitU_of_bool[simp]: + "bool_of_bitU \ bitU_of_bool = Some" + "bool_of_bitU \ (bitU_of_bool \ f) = Some \ f" + "bool_of_bitU (bitU_of_bool x) = Some x" + by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+ + +abbreviation "BC_bitU_list \ instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict" +lemmas BC_bitU_list_def = instance_Sail_values_Bitvector_list_dict_def instance_Sail_values_BitU_Sail_values_bitU_dict_def +abbreviation "BC_mword \ instance_Sail_values_Bitvector_Machine_word_mword_dict" +lemmas BC_mword_defs = instance_Sail_values_Bitvector_Machine_word_mword_dict_def + access_mword_def access_mword_inc_def access_mword_dec_def + (*update_mword_def update_mword_inc_def update_mword_dec_def*) + subrange_list_def subrange_list_inc_def subrange_list_dec_def + update_subrange_list_def update_subrange_list_inc_def update_subrange_list_dec_def + +declare size_itself_int_def[simp] +declare size_itself_def[simp] +declare word_size[simp] + +lemma int_of_mword_simps[simp]: + "int_of_mword False w = uint w" + "int_of_mword True w = sint w" + "int_of_bv BC_mword False w = Some (uint w)" + "int_of_bv BC_mword True w = Some (sint w)" + by (auto simp: int_of_mword_def int_of_bv_def BC_mword_defs) + +lemma BC_mword_simps[simp]: + "unsigned_method BC_mword a = Some (uint a)" + "signed_method BC_mword a = Some (sint a)" + "length_method BC_mword (a :: ('a :: len) word) = int (LENGTH('a))" + by (auto simp: BC_mword_defs) + +lemma of_bits_mword_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "of_bits_method BC_mword bus = Some (of_bl bs)" + and "of_bits_failwith BC_mword bus = of_bl bs" + using assms by (auto simp: BC_mword_defs of_bits_failwith_def maybe_failwith_def) + +lemma nat_of_bits_aux_bl_to_bin_aux: + "nat_of_bools_aux acc bs = nat (bl_to_bin_aux bs (int acc))" + by (induction acc bs rule: nat_of_bools_aux.induct) + (auto simp: Bit_def intro!: arg_cong[where f = nat] arg_cong2[where f = bl_to_bin_aux] split: if_splits) + +lemma nat_of_bits_bl_to_bin[simp]: + "nat_of_bools bs = nat (bl_to_bin bs)" + by (auto simp: nat_of_bools_def bl_to_bin_def nat_of_bits_aux_bl_to_bin_aux) + +lemma unsigned_bits_of_mword[simp]: + "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)" + by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def) + +lemma bits_of_bitU_list[simp]: + "bits_of_method BC_bitU_list v = v" + "of_bits_method BC_bitU_list v = Some v" + by (auto simp: BC_bitU_list_def) + +lemma subrange_list_inc_drop_take: + "subrange_list_inc xs i j = drop (nat i) (take (nat (j + 1)) xs)" + by (auto simp: subrange_list_inc_def split_at_def) + +lemma subrange_list_dec_drop_take: + assumes "i \ 0" and "j \ 0" + shows "subrange_list_dec xs i j = drop (length xs - nat (i + 1)) (take (length xs - nat j) xs)" + using assms unfolding subrange_list_dec_def + by (auto simp: subrange_list_inc_drop_take add.commute diff_diff_add nat_minus_as_int) + +lemma update_subrange_list_inc_drop_take: + assumes "i \ 0" and "j \ i" + shows "update_subrange_list_inc xs i j xs' = take (nat i) xs @ xs' @ drop (nat (j + 1)) xs" + using assms unfolding update_subrange_list_inc_def + by (auto simp: split_at_def min_def) + +lemma update_subrange_list_dec_drop_take: + assumes "j \ 0" and "i \ j" + shows "update_subrange_list_dec xs i j xs' = take (length xs - nat (i + 1)) xs @ xs' @ drop (length xs - nat j) xs" + using assms unfolding update_subrange_list_dec_def update_subrange_list_inc_def + by (auto simp: split_at_def min_def Let_def add.commute diff_diff_add nat_minus_as_int) + +declare access_list_inc_def[simp] + +lemma access_list_dec_rev_nth: + assumes "0 \ i" and "nat i < length xs" + shows "access_list_dec xs i = rev xs ! (nat i)" + using assms + by (auto simp: access_list_dec_def rev_nth intro!: arg_cong2[where f = List.nth]) + +lemma access_bv_dec_mword[simp]: + fixes w :: "('a::len) word" + assumes "0 \ n" and "nat n < LENGTH('a)" + shows "access_bv_dec BC_mword w n = bitU_of_bool (w !! (nat n))" + using assms unfolding access_bv_dec_def access_list_def + by (auto simp: access_list_dec_rev_nth BC_mword_defs rev_map test_bit_bl) + +lemma access_list_dec_nth[simp]: + assumes "0 \ i" + shows "access_list_dec xs i = xs ! (length xs - nat (i + 1))" + using assms + by (auto simp: access_list_dec_def add.commute diff_diff_add nat_minus_as_int) + +lemma update_list_inc_update[simp]: + "update_list_inc xs n x = xs[nat n := x]" + by (auto simp: update_list_inc_def) + +lemma update_list_dec_update[simp]: + "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]" + by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int) + +lemma bools_of_nat_aux_simps[simp]: + "\len. len \ 0 \ bools_of_nat_aux len x acc = acc" + "\len. bools_of_nat_aux (int (Suc len)) x acc = + bools_of_nat_aux (int len) (x div 2) ((if x mod 2 = 1 then True else False) # acc)" + by auto +declare bools_of_nat_aux.simps[simp del] + +lemma bools_of_nat_aux_bin_to_bl_aux: + "bools_of_nat_aux len n acc = bin_to_bl_aux (nat len) (int n) acc" +proof (cases len) + case (nonneg len') + show ?thesis unfolding nonneg + proof (induction len' arbitrary: n acc) + case (Suc len'' n acc) + then show ?case + using zmod_int[of n 2] + by (auto simp del: of_nat_simps simp add: bin_rest_def bin_last_def zdiv_int) + qed auto +qed auto + +lemma bools_of_nat_bin_to_bl[simp]: + "bools_of_nat len n = bin_to_bl (nat len) (int n)" + by (auto simp: bools_of_nat_def bools_of_nat_aux_bin_to_bl_aux) + +lemma add_one_bool_ignore_overflow_aux_rbl_succ[simp]: + "add_one_bool_ignore_overflow_aux xs = rbl_succ xs" + by (induction xs) auto + +lemma add_one_bool_ignore_overflow_rbl_succ[simp]: + "add_one_bool_ignore_overflow xs = rev (rbl_succ (rev xs))" + unfolding add_one_bool_ignore_overflow_def by auto + +lemma map_Not_bin_to_bl: + "map Not (bin_to_bl_aux len n acc) = bin_to_bl_aux len (-n - 1) (map Not acc)" +proof (induction len arbitrary: n acc) + case (Suc len n acc) + moreover have "(- (n div 2) - 1) = ((-n - 1) div 2)" by auto + moreover have "(n mod 2 = 0) = ((- n - 1) mod 2 = 1)" by presburger + ultimately show ?case by (auto simp: bin_rest_def bin_last_def) +qed auto + +lemma bools_of_int_bin_to_bl[simp]: + "bools_of_int (int len) n = bin_to_bl len n" + by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def]) + +end diff --git a/snapshots/isabelle/lib/sail/State.thy b/snapshots/isabelle/lib/sail/State.thy new file mode 100644 index 00000000..9d460e8e --- /dev/null +++ b/snapshots/isabelle/lib/sail/State.thy @@ -0,0 +1,102 @@ +chapter \Generated by Lem from ../../src/gen_lib/state.lem.\ + +theory "State" + +imports + Main + "Lem_pervasives_extra" + "Sail_values" + "Prompt_monad" + "Prompt" + "State_monad" + "State_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_values*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State_monad*) +(*open import {isabelle} `State_monad_lemmas`*) + +(* State monad wrapper around prompt monad *) + +(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*) +function (sequential,domintros) liftState :: "(string \ 'regs \ 'regval option)*(string \ 'regval \ 'regs \ 'regs option)\('regval,'a,'e)monad \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " liftState ra (Done a) = ( returnS a )" +|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) rk a sz) (\ v . liftState ra (k v)))" +|" liftState ra (Read_tag t k) = ( bindS (read_tagS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) t) (\ v . liftState ra (k v)))" +|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a) (\ v . liftState ra (k v)))" +|" liftState ra (Write_tag a t k) = ( bindS (write_tagS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) a t) (\ v . liftState ra (k v)))" +|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r) (\ v . liftState ra (k v)))" +|" liftState ra (Excl_res k) = ( bindS (excl_resultS () ) (\ v . liftState ra (k v)))" +|" liftState ra (Undefined k) = ( bindS (undefined_boolS () ) (\ v . liftState ra (k v)))" +|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) wk a sz) (liftState ra k))" +|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v) (liftState ra k))" +|" liftState ra (Footprint k) = ( liftState ra k )" +|" liftState ra (Barrier _ k) = ( liftState ra k )" +|" liftState ra (Print _ k) = ( liftState ra k )" +|" liftState ra (Fail descr) = ( failS descr )" +|" liftState ra (Exception e) = ( throwS e )" +by pat_completeness auto + + + +(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +fun iterS_aux :: " int \(int \ 'a \ 'rv sequential_state \(((unit),'e)result*'rv sequential_state)set)\ 'a list \('rv,(unit),'e)monadS " where + " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))" +|" iterS_aux i f ([]) = ( returnS () )" + + +(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iteriS :: "(int \ 'a \('rv,(unit),'e)monadS)\ 'a list \ 'rv sequential_state \(((unit),'e)result*'rv sequential_state)set " where + " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )" + + +(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iterS :: "('a \ 'rv sequential_state \(((unit),'e)result*'rv sequential_state)set)\ 'a list \ 'rv sequential_state \(((unit),'e)result*'rv sequential_state)set " where + " iterS f xs = ( iteriS ( \x . + (case x of _ => \ x . f x )) xs )" + + +(*val foreachS : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +fun foreachS :: " 'a list \ 'vars \('a \ 'vars \ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set)\ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set " where + " foreachS ([]) vars body = ( returnS vars )" +|" foreachS (x # xs) vars body = ( bindS + (body x vars) (\ vars . + foreachS xs vars body))" + + + +(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) whileS :: " 'vars \('vars \ 'rv sequential_state \(((bool),'e)result*'rv sequential_state)set)\('vars \ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set)\ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set " where + " whileS vars cond body s = ( + ( bindS(cond vars) (\ cond_val s' . + if cond_val then + ( bindS(body vars) (\ vars s'' . whileS vars cond body s'')) s' + else returnS vars s')) s )" +by pat_completeness auto + + +(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) untilS :: " 'vars \('vars \ 'rv sequential_state \(((bool),'e)result*'rv sequential_state)set)\('vars \ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set)\ 'rv sequential_state \(('vars,'e)result*'rv sequential_state)set " where + " untilS vars cond body s = ( + ( bindS(body vars) (\ vars s' . + ( bindS(cond vars) (\ cond_val s'' . + if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/sail/State_lemmas.thy b/snapshots/isabelle/lib/sail/State_lemmas.thy new file mode 100644 index 00000000..84b08e6c --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_lemmas.thy @@ -0,0 +1,202 @@ +theory State_lemmas + imports State +begin + +lemma All_liftState_dom: "liftState_dom (r, m)" + by (induction m) (auto intro: liftState.domintros) +termination liftState using All_liftState_dom by auto + +lemma liftState_bind[simp]: + "liftState r (bind m f) = bindS (liftState r m) (liftState r \ f)" + by (induction m f rule: bind.induct) auto + +lemma liftState_return[simp]: "liftState r (return a) = returnS a" by (auto simp: return_def) + +lemma Value_liftState_Run: + assumes "(Value a, s') \ liftState r m s" + obtains t where "Run m t a" + by (use assms in \induction r m arbitrary: s s' rule: liftState.induct\; + auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps; + blast elim: Value_bindS_elim) + +lemmas liftState_if_distrib[simp] = if_distrib[where f = "liftState ra" for ra] + +lemma liftState_throw[simp]: "liftState r (throw e) = throwS e" by (auto simp: throw_def) +lemma liftState_assert[simp]: "liftState r (assert_exp c msg) = assert_expS c msg" by (auto simp: assert_exp_def assert_expS_def) +lemma liftState_exit[simp]: "liftState r (exit0 ()) = exitS ()" by (auto simp: exit0_def exitS_def) +lemma liftState_exclResult[simp]: "liftState r (excl_result ()) = excl_resultS ()" by (auto simp: excl_result_def) +lemma liftState_barrier[simp]: "liftState r (barrier bk) = returnS ()" by (auto simp: barrier_def) +lemma liftState_footprint[simp]: "liftState r (footprint ()) = returnS ()" by (auto simp: footprint_def) +lemma liftState_undefined[simp]: "liftState r (undefined_bool ()) = undefined_boolS ()" by (auto simp: undefined_bool_def) +lemma liftState_maybe_fail[simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x" + by (auto simp: maybe_fail_def maybe_failS_def split: option.splits) + +lemma liftState_try_catch[simp]: + "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \ h)" + by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw) + +lemma liftState_early_return[simp]: + "liftState r (early_return r) = early_returnS r" + by (auto simp: early_return_def early_returnS_def) + +lemma liftState_catch_early_return[simp]: + "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)" + by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib cong: sum.case_cong) + +lemma liftState_liftR[simp]: + "liftState r (liftR m) = liftSR (liftState r m)" + by (auto simp: liftR_def liftSR_def) + +lemma liftState_try_catchR[simp]: + "liftState r (try_catchR m h) = try_catchSR (liftState r m) (liftState r \ h)" + by (auto simp: try_catchR_def try_catchSR_def sum.case_distrib cong: sum.case_cong) + +lemma liftState_read_mem_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz" + using assms + by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def split: option.splits) + +lemma liftState_read_mem[simp]: + "\a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz" + "\a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz" + by (auto simp: liftState_read_mem_BC) + +lemma liftState_write_mem_ea_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)" + using assms by (auto simp: write_mem_ea_def write_mem_eaS_def) + +lemma liftState_write_mem_ea[simp]: + "\a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)" + "\a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)" + by (auto simp: liftState_write_mem_ea_BC) + +lemma liftState_write_mem_val: + "liftState r (write_mem_val BC v) = write_mem_valS BC v" + by (auto simp: write_mem_val_def write_mem_valS_def split: option.splits) + +lemma liftState_read_reg_readS: + assumes "\s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)" + shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \ regstate)" +proof + fix s :: "'a sequential_state" + obtain rv v where "get_regval' (name reg) (regstate s) = Some rv" + and "of_regval reg rv \ Some v" and "read_from reg (regstate s) = v" + using assms unfolding bind_eq_Some_conv by blast + then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \ regstate) s" + by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def) +qed + +lemma liftState_write_reg_updateS: + assumes "\s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)" + shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))" + using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS) + +lemma liftState_iter_aux[simp]: + shows "liftState r (iter_aux i f xs) = iterS_aux i (\i x. liftState r (f i x)) xs" + by (induction i "\i x. liftState r (f i x)" xs rule: iterS_aux.induct) (auto cong: bindS_cong) + +lemma liftState_iteri[simp]: + "liftState r (iteri f xs) = iteriS (\i x. liftState r (f i x)) xs" + by (auto simp: iteri_def iteriS_def) + +lemma liftState_iter[simp]: + "liftState r (iter f xs) = iterS (liftState r \ f) xs" + by (auto simp: iter_def iterS_def) + +lemma liftState_foreachM[simp]: + "liftState r (foreachM xs vars body) = foreachS xs vars (\x vars. liftState r (body x vars))" + by (induction xs vars "\x vars. liftState r (body x vars)" rule: foreachS.induct) + (auto cong: bindS_cong) + +lemma whileS_dom_step: + assumes "whileS_dom (vars, cond, body, s)" + and "(Value True, s') \ cond vars s" + and "(Value vars', s'') \ body vars s'" + shows "whileS_dom (vars', cond, body, s'')" + by (use assms in \induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\) + (auto intro: whileS.domintros) + +lemma whileM_dom_step: + assumes "whileM_dom (vars, cond, body)" + and "Run (cond vars) t True" + and "Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + by (use assms in \induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\) + (auto intro: whileM.domintros) + +lemma whileM_dom_ex_step: + assumes "whileM_dom (vars, cond, body)" + and "\t. Run (cond vars) t True" + and "\t'. Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + using assms by (blast intro: whileM_dom_step) + +lemmas whileS_pinduct = whileS.pinduct[case_names Step] + +lemma liftState_whileM: + assumes "whileS_dom (vars, liftState r \ cond, liftState r \ body, s)" + and "whileM_dom (vars, cond, body)" + shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \ cond) (liftState r \ body) s" +proof (use assms in \induction vars "liftState r \ cond" "liftState r \ body" s rule: whileS.pinduct\) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases cond while) + case (while a s') + have "bindS (liftState r (body vars)) (liftState r \ (\vars. whileM vars cond body)) s' = + bindS (liftState r (body vars)) (\vars. whileS vars (liftState r \ cond) (liftState r \ body)) s'" + if "a" + proof (intro bindS_ext_cong, goal_cases body while') + case (while' vars' s'') + have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM]) + show "\t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run) + show "\t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run) + qed + then show ?case using while while' that IH by auto + qed auto + then show ?case by auto + qed auto +qed + + +lemma untilM_dom_step: + assumes "untilM_dom (vars, cond, body)" + and "Run (body vars) t vars'" + and "Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + by (use assms in \induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\) + (auto intro: untilM.domintros) + +lemma untilM_dom_ex_step: + assumes "untilM_dom (vars, cond, body)" + and "\t. Run (body vars) t vars'" + and "\t'. Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + using assms by (blast intro: untilM_dom_step) + +lemma liftState_untilM: + assumes "untilS_dom (vars, liftState r \ cond, liftState r \ body, s)" + and "untilM_dom (vars, cond, body)" + shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \ cond) (liftState r \ body) s" +proof (use assms in \induction vars "liftState r \ cond" "liftState r \ body" s rule: untilS.pinduct\) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases body k) + case (k vars' s') + show ?case unfolding comp_def liftState_bind + proof (intro bindS_ext_cong, goal_cases cond until) + case (until a s'') + have "untilM_dom (vars', cond, body)" if "\a" + proof (rule untilM_dom_ex_step[OF domM]) + show "\t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run) + show "\t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run) + qed + then show ?case using k until IH by (auto simp: comp_def) + qed auto + qed auto +qed + +end diff --git a/snapshots/isabelle/lib/sail/State_monad.thy b/snapshots/isabelle/lib/sail/State_monad.thy new file mode 100644 index 00000000..8e19f0b6 --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_monad.thy @@ -0,0 +1,375 @@ +chapter \Generated by Lem from ../../src/gen_lib/state_monad.lem.\ + +theory "State_monad" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) + +(* 'a is result type *) + +type_synonym memstate =" (int, memory_byte) Map.map " +type_synonym tagstate =" (int, bitU) Map.map " +(* type regstate = map string (vector bitU) *) + +record 'regs sequential_state = + + regstate ::" 'regs " + + memstate ::" memstate " + + tagstate ::" tagstate " + + write_ea ::" (write_kind * int * int)option " + + last_exclusive_operation_was_load ::" bool " + + (* Random bool generator for use as an undefined bit oracle *) + next_bool ::" nat \ (bool * nat)" + + seed ::" nat " + + +(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) +definition init_state :: " 'regs \(nat \ bool*nat)\ nat \ 'regs sequential_state " where + " init_state regs o1 s = ( + (| regstate = regs, + memstate = Map.empty, + tagstate = Map.empty, + write_ea = None, + last_exclusive_operation_was_load = False, + next_bool = o1, + seed = s |) )" + + +datatype 'e ex = + Failure " string " + | Throw " 'e " + +datatype( 'a, 'e) result = + Value " 'a " + | Ex " ( 'e ex)" + +(* State, nondeterminism and exception monad with result value type 'a + and exception type 'e. *) +type_synonym( 'regs, 'a, 'e) monadS =" 'regs sequential_state \ ( ('a, 'e)result * 'regs sequential_state) set " + +(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*) +definition returnS :: " 'a \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " returnS a s = ( {(Value a,s)})" + + +(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*) +definition bindS :: "('regs sequential_state \(('a,'e)result*'regs sequential_state)set)\('a \ 'regs sequential_state \(('b,'e)result*'regs sequential_state)set)\ 'regs sequential_state \(('b,'e)result*'regs sequential_state)set " where + " bindS m f (s :: 'regs sequential_state) = ( + \ (Set.image (\x . + (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s)))" + + +(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*) +definition seqS :: "('regs sequential_state \(((unit),'e)result*'regs sequential_state)set)\('regs sequential_state \(('b,'e)result*'regs sequential_state)set)\ 'regs sequential_state \(('b,'e)result*'regs sequential_state)set " where + " seqS m n = ( bindS m ( \x . + (case x of (_ :: unit) => n )))" + + +(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*) +definition chooseS :: " 'a set \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " chooseS xs s = ( Set.image (\ x . (Value x, s)) xs )" + + +(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*) +definition readS :: "('regs sequential_state \ 'a)\ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " readS f = ( (\ s . returnS (f s) s))" + + +(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*) +definition updateS :: "('regs sequential_state \ 'regs sequential_state)\ 'regs sequential_state \(((unit),'e)result*'regs sequential_state)set " where + " updateS f = ( (\ s . returnS () (f s)))" + + +(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*) +definition failS :: " string \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " failS msg s = ( {(Ex (Failure msg), s)})" + + +(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) +definition undefined_boolS :: " unit \('regs,(bool),'e)monadS " where + " undefined_boolS _ = ( bindS + (readS (\ s . (next_bool s) ((seed s)))) ( \x . + (case x of + (b, seed1) => seqS (updateS (\ s . ( s (| seed := seed1 |)))) + (returnS b) + )))" + + +(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) +definition exitS :: " unit \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " exitS _ = ( failS (''exit''))" + + +(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*) +definition throwS :: " 'e \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " throwS e s = ( {(Ex (Throw e), s)})" + + +(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*) +definition try_catchS :: "('regs sequential_state \(('a,'e1)result*'regs sequential_state)set)\('e1 \ 'regs sequential_state \(('a,'e2)result*'regs sequential_state)set)\ 'regs sequential_state \(('a,'e2)result*'regs sequential_state)set " where + " try_catchS m h s = ( + \ (Set.image (\x . + (case x of + (Value a, s') => returnS a s' + | (Ex (Throw e), s') => h e s' + | (Ex (Failure msg), s') => {(Ex (Failure msg), s')} + )) (m s)))" + + +(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*) +definition assert_expS :: " bool \ string \ 'regs sequential_state \(((unit),'e)result*'regs sequential_state)set " where + " assert_expS exp msg = ( if exp then returnS () else failS msg )" + + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is either 'r 'e, where Right e + represents a proper exception and Left r an early return of value r. *) +type_synonym( 'regs, 'a, 'r, 'e) monadSR =" ('regs, 'a, ( ('r, 'e)sum)) monadS " + +(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e*) +definition early_returnS :: " 'r \ 'regs sequential_state \(('a,(('r,'e)sum))result*'regs sequential_state)set " where + " early_returnS r = ( throwS (Inl r))" + + +(*val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) +definition catch_early_returnS :: "('regs sequential_state \(('a,(('a,'e)sum))result*'regs sequential_state)set)\ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " catch_early_returnS m = ( + try_catchS m + (\x . (case x of Inl a => returnS a | Inr e => throwS e )))" + + +(* Lift to monad with early return by wrapping exceptions *) +(*val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e*) +definition liftSR :: "('regs sequential_state \(('a,'e)result*'regs sequential_state)set)\ 'regs sequential_state \(('a,(('r,'e)sum))result*'regs sequential_state)set " where + " liftSR m = ( try_catchS m (\ e . throwS (Inr e)))" + + +(* Catch exceptions in the presence of early returns *) +(*val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) -> monadSR 'regs 'a 'r 'e2*) +definition try_catchSR :: "('regs sequential_state \(('a,(('r,'e1)sum))result*'regs sequential_state)set)\('e1 \ 'regs sequential_state \(('a,(('r,'e2)sum))result*'regs sequential_state)set)\ 'regs sequential_state \(('a,(('r,'e2)sum))result*'regs sequential_state)set " where + " try_catchSR m h = ( + try_catchS m + (\x . (case x of Inl r => throwS (Inl r) | Inr e => h e )))" + + +(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*) +definition maybe_failS :: " string \ 'a option \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " maybe_failS msg = ( \x . + (case x of Some a => returnS a | None => failS msg ) )" + + +(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*) +definition read_tagS :: " 'a Bitvector_class \ 'a \('regs,(bitU),'e)monadS " where + " read_tagS dict_Sail_values_Bitvector_a addr = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\ addr . + readS (\ s . case_option B0 id ((tagstate s) addr))))" + + +(* Read bytes from memory and return in little endian order *) +(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*) +definition read_mem_bytesS :: " 'a Bitvector_class \ read_kind \ 'a \ nat \('regs,(((bitU)list)list),'e)monadS " where + " read_mem_bytesS dict_Sail_values_Bitvector_a read_kind addr sz = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\ addr . + (let sz = (int sz) in + (let addrs = (index_list addr ((addr+sz)-( 1 :: int))(( 1 :: int))) in + (let read_byte = (\ s addr . (memstate s) addr) in + bindS (readS (\ s . just_list (List.map (read_byte s) addrs))) + (\x . (case x of + Some mem_val => seqS + (updateS + (\ s . + if read_is_exclusive read_kind + then + ( s (| last_exclusive_operation_was_load := True |)) + else s)) (returnS mem_val) + | None => failS (''read_memS'') + )))))))" + + +(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*) +definition read_memS :: " 'a Bitvector_class \ 'b Bitvector_class \ read_kind \ 'a \ int \('regs,'b,'e)monadS " where + " read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz = ( bindS + (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . + maybe_failS (''bits_of_mem_bytes'') ( + (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + + +(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) +definition excl_resultS :: " unit \('regs,(bool),'e)monadS " where + " excl_resultS _ = ( bindS + (readS (\ s . (last_exclusive_operation_was_load s))) (\ excl_load . seqS + (updateS (\ s . ( s (| last_exclusive_operation_was_load := False |)))) + (chooseS (if excl_load then {False, True} else {False}))))" + + +(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*) +definition write_mem_eaS :: " 'a Bitvector_class \ write_kind \ 'a \ nat \('regs,(unit),'e)monadS " where + " write_mem_eaS dict_Sail_values_Bitvector_a write_kind addr sz = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\ addr . + (let sz = (int sz) in + updateS (\ s . ( s (| write_ea := (Some (write_kind, addr, sz)) |))))))" + + +(* Write little-endian list of bytes to previously announced address *) +(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*) +definition write_mem_bytesS :: "((bitU)list)list \('regs,(bool),'e)monadS " where + " write_mem_bytesS v = ( bindS + (readS (\ s . (write_ea s))) (\x . + (case x of + None => failS (''write ea has not been announced yet'') + | Some (_, addr, sz) => + (let addrs = (index_list addr ((addr + sz) - ( 1 :: int)) (( 1 :: int))) in + (*let v = external_mem_value (bits_of v) in*) + (let a_v = (List.zip addrs v) in + (let write_byte = (\mem p . (case (mem ,p ) of + ( mem , (addr, v) ) => map_update + addr + v mem + )) in + seqS + (updateS + (\ s . + ( s (| memstate := (List.foldl write_byte (memstate s) a_v) |)))) + (returnS True)))) + )))" + + +(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) +definition write_mem_valS :: " 'a Bitvector_class \ 'a \ 'regs sequential_state \(((bool),'e)result*'regs sequential_state)set " where + " write_mem_valS dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail_values_Bitvector_a v of + Some v => write_mem_bytesS v + | None => failS (''write_mem_val'') +))" + + +(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*) +definition write_tagS :: " 'a Bitvector_class \ 'a \ bitU \('regs,(bool),'e)monadS " where + " write_tagS dict_Sail_values_Bitvector_a addr t = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\ addr . seqS + (updateS (\ s . ( s (| tagstate := (map_update addr t(tagstate s)) |)))) + (returnS True)))" + + +(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*) +definition read_regS :: "('regs,'rv,'a)register_ref \ 'regs sequential_state \(('a,'e)result*'regs sequential_state)set " where + " read_regS reg = ( readS (\ s . (read_from reg)(regstate s)))" + + +(* TODO +let read_reg_range reg i j state = + let v = slice (get_reg state (name_of_reg reg)) i j in + [(Value (vec_to_bvec v),state)] +let read_reg_bit reg i state = + let v = access (get_reg state (name_of_reg reg)) i in + [(Value v,state)] +let read_reg_field reg regfield = + let (i,j) = register_field_indices reg regfield in + read_reg_range reg i j +let read_reg_bitfield reg regfield = + let (i,_) = register_field_indices reg regfield in + read_reg_bit reg i *) + +(*val read_regvalS : forall 'regs 'rv 'e. + register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*) +fun read_regvalS :: "(string \ 'regs \ 'rv option)*(string \ 'rv \ 'regs \ 'regs option)\ string \('regs,'rv,'e)monadS " where + " read_regvalS (read, _) reg = ( bindS + (readS (\ s . read reg(regstate s))) (\x . + (case x of + Some v => returnS v + | None => failS ((''read_regvalS '') @ reg) + )))" + + +(*val write_regvalS : forall 'regs 'rv 'e. + register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*) +fun write_regvalS :: "(string \ 'regs \ 'rv option)*(string \ 'rv \ 'regs \ 'regs option)\ string \ 'rv \('regs,(unit),'e)monadS " where + " write_regvalS (_, write1) reg v = ( bindS + (readS (\ s . write1 reg v(regstate s))) (\x . + (case x of + Some rs' => updateS (\ s . ( s (| regstate := rs' |))) + | None => failS ((''write_regvalS '') @ reg) + )))" + + +(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*) +definition write_regS :: "('regs,'rv,'a)register_ref \ 'a \ 'regs sequential_state \(((unit),'e)result*'regs sequential_state)set " where + " write_regS reg v = ( + updateS (\ s . ( s (| regstate := ((write_to reg) v(regstate s)) |))))" + + +(* TODO +val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e +let update_reg reg f v state = + let current_value = get_reg state reg in + let new_value = f current_value v in + [(Value (), set_reg state reg new_value)] + +let write_reg_field reg regfield = update_reg reg regfield.set_field + +val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a +let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val) +let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) + +let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x +let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) + +let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit) +let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) + +let update_reg_field_range regfield i j reg_val new_val = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in + regfield.set_field reg_val new_field_value +let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) + +let update_reg_field_pos regfield i reg_val x = + let current_field_value = regfield.get_field reg_val in + let new_field_value = update_list regfield.field_is_inc current_field_value i x in + regfield.set_field reg_val new_field_value +let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) + +let update_reg_field_bit regfield i reg_val bit = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in + regfield.set_field reg_val new_field_value +let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*) + +(* TODO Add Show typeclass for value and exception type *) +(*val show_result : forall 'a 'e. result 'a 'e -> string*) +definition show_result :: "('a,'e)result \ string " where + " show_result = ( \x . + (case x of + Value _ => (''Value ()'') + | Ex (Failure msg) => (''Failure '') @ msg + | Ex (Throw _) => (''Throw'') + ) )" + + +(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*) +definition prerr_results :: "(('a,'e)result*'s)set \ unit " where + " prerr_results rs = ( + (let _ = (Set.image ( \x . + (case x of (r, _) => (let _ = (prerr_endline (show_result r)) in () ) )) rs) in + () ))" + +end diff --git a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy b/snapshots/isabelle/lib/sail/State_monad_lemmas.thy new file mode 100644 index 00000000..e0d684ba --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_monad_lemmas.thy @@ -0,0 +1,232 @@ +theory State_monad_lemmas + imports + State_monad + Sail_values_lemmas +begin + +(*context + notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp] +begin*) + +lemma bindS_ext_cong[fundef_cong]: + assumes m: "m1 s = m2 s" + and f: "\a s'. (Value a, s') \ (m2 s) \ f1 a s' = f2 a s'" + shows "bindS m1 f1 s = bindS m2 f2 s" + using assms unfolding bindS_def by (auto split: result.splits) + +lemma bindS_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\s a s'. (Value a, s') \ (m2 s) \ f1 a s' = f2 a s'" + shows "bindS m1 f1 = bindS m2 f2" + using assms by (intro ext bindS_ext_cong; blast) + +lemma bindS_returnS_left[simp]: "bindS (returnS x) f = f x" + by (auto simp add: bindS_def returnS_def) + +lemma bindS_returnS_right[simp]: "bindS m returnS = (m :: ('regs, 'a, 'e) monadS)" + by (intro ext) (auto simp: bindS_def returnS_def split: result.splits) + +lemma bindS_readS: "bindS (readS f) m = (\s. m (f s) s)" + by (auto simp: bindS_def readS_def returnS_def) + +lemma bindS_updateS: "bindS (updateS f) m = (\s. m () (f s))" + by (auto simp: bindS_def updateS_def returnS_def) + +lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()" + by (auto simp: assert_expS_def) + + +lemma result_cases: + fixes r :: "('a, 'e) result" + obtains (Value) a where "r = Value a" + | (Throw) e where "r = Ex (Throw e)" + | (Failure) msg where "r = Ex (Failure msg)" +proof (cases r) + case (Ex ex) then show ?thesis by (cases ex; auto intro: that) +qed + +lemma result_state_cases: + fixes rs :: "('a, 'e) result \ 's" + obtains (Value) a s where "rs = (Value a, s)" + | (Throw) e s where "rs = (Ex (Throw e), s)" + | (Failure) msg s where "rs = (Ex (Failure msg), s)" +proof - + obtain r s where rs: "rs = (r, s)" by (cases rs) + then show thesis by (cases r rule: result_cases) (auto intro: that) +qed + +lemma monadS_ext_eqI: + fixes m m' :: "('regs, 'a, 'e) monadS" + assumes "\a s'. (Value a, s') \ m s \ (Value a, s') \ m' s" + and "\e s'. (Ex (Throw e), s') \ m s \ (Ex (Throw e), s') \ m' s" + and "\msg s'. (Ex (Failure msg), s') \ m s \ (Ex (Failure msg), s') \ m' s" + shows "m s = m' s" +proof (intro set_eqI) + fix x + show "x \ m s \ x \ m' s" using assms by (cases x rule: result_state_cases) auto +qed + +lemma monadS_eqI: + fixes m m' :: "('regs, 'a, 'e) monadS" + assumes "\s a s'. (Value a, s') \ m s \ (Value a, s') \ m' s" + and "\s e s'. (Ex (Throw e), s') \ m s \ (Ex (Throw e), s') \ m' s" + and "\s msg s'. (Ex (Failure msg), s') \ m s \ (Ex (Failure msg), s') \ m' s" + shows "m = m'" + using assms by (intro ext monadS_ext_eqI) + +lemma bindS_cases: + assumes "(r, s') \ bindS m f s" + obtains (Value) a a' s'' where "r = Value a" and "(Value a', s'') \ m s" and "(Value a, s') \ f a' s''" + | (Ex_Left) e where "r = Ex e" and "(Ex e, s') \ m s" + | (Ex_Right) e a s'' where "r = Ex e" and "(Value a, s'') \ m s" and "(Ex e, s') \ f a s''" + using assms by (cases r; auto simp: bindS_def split: result.splits) + +lemma bindS_intros: + "\m f s a s' a' s''. (Value a', s'') \ m s \ (Value a, s') \ f a' s'' \ (Value a, s') \ bindS m f s" + "\m f s e s'. (Ex e, s') \ m s \ (Ex e, s') \ bindS m f s" + "\m f s e s' a s''. (Ex e, s') \ f a s'' \ (Value a, s'') \ m s \ (Ex e, s') \ bindS m f s" + by (auto simp: bindS_def intro: bexI[rotated]) + +lemma bindS_assoc[simp]: "bindS (bindS m f) g = bindS m (\x. bindS (f x) g)" + by (auto elim!: bindS_cases intro: bindS_intros monadS_eqI) + +lemma bindS_failS[simp]: "bindS (failS msg) f = failS msg" by (auto simp: bindS_def failS_def) +lemma bindS_throwS[simp]: "bindS (throwS e) f = throwS e" by (auto simp: bindS_def throwS_def) +declare seqS_def[simp] + +lemma Value_bindS_elim: + assumes "(Value a, s') \ bindS m f s" + obtains s'' a' where "(Value a', s'') \ m s" and "(Value a, s') \ f a' s''" + using assms by (auto elim: bindS_cases) + +lemma Ex_bindS_elim: + assumes "(Ex e, s') \ bindS m f s" + obtains (Left) "(Ex e, s') \ m s" + | (Right) s'' a' where "(Value a', s'') \ m s" and "(Ex e, s') \ f a' s''" + using assms by (auto elim: bindS_cases) + +lemma try_catchS_returnS[simp]: "try_catchS (returnS a) h = returnS a" + and try_catchS_failS[simp]: "try_catchS (failS msg) h = failS msg" + and try_catchS_throwS[simp]: "try_catchS (throwS e) h = h e" + by (auto simp: try_catchS_def returnS_def failS_def throwS_def) + +lemma try_catchS_cong[cong]: + assumes "\s. m1 s = m2 s" and "\e s. h1 e s = h2 e s" + shows "try_catchS m1 h1 = try_catchS m2 h2" + using assms by (intro arg_cong2[where f = try_catchS] ext) auto + +lemma try_catchS_cases: + assumes "(r, s') \ try_catchS m h s" + obtains (Value) a where "r = Value a" and "(Value a, s') \ m s" + | (Fail) msg where "r = Ex (Failure msg)" and "(Ex (Failure msg), s') \ m s" + | (h) e s'' where "(Ex (Throw e), s'') \ m s" and "(r, s') \ h e s''" + using assms + by (cases r rule: result_cases) (auto simp: try_catchS_def returnS_def split: result.splits ex.splits) + +lemma try_catchS_intros: + "\m h s a s'. (Value a, s') \ m s \ (Value a, s') \ try_catchS m h s" + "\m h s msg s'. (Ex (Failure msg), s') \ m s \ (Ex (Failure msg), s') \ try_catchS m h s" + "\m h s e s'' r s'. (Ex (Throw e), s'') \ m s \ (r, s') \ h e s'' \ (r, s') \ try_catchS m h s" + by (auto simp: try_catchS_def returnS_def intro: bexI[rotated]) + +lemma no_Ex_basic_builtins[simp]: + "\s e s' a. (Ex e, s') \ returnS a s \ False" + "\s e s' f. (Ex e, s') \ readS f s \ False" + "\s e s' f. (Ex e, s') \ updateS f s \ False" + "\s e s' xs. (Ex e, s') \ chooseS xs s \ False" + by (auto simp: readS_def updateS_def returnS_def chooseS_def) + +fun ignore_throw_aux :: "(('a, 'e1) result \ 's) \ (('a, 'e2) result \ 's) set" where + "ignore_throw_aux (Value a, s') = {(Value a, s')}" +| "ignore_throw_aux (Ex (Throw e), s') = {}" +| "ignore_throw_aux (Ex (Failure msg), s') = {(Ex (Failure msg), s')}" +definition "ignore_throw m s \ \(ignore_throw_aux ` m s)" + +lemma ignore_throw_cong: + assumes "\s. m1 s = m2 s" + shows "ignore_throw m1 = ignore_throw m2" + using assms by (auto simp: ignore_throw_def) + +lemma ignore_throw_aux_member_simps[simp]: + "(Value a, s') \ ignore_throw_aux ms \ ms = (Value a, s')" + "(Ex (Throw e), s') \ ignore_throw_aux ms \ False" + "(Ex (Failure msg), s') \ ignore_throw_aux ms \ ms = (Ex (Failure msg), s')" + by (cases ms rule: result_state_cases; auto)+ + +lemma ignore_throw_member_simps[simp]: + "(Value a, s') \ ignore_throw m s \ (Value a, s') \ m s" + "(Value a, s') \ ignore_throw m s \ (Value a, s') \ m s" + "(Ex (Throw e), s') \ ignore_throw m s \ False" + "(Ex (Failure msg), s') \ ignore_throw m s \ (Ex (Failure msg), s') \ m s" + by (auto simp: ignore_throw_def) + +lemma ignore_throw_cases: + assumes no_throw: "ignore_throw m s = m s" + and r: "(r, s') \ m s" + obtains (Value) a where "r = Value a" + | (Failure) msg where "r = Ex (Failure msg)" + using r unfolding no_throw[symmetric] + by (cases r rule: result_cases) (auto simp: ignore_throw_def) + +lemma ignore_throw_bindS[simp]: + "ignore_throw (bindS m f) = bindS (ignore_throw m) (ignore_throw \ f)" + by (intro monadS_eqI) (auto simp: ignore_throw_def elim!: bindS_cases intro: bindS_intros) + +lemma try_catchS_bindS_no_throw: + fixes m1 :: "('r, 'a, 'e1) monadS" and m2 :: "('r, 'a, 'e2) monadS" + assumes m1: "\s. ignore_throw m1 s = m1 s" + and m2: "\s. ignore_throw m1 s = m2 s" + shows "try_catchS (bindS m1 f) h = bindS m2 (\a. try_catchS (f a) h)" +proof + fix s + have "try_catchS (bindS m1 f) h s = bindS (ignore_throw m1) (\a. try_catchS (f a) h) s" + by (intro monadS_ext_eqI; + auto elim!: bindS_cases try_catchS_cases elim: ignore_throw_cases[OF m1]; + auto simp: ignore_throw_def intro: bindS_intros try_catchS_intros) + also have "\ = bindS m2 (\a. try_catchS (f a) h) s" using m2 by (intro bindS_ext_cong) auto + finally show "try_catchS (bindS m1 f) h s = bindS m2 (\a. try_catchS (f a) h) s" . +qed + +lemma no_throw_basic_builtins[simp]: + "ignore_throw (returnS a) = returnS a" + "\f. ignore_throw (readS f) = readS f" + "\f. ignore_throw (updateS f) = updateS f" + "ignore_throw (chooseS xs) = chooseS xs" + "ignore_throw (failS msg) = failS msg" + "ignore_throw (maybe_failS msg x) = maybe_failS msg x" + unfolding ignore_throw_def returnS_def chooseS_def maybe_failS_def failS_def readS_def updateS_def + by (intro ext; auto split: option.splits)+ + +lemmas ignore_throw_option_case_distrib = + option.case_distrib[where h = "\c. ignore_throw c s" and option = "c s" for c s] + +lemma no_throw_mem_builtins: + "\BC rk a sz s. ignore_throw (read_mem_bytesS BC rk a sz) s = read_mem_bytesS BC rk a sz s" + "\BC a s. ignore_throw (read_tagS BC a) s = read_tagS BC a s" + "\BC wk a sz s. ignore_throw (write_mem_eaS BC wk a sz) s = write_mem_eaS BC wk a sz s" + "\v s. ignore_throw (write_mem_bytesS v) s = write_mem_bytesS v s" + "\BC v s. ignore_throw (write_mem_valS BC v) s = write_mem_valS BC v s" + "\BC a t s. ignore_throw (write_tagS BC a t) s = write_tagS BC a t s" + "\s. ignore_throw (excl_resultS ()) s = excl_resultS () s" + "\s. ignore_throw (undefined_boolS ()) s = undefined_boolS () s" + unfolding read_mem_bytesS_def read_memS_def read_tagS_def write_mem_eaS_def + unfolding write_mem_valS_def write_mem_bytesS_def write_tagS_def + unfolding excl_resultS_def undefined_boolS_def + by (auto cong: bindS_cong bindS_ext_cong ignore_throw_cong option.case_cong + simp: option.case_distrib prod.case_distrib ignore_throw_option_case_distrib comp_def) + +lemma no_throw_read_memS: "ignore_throw (read_memS BCa BCb rk a sz) s = read_memS BCa BCb rk a sz s" + by (auto simp: read_memS_def no_throw_mem_builtins cong: bindS_ext_cong) + +lemma no_throw_read_regvalS: "ignore_throw (read_regvalS r reg_name) s = read_regvalS r reg_name s" + by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong) + +lemma no_throw_write_regvalS: "ignore_throw (write_regvalS r reg_name v) s = write_regvalS r reg_name v s" + by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong) + +lemmas no_throw_builtins[simp] = + no_throw_mem_builtins no_throw_read_regvalS no_throw_write_regvalS no_throw_read_memS + +(* end *) + +end diff --git a/snapshots/isabelle/riscv/Riscv.thy b/snapshots/isabelle/riscv/Riscv.thy new file mode 100644 index 00000000..71873cec --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv.thy @@ -0,0 +1,7876 @@ +chapter \Generated by Lem from riscv.lem.\ + +theory "Riscv" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Riscv_types" + "Riscv_extras" + +begin + +(*Generated by Sail from riscv.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Riscv_types*) +(*open import Riscv_extras*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) + +definition GetSlice_int :: " int \ int \ int \('n::len)Word.word " where + " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) + +definition RISCV_write :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),(bool),(exception))monad " where + " RISCV_write addr width data = ( + write_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data \ + return True )" + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) + +definition RISCV_read :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)option),(exception))monad " where + " RISCV_read addr width = ( + (read_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \ (\ (w__0 :: ( 'int8_times_n::len)Word.word) . + return (Some w__0)))" + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val ex_nat : ii -> integer*) + +definition ex_nat :: " int \ int " where + " ex_nat n = ( n )" + + +(*val ex_int : ii -> integer*) + +definition ex_int :: " int \ int " where + " ex_int n = ( n )" + + +(*val coerce_int_nat : ii -> M ii*) + +definition coerce_int_nat :: " int \((register_value),(int),(exception))monad " where + " coerce_int_nat x = ( assert_exp True ('''') \ return x )" + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition EXTS :: " int \('n::len)Word.word \('m::len)Word.word " where + " EXTS (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" + + +definition EXTZ :: " int \('n::len)Word.word \('m::len)Word.word " where + " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \ ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \ ((Word.uint y)))" + + +definition zopz0zIzJ_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zIzJ_u x y = ( ((Word.uint x)) \ ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \ bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val vector64 : ii -> mword ty64*) + +definition vector64 :: " int \(64)Word.word " where + " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) + +definition to_bits :: " int \ int \('l::len)Word.word " where + " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" + + +(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) + +definition shift_right_arith64 :: "(64)Word.word \(6)Word.word \(64)Word.word " where + " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = ( + (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in + (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))" + + +(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) + +definition shift_right_arith32 :: "(32)Word.word \(5)Word.word \(32)Word.word " where + " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = ( + (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in + (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))" + + +definition xlen :: " int " where + " xlen = ( (( 64 :: int)::ii))" + + +definition xlen_max_unsigned :: " int " where + " xlen_max_unsigned = ( ((pow2 xlen)) - (( 1 :: int)::ii))" + + +definition xlen_max_signed :: " int " where + " xlen_max_signed = ( ((pow2 ((xlen - (( 1 :: int)::ii))))) - (( 1 :: int)::ii))" + + +definition xlen_min_signed :: " int " where + " xlen_min_signed = ( (( 0 :: int)::ii) - ((pow2 ((xlen - (( 1 :: int)::ii))))))" + + +(*val regbits_to_regno : mword ty5 -> integer*) + +definition regbits_to_regno :: "(5)Word.word \ int " where + " regbits_to_regno b = ( + (let r = (Word.uint b) in + r))" + + +(*val creg2reg_bits : mword ty3 -> mword ty5*) + +definition creg2reg_bits :: "(3)Word.word \(5)Word.word " where + " creg2reg_bits creg = ( (concat_vec (vec_of_bits [B0,B1] :: 2 Word.word) creg :: 5 Word.word))" + + +definition zreg :: "(5)Word.word " where + " zreg = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" + + +definition ra :: "(5)Word.word " where + " ra = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))" + + +definition sp :: "(5)Word.word " where + " sp = ( (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))" + + +(*val rX : integer -> M (mword ty64)*) + +definition rX :: " int \((register_value),((64)Word.word),(exception))monad " where + " rX l__81 = ( + if (((l__81 = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg Xs_ref \ (\ (w__0 :: xlenbits list) . + return ((access_list_dec w__0 l__81 :: 64 Word.word))))" + + +(*val wX : integer -> mword ty64 -> M unit*) + +definition wX :: " int \(64)Word.word \((register_value),(unit),(exception))monad " where + " wX r v = ( + if (((r \ (( 0 :: int)::ii)))) then + read_reg Xs_ref \ (\ (w__0 :: ( 64 Word.word) list) . + write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list)) \ + return ((prerr_endline + (((op@) (''x'') + (((op@) ((stringFromInteger r)) + (((op@) ('' <- '') ((string_of_vec v))))))))))) + else return () )" + + +(*val reg_name_abi : mword ty5 -> string*) + +definition reg_name_abi :: "(5)Word.word \ string " where + " reg_name_abi r = ( + (let b__0 = r in + if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then + (''zero'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''ra'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''sp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''gp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''tp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''t0'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''t1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''t2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''fp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''a0'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''a1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''a2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''a3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''a4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then + (''a5'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + (''a6'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''a7'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''s2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''s3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''s4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''s5'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''s6'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''s7'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''s8'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s9'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''s10'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''s11'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''t3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''t4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''t5'') + else (''t6'')))" + + +(*val Architecture_of_num : integer -> Architecture*) + +definition Architecture_of_num :: " int \ Architecture " where + " Architecture_of_num arg0 = ( + (let l__79 = arg0 in + if (((l__79 = (( 0 :: int)::ii)))) then RV32 + else if (((l__79 = (( 1 :: int)::ii)))) then RV64 + else RV128))" + + +(*val num_of_Architecture : Architecture -> integer*) + +fun num_of_Architecture :: " Architecture \ int " where + " num_of_Architecture RV32 = ( (( 0 :: int)::ii))" +|" num_of_Architecture RV64 = ( (( 1 :: int)::ii))" +|" num_of_Architecture RV128 = ( (( 2 :: int)::ii))" + + +(*val architecture : mword ty2 -> maybe Architecture*) + +definition architecture :: "(2)Word.word \(Architecture)option " where + " architecture a = ( + (let b__0 = a in + if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Some RV32 + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Some RV64 + else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then Some RV128 + else None))" + + +(*val arch_to_bits : Architecture -> mword ty2*) + +fun arch_to_bits :: " Architecture \(2)Word.word " where + " arch_to_bits RV32 = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" arch_to_bits RV64 = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" arch_to_bits RV128 = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val Privilege_of_num : integer -> Privilege*) + +definition Privilege_of_num :: " int \ Privilege " where + " Privilege_of_num arg0 = ( + (let l__77 = arg0 in + if (((l__77 = (( 0 :: int)::ii)))) then User + else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + else Machine))" + + +(*val num_of_Privilege : Privilege -> integer*) + +fun num_of_Privilege :: " Privilege \ int " where + " num_of_Privilege User = ( (( 0 :: int)::ii))" +|" num_of_Privilege Supervisor = ( (( 1 :: int)::ii))" +|" num_of_Privilege Machine = ( (( 2 :: int)::ii))" + + +(*val privLevel_to_bits : Privilege -> mword ty2*) + +fun privLevel_to_bits :: " Privilege \(2)Word.word " where + " privLevel_to_bits User = ( (vec_of_bits [B0,B0] :: 2 Word.word))" +|" privLevel_to_bits Supervisor = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" privLevel_to_bits Machine = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val privLevel_of_bits : mword ty2 -> Privilege*) + +definition privLevel_of_bits :: "(2)Word.word \ Privilege " where + " privLevel_of_bits p = ( + (let b__0 = p in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then User + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor + else Machine))" + + +(*val privLevel_to_str : Privilege -> string*) + +fun privLevel_to_str :: " Privilege \ string " where + " privLevel_to_str User = ( (''U''))" +|" privLevel_to_str Supervisor = ( (''S''))" +|" privLevel_to_str Machine = ( (''M''))" + + +(*val AccessType_of_num : integer -> AccessType*) + +definition AccessType_of_num :: " int \ AccessType " where + " AccessType_of_num arg0 = ( + (let l__74 = arg0 in + if (((l__74 = (( 0 :: int)::ii)))) then Read + else if (((l__74 = (( 1 :: int)::ii)))) then Write + else if (((l__74 = (( 2 :: int)::ii)))) then ReadWrite + else Execute))" + + +(*val num_of_AccessType : AccessType -> integer*) + +fun num_of_AccessType :: " AccessType \ int " where + " num_of_AccessType Read = ( (( 0 :: int)::ii))" +|" num_of_AccessType Write = ( (( 1 :: int)::ii))" +|" num_of_AccessType ReadWrite = ( (( 2 :: int)::ii))" +|" num_of_AccessType Execute = ( (( 3 :: int)::ii))" + + +(*val ReadType_of_num : integer -> ReadType*) + +definition ReadType_of_num :: " int \ ReadType " where + " ReadType_of_num arg0 = ( + (let l__73 = arg0 in + if (((l__73 = (( 0 :: int)::ii)))) then Instruction + else Data))" + + +(*val num_of_ReadType : ReadType -> integer*) + +fun num_of_ReadType :: " ReadType \ int " where + " num_of_ReadType Instruction = ( (( 0 :: int)::ii))" +|" num_of_ReadType Data = ( (( 1 :: int)::ii))" + + +(*val ExceptionType_of_num : integer -> ExceptionType*) + +definition ExceptionType_of_num :: " int \ ExceptionType " where + " ExceptionType_of_num arg0 = ( + (let l__58 = arg0 in + if (((l__58 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align + else if (((l__58 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault + else if (((l__58 = (( 2 :: int)::ii)))) then E_Illegal_Instr + else if (((l__58 = (( 3 :: int)::ii)))) then E_Breakpoint + else if (((l__58 = (( 4 :: int)::ii)))) then E_Load_Addr_Align + else if (((l__58 = (( 5 :: int)::ii)))) then E_Load_Access_Fault + else if (((l__58 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align + else if (((l__58 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault + else if (((l__58 = (( 8 :: int)::ii)))) then E_U_EnvCall + else if (((l__58 = (( 9 :: int)::ii)))) then E_S_EnvCall + else if (((l__58 = (( 10 :: int)::ii)))) then E_Reserved_10 + else if (((l__58 = (( 11 :: int)::ii)))) then E_M_EnvCall + else if (((l__58 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault + else if (((l__58 = (( 13 :: int)::ii)))) then E_Load_Page_Fault + else if (((l__58 = (( 14 :: int)::ii)))) then E_Reserved_14 + else E_SAMO_Page_Fault))" + + +(*val num_of_ExceptionType : ExceptionType -> integer*) + +fun num_of_ExceptionType :: " ExceptionType \ int " where + " num_of_ExceptionType E_Fetch_Addr_Align = ( (( 0 :: int)::ii))" +|" num_of_ExceptionType E_Fetch_Access_Fault = ( (( 1 :: int)::ii))" +|" num_of_ExceptionType E_Illegal_Instr = ( (( 2 :: int)::ii))" +|" num_of_ExceptionType E_Breakpoint = ( (( 3 :: int)::ii))" +|" num_of_ExceptionType E_Load_Addr_Align = ( (( 4 :: int)::ii))" +|" num_of_ExceptionType E_Load_Access_Fault = ( (( 5 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Addr_Align = ( (( 6 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Access_Fault = ( (( 7 :: int)::ii))" +|" num_of_ExceptionType E_U_EnvCall = ( (( 8 :: int)::ii))" +|" num_of_ExceptionType E_S_EnvCall = ( (( 9 :: int)::ii))" +|" num_of_ExceptionType E_Reserved_10 = ( (( 10 :: int)::ii))" +|" num_of_ExceptionType E_M_EnvCall = ( (( 11 :: int)::ii))" +|" num_of_ExceptionType E_Fetch_Page_Fault = ( (( 12 :: int)::ii))" +|" num_of_ExceptionType E_Load_Page_Fault = ( (( 13 :: int)::ii))" +|" num_of_ExceptionType E_Reserved_14 = ( (( 14 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Page_Fault = ( (( 15 :: int)::ii))" + + +(*val exceptionType_to_bits : ExceptionType -> mword ty4*) + +fun exceptionType_to_bits :: " ExceptionType \(4)Word.word " where + " exceptionType_to_bits E_Fetch_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Fetch_Access_Fault = ( (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Illegal_Instr = ( (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Breakpoint = ( (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Addr_Align = ( (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Access_Fault = ( (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Addr_Align = ( (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Access_Fault = ( (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_U_EnvCall = ( (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_S_EnvCall = ( (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Reserved_10 = ( (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_M_EnvCall = ( (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Fetch_Page_Fault = ( (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Page_Fault = ( (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Reserved_14 = ( (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Page_Fault = ( (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word))" + + +(*val exceptionType_to_str : ExceptionType -> string*) + +fun exceptionType_to_str :: " ExceptionType \ string " where + " exceptionType_to_str E_Fetch_Addr_Align = ( (''fisaligned-fetch''))" +|" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))" +|" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))" +|" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))" +|" exceptionType_to_str E_Load_Addr_Align = ( (''misaligned-load''))" +|" exceptionType_to_str E_Load_Access_Fault = ( (''load-access-fault''))" +|" exceptionType_to_str E_SAMO_Addr_Align = ( (''misaliged-store/amo''))" +|" exceptionType_to_str E_SAMO_Access_Fault = ( (''store/amo-access-fault''))" +|" exceptionType_to_str E_U_EnvCall = ( (''u-call''))" +|" exceptionType_to_str E_S_EnvCall = ( (''s-call''))" +|" exceptionType_to_str E_Reserved_10 = ( (''reserved-0''))" +|" exceptionType_to_str E_M_EnvCall = ( (''m-call''))" +|" exceptionType_to_str E_Fetch_Page_Fault = ( (''fetch-page-fault''))" +|" exceptionType_to_str E_Load_Page_Fault = ( (''load-page-fault''))" +|" exceptionType_to_str E_Reserved_14 = ( (''reserved-1''))" +|" exceptionType_to_str E_SAMO_Page_Fault = ( (''store/amo-page-fault''))" + + +(*val InterruptType_of_num : integer -> InterruptType*) + +definition InterruptType_of_num :: " int \ InterruptType " where + " InterruptType_of_num arg0 = ( + (let l__50 = arg0 in + if (((l__50 = (( 0 :: int)::ii)))) then I_U_Software + else if (((l__50 = (( 1 :: int)::ii)))) then I_S_Software + else if (((l__50 = (( 2 :: int)::ii)))) then I_M_Software + else if (((l__50 = (( 3 :: int)::ii)))) then I_U_Timer + else if (((l__50 = (( 4 :: int)::ii)))) then I_S_Timer + else if (((l__50 = (( 5 :: int)::ii)))) then I_M_Timer + else if (((l__50 = (( 6 :: int)::ii)))) then I_U_External + else if (((l__50 = (( 7 :: int)::ii)))) then I_S_External + else I_M_External))" + + +(*val num_of_InterruptType : InterruptType -> integer*) + +fun num_of_InterruptType :: " InterruptType \ int " where + " num_of_InterruptType I_U_Software = ( (( 0 :: int)::ii))" +|" num_of_InterruptType I_S_Software = ( (( 1 :: int)::ii))" +|" num_of_InterruptType I_M_Software = ( (( 2 :: int)::ii))" +|" num_of_InterruptType I_U_Timer = ( (( 3 :: int)::ii))" +|" num_of_InterruptType I_S_Timer = ( (( 4 :: int)::ii))" +|" num_of_InterruptType I_M_Timer = ( (( 5 :: int)::ii))" +|" num_of_InterruptType I_U_External = ( (( 6 :: int)::ii))" +|" num_of_InterruptType I_S_External = ( (( 7 :: int)::ii))" +|" num_of_InterruptType I_M_External = ( (( 8 :: int)::ii))" + + +(*val interruptType_to_bits : InterruptType -> mword ty4*) + +fun interruptType_to_bits :: " InterruptType \(4)Word.word " where + " interruptType_to_bits I_U_Software = ( (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_Software = ( (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_Software = ( (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))" +|" interruptType_to_bits I_U_Timer = ( (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_Timer = ( (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_Timer = ( (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))" +|" interruptType_to_bits I_U_External = ( (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_External = ( (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_External = ( (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word))" + + +(*val TrapVectorMode_of_num : integer -> TrapVectorMode*) + +definition TrapVectorMode_of_num :: " int \ TrapVectorMode " where + " TrapVectorMode_of_num arg0 = ( + (let l__48 = arg0 in + if (((l__48 = (( 0 :: int)::ii)))) then TV_Direct + else if (((l__48 = (( 1 :: int)::ii)))) then TV_Vector + else TV_Reserved))" + + +(*val num_of_TrapVectorMode : TrapVectorMode -> integer*) + +fun num_of_TrapVectorMode :: " TrapVectorMode \ int " where + " num_of_TrapVectorMode TV_Direct = ( (( 0 :: int)::ii))" +|" num_of_TrapVectorMode TV_Vector = ( (( 1 :: int)::ii))" +|" num_of_TrapVectorMode TV_Reserved = ( (( 2 :: int)::ii))" + + +(*val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode*) + +definition trapVectorMode_of_bits :: "(2)Word.word \ TrapVectorMode " where + " trapVectorMode_of_bits m = ( + (let b__0 = m in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then TV_Direct + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then TV_Vector + else TV_Reserved))" + + +(*val not_implemented : forall 'a. string -> M 'a*) + +definition not_implemented :: " string \((register_value),'a,(exception))monad " where + " not_implemented message = ( throw (Error_not_implemented message))" + + +(*val internal_error : forall 'a. string -> M 'a*) + +definition internal_error :: " string \((register_value),'a,(exception))monad " where + " internal_error s = ( assert_exp False s \ throw (Error_internal_error () ))" + + +(*val ExtStatus_of_num : integer -> ExtStatus*) + +definition ExtStatus_of_num :: " int \ ExtStatus " where + " ExtStatus_of_num arg0 = ( + (let l__45 = arg0 in + if (((l__45 = (( 0 :: int)::ii)))) then Off + else if (((l__45 = (( 1 :: int)::ii)))) then Initial + else if (((l__45 = (( 2 :: int)::ii)))) then Clean + else Dirty))" + + +(*val num_of_ExtStatus : ExtStatus -> integer*) + +fun num_of_ExtStatus :: " ExtStatus \ int " where + " num_of_ExtStatus Off = ( (( 0 :: int)::ii))" +|" num_of_ExtStatus Initial = ( (( 1 :: int)::ii))" +|" num_of_ExtStatus Clean = ( (( 2 :: int)::ii))" +|" num_of_ExtStatus Dirty = ( (( 3 :: int)::ii))" + + +(*val extStatus_to_bits : ExtStatus -> mword ty2*) + +fun extStatus_to_bits :: " ExtStatus \(2)Word.word " where + " extStatus_to_bits Off = ( (vec_of_bits [B0,B0] :: 2 Word.word))" +|" extStatus_to_bits Initial = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" extStatus_to_bits Clean = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" extStatus_to_bits Dirty = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val extStatus_of_bits : mword ty2 -> ExtStatus*) + +definition extStatus_of_bits :: "(2)Word.word \ ExtStatus " where + " extStatus_of_bits e = ( + (let b__0 = e in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Off + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Initial + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Clean + else Dirty))" + + +(*val SATPMode_of_num : integer -> SATPMode*) + +definition SATPMode_of_num :: " int \ SATPMode " where + " SATPMode_of_num arg0 = ( + (let l__43 = arg0 in + if (((l__43 = (( 0 :: int)::ii)))) then Sbare + else if (((l__43 = (( 1 :: int)::ii)))) then Sv32 + else Sv39))" + + +(*val num_of_SATPMode : SATPMode -> integer*) + +fun num_of_SATPMode :: " SATPMode \ int " where + " num_of_SATPMode Sbare = ( (( 0 :: int)::ii))" +|" num_of_SATPMode Sv32 = ( (( 1 :: int)::ii))" +|" num_of_SATPMode Sv39 = ( (( 2 :: int)::ii))" + + +(*val satpMode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*) + +definition satpMode_of_bits :: " Architecture \(4)Word.word \(SATPMode)option " where + " satpMode_of_bits (g__113 :: Architecture) (b__0 :: satp_mode) = ( Some Sbare )" + + +(*val uop_of_num : integer -> uop*) + +definition uop_of_num :: " int \ uop " where + " uop_of_num arg0 = ( + (let l__42 = arg0 in + if (((l__42 = (( 0 :: int)::ii)))) then RISCV_LUI + else RISCV_AUIPC))" + + +(*val num_of_uop : uop -> integer*) + +fun num_of_uop :: " uop \ int " where + " num_of_uop RISCV_LUI = ( (( 0 :: int)::ii))" +|" num_of_uop RISCV_AUIPC = ( (( 1 :: int)::ii))" + + +(*val bop_of_num : integer -> bop*) + +definition bop_of_num :: " int \ bop " where + " bop_of_num arg0 = ( + (let l__37 = arg0 in + if (((l__37 = (( 0 :: int)::ii)))) then RISCV_BEQ + else if (((l__37 = (( 1 :: int)::ii)))) then RISCV_BNE + else if (((l__37 = (( 2 :: int)::ii)))) then RISCV_BLT + else if (((l__37 = (( 3 :: int)::ii)))) then RISCV_BGE + else if (((l__37 = (( 4 :: int)::ii)))) then RISCV_BLTU + else RISCV_BGEU))" + + +(*val num_of_bop : bop -> integer*) + +fun num_of_bop :: " bop \ int " where + " num_of_bop RISCV_BEQ = ( (( 0 :: int)::ii))" +|" num_of_bop RISCV_BNE = ( (( 1 :: int)::ii))" +|" num_of_bop RISCV_BLT = ( (( 2 :: int)::ii))" +|" num_of_bop RISCV_BGE = ( (( 3 :: int)::ii))" +|" num_of_bop RISCV_BLTU = ( (( 4 :: int)::ii))" +|" num_of_bop RISCV_BGEU = ( (( 5 :: int)::ii))" + + +(*val iop_of_num : integer -> iop*) + +definition iop_of_num :: " int \ iop " where + " iop_of_num arg0 = ( + (let l__32 = arg0 in + if (((l__32 = (( 0 :: int)::ii)))) then RISCV_ADDI + else if (((l__32 = (( 1 :: int)::ii)))) then RISCV_SLTI + else if (((l__32 = (( 2 :: int)::ii)))) then RISCV_SLTIU + else if (((l__32 = (( 3 :: int)::ii)))) then RISCV_XORI + else if (((l__32 = (( 4 :: int)::ii)))) then RISCV_ORI + else RISCV_ANDI))" + + +(*val num_of_iop : iop -> integer*) + +fun num_of_iop :: " iop \ int " where + " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))" +|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))" +|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))" +|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))" +|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))" +|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))" + + +(*val sop_of_num : integer -> sop*) + +definition sop_of_num :: " int \ sop " where + " sop_of_num arg0 = ( + (let l__30 = arg0 in + if (((l__30 = (( 0 :: int)::ii)))) then RISCV_SLLI + else if (((l__30 = (( 1 :: int)::ii)))) then RISCV_SRLI + else RISCV_SRAI))" + + +(*val num_of_sop : sop -> integer*) + +fun num_of_sop :: " sop \ int " where + " num_of_sop RISCV_SLLI = ( (( 0 :: int)::ii))" +|" num_of_sop RISCV_SRLI = ( (( 1 :: int)::ii))" +|" num_of_sop RISCV_SRAI = ( (( 2 :: int)::ii))" + + +(*val rop_of_num : integer -> rop*) + +definition rop_of_num :: " int \ rop " where + " rop_of_num arg0 = ( + (let l__21 = arg0 in + if (((l__21 = (( 0 :: int)::ii)))) then RISCV_ADD + else if (((l__21 = (( 1 :: int)::ii)))) then RISCV_SUB + else if (((l__21 = (( 2 :: int)::ii)))) then RISCV_SLL + else if (((l__21 = (( 3 :: int)::ii)))) then RISCV_SLT + else if (((l__21 = (( 4 :: int)::ii)))) then RISCV_SLTU + else if (((l__21 = (( 5 :: int)::ii)))) then RISCV_XOR + else if (((l__21 = (( 6 :: int)::ii)))) then RISCV_SRL + else if (((l__21 = (( 7 :: int)::ii)))) then RISCV_SRA + else if (((l__21 = (( 8 :: int)::ii)))) then RISCV_OR + else RISCV_AND))" + + +(*val num_of_rop : rop -> integer*) + +fun num_of_rop :: " rop \ int " where + " num_of_rop RISCV_ADD = ( (( 0 :: int)::ii))" +|" num_of_rop RISCV_SUB = ( (( 1 :: int)::ii))" +|" num_of_rop RISCV_SLL = ( (( 2 :: int)::ii))" +|" num_of_rop RISCV_SLT = ( (( 3 :: int)::ii))" +|" num_of_rop RISCV_SLTU = ( (( 4 :: int)::ii))" +|" num_of_rop RISCV_XOR = ( (( 5 :: int)::ii))" +|" num_of_rop RISCV_SRL = ( (( 6 :: int)::ii))" +|" num_of_rop RISCV_SRA = ( (( 7 :: int)::ii))" +|" num_of_rop RISCV_OR = ( (( 8 :: int)::ii))" +|" num_of_rop RISCV_AND = ( (( 9 :: int)::ii))" + + +(*val ropw_of_num : integer -> ropw*) + +definition ropw_of_num :: " int \ ropw " where + " ropw_of_num arg0 = ( + (let l__17 = arg0 in + if (((l__17 = (( 0 :: int)::ii)))) then RISCV_ADDW + else if (((l__17 = (( 1 :: int)::ii)))) then RISCV_SUBW + else if (((l__17 = (( 2 :: int)::ii)))) then RISCV_SLLW + else if (((l__17 = (( 3 :: int)::ii)))) then RISCV_SRLW + else RISCV_SRAW))" + + +(*val num_of_ropw : ropw -> integer*) + +fun num_of_ropw :: " ropw \ int " where + " num_of_ropw RISCV_ADDW = ( (( 0 :: int)::ii))" +|" num_of_ropw RISCV_SUBW = ( (( 1 :: int)::ii))" +|" num_of_ropw RISCV_SLLW = ( (( 2 :: int)::ii))" +|" num_of_ropw RISCV_SRLW = ( (( 3 :: int)::ii))" +|" num_of_ropw RISCV_SRAW = ( (( 4 :: int)::ii))" + + +(*val amoop_of_num : integer -> amoop*) + +definition amoop_of_num :: " int \ amoop " where + " amoop_of_num arg0 = ( + (let l__9 = arg0 in + if (((l__9 = (( 0 :: int)::ii)))) then AMOSWAP + else if (((l__9 = (( 1 :: int)::ii)))) then AMOADD + else if (((l__9 = (( 2 :: int)::ii)))) then AMOXOR + else if (((l__9 = (( 3 :: int)::ii)))) then AMOAND + else if (((l__9 = (( 4 :: int)::ii)))) then AMOOR + else if (((l__9 = (( 5 :: int)::ii)))) then AMOMIN + else if (((l__9 = (( 6 :: int)::ii)))) then AMOMAX + else if (((l__9 = (( 7 :: int)::ii)))) then AMOMINU + else AMOMAXU))" + + +(*val num_of_amoop : amoop -> integer*) + +fun num_of_amoop :: " amoop \ int " where + " num_of_amoop AMOSWAP = ( (( 0 :: int)::ii))" +|" num_of_amoop AMOADD = ( (( 1 :: int)::ii))" +|" num_of_amoop AMOXOR = ( (( 2 :: int)::ii))" +|" num_of_amoop AMOAND = ( (( 3 :: int)::ii))" +|" num_of_amoop AMOOR = ( (( 4 :: int)::ii))" +|" num_of_amoop AMOMIN = ( (( 5 :: int)::ii))" +|" num_of_amoop AMOMAX = ( (( 6 :: int)::ii))" +|" num_of_amoop AMOMINU = ( (( 7 :: int)::ii))" +|" num_of_amoop AMOMAXU = ( (( 8 :: int)::ii))" + + +(*val csrop_of_num : integer -> csrop*) + +definition csrop_of_num :: " int \ csrop " where + " csrop_of_num arg0 = ( + (let l__7 = arg0 in + if (((l__7 = (( 0 :: int)::ii)))) then CSRRW + else if (((l__7 = (( 1 :: int)::ii)))) then CSRRS + else CSRRC))" + + +(*val num_of_csrop : csrop -> integer*) + +fun num_of_csrop :: " csrop \ int " where + " num_of_csrop CSRRW = ( (( 0 :: int)::ii))" +|" num_of_csrop CSRRS = ( (( 1 :: int)::ii))" +|" num_of_csrop CSRRC = ( (( 2 :: int)::ii))" + + +(*val word_width_of_num : integer -> word_width*) + +definition word_width_of_num :: " int \ word_width " where + " word_width_of_num arg0 = ( + (let l__4 = arg0 in + if (((l__4 = (( 0 :: int)::ii)))) then BYTE + else if (((l__4 = (( 1 :: int)::ii)))) then HALF + else if (((l__4 = (( 2 :: int)::ii)))) then WORD + else DOUBLE))" + + +(*val num_of_word_width : word_width -> integer*) + +fun num_of_word_width :: " word_width \ int " where + " num_of_word_width BYTE = ( (( 0 :: int)::ii))" +|" num_of_word_width HALF = ( (( 1 :: int)::ii))" +|" num_of_word_width WORD = ( (( 2 :: int)::ii))" +|" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))" + + +(*val is_aligned_addr : mword ty64 -> integer -> bool*) + +definition is_aligned_addr :: "(64)Word.word \ int \ bool " where + " is_aligned_addr (addr :: xlenbits) (width :: int) = ( + (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))" + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition checked_mem_read :: " ReadType \(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = ( + (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \ (\ (w__0 :: + (( 'int8_times_n::len)Word.word)option) . + return ((case (t, w__0) of + (Instruction, None) => MemException E_Fetch_Access_Fault + | (Data, None) => MemException E_Load_Access_Fault + | (_, Some (v)) => MemValue v + ))))" + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition MEMr :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr addr width = ( (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_acquire :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_strong_acquire :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_strong_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_acquire :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_strong_acquire :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_strong_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition mem_read :: "(64)Word.word \ int \ bool \ bool \ bool \((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " mem_read addr width aq rl res = ( + if ((((((aq \ res))) \ ((\ ((is_aligned_addr addr width))))))) then + return (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (False, False, False) => (MEMr addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, False) => (MEMr_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, False, True) => + (MEMr_reserved addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, True) => + (MEMr_reserved_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, False) => throw (Error_not_implemented (''load.rl'')) + | (True, True, False) => + (MEMr_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, True) => throw (Error_not_implemented (''lr.rl'')) + | (True, True, True) => + (MEMr_reserved_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + ))" + + +(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_ea :: "(64)Word.word \ int \ bool \ bool \ bool \((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_ea addr width aq rl con = ( + if ((((((rl \ con))) \ ((\ ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => MEMea addr width \ return (MemValue () ) + | (False, True, False) => MEMea_release addr width \ return (MemValue () ) + | (False, False, True) => MEMea_conditional addr width \ return (MemValue () ) + | (False, True, True) => MEMea_conditional_release addr width \ return (MemValue () ) + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMea_strong_release addr width \ return (MemValue () ) + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMea_conditional_strong_release addr width \ return (MemValue () ) + ))" + + +(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition checked_mem_write :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( + RISCV_write addr width data \ (\ (w__0 :: bool) . + return (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault)))" + + +(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition MEMval :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_release :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_strong_release :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_strong_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_release :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_strong_release :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )" + + +(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_value :: "(64)Word.word \ int \('int8_times_n::len)Word.word \ bool \ bool \ bool \((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_value addr width value1 aq rl con = ( + if ((((((rl \ con))) \ ((\ ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => MEMval addr width value1 + | (False, True, False) => MEMval_release addr width value1 + | (False, False, True) => MEMval_conditional addr width value1 + | (False, True, True) => MEMval_conditional_release addr width value1 + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMval_strong_release addr width value1 + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMval_conditional_strong_release addr width value1 + ))" + + +(*val _get_Misa : Misa -> mword ty64*) + +fun get_Misa :: " Misa \(64)Word.word " where + " get_Misa (Mk_Misa (v)) = ( v )" + + +(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*) + +definition set_Misa :: "((regstate),(register_value),(Misa))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Misa v) in + write_reg r_ref r)))" + + +(*val _get_SV39_PTE : SV39_PTE -> mword ty64*) + +(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) + +(*val _get_Misa_MXL : Misa -> mword ty2*) + +fun get_Misa_MXL :: " Misa \(2)Word.word " where + " get_Misa_MXL (Mk_Misa (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*) + +definition set_Misa_MXL :: "((regstate),(register_value),(Misa))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_MXL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*) + +fun update_Misa_MXL :: " Misa \(2)Word.word \ Misa " where + " update_Misa_MXL (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_Z : Misa -> mword ty1*) + +fun get_Misa_Z :: " Misa \(1)Word.word " where + " get_Misa_Z (Mk_Misa (v)) = ( (subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Z :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_Z r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 25 :: int)::ii) (( 25 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Z : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Z :: " Misa \(1)Word.word \ Misa " where + " update_Misa_Z (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_Y : Misa -> mword ty1*) + +fun get_Misa_Y :: " Misa \(1)Word.word " where + " get_Misa_Y (Mk_Misa (v)) = ( (subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Y :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_Y r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 24 :: int)::ii) (( 24 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Y : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Y :: " Misa \(1)Word.word \ Misa " where + " update_Misa_Y (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_X : Misa -> mword ty1*) + +fun get_Misa_X :: " Misa \(1)Word.word " where + " get_Misa_X (Mk_Misa (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_X :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_X r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_X : Misa -> mword ty1 -> Misa*) + +fun update_Misa_X :: " Misa \(1)Word.word \ Misa " where + " update_Misa_X (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_X : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_W : Misa -> mword ty1*) + +fun get_Misa_W :: " Misa \(1)Word.word " where + " get_Misa_W (Mk_Misa (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_W :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_W r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_W : Misa -> mword ty1 -> Misa*) + +fun update_Misa_W :: " Misa \(1)Word.word \ Misa " where + " update_Misa_W (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_W : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_V : Misa -> mword ty1*) + +fun get_Misa_V :: " Misa \(1)Word.word " where + " get_Misa_V (Mk_Misa (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_V :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_V r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_V : Misa -> mword ty1 -> Misa*) + +fun update_Misa_V :: " Misa \(1)Word.word \ Misa " where + " update_Misa_V (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_V : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_U : Misa -> mword ty1*) + +fun get_Misa_U :: " Misa \(1)Word.word " where + " get_Misa_U (Mk_Misa (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_U :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_U r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_U : Misa -> mword ty1 -> Misa*) + +fun update_Misa_U :: " Misa \(1)Word.word \ Misa " where + " update_Misa_U (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_U : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_T : Misa -> mword ty1*) + +fun get_Misa_T :: " Misa \(1)Word.word " where + " get_Misa_T (Mk_Misa (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_T :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_T r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_T : Misa -> mword ty1 -> Misa*) + +fun update_Misa_T :: " Misa \(1)Word.word \ Misa " where + " update_Misa_T (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_S : Misa -> mword ty1*) + +fun get_Misa_S :: " Misa \(1)Word.word " where + " get_Misa_S (Mk_Misa (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_S :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_S r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_S : Misa -> mword ty1 -> Misa*) + +fun update_Misa_S :: " Misa \(1)Word.word \ Misa " where + " update_Misa_S (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_R : Misa -> mword ty1*) + +fun get_Misa_R :: " Misa \(1)Word.word " where + " get_Misa_R (Mk_Misa (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_R :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_R r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_R : Misa -> mword ty1 -> Misa*) + +fun update_Misa_R :: " Misa \(1)Word.word \ Misa " where + " update_Misa_R (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_R : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_Q : Misa -> mword ty1*) + +fun get_Misa_Q :: " Misa \(1)Word.word " where + " get_Misa_Q (Mk_Misa (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Q :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_Q r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 16 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Q : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Q :: " Misa \(1)Word.word \ Misa " where + " update_Misa_Q (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_P : Misa -> mword ty1*) + +fun get_Misa_P :: " Misa \(1)Word.word " where + " get_Misa_P (Mk_Misa (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_P :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_P r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_P : Misa -> mword ty1 -> Misa*) + +fun update_Misa_P :: " Misa \(1)Word.word \ Misa " where + " update_Misa_P (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_O : Misa -> mword ty1*) + +fun get_Misa_O :: " Misa \(1)Word.word " where + " get_Misa_O (Mk_Misa (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_O :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_O r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 14 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_O : Misa -> mword ty1 -> Misa*) + +fun update_Misa_O :: " Misa \(1)Word.word \ Misa " where + " update_Misa_O (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_N : Misa -> mword ty1*) + +fun get_Misa_N :: " Misa \(1)Word.word " where + " get_Misa_N (Mk_Misa (v)) = ( (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_N :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_N r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_N : Misa -> mword ty1 -> Misa*) + +fun update_Misa_N :: " Misa \(1)Word.word \ Misa " where + " update_Misa_N (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_M : Misa -> mword ty1*) + +fun get_Misa_M :: " Misa \(1)Word.word " where + " get_Misa_M (Mk_Misa (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_M :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_M r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_M : Misa -> mword ty1 -> Misa*) + +fun update_Misa_M :: " Misa \(1)Word.word \ Misa " where + " update_Misa_M (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_L : Misa -> mword ty1*) + +fun get_Misa_L :: " Misa \(1)Word.word " where + " get_Misa_L (Mk_Misa (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_L :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_L r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_L : Misa -> mword ty1 -> Misa*) + +fun update_Misa_L :: " Misa \(1)Word.word \ Misa " where + " update_Misa_L (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_K : Misa -> mword ty1*) + +fun get_Misa_K :: " Misa \(1)Word.word " where + " get_Misa_K (Mk_Misa (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_K :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_K r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_K : Misa -> mword ty1 -> Misa*) + +fun update_Misa_K :: " Misa \(1)Word.word \ Misa " where + " update_Misa_K (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_J : Misa -> mword ty1*) + +fun get_Misa_J :: " Misa \(1)Word.word " where + " get_Misa_J (Mk_Misa (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_J :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_J r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_J : Misa -> mword ty1 -> Misa*) + +fun update_Misa_J :: " Misa \(1)Word.word \ Misa " where + " update_Misa_J (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_I : Misa -> mword ty1*) + +fun get_Misa_I :: " Misa \(1)Word.word " where + " get_Misa_I (Mk_Misa (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_I :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_I r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_I : Misa -> mword ty1 -> Misa*) + +fun update_Misa_I :: " Misa \(1)Word.word \ Misa " where + " update_Misa_I (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_H : Misa -> mword ty1*) + +fun get_Misa_H :: " Misa \(1)Word.word " where + " get_Misa_H (Mk_Misa (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_H :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_H r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_H : Misa -> mword ty1 -> Misa*) + +fun update_Misa_H :: " Misa \(1)Word.word \ Misa " where + " update_Misa_H (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_G : Misa -> mword ty1*) + +fun get_Misa_G :: " Misa \(1)Word.word " where + " get_Misa_G (Mk_Misa (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_G :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_G r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_G : Misa -> mword ty1 -> Misa*) + +fun update_Misa_G :: " Misa \(1)Word.word \ Misa " where + " update_Misa_G (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_G : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_F : Misa -> mword ty1*) + +fun get_Misa_F :: " Misa \(1)Word.word " where + " get_Misa_F (Mk_Misa (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_F :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_F r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_F : Misa -> mword ty1 -> Misa*) + +fun update_Misa_F :: " Misa \(1)Word.word \ Misa " where + " update_Misa_F (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_E : Misa -> mword ty1*) + +fun get_Misa_E :: " Misa \(1)Word.word " where + " get_Misa_E (Mk_Misa (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_E :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_E r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_E : Misa -> mword ty1 -> Misa*) + +fun update_Misa_E :: " Misa \(1)Word.word \ Misa " where + " update_Misa_E (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_D : Misa -> mword ty1*) + +fun get_Misa_D :: " Misa \(1)Word.word " where + " get_Misa_D (Mk_Misa (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_D :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_D r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_D : Misa -> mword ty1 -> Misa*) + +fun update_Misa_D :: " Misa \(1)Word.word \ Misa " where + " update_Misa_D (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_D : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_C : Misa -> mword ty1*) + +fun get_Misa_C :: " Misa \(1)Word.word " where + " get_Misa_C (Mk_Misa (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_C :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_C r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_C : Misa -> mword ty1 -> Misa*) + +fun update_Misa_C :: " Misa \(1)Word.word \ Misa " where + " update_Misa_C (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_B : Misa -> mword ty1*) + +fun get_Misa_B :: " Misa \(1)Word.word " where + " get_Misa_B (Mk_Misa (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_B :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_B r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_B : Misa -> mword ty1 -> Misa*) + +fun update_Misa_B :: " Misa \(1)Word.word \ Misa " where + " update_Misa_B (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_A : Misa -> mword ty1*) + +fun get_Misa_A :: " Misa \(1)Word.word " where + " get_Misa_A (Mk_Misa (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_A :: "((regstate),(register_value),(Misa))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Misa_A r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_A : Misa -> mword ty1 -> Misa*) + +fun update_Misa_A :: " Misa \(1)Word.word \ Misa " where + " update_Misa_A (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_A : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val legalize_misa : Misa -> mword ty64 -> Misa*) + +definition legalize_misa :: " Misa \(64)Word.word \ Misa " where + " legalize_misa (m :: Misa) (v :: xlenbits) = ( m )" + + +(*val _get_Mstatus : Mstatus -> mword ty64*) + +fun get_Mstatus :: " Mstatus \(64)Word.word " where + " get_Mstatus (Mk_Mstatus (v)) = ( v )" + + +(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) + +definition set_Mstatus :: "((regstate),(register_value),(Mstatus))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Mstatus v) in + write_reg r_ref r)))" + + +(*val _get_Mstatus_SD : Mstatus -> mword ty1*) + +fun get_Mstatus_SD :: " Mstatus \(1)Word.word " where + " get_Mstatus_SD (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SD :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SD r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SD :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_SD (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SD : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SXL : Mstatus -> mword ty2*) + +fun get_Mstatus_SXL :: " Mstatus \(2)Word.word " where + " get_Mstatus_SXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_SXL :: "((regstate),(register_value),(Mstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SXL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 34 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_SXL :: " Mstatus \(2)Word.word \ Mstatus " where + " update_Mstatus_SXL (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_UXL : Mstatus -> mword ty2*) + +fun get_Mstatus_UXL :: " Mstatus \(2)Word.word " where + " get_Mstatus_UXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_UXL :: "((regstate),(register_value),(Mstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_UXL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_UXL :: " Mstatus \(2)Word.word \ Mstatus " where + " update_Mstatus_UXL (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_UXL : Sstatus -> mword ty2*) + +(*val _set_Sstatus_UXL : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_TSR : Mstatus -> mword ty1*) + +fun get_Mstatus_TSR :: " Mstatus \(1)Word.word " where + " get_Mstatus_TSR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TSR :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_TSR r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TSR :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_TSR (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_TW : Mstatus -> mword ty1*) + +fun get_Mstatus_TW :: " Mstatus \(1)Word.word " where + " get_Mstatus_TW (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TW :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_TW r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TW :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_TW (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_TVM : Mstatus -> mword ty1*) + +fun get_Mstatus_TVM :: " Mstatus \(1)Word.word " where + " get_Mstatus_TVM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TVM :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_TVM r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TVM :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_TVM (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_MXR : Mstatus -> mword ty1*) + +fun get_Mstatus_MXR :: " Mstatus \(1)Word.word " where + " get_Mstatus_MXR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MXR :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_MXR r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MXR :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_MXR (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_MXR : Sstatus -> mword ty1*) + +(*val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SUM : Mstatus -> mword ty1*) + +fun get_Mstatus_SUM :: " Mstatus \(1)Word.word " where + " get_Mstatus_SUM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SUM :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SUM r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SUM :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_SUM (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SUM : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPRV : Mstatus -> mword ty1*) + +fun get_Mstatus_MPRV :: " Mstatus \(1)Word.word " where + " get_Mstatus_MPRV (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MPRV :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_MPRV r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MPRV :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_MPRV (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_XS : Mstatus -> mword ty2*) + +fun get_Mstatus_XS :: " Mstatus \(2)Word.word " where + " get_Mstatus_XS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_XS :: "((regstate),(register_value),(Mstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_XS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_XS :: " Mstatus \(2)Word.word \ Mstatus " where + " update_Mstatus_XS (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_XS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_FS : Mstatus -> mword ty2*) + +fun get_Mstatus_FS :: " Mstatus \(2)Word.word " where + " get_Mstatus_FS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_FS :: "((regstate),(register_value),(Mstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_FS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_FS :: " Mstatus \(2)Word.word \ Mstatus " where + " update_Mstatus_FS (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_FS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_MPP : Mstatus -> mword ty2*) + +fun get_Mstatus_MPP :: " Mstatus \(2)Word.word " where + " get_Mstatus_MPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_MPP :: "((regstate),(register_value),(Mstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_MPP r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_MPP :: " Mstatus \(2)Word.word \ Mstatus " where + " update_Mstatus_MPP (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SPP : Mstatus -> mword ty1*) + +fun get_Mstatus_SPP :: " Mstatus \(1)Word.word " where + " get_Mstatus_SPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SPP :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SPP r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SPP :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_SPP (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPP : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_MPIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_MPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MPIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_MPIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MPIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_MPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_SPIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_SPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SPIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SPIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SPIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_SPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_UPIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_UPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_UPIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_UPIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_UPIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_UPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MIE : Mstatus -> mword ty1*) + +fun get_Mstatus_MIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_MIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_MIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_MIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SIE : Mstatus -> mword ty1*) + +fun get_Mstatus_SIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_SIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_SIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_SIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UIE : Mstatus -> mword ty1*) + +fun get_Mstatus_UIE :: " Mstatus \(1)Word.word " where + " get_Mstatus_UIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_UIE :: "((regstate),(register_value),(Mstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mstatus_UIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_UIE :: " Mstatus \(1)Word.word \ Mstatus " where + " update_Mstatus_UIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val legalize_mstatus : Mstatus -> mword ty64 -> Mstatus*) + +definition legalize_mstatus :: " Mstatus \(64)Word.word \ Mstatus " where + " legalize_mstatus (o1 :: Mstatus) (v :: xlenbits) = ( + (let (m :: Mstatus) = (Mk_Mstatus v) in + (let m = (update_Mstatus_XS m ((extStatus_to_bits Off :: 2 Word.word))) in + (let m = + (update_Mstatus_SD m + ((bool_to_bits + ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)))) + :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))) \ (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)))) + :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))) + :: 1 Word.word))) in + (let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1 :: 2 Word.word))) in + (let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1 :: 2 Word.word))) in + (let m = (update_Mstatus_UPIE m ((bool_to_bits False :: 1 Word.word))) in + update_Mstatus_UIE m ((bool_to_bits False :: 1 Word.word)))))))))" + + +(*val cur_Architecture : unit -> M Architecture*) + +definition cur_Architecture :: " unit \((register_value),(Architecture),(exception))monad " where + " cur_Architecture _ = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (case w__0 of + Machine => + read_reg misa_ref \ (\ (w__1 :: Misa) . return ((get_Misa_MXL w__1 :: 2 Word.word))) + | Supervisor => + read_reg mstatus_ref \ (\ (w__2 :: Mstatus) . return ((get_Mstatus_SXL w__2 :: 2 Word.word))) + | User => + read_reg mstatus_ref \ (\ (w__3 :: Mstatus) . return ((get_Mstatus_UXL w__3 :: 2 Word.word))) + ) \ (\ (a :: arch_xlen) . + (case ((architecture a)) of + Some (a) => return a + | None => internal_error (''Invalid current architecture'') + ))))" + + +(*val in32BitMode : unit -> M bool*) + +definition in32BitMode :: " unit \((register_value),(bool),(exception))monad " where + " in32BitMode _ = ( cur_Architecture () \ (\ (w__0 :: Architecture) . return (((w__0 = RV32)))))" + + +(*val haveAtomics : unit -> M bool*) + +definition haveAtomics :: " unit \((register_value),(bool),(exception))monad " where + " haveAtomics _ = ( + read_reg misa_ref \ (\ (w__0 :: Misa) . + return (((((get_Misa_A w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveRVC : unit -> M bool*) + +definition haveRVC :: " unit \((register_value),(bool),(exception))monad " where + " haveRVC _ = ( + read_reg misa_ref \ (\ (w__0 :: Misa) . + return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveMulDiv : unit -> M bool*) + +definition haveMulDiv :: " unit \((register_value),(bool),(exception))monad " where + " haveMulDiv _ = ( + read_reg misa_ref \ (\ (w__0 :: Misa) . + return (((((get_Misa_M w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveFP : unit -> M bool*) + +definition haveFP :: " unit \((register_value),(bool),(exception))monad " where + " haveFP _ = ( + or_boolM + (read_reg misa_ref \ (\ (w__0 :: Misa) . + return (((((get_Misa_F w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (read_reg misa_ref \ (\ (w__1 :: Misa) . + return (((((get_Misa_D w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))" + + +(*val _get_Minterrupts : Minterrupts -> mword ty64*) + +fun get_Minterrupts :: " Minterrupts \(64)Word.word " where + " get_Minterrupts (Mk_Minterrupts (v)) = ( v )" + + +(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) + +definition set_Minterrupts :: "((regstate),(register_value),(Minterrupts))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Minterrupts v) in + write_reg r_ref r)))" + + +(*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MEI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_MEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MEI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_MEI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MEI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_MEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_SEI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_SEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_SEI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_SEI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_SEI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_SEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_UEI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_UEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_UEI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_UEI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_UEI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_UEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MTI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_MTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MTI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_MTI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MTI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_MTI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_STI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_STI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_STI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_STI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_STI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_STI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_STI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_STI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_UTI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_UTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_UTI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_UTI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_UTI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_UTI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MSI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_MSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MSI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_MSI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MSI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_MSI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_SSI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_SSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_SSI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_SSI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_SSI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_SSI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_USI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_USI :: " Minterrupts \(1)Word.word " where + " get_Minterrupts_USI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_USI :: "((regstate),(register_value),(Minterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Minterrupts_USI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_USI :: " Minterrupts \(1)Word.word \ Minterrupts " where + " update_Minterrupts_USI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_USI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val legalize_mip : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mip :: " Minterrupts \(64)Word.word \ Minterrupts " where + " legalize_mip (o1 :: Minterrupts) (v :: xlenbits) = ( + (let v = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))))))" + + +(*val legalize_mie : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mie :: " Minterrupts \(64)Word.word \ Minterrupts " where + " legalize_mie (o1 :: Minterrupts) (v :: xlenbits) = ( + (let v = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v :: 1 Word.word))) in + (let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v :: 1 Word.word))) in + (let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word)))))))))" + + +(*val legalize_mideleg : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mideleg :: " Minterrupts \(64)Word.word \ Minterrupts " where + " legalize_mideleg (o1 :: Minterrupts) (v :: xlenbits) = ( + (let m = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_MEI m ((bool_to_bits False :: 1 Word.word))) in + (let m = (update_Minterrupts_MTI m ((bool_to_bits False :: 1 Word.word))) in + update_Minterrupts_MSI m ((bool_to_bits False :: 1 Word.word))))))" + + +(*val _get_Medeleg : Medeleg -> mword ty64*) + +fun get_Medeleg :: " Medeleg \(64)Word.word " where + " get_Medeleg (Mk_Medeleg (v)) = ( v )" + + +(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) + +definition set_Medeleg :: "((regstate),(register_value),(Medeleg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Medeleg v) in + write_reg r_ref r)))" + + +(*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Page_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Page_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Page_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Page_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Page_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Page_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Page_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Page_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Page_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_MEnvCall :: " Medeleg \(1)Word.word " where + " get_Medeleg_MEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_MEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_MEnvCall r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_MEnvCall :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_MEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_SEnvCall :: " Medeleg \(1)Word.word " where + " get_Medeleg_SEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_SEnvCall r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SEnvCall :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_SEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_UEnvCall :: " Medeleg \(1)Word.word " where + " get_Medeleg_UEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_UEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_UEnvCall r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_UEnvCall :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_UEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Access_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Access_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Addr_Align :: " Medeleg \(1)Word.word " where + " get_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Addr_Align :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Access_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Access_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Addr_Align :: " Medeleg \(1)Word.word " where + " get_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Addr_Align :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*) + +fun get_Medeleg_Breakpoint :: " Medeleg \(1)Word.word " where + " get_Medeleg_Breakpoint (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Breakpoint :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Breakpoint r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Breakpoint :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Breakpoint (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*) + +fun get_Medeleg_Illegal_Instr :: " Medeleg \(1)Word.word " where + " get_Medeleg_Illegal_Instr (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Illegal_Instr :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Illegal_Instr r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Illegal_Instr :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Illegal_Instr (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Access_Fault :: " Medeleg \(1)Word.word " where + " get_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Access_Fault :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Addr_Align :: " Medeleg \(1)Word.word " where + " get_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Addr_Align :: " Medeleg \(1)Word.word \ Medeleg " where + " update_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val legalize_medeleg : Medeleg -> mword ty64 -> Medeleg*) + +definition legalize_medeleg :: " Medeleg \(64)Word.word \ Medeleg " where + " legalize_medeleg (o1 :: Medeleg) (v :: xlenbits) = ( + (let m = (Mk_Medeleg v) in + update_Medeleg_MEnvCall m ((bool_to_bits False :: 1 Word.word))))" + + +(*val _get_Mtvec : Mtvec -> mword ty64*) + +fun get_Mtvec :: " Mtvec \(64)Word.word " where + " get_Mtvec (Mk_Mtvec (v)) = ( v )" + + +(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) + +definition set_Mtvec :: "((regstate),(register_value),(Mtvec))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Mtvec r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Mtvec v) in + write_reg r_ref r)))" + + +(*val _get_Mtvec_Base : Mtvec -> mword ty62*) + +fun get_Mtvec_Base :: " Mtvec \(62)Word.word " where + " get_Mtvec_Base (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word))" + + +(*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*) + +definition set_Mtvec_Base :: "((regstate),(register_value),(Mtvec))register_ref \(62)Word.word \((register_value),(unit),(exception))monad " where + " set_Mtvec_Base r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mtvec) . + (let r = ((get_Mtvec w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mtvec r)))))" + + +(*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*) + +fun update_Mtvec_Base :: " Mtvec \(62)Word.word \ Mtvec " where + " update_Mtvec_Base (Mk_Mtvec (v)) x = ( + Mk_Mtvec ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mtvec_Mode : Mtvec -> mword ty2*) + +fun get_Mtvec_Mode :: " Mtvec \(2)Word.word " where + " get_Mtvec_Mode (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*) + +definition set_Mtvec_Mode :: "((regstate),(register_value),(Mtvec))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Mtvec_Mode r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mtvec) . + (let r = ((get_Mtvec w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mtvec r)))))" + + +(*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*) + +fun update_Mtvec_Mode :: " Mtvec \(2)Word.word \ Mtvec " where + " update_Mtvec_Mode (Mk_Mtvec (v)) x = ( + Mk_Mtvec ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*) + +(*val _get_Satp64_Mode : Satp64 -> mword ty4*) + +(*val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit*) + +(*val legalize_tvec : Mtvec -> mword ty64 -> Mtvec*) + +definition legalize_tvec :: " Mtvec \(64)Word.word \ Mtvec " where + " legalize_tvec (o1 :: Mtvec) (v :: xlenbits) = ( + (let v = (Mk_Mtvec v) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v :: 2 Word.word)))) of + TV_Direct => v + | TV_Vector => v + | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 :: 2 Word.word)) + )))" + + +(*val _get_Mcause : Mcause -> mword ty64*) + +fun get_Mcause :: " Mcause \(64)Word.word " where + " get_Mcause (Mk_Mcause (v)) = ( v )" + + +(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) + +definition set_Mcause :: "((regstate),(register_value),(Mcause))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Mcause r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Mcause v) in + write_reg r_ref r)))" + + +(*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*) + +fun get_Mcause_IsInterrupt :: " Mcause \(1)Word.word " where + " get_Mcause_IsInterrupt (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*) + +definition set_Mcause_IsInterrupt :: "((regstate),(register_value),(Mcause))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Mcause_IsInterrupt r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mcause) . + (let r = ((get_Mcause w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mcause r)))))" + + +(*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*) + +fun update_Mcause_IsInterrupt :: " Mcause \(1)Word.word \ Mcause " where + " update_Mcause_IsInterrupt (Mk_Mcause (v)) x = ( + Mk_Mcause ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mcause_Cause : Mcause -> mword ty63*) + +fun get_Mcause_Cause :: " Mcause \(63)Word.word " where + " get_Mcause_Cause (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))" + + +(*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*) + +definition set_Mcause_Cause :: "((regstate),(register_value),(Mcause))register_ref \(63)Word.word \((register_value),(unit),(exception))monad " where + " set_Mcause_Cause r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Mcause) . + (let r = ((get_Mcause w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mcause r)))))" + + +(*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*) + +fun update_Mcause_Cause :: " Mcause \(63)Word.word \ Mcause " where + " update_Mcause_Cause (Mk_Mcause (v)) x = ( + Mk_Mcause ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*) + +definition tvec_addr :: " Mtvec \ Mcause \((64)Word.word)option " where + " tvec_addr (m :: Mtvec) (c :: Mcause) = ( + (let (base :: xlenbits) = + ((concat_vec ((get_Mtvec_Base m :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m :: 2 Word.word)))) of + TV_Direct => Some base + | TV_Vector => + if (((((get_Mcause_IsInterrupt c :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some ((add_vec base + ((shift_bits_left + ((EXTZ (( 64 :: int)::ii) ((get_Mcause_Cause c :: 63 Word.word)) :: 64 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 64 Word.word)) + :: 64 Word.word)) + else Some base + | TV_Reserved => None + )))" + + +(*val legalize_xepc : mword ty64 -> M (mword ty64)*) + +definition legalize_xepc :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " legalize_xepc v = ( + haveRVC () \ (\ (w__0 :: bool) . + return ((and_vec v + ((EXTS (( 64 :: int)::ii) + (if w__0 then (vec_of_bits [B1,B1,B0] :: 3 Word.word) + else (vec_of_bits [B1,B0,B0] :: 3 Word.word)) + :: 64 Word.word)) + :: 64 Word.word))))" + + +(*val _get_Sstatus : Sstatus -> mword ty64*) + +fun get_Sstatus :: " Sstatus \(64)Word.word " where + " get_Sstatus (Mk_Sstatus (v)) = ( v )" + + +(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) + +definition set_Sstatus :: "((regstate),(register_value),(Sstatus))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Sstatus v) in + write_reg r_ref r)))" + + +fun get_Sstatus_SD :: " Sstatus \(1)Word.word " where + " get_Sstatus_SD (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SD :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_SD r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SD :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_SD (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UXL :: " Sstatus \(2)Word.word " where + " get_Sstatus_UXL (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_UXL :: "((regstate),(register_value),(Sstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_UXL r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UXL :: " Sstatus \(2)Word.word \ Sstatus " where + " update_Sstatus_UXL (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_MXR :: " Sstatus \(1)Word.word " where + " get_Sstatus_MXR (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_MXR :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_MXR r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_MXR :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_MXR (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SUM :: " Sstatus \(1)Word.word " where + " get_Sstatus_SUM (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SUM :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_SUM r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SUM :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_SUM (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_XS :: " Sstatus \(2)Word.word " where + " get_Sstatus_XS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_XS :: "((regstate),(register_value),(Sstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_XS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_XS :: " Sstatus \(2)Word.word \ Sstatus " where + " update_Sstatus_XS (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_FS :: " Sstatus \(2)Word.word " where + " get_Sstatus_FS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_FS :: "((regstate),(register_value),(Sstatus))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_FS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_FS :: " Sstatus \(2)Word.word \ Sstatus " where + " update_Sstatus_FS (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SPP :: " Sstatus \(1)Word.word " where + " get_Sstatus_SPP (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SPP :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_SPP r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SPP :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_SPP (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SPIE :: " Sstatus \(1)Word.word " where + " get_Sstatus_SPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SPIE :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_SPIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SPIE :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_SPIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UPIE :: " Sstatus \(1)Word.word " where + " get_Sstatus_UPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_UPIE :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_UPIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UPIE :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_UPIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SIE :: " Sstatus \(1)Word.word " where + " get_Sstatus_SIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SIE :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_SIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SIE :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_SIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UIE :: " Sstatus \(1)Word.word " where + " get_Sstatus_UIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_UIE :: "((regstate),(register_value),(Sstatus))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sstatus_UIE r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UIE :: " Sstatus \(1)Word.word \ Sstatus " where + " update_Sstatus_UIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val lower_mstatus : Mstatus -> Sstatus*) + +definition lower_mstatus :: " Mstatus \ Sstatus " where + " lower_mstatus m = ( + (let s = (Mk_Sstatus ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = (update_Sstatus_SD s ((get_Mstatus_SD m :: 1 Word.word))) in + (let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m :: 2 Word.word))) in + (let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m :: 1 Word.word))) in + (let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m :: 1 Word.word))) in + (let s = (update_Sstatus_XS s ((get_Mstatus_XS m :: 2 Word.word))) in + (let s = (update_Sstatus_FS s ((get_Mstatus_FS m :: 2 Word.word))) in + (let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m :: 1 Word.word))) in + (let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m :: 1 Word.word))) in + (let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m :: 1 Word.word))) in + (let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m :: 1 Word.word))) in + update_Sstatus_UIE s ((get_Mstatus_UIE m :: 1 Word.word))))))))))))))" + + +(*val lift_sstatus : Mstatus -> Sstatus -> Mstatus*) + +definition lift_sstatus :: " Mstatus \ Sstatus \ Mstatus " where + " lift_sstatus (m :: Mstatus) (s :: Sstatus) = ( + (let m = (update_Mstatus_SD m ((get_Sstatus_SD s :: 1 Word.word))) in + (let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s :: 2 Word.word))) in + (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s :: 1 Word.word))) in + (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s :: 1 Word.word))) in + (let m = (update_Mstatus_XS m ((get_Sstatus_XS s :: 2 Word.word))) in + (let m = (update_Mstatus_FS m ((get_Sstatus_FS s :: 2 Word.word))) in + (let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s :: 1 Word.word))) in + (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s :: 1 Word.word))) in + (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s :: 1 Word.word))) in + (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s :: 1 Word.word))) in + update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word)))))))))))))" + + +(*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*) + +definition legalize_sstatus :: " Mstatus \(64)Word.word \ Mstatus " where + " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m (Mk_Sstatus v))" + + +(*val _get_Sedeleg : Sedeleg -> mword ty64*) + +fun get_Sedeleg :: " Sedeleg \(64)Word.word " where + " get_Sedeleg (Mk_Sedeleg (v)) = ( v )" + + +(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) + +definition set_Sedeleg :: "((regstate),(register_value),(Sedeleg))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Sedeleg v) in + write_reg r_ref r)))" + + +fun get_Sedeleg_UEnvCall :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_UEnvCall (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_UEnvCall :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_UEnvCall r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_UEnvCall :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_UEnvCall (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_SAMO_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_SAMO_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Load_Access_Fault :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Load_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Load_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Load_Access_Fault :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Load_Addr_Align :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Load_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Load_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Load_Addr_Align :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Breakpoint :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Breakpoint (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Breakpoint :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Breakpoint r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Breakpoint :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Breakpoint (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Illegal_Instr :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Illegal_Instr :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Illegal_Instr r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Illegal_Instr :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Fetch_Access_Fault r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \(1)Word.word " where + " get_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sedeleg_Fetch_Addr_Align r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \(1)Word.word \ Sedeleg " where + " update_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*) + +definition legalize_sedeleg :: " Sedeleg \(64)Word.word \ Sedeleg " where + " legalize_sedeleg (s :: Sedeleg) (v :: xlenbits) = ( + Mk_Sedeleg ((EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word)) :: 64 Word.word)))" + + +(*val _get_Sinterrupts : Sinterrupts -> mword ty64*) + +fun get_Sinterrupts :: " Sinterrupts \(64)Word.word " where + " get_Sinterrupts (Mk_Sinterrupts (v)) = ( v )" + + +(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) + +definition set_Sinterrupts :: "((regstate),(register_value),(Sinterrupts))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Sinterrupts v) in + write_reg r_ref r)))" + + +fun get_Sinterrupts_SEI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_SEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_SEI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_SEI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_SEI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_SEI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_UEI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_UEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_UEI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_UEI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_UEI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_UEI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_STI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_STI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_STI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_STI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_STI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_STI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_UTI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_UTI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_UTI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_UTI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_UTI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_UTI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_SSI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_SSI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_SSI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_SSI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_SSI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_SSI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_USI :: " Sinterrupts \(1)Word.word " where + " get_Sinterrupts_USI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_USI :: "((regstate),(register_value),(Sinterrupts))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_Sinterrupts_USI r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_USI :: " Sinterrupts \(1)Word.word \ Sinterrupts " where + " update_Sinterrupts_USI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*) + +definition lower_mip :: " Minterrupts \ Minterrupts \ Sinterrupts " where + " lower_mip (m :: Minterrupts) (d :: Minterrupts) = ( + (let (s :: Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word)))))))))" + + +(*val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts*) + +definition lower_mie :: " Minterrupts \ Minterrupts \ Sinterrupts " where + " lower_mie (m :: Minterrupts) (d :: Minterrupts) = ( + (let (s :: Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word)))))))))" + + +(*val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +definition lift_sip :: " Minterrupts \ Minterrupts \ Sinterrupts \ Minterrupts " where + " lift_sip (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = ( + (let (m :: Minterrupts) = o1 in + (let m = + (update_Minterrupts_SSI m + ((and_vec ((get_Sinterrupts_SSI s :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let m = + (update_Minterrupts_UEI m + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Minterrupts_USI m + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word))))))" + + +(*val legalize_sip : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_sip :: " Minterrupts \ Minterrupts \(64)Word.word \ Minterrupts " where + " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( + lift_sip m d (Mk_Sinterrupts v))" + + +(*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +definition lift_sie :: " Minterrupts \ Minterrupts \ Sinterrupts \ Minterrupts " where + " lift_sie (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = ( + (let (m :: Minterrupts) = o1 in + (let m = + (if (((((get_Minterrupts_SEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_SEI m ((get_Sinterrupts_SEI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_STI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_STI m ((get_Sinterrupts_STI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_SSI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_SSI m ((get_Sinterrupts_SSI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_UTI m ((get_Sinterrupts_UTI s :: 1 Word.word)) + else m) in + if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word)) + else m)))))))" + + +(*val legalize_sie : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_sie :: " Minterrupts \ Minterrupts \(64)Word.word \ Minterrupts " where + " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( + lift_sie m d (Mk_Sinterrupts v))" + + +(*val _get_Satp64 : Satp64 -> mword ty64*) + +fun get_Satp64 :: " Satp64 \(64)Word.word " where + " get_Satp64 (Mk_Satp64 (v)) = ( v )" + + +(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) + +definition set_Satp64 :: "((regstate),(register_value),(Satp64))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_Satp64 r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_Satp64 v) in + write_reg r_ref r)))" + + +fun get_Satp64_Mode :: " Satp64 \(4)Word.word " where + " get_Satp64_Mode (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))" + + +definition set_Satp64_Mode :: "((regstate),(register_value),(Satp64))register_ref \(4)Word.word \((register_value),(unit),(exception))monad " where + " set_Satp64_Mode r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 60 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +fun update_Satp64_Mode :: " Satp64 \(4)Word.word \ Satp64 " where + " update_Satp64_Mode (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Satp64_Asid : Satp64 -> mword ty16*) + +fun get_Satp64_Asid :: " Satp64 \(16)Word.word " where + " get_Satp64_Asid (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))" + + +(*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*) + +definition set_Satp64_Asid :: "((regstate),(register_value),(Satp64))register_ref \(16)Word.word \((register_value),(unit),(exception))monad " where + " set_Satp64_Asid r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 44 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +(*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*) + +fun update_Satp64_Asid :: " Satp64 \(16)Word.word \ Satp64 " where + " update_Satp64_Asid (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Satp64_PPN : Satp64 -> mword ty44*) + +fun get_Satp64_PPN :: " Satp64 \(44)Word.word " where + " get_Satp64_PPN (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))" + + +(*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*) + +definition set_Satp64_PPN :: "((regstate),(register_value),(Satp64))register_ref \(44)Word.word \((register_value),(unit),(exception))monad " where + " set_Satp64_PPN r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 43 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +(*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*) + +fun update_Satp64_PPN :: " Satp64 \(44)Word.word \ Satp64 " where + " update_Satp64_PPN (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*) + +definition legalize_satp :: " Architecture \(64)Word.word \(64)Word.word \(64)Word.word " where + " legalize_satp (a :: Architecture) (o1 :: xlenbits) (v :: xlenbits) = ( + (let s = (Mk_Satp64 v) in + (case ((satpMode_of_bits a ((get_Satp64_Mode s :: 4 Word.word)))) of + None => o1 + | Some (Sv32) => o1 + | Some (_) => (get_Satp64 s :: 64 Word.word) + )))" + + +(*val csr_name : mword ty12 -> string*) + +definition csr_name :: "(12)Word.word \ string " where + " csr_name csr = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''ustatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''uie'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''utvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''fflags'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''frm'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''fcsr'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycle'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''time'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instret'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycleh'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''timeh'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instreth'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sstatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''sedeleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''sideleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sie'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''stvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''scounteren'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sscratch'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''sepc'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''scause'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''stval'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sip'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''satp'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mvendorid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (''marchid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mimpid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mhartid'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mstatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''misa'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''medeleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mideleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mie'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''mtvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''mcounteren'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mscratch'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mepc'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''mcause'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mtval'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mip'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycle'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstret'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycleh'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstreth'') + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''tselect'') + else (''UNKNOWN'')))" + + +(*val csrAccess : mword ty12 -> mword ty2*) + +definition csrAccess :: "(12)Word.word \(2)Word.word " where + " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word))" + + +(*val csrPriv : mword ty12 -> mword ty2*) + +definition csrPriv :: "(12)Word.word \(2)Word.word " where + " csrPriv csr = ( (subrange_vec_dec csr (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" + + +(*val is_CSR_defined : mword ty12 -> Privilege -> bool*) + +definition is_CSR_defined :: "(12)Word.word \ Privilege \ bool " where + " is_CSR_defined (csr :: 12 bits) (p :: Privilege) = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \ (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else False))" + + +(*val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool*) + +definition check_CSR_access :: "(2)Word.word \(2)Word.word \ Privilege \ bool \ bool " where + " check_CSR_access csrrw csrpr p isWrite = ( + (((\ ((((((((bool_to_bits isWrite :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ (((csrrw = (vec_of_bits [B1,B1] :: 2 Word.word))))))))) \ ((zopz0zKzJ_u ((privLevel_to_bits p :: 2 Word.word)) csrpr))))" + + +(*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*) + +definition check_TVM_SATP :: "(12)Word.word \ Privilege \((register_value),(bool),(exception))monad " where + " check_TVM_SATP (csr :: csreg) (p :: Privilege) = ( + and_boolM + (return (((csr = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))) + (and_boolM + (return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + (read_reg mstatus_ref \ (\ (w__0 :: Mstatus) . + return (((((get_Mstatus_TVM w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \ (\ (w__2 :: + bool) . + return ((\ w__2))))" + + +(*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*) + +definition check_CSR :: "(12)Word.word \ Privilege \ bool \((register_value),(bool),(exception))monad " where + " check_CSR (csr :: csreg) (p :: Privilege) (isWrite :: bool) = ( + and_boolM (return ((is_CSR_defined csr p))) + (and_boolM + (return ((check_CSR_access ((csrAccess csr :: 2 Word.word)) ((csrPriv csr :: 2 Word.word)) p + isWrite))) ((check_TVM_SATP csr p))))" + + +(*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*) + +definition exception_delegatee :: " ExceptionType \ Privilege \((register_value),(Privilege),(exception))monad " where + " exception_delegatee (e :: ExceptionType) (p :: Privilege) = ( + (let idx = (num_of_ExceptionType e) in + read_reg medeleg_ref \ (\ (w__0 :: Medeleg) . + (let super = (access_vec_dec ((get_Medeleg w__0 :: 64 Word.word)) idx) in + read_reg sedeleg_ref \ (\ (w__1 :: Sedeleg) . + (let user = (access_vec_dec ((get_Sedeleg w__1 :: 64 Word.word)) idx) in + and_boolM + (read_reg misa_ref \ (\ (w__2 :: Misa) . + return (((((get_Misa_S w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (return ((bit_to_bool super))) \ (\ (w__3 :: bool) . + (let deleg = (if w__3 then Supervisor else Machine) in + return (if ((zopz0zI_u ((privLevel_to_bits deleg :: 2 Word.word)) + ((privLevel_to_bits p :: 2 Word.word)))) then + p + else deleg)))))))))" + + +(*val findPendingInterrupt : mword ty64 -> maybe InterruptType*) + +definition findPendingInterrupt :: "(64)Word.word \(InterruptType)option " where + " findPendingInterrupt ip = ( + (let ip = (Mk_Minterrupts ip) in + if (((((get_Minterrupts_MEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + Some I_M_External + else if (((((get_Minterrupts_MSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_M_Software + else if (((((get_Minterrupts_MTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_M_Timer + else if (((((get_Minterrupts_SEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_External + else if (((((get_Minterrupts_SSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_Software + else if (((((get_Minterrupts_STI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_Timer + else if (((((get_Minterrupts_UEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_External + else if (((((get_Minterrupts_USI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_Software + else if (((((get_Minterrupts_UTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_Timer + else None))" + + +(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) + +definition curInterrupt :: " Minterrupts \ Minterrupts \ Minterrupts \((register_value),((InterruptType*Privilege)option),(exception))monad " where + " curInterrupt (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = ( + (let (en_mip :: xlenbits) = + ((and_vec ((get_Minterrupts pend :: 64 Word.word)) ((get_Minterrupts enbl :: 64 Word.word)) + :: 64 Word.word)) in + if (((en_mip = ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))))) then + return None + else + (let eff_mip = + ((and_vec en_mip ((not_vec ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) + :: 64 Word.word)) in + (let eff_sip = ((and_vec en_mip ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) in + and_boolM + (read_reg mstatus_ref \ (\ (w__0 :: Mstatus) . + return (((((get_Mstatus_MIE w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (return (((eff_mip \ ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) \ (\ (w__1 :: + bool) . + if w__1 then + return ((case ((findPendingInterrupt eff_mip)) of + Some (i) => + (let r = (i, Machine) in + Some r) + | None => None + )) + else + and_boolM + (read_reg mstatus_ref \ (\ (w__2 :: Mstatus) . + return (((((get_Mstatus_SIE w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (and_boolM + (return (((eff_sip \ ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) + (or_boolM + (read_reg cur_privilege_ref \ (\ (w__3 :: Privilege) . + return (((((privLevel_to_bits w__3 :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))) + (read_reg cur_privilege_ref \ (\ (w__4 :: Privilege) . + return (((((privLevel_to_bits w__4 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))))) \ (\ (w__7 :: bool) . + return (if w__7 then + (case ((findPendingInterrupt eff_sip)) of + Some (i) => + (let r = (i, Supervisor) in + Some r) + | None => None + ) + else None)))))))" + + +(*val tval : maybe (mword ty64) -> mword ty64*) + +fun tval :: "((64)Word.word)option \(64)Word.word " where + " tval (Some (e)) = ( e )" +|" tval None = ( (EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))" + + +(*val handle_trap : Privilege -> bool -> mword ty4 -> mword ty64 -> maybe (mword ty64) -> M (mword ty64)*) + +definition handle_trap :: " Privilege \ bool \(4)Word.word \(64)Word.word \(xlenbits)option \((register_value),((64)Word.word),(exception))monad " where + " handle_trap (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info :: + xlenbits option) = ( + (let (_ :: unit) = + (prerr_endline + (((op@) (''handling '') + (((op@) (if intr then (''int#'') else (''exc#'')) + (((op@) ((string_of_vec c)) + (((op@) ('' at priv '') + (((op@) ((privLevel_to_str del_priv)) + (((op@) ('' with tval '') + ((string_of_vec ((tval info :: 64 Word.word))))))))))))))))) in + (case del_priv of + Machine => + ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr :: 1 Word.word)) \ + set_Mcause_Cause mcause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \ + read_reg mstatus_ref) \ (\ (w__0 :: Mstatus) . + ((set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 :: 1 Word.word)) \ + set_Mstatus_MIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \ + read_reg cur_privilege_ref) \ (\ (w__1 :: Privilege) . + ((((set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 :: 2 Word.word)) \ + write_reg mtval_ref ((tval info :: 64 Word.word))) \ + write_reg mepc_ref pc) \ + write_reg cur_privilege_ref del_priv) \ + read_reg mtvec_ref) \ (\ (w__2 :: Mtvec) . + read_reg mcause_ref \ (\ (w__3 :: Mcause) . + (case ((tvec_addr w__2 w__3 :: ( 64 Word.word)option)) of + Some (epc) => return epc + | None => (internal_error (''Invalid mtvec mode'') :: ( 64 Word.word) M) + ))))) + | Supervisor => + ((set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr :: 1 Word.word)) \ + set_Mcause_Cause scause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \ + read_reg mstatus_ref) \ (\ (w__6 :: Mstatus) . + ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 :: 1 Word.word)) \ + set_Mstatus_SIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \ + read_reg cur_privilege_ref) \ (\ (w__7 :: Privilege) . + (case w__7 of + User => return ((bool_to_bits False :: 1 Word.word)) + | Supervisor => return ((bool_to_bits True :: 1 Word.word)) + | Machine => (internal_error (''invalid privilege for s-mode trap'') :: ( 1 Word.word) M) + ) \ (\ (w__9 :: 1 Word.word) . + ((((set_Mstatus_SPP mstatus_ref w__9 \ + write_reg stval_ref ((tval info :: 64 Word.word))) \ + write_reg sepc_ref pc) \ + write_reg cur_privilege_ref del_priv) \ + read_reg stvec_ref) \ (\ (w__10 :: Mtvec) . + read_reg scause_ref \ (\ (w__11 :: Mcause) . + (case ((tvec_addr w__10 w__11 :: ( 64 Word.word)option)) of + Some (epc) => return epc + | None => (internal_error (''Invalid stvec mode'') :: ( 64 Word.word) M) + )))))) + | User => (internal_error (''the N extension is currently unsupported'') :: ( 64 Word.word) M) + )))" + + +(*val handle_exception : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*) + +definition handle_exception :: " Privilege \ ctl_result \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " handle_exception (cur_priv :: Privilege) (ctl :: ctl_result) (pc :: xlenbits) = ( + (case (cur_priv, ctl) of + (_, CTL_TRAP (e)) => + exception_delegatee(sync_exception_trap e) cur_priv \ (\ del_priv . + (let (_ :: unit) = + (prerr_endline + (((op@) (''trapping from '') + (((op@) ((privLevel_to_str cur_priv)) + (((op@) ('' to '') + (((op@) ((privLevel_to_str del_priv)) + (((op@) ('' to handle '') + ((exceptionType_to_str(sync_exception_trap e)))))))))))))) in + (handle_trap del_priv False ((exceptionType_to_bits(sync_exception_trap e) :: 4 Word.word)) pc(sync_exception_excinfo + e) + :: ( 64 Word.word) M))) + | (_, CTL_MRET (_)) => + read_reg cur_privilege_ref \ (\ prev_priv . + read_reg mstatus_ref \ (\ (w__1 :: Mstatus) . + ((set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 :: 1 Word.word)) \ + set_Mstatus_MPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \ + read_reg mstatus_ref) \ (\ (w__2 :: Mstatus) . + ((write_reg cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word)))) \ + set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User :: 2 Word.word))) \ + read_reg cur_privilege_ref) \ (\ (w__3 :: Privilege) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''ret-ing from '') + (((op@) ((privLevel_to_str prev_priv)) + (((op@) ('' to '') ((privLevel_to_str w__3))))))))) in + (read_reg mepc_ref :: ( 64 Word.word) M)))))) + | (_, CTL_SRET (_)) => + read_reg cur_privilege_ref \ (\ prev_priv . + read_reg mstatus_ref \ (\ (w__5 :: Mstatus) . + ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 :: 1 Word.word)) \ + set_Mstatus_SPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \ + read_reg mstatus_ref) \ (\ (w__6 :: Mstatus) . + ((write_reg + cur_privilege_ref + (if (((((get_Mstatus_SPP w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Supervisor + else User) \ + set_Mstatus_SPP mstatus_ref ((bool_to_bits False :: 1 Word.word))) \ + read_reg cur_privilege_ref) \ (\ (w__7 :: Privilege) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''ret-ing from '') + (((op@) ((privLevel_to_str prev_priv)) + (((op@) ('' to '') ((privLevel_to_str w__7))))))))) in + (read_reg sepc_ref :: ( 64 Word.word) M)))))) + ))" + + +(*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*) + +definition handle_mem_exception :: "(64)Word.word \ ExceptionType \((register_value),(unit),(exception))monad " where + " handle_mem_exception (addr :: xlenbits) (e :: ExceptionType) = ( + (let (t :: sync_exception) = ((| sync_exception_trap = e, sync_exception_excinfo = (Some addr) |)) in + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val handle_decode_exception : mword ty64 -> M unit*) + +definition handle_decode_exception :: "(64)Word.word \((register_value),(unit),(exception))monad " where + " handle_decode_exception instbits = ( + (let (t :: sync_exception) = + ((| sync_exception_trap = E_Illegal_Instr, + sync_exception_excinfo = (Some instbits) |)) in + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val handle_interrupt : InterruptType -> Privilege -> M unit*) + +definition handle_interrupt :: " InterruptType \ Privilege \((register_value),(unit),(exception))monad " where + " handle_interrupt (i :: InterruptType) (del_priv :: Privilege) = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (handle_trap del_priv True ((interruptType_to_bits i :: 4 Word.word)) w__0 None + :: ( 64 Word.word) M) \ (\ (w__1 :: xlenbits) . + write_reg nextPC_ref w__1)))" + + +(*val handle_illegal : unit -> M unit*) + +definition handle_illegal :: " unit \((register_value),(unit),(exception))monad " where + " handle_illegal _ = ( + (let (t :: sync_exception) = + ((| sync_exception_trap = E_Illegal_Instr, + sync_exception_excinfo = None |)) in + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val init_sys : unit -> M unit*) + +definition init_sys :: " unit \((register_value),(unit),(exception))monad " where + " init_sys _ = ( + (((((write_reg cur_privilege_ref Machine \ + set_Misa_MXL misa_ref ((arch_to_bits RV64 :: 2 Word.word))) \ + set_Misa_C misa_ref ((bool_to_bits True :: 1 Word.word))) \ + set_Misa_U misa_ref ((bool_to_bits True :: 1 Word.word))) \ + set_Misa_S misa_ref ((bool_to_bits True :: 1 Word.word))) \ + read_reg misa_ref) \ (\ (w__0 :: Misa) . + (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 :: 2 Word.word)) \ + read_reg misa_ref) \ (\ (w__1 :: Misa) . + (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 :: 2 Word.word)) \ + set_Mstatus_SD mstatus_ref ((bool_to_bits False :: 1 Word.word))) \ + write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))" + + +(*val tick_clock : unit -> M unit*) + +definition tick_clock :: " unit \((register_value),(unit),(exception))monad " where + " tick_clock _ = ( + (read_reg mcycle_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word))))" + + +definition PAGESIZE_BITS :: " int " where + " PAGESIZE_BITS = ( (( 12 :: int)::ii))" + + +(*val _get_PTE_Bits : PTE_Bits -> mword ty8*) + +fun get_PTE_Bits :: " PTE_Bits \(8)Word.word " where + " get_PTE_Bits (Mk_PTE_Bits (v)) = ( v )" + + +(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) + +definition set_PTE_Bits :: "((regstate),(register_value),(PTE_Bits))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_PTE_Bits v) in + write_reg r_ref r)))" + + +fun get_PTE_Bits_D :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_D (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_D :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_D r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_D :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_D (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_A :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_A (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_A :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_A r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_A :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_A (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_G :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_G (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_G :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_G r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_G :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_G (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_U :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_U (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_U :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_U r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_U :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_U (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_X :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_X (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_X :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_X r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_X :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_X (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_W :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_W (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_W :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_W r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_W :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_W (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_R :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_R (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_R :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_R r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_R :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_R (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_V :: " PTE_Bits \(1)Word.word " where + " get_PTE_Bits_V (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_V :: "((regstate),(register_value),(PTE_Bits))register_ref \(1)Word.word \((register_value),(unit),(exception))monad " where + " set_PTE_Bits_V r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_V :: " PTE_Bits \(1)Word.word \ PTE_Bits " where + " update_PTE_Bits_V (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 8 Word.word)))" + + +(*val isPTEPtr : mword ty8 -> bool*) + +definition isPTEPtr :: "(8)Word.word \ bool " where + " isPTEPtr p = ( + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ (((((get_PTE_Bits_X a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))" + + +(*val isInvalidPTE : mword ty8 -> bool*) + +definition isInvalidPTE :: "(8)Word.word \ bool " where + " isInvalidPTE p = ( + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_V a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ (((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))" + + +(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*) + +fun checkPTEPermission :: " AccessType \ Privilege \ bool \ bool \ PTE_Bits \((register_value),(bool),(exception))monad " where + " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ mxr))))))))))" +|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ mxr)))))))))))))" +|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ do_sum))) \ ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ mxr))))))))))" +|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ do_sum))) \ (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ do_sum))) \ ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \ mxr)))))))))))))" +|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \ (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( internal_error (''m-mode mem perm check''))" + + +(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*) + +definition update_PTE_Bits :: " PTE_Bits \ AccessType \(PTE_Bits)option " where + " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = ( + (let update_d = + (((((((a = Write))) \ (((a = ReadWrite)))))) \ (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in + (let update_a = (((get_PTE_Bits_A p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))) in + if (((update_d \ update_a))) then + (let np = (update_PTE_Bits_A p ((bool_to_bits True :: 1 Word.word))) in + (let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits True :: 1 Word.word)) else np) in + Some np)) + else None)))" + + +(*val PTW_Error_of_num : integer -> PTW_Error*) + +definition PTW_Error_of_num :: " int \ PTW_Error " where + " PTW_Error_of_num arg0 = ( + (let l__0 = arg0 in + if (((l__0 = (( 0 :: int)::ii)))) then PTW_Access + else if (((l__0 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE + else if (((l__0 = (( 2 :: int)::ii)))) then PTW_No_Permission + else if (((l__0 = (( 3 :: int)::ii)))) then PTW_Misaligned + else PTW_PTE_Update))" + + +(*val num_of_PTW_Error : PTW_Error -> integer*) + +fun num_of_PTW_Error :: " PTW_Error \ int " where + " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))" +|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))" +|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))" +|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))" +|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))" + + +(*val translationException : AccessType -> PTW_Error -> ExceptionType*) + +fun translationException :: " AccessType \ PTW_Error \ ExceptionType " where + " translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )" +|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )" +|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )" +|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )" +|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )" +|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )" + + +definition SV39_LEVEL_BITS :: " int " where + " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))" + + +definition SV39_LEVELS :: " int " where + " SV39_LEVELS = ( (( 3 :: int)::ii))" + + +definition PTE39_LOG_SIZE :: " int " where + " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))" + + +definition PTE39_SIZE :: " int " where + " PTE39_SIZE = ( (( 8 :: int)::ii))" + + +(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*) + +fun get_SV39_Vaddr :: " SV39_Vaddr \(39)Word.word " where + " get_SV39_Vaddr (Mk_SV39_Vaddr (v)) = ( v )" + + +(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) + +definition set_SV39_Vaddr :: "((regstate),(register_value),(SV39_Vaddr))register_ref \(39)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_SV39_Vaddr v) in + write_reg r_ref r)))" + + +(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*) + +fun get_SV39_Vaddr_VPNi :: " SV39_Vaddr \(27)Word.word " where + " get_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))" + + +(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*) + +definition set_SV39_Vaddr_VPNi :: "((regstate),(register_value),(SV39_Vaddr))register_ref \(27)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr_VPNi r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_Vaddr) . + (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 38 :: int)::ii) (( 12 :: int)::ii) v :: 39 Word.word)) in + write_reg r_ref (Mk_SV39_Vaddr r)))))" + + +(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*) + +fun update_SV39_Vaddr_VPNi :: " SV39_Vaddr \(27)Word.word \ SV39_Vaddr " where + " update_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) x = ( + Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) x :: 39 Word.word)))" + + +(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*) + +fun get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \(12)Word.word " where + " get_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" + + +(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*) + +definition set_SV39_Vaddr_PgOfs :: "((regstate),(register_value),(SV39_Vaddr))register_ref \(12)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr_PgOfs r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_Vaddr) . + (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 39 Word.word)) in + write_reg r_ref (Mk_SV39_Vaddr r)))))" + + +(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*) + +fun update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \(12)Word.word \ SV39_Vaddr " where + " update_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) x = ( + Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 39 Word.word)))" + + +(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*) + +(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*) + +(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*) + +(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*) + +fun get_SV39_Paddr :: " SV39_Paddr \(56)Word.word " where + " get_SV39_Paddr (Mk_SV39_Paddr (v)) = ( v )" + + +(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) + +definition set_SV39_Paddr :: "((regstate),(register_value),(SV39_Paddr))register_ref \(56)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Paddr r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_SV39_Paddr v) in + write_reg r_ref r)))" + + +(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*) + +fun get_SV39_Paddr_PPNi :: " SV39_Paddr \(44)Word.word " where + " get_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))" + + +(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*) + +definition set_SV39_Paddr_PPNi :: "((regstate),(register_value),(SV39_Paddr))register_ref \(44)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Paddr_PPNi r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_Paddr) . + (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 55 :: int)::ii) (( 12 :: int)::ii) v :: 56 Word.word)) in + write_reg r_ref (Mk_SV39_Paddr r)))))" + + +(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*) + +fun update_SV39_Paddr_PPNi :: " SV39_Paddr \(44)Word.word \ SV39_Paddr " where + " update_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) x = ( + Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) x :: 56 Word.word)))" + + +(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*) + +(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*) + +(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*) + +fun get_SV39_Paddr_PgOfs :: " SV39_Paddr \(12)Word.word " where + " get_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" + + +definition set_SV39_Paddr_PgOfs :: "((regstate),(register_value),(SV39_Paddr))register_ref \(12)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_Paddr_PgOfs r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_Paddr) . + (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 56 Word.word)) in + write_reg r_ref (Mk_SV39_Paddr r)))))" + + +fun update_SV39_Paddr_PgOfs :: " SV39_Paddr \(12)Word.word \ SV39_Paddr " where + " update_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) x = ( + Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 56 Word.word)))" + + +fun get_SV39_PTE :: " SV39_PTE \(64)Word.word " where + " get_SV39_PTE (Mk_SV39_PTE (v)) = ( v )" + + +definition set_SV39_PTE :: "((regstate),(register_value),(SV39_PTE))register_ref \(64)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_PTE r_ref v = ( + reg_deref r_ref \ (\ r . + (let r = (Mk_SV39_PTE v) in + write_reg r_ref r)))" + + +fun get_SV39_PTE_PPNi :: " SV39_PTE \(44)Word.word " where + " get_SV39_PTE_PPNi (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))" + + +definition set_SV39_PTE_PPNi :: "((regstate),(register_value),(SV39_PTE))register_ref \(44)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_PTE_PPNi r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 53 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +fun update_SV39_PTE_PPNi :: " SV39_PTE \(44)Word.word \ SV39_PTE " where + " update_SV39_PTE_PPNi (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*) + +fun get_SV39_PTE_RSW :: " SV39_PTE \(2)Word.word " where + " get_SV39_PTE_RSW (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" + + +(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*) + +definition set_SV39_PTE_RSW :: "((regstate),(register_value),(SV39_PTE))register_ref \(2)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_PTE_RSW r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*) + +fun update_SV39_PTE_RSW :: " SV39_PTE \(2)Word.word \ SV39_PTE " where + " update_SV39_PTE_RSW (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*) + +fun get_SV39_PTE_BITS :: " SV39_PTE \(8)Word.word " where + " get_SV39_PTE_BITS (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*) + +definition set_SV39_PTE_BITS :: "((regstate),(register_value),(SV39_PTE))register_ref \(8)Word.word \((register_value),(unit),(exception))monad " where + " set_SV39_PTE_BITS r_ref v = ( + reg_deref r_ref \ (\ (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*) + +fun update_SV39_PTE_BITS :: " SV39_PTE \(8)Word.word \ SV39_PTE " where + " update_SV39_PTE_BITS (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val curAsid64 : unit -> M (mword ty16)*) + +definition curAsid64 :: " unit \((register_value),((16)Word.word),(exception))monad " where + " curAsid64 _ = ( + (read_reg satp_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let satp64 = (Mk_Satp64 w__0) in + return ((get_Satp64_Asid satp64 :: 16 Word.word)))))" + + +(*val curPTB39 : unit -> M (mword ty56)*) + +definition curPTB39 :: " unit \((register_value),((56)Word.word),(exception))monad " where + " curPTB39 _ = ( + (read_reg satp_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let satp64 = (Mk_Satp64 w__0) in + return ((EXTZ (( 56 :: int)::ii) + ((shiftl ((get_Satp64_PPN satp64 :: 44 Word.word)) PAGESIZE_BITS :: 44 Word.word)) + :: 56 Word.word)))))" + + +(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*) + +function (sequential,domintros) walk39 :: "(39)Word.word \ AccessType \ Privilege \ bool \ bool \(56)Word.word \ int \ bool \((register_value),(PTW_Result),(exception))monad " where + " walk39 vaddr ac priv mxr do_sum ptb level global1 = ( + (let va = (Mk_SV39_Vaddr vaddr) in + (let (pt_ofs :: paddr39) = + ((shiftl + ((EXTZ (( 56 :: int)::ii) + ((subrange_vec_dec + ((shiftr ((get_SV39_Vaddr_VPNi va :: 27 Word.word)) + ((level * SV39_LEVEL_BITS)) + :: 27 Word.word)) ((SV39_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 9 Word.word)) + :: 56 Word.word)) PTE39_LOG_SIZE + :: 56 Word.word)) in + (let pte_addr = ((add_vec ptb pt_ofs :: 56 Word.word)) in + (checked_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) + :: ( ( 64 Word.word)MemoryOpResult) M) \ (\ (w__0 :: ( 64 Word.word) MemoryOpResult) . + (case w__0 of + MemException (_) => return (PTW_Failure PTW_Access) + | MemValue (v) => + (let pte = (Mk_SV39_PTE v) in + (let pbits = ((get_SV39_PTE_BITS pte :: 8 Word.word)) in + (let pattr = (Mk_PTE_Bits pbits) in + (let is_global = + (global1 \ (((((get_PTE_Bits_G pattr :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) in + if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE) + else if ((isPTEPtr pbits)) then + if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE) + else + walk39 vaddr ac priv mxr do_sum + ((EXTZ (( 56 :: int)::ii) + ((shiftl ((get_SV39_PTE_PPNi pte :: 44 Word.word)) PAGESIZE_BITS :: 44 Word.word)) + :: 56 Word.word)) ((level - (( 1 :: int)::ii))) is_global + else + checkPTEPermission ac priv mxr do_sum pattr \ (\ (w__3 :: bool) . + return (if ((\ w__3)) then PTW_Failure PTW_No_Permission + else if ((level > (( 0 :: int)::ii))) then + (let mask1 = + ((sub_vec_int + ((shiftl + ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 44 Word.word)) + :: 44 Word.word)) + :: 44 Word.word)) ((level * SV39_LEVEL_BITS)) + :: 44 Word.word)) (( 1 :: int)::ii) + :: 44 Word.word)) in + if (((((and_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) mask1 :: 44 Word.word)) \ ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 44 Word.word))))) then + PTW_Failure PTW_Misaligned + else + (let ppn = + ((or_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((and_vec + ((EXTZ (( 44 :: int)::ii) ((get_SV39_Vaddr_VPNi va :: 27 Word.word)) :: 44 Word.word)) + mask1 + :: 44 Word.word)) + :: 44 Word.word)) in + PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va :: 12 Word.word)) + :: 56 Word.word),pte,pte_addr,level,is_global))) + else + PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((get_SV39_Vaddr_PgOfs va :: 12 Word.word)) + :: 56 Word.word),pte,pte_addr,level,is_global))))))) + ))))))" +by pat_completeness auto + + +(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*) + +definition make_TLB39_Entry :: "(16)Word.word \ bool \(39)Word.word \(56)Word.word \ SV39_PTE \ int \(56)Word.word \((register_value),(TLB39_Entry),(exception))monad " where + " make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr = ( + (let (shift :: ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in + (let (vAddrMask :: vaddr39) = + ((sub_vec_int + ((shiftl + ((xor_vec vAddr + ((xor_vec vAddr ((EXTZ (( 39 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 39 Word.word)) + :: 39 Word.word)) + :: 39 Word.word)) shift + :: 39 Word.word)) (( 1 :: int)::ii) + :: 39 Word.word)) in + (let (vMatchMask :: vaddr39) = ((not_vec vAddrMask :: 39 Word.word)) in + (read_reg mcycle_ref :: ( 64 Word.word) M) \ (\ (w__0 :: xlenbits) . + return ((| TLB39_Entry_asid = asid, + TLB39_Entry_global = global1, + TLB39_Entry_vAddr = ((and_vec vAddr vMatchMask :: 39 Word.word)), + TLB39_Entry_pAddr = + ((shiftl ((shiftr pAddr shift :: 56 Word.word)) shift :: 56 Word.word)), + TLB39_Entry_vMatchMask = vMatchMask, + TLB39_Entry_vAddrMask = vAddrMask, + TLB39_Entry_pte = pte, + TLB39_Entry_pteAddr = pteAddr, + TLB39_Entry_age = w__0 |)))))))" + + +definition TLBEntries :: " int " where + " TLBEntries = ( (( 32 :: int)::ii))" + + +(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*) + +definition lookupTLB39 :: "(16)Word.word \(39)Word.word \((register_value),((int*TLB39_Entry)option),(exception))monad " where + " lookupTLB39 asid vaddr = ( + read_reg tlb39_ref \ (\ (w__0 :: TLB39_Entry option) . + return ((case w__0 of + None => None + | Some (e) => + if (((((((TLB39_Entry_global e) \ ((((TLB39_Entry_asid e) = asid)))))) \ ((((TLB39_Entry_vAddr e) = ((and_vec(TLB39_Entry_vMatchMask e) vaddr :: 39 Word.word)))))))) + then + Some ((( 0 :: int)::ii), e) + else None + ))))" + + +(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*) + +definition addToTLB39 :: "(16)Word.word \(39)Word.word \(56)Word.word \ SV39_PTE \(56)Word.word \ int \ bool \((register_value),(unit),(exception))monad " where + " addToTLB39 asid vAddr pAddr pte pteAddr level global1 = ( + make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr \ (\ ent . + write_reg tlb39_ref (Some ent)))" + + +(*val writeTLB39 : ii -> TLB39_Entry -> M unit*) + +definition writeTLB39 :: " int \ TLB39_Entry \((register_value),(unit),(exception))monad " where + " writeTLB39 (idx :: ii) (ent :: TLB39_Entry) = ( write_reg tlb39_ref (Some ent))" + + +(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*) + +definition flushTLB :: "((16)Word.word)option \((39)Word.word)option \((register_value),(unit),(exception))monad " where + " flushTLB asid addr = ( + read_reg tlb39_ref \ (\ (w__0 :: TLB39_Entry option) . + (let (ent :: TLB39_Entry option) = + ((case (w__0, asid, addr) of + (None, _, _) => None + | (Some (e), None, None) => None + | (Some (e), None, Some (a)) => + if ((((TLB39_Entry_vAddr e) = ((and_vec(TLB39_Entry_vMatchMask e) a :: 39 Word.word))))) then + None + else Some e + | (Some (e), Some (i), None) => + if (((((((TLB39_Entry_asid e) = i))) \ ((\(TLB39_Entry_global e)))))) then None + else Some e + | (Some (e), Some (i), Some (a)) => + if (((((((TLB39_Entry_asid e) = i))) \ (((((((TLB39_Entry_vAddr e) = ((and_vec a(TLB39_Entry_vMatchMask e) :: 39 Word.word))))) \ ((\(TLB39_Entry_global e))))))))) then + None + else Some e + )) in + write_reg tlb39_ref ent)))" + + +definition enable_dirty_update :: " bool " where + " enable_dirty_update = ( False )" + + +(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*) + +definition translate39 :: "(39)Word.word \ AccessType \ Privilege \ bool \ bool \ int \((register_value),(TR39_Result),(exception))monad " where + " translate39 vAddr ac priv mxr do_sum level = ( + (curAsid64 () :: ( 16 Word.word) M) \ (\ asid . + lookupTLB39 asid vAddr \ (\ (w__0 :: ((ii * TLB39_Entry))option) . + (case w__0 of + Some (idx,ent) => + (let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS(TLB39_Entry_pte ent) :: 8 Word.word))) in + checkPTEPermission ac priv mxr do_sum pteBits \ (\ (w__1 :: bool) . + if ((\ w__1)) then return (TR39_Failure PTW_No_Permission) + else + (case ((update_PTE_Bits pteBits ac)) of + None => + return (TR39_Address ((or_vec(TLB39_Entry_pAddr ent) + ((EXTZ (( 56 :: int)::ii) + ((and_vec vAddr(TLB39_Entry_vAddrMask ent) :: 39 Word.word)) + :: 56 Word.word)) + :: 56 Word.word))) + | Some (pbits) => + if ((\ enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + else + (let (n_ent :: TLB39_Entry) = ent in + (let n_ent = + ((n_ent (| + TLB39_Entry_pte := + ((update_SV39_PTE_BITS(TLB39_Entry_pte ent) ((get_PTE_Bits pbits :: 8 Word.word))))|))) in + (writeTLB39 idx n_ent \ + checked_mem_write ((EXTZ (( 64 :: int)::ii)(TLB39_Entry_pteAddr ent) :: 64 Word.word)) (( 8 :: int)::ii) + ((get_SV39_PTE(TLB39_Entry_pte ent) :: 64 Word.word))) \ (\ (w__2 :: unit + MemoryOpResult) . + (case w__2 of + MemValue (_) => return () + | MemException (e) => internal_error (''invalid physical address in TLB'') + ) \ + return (TR39_Address ((or_vec(TLB39_Entry_pAddr ent) + ((EXTZ (( 56 :: int)::ii) + ((and_vec vAddr(TLB39_Entry_vAddrMask ent) :: 39 Word.word)) + :: 56 Word.word)) + :: 56 Word.word)))))) + ))) + | None => + (curPTB39 () :: ( 56 Word.word) M) \ (\ (w__6 :: 56 Word.word) . + walk39 vAddr ac priv mxr do_sum w__6 level False \ (\ (w__7 :: PTW_Result) . + (case w__7 of + PTW_Failure (f) => return (TR39_Failure f) + | PTW_Success (pAddr,pte,pteAddr,level,global1) => + (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word))) ac)) of + None => + addToTLB39 asid vAddr pAddr pte pteAddr level global1 \ return (TR39_Address pAddr) + | Some (pbits) => + if ((\ enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + else + (let (w_pte :: SV39_PTE) = + (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits :: 8 Word.word))) in + checked_mem_write ((EXTZ (( 64 :: int)::ii) pteAddr :: 64 Word.word)) (( 8 :: int)::ii) + ((get_SV39_PTE w_pte :: 64 Word.word)) \ (\ (w__8 :: unit MemoryOpResult) . + (case w__8 of + MemValue (_) => + addToTLB39 asid vAddr pAddr w_pte pteAddr level global1 \ + return (TR39_Address pAddr) + | MemException (e) => return (TR39_Failure PTW_Access) + ))) + ) + ))) + ))))" + + +(*val translationMode : Privilege -> M SATPMode*) + +definition translationMode :: " Privilege \((register_value),(SATPMode),(exception))monad " where + " translationMode priv = ( + if (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) + then + return Sbare + else + read_reg mstatus_ref \ (\ (w__0 :: Mstatus) . + (let arch = (architecture ((get_Mstatus_SXL w__0 :: 2 Word.word))) in + (case arch of + Some (RV64) => + (read_reg satp_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let (mbits :: satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) :: 4 Word.word)) in + (case ((satpMode_of_bits RV64 mbits)) of + Some (m) => return m + | None => internal_error (''invalid RV64 translation mode in satp'') + ))) + | _ => internal_error (''unsupported address translation arch'') + ))))" + + +(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*) + +definition translateAddr :: "(64)Word.word \ AccessType \ ReadType \((register_value),(TR_Result),(exception))monad " where + " translateAddr vAddr ac rt = ( + (case rt of + Instruction => read_reg cur_privilege_ref + | Data => + read_reg mstatus_ref \ (\ (w__1 :: Mstatus) . + if (((((get_Mstatus_MPRV w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + read_reg mstatus_ref \ (\ (w__2 :: Mstatus) . + return ((privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word))))) + else read_reg cur_privilege_ref) + ) \ (\ (effPriv :: Privilege) . + read_reg mstatus_ref \ (\ (w__5 :: Mstatus) . + (let (mxr :: bool) = + (((get_Mstatus_MXR w__5 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in + read_reg mstatus_ref \ (\ (w__6 :: Mstatus) . + (let (do_sum :: bool) = + (((get_Mstatus_SUM w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in + translationMode effPriv \ (\ (mode :: SATPMode) . + (case mode of + Sbare => return (TR_Address vAddr) + | SV39 => + translate39 + ((subrange_vec_dec vAddr (( 38 :: int):: ii) (( 0 :: int):: ii) :: 39 Word.word)) + ac effPriv mxr do_sum ((SV39_LEVELS - (( 1 :: int):: ii))) \ + (\ (w__7 :: TR39_Result) . + return + ((case w__7 of + TR39_Address (pa) => TR_Address + ((EXTZ (( 64 :: int):: ii) pa :: 64 Word.word)) + | TR39_Failure (f) => TR_Failure ((translationException ac f)) + ))) + ))))))))" + + +(*val decode : mword ty32 -> maybe ast*) + +(*val decodeCompressed : mword ty16 -> maybe ast*) + +(*val execute : ast -> M unit*) + +(*val print_insn : ast -> string*) + +(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*) + +fun extend_value :: " bool \(('int8_times_n::len)Word.word)MemoryOpResult \((64)Word.word)MemoryOpResult " where + " extend_value is_unsigned (MemValue (v)) = ( + MemValue (if is_unsigned then (EXTZ (( 64 :: int)::ii) v :: 64 Word.word) + else (EXTS (( 64 :: int)::ii) v :: 64 Word.word)))" +|" extend_value is_unsigned (MemException (e)) = ( MemException e )" + + +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*) + +definition process_load :: "(5)Word.word \(64)Word.word \(('int8_times_n::len)Word.word)MemoryOpResult \ bool \((register_value),(unit),(exception))monad " where + " process_load rd addr value1 is_unsigned = ( + (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of + MemValue (result) => wX ((regbits_to_regno rd)) result + | MemException (e) => handle_mem_exception addr e + ))" + + +(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*) + +(*val readCSR : mword ty12 -> M (mword ty64)*) + +definition readCSR :: "(12)Word.word \((register_value),((64)Word.word),(exception))monad " where + " readCSR csr = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mvendorid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg marchid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mimpid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (read_reg mhartid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \ (\ (w__4 :: Mstatus) . return ((get_Mstatus w__4 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg misa_ref \ (\ (w__5 :: Misa) . return ((get_Misa w__5 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg medeleg_ref \ (\ (w__6 :: Medeleg) . return ((get_Medeleg w__6 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg mideleg_ref \ (\ (w__7 :: Minterrupts) . + return ((get_Minterrupts w__7 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \ (\ (w__8 :: Minterrupts) . return ((get_Minterrupts w__8 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg mtvec_ref \ (\ (w__9 :: Mtvec) . return ((get_Mtvec w__9 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mepc_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg mcause_ref \ (\ (w__12 :: Mcause) . return ((get_Mcause w__12 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mtval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \ (\ (w__14 :: Minterrupts) . + return ((get_Minterrupts w__14 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \ (\ (w__15 :: Mstatus) . return ((get_Mstatus w__15 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg sedeleg_ref \ (\ (w__16 :: Sedeleg) . return ((get_Sedeleg w__16 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg sideleg_ref \ (\ (w__17 :: Sinterrupts) . + return ((get_Sinterrupts w__17 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \ (\ (w__18 :: Minterrupts) . + read_reg mideleg_ref \ (\ (w__19 :: Minterrupts) . + return ((get_Sinterrupts ((lower_mie w__18 w__19)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg stvec_ref \ (\ (w__20 :: Mtvec) . return ((get_Mtvec w__20 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg sscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg sepc_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg scause_ref \ (\ (w__23 :: Mcause) . return ((get_Mcause w__23 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg stval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \ (\ (w__25 :: Minterrupts) . + read_reg mideleg_ref \ (\ (w__26 :: Minterrupts) . + return ((get_Sinterrupts ((lower_mip w__25 w__26)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg satp_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mcycle_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mtime_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg minstret_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg tselect_ref :: ( 64 Word.word) M) \ (\ (w__31 :: 64 Word.word) . + return ((not_vec w__31 :: 64 Word.word))) + else + (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word))))" + + +(*val writeCSR : mword ty12 -> mword ty64 -> M unit*) + +definition writeCSR :: "(12)Word.word \(64)Word.word \((register_value),(unit),(exception))monad " where + " writeCSR (csr :: csreg) (value1 :: xlenbits) = ( + (let b__0 = csr in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \ (\ (w__0 :: Mstatus) . + (write_reg mstatus_ref ((legalize_mstatus w__0 value1)) \ + read_reg mstatus_ref) \ (\ (w__1 :: Mstatus) . + return (Some ((get_Mstatus w__1 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg medeleg_ref \ (\ (w__2 :: Medeleg) . + (write_reg medeleg_ref ((legalize_medeleg w__2 value1)) \ + read_reg medeleg_ref) \ (\ (w__3 :: Medeleg) . + return (Some ((get_Medeleg w__3 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg mideleg_ref \ (\ (w__4 :: Minterrupts) . + (write_reg mideleg_ref ((legalize_mideleg w__4 value1)) \ + read_reg mideleg_ref) \ (\ (w__5 :: Minterrupts) . + return (Some ((get_Minterrupts w__5 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \ (\ (w__6 :: Minterrupts) . + (write_reg mie_ref ((legalize_mie w__6 value1)) \ + read_reg mie_ref) \ (\ (w__7 :: Minterrupts) . + return (Some ((get_Minterrupts w__7 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg mtvec_ref \ (\ (w__8 :: Mtvec) . + (write_reg mtvec_ref ((legalize_tvec w__8 value1)) \ + read_reg mtvec_ref) \ (\ (w__9 :: Mtvec) . return (Some ((get_Mtvec w__9 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg mscratch_ref value1 \ + (read_reg mscratch_ref :: ( 64 Word.word) M)) \ (\ (w__10 :: 64 Word.word) . return (Some w__10)) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (legalize_xepc value1 :: ( 64 Word.word) M) \ (\ (w__11 :: xlenbits) . + (write_reg mepc_ref w__11 \ + (read_reg mepc_ref :: ( 64 Word.word) M)) \ (\ (w__12 :: 64 Word.word) . return (Some w__12))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (set_Mcause mcause_ref value1 \ + read_reg mcause_ref) \ (\ (w__13 :: Mcause) . + return (Some ((get_Mcause w__13 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (write_reg mtval_ref value1 \ + (read_reg mtval_ref :: ( 64 Word.word) M)) \ (\ (w__14 :: 64 Word.word) . return (Some w__14)) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \ (\ (w__15 :: Minterrupts) . + (write_reg mip_ref ((legalize_mip w__15 value1)) \ + read_reg mip_ref) \ (\ (w__16 :: Minterrupts) . + return (Some ((get_Minterrupts w__16 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \ (\ (w__17 :: Mstatus) . + (write_reg mstatus_ref ((legalize_sstatus w__17 value1)) \ + read_reg mstatus_ref) \ (\ (w__18 :: Mstatus) . + return (Some ((get_Mstatus w__18 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg sedeleg_ref \ (\ (w__19 :: Sedeleg) . + (write_reg sedeleg_ref ((legalize_sedeleg w__19 value1)) \ + read_reg sedeleg_ref) \ (\ (w__20 :: Sedeleg) . + return (Some ((get_Sedeleg w__20 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (set_Sinterrupts sideleg_ref value1 \ + read_reg sideleg_ref) \ (\ (w__21 :: Sinterrupts) . + return (Some ((get_Sinterrupts w__21 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \ (\ (w__22 :: Minterrupts) . + read_reg mideleg_ref \ (\ (w__23 :: Minterrupts) . + (write_reg mie_ref ((legalize_sie w__22 w__23 value1)) \ + read_reg mie_ref) \ (\ (w__24 :: Minterrupts) . + return (Some ((get_Minterrupts w__24 :: 64 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg stvec_ref \ (\ (w__25 :: Mtvec) . + (write_reg stvec_ref ((legalize_tvec w__25 value1)) \ + read_reg stvec_ref) \ (\ (w__26 :: Mtvec) . return (Some ((get_Mtvec w__26 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg sscratch_ref value1 \ + (read_reg sscratch_ref :: ( 64 Word.word) M)) \ (\ (w__27 :: 64 Word.word) . return (Some w__27)) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (legalize_xepc value1 :: ( 64 Word.word) M) \ (\ (w__28 :: xlenbits) . + (write_reg sepc_ref w__28 \ + (read_reg sepc_ref :: ( 64 Word.word) M)) \ (\ (w__29 :: 64 Word.word) . return (Some w__29))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (set_Mcause scause_ref value1 \ + read_reg scause_ref) \ (\ (w__30 :: Mcause) . + return (Some ((get_Mcause w__30 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (write_reg stval_ref value1 \ + (read_reg stval_ref :: ( 64 Word.word) M)) \ (\ (w__31 :: 64 Word.word) . return (Some w__31)) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \ (\ (w__32 :: Minterrupts) . + read_reg mideleg_ref \ (\ (w__33 :: Minterrupts) . + (write_reg mip_ref ((legalize_sip w__32 w__33 value1)) \ + read_reg mip_ref) \ (\ (w__34 :: Minterrupts) . + return (Some ((get_Minterrupts w__34 :: 64 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + cur_Architecture () \ (\ (w__35 :: Architecture) . + (read_reg satp_ref :: ( 64 Word.word) M) \ (\ (w__36 :: 64 Word.word) . + (write_reg satp_ref ((legalize_satp w__35 w__36 value1 :: 64 Word.word)) \ + (read_reg satp_ref :: ( 64 Word.word) M)) \ (\ (w__37 :: 64 Word.word) . return (Some w__37)))) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg tselect_ref value1 \ + (read_reg tselect_ref :: ( 64 Word.word) M)) \ (\ (w__38 :: 64 Word.word) . return (Some w__38)) + else return None) \ (\ (res :: xlenbits option) . + return ((case res of + Some (v) => + prerr_endline + (((op@) (''CSR '') + (((op@) ((csr_name csr)) + (((op@) ('' <- '') + (((op@) ((string_of_vec v)) + (((op@) ('' (input: '') (((op@) ((string_of_vec value1)) ('')''))))))))))))) + | None => print_bits (''unhandled write to CSR '') csr + )))))" + + +definition decode :: "(32)Word.word \(ast)option " where + " decode v__0 = ( + if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (UTYPE (imm,rd,RISCV_LUI)))) + else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (UTYPE (imm,rd,RISCV_AUIPC)))) + else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((concat_vec + ((cast_unit_vec0 ((access_vec_dec imm (( 8 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm (( 18 :: int)::ii) (( 13 :: int)::ii) :: 6 Word.word)) + ((concat_vec + ((subrange_vec_dec imm (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 20 Word.word)) + :: 21 Word.word),rd)))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RISCV_JALR (imm,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BEQ)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BNE)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BLT)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BGE)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BLTU)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BGEU)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_SLTI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_SLTIU))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_XORI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ORI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ANDI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_ADD))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SUB))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLL))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_XOR))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SRL))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SRA))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_OR))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_AND))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,BYTE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,HALF,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,WORD,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,DOUBLE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,BYTE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,HALF,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,WORD,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,BYTE,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,HALF,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,WORD,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,DOUBLE,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ADDIW (imm,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SLLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SRLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SRAI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_ADDW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SUBW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SLLW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SRLW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SRAW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,False,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,True,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REM (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REM (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MULW (rs2,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIVW (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIVW (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REMW (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REMW (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \ (((((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] + :: 20 Word.word))))))) then + (let (pred :: 4 bits) = ((subrange_vec_dec v__0 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in + (let (succ :: 4 bits) = ((subrange_vec_dec v__0 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in + Some (FENCE (pred,succ)))) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0, + B0,B0,B0,B0,B1,B1,B1,B1] + :: 32 Word.word)))) then + Some (FENCEI () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (ECALL () ) + else if (((v__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (MRET () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (SRET () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (EBREAK () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (WFI () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \ (((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word))))))) + then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + Some (SFENCE_VMA (rs1,rs2)))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \ ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRW))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRS))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRC))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRW))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRS))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRC))))) + else None )" + + +definition decodeCompressed :: "(16)Word.word \(ast)option " where + " decodeCompressed v__418 = ( + if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((nzi1 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) then + Some (NOP () ) + else None)) + else if (((v__418 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + Some (ILLEGAL () ) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (nz54 :: 2 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in + (let (nz96 :: 4 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in + (let (nz2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nz3 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let nzimm = + ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word)) + :: 8 Word.word)) in + if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then None + else Some (C_ADDI4SPN (rd,nzimm)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in + Some (C_LW (uimm,rs1,rd)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in + Some (C_LD (uimm,rs1,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in + Some (C_SW (uimm,rs1,rs2)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in + Some (C_SD (uimm,rs1,rs2))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let nzi = ((concat_vec nzi5 nzi40 :: 6 Word.word)) in + if ((((((nzi = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_ADDI (nzi,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + Some (C_ADDIW ((concat_vec imm5 imm40 :: 6 Word.word),rsd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LI ((concat_vec imm5 imm40 :: 6 Word.word),rd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + (let nzimm = + ((concat_vec nzi9 + ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) in + if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_ADDI16SP nzimm))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm17 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then + None + else Some (C_LUI ((concat_vec imm17 imm1612 :: 6 Word.word),rd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_SRLI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_SRAI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + Some (C_ANDI ((concat_vec i5 i40 :: 6 Word.word),rsd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_SUB (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_XOR (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_OR (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_AND (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_SUBW (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \ ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_ADDW (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i11 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i4 :: 1 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in + (let (i98 :: 2 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in + (let (i10 :: 1 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in + (let (i6 :: 1 bits) = ((subrange_vec_dec v__418 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let (i7 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (i31 :: 3 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_J ((concat_vec i11 + ((concat_vec i10 + ((concat_vec i98 + ((concat_vec i7 + ((concat_vec i6 + ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 9 Word.word)) + :: 10 Word.word)) + :: 11 Word.word))))))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_BEQZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word),rs)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_BNEZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word),rs)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if ((((((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_SLLI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui42 :: 3 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 :: 4 Word.word)) :: 6 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LWSP (uimm,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui43 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 :: 3 Word.word)) :: 6 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LDSP (uimm,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui52 :: 4 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui76 ui52 :: 6 Word.word)) in + Some (C_SWSP (uimm,rs2)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui86 ui53 :: 6 Word.word)) in + Some (C_SDSP (uimm,rs2)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \ (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None + else Some (C_JR rs1)) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \ (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None + else Some (C_JALR rs1)) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_MV (rd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \ (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_ADD (rsd,rs2)))) + else None )" + + +(*val execute_WFI : unit -> M unit*) + +fun execute_WFI :: " unit \((register_value),(unit),(exception))monad " where + " execute_WFI g__110 = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (case w__0 of + Machine => return () + | Supervisor => + read_reg mstatus_ref \ (\ (w__1 :: Mstatus) . + if (((((get_Mstatus_TW w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + handle_illegal () + else return () ) + | User => handle_illegal () + )))" + + +(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*) + +fun execute_UTYPE :: "(20)Word.word \(5)Word.word \ uop \((register_value),(unit),(exception))monad " where + " execute_UTYPE imm rd op1 = ( + (let (off :: xlenbits) = + ((EXTS (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 32 Word.word)) + :: 64 Word.word)) in + (case op1 of + RISCV_LUI => return off + | RISCV_AUIPC => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + return ((add_vec w__0 off :: 64 Word.word))) + ) \ (\ (ret :: xlenbits) . + wX ((regbits_to_regno rd)) ret)))" + + +(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_STORECON :: " bool \ bool \(5)Word.word \(5)Word.word \ word_width \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_STORECON aq rl rs2 rs1 width rd = ( + speculate_conditional_success () \ (\ (w__0 :: bool) . + (let (status :: 1 bits) = + (if w__0 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) status :: 64 Word.word)) \ + (if (((status = (vec_of_bits [B1] :: 1 Word.word)))) then return () + else + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (vaddr :: xlenbits) . + translateAddr vaddr Write Data \ (\ (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \ (\ (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (case width of + WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + aq rl True + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \ (\ (res :: unit MemoryOpResult) . + (case res of + MemValue (_) => return () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))))" + + +(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*) + +fun execute_STORE :: "(12)Word.word \(5)Word.word \(5)Word.word \ word_width \ bool \ bool \((register_value),(unit),(exception))monad " where + " execute_STORE imm rs2 rs1 width aq rl = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + translateAddr vaddr Write Data \ (\ (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False + | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False + | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False + ) \ (\ (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (case width of + BYTE => + mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) aq + rl False + | HALF => + mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) aq + rl False + | WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq + rl False + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False + ) \ (\ (res :: unit MemoryOpResult) . + (case res of + MemValue (_) => return () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))" + + +(*val execute_SRET : unit -> M unit*) + +fun execute_SRET :: " unit \((register_value),(unit),(exception))monad " where + " execute_SRET g__108 = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (case w__0 of + User => handle_illegal () + | Supervisor => + read_reg mstatus_ref \ (\ (w__1 :: Mstatus) . + if (((((get_Mstatus_TSR w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + handle_illegal () + else + read_reg cur_privilege_ref \ (\ (w__2 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (handle_exception w__2 (CTL_SRET () ) w__3 :: ( 64 Word.word) M) \ (\ (w__4 :: xlenbits) . + write_reg nextPC_ref w__4)))) + | Machine => + read_reg cur_privilege_ref \ (\ (w__5 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 Word.word) . + (handle_exception w__5 (CTL_SRET () ) w__6 :: ( 64 Word.word) M) \ (\ (w__7 :: xlenbits) . + write_reg nextPC_ref w__7))) + )))" + + +(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*) + +fun execute_SHIFTW :: "(5)Word.word \(5)Word.word \(5)Word.word \ sop \((register_value),(unit),(exception))monad " where + " execute_SHIFTW shamt rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (result :: 32 bits) = + ((case op1 of + RISCV_SLLI => (shift_bits_left rs1_val shamt :: 32 Word.word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 32 Word.word) + | RISCV_SRAI => (shift_right_arith32 rs1_val shamt :: 32 Word.word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))" + + +(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*) + +fun execute_SHIFTIOP :: "(6)Word.word \(5)Word.word \(5)Word.word \ sop \((register_value),(unit),(exception))monad " where + " execute_SHIFTIOP shamt rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (let (result :: xlenbits) = + ((case op1 of + RISCV_SLLI => (shift_bits_left rs1_val shamt :: 64 Word.word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 64 Word.word) + | RISCV_SRAI => (shift_right_arith64 rs1_val shamt :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result)))" + + +(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*) + +fun execute_SFENCE_VMA :: "(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_SFENCE_VMA rs1 rs2 = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) + then + handle_illegal () + else + read_reg mstatus_ref \ (\ (w__1 :: Mstatus) . + read_reg mstatus_ref \ (\ (w__2 :: Mstatus) . + (let p__104 = + (architecture ((get_Mstatus_SXL w__1 :: 2 Word.word)), (get_Mstatus_TVM w__2 :: 1 Word.word)) in + (case p__104 of + (Some (RV64), v_0) => + if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then handle_illegal () + else + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then return None + else + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + return (Some ((subrange_vec_dec w__3 (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))))) \ (\ (addr :: + vaddr39 option) . + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then return None + else + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + return (Some ((subrange_vec_dec w__4 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))))) \ (\ (asid :: + asid64 option) . + flushTLB asid addr)) + | (g__102, g__103) => internal_error (''unimplemented sfence architecture'') + ))))))" + + +(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*) + +fun execute_RTYPEW :: "(5)Word.word \(5)Word.word \(5)Word.word \ ropw \((register_value),(unit),(exception))monad " where + " execute_RTYPEW rs2 rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (result :: 32 bits) = + ((case op1 of + RISCV_ADDW => (add_vec rs1_val rs2_val :: 32 Word.word) + | RISCV_SUBW => (sub_vec rs1_val rs2_val :: 32 Word.word) + | RISCV_SLLW => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + | RISCV_SRLW => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + | RISCV_SRAW => + (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))))" + + +(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*) + +fun execute_RTYPE :: "(5)Word.word \(5)Word.word \(5)Word.word \ rop \((register_value),(unit),(exception))monad " where + " execute_RTYPE rs2 rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (let (result :: xlenbits) = + ((case op1 of + RISCV_ADD => (add_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SUB => (sub_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SLL => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_SLT => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_SLTU => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_XOR => (xor_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SRL => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_SRA => + (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_OR => (or_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_AND => (and_vec rs1_val rs2_val :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_RISCV_JALR :: "(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_RISCV_JALR imm rs1 rd = ( + (read_reg nextPC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (wX ((regbits_to_regno rd)) w__0 \ + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 Word.word) . + (let (newPC :: xlenbits) = ((add_vec w__1 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + write_reg + nextPC_ref + ((concat_vec ((subrange_vec_dec newPC (( 63 :: int)::ii) (( 1 :: int)::ii) :: 63 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 64 Word.word))))))" + + +(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*) + +fun execute_RISCV_JAL :: "(21)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_RISCV_JAL imm rd = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (pc :: xlenbits) . + (read_reg nextPC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + wX ((regbits_to_regno rd)) w__0 \ + ((let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + write_reg nextPC_ref ((add_vec pc offset :: 64 Word.word)))))))" + + +(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_REMW :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_REMW rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 64 Word.word))))))))))" + + +(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_REM :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_REM rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((to_bits xlen r :: 64 Word.word))))))))" + + +(*val execute_NOP : unit -> unit*) + +fun execute_NOP :: " unit \ unit " where + " execute_NOP g__111 = ( () )" + + +(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_MULW :: "(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_MULW rs2 rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (Word.sint rs1_val) in + (let (rs2_int :: ii) = (Word.sint rs2_val) in + (let result32 = + ((subrange_vec_dec ((to_bits (( 64 :: int)::ii) ((rs1_int * rs2_int)) :: 64 Word.word)) (( 31 :: int)::ii) + (( 0 :: int)::ii) + :: 32 Word.word)) in + (let (result :: xlenbits) = ((EXTS (( 64 :: int)::ii) result32 :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result)))))))))" + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*) + +fun execute_MUL :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \ bool \ bool \((register_value),(unit),(exception))monad " where + " execute_MUL rs2 rs1 rd high signed1 signed2 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (let (rs1_int :: ii) = (if signed1 then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if signed2 then Word.sint rs2_val else Word.uint rs2_val) in + (let result128 = ((to_bits (( 128 :: int)::ii) ((rs1_int * rs2_int)) :: 128 Word.word)) in + (let result = + (if high then (subrange_vec_dec result128 (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word) + else (subrange_vec_dec result128 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result)))))))" + + +(*val execute_MRET : unit -> M unit*) + +fun execute_MRET :: " unit \((register_value),(unit),(exception))monad " where + " execute_MRET g__107 = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) + then + read_reg cur_privilege_ref \ (\ (w__1 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (handle_exception w__1 (CTL_MRET () ) w__2 :: ( 64 Word.word) M) \ (\ (w__3 :: xlenbits) . + write_reg nextPC_ref w__3))) + else handle_illegal () ))" + + +(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_LOADRES :: " bool \ bool \(5)Word.word \ word_width \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_LOADRES aq rl rs1 width rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (vaddr :: xlenbits) . + translateAddr vaddr Read Data \ (\ (w__0 :: TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => + (mem_read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \ (\ (w__1 :: ( 32 Word.word) + MemoryOpResult) . + process_load rd addr w__1 False) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl True :: ( ( 64 Word.word)MemoryOpResult) M) \ (\ (w__2 :: ( 64 Word.word) + MemoryOpResult) . + process_load rd addr w__2 False) + | _ => internal_error (''LOADRES expected WORD or DOUBLE'') + ) + ))))" + + +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*) + +fun execute_LOAD :: "(12)Word.word \(5)Word.word \(5)Word.word \ bool \ word_width \ bool \ bool \((register_value),(unit),(exception))monad " where + " execute_LOAD imm rs1 rd is_unsigned width aq rl = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + translateAddr vaddr Read Data \ (\ (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => + (mem_read addr (( 1 :: int)::ii) aq rl False :: ( ( 8 Word.word)MemoryOpResult) M) \ (\ (w__2 :: ( 8 Word.word) + MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => + (mem_read addr (( 2 :: int)::ii) aq rl False :: ( ( 16 Word.word)MemoryOpResult) M) \ (\ (w__3 :: ( 16 Word.word) + MemoryOpResult) . + process_load rd vaddr w__3 is_unsigned) + | WORD => + (mem_read addr (( 4 :: int)::ii) aq rl False :: ( ( 32 Word.word)MemoryOpResult) M) \ (\ (w__4 :: ( 32 Word.word) + MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl False :: ( ( 64 Word.word)MemoryOpResult) M) \ (\ (w__5 :: ( 64 Word.word) + MemoryOpResult) . + process_load rd vaddr w__5 is_unsigned) + ) + )))))" + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + +fun execute_ITYPE :: "(12)Word.word \(5)Word.word \(5)Word.word \ iop \((register_value),(unit),(exception))monad " where + " execute_ITYPE imm rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (let (immext :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (result :: xlenbits) = + ((case op1 of + RISCV_ADDI => (add_vec rs1_val immext :: 64 Word.word) + | RISCV_SLTI => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_SLTIU => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_XORI => (xor_vec rs1_val immext :: 64 Word.word) + | RISCV_ORI => (or_vec rs1_val immext :: 64 Word.word) + | RISCV_ANDI => (and_vec rs1_val immext :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_ILLEGAL : unit -> M unit*) + +fun execute_ILLEGAL :: " unit \((register_value),(unit),(exception))monad " where + " execute_ILLEGAL g__112 = ( handle_illegal () )" + + +(*val execute_FENCEI : unit -> M unit*) + +fun execute_FENCEI :: " unit \((register_value),(unit),(exception))monad " where + " execute_FENCEI g__105 = ( MEM_fence_i () )" + + +(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*) + +fun execute_FENCE :: "(4)Word.word \(4)Word.word \((register_value),(unit),(exception))monad " where + " execute_FENCE b__0 b__1 = ( + if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then + MEM_fence_rw_rw () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then + MEM_fence_r_rw () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))))))) then + MEM_fence_r_r () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))))))) then + MEM_fence_rw_w () + else MEM_fence_w_w () )" + + +(*val execute_ECALL : unit -> M unit*) + +fun execute_ECALL :: " unit \((register_value),(unit),(exception))monad " where + " execute_ECALL g__106 = ( + read_reg cur_privilege_ref \ (\ (w__0 :: Privilege) . + (let (t :: sync_exception) = + ((| sync_exception_trap = + ((case w__0 of + User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + )), + sync_exception_excinfo = None |)) in + read_reg cur_privilege_ref \ (\ (w__1 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (handle_exception w__1 (CTL_TRAP t) w__2 :: ( 64 Word.word) M) \ (\ (w__3 :: xlenbits) . + write_reg nextPC_ref w__3))))))" + + +(*val execute_EBREAK : unit -> M unit*) + +fun execute_EBREAK :: " unit \((register_value),(unit),(exception))monad " where + " execute_EBREAK g__109 = ( throw (Error_EBREAK () ))" + + +(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_DIVW :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_DIVW rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in + (let (q' :: ii) = + (if (((s \ ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then + (( 0 :: int)::ii) - ((ex_int ((pow (( 2 :: int)::ii) (( 31 :: int)::ii))))) + else q) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 64 Word.word)))))))))))" + + +(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_DIV :: "(5)Word.word \(5)Word.word \(5)Word.word \ bool \((register_value),(unit),(exception))monad " where + " execute_DIV rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in + (let (q' :: ii) = (if (((s \ ((q > xlen_max_signed))))) then xlen_min_signed else q) in + wX ((regbits_to_regno rd)) ((to_bits xlen q' :: 64 Word.word)))))))))" + + +(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*) + +fun execute_C_ADDIW :: "(6)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_C_ADDIW imm rsd = ( + (let (imm :: 32 bits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in + (rX ((regbits_to_regno rsd)) :: ( 64 Word.word) M) \ (\ rs_val . + (let (res :: 32 bits) = + ((add_vec ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) imm :: 32 Word.word)) in + wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res :: 64 Word.word))))))" + + +(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*) + +fun execute_CSR :: "(12)Word.word \(5)Word.word \(5)Word.word \ bool \ csrop \((register_value),(unit),(exception))monad " where + " execute_CSR csr rs1 rd is_imm op1 = ( + (if is_imm then return ((EXTZ (( 64 :: int)::ii) rs1 :: 64 Word.word)) + else (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M)) \ (\ (rs1_val :: xlenbits) . + (let (isWrite :: bool) = + ((case op1 of + CSRRW => True + | _ => if is_imm then (((Word.uint rs1_val)) \ (( 0 :: int)::ii)) else (((Word.uint rs1)) \ (( 0 :: int)::ii)) + )) in + read_reg cur_privilege_ref \ (\ (w__1 :: Privilege) . + check_CSR csr w__1 isWrite \ (\ (w__2 :: bool) . + if ((\ w__2)) then handle_illegal () + else + (readCSR csr :: ( 64 Word.word) M) \ (\ csr_val . + (if isWrite then + (let (new_val :: xlenbits) = + ((case op1 of + CSRRW => rs1_val + | CSRRS => (or_vec csr_val rs1_val :: 64 Word.word) + | CSRRC => (and_vec csr_val ((not_vec rs1_val :: 64 Word.word)) :: 64 Word.word) + )) in + writeCSR csr new_val) + else return () ) \ + wX ((regbits_to_regno rd)) csr_val))))))" + + +(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*) + +fun execute_BTYPE :: "(13)Word.word \(5)Word.word \(5)Word.word \ bop \((register_value),(unit),(exception))monad " where + " execute_BTYPE imm rs2 rs1 op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ rs2_val . + (let (taken :: bool) = + ((case op1 of + RISCV_BEQ => (rs1_val = rs2_val) + | RISCV_BNE => (rs1_val \ rs2_val) + | RISCV_BLT => zopz0zI_s rs1_val rs2_val + | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val + | RISCV_BLTU => zopz0zI_u rs1_val rs2_val + | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val + )) in + if taken then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))) + else return () ))))" + + +(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_AMO :: " amoop \ bool \ bool \(5)Word.word \(5)Word.word \ word_width \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_AMO op1 aq rl rs2 rs1 width rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (vaddr :: xlenbits) . + translateAddr vaddr ReadWrite Data \ (\ (w__0 :: TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => mem_write_ea addr (( 4 :: int)::ii) (((aq \ rl))) rl True + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) (((aq \ rl))) rl True + | _ => internal_error (''AMO expected WORD or DOUBLE'') + ) \ (\ (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (case width of + WORD => + (mem_read addr (( 4 :: int)::ii) aq (((aq \ rl))) True :: ( ( 32 Word.word)MemoryOpResult) M) \ (\ (w__4 :: ( 32 Word.word) + MemoryOpResult) . + return ((extend_value False w__4 :: ( 64 Word.word) MemoryOpResult))) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq (((aq \ rl))) True :: ( ( 64 Word.word)MemoryOpResult) M) \ (\ (w__5 :: ( 64 Word.word) + MemoryOpResult) . + return ((extend_value False w__5 :: ( 64 Word.word) MemoryOpResult))) + | _ => (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 64 Word.word)MemoryOpResult) M) + ) \ (\ (rval :: xlenbits MemoryOpResult) . + (case rval of + MemException (e) => handle_mem_exception addr e + | MemValue (loaded) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \ (\ (rs2_val :: xlenbits) . + (let (result :: xlenbits) = + ((case op1 of + AMOSWAP => rs2_val + | AMOADD => (add_vec rs2_val loaded :: 64 Word.word) + | AMOXOR => (xor_vec rs2_val loaded :: 64 Word.word) + | AMOAND => (and_vec rs2_val loaded :: 64 Word.word) + | AMOOR => (or_vec rs2_val loaded :: 64 Word.word) + | AMOMIN => (vector64 ((min ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word) + | AMOMAX => (vector64 ((max ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word) + | AMOMINU => (vector64 ((min ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word) + | AMOMAXU => (vector64 ((max ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word) + )) in + (case width of + WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + (((aq \ rl))) rl True + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) result (((aq \ rl))) rl True + | _ => internal_error (''AMO expected WORD or DOUBLE'') + ) \ (\ (wval :: unit MemoryOpResult) . + (case wval of + MemValue (_) => wX ((regbits_to_regno rd)) loaded + | MemException (e) => handle_mem_exception addr e + )))) + )) + )) + ))))" + + +(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_ADDIW :: "(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " execute_ADDIW imm rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (result :: xlenbits) = ((add_vec ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) w__0 :: 64 Word.word)) in + wX ((regbits_to_regno rd)) + ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + + +function (sequential,domintros) execute :: " ast \((register_value),(unit),(exception))monad " where + " execute (C_ADDI4SPN (rdc,nzimm)) = ( + (let (imm :: 12 bits) = + ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word) + ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 10 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + execute (ITYPE (imm,sp,rd,RISCV_ADDI)))))" +|" execute (C_LW (uimm,rsc,rdc)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + (let rs = ((creg2reg_bits rsc :: 5 Word.word)) in + execute (LOAD (imm,rs,rd,False,WORD,False,False))))))" +|" execute (C_LD (uimm,rsc,rdc)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + (let rs = ((creg2reg_bits rsc :: 5 Word.word)) in + execute (LOAD (imm,rs,rd,False,DOUBLE,False,False))))))" +|" execute (C_SW (uimm,rsc1,rsc2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word)) + :: 12 Word.word)) in + (let rs1 = ((creg2reg_bits rsc1 :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rsc2 :: 5 Word.word)) in + execute (STORE (imm,rs2,rs1,WORD,False,False))))))" +|" execute (C_SD (uimm,rsc1,rsc2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + (let rs1 = ((creg2reg_bits rsc1 :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rsc2 :: 5 Word.word)) in + execute (STORE (imm,rs2,rs1,DOUBLE,False,False))))))" +|" execute (C_ADDI (nzi,rsd)) = ( + (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) nzi :: 12 Word.word)) in + execute (ITYPE (imm,rsd,rsd,RISCV_ADDI))))" +|" execute (C_JAL (imm)) = ( + execute + (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)) + :: 21 Word.word),ra)))" +|" execute (C_LI (imm,rd)) = ( + (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word)) in + execute (ITYPE (imm,zreg,rd,RISCV_ADDI))))" +|" execute (C_ADDI16SP (imm)) = ( + (let (imm :: 12 bits) = + ((EXTS (( 12 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 10 Word.word)) + :: 12 Word.word)) in + execute (ITYPE (imm,sp,sp,RISCV_ADDI))))" +|" execute (C_LUI (imm,rd)) = ( + (let (res :: 20 bits) = ((EXTS (( 20 :: int)::ii) imm :: 20 Word.word)) in + execute (UTYPE (res,rd,RISCV_LUI))))" +|" execute (C_SRLI (shamt,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI))))" +|" execute (C_SRAI (shamt,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI))))" +|" execute (C_ANDI (imm,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (ITYPE ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word),rsd,rsd,RISCV_ANDI))))" +|" execute (C_SUB (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_SUB)))))" +|" execute (C_XOR (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_XOR)))))" +|" execute (C_OR (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_OR)))))" +|" execute (C_AND (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_AND)))))" +|" execute (C_SUBW (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW)))))" +|" execute (C_ADDW (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW)))))" +|" execute (C_J (imm)) = ( + execute + (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)) + :: 21 Word.word),zreg)))" +|" execute (C_BEQZ (imm,rs)) = ( + execute + (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word)) + :: 13 Word.word),zreg,(creg2reg_bits rs :: 5 Word.word),RISCV_BEQ)))" +|" execute (C_BNEZ (imm,rs)) = ( + execute + (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word)) + :: 13 Word.word),zreg,(creg2reg_bits rs :: 5 Word.word),RISCV_BNE)))" +|" execute (C_SLLI (shamt,rsd)) = ( execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI)))" +|" execute (C_LWSP (uimm,rd)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + execute (LOAD (imm,sp,rd,False,WORD,False,False))))" +|" execute (C_LDSP (uimm,rd)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word)) + :: 12 Word.word)) in + execute (LOAD (imm,sp,rd,False,DOUBLE,False,False))))" +|" execute (C_SWSP (uimm,rs2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + execute (STORE (imm,rs2,sp,WORD,False,False))))" +|" execute (C_SDSP (uimm,rs2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word)) + :: 12 Word.word)) in + execute (STORE (imm,rs2,sp,DOUBLE,False,False))))" +|" execute (C_JR (rs1)) = ( + execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word),rs1,zreg)))" +|" execute (C_JALR (rs1)) = ( + execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word),rs1,ra)))" +|" execute (C_MV (rd,rs2)) = ( execute (RTYPE (rs2,zreg,rd,RISCV_ADD)))" +|" execute (C_ADD (rsd,rs2)) = ( execute (RTYPE (rs2,rsd,rsd,RISCV_ADD)))" +|" execute (UTYPE (imm,rd,op1)) = ( execute_UTYPE imm rd op1 )" +|" execute (RISCV_JAL (imm,rd)) = ( execute_RISCV_JAL imm rd )" +|" execute (RISCV_JALR (imm,rs1,rd)) = ( execute_RISCV_JALR imm rs1 rd )" +|" execute (BTYPE (imm,rs2,rs1,op1)) = ( execute_BTYPE imm rs2 rs1 op1 )" +|" execute (ITYPE (imm,rs1,rd,op1)) = ( execute_ITYPE imm rs1 rd op1 )" +|" execute (SHIFTIOP (shamt,rs1,rd,op1)) = ( execute_SHIFTIOP shamt rs1 rd op1 )" +|" execute (RTYPE (rs2,rs1,rd,op1)) = ( execute_RTYPE rs2 rs1 rd op1 )" +|" execute (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = ( execute_LOAD imm rs1 rd is_unsigned width aq rl )" +|" execute (STORE (imm,rs2,rs1,width,aq,rl)) = ( execute_STORE imm rs2 rs1 width aq rl )" +|" execute (ADDIW (imm,rs1,rd)) = ( execute_ADDIW imm rs1 rd )" +|" execute (SHIFTW (shamt,rs1,rd,op1)) = ( execute_SHIFTW shamt rs1 rd op1 )" +|" execute (RTYPEW (rs2,rs1,rd,op1)) = ( execute_RTYPEW rs2 rs1 rd op1 )" +|" execute (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( execute_MUL rs2 rs1 rd high signed1 signed2 )" +|" execute (DIV (rs2,rs1,rd,s)) = ( execute_DIV rs2 rs1 rd s )" +|" execute (REM (rs2,rs1,rd,s)) = ( execute_REM rs2 rs1 rd s )" +|" execute (MULW (rs2,rs1,rd)) = ( execute_MULW rs2 rs1 rd )" +|" execute (DIVW (rs2,rs1,rd,s)) = ( execute_DIVW rs2 rs1 rd s )" +|" execute (REMW (rs2,rs1,rd,s)) = ( execute_REMW rs2 rs1 rd s )" +|" execute (FENCE (pred,succ)) = ( execute_FENCE pred succ )" +|" execute (FENCEI (g__105)) = ( execute_FENCEI g__105 )" +|" execute (ECALL (g__106)) = ( execute_ECALL g__106 )" +|" execute (MRET (g__107)) = ( execute_MRET g__107 )" +|" execute (SRET (g__108)) = ( execute_SRET g__108 )" +|" execute (EBREAK (g__109)) = ( execute_EBREAK g__109 )" +|" execute (WFI (g__110)) = ( execute_WFI g__110 )" +|" execute (SFENCE_VMA (rs1,rs2)) = ( execute_SFENCE_VMA rs1 rs2 )" +|" execute (LOADRES (aq,rl,rs1,width,rd)) = ( execute_LOADRES aq rl rs1 width rd )" +|" execute (STORECON (aq,rl,rs2,rs1,width,rd)) = ( execute_STORECON aq rl rs2 rs1 width rd )" +|" execute (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( execute_AMO op1 aq rl rs2 rs1 width rd )" +|" execute (CSR (csr,rs1,rd,is_imm,op1)) = ( execute_CSR csr rs1 rd is_imm op1 )" +|" execute (NOP (g__111)) = ( return ((execute_NOP g__111)))" +|" execute (ILLEGAL (g__112)) = ( execute_ILLEGAL g__112 )" +|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )" +by pat_completeness auto + + +fun print_insn :: " ast \ string " where + " print_insn (UTYPE (imm,rd,op1)) = ( + (case op1 of + RISCV_LUI => + (op@) (''lui '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) + | RISCV_AUIPC => + (op@) (''auipc '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) + ))" +|" print_insn (RISCV_JAL (imm,rd)) = ( + (op@) (''jal '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (RISCV_JALR (imm,rs1,rd)) = ( + (op@) (''jalr '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" +|" print_insn (BTYPE (imm,rs2,rs1,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_BEQ => (''beq '') + | RISCV_BNE => (''bne '') + | RISCV_BLT => (''blt '') + | RISCV_BGE => (''bge '') + | RISCV_BLTU => (''bltu '') + | RISCV_BGEU => (''bgeu '') + )) in + (op@) insn + (((op@) ((reg_name_abi rs1)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs2)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (ITYPE (imm,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADDI => (''addi '') + | RISCV_SLTI => (''slti '') + | RISCV_SLTIU => (''sltiu '') + | RISCV_XORI => (''xori '') + | RISCV_ORI => (''ori '') + | RISCV_ANDI => (''andi '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (SHIFTIOP (shamt,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" +|" print_insn (RTYPE (rs2,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADD => (''add '') + | RISCV_SUB => (''sub '') + | RISCV_SLL => (''sll '') + | RISCV_SLT => (''slt '') + | RISCV_SLTU => (''sltu '') + | RISCV_XOR => (''xor '') + | RISCV_SRL => (''srl '') + | RISCV_SRA => (''sra '') + | RISCV_OR => (''or '') + | RISCV_AND => (''and '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = ( + (let (insn :: string) = + ((case (width, is_unsigned) of + (BYTE, False) => (''lb '') + | (BYTE, True) => (''lbu '') + | (HALF, False) => (''lh '') + | (HALF, True) => (''lhu '') + | (WORD, False) => (''lw '') + | (WORD, True) => (''lwu '') + | (DOUBLE, False) => (''ld '') + | (DOUBLE, True) => (''ldu '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (STORE (imm,rs2,rs1,width,aq,rl)) = ( + (let (insn :: string) = + ((case width of + BYTE => (''sb '') + | HALF => (''sh '') + | WORD => (''sw '') + | DOUBLE => (''sd '') + )) in + (op@) insn + (((op@) ((reg_name_abi rs2)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (ADDIW (imm,rs1,rd)) = ( + (op@) (''addiw '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" +|" print_insn (SHIFTW (shamt,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" +|" print_insn (RTYPEW (rs2,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADDW => (''addw '') + | RISCV_SUBW => (''subw '') + | RISCV_SLLW => (''sllw '') + | RISCV_SRLW => (''srlw '') + | RISCV_SRAW => (''sraw '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( + (let (insn :: string) = + ((case (high, signed1, signed2) of + (False, True, True) => (''mul '') + | (True, True, True) => (''mulh '') + | (True, True, False) => (''mulhsu '') + | (True, False, False) => (''mulhu'') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (DIV (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''div '') else (''divu '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (REM (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''rem '') else (''remu '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (MULW (rs2,rs1,rd)) = ( + (op@) (''mulw '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))))))" +|" print_insn (DIVW (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''divw '') else (''divuw '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (REMW (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''remw '') else (''remuw '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (FENCE (pred,succ)) = ( (''fence''))" +|" print_insn (FENCEI (g__93)) = ( (''fence.i''))" +|" print_insn (ECALL (g__94)) = ( (''ecall''))" +|" print_insn (MRET (g__95)) = ( (''mret''))" +|" print_insn (SRET (g__96)) = ( (''sret''))" +|" print_insn (EBREAK (g__97)) = ( (''ebreak''))" +|" print_insn (WFI (g__98)) = ( (''wfi''))" +|" print_insn (SFENCE_VMA (rs1,rs2)) = ( + (op@) (''sfence.vma '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))" +|" print_insn (LOADRES (aq,rl,rs1,width,rd)) = ( + (let (insn :: string) = + ((case width of WORD => (''lr.w '') | DOUBLE => (''lr.d '') | _ => (''lr.bad '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs1))))))))" +|" print_insn (STORECON (aq,rl,rs2,rs1,width,rd)) = ( + (let (insn :: string) = + ((case width of WORD => (''sc.w '') | DOUBLE => (''sc.d '') | _ => (''sc.bad '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( + (let (insn :: string) = + ((case (op1, width) of + (AMOSWAP, WORD) => (''amoswap.w '') + | (AMOADD, WORD) => (''amoadd.w '') + | (AMOXOR, WORD) => (''amoxor.w '') + | (AMOAND, WORD) => (''amoand.w '') + | (AMOOR, WORD) => (''amoor.w '') + | (AMOMIN, WORD) => (''amomin.w '') + | (AMOMAX, WORD) => (''amomax.w '') + | (AMOMINU, WORD) => (''amominu.w '') + | (AMOMAXU, WORD) => (''amomaxu.w '') + | (AMOSWAP, DOUBLE) => (''amoswap.d '') + | (AMOADD, DOUBLE) => (''amoadd.d '') + | (AMOXOR, DOUBLE) => (''amoxor.d '') + | (AMOAND, DOUBLE) => (''amoand.d '') + | (AMOOR, DOUBLE) => (''amoor.d '') + | (AMOMIN, DOUBLE) => (''amomin.d '') + | (AMOMAX, DOUBLE) => (''amomax.d '') + | (AMOMINU, DOUBLE) => (''amominu.d '') + | (AMOMAXU, DOUBLE) => (''amomaxu.d '') + | (_, _) => (''amo.bad '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (CSR (csr,rs1,rd,is_imm,op1)) = ( + (let (insn :: string) = + ((case (op1, is_imm) of + (CSRRW, True) => (''csrrwi '') + | (CSRRW, False) => (''csrrw '') + | (CSRRS, True) => (''csrrsi '') + | (CSRRS, False) => (''csrrs '') + | (CSRRC, True) => (''csrrci '') + | (CSRRC, False) => (''csrrc '') + )) in + (let (rs1_str :: string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') (((op@) rs1_str (((op@) ('', '') ((csr_name csr)))))))))))))" +|" print_insn (NOP (g__99)) = ( (''nop''))" +|" print_insn (ILLEGAL (g__100)) = ( (''illegal''))" +|" print_insn (C_ADDI4SPN (rdc,nzimm)) = ( + (op@) (''c.addi4spn '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec nzimm)))))))" +|" print_insn (C_LW (uimm,rsc,rdc)) = ( + (op@) (''c.lw '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_LD (uimm,rsc,rdc)) = ( + (op@) (''c.ld '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_SW (uimm,rsc1,rsc2)) = ( + (op@) (''c.sw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_SD (uimm,rsc1,rsc2)) = ( + (op@) (''c.sd '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_ADDI (nzi,rsd)) = ( + (op@) (''c.addi '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec nzi)))))))" +|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal '') ((string_of_vec imm)))" +|" print_insn (C_ADDIW (imm,rsd)) = ( + (op@) (''c.addiw '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_LI (imm,rd)) = ( + (op@) (''c.li '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp '') ((string_of_vec imm)))" +|" print_insn (C_LUI (imm,rd)) = ( + (op@) (''c.lui '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SRLI (shamt,rsd)) = ( + (op@) (''c.srli '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_SRAI (shamt,rsd)) = ( + (op@) (''c.srai '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_ANDI (imm,rsd)) = ( + (op@) (''c.andi '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SUB (rsd,rs2)) = ( + (op@) (''c.sub '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_XOR (rsd,rs2)) = ( + (op@) (''c.xor '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_OR (rsd,rs2)) = ( + (op@) (''c.or '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_AND (rsd,rs2)) = ( + (op@) (''c.and '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_SUBW (rsd,rs2)) = ( + (op@) (''c.subw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_ADDW (rsd,rs2)) = ( + (op@) (''c.addw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_J (imm)) = ( (op@) (''c.j '') ((string_of_vec imm)))" +|" print_insn (C_BEQZ (imm,rs)) = ( + (op@) (''c.beqz '') + (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_BNEZ (imm,rs)) = ( + (op@) (''c.bnez '') + (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SLLI (shamt,rsd)) = ( + (op@) (''c.slli '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_LWSP (uimm,rd)) = ( + (op@) (''c.lwsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_LDSP (uimm,rd)) = ( + (op@) (''c.ldsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_SWSP (uimm,rd)) = ( + (op@) (''c.swsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_SDSP (uimm,rd)) = ( + (op@) (''c.sdsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_JR (rs1)) = ( (op@) (''c.jr '') ((reg_name_abi rs1)))" +|" print_insn (C_JALR (rs1)) = ( (op@) (''c.jalr '') ((reg_name_abi rs1)))" +|" print_insn (C_MV (rd,rs2)) = ( + (op@) (''c.mv '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs2)))))))" +|" print_insn (C_ADD (rsd,rs2)) = ( + (op@) (''c.add '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((reg_name_abi rs2)))))))" + + +(*val isRVC : mword ty16 -> bool*) + +definition isRVC :: "(16)Word.word \ bool " where + " isRVC h = ( + \ (((((subrange_vec_dec h (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))" + + +(*val fetch : unit -> M FetchResult*) + +definition fetch :: " unit \((register_value),(FetchResult),(exception))monad " where + " fetch _ = ( + or_boolM + ((read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: xlenbits) . + return (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 :: int)::ii))) :: 1 Word.word)) \ (vec_of_bits [B0] :: 1 Word.word)))))) + (and_boolM + ((read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__1 :: xlenbits) . + return (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 :: int)::ii))) :: 1 Word.word)) \ (vec_of_bits [B0] :: 1 Word.word)))))) + (haveRVC () \ (\ (w__2 :: bool) . return ((\ w__2))))) \ (\ (w__4 :: bool) . + if w__4 then + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . + return (F_Error (E_Fetch_Addr_Align,w__5))) + else + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 Word.word) . + translateAddr w__6 Execute Instruction \ (\ (w__7 :: TR_Result) . + (case w__7 of + TR_Failure (e) => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 Word.word) . return (F_Error (e,w__8))) + | TR_Address (ppclo) => + (checked_mem_read Instruction ppclo (( 2 :: int)::ii) :: ( ( 16 Word.word)MemoryOpResult) M) \ (\ (w__9 :: ( 16 Word.word) + MemoryOpResult) . + (case w__9 of + MemException (e) => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__10 :: 64 Word.word) . + return (F_Error (E_Fetch_Access_Fault,w__10))) + | MemValue (ilo) => + if ((isRVC ilo)) then return (F_RVC ilo) + else + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__11 :: 64 Word.word) . + (let (PChi :: xlenbits) = ((add_vec_int w__11 (( 2 :: int)::ii) :: 64 Word.word)) in + translateAddr PChi Execute Instruction \ (\ (w__12 :: TR_Result) . + (case w__12 of + TR_Failure (e) => return (F_Error (e,PChi)) + | TR_Address (ppchi) => + (checked_mem_read Instruction ppchi (( 2 :: int)::ii) :: ( ( 16 Word.word)MemoryOpResult) M) \ (\ (w__13 :: ( 16 Word.word) + MemoryOpResult) . + return ((case w__13 of + MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) + | MemValue (ihi) => F_Base ((concat_vec ihi ilo :: 32 Word.word)) + ))) + )))) + )) + )))))" + + +(*val step : unit -> M bool*) + +definition step :: " unit \((register_value),(bool),(exception))monad " where + " step _ = ( + read_reg mip_ref \ (\ (w__0 :: Minterrupts) . + read_reg mie_ref \ (\ (w__1 :: Minterrupts) . + read_reg mideleg_ref \ (\ (w__2 :: Minterrupts) . + curInterrupt w__0 w__1 w__2 \ (\ (w__3 :: ((InterruptType * Privilege))option) . + (case w__3 of + Some (intr,priv) => + (let (_ :: unit) = (print_bits (''Handling interrupt: '') ((interruptType_to_bits intr :: 4 Word.word))) in + handle_interrupt intr priv \ return False) + | None => + fetch () \ (\ (w__4 :: FetchResult) . + (case w__4 of + F_Error (e,addr) => handle_mem_exception addr e \ return False + | F_RVC (h) => + (case ((decodeCompressed h)) of + None => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__5 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__5)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec h)) ('' : '')))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) h :: 64 Word.word)) \ return False)) + | Some (ast) => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__6 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__6)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec h)) + (((op@) ('' : '') ((print_insn ast))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii) :: 64 Word.word)) \ + execute ast) \ return True))) + ) + | F_Base (w) => + (case ((decode w)) of + None => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__9 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__9)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec w)) ('' : '')))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) w :: 64 Word.word)) \ return False)) + | Some (ast) => + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__10 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__10)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec w)) + (((op@) ('' : '') ((print_insn ast))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__11 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__11 (( 4 :: int)::ii) :: 64 Word.word)) \ + execute ast) \ return True))) + ) + )) + ))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| tlb39 = None, + tselect = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + stval = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + scause = + (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sepc = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sscratch = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + stvec = + (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + satp = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sideleg = + (Mk_Sinterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + sedeleg = + (Mk_Sedeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + pmpcfg0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + pmpaddr0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mhartid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + marchid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mimpid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mvendorid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + minstret = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtime = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mcycle = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mscratch = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtval = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mepc = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mcause = + (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtvec = + (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + medeleg = + (Mk_Medeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mideleg = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mie = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mip = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mstatus = + (Mk_Mstatus (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + misa = + (Mk_Misa (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + cur_inst = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + cur_privilege = User, + Xs = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod.thy b/snapshots/isabelle/riscv/Riscv_duopod.thy new file mode 100644 index 00000000..9087ec9c --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod.thy @@ -0,0 +1,461 @@ +chapter \Generated by Lem from riscv_duopod.lem.\ + +theory "Riscv_duopod" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Riscv_duopod_types" + "Riscv_extras" + +begin + +(*Generated by Sail from riscv_duopod.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Riscv_duopod_types*) +(*open import Riscv_extras*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) + +definition GetSlice_int :: " int \ int \ int \('n::len)Word.word " where + " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) + +definition RISCV_write :: "(64)Word.word \ int \('int8_times_n::len)Word.word \((register_value),(bool),(unit))monad " where + " RISCV_write addr width data = ( + write_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data \ + return True )" + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) + +definition RISCV_read :: "(64)Word.word \ int \((register_value),((('int8_times_n::len)Word.word)option),(unit))monad " where + " RISCV_read addr width = ( + (read_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \ (\ (w__0 :: ( 'int8_times_n::len)Word.word) . + return (Some w__0)))" + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val ex_nat : ii -> integer*) + +definition ex_nat :: " int \ int " where + " ex_nat n = ( n )" + + +(*val ex_int : ii -> integer*) + +definition ex_int :: " int \ int " where + " ex_int n = ( n )" + + +(*val coerce_int_nat : ii -> M ii*) + +definition coerce_int_nat :: " int \((register_value),(int),(unit))monad " where + " coerce_int_nat x = ( assert_exp True ('''') \ return x )" + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition EXTS :: " int \('n::len)Word.word \('m::len)Word.word " where + " EXTS (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" + + +definition EXTZ :: " int \('n::len)Word.word \('m::len)Word.word " where + " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \ ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \ ((Word.uint y)))" + + +definition zopz0zIzJ_u :: "('n::len)Word.word \('n::len)Word.word \ bool " where + " zopz0zIzJ_u x y = ( ((Word.uint x)) \ ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \ bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val vector64 : ii -> mword ty64*) + +definition vector64 :: " int \(64)Word.word " where + " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) + +definition to_bits :: " int \ int \('l::len)Word.word " where + " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" + + +(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) + +definition shift_right_arith64 :: "(64)Word.word \(6)Word.word \(64)Word.word " where + " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = ( + (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in + (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))" + + +(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) + +definition shift_right_arith32 :: "(32)Word.word \(5)Word.word \(32)Word.word " where + " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = ( + (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in + (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))" + + +(*val zeros : forall 'n. Size 'n => integer -> mword 'n*) + +definition zeros0 :: " int \('n::len)Word.word " where + " zeros0 n = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n :: ( 'n::len)Word.word))" + + +(*val regbits_to_regno : mword ty5 -> integer*) + +definition regbits_to_regno :: "(5)Word.word \ int " where + " regbits_to_regno b = ( + (let r = (Word.uint b) in + r))" + + +(*val rX : integer -> M (mword ty64)*) + +definition rX :: " int \((register_value),((64)Word.word),(unit))monad " where + " rX l__5 = ( + if (((l__5 = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg Xs_ref \ (\ (w__0 :: xlen_t list) . + return ((access_list_dec w__0 l__5 :: 64 Word.word))))" + + +(*val wX : integer -> mword ty64 -> M unit*) + +definition wX :: " int \(64)Word.word \((register_value),(unit),(unit))monad " where + " wX r v = ( + if (((r \ (( 0 :: int)::ii)))) then + read_reg Xs_ref \ (\ (w__0 :: ( 64 Word.word) list) . + write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list))) + else return () )" + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (mword 'int8_times_n)*) + +definition MEMr :: "(64)Word.word \ int \((register_value),(('int8_times_n::len)Word.word),(unit))monad " where + " MEMr addr width = ( + (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \ (\ (w__0 :: + (( 'int8_times_n::len)Word.word)option) . + return ((case w__0 of + Some (v) => v + | None => (zeros0 (((( 8 :: int)::ii) * width)) :: ( 'int8_times_n::len)Word.word) + ))))" + + +(*val iop_of_num : integer -> iop*) + +definition iop_of_num :: " int \ iop " where + " iop_of_num arg0 = ( + (let l__0 = arg0 in + if (((l__0 = (( 0 :: int)::ii)))) then RISCV_ADDI + else if (((l__0 = (( 1 :: int)::ii)))) then RISCV_SLTI + else if (((l__0 = (( 2 :: int)::ii)))) then RISCV_SLTIU + else if (((l__0 = (( 3 :: int)::ii)))) then RISCV_XORI + else if (((l__0 = (( 4 :: int)::ii)))) then RISCV_ORI + else RISCV_ANDI))" + + +(*val num_of_iop : iop -> integer*) + +fun num_of_iop :: " iop \ int " where + " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))" +|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))" +|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))" +|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))" +|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))" +|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))" + + +(*val decode : mword ty32 -> maybe ast*) + +(*val execute : ast -> M unit*) + +definition decode :: "(32)Word.word \(ast)option " where + " decode v__0 = ( + if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd))))) + else None )" + + +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_LOAD :: "(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(unit))monad " where + " execute_LOAD imm rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (addr :: xlen_t) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + (MEMr addr (( 8 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: xlen_t) . + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + +fun execute_ITYPE :: "(12)Word.word \(5)Word.word \(5)Word.word \ iop \((register_value),(unit),(unit))monad " where + " execute_ITYPE imm rs1 rd RISCV_ADDI = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \ (\ rs1_val . + (let (imm_ext :: xlen_t) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let result = ((add_vec rs1_val imm_ext :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result))))" + + +fun execute :: " ast \((register_value),(unit),(unit))monad " where + " execute (ITYPE (imm,rs1,rd,arg3)) = ( execute_ITYPE imm rs1 rd arg3 )" +|" execute (LOAD (imm,rs1,rd)) = ( execute_LOAD imm rs1 rd )" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| Xs = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy new file mode 100644 index 00000000..d6ca4d7d --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy @@ -0,0 +1,48 @@ +theory Riscv_duopod_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Riscv_duopod +begin + +abbreviation "liftS \ liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def Xs_ref_def nextPC_ref_def PC_ref_def + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \ rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_Xs[simp]: + "liftS (read_reg Xs_ref) = readS (Xs \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Xs[simp]: + "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_types.thy b/snapshots/isabelle/riscv/Riscv_duopod_types.thy new file mode 100644 index 00000000..8e92ede0 --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod_types.thy @@ -0,0 +1,170 @@ +chapter \Generated by Lem from riscv_duopod_types.lem.\ + +theory "Riscv_duopod_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from riscv_duopod.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +type_synonym xlen =" int " + +type_synonym xlen_t =" 64 bits " + +type_synonym 'n regno =" int " + +type_synonym regbits =" 5 bits " + +datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI + + + +datatype ast = + ITYPE " (( 12 bits * regbits * regbits * iop))" | LOAD " (( 12 bits * regbits * regbits))" + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + + + +record regstate = + Xs ::" ( 64 Word.word) list " + nextPC ::" 64 Word.word " + PC ::" 64 Word.word " + + + + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__6 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \ register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " vector_of_regval of_regval1 = ( \x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \ register_value)\ int \ bool \ 'a list \ register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " list_of_regval of_regval1 = ( \x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \ register_value)\ 'a list \ register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \ 'a option)\ register_value \('a option)option " where + " option_of_regval of_regval1 = ( \x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \ register_value)\ 'a option \ register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " Xs_ref = ( (| + name = (''Xs''), + read_from = (\ s . (Xs s)), + write_to = (\ v s . (( s (| Xs := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\ s . (nextPC s)), + write_to = (\ v s . (( s (| nextPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\ s . (PC s)), + write_to = (\ v s . (( s (| PC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \ regstate \(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \ register_value \ regstate \(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''Xs'') then map_option (\ v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else + if reg_name = (''nextPC'') then map_option (\ v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\ v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \ regstate \(register_value)option)*(string \ register_value \ regstate \(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, unit) monadR " +type_synonym 'a M =" (register_value, 'a, unit) monad " +end diff --git a/snapshots/isabelle/riscv/Riscv_extras.thy b/snapshots/isabelle/riscv/Riscv_extras.thy new file mode 100644 index 00000000..fc83385b --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_extras.thy @@ -0,0 +1,126 @@ +chapter \Generated by Lem from riscv_extras.lem.\ + +theory "Riscv_extras" + +imports + Main + "Lem_pervasives" + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) + +type_synonym 'a bitvector =" ( 'a::len)Word.word " + +definition MEM_fence_rw_rw :: " unit \('b,(unit),'a)monad " where + " MEM_fence_rw_rw _ = ( barrier Barrier_RISCV_rw_rw )" + +definition MEM_fence_r_rw :: " unit \('b,(unit),'a)monad " where + " MEM_fence_r_rw _ = ( barrier Barrier_RISCV_r_rw )" + +definition MEM_fence_r_r :: " unit \('b,(unit),'a)monad " where + " MEM_fence_r_r _ = ( barrier Barrier_RISCV_r_r )" + +definition MEM_fence_rw_w :: " unit \('b,(unit),'a)monad " where + " MEM_fence_rw_w _ = ( barrier Barrier_RISCV_rw_w )" + +definition MEM_fence_w_w :: " unit \('b,(unit),'a)monad " where + " MEM_fence_w_w _ = ( barrier Barrier_RISCV_w_w )" + +definition MEM_fence_i :: " unit \('b,(unit),'a)monad " where + " MEM_fence_i _ = ( barrier Barrier_RISCV_i )" + + +(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) + +definition MEMea :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " where + " MEMea addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )" + +definition MEMea_release :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " where + " MEMea_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )" + +definition MEMea_strong_release :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " where + " MEMea_strong_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )" + +definition MEMea_conditional :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " where + " MEMea_conditional addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )" + +definition MEMea_conditional_release :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " where + " MEMea_conditional_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )" + +definition MEMea_conditional_strong_release :: "('a::len)Word.word \ int \('rv,(unit),'e)monad " + where + " MEMea_conditional_strong_release addr size1 + = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )" + + +(*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*) +definition write_ram :: " int \ int \('a::len)Word.word \('a::len)Word.word \('b::len)Word.word \('rv,(unit),'e)monad " where + " write_ram addrsize size1 hexRAM address value1 = ( + (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \ + write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \ (\x . (case x of _ => return () )) )" + + +(*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +definition read_ram :: " int \ int \('a::len)Word.word \('a::len)Word.word \('rv,(('b::len)Word.word),'e)monad " where + " read_ram addrsize size1 hexRAM address = ( + read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )" + + +definition speculate_conditional_success :: " unit \('b,(bool),'a)monad " where + " speculate_conditional_success _ = ( excl_result () )" + + +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*) +definition get_slice_int0 :: " int \ int \ int \('a::len)Word.word " where + " get_slice_int0 len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bits = (bits_of_int (hi +( 1 :: int)) n) in + of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list False bits hi lo))))" + + +(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +definition shift_bits_right :: "('a::len)Word.word \('b::len)Word.word \('a::len)Word.word " where + " shift_bits_right v m = ( shiftr v (Word.uint m))" + +(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +definition shift_bits_left :: "('a::len)Word.word \('b::len)Word.word \('a::len)Word.word " where + " shift_bits_left v m = ( shiftl v (Word.uint m))" + + +(*val print_string : string -> string -> unit*) +definition print_string :: " string \ string \ unit " where + " print_string msg s = ( prerr_endline (msg @ s))" + + +(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) +definition print_bits :: " string \('a::len)Word.word \ unit " where + " print_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))" + +end diff --git a/snapshots/isabelle/riscv/Riscv_lemmas.thy b/snapshots/isabelle/riscv/Riscv_lemmas.thy new file mode 100644 index 00000000..b2f4e80d --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_lemmas.thy @@ -0,0 +1,350 @@ +theory Riscv_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Riscv +begin + +abbreviation "liftS \ liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def tselect_ref_def stval_ref_def + scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def satp_ref_def sideleg_ref_def + sedeleg_ref_def pmpcfg0_ref_def pmpaddr0_ref_def mhartid_ref_def marchid_ref_def mimpid_ref_def + mvendorid_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def mscratch_ref_def mtval_ref_def + mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def + mstatus_ref_def misa_ref_def cur_inst_ref_def cur_privilege_ref_def Xs_ref_def nextPC_ref_def + PC_ref_def + +lemma regval_Mcause[simp]: + "Mcause_of_regval (regval_of_Mcause v) = Some v" + by (auto simp: regval_of_Mcause_def) + +lemma regval_Medeleg[simp]: + "Medeleg_of_regval (regval_of_Medeleg v) = Some v" + by (auto simp: regval_of_Medeleg_def) + +lemma regval_Minterrupts[simp]: + "Minterrupts_of_regval (regval_of_Minterrupts v) = Some v" + by (auto simp: regval_of_Minterrupts_def) + +lemma regval_Misa[simp]: + "Misa_of_regval (regval_of_Misa v) = Some v" + by (auto simp: regval_of_Misa_def) + +lemma regval_Mstatus[simp]: + "Mstatus_of_regval (regval_of_Mstatus v) = Some v" + by (auto simp: regval_of_Mstatus_def) + +lemma regval_Mtvec[simp]: + "Mtvec_of_regval (regval_of_Mtvec v) = Some v" + by (auto simp: regval_of_Mtvec_def) + +lemma regval_Privilege[simp]: + "Privilege_of_regval (regval_of_Privilege v) = Some v" + by (auto simp: regval_of_Privilege_def) + +lemma regval_Sedeleg[simp]: + "Sedeleg_of_regval (regval_of_Sedeleg v) = Some v" + by (auto simp: regval_of_Sedeleg_def) + +lemma regval_Sinterrupts[simp]: + "Sinterrupts_of_regval (regval_of_Sinterrupts v) = Some v" + by (auto simp: regval_of_Sinterrupts_def) + +lemma regval_TLB39_Entry[simp]: + "TLB39_Entry_of_regval (regval_of_TLB39_Entry v) = Some v" + by (auto simp: regval_of_TLB39_Entry_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \ rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_tlb39[simp]: + "liftS (read_reg tlb39_ref) = readS (tlb39 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tlb39[simp]: + "liftS (write_reg tlb39_ref v) = updateS (regstate_update (tlb39_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_tselect[simp]: + "liftS (read_reg tselect_ref) = readS (tselect \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tselect[simp]: + "liftS (write_reg tselect_ref v) = updateS (regstate_update (tselect_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stval[simp]: + "liftS (read_reg stval_ref) = readS (stval \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stval[simp]: + "liftS (write_reg stval_ref v) = updateS (regstate_update (stval_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_scause[simp]: + "liftS (read_reg scause_ref) = readS (scause \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_scause[simp]: + "liftS (write_reg scause_ref v) = updateS (regstate_update (scause_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sepc[simp]: + "liftS (read_reg sepc_ref) = readS (sepc \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sepc[simp]: + "liftS (write_reg sepc_ref v) = updateS (regstate_update (sepc_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sscratch[simp]: + "liftS (read_reg sscratch_ref) = readS (sscratch \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sscratch[simp]: + "liftS (write_reg sscratch_ref v) = updateS (regstate_update (sscratch_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stvec[simp]: + "liftS (read_reg stvec_ref) = readS (stvec \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stvec[simp]: + "liftS (write_reg stvec_ref v) = updateS (regstate_update (stvec_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_satp[simp]: + "liftS (read_reg satp_ref) = readS (satp \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_satp[simp]: + "liftS (write_reg satp_ref v) = updateS (regstate_update (satp_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sideleg[simp]: + "liftS (read_reg sideleg_ref) = readS (sideleg \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sideleg[simp]: + "liftS (write_reg sideleg_ref v) = updateS (regstate_update (sideleg_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sedeleg[simp]: + "liftS (read_reg sedeleg_ref) = readS (sedeleg \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sedeleg[simp]: + "liftS (write_reg sedeleg_ref v) = updateS (regstate_update (sedeleg_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpcfg0[simp]: + "liftS (read_reg pmpcfg0_ref) = readS (pmpcfg0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpcfg0[simp]: + "liftS (write_reg pmpcfg0_ref v) = updateS (regstate_update (pmpcfg0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpaddr0[simp]: + "liftS (read_reg pmpaddr0_ref) = readS (pmpaddr0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpaddr0[simp]: + "liftS (write_reg pmpaddr0_ref v) = updateS (regstate_update (pmpaddr0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mhartid[simp]: + "liftS (read_reg mhartid_ref) = readS (mhartid \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mhartid[simp]: + "liftS (write_reg mhartid_ref v) = updateS (regstate_update (mhartid_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_marchid[simp]: + "liftS (read_reg marchid_ref) = readS (marchid \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_marchid[simp]: + "liftS (write_reg marchid_ref v) = updateS (regstate_update (marchid_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mimpid[simp]: + "liftS (read_reg mimpid_ref) = readS (mimpid \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mimpid[simp]: + "liftS (write_reg mimpid_ref v) = updateS (regstate_update (mimpid_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mvendorid[simp]: + "liftS (read_reg mvendorid_ref) = readS (mvendorid \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mvendorid[simp]: + "liftS (write_reg mvendorid_ref v) = updateS (regstate_update (mvendorid_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_minstret[simp]: + "liftS (read_reg minstret_ref) = readS (minstret \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_minstret[simp]: + "liftS (write_reg minstret_ref v) = updateS (regstate_update (minstret_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtime[simp]: + "liftS (read_reg mtime_ref) = readS (mtime \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtime[simp]: + "liftS (write_reg mtime_ref v) = updateS (regstate_update (mtime_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcycle[simp]: + "liftS (read_reg mcycle_ref) = readS (mcycle \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcycle[simp]: + "liftS (write_reg mcycle_ref v) = updateS (regstate_update (mcycle_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mscratch[simp]: + "liftS (read_reg mscratch_ref) = readS (mscratch \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mscratch[simp]: + "liftS (write_reg mscratch_ref v) = updateS (regstate_update (mscratch_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtval[simp]: + "liftS (read_reg mtval_ref) = readS (mtval \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtval[simp]: + "liftS (write_reg mtval_ref v) = updateS (regstate_update (mtval_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mepc[simp]: + "liftS (read_reg mepc_ref) = readS (mepc \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mepc[simp]: + "liftS (write_reg mepc_ref v) = updateS (regstate_update (mepc_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcause[simp]: + "liftS (read_reg mcause_ref) = readS (mcause \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcause[simp]: + "liftS (write_reg mcause_ref v) = updateS (regstate_update (mcause_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtvec[simp]: + "liftS (read_reg mtvec_ref) = readS (mtvec \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtvec[simp]: + "liftS (write_reg mtvec_ref v) = updateS (regstate_update (mtvec_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_medeleg[simp]: + "liftS (read_reg medeleg_ref) = readS (medeleg \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_medeleg[simp]: + "liftS (write_reg medeleg_ref v) = updateS (regstate_update (medeleg_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mideleg[simp]: + "liftS (read_reg mideleg_ref) = readS (mideleg \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mideleg[simp]: + "liftS (write_reg mideleg_ref v) = updateS (regstate_update (mideleg_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mie[simp]: + "liftS (read_reg mie_ref) = readS (mie \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mie[simp]: + "liftS (write_reg mie_ref v) = updateS (regstate_update (mie_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mip[simp]: + "liftS (read_reg mip_ref) = readS (mip \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mip[simp]: + "liftS (write_reg mip_ref v) = updateS (regstate_update (mip_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mstatus[simp]: + "liftS (read_reg mstatus_ref) = readS (mstatus \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mstatus[simp]: + "liftS (write_reg mstatus_ref v) = updateS (regstate_update (mstatus_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_misa[simp]: + "liftS (read_reg misa_ref) = readS (misa \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_misa[simp]: + "liftS (write_reg misa_ref v) = updateS (regstate_update (misa_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_inst[simp]: + "liftS (read_reg cur_inst_ref) = readS (cur_inst \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_cur_inst[simp]: + "liftS (write_reg cur_inst_ref v) = updateS (regstate_update (cur_inst_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_privilege[simp]: + "liftS (read_reg cur_privilege_ref) = readS (cur_privilege \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_cur_privilege[simp]: + "liftS (write_reg cur_privilege_ref v) = updateS (regstate_update (cur_privilege_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_Xs[simp]: + "liftS (read_reg Xs_ref) = readS (Xs \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Xs[simp]: + "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/riscv/Riscv_types.thy b/snapshots/isabelle/riscv/Riscv_types.thy new file mode 100644 index 00000000..b4fc7f6c --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_types.thy @@ -0,0 +1,1052 @@ +chapter \Generated by Lem from riscv_types.lem.\ + +theory "Riscv_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from riscv.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +type_synonym xlenbits =" 64 bits " + +type_synonym half =" 16 bits " + +type_synonym word0 =" 32 bits " + +type_synonym 'n regno =" int " + +type_synonym regbits =" 5 bits " + +type_synonym cregbits =" 3 bits " + +type_synonym csreg =" 12 bits " + +type_synonym opcode =" 7 bits " + +type_synonym imm12 =" 12 bits " + +type_synonym imm20 =" 20 bits " + +type_synonym amo =" 1 bits " + +datatype Architecture = RV32 | RV64 | RV128 + + + +type_synonym arch_xlen =" 2 bits " + +type_synonym priv_level =" 2 bits " + +datatype Privilege = User | Supervisor | Machine + + + +datatype AccessType = Read | Write | ReadWrite | Execute + + + +datatype ReadType = Instruction | Data + + + +type_synonym exc_code =" 4 bits " + +datatype ExceptionType = + E_Fetch_Addr_Align + | E_Fetch_Access_Fault + | E_Illegal_Instr + | E_Breakpoint + | E_Load_Addr_Align + | E_Load_Access_Fault + | E_SAMO_Addr_Align + | E_SAMO_Access_Fault + | E_U_EnvCall + | E_S_EnvCall + | E_Reserved_10 + | E_M_EnvCall + | E_Fetch_Page_Fault + | E_Load_Page_Fault + | E_Reserved_14 + | E_SAMO_Page_Fault + + + +datatype InterruptType = + I_U_Software + | I_S_Software + | I_M_Software + | I_U_Timer + | I_S_Timer + | I_M_Timer + | I_U_External + | I_S_External + | I_M_External + + + +type_synonym tv_mode =" 2 bits " + +datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved + + + +datatype exception = + Error_not_implemented " (string)" | Error_EBREAK " (unit)" | Error_internal_error " (unit)" + + + +type_synonym ext_status =" 2 bits " + +datatype ExtStatus = Off | Initial | Clean | Dirty + + + +type_synonym satp_mode =" 4 bits " + +datatype SATPMode = Sbare | Sv32 | Sv39 + + + +type_synonym csrRW =" 2 bits " + +datatype uop = RISCV_LUI | RISCV_AUIPC + + + +datatype bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU + + + +datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI + + + +datatype sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI + + + +datatype rop = + RISCV_ADD + | RISCV_SUB + | RISCV_SLL + | RISCV_SLT + | RISCV_SLTU + | RISCV_XOR + | RISCV_SRL + | RISCV_SRA + | RISCV_OR + | RISCV_AND + + + +datatype ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW + + + +datatype amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU + + + +datatype csrop = CSRRW | CSRRS | CSRRC + + + +datatype word_width = BYTE | HALF | WORD | DOUBLE + + + +datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)" + + + +datatype Misa = Mk_Misa " ( 64 Word.word)" + + + +datatype SV39_PTE = Mk_SV39_PTE " ( 64 Word.word)" + + + +datatype PTE_Bits = Mk_PTE_Bits " ( 8 Word.word)" + + + +datatype Mstatus = Mk_Mstatus " ( 64 Word.word)" + + + +datatype Sstatus = Mk_Sstatus " ( 64 Word.word)" + + + +datatype Minterrupts = Mk_Minterrupts " ( 64 Word.word)" + + + +datatype Sinterrupts = Mk_Sinterrupts " ( 64 Word.word)" + + + +datatype Medeleg = Mk_Medeleg " ( 64 Word.word)" + + + +datatype Sedeleg = Mk_Sedeleg " ( 64 Word.word)" + + + +datatype Mtvec = Mk_Mtvec " ( 64 Word.word)" + + + +datatype Satp64 = Mk_Satp64 " ( 64 Word.word)" + + + +datatype Mcause = Mk_Mcause " ( 64 Word.word)" + + + +record sync_exception = + + sync_exception_trap ::" ExceptionType " + sync_exception_excinfo ::" xlenbits option " + + + +datatype ctl_result = CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL_MRET " (unit)" + + + +type_synonym pteAttribs =" 8 bits " + +datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update + + + +type_synonym vaddr39 =" 39 bits " + +type_synonym paddr39 =" 56 bits " + +type_synonym pte39 =" xlenbits " + +datatype SV39_Vaddr = Mk_SV39_Vaddr " ( 39 Word.word)" + + + +datatype SV39_Paddr = Mk_SV39_Paddr " ( 56 Word.word)" + + + +type_synonym asid64 =" 16 bits " + +datatype PTW_Result = + PTW_Success " ((paddr39 * SV39_PTE * paddr39 * ii * bool))" | PTW_Failure " (PTW_Error)" + + + +record TLB39_Entry = + + TLB39_Entry_asid ::" asid64 " + + TLB39_Entry_global ::" bool " + + TLB39_Entry_vAddr ::" vaddr39 " + + TLB39_Entry_pAddr ::" paddr39 " + + TLB39_Entry_vMatchMask ::" vaddr39 " + + TLB39_Entry_vAddrMask ::" vaddr39 " + + TLB39_Entry_pte ::" SV39_PTE " + + TLB39_Entry_pteAddr ::" paddr39 " + + TLB39_Entry_age ::" xlenbits " + + + +datatype TR39_Result = TR39_Address " (paddr39)" | TR39_Failure " (PTW_Error)" + + + +datatype TR_Result = TR_Address " (xlenbits)" | TR_Failure " (ExceptionType)" + + + +datatype (plugins only: size) ast = + UTYPE " (( 20 bits * regbits * uop))" + | RISCV_JAL " (( 21 bits * regbits))" + | RISCV_JALR " (( 12 bits * regbits * regbits))" + | BTYPE " (( 13 bits * regbits * regbits * bop))" + | ITYPE " (( 12 bits * regbits * regbits * iop))" + | SHIFTIOP " (( 6 bits * regbits * regbits * sop))" + | RTYPE " ((regbits * regbits * regbits * rop))" + | LOAD " (( 12 bits * regbits * regbits * bool * word_width * bool * bool))" + | STORE " (( 12 bits * regbits * regbits * word_width * bool * bool))" + | ADDIW " (( 12 bits * regbits * regbits))" + | SHIFTW " (( 5 bits * regbits * regbits * sop))" + | RTYPEW " ((regbits * regbits * regbits * ropw))" + | MUL " ((regbits * regbits * regbits * bool * bool * bool))" + | DIV " ((regbits * regbits * regbits * bool))" + | REM " ((regbits * regbits * regbits * bool))" + | MULW " ((regbits * regbits * regbits))" + | DIVW " ((regbits * regbits * regbits * bool))" + | REMW " ((regbits * regbits * regbits * bool))" + | FENCE " (( 4 bits * 4 bits))" + | FENCEI " (unit)" + | ECALL " (unit)" + | MRET " (unit)" + | SRET " (unit)" + | EBREAK " (unit)" + | WFI " (unit)" + | SFENCE_VMA " ((regbits * regbits))" + | LOADRES " ((bool * bool * regbits * word_width * regbits))" + | STORECON " ((bool * bool * regbits * regbits * word_width * regbits))" + | AMO " ((amoop * bool * bool * regbits * regbits * word_width * regbits))" + | CSR " (( 12 bits * regbits * regbits * bool * csrop))" + | NOP " (unit)" + | ILLEGAL " (unit)" + | C_ADDI4SPN " ((cregbits * 8 bits))" + | C_LW " (( 5 bits * cregbits * cregbits))" + | C_LD " (( 5 bits * cregbits * cregbits))" + | C_SW " (( 5 bits * cregbits * cregbits))" + | C_SD " (( 5 bits * cregbits * cregbits))" + | C_ADDI " (( 6 bits * regbits))" + | C_JAL " ( 11 bits)" + | C_ADDIW " (( 6 bits * regbits))" + | C_LI " (( 6 bits * regbits))" + | C_ADDI16SP " ( 6 bits)" + | C_LUI " (( 6 bits * regbits))" + | C_SRLI " (( 6 bits * cregbits))" + | C_SRAI " (( 6 bits * cregbits))" + | C_ANDI " (( 6 bits * cregbits))" + | C_SUB " ((cregbits * cregbits))" + | C_XOR " ((cregbits * cregbits))" + | C_OR " ((cregbits * cregbits))" + | C_AND " ((cregbits * cregbits))" + | C_SUBW " ((cregbits * cregbits))" + | C_ADDW " ((cregbits * cregbits))" + | C_J " ( 11 bits)" + | C_BEQZ " (( 8 bits * cregbits))" + | C_BNEZ " (( 8 bits * cregbits))" + | C_SLLI " (( 6 bits * regbits))" + | C_LWSP " (( 6 bits * regbits))" + | C_LDSP " (( 6 bits * regbits))" + | C_SWSP " (( 6 bits * regbits))" + | C_SDSP " (( 6 bits * regbits))" + | C_JR " (regbits)" + | C_JALR " (regbits)" + | C_MV " ((regbits * regbits))" + | C_ADD " ((regbits * regbits))" + + + +datatype FetchResult = F_Base " (word0)" | F_RVC " (half)" | F_Error " ((ExceptionType * xlenbits))" + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_Mcause " (Mcause)" + | Regval_Medeleg " (Medeleg)" + | Regval_Minterrupts " (Minterrupts)" + | Regval_Misa " (Misa)" + | Regval_Mstatus " (Mstatus)" + | Regval_Mtvec " (Mtvec)" + | Regval_Privilege " (Privilege)" + | Regval_Sedeleg " (Sedeleg)" + | Regval_Sinterrupts " (Sinterrupts)" + | Regval_TLB39_Entry " (TLB39_Entry)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + + + +record regstate = + + tlb39 ::" TLB39_Entry option " + + tselect ::" 64 Word.word " + + stval ::" 64 Word.word " + + scause ::" Mcause " + + sepc ::" 64 Word.word " + + sscratch ::" 64 Word.word " + + stvec ::" Mtvec " + + satp ::" 64 Word.word " + + sideleg ::" Sinterrupts " + + sedeleg ::" Sedeleg " + + pmpcfg0 ::" 64 Word.word " + + pmpaddr0 ::" 64 Word.word " + + mhartid ::" 64 Word.word " + + marchid ::" 64 Word.word " + + mimpid ::" 64 Word.word " + + mvendorid ::" 64 Word.word " + + minstret ::" 64 Word.word " + + mtime ::" 64 Word.word " + + mcycle ::" 64 Word.word " + + mscratch ::" 64 Word.word " + + mtval ::" 64 Word.word " + + mepc ::" 64 Word.word " + + mcause ::" Mcause " + + mtvec ::" Mtvec " + + medeleg ::" Medeleg " + + mideleg ::" Minterrupts " + + mie ::" Minterrupts " + + mip ::" Minterrupts " + + mstatus ::" Mstatus " + + misa ::" Misa " + + cur_inst ::" 64 Word.word " + + cur_privilege ::" Privilege " + + Xs ::" ( 64 Word.word) list " + + nextPC ::" 64 Word.word " + + PC ::" 64 Word.word " + + + + + +(*val Mcause_of_regval : register_value -> maybe Mcause*) + +fun Mcause_of_regval :: " register_value \(Mcause)option " where + " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )" +|" Mcause_of_regval g__92 = ( None )" + + +(*val regval_of_Mcause : Mcause -> register_value*) + +definition regval_of_Mcause :: " Mcause \ register_value " where + " regval_of_Mcause v = ( Regval_Mcause v )" + + +(*val Medeleg_of_regval : register_value -> maybe Medeleg*) + +fun Medeleg_of_regval :: " register_value \(Medeleg)option " where + " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )" +|" Medeleg_of_regval g__91 = ( None )" + + +(*val regval_of_Medeleg : Medeleg -> register_value*) + +definition regval_of_Medeleg :: " Medeleg \ register_value " where + " regval_of_Medeleg v = ( Regval_Medeleg v )" + + +(*val Minterrupts_of_regval : register_value -> maybe Minterrupts*) + +fun Minterrupts_of_regval :: " register_value \(Minterrupts)option " where + " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )" +|" Minterrupts_of_regval g__90 = ( None )" + + +(*val regval_of_Minterrupts : Minterrupts -> register_value*) + +definition regval_of_Minterrupts :: " Minterrupts \ register_value " where + " regval_of_Minterrupts v = ( Regval_Minterrupts v )" + + +(*val Misa_of_regval : register_value -> maybe Misa*) + +fun Misa_of_regval :: " register_value \(Misa)option " where + " Misa_of_regval (Regval_Misa (v)) = ( Some v )" +|" Misa_of_regval g__89 = ( None )" + + +(*val regval_of_Misa : Misa -> register_value*) + +definition regval_of_Misa :: " Misa \ register_value " where + " regval_of_Misa v = ( Regval_Misa v )" + + +(*val Mstatus_of_regval : register_value -> maybe Mstatus*) + +fun Mstatus_of_regval :: " register_value \(Mstatus)option " where + " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )" +|" Mstatus_of_regval g__88 = ( None )" + + +(*val regval_of_Mstatus : Mstatus -> register_value*) + +definition regval_of_Mstatus :: " Mstatus \ register_value " where + " regval_of_Mstatus v = ( Regval_Mstatus v )" + + +(*val Mtvec_of_regval : register_value -> maybe Mtvec*) + +fun Mtvec_of_regval :: " register_value \(Mtvec)option " where + " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )" +|" Mtvec_of_regval g__87 = ( None )" + + +(*val regval_of_Mtvec : Mtvec -> register_value*) + +definition regval_of_Mtvec :: " Mtvec \ register_value " where + " regval_of_Mtvec v = ( Regval_Mtvec v )" + + +(*val Privilege_of_regval : register_value -> maybe Privilege*) + +fun Privilege_of_regval :: " register_value \(Privilege)option " where + " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )" +|" Privilege_of_regval g__86 = ( None )" + + +(*val regval_of_Privilege : Privilege -> register_value*) + +definition regval_of_Privilege :: " Privilege \ register_value " where + " regval_of_Privilege v = ( Regval_Privilege v )" + + +(*val Sedeleg_of_regval : register_value -> maybe Sedeleg*) + +fun Sedeleg_of_regval :: " register_value \(Sedeleg)option " where + " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )" +|" Sedeleg_of_regval g__85 = ( None )" + + +(*val regval_of_Sedeleg : Sedeleg -> register_value*) + +definition regval_of_Sedeleg :: " Sedeleg \ register_value " where + " regval_of_Sedeleg v = ( Regval_Sedeleg v )" + + +(*val Sinterrupts_of_regval : register_value -> maybe Sinterrupts*) + +fun Sinterrupts_of_regval :: " register_value \(Sinterrupts)option " where + " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )" +|" Sinterrupts_of_regval g__84 = ( None )" + + +(*val regval_of_Sinterrupts : Sinterrupts -> register_value*) + +definition regval_of_Sinterrupts :: " Sinterrupts \ register_value " where + " regval_of_Sinterrupts v = ( Regval_Sinterrupts v )" + + +(*val TLB39_Entry_of_regval : register_value -> maybe TLB39_Entry*) + +fun TLB39_Entry_of_regval :: " register_value \(TLB39_Entry)option " where + " TLB39_Entry_of_regval (Regval_TLB39_Entry (v)) = ( Some v )" +|" TLB39_Entry_of_regval g__83 = ( None )" + + +(*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) + +definition regval_of_TLB39_Entry :: " TLB39_Entry \ register_value " where + " regval_of_TLB39_Entry v = ( Regval_TLB39_Entry v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__82 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \ register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " vector_of_regval of_regval1 = ( \x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \ register_value)\ int \ bool \ 'a list \ register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " list_of_regval of_regval1 = ( \x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \ register_value)\ 'a list \ register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \ 'a option)\ register_value \('a option)option " where + " option_of_regval of_regval1 = ( \x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \ register_value)\ 'a option \ register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition tlb39_ref :: "((regstate),(register_value),((TLB39_Entry)option))register_ref " where + " tlb39_ref = ( (| + name = (''tlb39''), + read_from = (\ s . (tlb39 s)), + write_to = (\ v s . (( s (| tlb39 := v |)))), + of_regval = (\ v . option_of_regval (\ v . TLB39_Entry_of_regval v) v), + regval_of = (\ v . regval_of_option (\ v . regval_of_TLB39_Entry v) v) |) )" + + +definition tselect_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " tselect_ref = ( (| + name = (''tselect''), + read_from = (\ s . (tselect s)), + write_to = (\ v s . (( s (| tselect := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition stval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " stval_ref = ( (| + name = (''stval''), + read_from = (\ s . (stval s)), + write_to = (\ v s . (( s (| stval := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition scause_ref :: "((regstate),(register_value),(Mcause))register_ref " where + " scause_ref = ( (| + name = (''scause''), + read_from = (\ s . (scause s)), + write_to = (\ v s . (( s (| scause := v |)))), + of_regval = (\ v . Mcause_of_regval v), + regval_of = (\ v . regval_of_Mcause v) |) )" + + +definition sepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " sepc_ref = ( (| + name = (''sepc''), + read_from = (\ s . (sepc s)), + write_to = (\ v s . (( s (| sepc := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition sscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " sscratch_ref = ( (| + name = (''sscratch''), + read_from = (\ s . (sscratch s)), + write_to = (\ v s . (( s (| sscratch := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition stvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where + " stvec_ref = ( (| + name = (''stvec''), + read_from = (\ s . (stvec s)), + write_to = (\ v s . (( s (| stvec := v |)))), + of_regval = (\ v . Mtvec_of_regval v), + regval_of = (\ v . regval_of_Mtvec v) |) )" + + +definition satp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " satp_ref = ( (| + name = (''satp''), + read_from = (\ s . (satp s)), + write_to = (\ v s . (( s (| satp := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition sideleg_ref :: "((regstate),(register_value),(Sinterrupts))register_ref " where + " sideleg_ref = ( (| + name = (''sideleg''), + read_from = (\ s . (sideleg s)), + write_to = (\ v s . (( s (| sideleg := v |)))), + of_regval = (\ v . Sinterrupts_of_regval v), + regval_of = (\ v . regval_of_Sinterrupts v) |) )" + + +definition sedeleg_ref :: "((regstate),(register_value),(Sedeleg))register_ref " where + " sedeleg_ref = ( (| + name = (''sedeleg''), + read_from = (\ s . (sedeleg s)), + write_to = (\ v s . (( s (| sedeleg := v |)))), + of_regval = (\ v . Sedeleg_of_regval v), + regval_of = (\ v . regval_of_Sedeleg v) |) )" + + +definition pmpcfg0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " pmpcfg0_ref = ( (| + name = (''pmpcfg0''), + read_from = (\ s . (pmpcfg0 s)), + write_to = (\ v s . (( s (| pmpcfg0 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition pmpaddr0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " pmpaddr0_ref = ( (| + name = (''pmpaddr0''), + read_from = (\ s . (pmpaddr0 s)), + write_to = (\ v s . (( s (| pmpaddr0 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mhartid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mhartid_ref = ( (| + name = (''mhartid''), + read_from = (\ s . (mhartid s)), + write_to = (\ v s . (( s (| mhartid := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition marchid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " marchid_ref = ( (| + name = (''marchid''), + read_from = (\ s . (marchid s)), + write_to = (\ v s . (( s (| marchid := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mimpid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mimpid_ref = ( (| + name = (''mimpid''), + read_from = (\ s . (mimpid s)), + write_to = (\ v s . (( s (| mimpid := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mvendorid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mvendorid_ref = ( (| + name = (''mvendorid''), + read_from = (\ s . (mvendorid s)), + write_to = (\ v s . (( s (| mvendorid := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition minstret_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " minstret_ref = ( (| + name = (''minstret''), + read_from = (\ s . (minstret s)), + write_to = (\ v s . (( s (| minstret := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mtime_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mtime_ref = ( (| + name = (''mtime''), + read_from = (\ s . (mtime s)), + write_to = (\ v s . (( s (| mtime := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mcycle_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mcycle_ref = ( (| + name = (''mcycle''), + read_from = (\ s . (mcycle s)), + write_to = (\ v s . (( s (| mcycle := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mscratch_ref = ( (| + name = (''mscratch''), + read_from = (\ s . (mscratch s)), + write_to = (\ v s . (( s (| mscratch := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mtval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mtval_ref = ( (| + name = (''mtval''), + read_from = (\ s . (mtval s)), + write_to = (\ v s . (( s (| mtval := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mepc_ref = ( (| + name = (''mepc''), + read_from = (\ s . (mepc s)), + write_to = (\ v s . (( s (| mepc := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition mcause_ref :: "((regstate),(register_value),(Mcause))register_ref " where + " mcause_ref = ( (| + name = (''mcause''), + read_from = (\ s . (mcause s)), + write_to = (\ v s . (( s (| mcause := v |)))), + of_regval = (\ v . Mcause_of_regval v), + regval_of = (\ v . regval_of_Mcause v) |) )" + + +definition mtvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where + " mtvec_ref = ( (| + name = (''mtvec''), + read_from = (\ s . (mtvec s)), + write_to = (\ v s . (( s (| mtvec := v |)))), + of_regval = (\ v . Mtvec_of_regval v), + regval_of = (\ v . regval_of_Mtvec v) |) )" + + +definition medeleg_ref :: "((regstate),(register_value),(Medeleg))register_ref " where + " medeleg_ref = ( (| + name = (''medeleg''), + read_from = (\ s . (medeleg s)), + write_to = (\ v s . (( s (| medeleg := v |)))), + of_regval = (\ v . Medeleg_of_regval v), + regval_of = (\ v . regval_of_Medeleg v) |) )" + + +definition mideleg_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mideleg_ref = ( (| + name = (''mideleg''), + read_from = (\ s . (mideleg s)), + write_to = (\ v s . (( s (| mideleg := v |)))), + of_regval = (\ v . Minterrupts_of_regval v), + regval_of = (\ v . regval_of_Minterrupts v) |) )" + + +definition mie_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mie_ref = ( (| + name = (''mie''), + read_from = (\ s . (mie s)), + write_to = (\ v s . (( s (| mie := v |)))), + of_regval = (\ v . Minterrupts_of_regval v), + regval_of = (\ v . regval_of_Minterrupts v) |) )" + + +definition mip_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mip_ref = ( (| + name = (''mip''), + read_from = (\ s . (mip s)), + write_to = (\ v s . (( s (| mip := v |)))), + of_regval = (\ v . Minterrupts_of_regval v), + regval_of = (\ v . regval_of_Minterrupts v) |) )" + + +definition mstatus_ref :: "((regstate),(register_value),(Mstatus))register_ref " where + " mstatus_ref = ( (| + name = (''mstatus''), + read_from = (\ s . (mstatus s)), + write_to = (\ v s . (( s (| mstatus := v |)))), + of_regval = (\ v . Mstatus_of_regval v), + regval_of = (\ v . regval_of_Mstatus v) |) )" + + +definition misa_ref :: "((regstate),(register_value),(Misa))register_ref " where + " misa_ref = ( (| + name = (''misa''), + read_from = (\ s . (misa s)), + write_to = (\ v s . (( s (| misa := v |)))), + of_regval = (\ v . Misa_of_regval v), + regval_of = (\ v . regval_of_Misa v) |) )" + + +definition cur_inst_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " cur_inst_ref = ( (| + name = (''cur_inst''), + read_from = (\ s . (cur_inst s)), + write_to = (\ v s . (( s (| cur_inst := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition cur_privilege_ref :: "((regstate),(register_value),(Privilege))register_ref " where + " cur_privilege_ref = ( (| + name = (''cur_privilege''), + read_from = (\ s . (cur_privilege s)), + write_to = (\ v s . (( s (| cur_privilege := v |)))), + of_regval = (\ v . Privilege_of_regval v), + regval_of = (\ v . regval_of_Privilege v) |) )" + + +definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " Xs_ref = ( (| + name = (''Xs''), + read_from = (\ s . (Xs s)), + write_to = (\ v s . (( s (| Xs := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\ s . (nextPC s)), + write_to = (\ v s . (( s (| nextPC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\ s . (PC s)), + write_to = (\ v s . (( s (| PC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \ regstate \(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''tlb39'') then Some ((regval_of tlb39_ref) ((read_from tlb39_ref) s)) else + if reg_name = (''tselect'') then Some ((regval_of tselect_ref) ((read_from tselect_ref) s)) else + if reg_name = (''stval'') then Some ((regval_of stval_ref) ((read_from stval_ref) s)) else + if reg_name = (''scause'') then Some ((regval_of scause_ref) ((read_from scause_ref) s)) else + if reg_name = (''sepc'') then Some ((regval_of sepc_ref) ((read_from sepc_ref) s)) else + if reg_name = (''sscratch'') then Some ((regval_of sscratch_ref) ((read_from sscratch_ref) s)) else + if reg_name = (''stvec'') then Some ((regval_of stvec_ref) ((read_from stvec_ref) s)) else + if reg_name = (''satp'') then Some ((regval_of satp_ref) ((read_from satp_ref) s)) else + if reg_name = (''sideleg'') then Some ((regval_of sideleg_ref) ((read_from sideleg_ref) s)) else + if reg_name = (''sedeleg'') then Some ((regval_of sedeleg_ref) ((read_from sedeleg_ref) s)) else + if reg_name = (''pmpcfg0'') then Some ((regval_of pmpcfg0_ref) ((read_from pmpcfg0_ref) s)) else + if reg_name = (''pmpaddr0'') then Some ((regval_of pmpaddr0_ref) ((read_from pmpaddr0_ref) s)) else + if reg_name = (''mhartid'') then Some ((regval_of mhartid_ref) ((read_from mhartid_ref) s)) else + if reg_name = (''marchid'') then Some ((regval_of marchid_ref) ((read_from marchid_ref) s)) else + if reg_name = (''mimpid'') then Some ((regval_of mimpid_ref) ((read_from mimpid_ref) s)) else + if reg_name = (''mvendorid'') then Some ((regval_of mvendorid_ref) ((read_from mvendorid_ref) s)) else + if reg_name = (''minstret'') then Some ((regval_of minstret_ref) ((read_from minstret_ref) s)) else + if reg_name = (''mtime'') then Some ((regval_of mtime_ref) ((read_from mtime_ref) s)) else + if reg_name = (''mcycle'') then Some ((regval_of mcycle_ref) ((read_from mcycle_ref) s)) else + if reg_name = (''mscratch'') then Some ((regval_of mscratch_ref) ((read_from mscratch_ref) s)) else + if reg_name = (''mtval'') then Some ((regval_of mtval_ref) ((read_from mtval_ref) s)) else + if reg_name = (''mepc'') then Some ((regval_of mepc_ref) ((read_from mepc_ref) s)) else + if reg_name = (''mcause'') then Some ((regval_of mcause_ref) ((read_from mcause_ref) s)) else + if reg_name = (''mtvec'') then Some ((regval_of mtvec_ref) ((read_from mtvec_ref) s)) else + if reg_name = (''medeleg'') then Some ((regval_of medeleg_ref) ((read_from medeleg_ref) s)) else + if reg_name = (''mideleg'') then Some ((regval_of mideleg_ref) ((read_from mideleg_ref) s)) else + if reg_name = (''mie'') then Some ((regval_of mie_ref) ((read_from mie_ref) s)) else + if reg_name = (''mip'') then Some ((regval_of mip_ref) ((read_from mip_ref) s)) else + if reg_name = (''mstatus'') then Some ((regval_of mstatus_ref) ((read_from mstatus_ref) s)) else + if reg_name = (''misa'') then Some ((regval_of misa_ref) ((read_from misa_ref) s)) else + if reg_name = (''cur_inst'') then Some ((regval_of cur_inst_ref) ((read_from cur_inst_ref) s)) else + if reg_name = (''cur_privilege'') then Some ((regval_of cur_privilege_ref) ((read_from cur_privilege_ref) s)) else + if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \ register_value \ regstate \(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''tlb39'') then map_option (\ v . (write_to tlb39_ref) v s) ((of_regval tlb39_ref) v) else + if reg_name = (''tselect'') then map_option (\ v . (write_to tselect_ref) v s) ((of_regval tselect_ref) v) else + if reg_name = (''stval'') then map_option (\ v . (write_to stval_ref) v s) ((of_regval stval_ref) v) else + if reg_name = (''scause'') then map_option (\ v . (write_to scause_ref) v s) ((of_regval scause_ref) v) else + if reg_name = (''sepc'') then map_option (\ v . (write_to sepc_ref) v s) ((of_regval sepc_ref) v) else + if reg_name = (''sscratch'') then map_option (\ v . (write_to sscratch_ref) v s) ((of_regval sscratch_ref) v) else + if reg_name = (''stvec'') then map_option (\ v . (write_to stvec_ref) v s) ((of_regval stvec_ref) v) else + if reg_name = (''satp'') then map_option (\ v . (write_to satp_ref) v s) ((of_regval satp_ref) v) else + if reg_name = (''sideleg'') then map_option (\ v . (write_to sideleg_ref) v s) ((of_regval sideleg_ref) v) else + if reg_name = (''sedeleg'') then map_option (\ v . (write_to sedeleg_ref) v s) ((of_regval sedeleg_ref) v) else + if reg_name = (''pmpcfg0'') then map_option (\ v . (write_to pmpcfg0_ref) v s) ((of_regval pmpcfg0_ref) v) else + if reg_name = (''pmpaddr0'') then map_option (\ v . (write_to pmpaddr0_ref) v s) ((of_regval pmpaddr0_ref) v) else + if reg_name = (''mhartid'') then map_option (\ v . (write_to mhartid_ref) v s) ((of_regval mhartid_ref) v) else + if reg_name = (''marchid'') then map_option (\ v . (write_to marchid_ref) v s) ((of_regval marchid_ref) v) else + if reg_name = (''mimpid'') then map_option (\ v . (write_to mimpid_ref) v s) ((of_regval mimpid_ref) v) else + if reg_name = (''mvendorid'') then map_option (\ v . (write_to mvendorid_ref) v s) ((of_regval mvendorid_ref) v) else + if reg_name = (''minstret'') then map_option (\ v . (write_to minstret_ref) v s) ((of_regval minstret_ref) v) else + if reg_name = (''mtime'') then map_option (\ v . (write_to mtime_ref) v s) ((of_regval mtime_ref) v) else + if reg_name = (''mcycle'') then map_option (\ v . (write_to mcycle_ref) v s) ((of_regval mcycle_ref) v) else + if reg_name = (''mscratch'') then map_option (\ v . (write_to mscratch_ref) v s) ((of_regval mscratch_ref) v) else + if reg_name = (''mtval'') then map_option (\ v . (write_to mtval_ref) v s) ((of_regval mtval_ref) v) else + if reg_name = (''mepc'') then map_option (\ v . (write_to mepc_ref) v s) ((of_regval mepc_ref) v) else + if reg_name = (''mcause'') then map_option (\ v . (write_to mcause_ref) v s) ((of_regval mcause_ref) v) else + if reg_name = (''mtvec'') then map_option (\ v . (write_to mtvec_ref) v s) ((of_regval mtvec_ref) v) else + if reg_name = (''medeleg'') then map_option (\ v . (write_to medeleg_ref) v s) ((of_regval medeleg_ref) v) else + if reg_name = (''mideleg'') then map_option (\ v . (write_to mideleg_ref) v s) ((of_regval mideleg_ref) v) else + if reg_name = (''mie'') then map_option (\ v . (write_to mie_ref) v s) ((of_regval mie_ref) v) else + if reg_name = (''mip'') then map_option (\ v . (write_to mip_ref) v s) ((of_regval mip_ref) v) else + if reg_name = (''mstatus'') then map_option (\ v . (write_to mstatus_ref) v s) ((of_regval mstatus_ref) v) else + if reg_name = (''misa'') then map_option (\ v . (write_to misa_ref) v s) ((of_regval misa_ref) v) else + if reg_name = (''cur_inst'') then map_option (\ v . (write_to cur_inst_ref) v s) ((of_regval cur_inst_ref) v) else + if reg_name = (''cur_privilege'') then map_option (\ v . (write_to cur_privilege_ref) v s) ((of_regval cur_privilege_ref) v) else + if reg_name = (''Xs'') then map_option (\ v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else + if reg_name = (''nextPC'') then map_option (\ v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\ v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \ regstate \(register_value)option)*(string \ register_value \ regstate \(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end -- cgit v1.2.3 From c1ffcd56c941c3850d2de82a9011b3ae9b36a6d1 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Fri, 11 May 2018 15:48:26 +0100 Subject: Work around Lem generation problem in RISC-V "sum" is an existing constant in Isabelle, and the Lem constant avoiding mechanism does not seem to pick it up when used as the name of a function parameter. --- riscv/riscv_vmem.sail | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail index 7fddb047..4fb7b5d5 100644 --- a/riscv/riscv_vmem.sail +++ b/riscv/riscv_vmem.sail @@ -27,16 +27,16 @@ function isInvalidPTE(p : pteAttribs) -> bool = { a.V() == false | (a.W() == true & a.R() == false) } -function checkPTEPermission(ac : AccessType, priv : Privilege, mxr : bool, sum : bool, p : PTE_Bits) -> bool = { +function checkPTEPermission(ac : AccessType, priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits) -> bool = { match (ac, priv) { (Read, User) => p.U() == true & (p.R() == true | (p.X() == true & mxr)), (Write, User) => p.U() == true & p.W() == true, (ReadWrite, User) => p.U() == true & p.W() == true & (p.R() == true | (p.X() == true & mxr)), (Execute, User) => p.U() == true & p.X() == true, - (Read, Supervisor) => (p.U() == false | sum) & (p.R() == true | (p.X() == true & mxr)), - (Write, Supervisor) => (p.U() == false | sum) & p.W() == true, - (ReadWrite, Supervisor) => (p.U() == false | sum) & p.W() == true & (p.R() == true | (p.X() == true & mxr)), + (Read, Supervisor) => (p.U() == false | do_sum) & (p.R() == true | (p.X() == true & mxr)), + (Write, Supervisor) => (p.U() == false | do_sum) & p.W() == true, + (ReadWrite, Supervisor) => (p.U() == false | do_sum) & p.W() == true & (p.R() == true | (p.X() == true & mxr)), (Execute, Supervisor) => p.U() == false & p.X() == true, (_, Machine) => internal_error("m-mode mem perm check") @@ -126,7 +126,7 @@ union PTW_Result = { } val walk39 : (vaddr39, AccessType, Privilege, bool, bool, paddr39, nat, bool) -> PTW_Result effect {rmem, escape} -function walk39(vaddr, ac, priv, mxr, sum, ptb, level, global) -> PTW_Result = { +function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result = { let va = Mk_SV39_Vaddr(vaddr); let pt_ofs : paddr39 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]), PTE39_LOG_SIZE); @@ -147,10 +147,10 @@ function walk39(vaddr, ac, priv, mxr, sum, ptb, level, global) -> PTW_Result = { PTW_Failure(PTW_Invalid_PTE) } else { /* walk down the pointer to the next level */ - walk39(vaddr, ac, priv, mxr, sum, EXTZ(shiftl(pte.PPNi(), PAGESIZE_BITS)), level - 1, is_global) + walk39(vaddr, ac, priv, mxr, do_sum, EXTZ(shiftl(pte.PPNi(), PAGESIZE_BITS)), level - 1, is_global) } } else { /* leaf PTE */ - if ~ (checkPTEPermission(ac, priv, mxr, sum, pattr)) then { + if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then { PTW_Failure(PTW_No_Permission) } else { if level > 0 then { /* superpage */ @@ -259,12 +259,12 @@ union TR39_Result = { let enable_dirty_update = false val translate39 : (vaddr39, AccessType, Privilege, bool, bool, nat) -> TR39_Result effect {rreg, wreg, wmv, escape, rmem} -function translate39(vAddr, ac, priv, mxr, sum, level) = { +function translate39(vAddr, ac, priv, mxr, do_sum, level) = { let asid = curAsid64(); match lookupTLB39(asid, vAddr) { Some(idx, ent) => { let pteBits = Mk_PTE_Bits(ent.pte.BITS()); - if ~ (checkPTEPermission(ac, priv, mxr, sum, pteBits)) + if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pteBits)) then TR39_Failure(PTW_No_Permission) else { match update_PTE_Bits(pteBits, ac) { @@ -291,7 +291,7 @@ function translate39(vAddr, ac, priv, mxr, sum, level) = { } }, None() => { - match walk39(vAddr, ac, priv, mxr, sum, curPTB39(), level, false) { + match walk39(vAddr, ac, priv, mxr, do_sum, curPTB39(), level, false) { PTW_Failure(f) => TR39_Failure(f), PTW_Success(pAddr, pte, pteAddr, level, global) => { match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac) { @@ -360,11 +360,11 @@ function translateAddr(vAddr, ac, rt) = { else cur_privilege }; let mxr : bool = mstatus.MXR() == true; - let sum : bool = mstatus.SUM() == true; + let do_sum : bool = mstatus.SUM() == true; let mode : SATPMode = translationMode(effPriv); match mode { Sbare => TR_Address(vAddr), - SV39 => match translate39(vAddr[38 .. 0], ac, effPriv, mxr, sum, SV39_LEVELS - 1) { + SV39 => match translate39(vAddr[38 .. 0], ac, effPriv, mxr, do_sum, SV39_LEVELS - 1) { TR39_Address(pa) => TR_Address(EXTZ(pa)), TR39_Failure(f) => TR_Failure(translationException(ac, f)) }, -- cgit v1.2.3 From 10a6951c565c5da74ca5ff771ddc78b091601abb Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 16:45:22 +0100 Subject: More work on documentation Should have all the main language features covered in at least some detail now. --- doc/examples/exn.sail | 20 +++ doc/examples/my_replicate_bits.sail | 3 +- doc/examples/regref.sail | 17 +++ doc/manual.tex | 2 +- doc/riscv.tex | 15 +-- doc/tutorial.tex | 260 +++++++++++++++++++++++++++++++++--- doc/usage.tex | 2 +- 7 files changed, 288 insertions(+), 31 deletions(-) create mode 100644 doc/examples/exn.sail create mode 100644 doc/examples/regref.sail diff --git a/doc/examples/exn.sail b/doc/examples/exn.sail new file mode 100644 index 00000000..de97e3f9 --- /dev/null +++ b/doc/examples/exn.sail @@ -0,0 +1,20 @@ +val print = {ocaml: "print_endline"} : string -> unit + +scattered union exception + +union clause exception = Epair : (range(0, 255), range(0, 255)) + +union clause exception = Eunknown : string + +function main() : unit -> unit = { + try { + throw(Eunknown("foo")) + } catch { + Eunknown(msg) => print(msg), + _ => exit() + } +} + +union clause exception = Eint : int + +end exception diff --git a/doc/examples/my_replicate_bits.sail b/doc/examples/my_replicate_bits.sail index bd45a32d..c9972cd6 100644 --- a/doc/examples/my_replicate_bits.sail +++ b/doc/examples/my_replicate_bits.sail @@ -11,7 +11,8 @@ val "shiftl" : forall 'm. (bits('m), int) -> bits('m) val operator >> = { ocaml: "shiftr_ocaml", c: "shiftr_c", - lem: "shiftr_lem" + lem: "shiftr_lem", + _: "shiftr" } : forall 'm. (bits('m), int) -> bits('m) val "or_vec" : forall 'n. (bits('n), bits('n)) -> bits('n) diff --git a/doc/examples/regref.sail b/doc/examples/regref.sail new file mode 100644 index 00000000..268af295 --- /dev/null +++ b/doc/examples/regref.sail @@ -0,0 +1,17 @@ +default Order dec +$include + +register X0 : bits(8) +register X1 : bits(8) +register X2 : bits(8) + +let X : vector(3, dec, register(bits(8))) = [ref X2, ref X1, ref X0] + +function main() : unit -> unit = { + X0 = 0xFF; + assert(X0 == 0xFF); + (*X[0]) = 0x11; + assert(X0 == 0x11); + (*ref X0) = 0x00; + assert(X0 == 0x00) +} \ No newline at end of file diff --git a/doc/manual.tex b/doc/manual.tex index a52600a5..1148835e 100644 --- a/doc/manual.tex +++ b/doc/manual.tex @@ -25,7 +25,7 @@ \lstdefinelanguage{sail} { morekeywords={val,function,cast,type,forall,overload,operator,enum,union,undefined,exit,and,assert,sizeof, scattered,register,inc,dec,if,then,else,effect,let,as,@,in,end,Type,Int,Order,match,clause,struct, - foreach,from,to,by,infix,infixl,infixr,bitfield,default}, + foreach,from,to,by,infix,infixl,infixr,bitfield,default,try,catch,throw}, keywordstyle={\bf\ttfamily\color{blue}}, morestring=[b]", stringstyle={\ttfamily\color{red}}, diff --git a/doc/riscv.tex b/doc/riscv.tex index e2aa3025..1e50c90c 100644 --- a/doc/riscv.tex +++ b/doc/riscv.tex @@ -63,14 +63,13 @@ register Xs : vector(32, dec, xlen_t) \sailX We also give a function \ll{MEMr} for reading memory, this function -just points at a builtin we have defined elsewhere \TODO{Section where - we talk about preludes, built-in type environment etc}. Note that functions in sail are -annotated with effects. This effect system is quite basic, but -indicates whether or not functions read or write registers (rreg and -wreg), read and write memory (rmem and wmem), as well as a host of -other concurrency model related effects. They also indicate whether a -function throws exceptions or has other non-local control flow (the -escape effect). +just points at a builtin we have defined elsewhere. Note that +functions in sail are annotated with effects. This effect system is +quite basic, but indicates whether or not functions read or write +registers (rreg and wreg), read and write memory (rmem and wmem), as +well as a host of other concurrency model related effects. They also +indicate whether a function throws exceptions or has other non-local +control flow (the escape effect). \sailMEMr \sailfnMEMr diff --git a/doc/tutorial.tex b/doc/tutorial.tex index 98a06710..34046e2b 100644 --- a/doc/tutorial.tex +++ b/doc/tutorial.tex @@ -60,6 +60,31 @@ does not make any distinction between expressions and statements, so since there is only a single line of code within the foreach block, we can drop it and simply write: \mrbfnmyreplicatebitsthree +\subsection{External Bindings} + +Rather than defining functions within Sail itself, they can be mapped +onto functions definition within the various backend targets supported +by Sail. This is primarily used to setup the primitive functions +defined in the Sail library. These declarations work like much FFI +bindings in many programming languages---in Sail we provide the +\ll{val} declaration, except rather than giving a function body we +supply a string used to identify the external operator in each +backend. For example, we could link the \ll{>>} operator with the +\verb|shiftl| primitive as \mrbzeightoperatorzzerozIzIznine If the +external function has the same name as the sail function, such as +\ll{shiftl = "shiftl"}, then we can use the shorthand syntax +\mrbshiftl + +We can map onto differently-named operations for different targets by +using a JSON-like \ll{key: "value"} notation, for example: +\mrbzeightoperatorzzerozKzKznine We can also omit backends---in which +case those targets will expect a definition written in Sail. Note that +no checking is done to ensure that the definition in the target +matches the type of the Sail function. Finally, the \ll{_} key used +above is a wildcard that will be used for any backend not otherwise +included. If we use the wildcard key, then we cannot omit specific +backends to force them to use a definition in Sail. + \subsection{Numeric Types} \label{sec:numeric} @@ -95,7 +120,9 @@ Note that \ll{bit} isn't a numeric type (i.e. it's not \ll{range(0,1)}. This is intentional, as otherwise it would be possible to write expressions like \ll{(1 : bit) + 5} which would end up being equal to \ll{6 : range(5, 6)}. This kind of implicit casting -from bits to other numeric types would be highly undesirable. +from bits to other numeric types would be highly undesirable. The +\ll{bit} type itself is a two-element type with members \ll{bitzero} and +\ll{bitone}. \subsection{Vector Type} \label{sec:vec} @@ -236,6 +263,12 @@ Pattern matching can be used to destructure lists, see Section~\ref{sec:pat} \subsection{Other Types} +Sail also has a \ll{string} type, and a \ll{real} type. The \ll{real} +type is used to model arbitrary real numbers, so floating point +instructions could be specified by saying that they are equivalent to +mapping the floating point inputs to real numbers, performing the +arithmetic operation on the real numbers, and then mapping back to a +floating point value of the appropriate precision. \subsection{Pattern Matching} \label{sec:pat} @@ -307,6 +340,17 @@ somewhat ambiguous. This is the primary reason why we have the basic, but incomplete, pattern exhaustiveness check mentioned above---it can warn you if removing an enum constructor breaks a pattern match. +\paragraph{Matching on tuples} + +We use match to destructure tuple types, for example: +\begin{lstlisting} +let x : (int, int) = (2, 3) in +match x { + (y, z) => print("y = 2 and z = 3") +} + +\end{lstlisting} + \paragraph{Matching on unions} Match can also be used to destructure union constructors, for example @@ -443,10 +487,10 @@ assignment operator within a block. } \end{lstlisting} The assignment operator is the equality symbol, as in C and other -programming languages. Sail supports a rich language of -\emph{l-expression} forms, which can appear on the left of an -assignment. These will be described in Subsection~\ref{sec:lexp}. Note -that we could have written +programming languages. Sail supports a rich language of \emph{l-value} +forms, which can appear on the left of an assignment. These will be +described in Subsection~\ref{sec:lexp}. Note that we could have +written \begin{lstlisting} { x = 3; @@ -473,23 +517,130 @@ the variable \ll{x}, so would allow \ll{x} to be either 2 or 3, but not any other value. The \lstinline+{|2, 3|}+ syntax is equivalent to \lstinline+{'n, 'n in {2, 3}. int('n)}+. -\subsubsection{l-expressions} +\subsubsection{Assignment and l-values} \label{sec:lexp} -Sail allows for setter functions to be declared in a very simple way: -\ll{f(x) = y} is sugar for \ll{f(x, y)}. This feature is commonly used -when setting +It is common in ISA specifications to assign to complex l-values, +e.g.~to a subvector or named field of a bitvector register, or to an +l-value computed with some auxiliary function, e.g.~to select the +appropriate register for the current execution model. + +We have l-values that allow us to write to individual elements of a +vector: +\begin{lstlisting} +{ + v : bits(8) = 0xFF; + v[0] = bitzero; + assert(v == 0xFE) +} +\end{lstlisting} +as well as sub ranges of a vector: +\begin{lstlisting} +{ + v : bits(8) = 0xFF; + v[4 .. 0] = 0x0; // assume default Order dec + assert(v == 0xF0) +} +\end{lstlisting} +We also have vector concatenation l-values, which work much like +vector concatenation patterns +\begin{lstlisting} +{ + v1 : bits(4) = 0xF; + v2 : bits(4) = 0xF; + v1 @ v2 = 0xAB; + assert(v1 == 0xA & v2 == 0xB) +} +\end{lstlisting} +For structs we can write to an individual struct field as +\begin{lstlisting} +{ + s : S = struct { field = 0xFF } + s.field = 0x00 +} +\end{lstlisting} +assume we have a struct type \ll{S}, with a field simply called +\ll{field}. We can do multiple assignment using tuples, e.g. +\begin{lstlisting} +{ + (x, y) = (2, 3); + assert(x == 2 & x == 3) +} +\end{lstlisting} + +Finally, we allow functions to appear in l-values. This is a very +simple way to declare `setter' functions that look like custom +l-values, for example: +\begin{lstlisting} +{ + memory(addr) = 0x0F +} +\end{lstlisting} +This works because \ll{f(x) = y} is sugar for \ll{f(x, y)}. This +feature is commonly used when setting registers or memory that has +additional semantics for when they are read or written. We commonly +use the overloading feature to declare what appear to be getter/setter +pairs, so the above example we could implement a \ll{read_memory} +function and a \ll{write_memory} function and overload them both as +\ll{memory} to allow us to write memory using \ll{memory(addr) = data} +and read memory as \ll{data = memory(addr)}, as so: +\begin{lstlisting} +val read_memory : bits(64) -> bits(8) +val write_memory : (bits(64), bits(8)) -> unit + +overload memory = {read_memory, write_memory} +\end{lstlisting} +For more details on operator and function overloading see +Section~\ref{sec:overload}. + +\subsection{Registers} + +Registers can be declared with a top level +\begin{center} + \ll{register} \textit{name} \ll{:} \textit{type} +\end{center} +declaration. Registers are essentially top-level global variables and +can be set with the previously discussed l-expression forms. There is +currently no restriction on the type of a register in +Sail.\footnote{We may at some point want to enforce that they can be + mapped to bitvectors.} + +Registers differ from ordinary mutable variables as we can pass around +references to them by name. A reference to a register \ll{R} is +created as \ll{ref R}. If the register \ll{R} has the type \ll{A}, +then the type of \ll{ref R} will be \ll{register(A)}. There is a +dereferencing l-value operator \ll{*} for assigning to a register +reference. One use for register references is to create a list of +general purpose registers, so they can be indexed using numeric +variables. For example: +\lstinputlisting{examples/regref.sail} + +We can dereference register references using the \ll{"reg_deref"} +builtin (see Section~\ref{sec:prelude}), which is set up like so: +\begin{lstlisting} +val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg} +\end{lstlisting} +Currently there is no built-in syntactic sugar for dereferencing +registers in expressions. + +Unlike previous versions of Sail, referencing and de-referencing +registers is done explicitly, although we can use an automatic cast to +implictly dereference registers if that semantics is desired for a +specific specification that makes heavy use of register references, +like so: +\begin{lstlisting} +val cast auto_reg_deref = "reg_deref" : forall ('a : Type). register('a) -> a effect {rreg} +\end{lstlisting} -\fbox{TODO} \subsection{Type declarations} \subsubsection{Enumerations} -Enumerations can be defined in either a Haskell-like syntax -(useful for smaller enums) or a more traditional C-like syntax, which -is often more readable for enumerations with more members. There are -no lexical constraints on the identifiers that can be part of an +Enumerations can be defined in either a Haskell-like syntax (useful +for smaller enums) or a more traditional C-like syntax, which is often +more readable for enumerations with more members. There are no lexical +constraints on the identifiers that can be part of an enumeration. There are also no restrictions on the name of a enumeration type, other than it must be a valid identifier. For example, the following shows two ways to define the enumeration @@ -658,6 +809,7 @@ vector slicing. Operators used in types always share precedence with identically named operators at the expression level. \subsection{Ad-hoc Overloading} +\label{sec:overload} Sail has a flexible overloading mechanism using the \ll{overload} keyword @@ -736,14 +888,14 @@ so we can use this to define functions with optional arguments, e.g. \ll{sizeof}, see Section~\ref{sec:sizeof}) or we can provide it ourselves as an explicit argument. -\subsection{Getters and Setters} -\label{sec:getset} +%% \subsection{Getters and Setters} +%% \label{sec:getset} -We have already seen some examples of getters and setters in -Subsection~\ref{sec:bitfield}, but they can be used in many other -contexts. +%% We have already seen some examples of getters and setters in +%% Subsection~\ref{sec:bitfield}, but they can be used in many other +%% contexts. -\fbox{TODO} +%% \fbox{TODO} \subsection{Sizeof and Constraint} \label{sec:sizeof} @@ -793,8 +945,73 @@ otherwise not accessible at runtime, and so can be used to implement implicit arguments, as was seen for \ll{replicate_bits} in Section~\ref{sec:functions}. +\subsection{Scattered Definitions} +\label{sec:scattered} +In a Sail specification, sometimes it is desirable to collect together +the definitions relating to each machine instruction (or group +thereof), e.g.~grouping the clauses of an AST type with the associated +clauses of decode and execute functions, as in +Section~\ref{sec:riscv}. Sail permits this with syntactic sugar for +`scattered' definitions. Either functions or union types can be +scattered. + +One begins a scattered definition by declaring the name and kind +(either function or union) of the scattered definition, e.g. +\begin{lstlisting} +scattered function foo + +scattered union bar +\end{lstlisting} +This is then followed by a list of clauses for either the union or the +function, which can be freely interleaved with other definitions (such +as \ll{E} in the below code) +\begin{lstlisting}[mathescape] +union clause bar : Baz(int, int) + +function clause foo(Baz(x, y)) = $\ldots$ + +enum E = A | B | C + +union clause bar : Quux(string) + +function clause foo(Quux(str)) = print(str) +\end{lstlisting} +Finally the scattered definition is ended with the \ll{end} keyword, like so: +\begin{lstlisting} +end foo + +end bar +\end{lstlisting} + +Semantically, scattered definitions of union types appear at the start +of their definition, and scattered definitions of functions appear at +the end. A scattered function definition can be recursive, but +mutually recursive scattered function definitions should be avoided. + +\subsection{Exceptions} +\label{sec:exn} + +Perhaps suprisingly for a specification language, Sail has exception +support. This is because exceptions as a language feature do sometimes +appear in vendor ISA pseudocode, and such code would be very difficult +to translate into Sail if Sail did not itself support exceptions. We +already translate Sail to monadic theorem prover code, so working with +a monad that supports exceptions there is fairly natural. + +For exceptions we have two language features: \ll{throw} statements +and \ll{try}-\ll{catch} blocks. The throw keyword takes a value of +type \ll{exception} as an argument, which can be any user defined type +with that name. There is no builtin exception type, so to use +exceptions one must be set up on a per-project basis. Usually the +exception type will be a union, often a scattered union, which allows +for the exceptions to be declared throughout the specification as they +would be in OCaml, for example: \lstinputlisting{examples/exn.sail} +Note how the use of the scattered type allows additional exceptions to +be declared even after they are used. + \subsection{Preludes and Default Environment} \label{sec:prelude} + By default Sail has almost no built-in types or functions, except for the primitive types described in this Chapter. This is because different vendor-pseudocode's have varying naming conventions and @@ -834,4 +1051,7 @@ operations. These are listed below: the default order (which must be set before including this file). \item[smt.sail] Defines operators allowing div, mod, and abs to be used in types by exposing them to the Z3 SMT solver. + \item[exception\_basic.sail] Defines a trivial exception type, for + situations where you don't want to declare your own (see + Section~\ref{sec:exn}). \end{description} diff --git a/doc/usage.tex b/doc/usage.tex index 12095822..293d0587 100644 --- a/doc/usage.tex +++ b/doc/usage.tex @@ -21,7 +21,7 @@ definitions used in the rest of the specification and then specification. For more complex projects, once can use \ll{$include} statments in -Sail source, for example: \TODO{use \# like C} +Sail source, for example: \begin{lstlisting} $include $include "file.sail" -- cgit v1.2.3 From 13848ba495e79fcc6efe10cf7d98f68fa9453f29 Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 17:23:36 +0100 Subject: Add link to Thomas's Sail/Isabelle documentation in manual Replace the old manual with new version in repository root --- doc/manual.tex | 2 +- doc/types.tex | 2 ++ doc/usage.tex | 42 +++++++++++++++++++++++++++++++++--------- manual.pdf | Bin 939243 -> 403769 bytes 4 files changed, 36 insertions(+), 10 deletions(-) diff --git a/doc/manual.tex b/doc/manual.tex index 1148835e..1645f735 100644 --- a/doc/manual.tex +++ b/doc/manual.tex @@ -65,7 +65,7 @@ \title{The Sail instruction-set semantics specification language} \author{Kathryn E. Gray \and Peter Sewell \and Christopher Pulte \and - Shaked Flur \and Robert Norton-Wright \and Alasdair Armstrong} + Shaked Flur \and Robert Norton-Wright \and Alasdair Armstrong \and Thomas Bauereiss} \maketitle diff --git a/doc/types.tex b/doc/types.tex index 11037c91..a74cdea9 100644 --- a/doc/types.tex +++ b/doc/types.tex @@ -1,6 +1,8 @@ \section{Type System} \label{sec:types} +(This section is still a work in progress) + \newcommand{\tcheck}[3]{#1 \vdash #2 \Leftarrow #3} \newcommand{\tinfer}[3]{#1 \vdash #2 \Rightarrow #3} \newcommand{\msail}[1]{\text{\lstinline[mathescape]+#1+}} diff --git a/doc/usage.tex b/doc/usage.tex index 293d0587..3b8eed5f 100644 --- a/doc/usage.tex +++ b/doc/usage.tex @@ -38,7 +38,7 @@ AST is parsed~\footnote{This can affect precedence declarations for custom user \subsection{OCaml compilation} -To compile a sail specification into OCaml, one calls Sail as +To compile a Sail specification into OCaml, one calls Sail as \begin{verbatim} sail -ocaml FILES \end{verbatim} @@ -76,25 +76,46 @@ specification. In particular \verb+elf.sail+ defines a function correct location. ELF loading is done by the linksem library\footnote{\url{https://github.com/rems-project/linksem}}. -There is also an \verb+-ocaml_trace+ option which instruments the -generated OCaml code with tracing information this option implies \verb+-ocaml+. +There is also an \verb+-ocaml_trace+ option which is the same as +\verb+-ocaml+ except it instruments the generated OCaml code with +tracing information. -\subsection{C compilation} +%% \subsection{C compilation} -WIP but basically like OCaml +%% WIP but basically like OCaml -\subsection{Lem embedding} +\subsection{Lem and Isabelle} -\TODO{Document generating lem} +We have a separate document detailing how to generate Isabelle +theories from Sail models, and how to work with those models in +Isabelle, see: +\begin{center} +\url{https://github.com/rems-project/sail/raw/sail2/snapshots/isabelle/Manual.pdf} +\end{center} +Currently there are generated Isabelle snapshots for some of our +models in \verb+snapshots/isabelle+ in the Sail repository. These +snapshots are provided for convenience, and are not guaranteed to be +up-to-date. + +In order to open a theory of one of the specifications in Isabelle, +use the -l Sail command-line flag to load the session containing the +Sail library. Snapshots of the Sail and Lem libraries are in the +\verb+lib/sail+ and \verb+lib/lem+ directories, respectively. You can +tell Isabelle where to find them using the -d flag, as in +\begin{verbatim} +isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy +\end{verbatim} +When run from the \verb+snapshots/isabelle+ directory this will open +the RISC-V specification. \subsection{Interactive mode} -Compiling sail with +Compiling Sail with \begin{verbatim} make isail \end{verbatim} builds it with a GHCi-style interactive interpreter. This can be used -by starting Sail with \verb+sail -i+. If sail is not compiled with +by starting Sail with \verb+sail -i+. If Sail is not compiled with interactive support the \verb+-i+ flag does nothing. Sail will still handle any other command line arguments as per usual, including compiling to OCaml or Lem. One can also pass a list of commands to the @@ -127,6 +148,9 @@ indicated by starting with the letter d. improve typechecking times if you are repeatedly typechecking the same specification while developing it. +\item \verb+-no_lexp_bounds_check+ Turn off bounds checking in the left + hand side of assignments. + \item \verb+-no_effects+ Turn off effect checking. May break some backends that assume effects are properly checked. diff --git a/manual.pdf b/manual.pdf index 0c7ee474..2e501ffa 100644 Binary files a/manual.pdf and b/manual.pdf differ -- cgit v1.2.3 From 1763b8b5dceb614c04ccab83a8100268e0852626 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 10:16:23 +0100 Subject: Use type from funcl in singleton rewriting The pattern types may be subtypes, using those caused it to try rewriting int parameters and failing --- src/monomorphise.ml | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/monomorphise.ml b/src/monomorphise.ml index 0585d9fa..3af0b480 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -2241,13 +2241,16 @@ let rewrite_size_parameters env (Defs defs) = let open Rewriter in let open Util in - let sizes_funcl fsizes (FCL_aux (FCL_Funcl (id,pexp),(l,_))) = + let sizes_funcl fsizes (FCL_aux (FCL_Funcl (id,pexp),(l,ann))) = let pat,guard,exp,pannot = destruct_pexp pexp in - let parameters = match pat with - | P_aux (P_tup ps,_) -> ps - | _ -> [pat] + let env = env_of_annot (l,ann) in + let _, typ = Env.get_val_spec_orig id env in + let types = + match pat, Env.expand_synonyms env typ with + | P_aux (P_tup ps,_), Typ_aux (Typ_tup ts,_) -> ts + | _, _ -> [typ] in - let add_parameter (i,nmap) (P_aux (_,(_,Some (env,typ,_)))) = + let add_parameter (i,nmap) typ = let nmap = match Env.base_typ_of env typ with Typ_aux (Typ_app(Id_aux (Id "range",_), @@ -2262,8 +2265,13 @@ let rewrite_size_parameters env (Defs defs) = | _ -> nmap in (i+1,nmap) in - let (_,nexp_map) = List.fold_left add_parameter (0,NexpMap.empty) parameters in + let (_,nexp_map) = List.fold_left add_parameter (0,NexpMap.empty) types in let nexp_list = NexpMap.bindings nexp_map in +(* let () = + print_endline ("Type of pattern for " ^ string_of_id id ^": " ^string_of_typ (pat_typ_of pat)); + print_endline ("Nexp map for " ^ string_of_id id); + List.iter (fun (nexp, i) -> print_endline (" " ^ string_of_nexp nexp ^ " -> " ^ string_of_int i)) nexp_list +in *) let parameters_for = function | Some (env,typ,_) -> begin match Env.base_typ_of env typ with -- cgit v1.2.3 From 4c7507ae9d605bd3c1d3e6d2ca1e040f040705c8 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 11:00:25 +0100 Subject: Handle automatic existential unpacking in function application in mono analysis --- src/monomorphise.ml | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/src/monomorphise.ml b/src/monomorphise.ml index 3af0b480..48a7ac65 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -2704,12 +2704,10 @@ let kids_bound_by_pat pat = | ((s,p),ann) -> s, P_aux (p,ann)) }) pat) -(* Add bound variables from a pattern to the environment with the given dependency. *) +(* Diff the type environment to find new type variables and record that they + depend on deps *) -let update_env env deps pat typ_env_pre typ_env_post = - let bound = bindings_from_pat pat in - let var_deps = List.fold_left (fun ds v -> Bindings.add v deps ds) env.var_deps bound in - (* Diff the type environment to find the new variables *) +let update_env_new_kids env deps typ_env_pre typ_env_post = let kbound = KBindings.merge (fun k x y -> match x,y with @@ -2719,7 +2717,15 @@ let update_env env deps pat typ_env_pre typ_env_post = (Env.get_typ_vars typ_env_pre) in let kid_deps = KBindings.fold (fun v _ ds -> KBindings.add v deps ds) kbound env.kid_deps in - { env with var_deps = var_deps; kid_deps = kid_deps } + { env with kid_deps = kid_deps } + +(* Add bound variables from a pattern to the environment with the given dependency, + plus any new type variables. *) + +let update_env env deps pat typ_env_pre typ_env_post = + let bound = bindings_from_pat pat in + let var_deps = List.fold_left (fun ds v -> Bindings.add v deps ds) env.var_deps bound in + update_env_new_kids { env with var_deps = var_deps } deps typ_env_pre typ_env_post let assigned_vars_exps es = List.fold_left (fun vs exp -> IdSet.union vs (assigned_vars exp)) @@ -2894,6 +2900,30 @@ let rec analyse_exp fn_id env assigns (E_aux (e,(l,annot)) as exp) = let deps, _, rs = split3 (List.map (analyse_exp fn_id env assigns) es) in (deps, assigns, List.fold_left merge empty rs) in + (* We allow for arguments to functions being executed non-deterministically, but + follow the type checker in processing them in-order to detect the automatic + unpacking of existentials. When we spot a new type variable (using + update_env_new_kids) we set them to depend on the previous argument. *) + let non_det_args es = + let assigns = remove_assigns es " assigned in non-deterministic expressions" in + let rec aux prev_typ_env prev_deps env = function + | [] -> [], empty + | h::t -> + let typ_env = env_of h in + let env = update_env_new_kids env prev_deps prev_typ_env typ_env in + let new_deps, _, new_r = analyse_exp fn_id env assigns h in + let t_deps, t_r = aux typ_env new_deps env t in + new_deps::t_deps, merge new_r t_r + in + let deps, r = match es with + | [] -> [], empty + | h::t -> + let new_deps, _, new_r = analyse_exp fn_id env assigns h in + let t_deps, t_r = aux (env_of h) new_deps env t in + new_deps::t_deps, merge new_r t_r + in + (deps, assigns, r) + in let merge_deps deps = List.fold_left dmerge dempty deps in let deps, assigns, r = match e with @@ -2930,7 +2960,7 @@ let rec analyse_exp fn_id env assigns (E_aux (e,(l,annot)) as exp) = | E_lit _ -> (dempty,assigns,empty) | E_cast (_,e) -> analyse_exp fn_id env assigns e | E_app (id,args) -> - let deps, assigns, r = non_det args in + let deps, assigns, r = non_det_args args in let typ_env = env_of_annot (l,annot) in let (_,fn_typ) = Env.get_val_spec id typ_env in let fn_effect = match fn_typ with -- cgit v1.2.3 From 58b895c8c5c6f1c98370876c87bb4ac5b980f770 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 15:55:26 +0100 Subject: Be much more careful to introduce the right bitvector casts to the right sizes --- src/monomorphise.ml | 94 +++++++++++++++++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 35 deletions(-) diff --git a/src/monomorphise.ml b/src/monomorphise.ml index 48a7ac65..3f49689b 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -3810,10 +3810,21 @@ end module BitvectorSizeCasts = struct +let simplify_size_nexp env quant_kids (Nexp_aux (_,l) as nexp) = + match solve env nexp with + | Some n -> Some (nconstant n) + | None -> + let is_equal kid = + prove env (NC_aux (NC_equal (Nexp_aux (Nexp_var kid,Unknown), nexp),Unknown)) + in + match List.find is_equal quant_kids with + | kid -> Some (Nexp_aux (Nexp_var kid,Generated l)) + | exception Not_found -> None + (* These functions add cast functions across case splits, so that when a bitvector size becomes known in sail, the generated Lem code contains a function call to change mword 'n to (say) mword ty16, and vice versa. *) -let make_bitvector_cast_fns env src_typ target_typ = +let make_bitvector_cast_fns env quant_kids src_typ target_typ = let genunk = Generated Unknown in let fresh = let counter = ref 0 in @@ -3822,7 +3833,7 @@ let make_bitvector_cast_fns env src_typ target_typ = let () = counter := n+1 in mk_id ("cast#" ^ string_of_int n) in - let required = ref false in + let at_least_one = ref None in let rec aux (Typ_aux (src_t,src_l) as src_typ) (Typ_aux (tar_t,tar_l) as tar_typ) = let src_ann = Some (env,src_typ,no_effect) in let tar_ann = Some (env,tar_typ,no_effect) in @@ -3834,18 +3845,26 @@ let make_bitvector_cast_fns env src_typ target_typ = | Typ_app (Id_aux (Id "vector",_), [Typ_arg_aux (Typ_arg_nexp size,_); _; Typ_arg_aux (Typ_arg_typ (Typ_aux (Typ_id (Id_aux (Id "bit",_)),_)),_)]), - Typ_app (Id_aux (Id "vector",_), - [Typ_arg_aux (Typ_arg_nexp size',_); _; - Typ_arg_aux (Typ_arg_typ (Typ_aux (Typ_id (Id_aux (Id "bit",_)),_)),_)]) - when Nexp.compare size size' <> 0 -> - let () = required := true in - let var = fresh () in - P_aux (P_id var,(Generated src_l,src_ann)), - E_aux - (E_cast (tar_typ, - E_aux (E_app (Id_aux (Id "bitvector_cast", genunk), - [E_aux (E_id var, (genunk, src_ann))]), (genunk, tar_ann))), - (genunk, tar_ann)) + Typ_app (Id_aux (Id "vector",_) as t_id, + [Typ_arg_aux (Typ_arg_nexp size',l_size'); t_ord; + Typ_arg_aux (Typ_arg_typ (Typ_aux (Typ_id (Id_aux (Id "bit",_)),_)),_) as t_bit]) -> begin + match simplify_size_nexp env quant_kids size, simplify_size_nexp env quant_kids size' with + | Some size, Some size' when Nexp.compare size size' <> 0 -> + let var = fresh () in + let tar_typ' = Typ_aux (Typ_app (t_id, [Typ_arg_aux (Typ_arg_nexp size',l_size');t_ord;t_bit]), + tar_l) in + let () = at_least_one := Some tar_typ' in + P_aux (P_id var,(Generated src_l,src_ann)), + E_aux + (E_cast (tar_typ', + E_aux (E_app (Id_aux (Id "bitvector_cast", genunk), + [E_aux (E_id var, (genunk, src_ann))]), (genunk, tar_ann))), + (genunk, tar_ann)) + | _ -> + let var = fresh () in + P_aux (P_id var,(Generated src_l,src_ann)), + E_aux (E_id var,(Generated src_l,tar_ann)) + end | _ -> let var = fresh () in P_aux (P_id var,(Generated src_l,src_ann)), @@ -3854,8 +3873,8 @@ let make_bitvector_cast_fns env src_typ target_typ = let src_typ' = Env.base_typ_of env src_typ in let target_typ' = Env.base_typ_of env target_typ in let pat, e' = aux src_typ' target_typ' in - if !required - then + match !at_least_one with + | Some one_target_typ -> begin let src_ann = Some (env,src_typ,no_effect) in let tar_ann = Some (env,target_typ,no_effect) in match src_typ' with @@ -3863,12 +3882,12 @@ let make_bitvector_cast_fns env src_typ target_typ = | Typ_aux (Typ_app _,_) -> (fun var exp -> let exp_ann = Some (env,typ_of exp,effect_of exp) in - E_aux (E_let (LB_aux (LB_val (P_aux (P_typ (target_typ, P_aux (P_id var,(genunk,tar_ann))),(genunk,tar_ann)), + E_aux (E_let (LB_aux (LB_val (P_aux (P_typ (one_target_typ, P_aux (P_id var,(genunk,tar_ann))),(genunk,tar_ann)), E_aux (E_app (Id_aux (Id "bitvector_cast",genunk), [E_aux (E_id var,(genunk,src_ann))]),(genunk,tar_ann))),(genunk,tar_ann)), exp),(genunk,exp_ann))), (fun (E_aux (_,(exp_l,exp_ann)) as exp) -> - E_aux (E_cast (target_typ, + E_aux (E_cast (one_target_typ, E_aux (E_app (Id_aux (Id "bitvector_cast", genunk), [exp]), (Generated exp_l,tar_ann))), (Generated exp_l,tar_ann))) | _ -> @@ -3879,16 +3898,17 @@ let make_bitvector_cast_fns env src_typ target_typ = exp),(genunk,exp_ann))),(genunk,exp_ann))), (fun (E_aux (_,(exp_l,exp_ann)) as exp) -> E_aux (E_let (LB_aux (LB_val (pat, exp),(Generated exp_l,exp_ann)), e'),(Generated exp_l,tar_ann))) - else (fun _ e -> e),(fun e -> e) + end + | None -> (fun _ e -> e),(fun e -> e) (* TODO: bound vars *) -let make_bitvector_env_casts env (kid,i) exp = - let mk_cast var typ exp = (fst (make_bitvector_cast_fns env typ (subst_src_typ (KBindings.singleton kid (nconstant i)) typ))) var exp in +let make_bitvector_env_casts env quant_kids (kid,i) exp = + let mk_cast var typ exp = (fst (make_bitvector_cast_fns env quant_kids typ (subst_src_typ (KBindings.singleton kid (nconstant i)) typ))) var exp in let locals = Env.get_locals env in Bindings.fold (fun var (mut,typ) exp -> if mut = Immutable then mk_cast var typ exp else exp) locals exp -let make_bitvector_cast_exp typ target_typ exp = (snd (make_bitvector_cast_fns (env_of exp) typ target_typ)) exp +let make_bitvector_cast_exp env quant_kids typ target_typ exp = (snd (make_bitvector_cast_fns env quant_kids typ target_typ)) exp let rec extract_value_from_guard var (E_aux (e,_)) = match e with @@ -3909,14 +3929,14 @@ let fill_in_type env typ = | BK_type | BK_order -> subst | BK_int -> - match solve env (nvar kid) with + (match solve env (nvar kid) with | None -> subst - | Some n -> KBindings.add kid (nconstant n) subst) tyvars KBindings.empty in + | Some n -> KBindings.add kid (nconstant n) subst)) tyvars KBindings.empty in subst_src_typ subst typ (* TODO: top-level patterns *) let add_bitvector_casts (Defs defs) = - let rewrite_body ret_typ exp = + let rewrite_body id quant_kids top_env ret_typ exp = let rewrite_aux (e,ann) = match e with | E_case (E_aux (e',ann') as exp',cases) -> begin @@ -3931,16 +3951,17 @@ let add_bitvector_casts (Defs defs) = let body = match pat, guard with | P_aux (P_lit (L_aux (L_num i,_)),_), _ -> let src_typ = subst_src_typ (KBindings.singleton kid (nconstant i)) result_typ in - make_bitvector_cast_exp src_typ result_typ - (make_bitvector_env_casts env (kid,i) body) + make_bitvector_cast_exp env quant_kids src_typ result_typ + (make_bitvector_env_casts env quant_kids (kid,i) body) | P_aux (P_id var,_), Some guard -> (match extract_value_from_guard var guard with | Some i -> let src_typ = subst_src_typ (KBindings.singleton kid (nconstant i)) result_typ in - make_bitvector_cast_exp src_typ result_typ - (make_bitvector_env_casts env (kid,i) body) + make_bitvector_cast_exp env quant_kids src_typ result_typ + (make_bitvector_env_casts env quant_kids (kid,i) body) | None -> body) - | _ -> body + | _ -> + body in construct_pexp (pat, guard, body, ann) in @@ -3948,10 +3969,10 @@ let add_bitvector_casts (Defs defs) = | _ -> E_aux (e,ann) end | E_return e' -> - E_aux (E_return (make_bitvector_cast_exp (fill_in_type (env_of e') (typ_of e')) ret_typ e'),ann) + E_aux (E_return (make_bitvector_cast_exp top_env quant_kids (fill_in_type (env_of e') (typ_of e')) ret_typ e'),ann) | E_assign (LEXP_aux (lexp,lexp_annot),e') -> E_aux (E_assign (LEXP_aux (lexp,lexp_annot), - make_bitvector_cast_exp (fill_in_type (env_of e') (typ_of e')) + make_bitvector_cast_exp (env_of_annot ann) quant_kids (fill_in_type (env_of e') (typ_of e')) (typ_of_annot lexp_annot) e'),ann) | _ -> E_aux (e,ann) in @@ -3961,8 +3982,10 @@ let add_bitvector_casts (Defs defs) = e_aux = rewrite_aux } exp in let rewrite_funcl (FCL_aux (FCL_Funcl (id,pexp),fcl_ann)) = + let (tq,typ) = Env.get_val_spec_orig id (env_of_annot fcl_ann) in + let quant_kids = List.map kopt_kid (quant_kopts tq) in let ret_typ = - match typ_of_annot fcl_ann with + match typ with | Typ_aux (Typ_fn (_,ret,_),_) -> ret | Typ_aux (_,l) as typ -> raise (Reporting_basic.err_unreachable l @@ -3970,10 +3993,11 @@ let add_bitvector_casts (Defs defs) = " is not a function type")) in let pat,guard,body,annot = destruct_pexp pexp in - let body = rewrite_body ret_typ body in + let env = env_of body in + let body = rewrite_body id quant_kids env ret_typ body in (* Also add a cast around the entire function clause body, if necessary *) let body = - make_bitvector_cast_exp (fill_in_type (env_of body) (typ_of body)) ret_typ body + make_bitvector_cast_exp env quant_kids (fill_in_type (env_of body) (typ_of body)) ret_typ body in let pexp = construct_pexp (pat,guard,body,annot) in FCL_aux (FCL_Funcl (id,pexp),fcl_ann) -- cgit v1.2.3 From 7c0117f992fbe27ea0684b55cb7f39bd87393cdc Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 17:02:18 +0100 Subject: Actually use the correct type for singleton rewriting this time --- src/monomorphise.ml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/monomorphise.ml b/src/monomorphise.ml index 3f49689b..6dcd14ba 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -2245,6 +2245,10 @@ let rewrite_size_parameters env (Defs defs) = let pat,guard,exp,pannot = destruct_pexp pexp in let env = env_of_annot (l,ann) in let _, typ = Env.get_val_spec_orig id env in + let typ = match typ with + | Typ_aux (Typ_fn (arg_typ,_,_),_) -> arg_typ + | _ -> typ (* TODO: error *) + in let types = match pat, Env.expand_synonyms env typ with | P_aux (P_tup ps,_), Typ_aux (Typ_tup ts,_) -> ts @@ -2269,6 +2273,7 @@ let rewrite_size_parameters env (Defs defs) = let nexp_list = NexpMap.bindings nexp_map in (* let () = print_endline ("Type of pattern for " ^ string_of_id id ^": " ^string_of_typ (pat_typ_of pat)); + print_endline ("Types : " ^ String.concat ", " (List.map string_of_typ types)); print_endline ("Nexp map for " ^ string_of_id id); List.iter (fun (nexp, i) -> print_endline (" " ^ string_of_nexp nexp ^ " -> " ^ string_of_int i)) nexp_list in *) -- cgit v1.2.3 From d03a5adef64d66a49b69f1c9125e20c45e8b45b0 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 17:03:11 +0100 Subject: Make nexp simplification a little smarter (should really make the Lem pretty printer use the solver properly, but this is a useful stopgap) --- src/ast_util.ml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/ast_util.ml b/src/ast_util.ml index f7574b9d..968cb320 100644 --- a/src/ast_util.ml +++ b/src/ast_util.ml @@ -244,6 +244,13 @@ and nexp_simp_aux = function when Big_int.equal c1 (Big_int.negate c2) -> n | _, _ -> Nexp_minus (n1, n2) end + | Nexp_neg n -> + begin + let (Nexp_aux (n_simp, _) as n) = nexp_simp n in + match n_simp with + | Nexp_constant c -> Nexp_constant (Big_int.negate c) + | _ -> Nexp_neg n + end | Nexp_app (Id_aux (Id "div",_) as id,[n1;n2]) -> begin let (Nexp_aux (n1_simp, _) as n1) = nexp_simp n1 in -- cgit v1.2.3 From 3dd6497c7b70de1ac7c91a819f2dc46296715640 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 17:20:36 +0100 Subject: Temporary hacks for monomorphisation Mostly introducing type variables for regsize in valspecs --- aarch64/mono/demo/aarch64_no_vector/spec.sail | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/aarch64/mono/demo/aarch64_no_vector/spec.sail b/aarch64/mono/demo/aarch64_no_vector/spec.sail index 0bdd8f68..01b7660a 100644 --- a/aarch64/mono/demo/aarch64_no_vector/spec.sail +++ b/aarch64/mono/demo/aarch64_no_vector/spec.sail @@ -8818,9 +8818,9 @@ function memory_literal_general_decode (opc, V, imm19, Rt) = { aarch64_memory_literal_general(memop, offset, signed, 8 * size, t) } -val aarch64_memory_atomicops_swp : (int, AccType, int, int, int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_atomicops_swp : forall 'regsize. (int, AccType, int, atom('regsize), int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_atomicops_swp ('datasize, ldacctype, 'n, 'regsize, 's, stacctype, 't) = { +function aarch64_memory_atomicops_swp ('datasize, ldacctype, 'n, regsize, 's, stacctype, 't) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -8864,9 +8864,9 @@ function aarch64_memory_atomicops_st ('datasize, ldacctype, 'n, op, 's, stacctyp aset_Mem(address, datasize / 8, stacctype, result) } -val aarch64_memory_atomicops_ld : (int, AccType, int, MemAtomicOp, int, int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_atomicops_ld : forall 'regsize. (int, AccType, int, MemAtomicOp, atom('regsize), int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_atomicops_ld ('datasize, ldacctype, 'n, op, 'regsize, 's, stacctype, 't) = { +function aarch64_memory_atomicops_ld ('datasize, ldacctype, 'n, op, regsize, 's, stacctype, 't) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -8895,9 +8895,9 @@ function aarch64_memory_atomicops_ld ('datasize, ldacctype, 'n, op, 'regsize, 's aset_X(t, ZeroExtend(data, regsize)) } -val aarch64_memory_atomicops_cas_single : (int, AccType, int, int, int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_atomicops_cas_single : forall 'regsize. (int, AccType, int, atom('regsize), int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_atomicops_cas_single ('datasize, ldacctype, 'n, 'regsize, 's, stacctype, 't) = { +function aarch64_memory_atomicops_cas_single ('datasize, ldacctype, 'n, regsize, 's, stacctype, 't) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -8917,9 +8917,9 @@ function aarch64_memory_atomicops_cas_single ('datasize, ldacctype, 'n, 'regsize aset_X(s, ZeroExtend(data, regsize)) } -val aarch64_memory_atomicops_cas_pair : (int, AccType, int, int, int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_atomicops_cas_pair : forall 'regsize. (int, AccType, int, atom('regsize), int, AccType, int) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_atomicops_cas_pair ('datasize, ldacctype, 'n, 'regsize, 's, stacctype, 't) = { +function aarch64_memory_atomicops_cas_pair ('datasize, ldacctype, 'n, regsize, 's, stacctype, 't) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9198,9 +9198,9 @@ function system_exceptions_runtime_hvc_decode (opc, imm16, op2, LL) = { aarch64_system_exceptions_runtime_hvc(imm) } -val aarch64_memory_single_general_register : (AccType, int, ExtendType, int, MemOp, int, bool, int, int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_single_general_register : forall 'regsize. (AccType, int, ExtendType, int, MemOp, int, bool, atom('regsize), int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_single_general_register (acctype, 'datasize, extend_type, 'm, memop, 'n, postindex, 'regsize, 'shift, signed, 't, wback__arg) = { +function aarch64_memory_single_general_register (acctype, 'datasize, extend_type, 'm, memop, 'n, postindex, regsize, 'shift, signed, 't, wback__arg) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9254,9 +9254,9 @@ function aarch64_memory_single_general_register (acctype, 'datasize, extend_type } else () } -val aarch64_memory_single_general_immediate_unsigned : (AccType, int, MemOp, int, bits(64), bool, int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_single_general_immediate_unsigned : forall 'regsize. (AccType, int, MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_single_general_immediate_unsigned (acctype, 'datasize, memop, 'n, offset, postindex, 'regsize, signed, 't, wback__arg) = { +function aarch64_memory_single_general_immediate_unsigned (acctype, 'datasize, memop, 'n, offset, postindex, regsize, signed, 't, wback__arg) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9309,9 +9309,9 @@ function aarch64_memory_single_general_immediate_unsigned (acctype, 'datasize, m } else () } -val aarch64_memory_single_general_immediate_signed_postidx : (AccType, int, MemOp, int, bits(64), bool, int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_single_general_immediate_signed_postidx : forall 'regsize. (AccType, int, MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_single_general_immediate_signed_postidx (acctype, 'datasize, memop, 'n, offset, postindex, 'regsize, signed, 't, wback__arg) = { +function aarch64_memory_single_general_immediate_signed_postidx (acctype, 'datasize, memop, 'n, offset, postindex, regsize, signed, 't, wback__arg) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9396,9 +9396,9 @@ function aarch64_memory_single_general_immediate_signed_pac ('n, offset, 't, use } else () } -val aarch64_memory_single_general_immediate_signed_offset_unpriv : (AccType, int, MemOp, int, bits(64), bool, int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_single_general_immediate_signed_offset_unpriv : forall 'regsize. (AccType, int, MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_single_general_immediate_signed_offset_unpriv (acctype, 'datasize, memop, 'n, offset, postindex, 'regsize, signed, 't, wback__arg) = { +function aarch64_memory_single_general_immediate_signed_offset_unpriv (acctype, 'datasize, memop, 'n, offset, postindex, regsize, signed, 't, wback__arg) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9451,9 +9451,9 @@ function aarch64_memory_single_general_immediate_signed_offset_unpriv (acctype, } else () } -val aarch64_memory_single_general_immediate_signed_offset_normal : (AccType, int, MemOp, int, bits(64), bool, int, bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} +val aarch64_memory_single_general_immediate_signed_offset_normal : forall 'regsize. (AccType, int, MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} -function aarch64_memory_single_general_immediate_signed_offset_normal (acctype, 'datasize, memop, 'n, offset, postindex, 'regsize, signed, 't, wback__arg) = { +function aarch64_memory_single_general_immediate_signed_offset_normal (acctype, 'datasize, memop, 'n, offset, postindex, regsize, signed, 't, wback__arg) = { assert(constraint('regsize >= 0), "regsize constraint"); let 'dbytes = ex_int(datasize / 8); assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); @@ -9921,9 +9921,9 @@ function aarch64_memory_exclusive_pair (acctype, datasize, elsize, memop, n, pai }, MemOp_LOAD => { AArch64_SetExclusiveMonitors(address, dbytes); - if pair then + if pair then { + assert(constraint(- 'elsize + 'datasize > 0 & 'elsize >= 0), "datasize constraint"); if rt_unknown then aset_X(t, undefined : bits(32)) else if elsize == 32 then { - assert(constraint(- 'elsize + 'datasize > 0 & 'elsize >= 0), "datasize constraint"); data = aget_Mem(address, dbytes, acctype); if BigEndian() then { aset_X(t, slice(data, elsize, negate(elsize) + datasize)); @@ -9941,7 +9941,7 @@ function aarch64_memory_exclusive_pair (acctype, datasize, elsize, memop, n, pai aset_X(t, aget_Mem(address + 0, 8, acctype)); aset_X(t2, aget_Mem(address + 8, 8, acctype)) } - else { + } else { data = aget_Mem(address, dbytes, acctype); aset_X(t, ZeroExtend(data, regsize)) } -- cgit v1.2.3 From 8041ff0692b7f16a09afb36cd35199d5021e63b2 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 17:20:56 +0100 Subject: More builtin names in constant propagation --- src/monomorphise.ml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/monomorphise.ml b/src/monomorphise.ml index 6dcd14ba..4f257712 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -856,7 +856,7 @@ let try_app (l,ann) (id,args) = | [E_aux (E_lit L_aux (L_num i,_),_); E_aux (E_lit L_aux (L_num j,_),_)] -> Some (E_aux (E_lit (L_aux (L_num (Big_int.shift_left i (Big_int.to_int j)),new_l)),(l,ann))) | _ -> None - else if is_id "mult_int" || is_id "mult_range" then + else if is_id "mult_atom" || is_id "mult_int" || is_id "mult_range" then match args with | [E_aux (E_lit L_aux (L_num i,_),_); E_aux (E_lit L_aux (L_num j,_),_)] -> Some (E_aux (E_lit (L_aux (L_num (Big_int.mul i j),new_l)),(l,ann))) @@ -866,7 +866,7 @@ let try_app (l,ann) (id,args) = | [E_aux (E_lit L_aux (L_num i,_),_); E_aux (E_lit L_aux (L_num j,_),_)] -> Some (E_aux (E_lit (L_aux (L_num (Big_int.div i j),new_l)),(l,ann))) | _ -> None - else if is_id "add_range" then + else if is_id "add_atom" || is_id "add_int" || is_id "add_range" then match args with | [E_aux (E_lit L_aux (L_num i,_),_); E_aux (E_lit L_aux (L_num j,_),_)] -> Some (E_aux (E_lit (L_aux (L_num (Big_int.add i j),new_l)),(l,ann))) -- cgit v1.2.3 From 042caf8249e3d44d25e9bb94134cc2ef1b47084b Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 17:42:31 +0100 Subject: Update and alphabetise author list in manual --- doc/manual.tex | 5 +++-- manual.pdf | Bin 403769 -> 403774 bytes 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/manual.tex b/doc/manual.tex index 1645f735..3b75b26a 100644 --- a/doc/manual.tex +++ b/doc/manual.tex @@ -64,8 +64,9 @@ \title{The Sail instruction-set semantics specification language} -\author{Kathryn E. Gray \and Peter Sewell \and Christopher Pulte \and - Shaked Flur \and Robert Norton-Wright \and Alasdair Armstrong \and Thomas Bauereiss} +\author{Alasdair Armstrong \and Thomas Bauereiss \and Brian Campbell \and + Shaked Flur \and Kathryn E. Gray \and Robert Norton-Wright \and Christopher Pulte \and + Peter Sewell} \maketitle diff --git a/manual.pdf b/manual.pdf index 2e501ffa..45715da7 100644 Binary files a/manual.pdf and b/manual.pdf differ -- cgit v1.2.3 From 2140f736dbc5094a5e77315fdb7ace40162a464e Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 17:45:11 +0100 Subject: Add missing document list example to repository --- doc/examples/list.sail | 1 + 1 file changed, 1 insertion(+) create mode 100644 doc/examples/list.sail diff --git a/doc/examples/list.sail b/doc/examples/list.sail new file mode 100644 index 00000000..4eaeb67a --- /dev/null +++ b/doc/examples/list.sail @@ -0,0 +1 @@ +let l : list(int) = 1 :: 2 :: 3 :: [||] \ No newline at end of file -- cgit v1.2.3 From 18550ec15e8ca25770ca6d9a58c9d754d9c9861e Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Fri, 11 May 2018 18:21:28 +0100 Subject: Add snapshot of HOL4 output for CHERI and RISC-V --- snapshots/hol4/README.md | 13 + snapshots/hol4/build | 5 + snapshots/hol4/clean | 5 + snapshots/hol4/lem/hol-lib/Holmakefile | 14 + snapshots/hol4/lem/hol-lib/lemLib.sml | 105 + snapshots/hol4/lem/hol-lib/lemScript.sml | 284 + .../hol4/lem/hol-lib/lem_assert_extraScript.sml | 46 + .../hol4/lem/hol-lib/lem_basic_classesScript.sml | 504 ++ snapshots/hol4/lem/hol-lib/lem_boolScript.sml | 75 + snapshots/hol4/lem/hol-lib/lem_eitherScript.sml | 83 + snapshots/hol4/lem/hol-lib/lem_functionScript.sml | 72 + .../hol4/lem/hol-lib/lem_function_extraScript.sml | 25 + snapshots/hol4/lem/hol-lib/lem_listScript.sml | 776 ++ .../hol4/lem/hol-lib/lem_list_extraScript.sml | 110 + .../hol4/lem/hol-lib/lem_machine_wordScript.sml | 433 + snapshots/hol4/lem/hol-lib/lem_mapScript.sml | 153 + snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml | 72 + snapshots/hol4/lem/hol-lib/lem_maybeScript.sml | 112 + .../hol4/lem/hol-lib/lem_maybe_extraScript.sml | 23 + snapshots/hol4/lem/hol-lib/lem_numScript.sml | 1317 +++ snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml | 34 + .../hol4/lem/hol-lib/lem_pervasivesScript.sml | 18 + .../lem/hol-lib/lem_pervasives_extraScript.sml | 16 + snapshots/hol4/lem/hol-lib/lem_relationScript.sml | 448 + snapshots/hol4/lem/hol-lib/lem_setScript.sml | 317 + snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml | 118 + .../hol4/lem/hol-lib/lem_set_helpersScript.sml | 47 + snapshots/hol4/lem/hol-lib/lem_showScript.sml | 85 + .../hol4/lem/hol-lib/lem_show_extraScript.sml | 67 + snapshots/hol4/lem/hol-lib/lem_sortingScript.sml | 107 + snapshots/hol4/lem/hol-lib/lem_stringScript.sml | 74 + .../hol4/lem/hol-lib/lem_string_extraScript.sml | 124 + snapshots/hol4/lem/hol-lib/lem_tupleScript.sml | 51 + snapshots/hol4/lem/hol-lib/lem_wordScript.sml | 1021 +++ snapshots/hol4/sail/cheri/Holmakefile | 11 + .../hol4/sail/cheri/cheri_sequentialScript.sml | 9255 ++++++++++++++++++++ .../sail/cheri/cheri_sequential_typesScript.sml | 2285 +++++ .../sail/cheri/mips_extras_sequentialScript.sml | 235 + snapshots/hol4/sail/lib/hol/Holmakefile | 27 + snapshots/hol4/sail/riscv/Holmakefile | 11 + .../sail/riscv/riscv_extras_sequentialScript.sml | 127 + .../sail/riscv/riscv_sequentialAuxiliaryScript.sml | 41 + .../hol4/sail/riscv/riscv_sequentialScript.sml | 7554 ++++++++++++++++ .../sail/riscv/riscv_sequential_typesScript.sml | 1078 +++ 44 files changed, 27378 insertions(+) create mode 100644 snapshots/hol4/README.md create mode 100755 snapshots/hol4/build create mode 100755 snapshots/hol4/clean create mode 100644 snapshots/hol4/lem/hol-lib/Holmakefile create mode 100644 snapshots/hol4/lem/hol-lib/lemLib.sml create mode 100644 snapshots/hol4/lem/hol-lib/lemScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_boolScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_eitherScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_functionScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_listScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_mapScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_maybeScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_numScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_relationScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_setScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_showScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_sortingScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_stringScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_tupleScript.sml create mode 100644 snapshots/hol4/lem/hol-lib/lem_wordScript.sml create mode 100644 snapshots/hol4/sail/cheri/Holmakefile create mode 100644 snapshots/hol4/sail/cheri/cheri_sequentialScript.sml create mode 100644 snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml create mode 100644 snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/Holmakefile create mode 100644 snapshots/hol4/sail/riscv/Holmakefile create mode 100644 snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml create mode 100644 snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml create mode 100644 snapshots/hol4/sail/riscv/riscv_sequentialScript.sml create mode 100644 snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md new file mode 100644 index 00000000..2a8208c9 --- /dev/null +++ b/snapshots/hol4/README.md @@ -0,0 +1,13 @@ +# Snapshot of HOL4 output for Sail CHERI and RISC-V models + +These theories are a snapshot of the generated files for the Sail +CHERI and RISC-V models, translated to HOL4 via Lem. These are all +accepted by the current source repository version of HOL4 (from +roughly 7th May 2018), although we have not done any further testing +of them yet. + +They were generated using the `cheri-mono` branch of Sail, and the +`hol-with-extra-types` branch of Lem, which currently contain some +changes that are not yet ready of the main branches of these projects. + +11th May 2018. diff --git a/snapshots/hol4/build b/snapshots/hol4/build new file mode 100755 index 00000000..2b8be130 --- /dev/null +++ b/snapshots/hol4/build @@ -0,0 +1,5 @@ +#!/bin/bash + +for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do + (cd $d; Holmake) +done diff --git a/snapshots/hol4/clean b/snapshots/hol4/clean new file mode 100755 index 00000000..f4301d3f --- /dev/null +++ b/snapshots/hol4/clean @@ -0,0 +1,5 @@ +#!/bin/bash + +for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do + (cd $d; Holmake cleanAll) +done diff --git a/snapshots/hol4/lem/hol-lib/Holmakefile b/snapshots/hol4/lem/hol-lib/Holmakefile new file mode 100644 index 00000000..0d07567c --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/Holmakefile @@ -0,0 +1,14 @@ +ifdef POLY +HOLHEAP_NAME = lemheap +EXTRA_CLEANS = $(HOLHEAP_NAME) $(HOLHEAP_NAME).o + +BARE_DEPS = lemLib lemTheory lem_pervasivesTheory lem_pervasives_extraTheory lem_stringTheory lem_wordTheory +DEPS = $(patsubst %,%.uo,$(BARE_DEPS)) + +.PHONY: all +all: $(HOLHEAP_NAME) + +$(HOLHEAP_NAME): $(DEPS) + rm -f $(HOLHEAP_NAME) + $(protect $(HOLDIR)/bin/buildheap) -o $@ $(BARE_DEPS) +endif diff --git a/snapshots/hol4/lem/hol-lib/lemLib.sml b/snapshots/hol4/lem/hol-lib/lemLib.sml new file mode 100644 index 00000000..93d06dc2 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lemLib.sml @@ -0,0 +1,105 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* *) +(* The Lem sources are copyright 2010-2013 *) +(* by the UK authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + + +structure lemLib = +struct + +open HolKernel Parse boolLib bossLib; +open lemTheory intReduce wordsLib; + +val run_interactive = ref false +val lem_conv_eval = computeLib.EVAL_CONV +val lem_conv_simp = SIMP_CONV (srw_ss()++permLib.PERM_ss) [] + + +val lem_convs = [lem_conv_eval, lem_conv_simp]; + + +datatype test_result = + Success + | Fail + | Unknown of term + + +fun lem_run_single_test (t:term) conv = +case total conv t of + NONE => NONE + | SOME thm => + if (can EQT_ELIM thm) then SOME Success else + if (can EQF_ELIM thm) then SOME Fail else + NONE +; + +fun lem_run_test t = + case Lib.get_first (lem_run_single_test t) lem_convs of + NONE => Unknown (rhs (concl (EVAL t))) + | SOME r => r + + +fun lem_assertion s t = +let + open PPBackEnd Parse; + fun terminal_print sty s = (if !run_interactive then print_with_style sty s else + Lib.with_flag (Parse.current_backend, PPBackEnd.vt100_terminal) (print_with_style sty) s); + val _ = print "Testing "; + val _ = terminal_print [FG LightBlue] s; + val _ = print ": ``"; + val _ = print_term t; + val _ = print ("`` "); + val result = lem_run_test t; + val _ = case result of + Success => terminal_print [FG Green] "OK\n" + | Fail => (terminal_print [FG OrangeRed] "FAILED\n"; + if (not (!run_interactive)) then Process.exit Process.failure else ()) + | Unknown t => (terminal_print [FG Yellow] "evaluation failed\n") +(* print_term t; + print "\n\n"*) +in + () +end; + +end diff --git a/snapshots/hol4/lem/hol-lib/lemScript.sml b/snapshots/hol4/lem/hol-lib/lemScript.sml new file mode 100644 index 00000000..d6bb1bc8 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lemScript.sml @@ -0,0 +1,284 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* *) +(* The Lem sources are copyright 2010-2013 *) +(* by the UK authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + +open finite_mapTheory finite_mapLib +open HolKernel Parse boolLib bossLib; +open pred_setSimps pred_setTheory +open finite_mapTheory +open set_relationTheory +open integerTheory intReduce quantHeuristicsLib; +open wordsTheory + +val _ = numLib.prefer_num(); + +(* From BasicProvers, for compatibility with older versions of HOL *) +fun subgoal q = Q.SUBGOAL_THEN q STRIP_ASSUME_TAC + +val _ = new_theory "lem" + +val failwith_def = Define `failwith (s:'a) = (ARB:'b)`; + +val set_CASE_def = zDefine ` + set_CASE s c_emp c_sing c_else = + (if s = {} then c_emp else ( + if (FINITE s /\ (CARD s = 1)) then c_sing (CHOICE s) else + c_else))` + +val set_CASE_emp = prove ( +``!c_emp c_sing c_else. set_CASE {} c_emp c_sing c_else = c_emp``, + SIMP_TAC std_ss [set_CASE_def]) + + + +val set_CASE_sing = prove ( +``!x c_emp c_sing c_else. set_CASE {x} c_emp c_sing c_else = c_sing x``, + SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def]) + + +val set_CASE_infinite = prove (``~(FINITE s) ==> (set_CASE s c_emp c_sing c_else = c_else)``, +REPEAT STRIP_TAC THEN +`~ (s = {})` by METIS_TAC [FINITE_EMPTY] THEN +ASM_SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def]) + +val set_CASE_else_two_elems = store_thm ("set_CASE_else_two_elems", +``(x1 IN s /\ x2 IN s /\ ~(x1 = x2)) ==> + (set_CASE s c_emp c_sing c_else = c_else)``, + +REPEAT STRIP_TAC THEN +Tactical.REVERSE (Cases_on `FINITE s`) THEN1 ( + ASM_SIMP_TAC std_ss [set_CASE_infinite] +) THEN + +`~(s = {})` by (PROVE_TAC [MEMBER_NOT_EMPTY]) THEN + +subgoal `2 <= CARD s` THEN1 ( + `CARD {x1; x2} = 2` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN + `{x1; x2} SUBSET s` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN + PROVE_TAC [CARD_SUBSET] +) THEN + +ASM_SIMP_TAC arith_ss [set_CASE_def]); + + +val set_CASE_else_1 = prove (``~(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = c_else)``, +REPEAT STRIP_TAC THEN +MATCH_MP_TAC set_CASE_else_two_elems THEN +ASM_SIMP_TAC (std_ss++PRED_SET_ss) []) + + +val set_CASE_else_2 = prove (``(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = set_CASE (x2 INSERT s) c_emp c_sing c_else)``, +SIMP_TAC (std_ss++PRED_SET_ss) []) + + +val set_CASE_REWRITES = save_thm ("set_CASE_REWRITES", + LIST_CONJ (map GEN_ALL [set_CASE_emp, set_CASE_sing, set_CASE_else_1, set_CASE_else_2, set_CASE_infinite])); + +val _ = export_rewrites ["set_CASE_REWRITES"] + + +val set_CASE_compute = store_thm ("set_CASE_compute", `` + (!c_sing c_emp c_else. set_CASE {} c_emp c_sing c_else = c_emp) /\ + (!x c_sing c_emp c_else. + set_CASE {x} c_emp c_sing c_else = c_sing x) /\ + (!x2 x1 s c_sing c_emp c_else. + x1 <> x2 ==> + (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else = + c_else)) /\ + (!x2 x1 s c_sing c_emp c_else. + (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else = + if (x1 = x2) then set_CASE (x2 INSERT s) c_emp c_sing c_else else c_else))``, +METIS_TAC[set_CASE_REWRITES]); + + +val SET_FILTER_def = zDefine ` + (SET_FILTER P s = ({e | e | (e IN s) /\ P e}))`; + +val SET_FILTER_REWRITES = store_thm ("SET_FILTER_REWRITES",`` + (!P. (SET_FILTER P {} = {})) /\ + (!P x s. P x ==> (SET_FILTER P (x INSERT s) = x INSERT (SET_FILTER P s))) /\ + (!P x s. (~(P x) ==> (SET_FILTER P (x INSERT s) = SET_FILTER P s)))``, + +SIMP_TAC (std_ss++PRED_SET_ss) [SET_FILTER_def, EXTENSION] THEN +METIS_TAC[]) + +val _ = export_rewrites ["SET_FILTER_REWRITES"] + + +val SET_FILTER_compute = store_thm ("SET_FILTER_compute",`` + (!P. (SET_FILTER P {} = {})) /\ + (!P x s. (SET_FILTER P (x INSERT s) = if P x then + x INSERT (SET_FILTER P s) else (SET_FILTER P s)))``, +METIS_TAC [SET_FILTER_REWRITES]) + + +val _ = computeLib.add_persistent_funs ["set_CASE_compute", "SET_FILTER_compute"] + + +val SET_SIGMA_def = zDefine + `SET_SIGMA P Q = { (x, y) | x IN P /\ y IN Q x }`; + +val SET_SIGMA_EMPTY = store_thm( + "SET_SIGMA_EMPTY", + ``!Q. SET_SIGMA {} Q = {}``, + SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION]); +val _ = export_rewrites ["SET_SIGMA_EMPTY"] +val _ = computeLib.add_persistent_funs ["SET_SIGMA_EMPTY"] + +val SET_SIGMA_INSERT_LEFT = store_thm( + "SET_SIGMA_INSERT_LEFT", + ``!P Q x. SET_SIGMA (x INSERT P) Q = + (IMAGE (\y. (x, y)) (Q x)) UNION (SET_SIGMA P Q)``, + SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION] THEN + METIS_TAC[]) +val _ = export_rewrites ["SET_SIGMA_INSERT_LEFT"] +val _ = computeLib.add_persistent_funs ["SET_SIGMA_INSERT_LEFT"] + + +val _ = computeLib.add_persistent_funs ["list.LIST_TO_SET"] + + +val FMAP_TO_SET_def = zDefine + `FMAP_TO_SET m = IMAGE (\k. (k, FAPPLY m k)) (FDOM m)`; + +val FMAP_TO_SET_FEMPTY = store_thm ("FMAP_TO_SET_FEMPTY", + ``FMAP_TO_SET FEMPTY = {}``, +SIMP_TAC std_ss [FMAP_TO_SET_def, FDOM_FEMPTY, IMAGE_EMPTY]); +val _ = export_rewrites ["FMAP_TO_SET_FEMPTY"] +val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FEMPTY"] + +val FMAP_TO_SET_FUPDATE = store_thm ("FMAP_TO_SET_FUPDATE", + ``FMAP_TO_SET (FUPDATE m (k, v)) = (k, v) INSERT (FMAP_TO_SET (m \\ k))``, +SIMP_TAC (std_ss ++ PRED_SET_ss) [FMAP_TO_SET_def, FDOM_FUPDATE, FAPPLY_FUPDATE_THM, EXTENSION, + FDOM_DOMSUB, DOMSUB_FAPPLY_THM] THEN +METIS_TAC[]); +val _ = export_rewrites ["FMAP_TO_SET_FUPDATE"] +val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FUPDATE"] + + +val IN_FMAP_TO_SET = store_thm ("IN_FMAP_TO_SET", + ``(k, v) IN FMAP_TO_SET m = (FLOOKUP m k = SOME v)``, +SIMP_TAC (std_ss++PRED_SET_ss) [FMAP_TO_SET_def, FLOOKUP_DEF] THEN +METIS_TAC[optionTheory.option_CLAUSES]) + +val FUPDATE_NEQ_FEMPTY = store_thm ("FUPDATE_NEQ_FEMPTY", ``(FUPDATE m (k, v) = FEMPTY) = F``, + SIMP_TAC (std_ss++PRED_SET_ss) [fmap_EXT, FDOM_FUPDATE, FDOM_FEMPTY]) +val _ = export_rewrites ["FUPDATE_NEQ_FEMPTY"] +val _ = computeLib.add_persistent_funs ["FUPDATE_NEQ_FEMPTY"] + +val FUPDATE_EQ_FUPDATE = store_thm ("FUPDATE_EQ_FUPDATE", + ``(FUPDATE m (k, v) = FUPDATE m' (k', v')) = + (k IN FDOM (FUPDATE m' (k', v')) /\ + (FUPDATE m' (k', v') ' k = v) /\ + (m \\ k = (FUPDATE m' (k', v') \\ k))) ``, + + EQ_TAC THEN STRIP_TAC THEN1 ( + POP_ASSUM (ASSUME_TAC o GSYM) THEN + ASM_REWRITE_TAC [] THEN + SIMP_TAC std_ss [FDOM_FUPDATE, IN_INSERT, FAPPLY_FUPDATE, DOMSUB_FUPDATE] + ) THEN + FULL_SIMP_TAC std_ss [fmap_EXT, EXTENSION, FDOM_DOMSUB, IN_DELETE, FDOM_FUPDATE, IN_INSERT, + DOMSUB_FAPPLY_THM, FAPPLY_FUPDATE_THM] THEN + METIS_TAC[] +) + +val _ = export_rewrites ["FUPDATE_EQ_FUPDATE"] +val _ = computeLib.add_persistent_funs ["FUPDATE_EQ_FUPDATE"] + + +val FEVERY_FUPDATE_DOMSUB = store_thm ("FEVERY_FUPDATE_DOMSUB", + ``(FEVERY P (FUPDATE m (k, v))) = (P (k, v) /\ FEVERY P (m \\ k))``, +SIMP_TAC std_ss [FEVERY_FUPDATE, fmap_domsub]); + +val _ = computeLib.add_persistent_funs ["finite_map.FRANGE_FEMPTY", "finite_map.FRANGE_FUPDATE_DOMSUB", + "finite_map.FEVERY_FEMPTY", "FEVERY_FUPDATE_DOMSUB"] + +val _ = computeLib.add_persistent_funs ["finite_map.o_f_FUPDATE", "finite_map.o_f_FEMPTY", + "finite_map.FCARD_FEMPTY", "finite_map.FCARD_FUPDATE"] + + + + + +val rcomp_empty_1 = store_thm ("rcomp_empty_1", + ``({} OO r) = {}``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION]) + +val rcomp_empty_2 = store_thm ("rcomp_empty_2", + ``(r OO {}) = {}``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION]) + +val rcomp_insert_compute = store_thm ("rcomp_insert_compute", + ``(r1 OO ((x, y) INSERT r2)) = ((r1 OO r2) UNION (IMAGE (\ xy'. (FST xy', y)) (SET_FILTER (\ xy'. SND xy' = x) r1)))``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rcomp_def, EXTENSION, SET_FILTER_def] THEN +METIS_TAC[]) + +val _ = computeLib.add_persistent_funs ["rcomp_insert_compute", "rcomp_empty_1", "rcomp_empty_2"] + + +val rrestrict_eval = store_thm ("rrestrict_eval", + ``rrestrict r s = SET_FILTER (\ (x, y). x IN s /\ y IN s) r``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rrestrict_def, EXTENSION, SET_FILTER_def]) + +val domain_eval = store_thm ("domain_eval", + ``domain r = IMAGE FST r``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [domain_def, EXTENSION]) + +val range_eval = store_thm ("range_eval", + ``range r = IMAGE SND r``, +SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [range_def, EXTENSION]) + +val _ = computeLib.add_persistent_funs ["rrestrict_eval", "domain_eval", "range_eval"] + +val w2int_def = Define `w2int (w : 'a word) = + let i1 = (w2n w) in + let i2 = (INT_MAX (:'a)) in + if i1 > i2 then (int_of_num i1 - (int_of_num (UINT_MAX (:'a)))) - 1 else int_of_num i1` + +val w2ui_def = Define `w2ui (w : 'a word) = int_of_num (w2n w)` + +val _ = Define `MAP_TO_LIST m = SET_TO_LIST (\(x, y). FAPPLY m x = y)` + +val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml new file mode 100644 index 00000000..7ef74237 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml @@ -0,0 +1,46 @@ +(*Generated by Lem from assert_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open stringTheory lemTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_assert_extra" + + +(*open import {ocaml} `Xstring`*) +(*open import {hol} `stringTheory` `lemTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------------------ *) +(* failing with a proper error message *) +(* ------------------------------------ *) + +(*val failwith: forall 'a. string -> 'a*) + +(* ------------------------------------ *) +(* failing without an error message *) +(* ------------------------------------ *) + +(*val fail : forall 'a. 'a*) +val _ = Define ` + ((fail:'a)= (failwith "fail"))`; + + +(* ------------------------------------- *) +(* assertions *) +(* ------------------------------------- *) + +(*val ensure : bool -> string -> unit*) +val _ = Define ` + ((ensure:bool -> string -> unit) test msg= + (if test then + () + else + failwith msg))`; + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml new file mode 100644 index 00000000..eba5f169 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml @@ -0,0 +1,504 @@ +(*Generated by Lem from basic_classes.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_basic_classes" + +(******************************************************************************) +(* Basic Type Classes *) +(******************************************************************************) + +(*open import Bool*) + +(*open import {coq} `Coq.Strings.Ascii`*) + +(* ========================================================================== *) +(* Equality *) +(* ========================================================================== *) + +(* Lem`s default equality (=) is defined by the following type-class Eq. + This typeclass should define equality on an abstract datatype 'a. It should + always coincide with the default equality of Coq, HOL and Isabelle. + For OCaml, it might be different, since abstract datatypes like sets + might have fancy equalities. *) + +(*class ( Eq 'a ) + val = [isEqual] : 'a -> 'a -> bool + val <> [isInequal] : 'a -> 'a -> bool +end*) + + +(* (=) should for all instances be an equivalence relation + The isEquivalence predicate of relations could be used here. + However, this would lead to a cyclic dependency. *) + +(* TODO: add later, once lemmata can be assigned to classes +lemma eq_equiv: ((forall x. (x = x)) && + (forall x y. (x = y) <-> (y = x)) && + (forall x y z. ((x = y) && (y = z)) --> (x = z))) +*) + +(* Structural equality *) + +(* Sometimes, it is also handy to be able to use structural equality. + This equality is mapped to the build-in equality of backends. This equality + differs significantly for each backend. For example, OCaml can`t check equality + of function types, whereas HOL can. When using structural equality, one should + know what one is doing. The only guarentee is that is behaves like + the native backend equality. + + A lengthy name for structural equality is used to discourage its direct use. + It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions + for equality *) +(*val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool*) + +(*val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool*) +(*let unsafe_structural_inequality x y= not (unsafe_structural_equality x y)*) + + +(* ========================================================================== *) +(* Orderings *) +(* ========================================================================== *) + +(* The type-class Ord represents total orders (also called linear orders) *) +val _ = Hol_datatype ` + ordering = LT | EQ | GT`; + + +val _ = Define ` + ((orderingIsLess:ordering -> bool) LT= T) +/\ ((orderingIsLess:ordering -> bool) _= F)`; + +val _ = Define ` + ((orderingIsGreater:ordering -> bool) GT= T) +/\ ((orderingIsGreater:ordering -> bool) _= F)`; + +val _ = Define ` + ((orderingIsEqual:ordering -> bool) EQ= T) +/\ ((orderingIsEqual:ordering -> bool) _= F)`; + + +val _ = Define ` + ((ordering_cases:ordering -> 'a -> 'a -> 'a -> 'a) r lt eq gt= + (if orderingIsLess r then lt else + if orderingIsEqual r then eq else gt))`; + + + +(*val orderingEqual : ordering -> ordering -> bool*) + +val _ = Hol_datatype ` +(* 'a *) Ord_class= <| + compare_method : 'a -> 'a -> ordering; + isLess_method : 'a -> 'a -> bool; + isLessEqual_method : 'a -> 'a -> bool; + isGreater_method : 'a -> 'a -> bool; + isGreaterEqual_method : 'a -> 'a -> bool +|>`; + + + +(* Ocaml provides default, polymorphic compare functions. Let's use them + as the default. However, because used perhaps in a typeclass they must be + defined for all targets. So, explicitly declare them as undefined for + all other targets. If explictly declare undefined, the type-checker won't complain and + an error will only be raised when trying to actually output the function for a certain + target. *) +(*val defaultCompare : forall 'a. 'a -> 'a -> ordering*) +(*val defaultLess : forall 'a. 'a -> 'a -> bool*) +(*val defaultLessEq : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreater : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreaterEq : forall 'a. 'a -> 'a -> bool*) + + +val _ = Define ` + ((genericCompare:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a -> 'a -> ordering) (less: 'a -> 'a -> bool) (equal: 'a -> 'a -> bool) (x : 'a) (y : 'a)= + (if less x y then + LT + else if equal x y then + EQ + else + GT))`; + + + +(* +(* compare should really be a total order *) +lemma ord_OK_1: ( + (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) && + (forall x y. (compare x y = LT) <-> (compare y x = GT))) + +lemma ord_OK_2: ( + (forall x y z. (x <= y) && (y <= z) --> (x <= z)) && + (forall x y. (x <= y) || (y <= x)) +) +*) + +(* let's derive a compare function from the Ord type-class *) +(*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*) +val _ = Define ` + ((ordCompare:'a Ord_class -> 'a -> 'a -> ordering)dict_Basic_classes_Ord_a x y= + (if ( dict_Basic_classes_Ord_a.isLess_method x y) then LT else + if (x = y) then EQ else GT))`; + + +val _ = Hol_datatype ` +(* 'a *) OrdMaxMin_class= <| + max_method : 'a -> 'a -> 'a; + min_method : 'a -> 'a -> 'a +|>`; + + +(*val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) +val _ = Define ` + ((minByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y= (if (le x y) then x else y))`; + + +(*val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) +val _ = Define ` + ((maxByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y= (if (le y x) then x else y))`; + + +(*val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +(*val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_var_dict:'a Ord_class -> 'a OrdMaxMin_class)dict_Basic_classes_Ord_a= (<| + + max_method := (maxByLessEqual + dict_Basic_classes_Ord_a.isLessEqual_method); + + min_method := (minByLessEqual + dict_Basic_classes_Ord_a.isLessEqual_method)|>))`; + + + +(* ========================================================================== *) +(* SetTypes *) +(* ========================================================================== *) + +(* Set implementations use often an order on the elements. This allows the OCaml implementation + to use trees for implementing them. At least, one needs to be able to check equality on sets. + One could use the Ord type-class for sets. However, defining a special typeclass is cleaner + and allows more flexibility. One can make e.g. sure, that this type-class is ignored for + backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate + the functions "<", "<=" ... *) + +(*class ( SetType 'a ) + val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering +end*) + +val _ = Define ` + ((boolCompare:bool -> bool -> ordering) T T= EQ) +/\ ((boolCompare:bool -> bool -> ordering) T F= GT) +/\ ((boolCompare:bool -> bool -> ordering) F T= LT) +/\ ((boolCompare:bool -> bool -> ordering) F F= EQ)`; + + +(* strings *) + +(*val charEqual : char -> char -> bool*) + +(*val stringEquality : string -> string -> bool*) + +(* pairs *) + +(*val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool*) +(*let pairEqual (a1, b1) (a2, b2)= (a1 = a2) && (b1 = b2)*) + +(*val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool*) + +(*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*) +val _ = Define ` + ((pairCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) -> 'a#'b -> 'a#'b -> ordering) cmpa cmpb (a1, b1) (a2, b2)= + ((case cmpa a1 a2 of + LT => LT + | GT => GT + | EQ => cmpb b1 b2 + )))`; + + +val _ = Define ` + ((pairLess:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)= (( + dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLess_method x2 y2))))`; + +val _ = Define ` + ((pairLessEq:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)= (( + dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLessEqual_method x2 y2))))`; + + +val _ = Define ` + ((pairGreater:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12= (pairLess + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`; + +val _ = Define ` + ((pairGreaterEq:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12= (pairLessEq + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_tup2_dict:'a Ord_class -> 'b Ord_class ->('a#'b)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b= (<| + + compare_method := (pairCompare + dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method); + + isLess_method := + (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a); + + isLessEqual_method := + (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a); + + isGreater_method := + (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b); + + isGreaterEqual_method := + (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b)|>))`; + + + +(* triples *) + +(*val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool*) +(*let tripleEqual (x1, x2, x3) (y1, y2, y3)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))*) + +(*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*) +val _ = Define ` + ((tripleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) -> 'a#'b#'c -> 'a#'b#'c -> ordering) cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2)= + (pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2))))`; + + +val _ = Define ` + ((tripleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)= (pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`; + +val _ = Define ` + ((tripleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)= (pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`; + + +val _ = Define ` + ((tripleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123= (tripleLess + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`; + +val _ = Define ` + ((tripleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123= (tripleLessEq + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_tup3_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class ->('a#'b#'c)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c= (<| + + compare_method := (tripleCompare + dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method); + + isLess_method := + (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c); + + isLessEqual_method := + (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c); + + isGreater_method := + (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a); + + isGreaterEqual_method := + (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a)|>))`; + + +(* quadruples *) + +(*val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool*) +(*let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))*) + +(*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*) +val _ = Define ` + ((quadrupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> ordering) cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2)))))`; + + +val _ = Define ` + ((quadrupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)= (pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`; + +val _ = Define ` + ((quadrupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)= (pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`; + + +val _ = Define ` + ((quadrupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234= (quadrupleLess + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`; + +val _ = Define ` + ((quadrupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234= (quadrupleLessEq + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_tup4_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class ->('a#'b#'c#'d)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d= (<| + + compare_method := (quadrupleCompare + dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method); + + isLess_method := + (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d); + + isLessEqual_method := + (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d); + + isGreater_method := + (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a); + + isGreaterEqual_method := + (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`; + + +(* quintuples *) + +(*val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool*) +(*let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))*) + +(*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*) +val _ = Define ` + ((quintupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> ordering) cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2))))))`; + + +val _ = Define ` + ((quintupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= (pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`; + +val _ = Define ` + ((quintupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= (pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`; + + +val _ = Define ` + ((quintupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345= (quintupleLess + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`; + +val _ = Define ` + ((quintupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345= (quintupleLessEq + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_tup5_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class ->('a#'b#'c#'d#'e)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e= (<| + + compare_method := (quintupleCompare + dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method dict_Basic_classes_Ord_e.compare_method); + + isLess_method := + (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e); + + isLessEqual_method := + (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e); + + isGreater_method := + (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a); + + isGreaterEqual_method := + (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a)|>))`; + + +(* sextuples *) + +(*val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool*) +(*let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))*) + +(*val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) -> + ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*) +val _ = Define ` + ((sextupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) ->('f -> 'f -> ordering) -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> ordering) cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2)))))))`; + + +val _ = Define ` + ((sextupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= (pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`; + +val _ = Define ` + ((sextupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= (pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`; + + +val _ = Define ` + ((sextupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456= (sextupleLess + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`; + +val _ = Define ` + ((sextupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456= (sextupleLessEq + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_tup6_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class ->('a#'b#'c#'d#'e#'f)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f= (<| + + compare_method := (sextupleCompare + dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method dict_Basic_classes_Ord_e.compare_method dict_Basic_classes_Ord_f.compare_method); + + isLess_method := + (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f); + + isLessEqual_method := + (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f); + + isGreater_method := + (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a); + + isGreaterEqual_method := + (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_boolScript.sml b/snapshots/hol4/lem/hol-lib/lem_boolScript.sml new file mode 100644 index 00000000..5e6aa09f --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_boolScript.sml @@ -0,0 +1,75 @@ +(*Generated by Lem from bool.lem.*) +open HolKernel Parse boolLib bossLib; +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_bool" + + + +(* The type bool is hard-coded, so are true and false *) + +(* ----------------------- *) +(* not *) +(* ----------------------- *) + +(*val not : bool -> bool*) +(*let not b= match b with + | true -> false + | false -> true +end*) + +(* ----------------------- *) +(* and *) +(* ----------------------- *) + +(*val && [and] : bool -> bool -> bool*) +(*let && b1 b2= match (b1, b2) with + | (true, true) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* or *) +(* ----------------------- *) + +(*val || [or] : bool -> bool -> bool*) +(*let || b1 b2= match (b1, b2) with + | (false, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* implication *) +(* ----------------------- *) + +(*val --> [imp] : bool -> bool -> bool*) +(*let --> b1 b2= match (b1, b2) with + | (true, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* equivalence *) +(* ----------------------- *) + +(*val <-> [equiv] : bool -> bool -> bool*) +(*let <-> b1 b2= match (b1, b2) with + | (true, true) -> true + | (false, false) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* xor *) +(* ----------------------- *) + +(*val xor : bool -> bool -> bool*) + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml new file mode 100644 index 00000000..15437410 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml @@ -0,0 +1,83 @@ +(*Generated by Lem from either.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_listTheory lem_tupleTheory sumTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_either" + + + +(*open import Bool Basic_classes List Tuple*) +(*open import {hol} `sumTheory`*) +(*open import {ocaml} `Either`*) + +(*type either 'a 'b + = Left of 'a + | Right of 'b*) + + +(* -------------------------------------------------------------------------- *) +(* Equality. *) +(* -------------------------------------------------------------------------- *) + +(*val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool*) +(*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*) + +val _ = Define ` + ((eitherEqualBy:('a -> 'a -> bool) ->('b -> 'b -> bool) ->('a,'b)sum ->('a,'b)sum -> bool) eql eqr (left: ('a, 'b) sum) (right: ('a, 'b) sum)= + ((case (left, right) of + (INL l, INL l') => eql l l' + | (INR r, INR r') => eqr r r' + | _ => F + )))`; + +(*let eitherEqual= eitherEqualBy (=) (=)*) + +val _ = Define ` + ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL x') (INL y')= (cmpa x' y')) +/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR x') (INR y')= (cmpb x' y')) +/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL _) (INR _)= LT) +/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR _) (INL _)= GT)`; + + + +(* -------------------------------------------------------------------------- *) +(* Utility functions. *) +(* -------------------------------------------------------------------------- *) + +(*val isLeft : forall 'a 'b. either 'a 'b -> bool*) + +(*val isRight : forall 'a 'b. either 'a 'b -> bool*) + + +(*val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c*) +(*let either fa fb x= match x with + | Left a -> fa a + | Right b -> fb b +end*) + + +(*val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)*) + val _ = Define ` + ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) ([])= ([], [])) +/\ ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) (x :: xs)= (( + let (ll, rl) = (SUM_PARTITION xs) in + (case x of + INL l => ((l::ll), rl) + | INR r => (ll, (r::rl)) + ) + )))`; + + + +(*val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a*) + + +(*val rights : forall 'a 'b. list (either 'a 'b) -> list 'b*) + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_functionScript.sml b/snapshots/hol4/lem/hol-lib/lem_functionScript.sml new file mode 100644 index 00000000..2f6f52b8 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_functionScript.sml @@ -0,0 +1,72 @@ +(*Generated by Lem from function.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_function" + +(******************************************************************************) +(* A library for common operations on functions *) +(******************************************************************************) + +(*open import Bool Basic_classes*) + +(*open import {coq} `Program.Basics`*) + +(* ----------------------- *) +(* identity function *) +(* ----------------------- *) + +(*val id : forall 'a. 'a -> 'a*) +(*let id x= x*) + + +(* ----------------------- *) +(* constant function *) +(* ----------------------- *) + +(*val const : forall 'a 'b. 'a -> 'b -> 'a*) + + +(* ----------------------- *) +(* function composition *) +(* ----------------------- *) + +(*val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)*) +(*let comb f g= (fun x -> f (g x))*) + + +(* ----------------------- *) +(* function application *) +(* ----------------------- *) + +(*val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)*) +(*let $ f= (fun x -> f x)*) + +(*val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b*) +(*let $> x f= f x*) + +(* ----------------------- *) +(* flipping argument order *) +(* ----------------------- *) + +(*val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)*) +(*let flip f= (fun x y -> f y x)*) + + +(* currying / uncurrying *) + +(*val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c*) +val _ = Define ` + ((curry:('a#'b -> 'c) -> 'a -> 'b -> 'c) f= (\ a b . f (a, b)))`; + + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) +val _ = Define ` + ((uncurry:('a -> 'b -> 'c) -> 'a#'b -> 'c) f (a,b)= (f a b))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml new file mode 100644 index 00000000..6543ef87 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml @@ -0,0 +1,25 @@ +(*Generated by Lem from function_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_maybeTheory lem_boolTheory lem_basic_classesTheory lem_numTheory lem_functionTheory lemTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_function_extra" + + + +(*open import Maybe Bool Basic_classes Num Function*) + +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* getting a unique value *) +(* ----------------------- *) + +(*val THE : forall 'a. ('a -> bool) -> Maybe.maybe 'a*) + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_listScript.sml b/snapshots/hol4/lem/hol-lib/lem_listScript.sml new file mode 100644 index 00000000..f2ba75d6 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_listScript.sml @@ -0,0 +1,776 @@ +(*Generated by Lem from list.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_functionTheory lem_tupleTheory lem_numTheory lemTheory listTheory rich_listTheory sortingTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_list" + + + +(*open import Bool Maybe Basic_classes Function Tuple Num*) + +(*open import {coq} `Coq.Lists.List`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) +(*open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`*) + +(* ========================================================================== *) +(* Basic list functions *) +(* ========================================================================== *) + +(* The type of lists as well as list literals like [], [1;2], ... are hardcoded. + Thus, we can directly dive into derived definitions. *) + + +(* ----------------------- *) +(* cons *) +(* ----------------------- *) + +(*val :: : forall 'a. 'a -> list 'a -> list 'a*) + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. list 'a -> bool*) +(*let null l= match l with [] -> true | _ -> false end*) + +(* ----------------------- *) +(* Length *) +(* ----------------------- *) + +(*val length : forall 'a. list 'a -> nat*) +(*let rec length l= + match l with + | [] -> 0 + | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1 + end*) + +(* ----------------------- *) +(* Equality *) +(* ----------------------- *) + +(*val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + + val _ = Define ` + ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) ([])= T) +/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) (_::_)= F) +/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (_::_) ([])= F) +/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x::xs) (y :: ys)= (eq x y /\ listEqualBy eq xs ys))`; + + + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> Basic_classes.ordering*) +(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a -> Basic_classes.ordering*) + + val _ = Define ` + ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) ([])= EQ) +/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) (_::_)= LT) +/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (_::_) ([])= GT) +/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (x::xs) (y::ys)= (( + (case cmp x y of + LT => LT + | GT => GT + | EQ => lexicographic_compare cmp xs ys + ) + )))`; + + +(*val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + val _ = Define ` + ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])= F) +/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)= T) +/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])= F) +/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)= ((less x y) \/ ((less_eq x y) /\ (lexicographic_less less less_eq xs ys))))`; + + +(*val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + val _ = Define ` + ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])= T) +/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)= T) +/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])= F) +/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)= (less x y \/ (less_eq x y /\ lexicographic_less_eq less less_eq xs ys)))`; + + + +val _ = Define ` +((instance_Basic_classes_Ord_list_dict:'a lem_basic_classes$Ord_class ->('a list)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<| + + compare_method := (lexicographic_compare + dict_Basic_classes_Ord_a.compare_method); + + isLess_method := (lexicographic_less + dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method); + + isLessEqual_method := (lexicographic_less_eq + dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method); + + isGreater_method := (\ x y. (lexicographic_less + dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method y x)); + + isGreaterEqual_method := (\ x y. (lexicographic_less_eq + dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method y x))|>))`; + + + +(* ----------------------- *) +(* Append *) +(* ----------------------- *) + +(*val ++ : forall 'a. list 'a -> list 'a -> list 'a*) (* originally append *) +(*let rec ++ xs ys= match xs with + | [] -> ys + | x :: xs' -> x :: (xs' ++ ys) + end*) + +(* ----------------------- *) +(* snoc *) +(* ----------------------- *) + +(*val snoc : forall 'a. 'a -> list 'a -> list 'a*) +(*let snoc e l= l ++ [e]*) + + +(* ----------------------- *) +(* Reverse *) +(* ----------------------- *) + +(* First lets define the function [reverse_append], which is + closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1]. + This can be implemented more efficienctly than appending and is + used to implement reverse. *) + +(*val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a*) (* originally named rev_append *) +(*let rec reverseAppend l1 l2= match l1 with + | [] -> l2 + | x :: xs -> reverseAppend xs (x :: l2) + end*) + +(* Reversing a list *) +(*val reverse : forall 'a. list 'a -> list 'a*) (* originally named rev *) +(*let reverse l= reverseAppend l []*) + +(* ----------------------- *) +(* Map *) +(* ----------------------- *) + +(*val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b*) + val map_tr_defn = Defn.Hol_multi_defns ` + ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f ([])= (REVERSE rev_acc)) +/\ ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f (x :: xs)= (map_tr ((f x) :: rev_acc) f xs))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) map_tr_defn; + +(* taken from: https://blogs.janestreet.com/optimizing-list-map/ *) +(*val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b*) + val count_map_defn = Defn.Hol_multi_defns ` + ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f ([]) ctr= ([])) +/\ ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f (hd :: tl) ctr= (f hd :: + (if ctr <( 5000 : num) then count_map f tl (ctr +( 1 : num)) + else map_tr [] f tl)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) count_map_defn; + +(*val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) +(*let map f l= count_map f l 0*) + +(* ----------------------- *) +(* Reverse Map *) +(* ----------------------- *) + +(*val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) + + +(* ========================================================================== *) +(* Folding *) +(* ========================================================================== *) + +(* ----------------------- *) +(* fold left *) +(* ----------------------- *) + +(*val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a*) (* originally foldl *) + +(*let rec foldl f b l= match l with + | [] -> b + | x :: xs -> foldl f (f b x) xs +end*) + + +(* ----------------------- *) +(* fold right *) +(* ----------------------- *) + +(*val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b*) (* originally foldr with different argument order *) +(*let rec foldr f b l= match l with + | [] -> b + | x :: xs -> f x (foldr f b xs) +end*) + + +(* ----------------------- *) +(* concatenating lists *) +(* ----------------------- *) + +(*val concat : forall 'a. list (list 'a) -> list 'a*) (* before also called "flatten" *) +(*let concat= foldr (++) []*) + + +(* -------------------------- *) +(* concatenating with mapping *) +(* -------------------------- *) + +(*val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b*) + + +(* ------------------------- *) +(* universal qualification *) +(* ------------------------- *) + +(*val all : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally for_all *) +(*let all P l= foldl (fun r e -> P e && r) true l*) + + + +(* ------------------------- *) +(* existential qualification *) +(* ------------------------- *) + +(*val any : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally exist *) +(*let any P l= foldl (fun r e -> P e || r) false l*) + + +(* ------------------------- *) +(* dest_init *) +(* ------------------------- *) + +(* get the initial part and the last element of the list in a safe way *) + +(*val dest_init : forall 'a. list 'a -> Maybe.maybe (list 'a * 'a)*) + + val _ = Define ` + ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen ([])= (REVERSE rev_init, last_elem_seen)) +/\ ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen (x::xs)= (dest_init_aux (last_elem_seen::rev_init) x xs))`; + + +val _ = Define ` + ((dest_init:'a list ->('a list#'a)option) ([])= NONE) +/\ ((dest_init:'a list ->('a list#'a)option) (x::xs)= (SOME (dest_init_aux [] x xs)))`; + + + +(* ========================================================================== *) +(* Indexing lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* index / nth with maybe *) +(* ------------------------- *) + +(*val index : forall 'a. list 'a -> nat -> Maybe.maybe 'a*) + + val _ = Define ` + ((list_index:'a list -> num -> 'a option) ([]) n= NONE) +/\ ((list_index:'a list -> num -> 'a option) (x :: xs) n= (if n =( 0 : num) then SOME x else list_index xs (n -( 1 : num))))`; + + +(* ------------------------- *) +(* findIndices *) +(* ------------------------- *) + +(* [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P]. + Counting starts with 0, the result list is sorted ascendingly *) +(*val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat*) + + val _ = Define ` + ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P ([])= ([])) +/\ ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P (x :: xs)= (if P x then i :: find_indices_aux (i +( 1 : num)) P xs else find_indices_aux (i +( 1 : num)) P xs))`; + +val _ = Define ` + ((find_indices:('a -> bool) -> 'a list ->(num)list) P l= (find_indices_aux(( 0 : num)) P l))`; + + + + +(* ------------------------- *) +(* findIndex *) +(* ------------------------- *) + +(* findIndex returns the first index of a list that satisfies a given predicate. *) +(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe nat*) +val _ = Define ` + ((find_index:('a -> bool) -> 'a list ->(num)option) P l= ((case find_indices P l of + [] => NONE + | x :: _ => SOME x +)))`; + + +(* ------------------------- *) +(* elemIndices *) +(* ------------------------- *) + +(*val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat*) + +(* ------------------------- *) +(* elemIndex *) +(* ------------------------- *) + +(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> Maybe.maybe nat*) + + +(* ========================================================================== *) +(* Creating lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* genlist *) +(* ------------------------- *) + +(* [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] *) +(*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*) + + +(*let rec genlist f n= + match n with + | 0 -> [] + | n' + 1 -> snoc (f n') (genlist f n') + end*) + + +(* ------------------------- *) +(* replicate *) +(* ------------------------- *) + +(*val replicate : forall 'a. nat -> 'a -> list 'a*) +(*let rec replicate n x= + match n with + | 0 -> [] + | n' + 1 -> x :: replicate n' x + end*) + + +(* ========================================================================== *) +(* Sublists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* splitAt *) +(* ------------------------- *) + +(* [splitAt n xs] returns a tuple (xs1, xs2), with "append xs1 xs2 = xs" and + "length xs1 = n". If there are not enough elements + in [xs], the original list and the empty one are returned. *) +(*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*) + val splitAtAcc_defn = Hol_defn "splitAtAcc" ` + ((splitAtAcc:'a list -> num -> 'a list -> 'a list#'a list) revAcc n l= + ((case l of + [] => (REVERSE revAcc, []) + | x::xs => if n <=( 0 : num) then (REVERSE revAcc, l) else splitAtAcc (x::revAcc) (n -( 1 : num)) xs + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn splitAtAcc_defn; + +(*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*) +(*let rec splitAt n l= + splitAtAcc [] n l*) + + +(* ------------------------- *) +(* take *) +(* ------------------------- *) + +(* take n xs returns the prefix of xs of length n, or xs itself if n > length xs *) +(*val take : forall 'a. nat -> list 'a -> list 'a*) +(*let take n l= fst (splitAt n l)*) + +(* ------------------------- *) +(* drop *) +(* ------------------------- *) + +(* [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. *) +(*val drop : forall 'a. nat -> list 'a -> list 'a*) +(*let drop n l= snd (splitAt n l)*) + +(* ------------------------------------ *) +(* splitWhile, takeWhile, and dropWhile *) +(* ------------------------------------ *) + +(*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*) + val _ = Define ` + ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p ([]) acc= + (REVERSE acc, [])) +/\ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p (x::xs) acc= + (if p x then + splitWhile_tr p xs (x::acc) + else + (REVERSE acc, (x::xs))))`; + + +(*val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)*) +val _ = Define ` + ((splitWhile:('a -> bool) -> 'a list -> 'a list#'a list) p xs= (splitWhile_tr p xs []))`; + + +(* [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. *) +(*val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +val _ = Define ` + ((takeWhile:('a -> bool) -> 'a list -> 'a list) p l= (FST (splitWhile p l)))`; + + +(* [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. *) +(*val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +val _ = Define ` + ((dropWhile:('a -> bool) -> 'a list -> 'a list) p l= (SND (splitWhile p l)))`; + + +(* ------------------------- *) +(* isPrefixOf *) +(* ------------------------- *) + +(*val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*let rec isPrefixOf l1 l2= match (l1, l2) with + | ([], _) -> true + | (_::_, []) -> false + | (x::xs, y::ys) -> (x = y) && isPrefixOf xs ys +end*) + +(* ------------------------- *) +(* update *) +(* ------------------------- *) +(*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*) +(*let rec update l n e= + match l with + | [] -> [] + | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e) +end*) + + + +(* ========================================================================== *) +(* Searching lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* Membership test *) +(* ------------------------- *) + +(* The membership test, one of the basic list functions, is actually tricky for + Lem, because it is tricky, which equality to use. From Lem`s point of + perspective, we want to use the equality provided by the equality type - class. + This allows for example to check whether a set is in a list of sets. + + However, in order to use the equality type class, elem essentially becomes + existential quantification over lists. For types, which implement semantic + equality (=) with syntactic equality, this is overly complicated. In + our theorem prover backend, we would end up with overly complicated, harder + to read definitions and some of the automation would be harder to apply. + Moreover, nearly all the old Lem generated code would change and require + (hopefully minor) adaptions of proofs. + + For now, we ignore this problem and just demand, that all instances of + the equality type class do the right thing for the theorem prover backends. +*) + +(*val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool*) +(*val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool*) + +val _ = Define ` + ((elemBy:('a -> 'a -> bool) -> 'a -> 'a list -> bool) eq e l= (EXISTS (eq e) l))`; + +(*let elem= elemBy (=)*) + +(* ------------------------- *) +(* Find *) +(* ------------------------- *) +(*val find : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe 'a*) (* previously not of maybe type *) + val _ = Define ` + ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P ([])= NONE) +/\ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P (x :: xs)= (if P x then SOME x else list_find_opt P xs))`; + + + +(* ----------------------------- *) +(* Lookup in an associative list *) +(* ----------------------------- *) +(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> Maybe.maybe 'b*) +(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> Maybe.maybe 'b*) + +(* DPM: eta-expansion for Coq backend type-inference. *) +val _ = Define ` + ((lookupBy:('a -> 'a -> bool) -> 'a ->('a#'b)list -> 'b option) eq k m= (OPTION_MAP (\ x . SND x) (list_find_opt (\p . + (case (p ) of ( (k', _) ) => eq k k' )) m)))`; + + +(* ------------------------- *) +(* filter *) +(* ------------------------- *) +(*val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +(*let rec filter P l= match l with + | [] -> [] + | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs + end*) + + +(* ------------------------- *) +(* partition *) +(* ------------------------- *) +(*val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +(*let partition P l= (filter P l, filter (fun x -> not (P x)) l)*) + +(*val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +(*let reversePartition P l= partition P (reverse l)*) + + +(* ------------------------- *) +(* delete first element *) +(* with certain property *) +(* ------------------------- *) + +(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe (list 'a)*) + val _ = Define ` + ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P ([])= NONE) +/\ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P (x :: xs)= (if (P x) then SOME xs else OPTION_MAP (\ xs' . x :: xs') (list_delete_first P xs)))`; + + + +(*val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a*) +(*val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +val _ = Define ` + ((list_delete:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) eq x l= (option_CASE (list_delete_first (eq x) l) l I))`; + + + +(* ========================================================================== *) +(* Zipping and unzipping lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* zip *) +(* ------------------------- *) + +(* zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. *) +(*val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) (* before combine *) + val _ = Define ` + ((list_combine:'a list -> 'b list ->('a#'b)list) l1 l2= ((case (l1, l2) of + (x :: xs, y :: ys) => (x, y) :: list_combine xs ys + | _ => [] +)))`; + + +(* ------------------------- *) +(* unzip *) +(* ------------------------- *) + +(*val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)*) +(*let rec unzip l= match l with + | [] -> ([], []) + | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys) +end*) + +(* ------------------------- *) +(* distinct elements *) +(* ------------------------- *) + +(*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*) +(*let rec allDistinct l= + match l with + | [] -> true + | (x::l') -> not (elem x l') && allDistinct l' + end*) + +(* some more useful functions *) +(*val mapMaybe : forall 'a 'b. ('a -> Maybe.maybe 'b) -> list 'a -> list 'b*) + val mapMaybe_defn = Defn.Hol_multi_defns ` + ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f ([])= ([])) +/\ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f (x::xs)= + ((case f x of + NONE => mapMaybe f xs + | SOME y => y :: (mapMaybe f xs) + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapMaybe_defn; + +(*val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b*) + val mapiAux_defn = Defn.Hol_multi_defns ` + ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) ([])= ([])) +/\ ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) (x :: xs)= ((f n x) :: mapiAux f (n +( 1 : num)) xs))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapiAux_defn; +val _ = Define ` + ((mapi:(num -> 'a -> 'b) -> 'a list -> 'b list) f l= (mapiAux f(( 0 : num)) l))`; + + +(*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*) +val _ = Define ` + ((deletes:'a list -> 'a list -> 'a list) xs ys= + (FOLDL (combin$C (list_delete (=))) xs ys))`; + + +(* ========================================================================== *) +(* Comments (not clean yet, please ignore the rest of the file) *) +(* ========================================================================== *) + +(* ----------------------- *) +(* skipped from Haskell Lib*) +(* ----------------------- + +intersperse :: a -> [a] -> [a] +intercalate :: [a] -> [[a]] -> [a] +transpose :: [[a]] -> [[a]] +subsequences :: [a] -> [[a]] +permutations :: [a] -> [[a]] +foldl` :: (a -> b -> a) -> a -> [b] -> aSource +foldl1` :: (a -> a -> a) -> [a] -> aSource + +and +or +sum +product +maximum +minimum +scanl +scanr +scanl1 +scanr1 +Accumulating maps + +mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source +mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source + +iterate :: (a -> a) -> a -> [a] +repeat :: a -> [a] +cycle :: [a] -> [a] +unfoldr + + +takeWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source +span :: (a -> Bool) -> [a] -> ([a], [a])Source +break :: (a -> Bool) -> [a] -> ([a], [a])Source +break p is equivalent to span (not . p). +stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source +group :: Eq a => [a] -> [[a]]Source +inits :: [a] -> [[a]]Source +tails :: [a] -> [[a]]Source + + +isPrefixOf :: Eq a => [a] -> [a] -> BoolSource +isSuffixOf :: Eq a => [a] -> [a] -> BoolSource +isInfixOf :: Eq a => [a] -> [a] -> BoolSource + + + +notElem :: Eq a => a -> [a] -> BoolSource + +zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source +zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source +zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source +zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source +zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source + +zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source +zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source +zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source +zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source +zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source +zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source + + +unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source +unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source +unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source +unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source +unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source + + +lines :: String -> [String]Source +words :: String -> [String]Source +unlines :: [String] -> StringSource +unwords :: [String] -> StringSource +nub :: Eq a => [a] -> [a]Source +delete :: Eq a => a -> [a] -> [a]Source + +(\\) :: Eq a => [a] -> [a] -> [a]Source +union :: Eq a => [a] -> [a] -> [a]Source +intersect :: Eq a => [a] -> [a] -> [a]Source +sort :: Ord a => [a] -> [a]Source +insert :: Ord a => a -> [a] -> [a]Source + + +nubBy :: (a -> a -> Bool) -> [a] -> [a]Source +deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source +deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source +sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source +insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source +maximumBy :: (a -> a -> Ordering) -> [a] -> aSource +minimumBy :: (a -> a -> Ordering) -> [a] -> aSource +genericLength :: Num i => [b] -> iSource +genericTake :: Integral i => i -> [a] -> [a]Source +genericDrop :: Integral i => i -> [a] -> [a]Source +genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source +genericIndex :: Integral a => [b] -> a -> bSource +genericReplicate :: Integral i => i -> a -> [a]Source + + +*) + + +(* ----------------------- *) +(* skipped from Lem Lib *) +(* ----------------------- + + +val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a +val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c + + +(* now maybe result and called lookup *) +val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b +let inline {ocaml} assoc = Ocaml.List.assoc + + +val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool +val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b) + + + +val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a +val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a + +val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a +val intersect : forall 'a. list 'a -> list 'a -> list 'a + + +*) + +(*val catMaybes : forall 'a. list (Maybe.maybe 'a) -> list 'a*) + val catMaybes_defn = Defn.Hol_multi_defns ` + ((catMaybes:('a option)list -> 'a list) ([])= + ([])) +/\ ((catMaybes:('a option)list -> 'a list) (NONE :: xs')= + (catMaybes xs')) +/\ ((catMaybes:('a option)list -> 'a list) (SOME x :: xs')= + (x :: catMaybes xs'))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) catMaybes_defn; +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml new file mode 100644 index 00000000..b8e452d3 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml @@ -0,0 +1,110 @@ +(*Generated by Lem from list_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_tupleTheory lem_numTheory lem_listTheory lem_assert_extraTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_list_extra" + + + +(*open import Bool Maybe Basic_classes Tuple Num List Assert_extra*) + +(* ------------------------- *) +(* head of non-empty list *) +(* ------------------------- *) +(*val head : forall 'a. list 'a -> 'a*) +(*let head l= match l with | x::xs -> x | [] -> failwith "List_extra.head of empty list" end*) + + +(* ------------------------- *) +(* tail of non-empty list *) +(* ------------------------- *) +(*val tail : forall 'a. list 'a -> list 'a*) +(*let tail l= match l with | x::xs -> xs | [] -> failwith "List_extra.tail of empty list" end*) + + +(* ------------------------- *) +(* last *) +(* ------------------------- *) +(*val last : forall 'a. list 'a -> 'a*) +(*let rec last l= match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith "List_extra.last of empty list" end*) + + +(* ------------------------- *) +(* init *) +(* ------------------------- *) + +(* All elements of a non-empty list except the last one. *) +(*val init : forall 'a. list 'a -> list 'a*) +(*let rec init l= match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith "List_extra.init of empty list" end*) + + +(* ------------------------- *) +(* foldl1 / foldr1 *) +(* ------------------------- *) + +(* folding functions for non-empty lists, + which don`t take the base case *) +(*val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +val _ = Define ` + ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)= (FOLDL f x xs)) +/\ ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])= (failwith "List_extra.foldl1 of empty list"))`; + + +(*val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +val _ = Define ` + ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)= (FOLDR f x xs)) +/\ ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])= (failwith "List_extra.foldr1 of empty list"))`; + + + +(* ------------------------- *) +(* nth element *) +(* ------------------------- *) + +(* get the nth element of a list *) +(*val nth : forall 'a. list 'a -> nat -> 'a*) +(*let nth l n= match index l n with Just e -> e | Nothing -> failwith "List_extra.nth" end*) + + +(* ------------------------- *) +(* Find_non_pure *) +(* ------------------------- *) +(*val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a*) +val _ = Define ` + ((findNonPure:('a -> bool) -> 'a list -> 'a) P l= ((case (list_find_opt P l) of + SOME e => e + | NONE => failwith "List_extra.findNonPure" +)))`; + + + +(* ------------------------- *) +(* zip same length *) +(* ------------------------- *) + +(*val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) +(*let rec zipSameLength l1 l2= match (l1, l2) with + | (x :: xs, y :: ys) -> (x, y) :: zipSameLength xs ys + | ([], []) -> [] + | _ -> failwith "List_extra.zipSameLength of different length lists" + +end*) + +(*val unfoldr: forall 'a 'b. ('a -> Maybe.maybe ('b * 'a)) -> 'a -> list 'b*) + val unfoldr_defn = Hol_defn "unfoldr" ` + ((unfoldr:('a ->('b#'a)option) -> 'a -> 'b list) f x= + ((case f x of + SOME (y, x') => + y :: unfoldr f x' + | NONE => + [] + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn unfoldr_defn; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml new file mode 100644 index 00000000..c169e9a8 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml @@ -0,0 +1,433 @@ +(*Generated by Lem from machine_word.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_numTheory lem_basic_classesTheory lem_showTheory lem_functionTheory wordsTheory wordsLib bitstringTheory integer_wordTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_machine_word" + + + +(*open import Bool Num Basic_classes Show Function*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*) + +(*type mword 'a*) + +(*class (Size 'a) + val size : nat +end*) + +(*val native_size : forall 'a. nat*) + +(*val ocaml_inject : forall 'a. nat * Num.natural -> mword 'a*) + +(* A singleton type family that can be used to carry a size as the type parameter *) + +(*type itself 'a*) + +(*val the_value : forall 'a. itself 'a*) + +(*val size_itself : forall 'a. Size 'a => itself 'a -> nat*) +val _ = Define ` + ((size_itself:'a itself -> num) x= (dimindex (the_value : 'a itself)))`; + + +(*******************************************************************) +(* Fixed bitwidths extracted from Anthony's models. *) +(* *) +(* If you need a size N that is not included here, put the lines *) +(* *) +(* type tyN *) +(* instance (Size tyN) let size = N end *) +(* declare isabelle target_rep type tyN = `N` *) +(* declare hol target_rep type tyN = `N` *) +(* *) +(* in your project, replacing N in each line. *) +(*******************************************************************) + +(*type ty1*) +(*type ty2*) +(*type ty3*) +(*type ty4*) +(*type ty5*) +(*type ty6*) +(*type ty7*) +(*type ty8*) +(*type ty9*) +(*type ty10*) +(*type ty11*) +(*type ty12*) +(*type ty13*) +(*type ty14*) +(*type ty15*) +(*type ty16*) +(*type ty17*) +(*type ty18*) +(*type ty19*) +(*type ty20*) +(*type ty21*) +(*type ty22*) +(*type ty23*) +(*type ty24*) +(*type ty25*) +(*type ty26*) +(*type ty27*) +(*type ty28*) +(*type ty29*) +(*type ty30*) +(*type ty31*) +(*type ty32*) +(*type ty33*) +(*type ty34*) +(*type ty35*) +(*type ty36*) +(*type ty37*) +(*type ty38*) +(*type ty39*) +(*type ty40*) +(*type ty41*) +(*type ty42*) +(*type ty43*) +(*type ty44*) +(*type ty45*) +(*type ty46*) +(*type ty47*) +(*type ty48*) +(*type ty49*) +(*type ty50*) +(*type ty51*) +(*type ty52*) +(*type ty53*) +(*type ty54*) +(*type ty55*) +(*type ty56*) +(*type ty57*) +(*type ty58*) +(*type ty59*) +(*type ty60*) +(*type ty61*) +(*type ty62*) +(*type ty63*) +(*type ty64*) +(*type ty65*) +(*type ty66*) +(*type ty67*) +(*type ty68*) +(*type ty69*) +(*type ty70*) +(*type ty71*) +(*type ty72*) +(*type ty73*) +(*type ty74*) +(*type ty75*) +(*type ty76*) +(*type ty77*) +(*type ty78*) +(*type ty79*) +(*type ty80*) +(*type ty81*) +(*type ty82*) +(*type ty83*) +(*type ty84*) +(*type ty85*) +(*type ty86*) +(*type ty87*) +(*type ty88*) +(*type ty89*) +(*type ty90*) +(*type ty91*) +(*type ty92*) +(*type ty93*) +(*type ty94*) +(*type ty95*) +(*type ty96*) +(*type ty97*) +(*type ty98*) +(*type ty99*) +(*type ty100*) +(*type ty101*) +(*type ty102*) +(*type ty103*) +(*type ty104*) +(*type ty105*) +(*type ty106*) +(*type ty107*) +(*type ty108*) +(*type ty109*) +(*type ty110*) +(*type ty111*) +(*type ty112*) +(*type ty113*) +(*type ty114*) +(*type ty115*) +(*type ty116*) +(*type ty117*) +(*type ty118*) +(*type ty119*) +(*type ty120*) +(*type ty121*) +(*type ty122*) +(*type ty123*) +(*type ty124*) +(*type ty125*) +(*type ty126*) +(*type ty127*) +(*type ty128*) +(*type ty129*) +(*type ty130*) +(*type ty131*) +(*type ty132*) +(*type ty133*) +(*type ty134*) +(*type ty135*) +(*type ty136*) +(*type ty137*) +(*type ty138*) +(*type ty139*) +(*type ty140*) +(*type ty141*) +(*type ty142*) +(*type ty143*) +(*type ty144*) +(*type ty145*) +(*type ty146*) +(*type ty147*) +(*type ty148*) +(*type ty149*) +(*type ty150*) +(*type ty151*) +(*type ty152*) +(*type ty153*) +(*type ty154*) +(*type ty155*) +(*type ty156*) +(*type ty157*) +(*type ty158*) +(*type ty159*) +(*type ty160*) +(*type ty161*) +(*type ty162*) +(*type ty163*) +(*type ty164*) +(*type ty165*) +(*type ty166*) +(*type ty167*) +(*type ty168*) +(*type ty169*) +(*type ty170*) +(*type ty171*) +(*type ty172*) +(*type ty173*) +(*type ty174*) +(*type ty175*) +(*type ty176*) +(*type ty177*) +(*type ty178*) +(*type ty179*) +(*type ty180*) +(*type ty181*) +(*type ty182*) +(*type ty183*) +(*type ty184*) +(*type ty185*) +(*type ty186*) +(*type ty187*) +(*type ty188*) +(*type ty189*) +(*type ty190*) +(*type ty191*) +(*type ty192*) +(*type ty193*) +(*type ty194*) +(*type ty195*) +(*type ty196*) +(*type ty197*) +(*type ty198*) +(*type ty199*) +(*type ty200*) +(*type ty201*) +(*type ty202*) +(*type ty203*) +(*type ty204*) +(*type ty205*) +(*type ty206*) +(*type ty207*) +(*type ty208*) +(*type ty209*) +(*type ty210*) +(*type ty211*) +(*type ty212*) +(*type ty213*) +(*type ty214*) +(*type ty215*) +(*type ty216*) +(*type ty217*) +(*type ty218*) +(*type ty219*) +(*type ty220*) +(*type ty221*) +(*type ty222*) +(*type ty223*) +(*type ty224*) +(*type ty225*) +(*type ty226*) +(*type ty227*) +(*type ty228*) +(*type ty229*) +(*type ty230*) +(*type ty231*) +(*type ty232*) +(*type ty233*) +(*type ty234*) +(*type ty235*) +(*type ty236*) +(*type ty237*) +(*type ty238*) +(*type ty239*) +(*type ty240*) +(*type ty241*) +(*type ty242*) +(*type ty243*) +(*type ty244*) +(*type ty245*) +(*type ty246*) +(*type ty247*) +(*type ty248*) +(*type ty249*) +(*type ty250*) +(*type ty251*) +(*type ty252*) +(*type ty253*) +(*type ty254*) +(*type ty255*) +(*type ty256*) +(*type ty257*) + +(*val word_length : forall 'a. mword 'a -> nat*) + +(******************************************************************) +(* Conversions *) +(******************************************************************) + +(*val signedIntegerFromWord : forall 'a. mword 'a -> Num.integer*) + +(*val unsignedIntegerFromWord : forall 'a. mword 'a -> Num.integer*) + +(* Version without typeclass constraint so that we can derive operations + in Lem for one of the theorem provers without requiring it. *) +(*val proverWordFromInteger : forall 'a. Num.integer -> mword 'a*) + +(*val wordFromInteger : forall 'a. Size 'a => Num.integer -> mword 'a*) +(* The OCaml version is defined after the arithmetic operations, below. *) + +(*val naturalFromWord : forall 'a. mword 'a -> Num.natural*) + +(*val wordFromNatural : forall 'a. Size 'a => Num.natural -> mword 'a*) + +(*val wordToHex : forall 'a. mword 'a -> string*) + +val _ = Define ` +((instance_Show_Show_Machine_word_mword_dict:('a words$word)lem_show$Show_class)= (<| + + show_method := words$word_to_hex_string|>))`; + + +(*val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a*) + +(*val bitlistFromWord : forall 'a. mword 'a -> list bool*) + + +(*val size_test_fn : forall 'a. Size 'a => mword 'a -> nat*) +val _ = Define ` + ((size_test_fn:'a words$word -> num) _= (dimindex (the_value : 'a itself)))`; + + +(******************************************************************) +(* Comparisons *) +(******************************************************************) + +(*val mwordEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(* Comparison tests are below, after the definition of wordFromInteger *) + +(******************************************************************) +(* Appending, splitting and probing words *) +(******************************************************************) + +(*val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c*) + +(* Note that we assume the result type has the correct size, especially + for Isabelle. *) +(*val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b*) + +(* Needs to be in the prover because we'd end up with unknown sizes in the + types in Lem. +*) +(*val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a*) + +(*val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a*) + +(*val getBit : forall 'a. mword 'a -> nat -> bool*) + +(*val msb : forall 'a. mword 'a -> bool*) + +(*val lsb : forall 'a. mword 'a -> bool*) + +(******************************************************************) +(* Bitwise operations, shifts, etc. *) +(******************************************************************) + +(*val shiftLeft : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val shiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val lAnd : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lOr : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lXor : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lNot : forall 'a. mword 'a -> mword 'a*) + +(*val rotateRight : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(*val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(* Sign extension tests are below, after the definition of wordFromInteger *) + +(*****************************************************************) +(* Arithmetic *) +(*****************************************************************) + +(*val plus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val minus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val uminus : forall 'a. mword 'a -> mword 'a*) + +(*val times : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) +(*val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a*) +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_mapScript.sml b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml new file mode 100644 index 00000000..a85a9d67 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml @@ -0,0 +1,153 @@ +(*Generated by Lem from map.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_maybeTheory lem_listTheory lem_tupleTheory lem_setTheory lem_numTheory finite_mapTheory finite_mapLib; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_map" + + + +(*open import Bool Basic_classes Function Maybe List Tuple Set Num*) +(*open import {hol} `finite_mapTheory` `finite_mapLib`*) + +(*type map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Map equality. *) +(* -------------------------------------------------------------------------- *) + +(*val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool*) +(*val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* Map type class *) +(* -------------------------------------------------------------------------- *) + +(*class ( MapKeyType 'a ) + val {ocaml;coq} mapKeyCompare : 'a -> 'a -> Basic_classes.ordering +end*) + +(* -------------------------------------------------------------------------- *) +(* Empty maps *) +(* -------------------------------------------------------------------------- *) + +(*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*) +(*val emptyBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Insertion *) +(* -------------------------------------------------------------------------- *) + +(*val insert : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Singleton *) +(* -------------------------------------------------------------------------- *) + +(*val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Emptyness check *) +(* -------------------------------------------------------------------------- *) + +(*val null : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* lookup *) +(* -------------------------------------------------------------------------- *) + +(*val lookupBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> Maybe.maybe 'v*) + +(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> Maybe.maybe 'v*) + +(* -------------------------------------------------------------------------- *) +(* findWithDefault *) +(* -------------------------------------------------------------------------- *) + +(*val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v*) + +(* -------------------------------------------------------------------------- *) +(* from lists *) +(* -------------------------------------------------------------------------- *) + +(*val fromList : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v*) +(*let fromList l= foldl (fun m (k,v) -> insert k v m) empty l*) + + +(* -------------------------------------------------------------------------- *) +(* to sets / domain / range *) +(* -------------------------------------------------------------------------- *) + +(*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*) +(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> Basic_classes.ordering) -> map 'k 'v -> set ('k * 'v)*) + + +(*val domainBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v -> set 'k*) +(*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*) + + +(*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*) +(*val rangeBy : forall 'k 'v. ('v -> 'v -> Basic_classes.ordering) -> map 'k 'v -> set 'v*) + + +(* -------------------------------------------------------------------------- *) +(* member *) +(* -------------------------------------------------------------------------- *) + +(*val member : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(*val notMember : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(* -------------------------------------------------------------------------- *) +(* Quantification *) +(* -------------------------------------------------------------------------- *) + +(*val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) +(*val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) + +(*let all P m= (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))*) + + +(* -------------------------------------------------------------------------- *) +(* Set-like operations. *) +(* -------------------------------------------------------------------------- *) +(*val deleteBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> map 'k 'v*) +(*val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*) +(*val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*) + +(*val union : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v*) + +(*val unions : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Maps (in the functor sense). *) +(* -------------------------------------------------------------------------- *) + +(*val map : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(*val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(* -------------------------------------------------------------------------- *) +(* Cardinality *) +(* -------------------------------------------------------------------------- *) +(*val size : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat*) + +(* instance of SetType *) +val _ = Define ` + ((map_setElemCompare:(('d#'c)set ->('b#'a)set -> 'e) ->('d,'c)fmap ->('b,'a)fmap -> 'e) cmp x y= + (cmp (FMAP_TO_SET x) (FMAP_TO_SET y)))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml new file mode 100644 index 00000000..57a258f8 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml @@ -0,0 +1,72 @@ +(*Generated by Lem from map_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_assert_extraTheory lem_maybeTheory lem_listTheory lem_numTheory lem_setTheory lem_mapTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_map_extra" + + + +(*open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map*) + +(* -------------------------------------------------------------------------- *) +(* find *) +(* -------------------------------------------------------------------------- *) + +(*val find : forall 'k 'v. MapKeyType 'k => 'k -> Map.map 'k 'v -> 'v*) +(*let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith "Map_extra.find" end*) + + + +(* -------------------------------------------------------------------------- *) +(* from sets / domain / range *) +(* -------------------------------------------------------------------------- *) + + +(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> Map.map 'k 'v*) +(*let fromSet f s= Set_helpers.fold (fun k m -> Map.insert k (f k) m) s Map.empty*) + +(* +assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty) +assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)] +*) + +(* -------------------------------------------------------------------------- *) +(* fold *) +(* -------------------------------------------------------------------------- *) + +(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> Map.map 'k 'v -> 'r -> 'r*) +val _ = Define ` + ((fold:('k -> 'v -> 'r -> 'r) ->('k,'v)fmap -> 'r -> 'r) f m v= (ITSET (\ (k, v) r . f k v r) (FMAP_TO_SET m) v))`; + + +(* +assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9) +assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12) +*) + +(*val toList: forall 'k 'v. MapKeyType 'k => Map.map 'k 'v -> list ('k * 'v)*) +(* declare compile_message toList = "Map_extra.toList is only defined for the ocaml, isabelle and coq backend" *) + +(* more 'map' functions *) + +(* TODO: this function is in map_extra rather than map just for implementation reasons *) +(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> Maybe.maybe 'c) -> Map.map 'a 'b -> Map.map 'a 'c*) +(* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *) +val _ = Define ` + ((option_map:('a -> 'b -> 'c option) ->('a,'b)fmap ->('a,'c)fmap) f m= + (FOLDL + (\ m' (k, v) . + (case f k v of + NONE => m' + | SOME v' =>m' |+ (k, v') + )) + FEMPTY + (MAP_TO_LIST m)))`; + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml new file mode 100644 index 00000000..29562d66 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml @@ -0,0 +1,112 @@ +(*Generated by Lem from maybe.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_functionTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_maybe" + + + +(*open import Bool Basic_classes Function*) + +(* ========================================================================== *) +(* Basic stuff *) +(* ========================================================================== *) + +(*type maybe 'a = + | Nothing + | Just of 'a*) + + +(*val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool*) +(*val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool*) + +val _ = Define ` + ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE NONE= T) +/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE (SOME _)= F) +/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME _) NONE= F) +/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME x') (SOME y')= (eq x' y'))`; + + + +val _ = Define ` + ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE NONE= EQ) +/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE (SOME _)= LT) +/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME _) NONE= GT) +/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME x') (SOME y')= (cmp x' y'))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_Maybe_maybe_dict:'a lem_basic_classes$Ord_class ->('a option)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<| + + compare_method := (maybeCompare + dict_Basic_classes_Ord_a.compare_method); + + isLess_method := (\ m1 . (\ m2 . maybeCompare + dict_Basic_classes_Ord_a.compare_method m1 m2 = LT)); + + isLessEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare + dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = LT) \/ (r = EQ)))); + + isGreater_method := (\ m1 . (\ m2 . maybeCompare + dict_Basic_classes_Ord_a.compare_method m1 m2 = GT)); + + isGreaterEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare + dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = GT) \/ (r = EQ))))|>))`; + + +(* ----------------------- *) +(* maybe *) +(* ----------------------- *) + +(*val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b*) +(*let maybe d f mb= match mb with + | Just a -> f a + | Nothing -> d +end*) + +(* ----------------------- *) +(* isJust / isNothing *) +(* ----------------------- *) + +(*val isJust : forall 'a. maybe 'a -> bool*) +(*let isJust mb= match mb with + | Just _ -> true + | Nothing -> false +end*) + +(*val isNothing : forall 'a. maybe 'a -> bool*) +(*let isNothing mb= match mb with + | Just _ -> false + | Nothing -> true +end*) + +(* ----------------------- *) +(* fromMaybe *) +(* ----------------------- *) + +(*val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a*) +(*let fromMaybe d mb= match mb with + | Just v -> v + | Nothing -> d +end*) + +(* ----------------------- *) +(* map *) +(* ----------------------- *) + +(*val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b*) +(*let map f= maybe Nothing (fun v -> Just (f v))*) + + +(* ----------------------- *) +(* bind *) +(* ----------------------- *) + +(*val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b*) +(*let bind mb f= maybe Nothing f mb*) +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml new file mode 100644 index 00000000..6b04d291 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml @@ -0,0 +1,23 @@ +(*Generated by Lem from maybe_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_basic_classesTheory lem_maybeTheory lem_assert_extraTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_maybe_extra" + + + +(*open import Basic_classes Maybe Assert_extra*) + +(* ----------------------- *) +(* fromJust *) +(* ----------------------- *) + +(*val fromJust : forall 'a. Maybe.maybe 'a -> 'a*) +(*let fromJust op= match op with | Just v -> v | Nothing -> failwith "fromJust of Nothing" end*) + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_numScript.sml b/snapshots/hol4/lem/hol-lib/lem_numScript.sml new file mode 100644 index 00000000..9dcd0554 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_numScript.sml @@ -0,0 +1,1317 @@ +(*Generated by Lem from num.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_num" + + + +(*open import Bool Basic_classes*) +(*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*) +(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*) +(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) + +(*class inline ( Numeral 'a ) + val fromNumeral : numeral -> 'a +end*) + +(* ========================================================================== *) +(* Syntactic type-classes for common operations *) +(* ========================================================================== *) + +(* Typeclasses can be used as a mean to overload constants like "+", "-", etc *) + +val _ = Hol_datatype ` +(* 'a *) NumNegate_class= <| + numNegate_method : 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumAbs_class= <| + abs_method : 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumAdd_class= <| + numAdd_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumMinus_class= <| + numMinus_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumMult_class= <| + numMult_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumPow_class= <| + numPow_method : 'a -> num -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumDivision_class= <| + numDivision_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumIntegerDivision_class= <| + div_method : 'a -> 'a -> 'a +|>`; + + + +val _ = Hol_datatype ` +(* 'a *) NumRemainder_class= <| + mod_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumSucc_class= <| + succ_method : 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) NumPred_class= <| + pred_method : 'a -> 'a +|>`; + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* unbounded size natural numbers *) +(*type natural*) + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* bounded size integers with uncertain length *) + +(*type int*) + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(* unbounded size integers *) + +(*type integer*) + +(* ----------------------- *) +(* bint *) +(* ----------------------- *) + +(* TODO the bounded ints are only partially implemented, use with care. *) + +(* 32 bit integers *) +(*type int32*) + +(* 64 bit integers *) +(*type int64*) + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(* unbounded size and precision rational numbers *) + +(*type rational*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(* real numbers *) +(* Note that for OCaml, this is mapped to floats with 64 bits. *) + +(*type real*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* double *) +(* ----------------------- *) + +(* double precision floating point (64 bits) *) + +(*type float64*) (* ???: better type for this in HOL? *) + +(*type float32*) (* ???: better type for this in HOL? *) + + +(* ========================================================================== *) +(* Binding the standard operations for the number types *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(*val natFromNumeral : numeral -> nat*) + +(*val natEq : nat -> nat -> bool*) + +(*val natLess : nat -> nat -> bool*) +(*val natLessEqual : nat -> nat -> bool*) +(*val natGreater : nat -> nat -> bool*) +(*val natGreaterEqual : nat -> nat -> bool*) + +(*val natCompare : nat -> nat -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_nat_dict:(num)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val natAdd : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumAdd_nat_dict:(num)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val natMinus : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumMinus_nat_dict:(num)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val natSucc : nat -> nat*) +(*let natSucc n= (Instance_Num_NumAdd_nat.+) n 1*) +val _ = Define ` +((instance_Num_NumSucc_nat_dict:(num)NumSucc_class)= (<| + + succ_method := SUC|>))`; + + +(*val natPred : nat -> nat*) +val _ = Define ` +((instance_Num_NumPred_nat_dict:(num)NumPred_class)= (<| + + pred_method := PRE|>))`; + + +(*val natMult : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumMult_nat_dict:(num)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + +(*val natDiv : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_nat_dict:(num)NumIntegerDivision_class)= (<| + + div_method := (DIV)|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_nat_dict:(num)NumDivision_class)= (<| + + numDivision_method := (DIV)|>))`; + + +(*val natMod : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumRemainder_nat_dict:(num)NumRemainder_class)= (<| + + mod_method := (MOD)|>))`; + + + +(*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*) + val _ = Define ` + ((gen_pow_aux:('a -> 'a -> 'a) -> 'a -> 'a -> num -> 'a) (mul : 'a -> 'a -> 'a) (a : 'a) (b : 'a) (e : num)= + ((case e of + 0 => a (* cannot happen, call discipline guarentees e >= 1 *) + | (SUC 0) => mul a b + | ( (SUC(SUC e'))) => let e'' = (e DIV( 2 : num)) in + let a' = (if (e MOD( 2 : num)) =( 0 : num) then a else mul a b) in + gen_pow_aux mul a' (mul b b) e'' + )))`; + + +val _ = Define ` + ((gen_pow:'a ->('a -> 'a -> 'a) -> 'a -> num -> 'a) (one1 : 'a) (mul : 'a -> 'a -> 'a) (b : 'a) (e : num) : 'a= + (if e <( 0 : num) then one1 else + if (e =( 0 : num)) then one1 else gen_pow_aux mul one1 b e))`; + + +(*val natPow : nat -> nat -> nat*) + +val _ = Define ` +((instance_Num_NumPow_nat_dict:(num)NumPow_class)= (<| + + numPow_method := ( ** )|>))`; + + +(*val natMin : nat -> nat -> nat*) + +(*val natMax : nat -> nat -> nat*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_nat_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := MAX; + + min_method := MIN|>))`; + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(*val naturalFromNumeral : numeral -> natural*) + +(*val naturalEq : natural -> natural -> bool*) + +(*val naturalLess : natural -> natural -> bool*) +(*val naturalLessEqual : natural -> natural -> bool*) +(*val naturalGreater : natural -> natural -> bool*) +(*val naturalGreaterEqual : natural -> natural -> bool*) + +(*val naturalCompare : natural -> natural -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_natural_dict:(num)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val naturalAdd : natural -> natural -> natural*) + +val _ = Define ` +((instance_Num_NumAdd_Num_natural_dict:(num)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val naturalMinus : natural -> natural -> natural*) + +val _ = Define ` +((instance_Num_NumMinus_Num_natural_dict:(num)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val naturalSucc : natural -> natural*) +(*let naturalSucc n= (Instance_Num_NumAdd_Num_natural.+) n 1*) +val _ = Define ` +((instance_Num_NumSucc_Num_natural_dict:(num)NumSucc_class)= (<| + + succ_method := SUC|>))`; + + +(*val naturalPred : natural -> natural*) +val _ = Define ` +((instance_Num_NumPred_Num_natural_dict:(num)NumPred_class)= (<| + + pred_method := PRE|>))`; + + +(*val naturalMult : natural -> natural -> natural*) + +val _ = Define ` +((instance_Num_NumMult_Num_natural_dict:(num)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + + +(*val naturalPow : natural -> nat -> natural*) + +val _ = Define ` +((instance_Num_NumPow_Num_natural_dict:(num)NumPow_class)= (<| + + numPow_method := ( ** )|>))`; + + +(*val naturalDiv : natural -> natural -> natural*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_Num_natural_dict:(num)NumIntegerDivision_class)= (<| + + div_method := (DIV)|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Num_natural_dict:(num)NumDivision_class)= (<| + + numDivision_method := (DIV)|>))`; + + +(*val naturalMod : natural -> natural -> natural*) + +val _ = Define ` +((instance_Num_NumRemainder_Num_natural_dict:(num)NumRemainder_class)= (<| + + mod_method := (MOD)|>))`; + + +(*val naturalMin : natural -> natural -> natural*) + +(*val naturalMax : natural -> natural -> natural*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_natural_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := MAX; + + min_method := MIN|>))`; + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(*val intFromNumeral : numeral -> int*) + +(*val intEq : int -> int -> bool*) + +(*val intLess : int -> int -> bool*) +(*val intLessEqual : int -> int -> bool*) +(*val intGreater : int -> int -> bool*) +(*val intGreaterEqual : int -> int -> bool*) + +(*val intCompare : int -> int -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_int_dict:(int)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val intNegate : int -> int*) + +val _ = Define ` +((instance_Num_NumNegate_Num_int_dict:(int)NumNegate_class)= (<| + + numNegate_method := (\ i. ~ i)|>))`; + + +(*val intAbs : int -> int*) (* TODO: check *) + +val _ = Define ` +((instance_Num_NumAbs_Num_int_dict:(int)NumAbs_class)= (<| + + abs_method := ABS|>))`; + + +(*val intAdd : int -> int -> int*) + +val _ = Define ` +((instance_Num_NumAdd_Num_int_dict:(int)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val intMinus : int -> int -> int*) + +val _ = Define ` +((instance_Num_NumMinus_Num_int_dict:(int)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val intSucc : int -> int*) +val _ = Define ` +((instance_Num_NumSucc_Num_int_dict:(int)NumSucc_class)= (<| + + succ_method := (\ n. n +( 1 : int))|>))`; + + +(*val intPred : int -> int*) +val _ = Define ` +((instance_Num_NumPred_Num_int_dict:(int)NumPred_class)= (<| + + pred_method := (\ n. n -( 1 : int))|>))`; + + +(*val intMult : int -> int -> int*) + +val _ = Define ` +((instance_Num_NumMult_Num_int_dict:(int)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + + +(*val intPow : int -> nat -> int*) + +val _ = Define ` +((instance_Num_NumPow_Num_int_dict:(int)NumPow_class)= (<| + + numPow_method := ( ** )|>))`; + + +(*val intDiv : int -> int -> int*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_Num_int_dict:(int)NumIntegerDivision_class)= (<| + + div_method := (/)|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Num_int_dict:(int)NumDivision_class)= (<| + + numDivision_method := (/)|>))`; + + +(*val intMod : int -> int -> int*) + +val _ = Define ` +((instance_Num_NumRemainder_Num_int_dict:(int)NumRemainder_class)= (<| + + mod_method := (%)|>))`; + + +(*val intMin : int -> int -> int*) + +(*val intMax : int -> int -> int*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_int_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := int_max; + + min_method := int_min|>))`; + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) +(*val int32FromNumeral : numeral -> int32*) + +(*val int32Eq : int32 -> int32 -> bool*) + +(*val int32Less : int32 -> int32 -> bool*) +(*val int32LessEqual : int32 -> int32 -> bool*) +(*val int32Greater : int32 -> int32 -> bool*) +(*val int32GreaterEqual : int32 -> int32 -> bool*) + +(*val int32Compare : int32 -> int32 -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_int32_dict:(word32)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val int32Negate : int32 -> int32*) + +val _ = Define ` +((instance_Num_NumNegate_Num_int32_dict:(word32)NumNegate_class)= (<| + + numNegate_method := (\ i. ((- i) : word32))|>))`; + + +(*val int32Abs : int32 -> int32*) +val _ = Define ` + ((int32Abs:word32 -> word32) i= (if((n2w 0) : word32) <= i then i else ((- i) : word32)))`; + + +val _ = Define ` +((instance_Num_NumAbs_Num_int32_dict:(word32)NumAbs_class)= (<| + + abs_method := int32Abs|>))`; + + + +(*val int32Add : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Num_NumAdd_Num_int32_dict:(word32)NumAdd_class)= (<| + + numAdd_method := (\ i1 i2. ((word_add i1 i2) : word32))|>))`; + + +(*val int32Minus : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Num_NumMinus_Num_int32_dict:(word32)NumMinus_class)= (<| + + numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word32))|>))`; + + +(*val int32Succ : int32 -> int32*) + +val _ = Define ` +((instance_Num_NumSucc_Num_int32_dict:(word32)NumSucc_class)= (<| + + succ_method := (\ n. ((word_add n (((n2w 1) : word32))) : word32))|>))`; + + +(*val int32Pred : int32 -> int32*) +val _ = Define ` +((instance_Num_NumPred_Num_int32_dict:(word32)NumPred_class)= (<| + + pred_method := (\ n. ((word_sub n (((n2w 1) : word32))) : word32))|>))`; + + +(*val int32Mult : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Num_NumMult_Num_int32_dict:(word32)NumMult_class)= (<| + + numMult_method := (\ i1 i2. ((word_mul i1 i2) : word32))|>))`; + + + +(*val int32Pow : int32 -> nat -> int32*) +val _ = Define ` + ((int32Pow:word32 -> num -> word32)= (gen_pow(((n2w 1) : word32)) (\ i1 i2. ((word_mul i1 i2) : word32))))`; + + +val _ = Define ` +((instance_Num_NumPow_Num_int32_dict:(word32)NumPow_class)= (<| + + numPow_method := int32Pow|>))`; + + +(*val int32Div : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_Num_int32_dict:(word32)NumIntegerDivision_class)= (<| + + div_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Num_int32_dict:(word32)NumDivision_class)= (<| + + numDivision_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`; + + +(*val int32Mod : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Num_NumRemainder_Num_int32_dict:(word32)NumRemainder_class)= (<| + + mod_method := (\ i1 i2. ((word_mod i1 i2) : word32))|>))`; + + +(*val int32Min : int32 -> int32 -> int32*) + +(*val int32Max : int32 -> int32 -> int32*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_int32_dict:(word32)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := word_smax; + + min_method := word_smin|>))`; + + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) +(*val int64FromNumeral : numeral -> int64*) + +(*val int64Eq : int64 -> int64 -> bool*) + +(*val int64Less : int64 -> int64 -> bool*) +(*val int64LessEqual : int64 -> int64 -> bool*) +(*val int64Greater : int64 -> int64 -> bool*) +(*val int64GreaterEqual : int64 -> int64 -> bool*) + +(*val int64Compare : int64 -> int64 -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_int64_dict:(word64)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val int64Negate : int64 -> int64*) + +val _ = Define ` +((instance_Num_NumNegate_Num_int64_dict:(word64)NumNegate_class)= (<| + + numNegate_method := (\ i. ((- i) : word64))|>))`; + + +(*val int64Abs : int64 -> int64*) +val _ = Define ` + ((int64Abs:word64 -> word64) i= (if((n2w 0) : word64) <= i then i else ((- i) : word64)))`; + + +val _ = Define ` +((instance_Num_NumAbs_Num_int64_dict:(word64)NumAbs_class)= (<| + + abs_method := int64Abs|>))`; + + + +(*val int64Add : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Num_NumAdd_Num_int64_dict:(word64)NumAdd_class)= (<| + + numAdd_method := (\ i1 i2. ((word_add i1 i2) : word64))|>))`; + + +(*val int64Minus : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Num_NumMinus_Num_int64_dict:(word64)NumMinus_class)= (<| + + numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word64))|>))`; + + +(*val int64Succ : int64 -> int64*) + +val _ = Define ` +((instance_Num_NumSucc_Num_int64_dict:(word64)NumSucc_class)= (<| + + succ_method := (\ n. ((word_add n (((n2w 1) : word64))) : word64))|>))`; + + +(*val int64Pred : int64 -> int64*) +val _ = Define ` +((instance_Num_NumPred_Num_int64_dict:(word64)NumPred_class)= (<| + + pred_method := (\ n. ((word_sub n (((n2w 1) : word64))) : word64))|>))`; + + +(*val int64Mult : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Num_NumMult_Num_int64_dict:(word64)NumMult_class)= (<| + + numMult_method := (\ i1 i2. ((word_mul i1 i2) : word64))|>))`; + + + +(*val int64Pow : int64 -> nat -> int64*) +val _ = Define ` + ((int64Pow:word64 -> num -> word64)= (gen_pow(((n2w 1) : word64)) (\ i1 i2. ((word_mul i1 i2) : word64))))`; + + +val _ = Define ` +((instance_Num_NumPow_Num_int64_dict:(word64)NumPow_class)= (<| + + numPow_method := int64Pow|>))`; + + +(*val int64Div : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_Num_int64_dict:(word64)NumIntegerDivision_class)= (<| + + div_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Num_int64_dict:(word64)NumDivision_class)= (<| + + numDivision_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`; + + +(*val int64Mod : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Num_NumRemainder_Num_int64_dict:(word64)NumRemainder_class)= (<| + + mod_method := (\ i1 i2. ((word_mod i1 i2) : word64))|>))`; + + +(*val int64Min : int64 -> int64 -> int64*) + +(*val int64Max : int64 -> int64 -> int64*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_int64_dict:(word64)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := word_smax; + + min_method := word_smin|>))`; + + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerFromNumeral : numeral -> integer*) + +(*val integerFromNat : nat -> integer*) (* TODO: check *) + +(*val integerEq : integer -> integer -> bool*) + +(*val integerLess : integer -> integer -> bool*) +(*val integerLessEqual : integer -> integer -> bool*) +(*val integerGreater : integer -> integer -> bool*) +(*val integerGreaterEqual : integer -> integer -> bool*) + +(*val integerCompare : integer -> integer -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_integer_dict:(int)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val integerNegate : integer -> integer*) + +val _ = Define ` +((instance_Num_NumNegate_Num_integer_dict:(int)NumNegate_class)= (<| + + numNegate_method := (\ i. ~ i)|>))`; + + +(*val integerAbs : integer -> integer*) (* TODO: check *) + +val _ = Define ` +((instance_Num_NumAbs_Num_integer_dict:(int)NumAbs_class)= (<| + + abs_method := ABS|>))`; + + +(*val integerAdd : integer -> integer -> integer*) + +val _ = Define ` +((instance_Num_NumAdd_Num_integer_dict:(int)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val integerMinus : integer -> integer -> integer*) + +val _ = Define ` +((instance_Num_NumMinus_Num_integer_dict:(int)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val integerSucc : integer -> integer*) +val _ = Define ` +((instance_Num_NumSucc_Num_integer_dict:(int)NumSucc_class)= (<| + + succ_method := (\ n. n +( 1 : int))|>))`; + + +(*val integerPred : integer -> integer*) +val _ = Define ` +((instance_Num_NumPred_Num_integer_dict:(int)NumPred_class)= (<| + + pred_method := (\ n. n -( 1 : int))|>))`; + + +(*val integerMult : integer -> integer -> integer*) + +val _ = Define ` +((instance_Num_NumMult_Num_integer_dict:(int)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + + +(*val integerPow : integer -> nat -> integer*) + +val _ = Define ` +((instance_Num_NumPow_Num_integer_dict:(int)NumPow_class)= (<| + + numPow_method := ( ** )|>))`; + + +(*val integerDiv : integer -> integer -> integer*) + +val _ = Define ` +((instance_Num_NumIntegerDivision_Num_integer_dict:(int)NumIntegerDivision_class)= (<| + + div_method := (/)|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Num_integer_dict:(int)NumDivision_class)= (<| + + numDivision_method := (/)|>))`; + + +(*val integerMod : integer -> integer -> integer*) + +val _ = Define ` +((instance_Num_NumRemainder_Num_integer_dict:(int)NumRemainder_class)= (<| + + mod_method := (%)|>))`; + + +(*val integerMin : integer -> integer -> integer*) + +(*val integerMax : integer -> integer -> integer*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_integer_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := int_max; + + min_method := int_min|>))`; + + + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(*val rationalFromNumeral : numeral -> rational*) + +(*val rationalFromInt : int -> rational*) + +(*val rationalEq : rational -> rational -> bool*) + +(*val rationalLess : rational -> rational -> bool*) +(*val rationalLessEqual : rational -> rational -> bool*) +(*val rationalGreater : rational -> rational -> bool*) +(*val rationalGreaterEqual : rational -> rational -> bool*) + +(*val rationalCompare : rational -> rational -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_rational_dict:(rat)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val rationalAdd : rational -> rational -> rational*) + +val _ = Define ` +((instance_Num_NumAdd_Num_rational_dict:(rat)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val rationalMinus : rational -> rational -> rational*) + +val _ = Define ` +((instance_Num_NumMinus_Num_rational_dict:(rat)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val rationalNegate : rational -> rational*) + +val _ = Define ` +((instance_Num_NumNegate_Num_rational_dict:(rat)NumNegate_class)= (<| + + numNegate_method := (\ n. ( 0 : rat) - n)|>))`; + + +(*val rationalAbs : rational -> rational*) + +val _ = Define ` +((instance_Num_NumAbs_Num_rational_dict:(rat)NumAbs_class)= (<| + + abs_method := (\ n. (if n >( 0 : rat) then n else( 0 : rat) - n))|>))`; + + +(*val rationalSucc : rational -> rational*) +val _ = Define ` +((instance_Num_NumSucc_Num_rational_dict:(rat)NumSucc_class)= (<| + + succ_method := (\ n. n +( 1 : rat))|>))`; + + +(*val rationalPred : rational -> rational*) +val _ = Define ` +((instance_Num_NumPred_Num_rational_dict:(rat)NumPred_class)= (<| + + pred_method := (\ n. n -( 1 : rat))|>))`; + + +(*val rationalMult : rational -> rational -> rational*) + +val _ = Define ` +((instance_Num_NumMult_Num_rational_dict:(rat)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + +(*val rationalDiv : rational -> rational -> rational*) + +val _ = Define ` +((instance_Num_NumDivision_Num_rational_dict:(rat)NumDivision_class)= (<| + + numDivision_method := (/)|>))`; + + +(*val rationalFromFrac : int -> int -> rational*) +(*let rationalFromFrac n d= (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)*) + +(*val rationalPowInteger : rational -> integer -> rational*) + val rationalPowInteger_defn = Hol_defn "rationalPowInteger" ` + ((rationalPowInteger:rat -> int -> rat) b e= + (if e =( 0 : int) then( 1 : rat) else + if e >( 0 : int) then rationalPowInteger b (e -( 1 : int)) * b else + rationalPowInteger b (e +( 1 : int)) / b))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn rationalPowInteger_defn; + +(*val rationalPowNat : rational -> nat -> rational*) +val _ = Define ` + ((rationalPowNat:rat -> num -> rat) r e= (rationalPowInteger r (int_of_num e)))`; + + +val _ = Define ` +((instance_Num_NumPow_Num_rational_dict:(rat)NumPow_class)= (<| + + numPow_method := rationalPowNat|>))`; + + +(*val rationalMin : rational -> rational -> rational*) + +(*val rationalMax : rational -> rational -> rational*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_rational_dict:(rat)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := (maxByLessEqual (<=)); + + min_method := (minByLessEqual (<=))|>))`; + + + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(*val realFromNumeral : numeral -> real*) + +(*val realFromInteger : integer -> real*) + +(*val realEq : real -> real -> bool*) + +(*val realLess : real -> real -> bool*) +(*val realLessEqual : real -> real -> bool*) +(*val realGreater : real -> real -> bool*) +(*val realGreaterEqual : real -> real -> bool*) + +(*val realCompare : real -> real -> Basic_classes.ordering*) + +val _ = Define ` +((instance_Basic_classes_Ord_Num_real_dict:(real)lem_basic_classes$Ord_class)= (<| + + compare_method := (genericCompare (<) (=)); + + isLess_method := (<); + + isLessEqual_method := (<=); + + isGreater_method := (>); + + isGreaterEqual_method := (>=)|>))`; + + +(*val realAdd : real -> real -> real*) + +val _ = Define ` +((instance_Num_NumAdd_Num_real_dict:(real)NumAdd_class)= (<| + + numAdd_method := (+)|>))`; + + +(*val realMinus : real -> real -> real*) + +val _ = Define ` +((instance_Num_NumMinus_Num_real_dict:(real)NumMinus_class)= (<| + + numMinus_method := (-)|>))`; + + +(*val realNegate : real -> real*) + +val _ = Define ` +((instance_Num_NumNegate_Num_real_dict:(real)NumNegate_class)= (<| + + numNegate_method := (\ n. (real_of_num 0) - n)|>))`; + + +(*val realAbs : real -> real*) + +val _ = Define ` +((instance_Num_NumAbs_Num_real_dict:(real)NumAbs_class)= (<| + + abs_method := (\ n. (if n >(real_of_num 0) then n else(real_of_num 0) - n))|>))`; + + +(*val realSucc : real -> real*) +val _ = Define ` +((instance_Num_NumSucc_Num_real_dict:(real)NumSucc_class)= (<| + + succ_method := (\ n. n +(real_of_num 1))|>))`; + + +(*val realPred : real -> real*) +val _ = Define ` +((instance_Num_NumPred_Num_real_dict:(real)NumPred_class)= (<| + + pred_method := (\ n. n -(real_of_num 1))|>))`; + + +(*val realMult : real -> real -> real*) + +val _ = Define ` +((instance_Num_NumMult_Num_real_dict:(real)NumMult_class)= (<| + + numMult_method := ( * )|>))`; + + +(*val realDiv : real -> real -> real*) + +val _ = Define ` +((instance_Num_NumDivision_Num_real_dict:(real)NumDivision_class)= (<| + + numDivision_method := (/)|>))`; + + +(*val realFromFrac : integer -> integer -> real*) +val _ = Define ` + ((realFromFrac:int -> int -> real) n d= (((real_of_int n)) / ((real_of_int d))))`; + + +(*val realPowInteger : real -> integer -> real*) + val realPowInteger_defn = Hol_defn "realPowInteger" ` + ((realPowInteger:real -> int -> real) b e= + (if e =( 0 : int) then(real_of_num 1) else + if e >( 0 : int) then realPowInteger b (e -( 1 : int)) * b else + realPowInteger b (e +( 1 : int)) / b))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn realPowInteger_defn; + +(*val realPowNat : real -> nat -> real*) +(*let realPowNat r e= realPowInteger r (integerFromNat e)*) + +val _ = Define ` +((instance_Num_NumPow_Num_real_dict:(real)NumPow_class)= (<| + + numPow_method := (pow)|>))`; + + +(*val realSqrt : real -> real*) + +(*val realMin : real -> real -> real*) + +(*val realMax : real -> real -> real*) + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Num_real_dict:(real)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := max; + + min_method := min|>))`; + + +(*val realCeiling : real -> integer*) + +(*val realFloor : real -> integer*) + +(* ========================================================================== *) +(* Translation between number types *) +(* ========================================================================== *) + +(******************) +(* integerFrom... *) +(******************) + +(*val integerFromInt : int -> integer*) + +(*val integerFromNatural : natural -> integer*) + + +(*val integerFromInt32 : int32 -> integer*) + + +(*val integerFromInt64 : int64 -> integer*) + + +(******************) +(* naturalFrom... *) +(******************) + +(*val naturalFromNat : nat -> natural*) + +(*val naturalFromInteger : integer -> natural*) + + +(******************) +(* intFrom ... *) +(******************) + +(*val intFromInteger : integer -> int*) + +(*val intFromNat : nat -> int*) + + +(******************) +(* natFrom ... *) +(******************) + +(*val natFromNatural : natural -> nat*) + +(*val natFromInt : int -> nat*) + + +(******************) +(* int32From ... *) +(******************) + +(*val int32FromNat : nat -> int32*) + +(*val int32FromNatural : natural -> int32*) + +(*val int32FromInteger : integer -> int32*) +val _ = Define ` + ((int32FromInteger:int -> word32) i= ( + let abs_int32 = (((n2w (Num (ABS i))) : word32)) in + if (i <( 0 : int)) then (((- abs_int32) : word32)) else abs_int32 +))`; + + +(*val int32FromInt : int -> int32*) +val _ = Define ` + ((int32FromInt:int -> word32) i= (int32FromInteger ( i)))`; + + + +(*val int32FromInt64 : int64 -> int32*) +(*let int32FromInt64 i= int32FromInteger (integerFromInt64 i)*) + + + + +(******************) +(* int64From ... *) +(******************) + +(*val int64FromNat : nat -> int64*) + +(*val int64FromNatural : natural -> int64*) + +(*val int64FromInteger : integer -> int64*) +val _ = Define ` + ((int64FromInteger:int -> word64) i= ( + let abs_int64 = (((n2w (Num (ABS i))) : word64)) in + if (i <( 0 : int)) then (((- abs_int64) : word64)) else abs_int64 +))`; + + +(*val int64FromInt : int -> int64*) +val _ = Define ` + ((int64FromInt:int -> word64) i= (int64FromInteger ( i)))`; + + + +(*val int64FromInt32 : int32 -> int64*) +(*let int64FromInt32 i= int64FromInteger (integerFromInt32 i)*) + + +(******************) +(* what's missing *) +(******************) + +(*val naturalFromInt : int -> natural*) +(*val naturalFromInt32 : int32 -> natural*) +(*val naturalFromInt64 : int64 -> natural*) + + +(*val intFromNatural : natural -> int*) +(*val intFromInt32 : int32 -> int*) +(*val intFromInt64 : int64 -> int*) + +(*val natFromInteger : integer -> nat*) +(*val natFromInt32 : int32 -> nat*) +(*val natFromInt64 : int64 -> nat*) +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml new file mode 100644 index 00000000..69644f94 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml @@ -0,0 +1,34 @@ +(*Generated by Lem from num_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_numTheory lem_stringTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_num_extra" + +(* **************************************************** *) +(* *) +(* A library of additional functions on numbers *) +(* *) +(* **************************************************** *) + +(*open import Num*) +(*open import String*) + +(*val naturalOfString : string -> Num.natural*) + +(*val integerOfString : string -> Num.integer*) + + +(* Truncation integer division (round toward zero) *) +(*val integerDiv_t: Num.integer -> Num.integer -> Num.integer*) + +(* Truncation modulo *) +(*val integerRem_t: Num.integer -> Num.integer -> Num.integer*) + +(* Flooring modulo *) +(*val integerRem_f: Num.integer -> Num.integer -> Num.integer*) +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml b/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml new file mode 100644 index 00000000..34c8b4ae --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml @@ -0,0 +1,18 @@ +(*Generated by Lem from pervasives.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_basic_classesTheory lem_boolTheory lem_tupleTheory lem_maybeTheory lem_eitherTheory lem_functionTheory lem_numTheory lem_mapTheory lem_setTheory lem_listTheory lem_stringTheory lem_wordTheory lem_showTheory lem_sortingTheory lem_relationTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_pervasives" + + + +(*include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show*) + +(*import Sorting Relation*) + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml new file mode 100644 index 00000000..33ccd627 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml @@ -0,0 +1,16 @@ +(*Generated by Lem from pervasives_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_function_extraTheory lem_maybe_extraTheory lem_map_extraTheory lem_num_extraTheory lem_set_extraTheory lem_set_helpersTheory lem_list_extraTheory lem_string_extraTheory lem_assert_extraTheory lem_show_extraTheory lem_machine_wordTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_pervasives_extra" + + + +(*include import Pervasives*) +(*include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word*) +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_relationScript.sml b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml new file mode 100644 index 00000000..e73b66ce --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml @@ -0,0 +1,448 @@ +(*Generated by Lem from relation.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_tupleTheory lem_setTheory lem_numTheory set_relationTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_relation" + + + +(*open import Bool Basic_classes Tuple Set Num*) +(*open import {hol} `set_relationTheory`*) + +(* ========================================================================== *) +(* The type of relations *) +(* ========================================================================== *) + +val _ = type_abbrev((* ( 'a, 'b) *) "rel_pred" , ``: 'a -> 'b -> bool``); +val _ = type_abbrev((* ( 'a, 'b) *) "rel_set" , ``: ('a # 'b) set``); + +(* Binary relations are usually represented as either + sets of pairs (rel_set) or as curried functions (rel_pred). + + The choice depends on taste and the backend. Lem should not take a + decision, but supports both representations. There is an abstract type + pred, which can be converted to both representations. The representation + of pred itself then depends on the backend. However, for the time beeing, + let's implement relations as sets to get them working more quickly. *) + +val _ = type_abbrev((* ( 'a, 'b) *) "rel" , ``: ('a, 'b) rel_set``); + +(*val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b*) +(*val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b*) + +(*val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool*) +val _ = Define ` + ((relEq:('a#'b)set ->('a#'b)set -> bool) r1 r2= (r1 = r2))`; + + +(*val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b*) +(*val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b*) + +(*let relToPred r= (fun x y -> (x, y) IN relToSet r)*) +val _ = Define ` + ((relFromPred:'a set -> 'b set ->('a -> 'b -> bool) ->('a#'b)set) xs ys p= (SET_FILTER (\ (x,y) . p x y) (xs CROSS ys)))`; + + + +(* ========================================================================== *) +(* Basic Operations *) +(* ========================================================================== *) + +(* ----------------------- *) +(* membership test *) +(* ----------------------- *) + +(*val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool*) + + +(* ----------------------- *) +(* empty relation *) +(* ----------------------- *) + +(*val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b*) + +(* ----------------------- *) +(* Insertion *) +(* ----------------------- *) + +(*val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b*) + + +(* ----------------------- *) +(* Identity relation *) +(* ----------------------- *) + +(*val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a*) +val _ = Define ` + ((relIdOn:'a set ->('a#'a)set) s= (relFromPred s s (=)))`; + + +(*val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a*) +val _ = Define ` + ((relId:('a#'a)set)= ({(x, x) | x | T}))`; + + +(* ----------------------- *) +(* relation union *) +(* ----------------------- *) + +(*val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* relation intersection *) +(* ----------------------- *) + +(*val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* Relation Composition *) +(* ----------------------- *) + +(*val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c*) +(*let relComp r1 r2= relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}*) + +(* ----------------------- *) +(* restrict *) +(* ----------------------- *) + +(*val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +(*let relRestrict r s= relFromSet ({ (a, b) | forall (a IN s) (b IN s) | inRel a b r })*) + + +(* ----------------------- *) +(* Converse *) +(* ----------------------- *) + +(*val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a*) +val _ = Define ` + ((lem_converse:('a#'b)set ->('b#'a)set) r= (IMAGE SWAP (r)))`; + + + +(* ----------------------- *) +(* domain *) +(* ----------------------- *) + +(*val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a*) +(*let relDomain r= Set.map (fun x -> fst x) (relToSet r)*) + +(* ----------------------- *) +(* range *) +(* ----------------------- *) + +(*val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b*) +(*let relRange r= Set.map (fun x -> snd x) (relToSet r)*) + + +(* ----------------------- *) +(* field / definedOn *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a*) + +(* ----------------------- *) +(* relOver *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((rel_over:('a#'a)set -> 'a set -> bool) r s= ((((domain r) UNION (range r))) SUBSET s))`; + + + +(* ----------------------- *) +(* apply a relation *) +(* ----------------------- *) + +(* Given a relation r and a set s, relApply r s applies s to r, i.e. + it returns the set of all value reachable via r from a value in s. + This operation can be seen as a generalisation of function application. *) + +(*val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b*) +val _ = Define ` + ((rapply:('a#'b)set -> 'a set -> 'b set) r s= + ({ y | x, y | ((x, y) IN (r)) /\ (x IN s) }))`; + + + +(* ========================================================================== *) +(* Properties *) +(* ========================================================================== *) + +(* ----------------------- *) +(* subrel *) +(* ----------------------- *) + +(*val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool*) + +(* ----------------------- *) +(* reflexivity *) +(* ----------------------- *) + +(*val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_reflexive_on:('a#'a)set -> 'a set -> bool) r s= (! (e :: s). (e, e) IN r))`; + + +(*val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_reflexive:('a#'a)set -> bool) r= (! e. (e, e) IN r))`; + + + +(* ----------------------- *) +(* irreflexivity *) +(* ----------------------- *) + +(*val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +(*let isIrreflexiveOn r s= (forall (e IN s). not (inRel e e r))*) + +(*val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_irreflexive:('a#'a)set -> bool) r= (! ((e1, e2) :: (r)). ~ (e1 = e2)))`; + + + +(* ----------------------- *) +(* symmetry *) +(* ----------------------- *) + +(*val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_symmetric_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> ((e2, e1) IN r)))`; + + +(*val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_symmetric:('a#'a)set -> bool) r= (! ((e1, e2) :: r). (e2, e1) IN r))`; + + + +(* ----------------------- *) +(* antisymmetry *) +(* ----------------------- *) + +(*val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_antisymmetric_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> (((e2, e1) IN r) ==> (e1 = e2))))`; + + +(*val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isAntisymmetric r= (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))*) + + +(* ----------------------- *) +(* transitivity *) +(* ----------------------- *) + +(*val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_transitive_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s) (e3 :: s). ((e1, e2) IN r) ==> (((e2, e3) IN r) ==> ((e1, e3) IN r))))`; + + +(*val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isTransitive r= (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)*) + +(* ----------------------- *) +(* total *) +(* ----------------------- *) + +(*val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_total_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e2, e1) IN r)))`; + + + +(*val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_total:('a#'a)set -> bool) r= (! e1 e2. ((e1, e2) IN r) \/ ((e2, e1) IN r)))`; + + +(*val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_trichotomous_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`; + + +(*val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_trichotomous:('a#'a)set -> bool) r= (! e1 e2. ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`; + + + +(* ----------------------- *) +(* is_single_valued *) +(* ----------------------- *) + +(*val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool*) +val _ = Define ` + ((lem_is_single_valued:('a#'b)set -> bool) r= (! ((e1, e2a) :: r) (e2b :: rapply r {e1}). e2a = e2b))`; + + + +(* ----------------------- *) +(* equivalence relation *) +(* ----------------------- *) + +(*val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_equivalence_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_is_symmetric_on r s /\ lem_transitive_on r s))`; + + + +(*val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_equivalence:('a#'a)set -> bool) r= (lem_is_reflexive r /\ lem_is_symmetric r /\ transitive r))`; + + + +(* ----------------------- *) +(* well founded *) +(* ----------------------- *) + +(*val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let ~{ocaml;coq} isWellFounded r= (forall P. (forall x. (forall y. inRel y x r --> P x) --> P x) --> (forall x. P x))*) + + +(* ========================================================================== *) +(* Orders *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* pre- or quasiorders *) +(* ----------------------- *) + +(*val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_preorder_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_transitive_on r s))`; + + +(*val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_preorder:('a#'a)set -> bool) r= (lem_is_reflexive r /\ transitive r))`; + + + +(* ----------------------- *) +(* partial orders *) +(* ----------------------- *) + +(*val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_partial_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_transitive_on r s /\ lem_is_antisymmetric_on r s))`; + + + +(*val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_strict_partial_order_on:('a#'a)set -> 'a set -> bool) r s= (irreflexive r s /\ lem_transitive_on r s))`; + + + +(*val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_strict_partial_order:('a#'a)set -> bool) r= (lem_is_irreflexive r /\ transitive r))`; + + +(*val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_partial_order:('a#'a)set -> bool) r= (lem_is_reflexive r /\ transitive r /\ antisym r))`; + + +(* ----------------------- *) +(* total / linear orders *) +(* ----------------------- *) + +(*val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_total_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_partial_order_on r s /\ lem_is_total_on r s))`; + + +(*val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +val _ = Define ` + ((lem_is_strict_total_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_strict_partial_order_on r s /\ lem_is_trichotomous_on r s))`; + + +(*val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_total_order:('a#'a)set -> bool) r= (lem_is_partial_order r /\ lem_is_total r))`; + + +(*val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +val _ = Define ` + ((lem_is_strict_total_order:('a#'a)set -> bool) r= (lem_is_strict_partial_order r /\ lem_is_trichotomous r))`; + + + + +(* ========================================================================== *) +(* closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* transitive closure *) +(* ----------------------- *) + +(*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> Basic_classes.ordering) -> rel 'a 'a -> rel 'a 'a*) + + +(* ----------------------- *) +(* transitive closure step *) +(* ----------------------- *) + +(*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*) + +val _ = Define ` + ((tc_insert:'a -> 'a ->('a#'a)set ->('a#'a)set) x y r= + ((((((x,y) INSERT (r)))) UNION ((((({(x, z) | z | + (z IN range r) /\ ((y, z) IN r)})) UNION (({(z, y) | z | + (z IN domain r) /\ ((z, x) IN r)}))))))))`; + + + +(* ========================================================================== *) +(* reflexive closure *) +(* ========================================================================== *) + +(*val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +val _ = Define ` + ((reflexive_transitive_closure_on:('a#'a)set -> 'a set ->('a#'a)set) r s= (tc (((r) UNION ((relIdOn s))))))`; + + + +(*val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +val _ = Define ` + ((reflexiveTransitiveClosure:('a#'a)set ->('a#'a)set) r= (tc (((r) UNION (relId)))))`; + + + + +(* ========================================================================== *) +(* inverse of closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* without transitve edges *) +(* ----------------------- *) + +(*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +val _ = Define ` + ((withoutTransitiveEdges:('a#'a)set ->('a#'a)set) r= + (let tc1 = (tc r) in + {(a, c) | a, c + | ((a, c) IN r) /\ + (! (b :: range r). + ((a <> b) /\ (b <> c)) ==> ~ (((a, b) IN tc1) /\ ((b, c) IN tc1)))}))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_setScript.sml b/snapshots/hol4/lem/hol-lib/lem_setScript.sml new file mode 100644 index 00000000..7f553a68 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_setScript.sml @@ -0,0 +1,317 @@ +(*Generated by Lem from set.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_set_helpersTheory lemTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_set" + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets. + OCaml and Haskell both represent sets by some kind of balancing trees. This means + that sets are finite and an order on the element type is required. + Such sets are constructed by simple, executable operations like inserting or + deleting elements, union, intersection, filtering etc. + + On the other hand, we want to use sets for specifications. This leads often + infinite sets, which are specificied in complicated, perhaps even undecidable + ways. + + The set library in this file, chooses the first approach. It describes + *finite* sets with an underlying order. Infinite sets should in the medium + run be represented by a separate type. Since this would require some significant + changes to Lem, for the moment also infinite sets are represented using this + class. However, a run-time exception might occour when using these sets. + This problem needs adressing in the future. *) + + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Set_helpers*) + +(* DPM: sets currently implemented as lists due to mismatch between Coq type + * class hierarchy and the hierarchy implemented in Lem. + *) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* Equality check *) +(* ----------------------- *) + +(*val setEqualBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) + +(*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* Empty set *) +(* ----------------------- *) + +(*val empty : forall 'a. SetType 'a => set 'a*) +(*val emptyBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a*) + +(* ----------------------- *) +(* any / all *) +(* ----------------------- *) + +(*val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + +(*val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + + +(* ----------------------- *) +(* (IN) *) +(* ----------------------- *) + +(*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) +(*val memberBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* not (IN) *) +(* ----------------------- *) + +(*val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) + + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ------------------------ *) +(* singleton *) +(* ------------------------ *) + +(*val singletonBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a*) +(*val singleton : forall 'a. SetType 'a => 'a -> set 'a*) + + +(* ----------------------- *) +(* size *) +(* ----------------------- *) + +(*val size : forall 'a. SetType 'a => set 'a -> nat*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b*) + + +(* ------------------------ *) +(* union *) +(* ------------------------ *) + +(*val unionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) +(*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* insert *) +(* ----------------------- *) + +(*val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* filter *) +(* ----------------------- *) + +(*val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a*) +(*let filter P s= {e | forall (e IN s) | P e}*) + + +(* ----------------------- *) +(* partition *) +(* ----------------------- *) + +(*val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a*) +val _ = Define ` + ((SET_PARTITION:('a -> bool) -> 'a set -> 'a set#'a set) P s= (SET_FILTER P s, SET_FILTER (\ e . ~ (P e)) s))`; + + + +(* ----------------------- *) +(* split *) +(* ----------------------- *) + +(*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*) +val _ = Define ` + ((SET_SPLIT:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( + dict_Basic_classes_Ord_a.isGreater_method p) s, SET_FILTER (dict_Basic_classes_Ord_a.isLess_method p) s))`; + + +(*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*) +val _ = Define ` + ((splitMember:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#bool#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( + dict_Basic_classes_Ord_a.isLess_method p) s, (p IN s), SET_FILTER ( + dict_Basic_classes_Ord_a.isGreater_method p) s))`; + + +(* ------------------------ *) +(* subset and proper subset *) +(* ------------------------ *) + +(*val isSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) +(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) + +(*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) +(*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + + +(* ------------------------ *) +(* delete *) +(* ------------------------ *) + +(*val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a*) +(*val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* bigunion *) +(* ------------------------ *) + +(*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +(*val bigunionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set (set 'a) -> set 'a*) + +(*let bigunion bs= {x | forall (s IN bs) (x IN s) | true}*) + +(* ------------------------ *) +(* big intersection *) +(* ------------------------ *) + +(* Shaked's addition, for which he is now forever responsible as a de facto + * Lem maintainer... + *) +(*val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +val _ = Define ` + ((bigintersection:('a set)set -> 'a set) bs= + ({x | x | (x IN (BIGUNION bs)) /\ (! (s :: bs). x IN s)}))`; + + +(* ------------------------ *) +(* difference *) +(* ------------------------ *) + +(*val differenceBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) +(*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ------------------------ *) +(* intersection *) +(* ------------------------ *) + +(*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) +(*val intersectionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* map *) +(* ------------------------ *) + +(*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *) +(*let map f s= { f e | forall (e IN s) | true }*) + +(*val mapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> 'b) -> set 'a -> set 'b*) + + +(* ------------------------ *) +(* bigunionMap *) +(* ------------------------ *) + +(* In order to avoid providing an comparison function for sets of sets, + it might be better to combine bigunion and map sometimes into a single operation. *) + +(*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*) +(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> set 'b) -> set 'a -> set 'b*) + +(* ------------------------ *) +(* mapMaybe and fromMaybe *) +(* ------------------------ *) + +(* If the mapping function returns Just x, x is added to the result + set. If it returns Nothing, no element is added. *) + +(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> Maybe.maybe 'b) -> set 'a -> set 'b*) +val _ = Define ` + ((setMapMaybe:('a -> 'b option) -> 'a set -> 'b set) f s= + (BIGUNION (IMAGE (\ x . (case f x of + SOME y => {y} + | NONE => EMPTY + )) s)))`; + + +(*val removeMaybe : forall 'a. SetType 'a => set (Maybe.maybe 'a) -> set 'a*) +val _ = Define ` + ((removeMaybe:('a option)set -> 'a set) s= (setMapMaybe (\ x . x) s))`; + + +(* ------------------------ *) +(* min and max *) +(* ------------------------ *) + +(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*) +(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*) + +(* ------------------------ *) +(* fromList *) +(* ------------------------ *) + +(*val fromList : forall 'a. SetType 'a => list 'a -> set 'a*) (* before from_list *) +(*val fromListBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> set 'a*) + + +(* ------------------------ *) +(* Sigma *) +(* ------------------------ *) + +(*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*) +(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*) + +(*let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }*) + + +(* ------------------------ *) +(* cross product *) +(* ------------------------ *) + +(*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*) +(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> set 'b -> set ('a * 'b)*) + +(*let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*) + + +(* ------------------------ *) +(* finite *) +(* ------------------------ *) + +(*val finite : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ----------------------------*) +(* fixed point *) +(* --------------------------- *) + +(*val leastFixedPoint : forall 'a. SetType 'a + => nat -> (set 'a -> set 'a) -> set 'a -> set 'a*) + val leastFixedPoint_defn = Defn.Hol_multi_defns ` + ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) 0 f x= x) +/\ ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) ((SUC bound')) f x= (let fx = (f x) in + if fx SUBSET x then x + else leastFixedPoint bound' f (fx UNION x)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) leastFixedPoint_defn; +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml new file mode 100644 index 00000000..5409a408 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml @@ -0,0 +1,118 @@ +(*Generated by Lem from set_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_sortingTheory lem_setTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_set_extra" + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Sorting Set*) + + +(* ----------------------------*) +(* set choose (be careful !) *) +(* --------------------------- *) + +(*val choose : forall 'a. SetType 'a => set 'a -> 'a*) + +(* ------------------------ *) +(* chooseAndSplit *) +(* ------------------------ *) +(* The idea here is to provide a simple primitive that Lem code can use + * to perform its own custom searches within the set -- likely using a + * search criterion related to the element ordering, but not necessarily). + * For example, sometimes we don't necessarily want to search for a specific + * element, but want to search for elements greater than or less than some other. + * Someties we'd like to use "split" but don't know a good value to "split" at. + * This function lets the set implementation decide that value. + * + * The contract of chooseAndSplit is simply to select an element nondeterministically + * and return that element, together with the subsets of elements less than and + * greater than it. In this way, we can recursively traverse the set with any + * search criterion, and we avoid baking in the tree representation (although that + * is the obvious choice). + *) +(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> Maybe.maybe (set 'a * 'a * set 'a)*) +val _ = Define ` + ((chooseAndSplit:'a lem_basic_classes$Ord_class -> 'a set ->('a set#'a#'a set)option)dict_Basic_classes_Ord_a s= + (if s = EMPTY then + NONE + else + let element1 = (CHOICE s) in + let (lt, gt) = (lem_set$SET_SPLIT + dict_Basic_classes_Ord_a element1 s) in + SOME (lt, element1, gt)))`; + + +(* ----------------------------*) +(* universal set *) +(* --------------------------- *) + +(*val universal : forall 'a. SetType 'a => set 'a*) + + +(* ----------------------------*) +(* toList *) +(* --------------------------- *) + +(*val toList : forall 'a. SetType 'a => set 'a -> list 'a*) + + +(* ----------------------------*) +(* toOrderedList *) +(* --------------------------- *) + +(* "toOrderedList" returns a sorted list. Therefore the result is (given a suitable order) deterministic. + Therefore, it is much preferred to "toList". However, it still is only defined for finite sets. So, please + use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations + and then transforming back to sets. *) + +(*val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a*) + +(*val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a*) + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val setCompareBy: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> Basic_classes.ordering*) +val _ = Define ` + ((setCompareBy:('a -> 'a -> lem_basic_classes$ordering) -> 'a set -> 'a set -> lem_basic_classes$ordering) cmp ss ts= + (let ss' = (ARB (\ x y . cmp x y = LT) ss) in + let ts' = (ARB (\ x y . cmp x y = LT) ts) in + lexicographic_compare cmp ss' ts'))`; + + +(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> Basic_classes.ordering*) +val _ = Define ` + ((setCompare:'a lem_basic_classes$Ord_class -> 'a set -> 'a set -> lem_basic_classes$ordering)dict_Basic_classes_Ord_a= (setCompareBy + dict_Basic_classes_Ord_a.compare_method))`; + + +(* ----------------------------*) +(* unbounded fixed point *) +(* --------------------------- *) + +(* Is NOT supported by the coq backend! *) +(*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*) + val leastFixedPointUnbounded_defn = Hol_defn "leastFixedPointUnbounded" ` + ((leastFixedPointUnbounded:('a set -> 'a set) -> 'a set -> 'a set) f x= + (let fx = (f x) in + if fx SUBSET x then x + else leastFixedPointUnbounded f (fx UNION x)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn leastFixedPointUnbounded_defn; +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml b/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml new file mode 100644 index 00000000..5ce9f938 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml @@ -0,0 +1,47 @@ +(*Generated by Lem from set_helpers.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_set_helpers" + +(******************************************************************************) +(* Helper functions for sets *) +(******************************************************************************) + +(* Usually there is a something.lem file containing the main definitions and a + something_extra.lem one containing functions that might cause problems for + some backends or are just seldomly used. + + For sets the situation is different. folding is not well defined, since it + is only sensibly defined for finite sets and the traversal + order is underspecified. *) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num*) + +(*open import {coq} `Coq.Lists.List`*) + +(* ------------------------ *) +(* fold *) +(* ------------------------ *) + +(* fold is suspicious, because if given a function, for which + the order, in which the arguments are given, matters, its + results are undefined. On the other hand, it is very handy to + define other - non suspicious functions. + + Moreover, fold is central for OCaml, since it is used to + compile set comprehensions *) + +(*val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b*) + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_showScript.sml b/snapshots/hol4/lem/hol-lib/lem_showScript.sml new file mode 100644 index 00000000..1852c219 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_showScript.sml @@ -0,0 +1,85 @@ +(*Generated by Lem from show.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lemTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_show" + + + +(*open import String Maybe Num Basic_classes*) + +(*open import {hol} `lemTheory`*) + +val _ = Hol_datatype ` +(* 'a *) Show_class= <| + show_method: 'a -> string +|>`; + + +val _ = Define ` +((instance_Show_Show_string_dict:(string)Show_class)= (<| + + show_method := (\ s. STRCAT"\"" (STRCAT s "\""))|>))`; + + +(*val stringFromMaybe : forall 'a. ('a -> string) -> Maybe.maybe 'a -> string*) +val _ = Define ` + ((stringFromMaybe:('a -> string) -> 'a option -> string) showX (SOME x)= (STRCAT"Just (" (STRCAT(showX x) ")"))) +/\ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX NONE= "Nothing")`; + + +val _ = Define ` +((instance_Show_Show_Maybe_maybe_dict:'a Show_class ->('a option)Show_class)dict_Show_Show_a= (<| + + show_method := (\ x_opt. stringFromMaybe + dict_Show_Show_a.show_method x_opt)|>))`; + + +(*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*) + val stringFromListAux_defn = Defn.Hol_multi_defns ` + ((stringFromListAux:('a -> string) -> 'a list -> string) showX ([])= "") +/\ ((stringFromListAux:('a -> string) -> 'a list -> string) showX (x::xs')= + ((case xs' of + [] => showX x + | _ => STRCAT(showX x) (STRCAT"; " (stringFromListAux showX xs')) + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) stringFromListAux_defn; + +(*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*) +val _ = Define ` + ((stringFromList:('a -> string) -> 'a list -> string) showX xs= + (STRCAT"[" (STRCAT(stringFromListAux showX xs) "]")))`; + + +val _ = Define ` +((instance_Show_Show_list_dict:'a Show_class ->('a list)Show_class)dict_Show_Show_a= (<| + + show_method := (\ xs. stringFromList + dict_Show_Show_a.show_method xs)|>))`; + + +(*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*) +val _ = Define ` + ((stringFromPair:('a -> string) ->('b -> string) -> 'a#'b -> string) showX showY (x,y)= + (STRCAT"(" (STRCAT(showX x) (STRCAT", " (STRCAT(showY y) ")")))))`; + + +val _ = Define ` +((instance_Show_Show_tup2_dict:'a Show_class -> 'b Show_class ->('a#'b)Show_class)dict_Show_Show_a dict_Show_Show_b= (<| + + show_method := (stringFromPair + dict_Show_Show_a.show_method dict_Show_Show_b.show_method)|>))`; + + +val _ = Define ` +((instance_Show_Show_bool_dict:(bool)Show_class)= (<| + + show_method := (\ b. if b then "true" else "false")|>))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml new file mode 100644 index 00000000..d8e50e16 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml @@ -0,0 +1,67 @@ +(*Generated by Lem from show_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_setTheory lem_relationTheory lem_showTheory lem_set_extraTheory lem_string_extraTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_show_extra" + + + +(*open import String Maybe Num Basic_classes Set Relation Show*) +(*import Set_extra String_extra*) + +val _ = Define ` +((instance_Show_Show_nat_dict:(num)lem_show$Show_class)= (<| + + show_method := num_to_dec_string|>))`; + + +val _ = Define ` +((instance_Show_Show_Num_natural_dict:(num)lem_show$Show_class)= (<| + + show_method := num_to_dec_string|>))`; + + +val _ = Define ` +((instance_Show_Show_Num_int_dict:(int)lem_show$Show_class)= (<| + + show_method := lem_string_extra$stringFromInt|>))`; + + +val _ = Define ` +((instance_Show_Show_Num_integer_dict:(int)lem_show$Show_class)= (<| + + show_method := lem_string_extra$stringFromInteger|>))`; + + +val _ = Define ` + ((stringFromSet:('a -> string) -> 'a set -> string) showX xs= + (STRCAT"{" (STRCAT(lem_show$stringFromListAux showX (SET_TO_LIST xs)) "}")))`; + + +(* Abbreviates the representation if the relation is transitive. *) +val _ = Define ` + ((stringFromRelation:('a#'a -> string) ->('a#'a)set -> string) showX rel= + (if transitive rel then + let pruned_rel = (withoutTransitiveEdges rel) in + if (! (e :: rel). (e IN pruned_rel)) then + (* The relations are the same (there are no transitive edges), + so we can just as well print the original one. *) + stringFromSet showX rel + else + STRCAT"trancl of " (stringFromSet showX pruned_rel) + else + stringFromSet showX rel))`; + + +val _ = Define ` +((instance_Show_Show_set_dict:'a lem_show$Show_class ->('a set)lem_show$Show_class)dict_Show_Show_a= (<| + + show_method := (\ xs. stringFromSet + dict_Show_Show_a.show_method xs)|>))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml new file mode 100644 index 00000000..30f66e5e --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml @@ -0,0 +1,107 @@ +(*Generated by Lem from sorting.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_listTheory lem_numTheory sortingTheory permLib; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_sorting" + + + +(*open import Bool Basic_classes Maybe List Num*) + +(*open import {isabelle} `~~/src/HOL/Library/Permutation`*) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `sortingTheory` `permLib`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------- *) +(* permutations *) +(* ------------------------- *) + +(*val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + + val _ = Define ` + ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) l2= (NULL l2)) +/\ ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x :: xs) l2= (( + (case list_delete_first (eq x) l2 of + NONE => F + | SOME ys => PERM_BY eq xs ys + ) + )))`; + + + + +(* ------------------------- *) +(* isSorted *) +(* ------------------------- *) + +(* isSortedBy R l + checks, whether the list l is sorted by ordering R. + R should represent an order, i.e. it should be transitive. + Different backends defined "isSorted" slightly differently. However, + the definitions coincide for transitive R. Therefore there is the + following restriction: + + WARNING: Use isSorted and isSortedBy only with transitive relations! +*) + +(*val isSorted : forall 'a. Ord 'a => list 'a -> bool*) +(*val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool*) + +(* DPM: rejigged the definition with a nested match to get past Coq's termination checker. *) +(*let rec isSortedBy cmp l= match l with + | [] -> true + | x1 :: xs -> + match xs with + | [] -> true + | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs) + end +end*) + + +(* ----------------------- *) +(* insertion sort *) +(* ----------------------- *) + +(*val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a*) +(*val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +(*val insertSort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) + + val _ = Define ` + ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e ([])= ([e])) +/\ ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e (x :: xs)= (if cmp x e then x :: (INSERT_SORT_INSERT cmp e xs) else (e :: (x :: xs))))`; + + +val _ = Define ` + ((INSERT_SORT:('a -> 'a -> bool) -> 'a list -> 'a list) cmp l= (FOLDL (\ l e . INSERT_SORT_INSERT cmp e l) [] l))`; + + + +(* ----------------------- *) +(* general sorting *) +(* ----------------------- *) + +(*val sort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) +(*val sortByOrd: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a*) + +(*val predicate_of_ord : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> 'a -> bool*) +val _ = Define ` + ((predicate_of_ord:('a -> 'a -> lem_basic_classes$ordering) -> 'a -> 'a -> bool) f x y= + ((case f x y of + LT => T + | EQ => T + | GT => F + )))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_stringScript.sml b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml new file mode 100644 index 00000000..9dd53778 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml @@ -0,0 +1,74 @@ +(*Generated by Lem from string.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory lem_listTheory lemTheory stringTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_string" + + + +(*open import Bool Basic_classes List*) +(*open import {ocaml} `Xstring`*) +(*open import {hol} `lemTheory` `stringTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) + +(* ------------------------------------------- *) +(* translations between strings and char lists *) +(* ------------------------------------------- *) + +(*val toCharList : string -> list char*) + +(*val toString : list char -> string*) + + +(* ----------------------- *) +(* generating strings *) +(* ----------------------- *) + +(*val makeString : nat -> char -> string*) +(*let makeString len c= toString (replicate len c)*) + +(* ----------------------- *) +(* length *) +(* ----------------------- *) + +(*val stringLength : string -> nat*) + +(* ----------------------- *) +(* string concatenation *) +(* ----------------------- *) + +(*val ^ [stringAppend] : string -> string -> string*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*) + +(*let string_case s c_empty c_cons= + match (toCharList s) with + | [] -> c_empty + | c :: cs -> c_cons c (toString cs) + end*) + +(*val empty_string : string*) + +(*val cons_string : char -> string -> string*) + +(*val concat : string -> list string -> string*) + val concat_defn = Defn.Hol_multi_defns ` + ((concat:string ->(string)list -> string) sep ([])= "") +/\ ((concat:string ->(string)list -> string) sep (s :: ss')= + ((case ss' of + [] => s + | _ => STRCAT s (STRCAT sep (concat sep ss')) + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) concat_defn; +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml new file mode 100644 index 00000000..0801601a --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml @@ -0,0 +1,124 @@ +(*Generated by Lem from string_extra.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_numTheory lem_listTheory lem_basic_classesTheory lem_stringTheory lem_list_extraTheory ASCIInumbersTheory stringLib; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_string_extra" + +(******************************************************************************) +(* String functions *) +(******************************************************************************) + +(*open import Basic_classes*) +(*open import Num*) +(*open import List*) +(*open import String*) +(*open import List_extra*) +(*open import {hol} `stringLib`*) +(*open import {hol} `ASCIInumbersTheory`*) + + +(******************************************************************************) +(* Character's to numbers *) +(******************************************************************************) + +(*val ord : char -> nat*) + +(*val chr : nat -> char*) + +(******************************************************************************) +(* Converting to strings *) +(******************************************************************************) + +(*val stringFromNatHelper : nat -> list char -> list char*) + val stringFromNatHelper_defn = Hol_defn "stringFromNatHelper" ` + ((stringFromNatHelper:num ->(char)list ->(char)list) n acc= + (if n =( 0 : num) then + acc + else + stringFromNatHelper (n DIV( 10 : num)) (CHR ((n MOD( 10 : num)) +( 48 : num)) :: acc)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNatHelper_defn; + +(*val stringFromNat : nat -> string*) + +(*val stringFromNaturalHelper : Num.natural -> list char -> list char*) + val stringFromNaturalHelper_defn = Hol_defn "stringFromNaturalHelper" ` + ((stringFromNaturalHelper:num ->(char)list ->(char)list) n acc= + (if n =( 0:num) then + acc + else + stringFromNaturalHelper (n DIV( 10:num)) (CHR ((((n MOD( 10:num)) +( 48:num)):num)) :: acc)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNaturalHelper_defn; + +(*val stringFromNatural : Num.natural -> string*) + +(*val stringFromInt : Num.int -> string*) +val _ = Define ` + ((stringFromInt:int -> string) i= + (if i <( 0 : int) then + STRCAT"-" (num_to_dec_string (Num (ABS i))) + else + num_to_dec_string (Num (ABS i))))`; + + +(*val stringFromInteger : Num.integer -> string*) +val _ = Define ` + ((stringFromInteger:int -> string) i= + (if i <( 0 : int) then + STRCAT"-" (num_to_dec_string (Num (ABS i))) + else + num_to_dec_string (Num (ABS i))))`; + + + +(******************************************************************************) +(* List-like operations *) +(******************************************************************************) + +(*val nth : string -> nat -> char*) +(*let nth s n= List_extra.nth (toCharList s) n*) + +(*val stringConcat : list string -> string*) +(*let stringConcat s= + List.foldr (^) "" s*) + +(******************************************************************************) +(* String comparison *) +(******************************************************************************) + +(*val stringCompare : string -> string -> Basic_classes.ordering*) + +val _ = Define ` + ((stringLess:string -> string -> bool) x y= (orderingIsLess (EQ)))`; + +val _ = Define ` + ((stringLessEq:string -> string -> bool) x y= (~ (orderingIsGreater (EQ))))`; + +val _ = Define ` + ((stringGreater:string -> string -> bool) x y= (stringLess y x))`; + +val _ = Define ` + ((stringGreaterEq:string -> string -> bool) x y= (stringLessEq y x))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_string_dict:(string)lem_basic_classes$Ord_class)= (<| + + compare_method := (\ x y. EQ); + + isLess_method := stringLess; + + isLessEqual_method := stringLessEq; + + isGreater_method := stringGreater; + + isGreaterEqual_method := stringGreaterEq|>))`; + + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml b/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml new file mode 100644 index 00000000..7ee21f63 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml @@ -0,0 +1,51 @@ +(*Generated by Lem from tuple.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_basic_classesTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_tuple" + + + +(*open import Bool Basic_classes*) + +(* ----------------------- *) +(* fst *) +(* ----------------------- *) + +(*val fst : forall 'a 'b. 'a * 'b -> 'a*) +(*let fst (v1, v2)= v1*) + +(* ----------------------- *) +(* snd *) +(* ----------------------- *) + +(*val snd : forall 'a 'b. 'a * 'b -> 'b*) +(*let snd (v1, v2)= v2*) + + +(* ----------------------- *) +(* curry *) +(* ----------------------- *) + +(*val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)*) + +(* ----------------------- *) +(* uncurry *) +(* ----------------------- *) + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) + + +(* ----------------------- *) +(* swap *) +(* ----------------------- *) + +(*val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)*) +(*let swap (v1, v2)= (v2, v1)*) + +val _ = export_theory() + diff --git a/snapshots/hol4/lem/hol-lib/lem_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml new file mode 100644 index 00000000..690909a0 --- /dev/null +++ b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml @@ -0,0 +1,1021 @@ +(*Generated by Lem from word.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_boolTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_listTheory wordsTheory wordsLib; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "lem_word" + + + +(*open import Bool Maybe Num Basic_classes List*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib`*) + + +(* ========================================================================== *) +(* Define general purpose word, i.e. sequences of bits of arbitrary length *) +(* ========================================================================== *) + +val _ = Hol_datatype ` + bitSequence = BitSeq of + num option => (* length of the sequence, Nothing means infinite length *) + bool => bool (* sign of the word, used to fill up after concrete value is exhausted *) + list`; + (* the initial part of the sequence, least significant bit first *) + +(*val bitSeqEq : bitSequence -> bitSequence -> bool*) + +(*val boolListFrombitSeq : nat -> bitSequence -> list bool*) + + val _ = Define ` + ((boolListFrombitSeqAux:num -> 'a -> 'a list -> 'a list) n s bl= + (if n =( 0 : num) then [] else + (case bl of + [] => REPLICATE n s + | b :: bl' => b :: (boolListFrombitSeqAux (n -( 1 : num)) s bl') + )))`; + + +val _ = Define ` + ((boolListFrombitSeq:num -> bitSequence ->(bool)list) n (BitSeq _ s bl)= (boolListFrombitSeqAux n s bl))`; + + + +(*val bitSeqFromBoolList : list bool -> Maybe.maybe bitSequence*) +val _ = Define ` + ((bitSeqFromBoolList:(bool)list ->(bitSequence)option) bl= + ((case dest_init bl of + NONE => NONE + | SOME (bl', s) => SOME (BitSeq (SOME (LENGTH bl)) s bl') + )))`; + + + +(* cleans up the representation of a bitSequence without changing its semantics *) +(*val cleanBitSeq : bitSequence -> bitSequence*) +val _ = Define ` + ((cleanBitSeq:bitSequence -> bitSequence) (BitSeq len s bl)= ((case len of + NONE => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE bl)))) + | SOME n => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE (TAKE (n -( 1 : num)) bl))))) +)))`; + + + +(*val bitSeqTestBit : bitSequence -> nat -> Maybe.maybe bool*) +val _ = Define ` + ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq NONE s bl) pos= (if pos < LENGTH bl then list_index bl pos else SOME s)) +/\ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq(SOME l) s bl) pos= (if (pos >= l) then NONE else + if ((pos = (l -( 1 : num))) \/ (pos >= LENGTH bl)) then SOME s else + list_index bl pos))`; + + +(*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*) +val _ = Define ` + ((bitSeqSetBit:bitSequence -> num -> bool -> bitSequence) (BitSeq len s bl) pos v= + (let bl' = (if (pos < LENGTH bl) then bl else bl ++ REPLICATE pos s) in + let bl'' = (LUPDATE v pos bl') in + let bs' = (BitSeq len s bl'') in + cleanBitSeq bs'))`; + + + +(*val resizeBitSeq : Maybe.maybe nat -> bitSequence -> bitSequence*) +val _ = Define ` + ((resizeBitSeq:(num)option -> bitSequence -> bitSequence) new_len bs= + ((case cleanBitSeq bs of + (BitSeq len s bl) => + let shorten_opt = ((case (new_len, len) of + (NONE, _) => NONE + | (SOME l1, NONE) => SOME l1 + | (SOME l1, SOME l2) => + if (l1 < l2) then SOME l1 else NONE + )) in + (case shorten_opt of + NONE => BitSeq new_len s bl + | SOME l1 => ( + let bl' = (TAKE l1 (bl ++ [s])) in + (case dest_init bl' of + NONE => (BitSeq len s bl) (* do nothing if size 0 is requested *) + | SOME (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'') + )) + ) + )))`; + + +(*val bitSeqNot : bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqNot:bitSequence -> bitSequence) (BitSeq len s bl)= (BitSeq len (~ s) (MAP (\ x. ~ x) bl)))`; + + +(*val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence*) + +(*val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool*) + val _ = Define ` + ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 ([])= ([])) +/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 ([])= ((binop b1 s2) :: bitSeqBinopAux binop s1 bl1' s2 [])) +/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 (b2 :: bl2')= ((binop s1 b2) :: bitSeqBinopAux binop s1 [] s2 bl2')) +/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 (b2 :: bl2')= ((binop b1 b2) :: bitSeqBinopAux binop s1 bl1' s2 bl2'))`; + + +val _ = Define ` + ((bitSeqBinop:(bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2= ( + (case cleanBitSeq bs1 of + (BitSeq len1 s1 bl1) => + (case cleanBitSeq bs2 of + (BitSeq len2 s2 bl2) => + let len = ((case (len1, len2) of + (SOME l1, SOME l2) => SOME (MAX l1 l2) + | _ => NONE + )) in + let s = (binop s1 s2) in + let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in + cleanBitSeq (BitSeq len s bl) + ) + ) +))`; + + +val _ = Define ` + ((bitSeqAnd:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (/\)))`; + +val _ = Define ` + ((bitSeqOr:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (\/)))`; + +val _ = Define ` + ((bitSeqXor:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (\ b1 b2. ~ (b1 <=> b2))))`; + + +(*val bitSeqShiftLeft : bitSequence -> nat -> bitSequence*) +val _ = Define ` + ((bitSeqShiftLeft:bitSequence -> num -> bitSequence) (BitSeq len s bl) n= (cleanBitSeq (BitSeq len s (REPLICATE n F ++ bl))))`; + + +(*val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence*) +val _ = Define ` + ((bitSeqArithmeticShiftRight:bitSequence -> num -> bitSequence) bs n= + ((case cleanBitSeq bs of + (BitSeq len s bl) => + cleanBitSeq (BitSeq len s (DROP n bl)) + )))`; + + +(*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*) +val _ = Define ` + ((bitSeqLogicalShiftRight:bitSequence -> num -> bitSequence) bs n= + (if (n =( 0 : num)) then cleanBitSeq bs else + (case cleanBitSeq bs of + (BitSeq len s bl) => + (case len of + NONE => cleanBitSeq (BitSeq len s (DROP n bl)) + | SOME l => cleanBitSeq (BitSeq len F ((DROP n bl) ++ REPLICATE l s)) + ) + )))`; + + + +(* integerFromBoolList sign bl creates an integer from a list of bits + (least significant bit first) and an explicitly given sign bit. + It uses two's complement encoding. *) +(*val integerFromBoolList : (bool * list bool) -> Num.integer*) + + val _ = Define ` + ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) (([]) : bool list)= acc) +/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((T :: bl') : bool list)= (integerFromBoolListAux ((acc *( 2 : int)) +( 1 : int)) bl')) +/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((F :: bl') : bool list)= (integerFromBoolListAux (acc *( 2 : int)) bl'))`; + + +val _ = Define ` + ((integerFromBoolList:bool#(bool)list -> int) (sign, bl)= + (if sign then + ~ (integerFromBoolListAux(( 0 : int)) (REVERSE (MAP (\ x. ~ x) bl)) +( 1 : int)) + else integerFromBoolListAux(( 0 : int)) (REVERSE bl)))`; + + +(* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*) +(*val boolListFromInteger : Num.integer -> bool * list bool*) + + val _ = Define ` + ((boolListFromNatural:(bool)list -> num ->(bool)list) acc (remainder : num)= + (if (remainder >( 0:num)) then + (boolListFromNatural (((remainder MOD( 2:num)) =( 1:num)) :: acc) + (remainder DIV( 2:num))) + else + REVERSE acc))`; + + +val _ = Define ` + ((boolListFromInteger:int -> bool#(bool)list) (i : int)= + (if (i <( 0 : int)) then + (T, MAP (\ x. ~ x) (boolListFromNatural [] (Num (ABS (~ (i +( 1 : int))))))) + else + (F, boolListFromNatural [] (Num (ABS i)))))`; + + + +(* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough + bits, truncation happens *) +(*val bitSeqFromInteger : Maybe.maybe nat -> Num.integer -> bitSequence*) +val _ = Define ` + ((bitSeqFromInteger:(num)option -> int -> bitSequence) len_opt i= + (let (s, bl) = (boolListFromInteger i) in + resizeBitSeq len_opt (BitSeq NONE s bl)))`; + + + +(*val integerFromBitSeq : bitSequence -> Num.integer*) +val _ = Define ` + ((integerFromBitSeq:bitSequence -> int) bs= + ((case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) )))`; + + + +(* Now we can via translation to integers map arithmetic operations to bitSequences *) + +(*val bitSeqArithUnaryOp : (Num.integer -> Num.integer) -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqArithUnaryOp:(int -> int) -> bitSequence -> bitSequence) uop bs= + ((case bs of + (BitSeq len _ _) => + bitSeqFromInteger len (uop (integerFromBitSeq bs)) + )))`; + + +(*val bitSeqArithBinOp : (Num.integer -> Num.integer -> Num.integer) -> bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqArithBinOp:(int -> int -> int) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2= + ((case bs1 of + (BitSeq len1 _ _) => + (case bs2 of + (BitSeq len2 _ _) => + let len = ((case (len1, len2) of + (SOME l1, SOME l2) => SOME (MAX l1 l2) + | _ => NONE + )) in + bitSeqFromInteger len + (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)) + ) + )))`; + + +(*val bitSeqArithBinTest : forall 'a. (Num.integer -> Num.integer -> 'a) -> bitSequence -> bitSequence -> 'a*) +val _ = Define ` + ((bitSeqArithBinTest:(int -> int -> 'a) -> bitSequence -> bitSequence -> 'a) binop bs1 bs2= (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)))`; + + + +(* now instantiate the number interface for bit-sequences *) + +(*val bitSeqFromNumeral : numeral -> bitSequence*) + +(*val bitSeqLess : bitSequence -> bitSequence -> bool*) +val _ = Define ` + ((bitSeqLess:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (<) bs1 bs2))`; + + +(*val bitSeqLessEqual : bitSequence -> bitSequence -> bool*) +val _ = Define ` + ((bitSeqLessEqual:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (<=) bs1 bs2))`; + + +(*val bitSeqGreater : bitSequence -> bitSequence -> bool*) +val _ = Define ` + ((bitSeqGreater:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (>) bs1 bs2))`; + + +(*val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool*) +val _ = Define ` + ((bitSeqGreaterEqual:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (>=) bs1 bs2))`; + + +(*val bitSeqCompare : bitSequence -> bitSequence -> Basic_classes.ordering*) +val _ = Define ` + ((bitSeqCompare:bitSequence -> bitSequence -> lem_basic_classes$ordering) bs1 bs2= (bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_Word_bitSequence_dict:(bitSequence)lem_basic_classes$Ord_class)= (<| + + compare_method := bitSeqCompare; + + isLess_method := bitSeqLess; + + isLessEqual_method := bitSeqLessEqual; + + isGreater_method := bitSeqGreater; + + isGreaterEqual_method := bitSeqGreaterEqual|>))`; + + +(* arithmetic negation, don't mix up with bitwise negation *) +(*val bitSeqNegate : bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqNegate:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ i. ~ i) bs))`; + + +val _ = Define ` +((instance_Num_NumNegate_Word_bitSequence_dict:(bitSequence)lem_num$NumNegate_class)= (<| + + numNegate_method := bitSeqNegate|>))`; + + + +(*val bitSeqAdd : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqAdd:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (+) bs1 bs2))`; + + +val _ = Define ` +((instance_Num_NumAdd_Word_bitSequence_dict:(bitSequence)lem_num$NumAdd_class)= (<| + + numAdd_method := bitSeqAdd|>))`; + + +(*val bitSeqMinus : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqMinus:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (-) bs1 bs2))`; + + +val _ = Define ` +((instance_Num_NumMinus_Word_bitSequence_dict:(bitSequence)lem_num$NumMinus_class)= (<| + + numMinus_method := bitSeqMinus|>))`; + + +(*val bitSeqSucc : bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqSucc:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ n. n +( 1 : int)) bs))`; + + +val _ = Define ` +((instance_Num_NumSucc_Word_bitSequence_dict:(bitSequence)lem_num$NumSucc_class)= (<| + + succ_method := bitSeqSucc|>))`; + + +(*val bitSeqPred : bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqPred:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ n. n -( 1 : int)) bs))`; + + +val _ = Define ` +((instance_Num_NumPred_Word_bitSequence_dict:(bitSequence)lem_num$NumPred_class)= (<| + + pred_method := bitSeqPred|>))`; + + +(*val bitSeqMult : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqMult:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp ( * ) bs1 bs2))`; + + +val _ = Define ` +((instance_Num_NumMult_Word_bitSequence_dict:(bitSequence)lem_num$NumMult_class)= (<| + + numMult_method := bitSeqMult|>))`; + + + +(*val bitSeqPow : bitSequence -> nat -> bitSequence*) +val _ = Define ` + ((bitSeqPow:bitSequence -> num -> bitSequence) bs n= (bitSeqArithUnaryOp (\ i . i ** n) bs))`; + + +val _ = Define ` +((instance_Num_NumPow_Word_bitSequence_dict:(bitSequence)lem_num$NumPow_class)= (<| + + numPow_method := bitSeqPow|>))`; + + +(*val bitSeqDiv : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqDiv:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (/) bs1 bs2))`; + + +val _ = Define ` +((instance_Num_NumIntegerDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumIntegerDivision_class)= (<| + + div_method := bitSeqDiv|>))`; + + +val _ = Define ` +((instance_Num_NumDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumDivision_class)= (<| + + numDivision_method := bitSeqDiv|>))`; + + +(*val bitSeqMod : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqMod:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (%) bs1 bs2))`; + + +val _ = Define ` +((instance_Num_NumRemainder_Word_bitSequence_dict:(bitSequence)lem_num$NumRemainder_class)= (<| + + mod_method := bitSeqMod|>))`; + + +(*val bitSeqMin : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqMin:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp int_min bs1 bs2))`; + + +(*val bitSeqMax : bitSequence -> bitSequence -> bitSequence*) +val _ = Define ` + ((bitSeqMax:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp int_max bs1 bs2))`; + + +val _ = Define ` +((instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict:(bitSequence)lem_basic_classes$OrdMaxMin_class)= (<| + + max_method := bitSeqMax; + + min_method := bitSeqMin|>))`; + + + + + +(* ========================================================================== *) +(* Interface for bitoperations *) +(* ========================================================================== *) + +val _ = Hol_datatype ` +(* 'a *) WordNot_class= <| + lnot_method : 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) WordAnd_class= <| + land_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) WordOr_class= <| + lor_method : 'a -> 'a -> 'a +|>`; + + + +val _ = Hol_datatype ` +(* 'a *) WordXor_class= <| + lxor_method : 'a -> 'a -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) WordLsl_class= <| + lsl_method : 'a -> num -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) WordLsr_class= <| + lsr_method : 'a -> num -> 'a +|>`; + + +val _ = Hol_datatype ` +(* 'a *) WordAsr_class= <| + asr_method : 'a -> num -> 'a +|>`; + + +(* ----------------------- *) +(* bitSequence *) +(* ----------------------- *) + +val _ = Define ` +((instance_Word_WordNot_Word_bitSequence_dict:(bitSequence)WordNot_class)= (<| + + lnot_method := bitSeqNot|>))`; + + +val _ = Define ` +((instance_Word_WordAnd_Word_bitSequence_dict:(bitSequence)WordAnd_class)= (<| + + land_method := bitSeqAnd|>))`; + + +val _ = Define ` +((instance_Word_WordOr_Word_bitSequence_dict:(bitSequence)WordOr_class)= (<| + + lor_method := bitSeqOr|>))`; + + +val _ = Define ` +((instance_Word_WordXor_Word_bitSequence_dict:(bitSequence)WordXor_class)= (<| + + lxor_method := bitSeqXor|>))`; + + +val _ = Define ` +((instance_Word_WordLsl_Word_bitSequence_dict:(bitSequence)WordLsl_class)= (<| + + lsl_method := bitSeqShiftLeft|>))`; + + +val _ = Define ` +((instance_Word_WordLsr_Word_bitSequence_dict:(bitSequence)WordLsr_class)= (<| + + lsr_method := bitSeqLogicalShiftRight|>))`; + + +val _ = Define ` +((instance_Word_WordAsr_Word_bitSequence_dict:(bitSequence)WordAsr_class)= (<| + + asr_method := bitSeqArithmeticShiftRight|>))`; + + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) + +(*val int32Lnot : Num.int32 -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordNot_Num_int32_dict:(word32)WordNot_class)= (<| + + lnot_method := (\ w. (~ w))|>))`; + + + +(*val int32Lor : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordOr_Num_int32_dict:(word32)WordOr_class)= (<| + + lor_method := word_or|>))`; + + +(*val int32Lxor : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordXor_Num_int32_dict:(word32)WordXor_class)= (<| + + lxor_method := word_xor|>))`; + + +(*val int32Land : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordAnd_Num_int32_dict:(word32)WordAnd_class)= (<| + + land_method := word_and|>))`; + + +(*val int32Lsl : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordLsl_Num_int32_dict:(word32)WordLsl_class)= (<| + + lsl_method := word_lsl|>))`; + + +(*val int32Lsr : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordLsr_Num_int32_dict:(word32)WordLsr_class)= (<| + + lsr_method := word_lsr|>))`; + + + +(*val int32Asr : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordAsr_Num_int32_dict:(word32)WordAsr_class)= (<| + + asr_method := word_asr|>))`; + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) + +(*val int64Lnot : Num.int64 -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordNot_Num_int64_dict:(word64)WordNot_class)= (<| + + lnot_method := (\ w. (~ w))|>))`; + + +(*val int64Lor : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordOr_Num_int64_dict:(word64)WordOr_class)= (<| + + lor_method := word_or|>))`; + + +(*val int64Lxor : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordXor_Num_int64_dict:(word64)WordXor_class)= (<| + + lxor_method := word_xor|>))`; + + +(*val int64Land : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordAnd_Num_int64_dict:(word64)WordAnd_class)= (<| + + land_method := word_and|>))`; + + +(*val int64Lsl : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordLsl_Num_int64_dict:(word64)WordLsl_class)= (<| + + lsl_method := word_lsl|>))`; + + +(*val int64Lsr : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordLsr_Num_int64_dict:(word64)WordLsr_class)= (<| + + lsr_method := word_lsr|>))`; + + +(*val int64Asr : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) + +val _ = Define ` +((instance_Word_WordAsr_Num_int64_dict:(word64)WordAsr_class)= (<| + + asr_method := word_asr|>))`; + + + +(* ----------------------- *) +(* Words via bit sequences *) +(* ----------------------- *) + +(*val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a*) +val _ = Define ` + ((defaultLnot:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a) fromBitSeq toBitSeq x= (fromBitSeq (bitSeqNegate (toBitSeq x))))`; + + +(*val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +val _ = Define ` + ((defaultLand:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2))))`; + + +(*val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +val _ = Define ` + ((defaultLor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2))))`; + + +(*val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +val _ = Define ` + ((defaultLxor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2))))`; + + +(*val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +val _ = Define ` + ((defaultLsl:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqShiftLeft (toBitSeq x) n)))`; + + +(*val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +val _ = Define ` + ((defaultLsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n)))`; + + +(*val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +val _ = Define ` + ((defaultAsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n)))`; + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerLnot : Num.integer -> Num.integer*) +val _ = Define ` + ((integerLnot:int -> int) i= (~ (i +( 1 : int))))`; + + +val _ = Define ` +((instance_Word_WordNot_Num_integer_dict:(int)WordNot_class)= (<| + + lnot_method := integerLnot|>))`; + + + +(*val integerLor : Num.integer -> Num.integer -> Num.integer*) +val _ = Define ` + ((integerLor:int -> int -> int) i1 i2= (defaultLor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordOr_Num_integer_dict:(int)WordOr_class)= (<| + + lor_method := integerLor|>))`; + + +(*val integerLxor : Num.integer -> Num.integer -> Num.integer*) +val _ = Define ` + ((integerLxor:int -> int -> int) i1 i2= (defaultLxor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordXor_Num_integer_dict:(int)WordXor_class)= (<| + + lxor_method := integerLxor|>))`; + + +(*val integerLand : Num.integer -> Num.integer -> Num.integer*) +val _ = Define ` + ((integerLand:int -> int -> int) i1 i2= (defaultLand integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordAnd_Num_integer_dict:(int)WordAnd_class)= (<| + + land_method := integerLand|>))`; + + +(*val integerLsl : Num.integer -> nat -> Num.integer*) +val _ = Define ` + ((integerLsl:int -> num -> int) i n= (defaultLsl integerFromBitSeq (bitSeqFromInteger NONE) i n))`; + + +val _ = Define ` +((instance_Word_WordLsl_Num_integer_dict:(int)WordLsl_class)= (<| + + lsl_method := integerLsl|>))`; + + +(*val integerAsr : Num.integer -> nat -> Num.integer*) +val _ = Define ` + ((integerAsr:int -> num -> int) i n= (defaultAsr integerFromBitSeq (bitSeqFromInteger NONE) i n))`; + + +val _ = Define ` +((instance_Word_WordLsr_Num_integer_dict:(int)WordLsr_class)= (<| + + lsr_method := integerAsr|>))`; + + +val _ = Define ` +((instance_Word_WordAsr_Num_integer_dict:(int)WordAsr_class)= (<| + + asr_method := integerAsr|>))`; + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on ints. + However, since int is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of int *) + +(*val intFromBitSeq : bitSequence -> Num.int*) +val _ = Define ` + ((intFromBitSeq:bitSequence -> int) bs= (I (integerFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs))))`; + + + +(*val bitSeqFromInt : Num.int -> bitSequence*) +val _ = Define ` + ((bitSeqFromInt:int -> bitSequence) i= (bitSeqFromInteger (SOME(( 31 : num))) ( i)))`; + + + +(*val intLnot : Num.int -> Num.int*) +val _ = Define ` + ((intLnot:int -> int) i= (~ (i +( 1 : int))))`; + + +val _ = Define ` +((instance_Word_WordNot_Num_int_dict:(int)WordNot_class)= (<| + + lnot_method := intLnot|>))`; + + +(*val intLor : Num.int -> Num.int -> Num.int*) +val _ = Define ` + ((intLor:int -> int -> int) i1 i2= (defaultLor intFromBitSeq bitSeqFromInt i1 i2))`; + + +val _ = Define ` +((instance_Word_WordOr_Num_int_dict:(int)WordOr_class)= (<| + + lor_method := intLor|>))`; + + +(*val intLxor : Num.int -> Num.int -> Num.int*) +val _ = Define ` + ((intLxor:int -> int -> int) i1 i2= (defaultLxor intFromBitSeq bitSeqFromInt i1 i2))`; + + +val _ = Define ` +((instance_Word_WordXor_Num_int_dict:(int)WordXor_class)= (<| + + lxor_method := intLxor|>))`; + + +(*val intLand : Num.int -> Num.int -> Num.int*) +val _ = Define ` + ((intLand:int -> int -> int) i1 i2= (defaultLand intFromBitSeq bitSeqFromInt i1 i2))`; + + +val _ = Define ` +((instance_Word_WordAnd_Num_int_dict:(int)WordAnd_class)= (<| + + land_method := intLand|>))`; + + +(*val intLsl : Num.int -> nat -> Num.int*) +val _ = Define ` + ((intLsl:int -> num -> int) i n= (defaultLsl intFromBitSeq bitSeqFromInt i n))`; + + +val _ = Define ` +((instance_Word_WordLsl_Num_int_dict:(int)WordLsl_class)= (<| + + lsl_method := intLsl|>))`; + + +(*val intAsr : Num.int -> nat -> Num.int*) +val _ = Define ` + ((intAsr:int -> num -> int) i n= (defaultAsr intFromBitSeq bitSeqFromInt i n))`; + + +val _ = Define ` +((instance_Word_WordAsr_Num_int_dict:(int)WordAsr_class)= (<| + + asr_method := intAsr|>))`; + + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* some operations work also on positive numbers *) + +(*val naturalFromBitSeq : bitSequence -> Num.natural*) +val _ = Define ` + ((naturalFromBitSeq:bitSequence -> num) bs= (Num (ABS (integerFromBitSeq bs))))`; + + +(*val bitSeqFromNatural : Maybe.maybe nat -> Num.natural -> bitSequence*) +val _ = Define ` + ((bitSeqFromNatural:(num)option -> num -> bitSequence) len n= (bitSeqFromInteger len (int_of_num n)))`; + + +(*val naturalLor : Num.natural -> Num.natural -> Num.natural*) +val _ = Define ` + ((naturalLor:num -> num -> num) i1 i2= (defaultLor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordOr_Num_natural_dict:(num)WordOr_class)= (<| + + lor_method := naturalLor|>))`; + + +(*val naturalLxor : Num.natural -> Num.natural -> Num.natural*) +val _ = Define ` + ((naturalLxor:num -> num -> num) i1 i2= (defaultLxor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordXor_Num_natural_dict:(num)WordXor_class)= (<| + + lxor_method := naturalLxor|>))`; + + +(*val naturalLand : Num.natural -> Num.natural -> Num.natural*) +val _ = Define ` + ((naturalLand:num -> num -> num) i1 i2= (defaultLand naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; + + +val _ = Define ` +((instance_Word_WordAnd_Num_natural_dict:(num)WordAnd_class)= (<| + + land_method := naturalLand|>))`; + + +(*val naturalLsl : Num.natural -> nat -> Num.natural*) +val _ = Define ` + ((naturalLsl:num -> num -> num) i n= (defaultLsl naturalFromBitSeq (bitSeqFromNatural NONE) i n))`; + + +val _ = Define ` +((instance_Word_WordLsl_Num_natural_dict:(num)WordLsl_class)= (<| + + lsl_method := naturalLsl|>))`; + + +(*val naturalAsr : Num.natural -> nat -> Num.natural*) +val _ = Define ` + ((naturalAsr:num -> num -> num) i n= (defaultAsr naturalFromBitSeq (bitSeqFromNatural NONE) i n))`; + + +val _ = Define ` +((instance_Word_WordLsr_Num_natural_dict:(num)WordLsr_class)= (<| + + lsr_method := naturalAsr|>))`; + + +val _ = Define ` +((instance_Word_WordAsr_Num_natural_dict:(num)WordAsr_class)= (<| + + asr_method := naturalAsr|>))`; + + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on nats. + However, since nat is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of nat *) + +(*val natFromBitSeq : bitSequence -> nat*) +val _ = Define ` + ((natFromBitSeq:bitSequence -> num) bs= (((naturalFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs)):num)))`; + + + +(*val bitSeqFromNat : nat -> bitSequence*) +val _ = Define ` + ((bitSeqFromNat:num -> bitSequence) i= (bitSeqFromNatural (SOME(( 31 : num))) (( i:num))))`; + + + +(*val natLor : nat -> nat -> nat*) +val _ = Define ` + ((natLor:num -> num -> num) i1 i2= (defaultLor natFromBitSeq bitSeqFromNat i1 i2))`; + + +val _ = Define ` +((instance_Word_WordOr_nat_dict:(num)WordOr_class)= (<| + + lor_method := natLor|>))`; + + +(*val natLxor : nat -> nat -> nat*) +val _ = Define ` + ((natLxor:num -> num -> num) i1 i2= (defaultLxor natFromBitSeq bitSeqFromNat i1 i2))`; + + +val _ = Define ` +((instance_Word_WordXor_nat_dict:(num)WordXor_class)= (<| + + lxor_method := natLxor|>))`; + + +(*val natLand : nat -> nat -> nat*) +val _ = Define ` + ((natLand:num -> num -> num) i1 i2= (defaultLand natFromBitSeq bitSeqFromNat i1 i2))`; + + +val _ = Define ` +((instance_Word_WordAnd_nat_dict:(num)WordAnd_class)= (<| + + land_method := natLand|>))`; + + +(*val natLsl : nat -> nat -> nat*) +val _ = Define ` + ((natLsl:num -> num -> num) i n= (defaultLsl natFromBitSeq bitSeqFromNat i n))`; + + +val _ = Define ` +((instance_Word_WordLsl_nat_dict:(num)WordLsl_class)= (<| + + lsl_method := natLsl|>))`; + + +(*val natAsr : nat -> nat -> nat*) +val _ = Define ` + ((natAsr:num -> num -> num) i n= (defaultAsr natFromBitSeq bitSeqFromNat i n))`; + + +val _ = Define ` +((instance_Word_WordAsr_nat_dict:(num)WordAsr_class)= (<| + + asr_method := natAsr|>))`; + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/Holmakefile b/snapshots/hol4/sail/cheri/Holmakefile new file mode 100644 index 00000000..604555b5 --- /dev/null +++ b/snapshots/hol4/sail/cheri/Holmakefile @@ -0,0 +1,11 @@ +LEMDIR=../../lem/hol-lib + +INCLUDES = $(LEMDIR) ../lib/hol + +all: cheri_sequentialTheory.uo +.PHONY: all + +ifdef POLY +BASE_HEAP = ../lib/hol/sail-heap + +endif diff --git a/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml b/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml new file mode 100644 index 00000000..3bc5ad50 --- /dev/null +++ b/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml @@ -0,0 +1,9255 @@ +(*Generated by Lem from cheri_sequential.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory cheri_sequential_typesTheory mips_extras_sequentialTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "cheri_sequential" + +(*Generated by Sail from cheri_sequential.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import State_monad*) +(*open import State*) +(*open import Cheri_sequential_types*) +(*open import Mips_extras_sequential*) + +val _ = Define ` + ((cap_size:int)= ((( 32 : int):sail_values$ii)))`; + + +(*val undefined_option : forall 'a. 'a -> Cheri_sequential_types.M (Maybe.maybe 'a)*) + +val _ = Define ` + ((undefined_option:'a ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('a option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) typ_a= (seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`; + + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +val _ = Define ` + ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; + + + + + + +(*val builtin_and_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*) + + + +(*val builtin_or_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*) + + + +(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val DecStr : Sail_values.ii -> string*) + +(*val HexStr : Sail_values.ii -> string*) + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width data= + (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) addr data))`; + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) + +val _ = Define ` + ((MIPS_read:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) addr + : ( 'p8_times_n_ words$word) cheri_sequential_types$M)))`; + + + + +(*val undefined_exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.exception*) + +val _ = Define ` + ((undefined_exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (seqS +(undefined_unit () ) +(undefined_string () )) (\ (w__0 : string) . seqS (seqS (seqS +(undefined_unit () ) +(undefined_unit () )) +(undefined_unit () )) +(internal_pick + [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`; + + +(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +val _ = Define ` + ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + + +val _ = Define ` + ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + + +(*val zeros : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*) + +val _ = Define ` + ((zeros:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B0] : 1 words$word) n__tv : 'n words$word)))`; + + +(*val ones : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*) + +val _ = Define ` + ((ones:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B1] : 1 words$word) n__tv : 'n words$word)))`; + + + + + + + + + + +(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val bit_to_bool : Sail_values.bitU -> bool*) + +val _ = Define ` + ((bit_to_bool:sail_values$bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; + + +(*val bits_to_bool : Machine_word.mword Machine_word.ty1 -> bool*) + +val _ = Define ` + ((bits_to_bool:(1)words$word -> bool) x= (bit_to_bool ((access_vec_dec x (( 0 : int):sail_values$ii)))))`; + + +(*val to_bits : forall 'l. Size 'l => Machine_word.itself 'l -> Sail_values.ii -> Machine_word.mword 'l*) + +val _ = Define ` + ((to_bits:'l itself -> int -> 'l words$word) l n= + (let l = (size_itself_int l) in + (get_slice_int instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):sail_values$ii) : 'l words$word)))`; + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'm -> Machine_word.mword 'n*) + +val _ = Define ` + ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs= + ((subrange_vec_dec bs ((n__tv - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii) : 'n words$word)))`; + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +val _ = Define ` + ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((extz_vec m__tv v : 'm words$word)))`; + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +val _ = Define ` + ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((exts_vec m__tv v : 'm words$word)))`; + + +(*val slice_mask : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*) + +val _ = Define ` + ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l= + (let (one1 : 'n cheri_sequential_types$bits) = ((extzv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`; + + +(*val is_zero_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) + +val _ = Define ` + ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= + (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0] : 1 words$word) : 'n words$word))))`; + + +(*val is_ones_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) + +val _ = Define ` + ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j= + (let (m : 'n cheri_sequential_types$bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i)) : 'n words$word)) in + (((and_vec xs m : 'n words$word)) = m)))`; + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'r*) + +val _ = Define ` + ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'= + (let xs = +((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + let ys = +((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l' : 'm words$word)) : 'm words$word)) i' + : 'm words$word)) in + (or_vec ((shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)) ((extzv r__tv ys : 'r words$word)) + : 'r words$word)))`; + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Num.integer -> Num.integer -> Machine_word.mword 'r*) + +val _ = Define ` + ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'= + (let xs = +((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)))`; + + +(*val subrange_subrange_eq : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) + +val _ = Define ` + ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'= + (let xs = +((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = +((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j')) : 'n words$word)) : 'n words$word)) + j' + : 'n words$word)) in + (xs = ys)))`; + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => Num.integer -> Machine_word.mword 'n -> Num.integer -> Num.integer -> Machine_word.mword 'm -> Num.integer -> Num.integer -> Machine_word.mword 's*) + +val _ = Define ` + ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'= + (let xs = +((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = +((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j')) : 'm words$word)) : 'm words$word)) + j' + : 'm words$word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs : 's words$word)) i' : 's words$word)) + ((j' - (( 1 : int):sail_values$ii))) + : 's words$word)) ((extzv s__tv ys : 's words$word)) + : 's words$word)))`; + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) + +val _ = Define ` + ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift= + (let xs = +((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) + +val _ = Define ` + ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift= + (let xs = +((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) + +val _ = Define ` + ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = +((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (extzv m__tv xs : 'm words$word)))`; + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) + +val _ = Define ` + ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = +((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) + ((((((int_of_num (words$word_len xs))) - i)) - l)) + : 'n words$word)) ((((int_of_num (words$word_len xs))) - l)) + : 'n words$word)) in + (extsv m__tv xs : 'm words$word)))`; + + +(*val unsigned_slice : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*) + +val _ = Define ` + ((unsigned_slice:'n words$word -> int -> int -> int) xs i l= + (let xs = +((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + lem$w2ui xs))`; + + +(*val unsigned_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*) + +val _ = Define ` + ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j= + (let xs = +((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) i + : 'n words$word)) in + lem$w2ui xs))`; + + +(*val zext_ones : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Machine_word.mword 'n*) + +val _ = Define ` + ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m= + (let (v : 'n cheri_sequential_types$bits) = ((extsv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftr v ((((int_of_num (words$word_len v))) - m)) : 'n words$word)))`; + + +(*val undefined_CauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((undefined_CauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 words$word) . + internal_pick [Mk_CauseReg w__0])))`; + + +(*val _get_CauseReg : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32*) + +val _ = Define ` + ((get_CauseReg:cheri_sequential_types$CauseReg ->(32)words$word) (Mk_CauseReg (v))= v)`; + + +(*val _set_CauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_CauseReg v) in + write_regS r_ref r)))`; + + +(*val _get_CapCauseReg : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16*) + +(*val _set_CapCauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +(*val _get_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_CauseReg_BD : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_BD:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_CauseReg_CE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_CE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_CauseReg_IV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_IV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_CauseReg_WP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_WP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_CauseReg_IP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_IP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5*) + +val _ = Define ` + ((get_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)))`; + + +(*val _set_CauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CauseReg*) + +val _ = Define ` + ((update_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _update_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*) + +(*val _get_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*) + +(*val _set_CapCauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +(*val undefined_TLBEntryLoReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((undefined_TLBEntryLoReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryLoReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_TLBEntryLoReg w__0])))`; + + +(*val _get_TLBEntryLoReg : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_TLBEntryLoReg:cheri_sequential_types$TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))= v)`; + + +(*val _set_TLBEntryLoReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_TLBEntryLoReg v) in + write_regS r_ref r)))`; + + +(*val _get_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapS : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapS:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24*) + +val _ = Define ` + ((get_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 24 words$word)))`; + + +(*val _set_TLBEntryLoReg_PFN : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_PFN:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3*) + +val _ = Define ` + ((get_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 3 words$word)))`; + + +(*val _set_TLBEntryLoReg_C : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_C:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_D : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_D:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_V : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_V:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_G : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_G:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val undefined_TLBEntryHiReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryHiReg*) + +val _ = Define ` + ((undefined_TLBEntryHiReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryHiReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_TLBEntryHiReg w__0])))`; + + +(*val _get_TLBEntryHiReg : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_TLBEntryHiReg:cheri_sequential_types$TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))= v)`; + + +(*val _set_TLBEntryHiReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_TLBEntryHiReg v) in + write_regS r_ref r)))`; + + +(*val _get_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_TLBEntryHiReg_R : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_R:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27*) + +val _ = Define ` + ((get_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))= + ((subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))`; + + +(*val _set_TLBEntryHiReg_VPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_VPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_TLBEntryHiReg_ASID : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_ASID:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val undefined_ContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.ContextReg*) + +val _ = Define ` + ((undefined_ContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_ContextReg w__0])))`; + + +(*val _get_ContextReg : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_ContextReg:cheri_sequential_types$ContextReg ->(64)words$word) (Mk_ContextReg (v))= v)`; + + +(*val _set_ContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_ContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_ContextReg v) in + write_regS r_ref r)))`; + + +(*val _get_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41*) + +val _ = Define ` + ((get_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 41 words$word)))`; + + +(*val _set_ContextReg_PTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_ContextReg_PTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(41)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . + let r = ((get_ContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_ContextReg r))))`; + + +(*val _update_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.ContextReg*) + +val _ = Define ` + ((update_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x= + (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19*) + +val _ = Define ` + ((get_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 19 words$word)))`; + + +(*val _set_ContextReg_BadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_ContextReg_BadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(19)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . + let r = ((get_ContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_ContextReg r))))`; + + +(*val _update_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.ContextReg*) + +val _ = Define ` + ((update_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x= + (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val undefined_XContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.XContextReg*) + +val _ = Define ` + ((undefined_XContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$XContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_XContextReg w__0])))`; + + +(*val _get_XContextReg : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_XContextReg:cheri_sequential_types$XContextReg ->(64)words$word) (Mk_XContextReg (v))= v)`; + + +(*val _set_XContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_XContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_XContextReg v) in + write_regS r_ref r)))`; + + +(*val _get_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31*) + +val _ = Define ` + ((get_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word) (Mk_XContextReg (v))= + ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) : 31 words$word)))`; + + +(*val _set_XContextReg_XPTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_XContextReg_XPTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(31)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.XContextReg*) + +val _ = Define ` + ((update_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word) (Mk_XContextReg (v))= ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_XContextReg_XR : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_XContextReg_XR:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.XContextReg*) + +val _ = Define ` + ((update_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27*) + +val _ = Define ` + ((get_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word) (Mk_XContextReg (v))= + ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 27 words$word)))`; + + +(*val _set_XContextReg_XBadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_XContextReg_XBadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.XContextReg*) + +val _ = Define ` + ((update_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((TLBNumEntries:int)= ((( 64 : int):sail_values$ii)))`; + + +val _ = Define ` +((TLBIndexMax:(6)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))`; + + +(*val MAX : Num.integer -> Num.integer*) + +val _ = Define ` + ((MAX0:int -> int) n= (((pow2 n)) - (( 1 : int):sail_values$ii)))`; + + +val _ = Define ` + ((MAX_U64:int)= (MAX0 (( 64 : int):sail_values$ii)))`; + + +val _ = Define ` + ((MAX_VA:int)= (MAX0 (( 40 : int):sail_values$ii)))`; + + +val _ = Define ` + ((MAX_PA:int)= (MAX0 (( 36 : int):sail_values$ii)))`; + + +(*val undefined_TLBEntry : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((undefined_TLBEntry:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntry),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):sail_values$ii) : ( 117 words$word) cheri_sequential_types$M) (\ (w__0 : 117 words$word) . + internal_pick [Mk_TLBEntry w__0])))`; + + +(*val _get_TLBEntry : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117*) + +val _ = Define ` + ((get_TLBEntry:cheri_sequential_types$TLBEntry ->(117)words$word) (Mk_TLBEntry (v))= v)`; + + +(*val _set_TLBEntry : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(117)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_TLBEntry v) in + write_regS r_ref r)))`; + + +(*val _get_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16*) + +val _ = Define ` + ((get_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) : 16 words$word)))`; + + +(*val _set_TLBEntry_pagemask : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_pagemask:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_TLBEntry_r : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_r:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27*) + +val _ = Define ` + ((get_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) : 27 words$word)))`; + + +(*val _set_TLBEntry_vpn2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_vpn2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_TLBEntry_asid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_asid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_g : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_g:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_valid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_valid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_caps1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_capl1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*) + +val _ = Define ` + ((get_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_c1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_d1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_v1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_caps0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_capl0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*) + +val _ = Define ` + ((get_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_c0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_d0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_TLBEntry_v0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 117 words$word)) in + write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 117 words$word))))`; + + +val _ = Define ` +((TLBEntries:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref)list)= + ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; + TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; + TLBEntry00_ref]))`; + + +(*val undefined_StatusReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((undefined_StatusReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$StatusReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 words$word) . + internal_pick [Mk_StatusReg w__0])))`; + + +(*val _get_StatusReg : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32*) + +val _ = Define ` + ((get_StatusReg:cheri_sequential_types$StatusReg ->(32)words$word) (Mk_StatusReg (v))= v)`; + + +(*val _set_StatusReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_StatusReg v) in + write_regS r_ref r)))`; + + +(*val _get_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4*) + +val _ = Define ` + ((get_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 4 words$word)))`; + + +(*val _set_StatusReg_CU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_CU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(4)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_BEV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_BEV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_StatusReg_IM : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_IM:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_KX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_KX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_SX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_SX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_UX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_UX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_StatusReg_KSU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_KSU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_ERL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_ERL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_EXL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_EXL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_StatusReg_IE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_StatusReg_IE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 32 words$word)) in + write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) + +val _ = Define ` + ((update_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 32 words$word))))`; + + +(*val execute_branch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_branch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) pc= (seqS +(write_regS delayedPC_ref pc) (write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + + +(*val NotWordVal : Machine_word.mword Machine_word.ty64 -> bool*) + +val _ = Define ` + ((NotWordVal:(64)words$word -> bool) word= + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):sail_values$ii))) : 1 words$word)) (( 32 : int):sail_values$ii) + : 32 words$word)) <> ((subrange_vec_dec word (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word))))`; + + +(*val rGPR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((rGPR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx= + (let i = (lem$w2ui idx) in + if (((i = (( 0 : int):sail_values$ii)))) then + returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) + else bindS +(read_regS GPR_ref) (\ (w__0 : ( 64 cheri_sequential_types$bits) list) . + returnS ((access_list_dec w__0 i : 64 words$word)))))`; + + +(*val wGPR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((wGPR:(5)words$word ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx v= + (let i = (lem$w2ui idx) in + if (((i = (( 0 : int):sail_values$ii)))) then returnS () + else bindS +(read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . + write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list)))))`; + + + + + + + + + + + + + + + + +(*val Exception_of_num : Num.integer -> Cheri_sequential_types.Exception*) + +val _ = Define ` + ((Exception_of_num:int -> cheri_sequential_types$Exception) arg_= + (let l__81 = arg_ in + if (((l__81 = (( 0 : int):sail_values$ii)))) then Interrupt + else if (((l__81 = (( 1 : int):sail_values$ii)))) then TLBMod + else if (((l__81 = (( 2 : int):sail_values$ii)))) then TLBL + else if (((l__81 = (( 3 : int):sail_values$ii)))) then TLBS + else if (((l__81 = (( 4 : int):sail_values$ii)))) then AdEL + else if (((l__81 = (( 5 : int):sail_values$ii)))) then AdES + else if (((l__81 = (( 6 : int):sail_values$ii)))) then Sys + else if (((l__81 = (( 7 : int):sail_values$ii)))) then Bp + else if (((l__81 = (( 8 : int):sail_values$ii)))) then ResI + else if (((l__81 = (( 9 : int):sail_values$ii)))) then CpU + else if (((l__81 = (( 10 : int):sail_values$ii)))) then Ov + else if (((l__81 = (( 11 : int):sail_values$ii)))) then Tr + else if (((l__81 = (( 12 : int):sail_values$ii)))) then C2E + else if (((l__81 = (( 13 : int):sail_values$ii)))) then C2Trap + else if (((l__81 = (( 14 : int):sail_values$ii)))) then XTLBRefillL + else if (((l__81 = (( 15 : int):sail_values$ii)))) then XTLBRefillS + else if (((l__81 = (( 16 : int):sail_values$ii)))) then XTLBInvL + else if (((l__81 = (( 17 : int):sail_values$ii)))) then XTLBInvS + else MCheck))`; + + +(*val num_of_Exception : Cheri_sequential_types.Exception -> Num.integer*) + +val _ = Define ` + ((num_of_Exception:cheri_sequential_types$Exception -> int) arg_= + ((case arg_ of + Interrupt => (( 0 : int):sail_values$ii) + | TLBMod => (( 1 : int):sail_values$ii) + | TLBL => (( 2 : int):sail_values$ii) + | TLBS => (( 3 : int):sail_values$ii) + | AdEL => (( 4 : int):sail_values$ii) + | AdES => (( 5 : int):sail_values$ii) + | Sys => (( 6 : int):sail_values$ii) + | Bp => (( 7 : int):sail_values$ii) + | ResI => (( 8 : int):sail_values$ii) + | CpU => (( 9 : int):sail_values$ii) + | Ov => (( 10 : int):sail_values$ii) + | Tr => (( 11 : int):sail_values$ii) + | C2E => (( 12 : int):sail_values$ii) + | C2Trap => (( 13 : int):sail_values$ii) + | XTLBRefillL => (( 14 : int):sail_values$ii) + | XTLBRefillS => (( 15 : int):sail_values$ii) + | XTLBInvL => (( 16 : int):sail_values$ii) + | XTLBInvS => (( 17 : int):sail_values$ii) + | MCheck => (( 18 : int):sail_values$ii) + )))`; + + +(*val undefined_Exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.Exception*) + +val _ = Define ` + ((undefined_Exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = + (internal_pick + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`; + + +(*val ExceptionCode : Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty5*) + +val _ = Define ` + ((ExceptionCode:cheri_sequential_types$Exception ->(5)words$word) ex= + (let (x : 8 cheri_sequential_types$bits) = +((case ex of + Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) + )) in + (subrange_vec_dec x (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)))`; + + +(*val SignalExceptionMIPS : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) + +val _ = Define ` + ((SignalExceptionMIPS:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex kccBase= (bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS (seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then bindS + (read_regS inBranchDelay_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . seqS +(write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):sail_values$ii) : 64 words$word))) +(set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : 1 words$word))) + else bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . seqS +(write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) + else returnS () ) +(read_regS CP0Status_ref)) (\ (w__4 : cheri_sequential_types$StatusReg) . + let vectorOffset = +(if ((bits_to_bool ((get_StatusReg_EXL w__4 : 1 words$word)))) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in bindS +(read_regS CP0Status_ref) (\ (w__5 : cheri_sequential_types$StatusReg) . + let (vectorBase : 64 cheri_sequential_types$bits) = +(if ((bits_to_bool ((get_StatusReg_BEV w__5 : 1 words$word)))) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)) in seqS (seqS (seqS +(write_regS + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((sign_extend1 (( 64 : int):sail_values$ii) vectorOffset : 64 words$word)) : 64 words$word)) + kccBase + : 64 words$word))) +(set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex : 5 words$word)))) +(set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (throwS (ISAException () )))))))`; + + +(*val SignalException : forall 'o. Cheri_sequential_types.Exception -> Cheri_sequential_types.M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) + +(*val capRegToCapStruct : Machine_word.mword Machine_word.ty257 -> Cheri_sequential_types.CapStruct*) + +val _ = Define ` + ((capRegToCapStruct:(257)words$word -> cheri_sequential_types$CapStruct) capReg= + (<| CapStruct_tag := ((bit_to_bool ((access_vec_dec capReg (( 256 : int):sail_values$ii))))); + CapStruct_padding := ((subrange_vec_dec capReg (( 255 : int):sail_values$ii) (( 248 : int):sail_values$ii) : 8 words$word)); + CapStruct_otype := ((subrange_vec_dec capReg (( 247 : int):sail_values$ii) (( 224 : int):sail_values$ii) : 24 words$word)); + CapStruct_uperms := ((subrange_vec_dec capReg (( 223 : int):sail_values$ii) (( 208 : int):sail_values$ii) : 16 words$word)); + CapStruct_perm_reserved11_14 := ((subrange_vec_dec capReg (( 207 : int):sail_values$ii) (( 204 : int):sail_values$ii) : 4 words$word)); + CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec capReg (( 203 : int):sail_values$ii))))); + CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec capReg (( 202 : int):sail_values$ii))))); + CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec capReg (( 201 : int):sail_values$ii))))); + CapStruct_permit_seal := ((bit_to_bool ((access_vec_dec capReg (( 200 : int):sail_values$ii))))); + CapStruct_permit_store_local_cap := ((bit_to_bool ((access_vec_dec capReg (( 199 : int):sail_values$ii))))); + CapStruct_permit_store_cap := ((bit_to_bool ((access_vec_dec capReg (( 198 : int):sail_values$ii))))); + CapStruct_permit_load_cap := ((bit_to_bool ((access_vec_dec capReg (( 197 : int):sail_values$ii))))); + CapStruct_permit_store := ((bit_to_bool ((access_vec_dec capReg (( 196 : int):sail_values$ii))))); + CapStruct_permit_load := ((bit_to_bool ((access_vec_dec capReg (( 195 : int):sail_values$ii))))); + CapStruct_permit_execute := ((bit_to_bool ((access_vec_dec capReg (( 194 : int):sail_values$ii))))); + CapStruct_global := ((bit_to_bool ((access_vec_dec capReg (( 193 : int):sail_values$ii))))); + CapStruct_sealed := ((bit_to_bool ((access_vec_dec capReg (( 192 : int):sail_values$ii))))); + CapStruct_address := ((subrange_vec_dec capReg (( 191 : int):sail_values$ii) (( 128 : int):sail_values$ii) : 64 words$word)); + CapStruct_base := ((subrange_vec_dec capReg (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word)); + CapStruct_length := ((subrange_vec_dec capReg (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) |>))`; + + +(*val getCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31*) + +val _ = Define ` + ((getCapPerms:cheri_sequential_types$CapStruct ->(31)words$word) cap= + ((concat_vec cap.CapStruct_uperms + ((concat_vec cap.CapStruct_perm_reserved11_14 + ((concat_vec ((bool_to_bits cap.CapStruct_access_system_regs : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_unseal : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_ccall : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_seal : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store_local_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_load_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_load : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_execute + : 1 words$word)) + ((bool_to_bits cap.CapStruct_global : 1 words$word)) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 8 words$word)) + : 9 words$word)) + : 10 words$word)) + : 11 words$word)) + : 15 words$word)) + : 31 words$word)))`; + + +(*val capStructToMemBits256 : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*) + +val _ = Define ` + ((capStructToMemBits256:cheri_sequential_types$CapStruct ->(256)words$word) cap= + ((concat_vec cap.CapStruct_padding + ((concat_vec cap.CapStruct_otype + ((concat_vec ((getCapPerms cap : 31 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_sealed : 1 words$word)) + ((concat_vec cap.CapStruct_address + ((concat_vec cap.CapStruct_base cap.CapStruct_length : 128 words$word)) + : 192 words$word)) + : 193 words$word)) + : 224 words$word)) + : 248 words$word)) + : 256 words$word)))`; + + +(*val capStructToCapReg : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty257*) + +val _ = Define ` + ((capStructToCapReg:cheri_sequential_types$CapStruct ->(257)words$word) cap= + ((concat_vec ((bool_to_bits cap.CapStruct_tag : 1 words$word)) + ((capStructToMemBits256 cap : 256 words$word)) + : 257 words$word)))`; + + +(*val getCapBase : Cheri_sequential_types.CapStruct -> Num.integer*) + +val _ = Define ` + ((getCapBase:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_base))`; + + +val _ = Define ` +((null_cap:cheri_sequential_types$CapStruct)= + (<| CapStruct_tag := F; + CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) () : 8 words$word)); + CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); + CapStruct_uperms := ((zeros (( 16 : int):sail_values$ii) () : 16 words$word)); + CapStruct_perm_reserved11_14 := ((zeros (( 4 : int):sail_values$ii) () : 4 words$word)); + CapStruct_access_system_regs := F; + CapStruct_permit_unseal := F; + CapStruct_permit_ccall := F; + CapStruct_permit_seal := F; + CapStruct_permit_store_local_cap := F; + CapStruct_permit_store_cap := F; + CapStruct_permit_load_cap := F; + CapStruct_permit_store := F; + CapStruct_permit_load := F; + CapStruct_permit_execute := F; + CapStruct_global := F; + CapStruct_sealed := F; + CapStruct_address := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); + CapStruct_base := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); + CapStruct_length := +((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : 64 words$word)) |>))`; + + +(*val int_to_cap : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.CapStruct*) + +val _ = Define ` + ((int_to_cap:(64)words$word -> cheri_sequential_types$CapStruct) address= ((null_cap with<| CapStruct_address := address|>)))`; + + +(*val setCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*) + +val _ = Define ` + ((setCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c offset= + (T, (c with<| CapStruct_address := ((add_vec c.CapStruct_base offset : 64 words$word))|>)))`; + + +val _ = Define ` + ((SignalException:cheri_sequential_types$Exception ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex= (bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS (seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ pc . bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in + let (success, epcc) = (setCapOffset pcc pc) in + if success then write_regS C31_ref ((capStructToCapReg epcc : 257 words$word)) + else + write_regS + C31_ref + ((capStructToCapReg + ((int_to_cap + ((add_vec_int + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase pcc)) + : 64 words$word)) ((lem$w2ui pc)) + : 64 words$word)))) + : 257 words$word)))) + else returnS () ) + (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__2 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS nextPCC_ref w__2) + (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS delayedPCC_ref w__3) + (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__4 : 257 words$word) . + let base = (getCapBase ((capRegToCapStruct w__4))) in + SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) base : 64 words$word))))))))`; + + +val _ = Define ` + ((SignalExceptionBadAddr:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr= (seqS (write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; + + +(*val SignalExceptionTLB : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) + +val _ = Define ` + ((SignalExceptionTLB:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr= (seqS (seqS (seqS (seqS (seqS (seqS +(write_regS CP0BadVAddr_ref badAddr) +(set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 19 words$word)))) +(set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))) +(set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))) +(set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))) +(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))) +(SignalException ex)))`; + + +(*val MemAccessType_of_num : Num.integer -> Cheri_sequential_types.MemAccessType*) + +val _ = Define ` + ((MemAccessType_of_num:int -> cheri_sequential_types$MemAccessType) arg_= + (let l__79 = arg_ in + if (((l__79 = (( 0 : int):sail_values$ii)))) then Instruction + else if (((l__79 = (( 1 : int):sail_values$ii)))) then LoadData + else StoreData))`; + + +(*val num_of_MemAccessType : Cheri_sequential_types.MemAccessType -> Num.integer*) + +val _ = Define ` + ((num_of_MemAccessType:cheri_sequential_types$MemAccessType -> int) arg_= + ((case arg_ of Instruction => (( 0 : int):sail_values$ii) | LoadData => (( 1 : int):sail_values$ii) | StoreData => (( 2 : int):sail_values$ii) )))`; + + +(*val undefined_MemAccessType : unit -> Cheri_sequential_types.M Cheri_sequential_types.MemAccessType*) + +val _ = Define ` + ((undefined_MemAccessType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$MemAccessType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [Instruction;LoadData;StoreData]))`; + + +(*val AccessLevel_of_num : Num.integer -> Cheri_sequential_types.AccessLevel*) + +val _ = Define ` + ((AccessLevel_of_num:int -> cheri_sequential_types$AccessLevel) arg_= + (let l__77 = arg_ in + if (((l__77 = (( 0 : int):sail_values$ii)))) then User + else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor + else Kernel))`; + + +(*val num_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Num.integer*) + +val _ = Define ` + ((num_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) arg_= + ((case arg_ of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`; + + +(*val undefined_AccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*) + +val _ = Define ` + ((undefined_AccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [User;Supervisor;Kernel]))`; + + +(*val int_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Sail_values.ii*) + +val _ = Define ` + ((int_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) level= + ((case level of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`; + + +(*val grantsAccess : Cheri_sequential_types.AccessLevel -> Cheri_sequential_types.AccessLevel -> bool*) + +val _ = Define ` + ((grantsAccess:cheri_sequential_types$AccessLevel -> cheri_sequential_types$AccessLevel -> bool) currentLevel requiredLevel= + (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`; + + +(*val getAccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*) + +val _ = Define ` + ((getAccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS +(read_regS CP0Status_ref) (\ (w__1 : cheri_sequential_types$StatusReg) . + if (((((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))) \/ ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) then + returnS Kernel + else bindS +(read_regS CP0Status_ref) (\ (w__2 : cheri_sequential_types$StatusReg) . + let p__132 = ((get_StatusReg_KSU w__2 : 2 words$word)) in + let b__0 = p__132 in + returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then User + else User))))))`; + + +(*val checkCP0Access : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((checkCP0Access:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(getAccessLevel () ) (\ accessLevel . bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + if ((((((accessLevel <> Kernel))) /\ ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):sail_values$ii)))))))))) + then seqS +(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : 2 words$word)) (SignalException CpU) + else returnS () ))))`; + + +(*val incrementCP0Count : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((incrementCP0Count:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$TLBIndexT) . bindS + (read_regS TLBWired_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__1 : 6 words$word) . bindS + (if (((w__0 = w__1))) then returnS TLBIndexMax + else bindS + (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__2 : 6 words$word) . + returnS ((sub_vec_int w__2 (( 1 : int):sail_values$ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . bindS (seqS +(write_regS TLBRandom_ref w__3) + (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M)) (\ (w__4 : 32 words$word) . bindS (seqS +(write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):sail_values$ii) : 32 words$word))) + (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M)) (\ (w__5 : 32 cheri_sequential_types$bits) . bindS + (read_regS CP0Compare_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__6 : 32 words$word) . bindS (seqS + (if (((w__5 = w__6))) then bindS +(read_regS CP0Cause_ref) (\ (w__7 : cheri_sequential_types$CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 : 8 words$word)) + (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + : 8 words$word))) + else returnS () ) +(read_regS CP0Status_ref)) (\ (w__8 : cheri_sequential_types$StatusReg) . + let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in bindS +(read_regS CP0Cause_ref) (\ (w__9 : cheri_sequential_types$CauseReg) . + let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in bindS +(read_regS CP0Status_ref) (\ (w__10 : cheri_sequential_types$StatusReg) . + let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in bindS +(read_regS CP0Status_ref) (\ (w__11 : cheri_sequential_types$StatusReg) . + let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in bindS +(read_regS CP0Status_ref) (\ (w__12 : cheri_sequential_types$StatusReg) . + let erl = ((get_StatusReg_ERL w__12 : 1 words$word)) in + if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))))))))) then + SignalException Interrupt + else returnS () )))))))))))))`; + + +(*val decode_failure_of_num : Num.integer -> Cheri_sequential_types.decode_failure*) + +val _ = Define ` + ((decode_failure_of_num:int -> cheri_sequential_types$decode_failure) arg_= + (let l__74 = arg_ in + if (((l__74 = (( 0 : int):sail_values$ii)))) then No_matching_pattern + else if (((l__74 = (( 1 : int):sail_values$ii)))) then Unsupported_instruction + else if (((l__74 = (( 2 : int):sail_values$ii)))) then Illegal_instruction + else Internal_error))`; + + +(*val num_of_decode_failure : Cheri_sequential_types.decode_failure -> Num.integer*) + +val _ = Define ` + ((num_of_decode_failure:cheri_sequential_types$decode_failure -> int) arg_= + ((case arg_ of no_matching_pattern => (( 0 : int): sail_values$ii) )))`; + + +(*val undefined_decode_failure : unit -> Cheri_sequential_types.M Cheri_sequential_types.decode_failure*) + +val _ = Define ` + ((undefined_decode_failure:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$decode_failure),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = + (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; + + +(*val Comparison_of_num : Num.integer -> Cheri_sequential_types.Comparison*) + +val _ = Define ` + ((Comparison_of_num:int -> cheri_sequential_types$Comparison) arg_= + (let l__67 = arg_ in + if (((l__67 = (( 0 : int):sail_values$ii)))) then EQ' + else if (((l__67 = (( 1 : int):sail_values$ii)))) then NE + else if (((l__67 = (( 2 : int):sail_values$ii)))) then GE + else if (((l__67 = (( 3 : int):sail_values$ii)))) then GEU + else if (((l__67 = (( 4 : int):sail_values$ii)))) then GT' + else if (((l__67 = (( 5 : int):sail_values$ii)))) then LE + else if (((l__67 = (( 6 : int):sail_values$ii)))) then LT' + else LTU))`; + + +(*val num_of_Comparison : Cheri_sequential_types.Comparison -> Num.integer*) + +val _ = Define ` + ((num_of_Comparison:cheri_sequential_types$Comparison -> int) arg_= + ((case arg_ of + EQ' => (( 0 : int):sail_values$ii) + | NE => (( 1 : int):sail_values$ii) + | GE => (( 2 : int):sail_values$ii) + | GEU => (( 3 : int):sail_values$ii) + | GT' => (( 4 : int):sail_values$ii) + | LE => (( 5 : int):sail_values$ii) + | LT' => (( 6 : int):sail_values$ii) + | LTU => (( 7 : int):sail_values$ii) + )))`; + + +(*val undefined_Comparison : unit -> Cheri_sequential_types.M Cheri_sequential_types.Comparison*) + +val _ = Define ` + ((undefined_Comparison:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Comparison),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; + + +(*val compare : Cheri_sequential_types.Comparison -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> bool*) + +val _ = Define ` + ((compare:cheri_sequential_types$Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB= + ((case cmp of + EQ' => (valA = valB) + | NE => (valA <> valB) + | GE => ((integer_word$w2i valA) >= (integer_word$w2i valB)) + | GEU => ((lem$w2ui valA) >= (lem$w2ui valB)) + | GT' => ((integer_word$w2i valB) < (integer_word$w2i valA)) + | LE => ((integer_word$w2i valB) >= (integer_word$w2i valA)) + | LT' => ((integer_word$w2i valA) < (integer_word$w2i valB)) + | LTU => ((lem$w2ui valA) < (lem$w2ui valB)) + )))`; + + +(*val WordType_of_num : Num.integer -> Cheri_sequential_types.WordType*) + +val _ = Define ` + ((WordType_of_num:int -> cheri_sequential_types$WordType) arg_= + (let l__64 = arg_ in + if (((l__64 = (( 0 : int):sail_values$ii)))) then B + else if (((l__64 = (( 1 : int):sail_values$ii)))) then H + else if (((l__64 = (( 2 : int):sail_values$ii)))) then W0 + else D))`; + + +(*val num_of_WordType : Cheri_sequential_types.WordType -> Num.integer*) + +val _ = Define ` + ((num_of_WordType:cheri_sequential_types$WordType -> int) arg_= + ((case arg_ of B => (( 0 : int):sail_values$ii) | H => (( 1 : int):sail_values$ii) | W0 => (( 2 : int):sail_values$ii) | D => (( 3 : int):sail_values$ii) )))`; + + +(*val undefined_WordType : unit -> Cheri_sequential_types.M Cheri_sequential_types.WordType*) + +val _ = Define ` + ((undefined_WordType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$WordType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [B;H;W0;D]))`; + + +(*val wordWidthBytes : Cheri_sequential_types.WordType -> Num.integer*) + +val _ = Define ` + ((wordWidthBytes:cheri_sequential_types$WordType -> int) w= ((case w of B => (( 1 : int):sail_values$ii) | H => (( 2 : int):sail_values$ii) | W0 => (( 4 : int):sail_values$ii) | D => (( 8 : int):sail_values$ii) )))`; + + +val _ = Define ` + ((alignment_width:int)= ((( 16 : int):sail_values$ii)))`; + + +(*val isAddressAligned : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.WordType -> bool*) + +val _ = Define ` + ((isAddressAligned:(64)words$word -> cheri_sequential_types$WordType -> bool) addr wordType= + (let a = (lem$w2ui addr) in + (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):sail_values$ii))) / + alignment_width)))))`; + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1= (bindS + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . + returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_reserve_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1= (bindS + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . + returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; + + +(*val init_cp0_state : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((init_cp0_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; + + +(*val init_cp2_state : unit -> Cheri_sequential_types.M unit*) + +(*val cp2_next_pc : unit -> Cheri_sequential_types.M unit*) + +(*val dump_cp2_state : unit -> Cheri_sequential_types.M unit*) + +(*val tlbEntryMatch : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty27 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry -> bool*) + +val _ = Define ` + ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> cheri_sequential_types$TLBEntry -> bool) r vpn2 asid entry= + (let entryValid = ((get_TLBEntry_valid entry : 1 words$word)) in + let entryR = ((get_TLBEntry_r entry : 2 words$word)) in + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let entryVPN = ((get_TLBEntry_vpn2 entry : 27 words$word)) in + let entryASID = ((get_TLBEntry_asid entry : 8 words$word)) in + let entryG = ((get_TLBEntry_g entry : 1 words$word)) in + let (vpnMask : 27 cheri_sequential_types$bits) = +((not_vec ((zero_extend1 (( 27 : int):sail_values$ii) entryMask : 27 words$word)) : 27 words$word)) in + (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask : 27 words$word)) = ((and_vec entryVPN vpnMask : 27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`; + + +(*val tlbSearch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Maybe.maybe (Machine_word.mword Machine_word.ty6))*) + +val _ = Define ` + ((tlbSearch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((((6)words$word)option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) VAddr= + (catch_early_returnS + (let r = ((subrange_vec_dec VAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)) in + let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)) in bindS +(liftRS (read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . + let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in seqS + (foreachS (index_list (( 0 : int):sail_values$ii) (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () + (\ idx unit_var . bindS +(liftRS (read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : cheri_sequential_types$TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):sail_values$ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) + cheri_sequential_types$MR) + else returnS () ))) +(returnS NONE)))))`; + + +(*val TLBTranslate2 : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*) + +val _ = Define ` + ((TLBTranslate2:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS + (tlbSearch vAddr : ( ( 6 words$word)option) cheri_sequential_types$M) (\ idx . + (case idx of + SOME (idx) => + let i = (lem$w2ui idx) in bindS +(read_regS ((access_list_dec TLBEntries i))) (\ entry . + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let b__0 = entryMask in bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + returnS (( 12 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) + then + returnS (( 14 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 16 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 18 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 20 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 22 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 24 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 26 : int):sail_values$ii) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + returnS (( 28 : int):sail_values$ii) + else undefined_range (( 12 : int):sail_values$ii) (( 28 : int):sail_values$ii)) (\ (evenOddBit : int) . + let isOdd = (access_vec_dec vAddr evenOddBit) in + let ((caps : 1 cheri_sequential_types$bits), (capl : 1 cheri_sequential_types$bits), (pfn : 24 cheri_sequential_types$bits), (d : 1 cheri_sequential_types$bits), (v : 1 cheri_sequential_types$bits)) = +(if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry : 1 words$word), + (get_TLBEntry_capl1 entry : 1 words$word), + (get_TLBEntry_pfn1 entry : 24 words$word), + (get_TLBEntry_d1 entry : 1 words$word), + (get_TLBEntry_v1 entry : 1 words$word)) + else + ((get_TLBEntry_caps0 entry : 1 words$word), + (get_TLBEntry_capl0 entry : 1 words$word), + (get_TLBEntry_pfn0 entry : 24 words$word), + (get_TLBEntry_d0 entry : 1 words$word), + (get_TLBEntry_v0 entry : 1 words$word))) in + if ((~ ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + : (( 64 words$word # bool)) cheri_sequential_types$M) + else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr : (( 64 words$word # bool)) cheri_sequential_types$M) + else + let (res : 64 cheri_sequential_types$bits) = +((zero_extend1 (( 64 : int):sail_values$ii) + ((subrange_subrange_concat + (((((((( 23 : int):sail_values$ii) - + ((((evenOddBit - (( 12 : int):sail_values$ii))) - (( 1 : int):sail_values$ii))))) + + + ((evenOddBit - (( 1 : int):sail_values$ii))))) + - (((( 0 : int):sail_values$ii) - (( 1 : int):sail_values$ii))))) pfn + (( 23 : int):sail_values$ii) ((evenOddBit - (( 12 : int):sail_values$ii))) vAddr + ((evenOddBit - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii) + : 36 words$word)) + : 64 words$word)) in + returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) + | NONE => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + : (( 64 words$word # bool)) cheri_sequential_types$M) + ))))`; + + +(*val TLBTranslateC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*) + +val _ = Define ` + ((TLBTranslateC:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS +(getAccessLevel () ) (\ currentAccessLevel . + let compat32 = + (((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 31 words$word)) in + let b__0 = ((subrange_vec_dec vAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)) in + let ((requiredLevel : cheri_sequential_types$AccessLevel), (addr : ( 64 cheri_sequential_types$bits)option)) = +(if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 : int):sail_values$ii) (( 29 : int):sail_values$ii) : 2 words$word)) of + (T, b__1) => + if (((b__1 = (vec_of_bits [B1;B1] : 2 words$word)))) then (Kernel, NONE) + else if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then (Supervisor, NONE) + else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + else + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + | (g__130, g__131) => (Kernel, NONE) + ) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((subrange_vec_dec vAddr (( 58 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 59 words$word)) + : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then (Supervisor, NONE) + else (User, NONE)) in + if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) cheri_sequential_types$M) + else bindS + (case addr of + SOME (a) => returnS (a, F) + | NONE => + if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 62 words$word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) cheri_sequential_types$M) + else (TLBTranslate2 vAddr accessType : (( 64 words$word # bool)) cheri_sequential_types$M) + ) (\ varstup . let ((pa : 64 cheri_sequential_types$bits), (c : bool)) = varstup in + if ((((lem$w2ui pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) cheri_sequential_types$M) + else returnS (pa, c)))))`; + + +(*val TLBTranslate : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((TLBTranslate:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS + (TLBTranslateC vAddr accessType : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (addr, c) = varstup in + returnS addr)))`; + + +(*val CPtrCmpOp_of_num : Num.integer -> Cheri_sequential_types.CPtrCmpOp*) + +val _ = Define ` + ((CPtrCmpOp_of_num:int -> cheri_sequential_types$CPtrCmpOp) arg_= + (let l__57 = arg_ in + if (((l__57 = (( 0 : int):sail_values$ii)))) then CEQ + else if (((l__57 = (( 1 : int):sail_values$ii)))) then CNE + else if (((l__57 = (( 2 : int):sail_values$ii)))) then CLT + else if (((l__57 = (( 3 : int):sail_values$ii)))) then CLE + else if (((l__57 = (( 4 : int):sail_values$ii)))) then CLTU + else if (((l__57 = (( 5 : int):sail_values$ii)))) then CLEU + else if (((l__57 = (( 6 : int):sail_values$ii)))) then CEXEQ + else CNEXEQ))`; + + +(*val num_of_CPtrCmpOp : Cheri_sequential_types.CPtrCmpOp -> Num.integer*) + +val _ = Define ` + ((num_of_CPtrCmpOp:cheri_sequential_types$CPtrCmpOp -> int) arg_= + ((case arg_ of + CEQ => (( 0 : int):sail_values$ii) + | CNE => (( 1 : int):sail_values$ii) + | CLT => (( 2 : int):sail_values$ii) + | CLE => (( 3 : int):sail_values$ii) + | CLTU => (( 4 : int):sail_values$ii) + | CLEU => (( 5 : int):sail_values$ii) + | CEXEQ => (( 6 : int):sail_values$ii) + | CNEXEQ => (( 7 : int):sail_values$ii) + )))`; + + +(*val undefined_CPtrCmpOp : unit -> Cheri_sequential_types.M Cheri_sequential_types.CPtrCmpOp*) + +val _ = Define ` + ((undefined_CPtrCmpOp:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CPtrCmpOp),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`; + + +(*val ClearRegSet_of_num : Num.integer -> Cheri_sequential_types.ClearRegSet*) + +val _ = Define ` + ((ClearRegSet_of_num:int -> cheri_sequential_types$ClearRegSet) arg_= + (let l__54 = arg_ in + if (((l__54 = (( 0 : int):sail_values$ii)))) then GPLo + else if (((l__54 = (( 1 : int):sail_values$ii)))) then GPHi + else if (((l__54 = (( 2 : int):sail_values$ii)))) then CLo + else CHi))`; + + +(*val num_of_ClearRegSet : Cheri_sequential_types.ClearRegSet -> Num.integer*) + +val _ = Define ` + ((num_of_ClearRegSet:cheri_sequential_types$ClearRegSet -> int) arg_= + ((case arg_ of GPLo => (( 0 : int):sail_values$ii) | GPHi => (( 1 : int):sail_values$ii) | CLo => (( 2 : int):sail_values$ii) | CHi => (( 3 : int):sail_values$ii) )))`; + + +(*val undefined_ClearRegSet : unit -> Cheri_sequential_types.M Cheri_sequential_types.ClearRegSet*) + +val _ = Define ` + ((undefined_ClearRegSet:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ClearRegSet),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [GPLo;GPHi;CLo;CHi]))`; + + +(*val undefined_CapStruct : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*) + +val _ = Define ` + ((undefined_CapStruct:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(undefined_bool0 () ) (\ (w__0 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 : 8 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):sail_values$ii) : ( 24 words$word) cheri_sequential_types$M) (\ (w__2 : 24 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 : 16 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):sail_values$ii) : ( 4 words$word) cheri_sequential_types$M) (\ (w__4 : 4 cheri_sequential_types$bits) . bindS +(undefined_bool0 () ) (\ (w__5 : bool) . bindS +(undefined_bool0 () ) (\ (w__6 : bool) . bindS +(undefined_bool0 () ) (\ (w__7 : bool) . bindS +(undefined_bool0 () ) (\ (w__8 : bool) . bindS +(undefined_bool0 () ) (\ (w__9 : bool) . bindS +(undefined_bool0 () ) (\ (w__10 : bool) . bindS +(undefined_bool0 () ) (\ (w__11 : bool) . bindS +(undefined_bool0 () ) (\ (w__12 : bool) . bindS +(undefined_bool0 () ) (\ (w__13 : bool) . bindS +(undefined_bool0 () ) (\ (w__14 : bool) . bindS +(undefined_bool0 () ) (\ (w__15 : bool) . bindS +(undefined_bool0 () ) (\ (w__16 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__17 : 64 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__18 : 64 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__19 : 64 cheri_sequential_types$bits) . + returnS (<| CapStruct_tag := w__0; + CapStruct_padding := w__1; + CapStruct_otype := w__2; + CapStruct_uperms := w__3; + CapStruct_perm_reserved11_14 := w__4; + CapStruct_access_system_regs := w__5; + CapStruct_permit_unseal := w__6; + CapStruct_permit_ccall := w__7; + CapStruct_permit_seal := w__8; + CapStruct_permit_store_local_cap := w__9; + CapStruct_permit_store_cap := w__10; + CapStruct_permit_load_cap := w__11; + CapStruct_permit_store := w__12; + CapStruct_permit_load := w__13; + CapStruct_permit_execute := w__14; + CapStruct_global := w__15; + CapStruct_sealed := w__16; + CapStruct_address := w__17; + CapStruct_base := w__18; + CapStruct_length := w__19 |>)))))))))))))))))))))))`; + + +val _ = Define ` +((default_cap:cheri_sequential_types$CapStruct)= + (<| CapStruct_tag := T; + CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) () : 8 words$word)); + CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); + CapStruct_uperms := ((ones (( 16 : int):sail_values$ii) () : 16 words$word)); + CapStruct_perm_reserved11_14 := ((ones (( 4 : int):sail_values$ii) () : 4 words$word)); + CapStruct_access_system_regs := T; + CapStruct_permit_unseal := T; + CapStruct_permit_ccall := T; + CapStruct_permit_seal := T; + CapStruct_permit_store_local_cap := T; + CapStruct_permit_store_cap := T; + CapStruct_permit_load_cap := T; + CapStruct_permit_store := T; + CapStruct_permit_load := T; + CapStruct_permit_execute := T; + CapStruct_global := T; + CapStruct_sealed := F; + CapStruct_address := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); + CapStruct_base := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); + CapStruct_length := +((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : 64 words$word)) |>))`; + + +val _ = Define ` +((null_cap_bits:(256)words$word)= ((capStructToMemBits256 null_cap : 256 words$word)))`; + + +(*val capStructToMemBits : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*) + +val _ = Define ` + ((capStructToMemBits:cheri_sequential_types$CapStruct ->(256)words$word) cap= + ((xor_vec ((capStructToMemBits256 cap : 256 words$word)) null_cap_bits : 256 words$word)))`; + + +(*val memBitsToCapBits : bool -> Machine_word.mword Machine_word.ty256 -> Machine_word.mword Machine_word.ty257*) + +val _ = Define ` + ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b= + ((concat_vec ((bool_to_bits tag : 1 words$word)) ((xor_vec b null_cap_bits : 256 words$word)) + : 257 words$word)))`; + + +(*val setCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.CapStruct*) + +val _ = Define ` + ((setCapPerms:cheri_sequential_types$CapStruct ->(31)words$word -> cheri_sequential_types$CapStruct) cap perms= + ((cap with<| + CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 16 words$word)); CapStruct_perm_reserved11_14 := + ((subrange_vec_dec perms (( 14 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 4 words$word)); CapStruct_access_system_regs := + ((bit_to_bool ((access_vec_dec perms (( 10 : int):sail_values$ii))))); CapStruct_permit_unseal := + ((bit_to_bool ((access_vec_dec perms (( 9 : int):sail_values$ii))))); CapStruct_permit_ccall := + ((bit_to_bool ((access_vec_dec perms (( 8 : int):sail_values$ii))))); CapStruct_permit_seal := + ((bit_to_bool ((access_vec_dec perms (( 7 : int):sail_values$ii))))); CapStruct_permit_store_local_cap := + ((bit_to_bool ((access_vec_dec perms (( 6 : int):sail_values$ii))))); CapStruct_permit_store_cap := + ((bit_to_bool ((access_vec_dec perms (( 5 : int):sail_values$ii))))); CapStruct_permit_load_cap := + ((bit_to_bool ((access_vec_dec perms (( 4 : int):sail_values$ii))))); CapStruct_permit_store := + ((bit_to_bool ((access_vec_dec perms (( 3 : int):sail_values$ii))))); CapStruct_permit_load := + ((bit_to_bool ((access_vec_dec perms (( 2 : int):sail_values$ii))))); CapStruct_permit_execute := + ((bit_to_bool ((access_vec_dec perms (( 1 : int):sail_values$ii))))); CapStruct_global := + ((bit_to_bool ((access_vec_dec perms (( 0 : int):sail_values$ii)))))|>)))`; + + +(*val sealCap : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty24 -> (bool * Cheri_sequential_types.CapStruct)*) + +val _ = Define ` + ((sealCap:cheri_sequential_types$CapStruct ->(24)words$word -> bool#cheri_sequential_types$CapStruct) cap otype= (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`; + + +(*val getCapTop : Cheri_sequential_types.CapStruct -> Num.integer*) + +val _ = Define ` + ((getCapTop:cheri_sequential_types$CapStruct -> int) c= (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`; + + +(*val getCapOffset : Cheri_sequential_types.CapStruct -> Num.integer*) + +val _ = Define ` + ((getCapOffset:cheri_sequential_types$CapStruct -> int) c= + (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base)))) + ((pow2 (( 64 : int):sail_values$ii)))))`; + + +(*val getCapLength : Cheri_sequential_types.CapStruct -> Num.integer*) + +val _ = Define ` + ((getCapLength:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_length))`; + + +(*val getCapCursor : Cheri_sequential_types.CapStruct -> Num.integer*) + +val _ = Define ` + ((getCapCursor:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_address))`; + + +(*val incCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*) + +val _ = Define ` + ((incCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c delta= + (let (newAddr : 64 cheri_sequential_types$bits) = ((add_vec c.CapStruct_address delta : 64 words$word)) in + (T, (c with<| CapStruct_address := newAddr|>))))`; + + +(*val setCapBounds : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty65 -> (bool * Cheri_sequential_types.CapStruct)*) + +val _ = Define ` + ((setCapBounds:cheri_sequential_types$CapStruct ->(64)words$word ->(65)words$word -> bool#cheri_sequential_types$CapStruct) cap base top= + (let (length : 65 cheri_sequential_types$bits) = +((sub_vec top ((concat_vec (vec_of_bits [B0] : 1 words$word) base : 65 words$word)) : 65 words$word)) in + (T, + (cap with<| + CapStruct_base := base; CapStruct_length := + ((subrange_vec_dec length (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)); CapStruct_address := base|>))))`; + + +(*val undefined_ast : unit -> Cheri_sequential_types.M Cheri_sequential_types.ast*) + +val _ = Define ` + ((undefined_ast:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ast),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__0 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__1 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__3 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__4 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__5 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__6 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__7 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__8 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__9 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__10 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__11 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__12 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__13 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__14 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__15 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__16 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__17 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__18 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__19 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__20 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__21 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__22 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__23 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__24 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__25 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__26 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__27 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__28 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__29 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__30 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__31 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__32 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__33 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__34 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__35 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__36 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__37 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__38 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__39 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__40 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__41 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__42 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__43 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__44 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__45 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__46 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__47 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__48 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__49 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__50 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__51 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__52 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__53 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__54 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__55 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__56 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__57 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__58 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__59 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__60 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__61 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__62 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__63 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__64 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__65 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__66 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__67 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__68 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__69 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__70 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__71 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__72 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__73 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__74 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__75 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__76 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__77 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__78 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__79 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__80 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__81 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__82 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__83 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__84 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__85 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__86 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__87 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__88 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__89 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__90 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__91 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__92 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__93 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__94 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__95 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__96 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__97 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__98 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__99 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__100 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__101 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__102 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__103 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__104 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__105 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__106 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__107 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__108 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__109 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__110 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__111 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__112 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__113 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__114 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__115 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__116 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__117 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__118 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__119 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__120 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__121 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__122 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__123 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__124 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__125 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__126 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__127 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__128 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__129 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__130 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__131 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__132 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__133 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__134 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__135 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__136 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__137 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__138 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__139 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__140 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__141 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__142 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__143 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__144 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__145 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__146 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__147 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__148 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__149 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__150 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__151 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__152 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 : int):sail_values$ii) : ( 26 words$word) cheri_sequential_types$M) (\ (w__153 : 26 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 : int):sail_values$ii) : ( 26 words$word) cheri_sequential_types$M) (\ (w__154 : 26 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__155 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__156 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__157 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__158 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__159 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__160 : 16 words$word) . bindS +(undefined_bool0 () ) (\ (w__161 : bool) . bindS +(undefined_bool0 () ) (\ (w__162 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__163 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__164 : 16 words$word) . bindS +(undefined_Comparison () ) (\ (w__165 : cheri_sequential_types$Comparison) . bindS +(undefined_bool0 () ) (\ (w__166 : bool) . bindS +(undefined_bool0 () ) (\ (w__167 : bool) . bindS (seqS (seqS (seqS (seqS (seqS +(undefined_unit () ) +(undefined_unit () )) +(undefined_unit () )) +(undefined_unit () )) +(undefined_unit () )) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__168 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__169 : 5 words$word) . bindS +(undefined_Comparison () ) (\ (w__170 : cheri_sequential_types$Comparison) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__171 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__172 : 16 words$word) . bindS +(undefined_Comparison () ) (\ (w__173 : cheri_sequential_types$Comparison) . bindS +(undefined_WordType () ) (\ (w__174 : cheri_sequential_types$WordType) . bindS +(undefined_bool0 () ) (\ (w__175 : bool) . bindS +(undefined_bool0 () ) (\ (w__176 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__177 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__178 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__179 : 16 words$word) . bindS +(undefined_WordType () ) (\ (w__180 : cheri_sequential_types$WordType) . bindS +(undefined_bool0 () ) (\ (w__181 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__182 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__183 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__184 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__185 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__186 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__187 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__188 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__189 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__190 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__191 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__192 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__193 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__194 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__195 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__196 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__197 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__198 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__199 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__200 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__201 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__202 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__203 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__204 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__205 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__206 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__207 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__208 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__209 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__210 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__211 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__212 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__213 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__214 : 16 words$word) . bindS (seqS +(undefined_unit () ) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__215 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__216 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 : int):sail_values$ii) : ( 3 words$word) cheri_sequential_types$M) (\ (w__217 : 3 words$word) . bindS +(undefined_bool0 () ) (\ (w__218 : bool) . bindS (seqS +(undefined_unit () ) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__219 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__220 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 : int):sail_values$ii) : ( 3 words$word) cheri_sequential_types$M) (\ (w__221 : 3 words$word) . bindS +(undefined_bool0 () ) (\ (w__222 : bool) . bindS (seqS (seqS (seqS (seqS +(undefined_unit () ) +(undefined_unit () )) +(undefined_unit () )) +(undefined_unit () )) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__223 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__224 : 5 words$word) . bindS (seqS +(undefined_unit () ) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__225 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__226 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__227 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__228 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__229 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__230 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__231 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__232 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__233 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__234 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__235 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__236 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__237 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__238 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__239 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__240 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__241 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__242 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__243 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__244 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__245 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__246 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__247 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__248 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__249 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__250 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__251 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__252 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__253 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__254 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__255 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__256 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__257 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__258 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__259 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__260 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__261 : 5 words$word) . bindS +(undefined_CPtrCmpOp () ) (\ (w__262 : cheri_sequential_types$CPtrCmpOp) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__263 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__264 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__265 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__266 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__267 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii) : ( 11 words$word) cheri_sequential_types$M) (\ (w__268 : 11 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__269 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__270 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__271 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__272 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__273 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__274 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__275 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__276 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii) : ( 11 words$word) cheri_sequential_types$M) (\ (w__277 : 11 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__278 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__279 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__280 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__281 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__282 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__283 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__284 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__285 : 5 words$word) . bindS +(undefined_bool0 () ) (\ (w__286 : bool) . bindS +(undefined_ClearRegSet () ) (\ (w__287 : cheri_sequential_types$ClearRegSet) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__288 : 16 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__289 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__290 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__291 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__292 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__293 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__294 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__295 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__296 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__297 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__298 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__299 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__300 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__301 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__302 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__303 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__304 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__305 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__306 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__307 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__308 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__309 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__310 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__311 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__312 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__313 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__314 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__315 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii) : ( 11 words$word) cheri_sequential_types$M) (\ (w__316 : 11 words$word) . bindS (seqS +(undefined_unit () ) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M)) (\ (w__317 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__318 : 16 words$word) . bindS +(undefined_bool0 () ) (\ (w__319 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__320 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__321 : 16 words$word) . bindS +(undefined_bool0 () ) (\ (w__322 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__323 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__324 : 5 words$word) . bindS +(undefined_bool0 () ) (\ (w__325 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__326 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__327 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__328 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__329 : 8 words$word) . bindS +(undefined_bool0 () ) (\ (w__330 : bool) . bindS +(undefined_WordType () ) (\ (w__331 : cheri_sequential_types$WordType) . bindS +(undefined_bool0 () ) (\ (w__332 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__333 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__334 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__335 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__336 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__337 : 8 words$word) . bindS +(undefined_WordType () ) (\ (w__338 : cheri_sequential_types$WordType) . bindS +(undefined_bool0 () ) (\ (w__339 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__340 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__341 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__342 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__343 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii) : ( 11 words$word) cheri_sequential_types$M) (\ (w__344 : 11 words$word) . bindS +(undefined_bool0 () ) (\ (w__345 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__346 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__347 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__348 : 5 words$word) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii) : ( 11 words$word) cheri_sequential_types$M) (\ (w__349 : 11 words$word) . bindS +(undefined_bool0 () ) (\ (w__350 : bool) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__351 : 5 words$word) . seqS +(undefined_unit () ) +(internal_pick + [DADDIU (w__0,w__1,w__2);DADDU (w__3,w__4,w__5);DADDI (w__6,w__7,w__8);DADD (w__9,w__10,w__11);ADD (w__12,w__13,w__14);ADDI (w__15,w__16,w__17);ADDU (w__18,w__19,w__20);ADDIU (w__21,w__22,w__23);DSUBU (w__24,w__25,w__26);DSUB (w__27,w__28,w__29);SUB0 (w__30,w__31,w__32);SUBU (w__33,w__34,w__35);AND (w__36,w__37,w__38);ANDI (w__39,w__40,w__41);OR (w__42,w__43,w__44);ORI (w__45,w__46,w__47);NOR (w__48,w__49,w__50);XOR (w__51,w__52,w__53);XORI (w__54,w__55,w__56);LUI (w__57,w__58);DSLL (w__59,w__60,w__61);DSLL32 (w__62,w__63,w__64);DSLLV (w__65,w__66,w__67);DSRA (w__68,w__69,w__70);DSRA32 (w__71,w__72,w__73);DSRAV (w__74,w__75,w__76);DSRL (w__77,w__78,w__79);DSRL32 (w__80,w__81,w__82);DSRLV (w__83,w__84,w__85);SLL (w__86,w__87,w__88);SLLV (w__89,w__90,w__91);SRA (w__92,w__93,w__94);SRAV (w__95,w__96,w__97);SRL (w__98,w__99,w__100);SRLV (w__101,w__102,w__103);SLT (w__104,w__105,w__106);SLTI (w__107,w__108,w__109);SLTU (w__110,w__111,w__112);SLTIU (w__113,w__114,w__115);MOVN (w__116,w__117,w__118);MOVZ (w__119,w__120,w__121);MFHI w__122;MFLO w__123;MTHI w__124;MTLO w__125;MUL (w__126,w__127,w__128);MULT (w__129,w__130);MULTU (w__131,w__132);DMULT (w__133,w__134);DMULTU (w__135,w__136);MADD (w__137,w__138);MADDU (w__139,w__140);MSUB (w__141,w__142);MSUBU (w__143,w__144);DIV0 (w__145,w__146);DIVU (w__147,w__148);DDIV (w__149,w__150);DDIVU (w__151,w__152);J w__153;JAL w__154;JR w__155;JALR (w__156,w__157);BEQ (w__158,w__159,w__160,w__161,w__162);BCMPZ (w__163,w__164,w__165,w__166,w__167);SYSCALL_THREAD_START () ;ImplementationDefinedStopFetching () ;SYSCALL () ;BREAK () ;WAIT () ;TRAPREG (w__168,w__169,w__170);TRAPIMM (w__171,w__172,w__173);Load (w__174,w__175,w__176,w__177,w__178,w__179);Store (w__180,w__181,w__182,w__183,w__184);LWL (w__185,w__186,w__187);LWR (w__188,w__189,w__190);SWL (w__191,w__192,w__193);SWR (w__194,w__195,w__196);LDL (w__197,w__198,w__199);LDR (w__200,w__201,w__202);SDL (w__203,w__204,w__205);SDR (w__206,w__207,w__208);CACHE (w__209,w__210,w__211);PREF (w__212,w__213,w__214);SYNC () ;MFC0 (w__215,w__216,w__217,w__218);HCF () ;MTC0 (w__219,w__220,w__221,w__222);TLBWI () ;TLBWR () ;TLBR () ;TLBP () ;RDHWR (w__223,w__224);ERET () ;CGetPerm (w__225,w__226);CGetType (w__227,w__228);CGetBase (w__229,w__230);CGetLen (w__231,w__232);CGetTag (w__233,w__234);CGetSealed (w__235,w__236);CGetOffset (w__237,w__238);CGetAddr (w__239,w__240);CGetPCC w__241;CGetPCCSetOffset (w__242,w__243);CGetCause w__244;CSetCause w__245;CReadHwr (w__246,w__247);CWriteHwr (w__248,w__249);CAndPerm (w__250,w__251,w__252);CToPtr (w__253,w__254,w__255);CSub (w__256,w__257,w__258);CPtrCmp (w__259,w__260,w__261,w__262);CIncOffset (w__263,w__264,w__265);CIncOffsetImmediate (w__266,w__267,w__268);CSetOffset (w__269,w__270,w__271);CSetBounds (w__272,w__273,w__274);CSetBoundsImmediate (w__275,w__276,w__277);CSetBoundsExact (w__278,w__279,w__280);CClearTag (w__281,w__282);CMOVX (w__283,w__284,w__285,w__286);ClearRegs (w__287,w__288);CFromPtr (w__289,w__290,w__291);CBuildCap (w__292,w__293,w__294);CCopyType (w__295,w__296,w__297);CCheckPerm (w__298,w__299);CCheckType (w__300,w__301);CTestSubset (w__302,w__303,w__304);CSeal (w__305,w__306,w__307);CCSeal (w__308,w__309,w__310);CUnseal (w__311,w__312,w__313);CCall (w__314,w__315,w__316);CReturn () ;CBX (w__317,w__318,w__319);CBZ (w__320,w__321,w__322);CJALR (w__323,w__324,w__325);CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332);CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339);CSC (w__340,w__341,w__342,w__343,w__344,w__345);CLC (w__346,w__347,w__348,w__349,w__350);C2Dump w__351;RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +(*val execute : Cheri_sequential_types.ast -> Cheri_sequential_types.M unit*) + +(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Cheri_sequential_types.ast*) + +val _ = Define ` +((DDC:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((IDC:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((KR1C:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((KR2C:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((KCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))`; + + +val _ = Define ` +((KDC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((EPCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((CapRegs:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapReg))sail_values$register_ref)list)= + ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref; + C10_ref;C09_ref;C08_ref;C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`; + + +val _ = Define ` + ((max_otype:int)= (MAX0 (( 24 : int):sail_values$ii)))`; + + +val _ = Define ` + ((have_cp2:bool)= T)`; + + +(*val readCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*) + +val _ = Define ` + ((readCapReg:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n= + (let i = (lem$w2ui n) in bindS + (read_regS ((access_list_dec CapRegs i : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) + : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . + returnS ((capRegToCapStruct w__0)))))`; + + +(*val writeCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((writeCapReg:(5)words$word -> cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n cap= + (let i = (lem$w2ui n) in + write_regS + ((access_list_dec CapRegs i : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) + ((capStructToCapReg cap : 257 words$word))))`; + + +(*val CapEx_of_num : Num.integer -> Cheri_sequential_types.CapEx*) + +val _ = Define ` + ((CapEx_of_num:int -> cheri_sequential_types$CapEx) arg_= + (let l__32 = arg_ in + if (((l__32 = (( 0 : int):sail_values$ii)))) then CapEx_None + else if (((l__32 = (( 1 : int):sail_values$ii)))) then CapEx_LengthViolation + else if (((l__32 = (( 2 : int):sail_values$ii)))) then CapEx_TagViolation + else if (((l__32 = (( 3 : int):sail_values$ii)))) then CapEx_SealViolation + else if (((l__32 = (( 4 : int):sail_values$ii)))) then CapEx_TypeViolation + else if (((l__32 = (( 5 : int):sail_values$ii)))) then CapEx_CallTrap + else if (((l__32 = (( 6 : int):sail_values$ii)))) then CapEx_ReturnTrap + else if (((l__32 = (( 7 : int):sail_values$ii)))) then CapEx_TSSUnderFlow + else if (((l__32 = (( 8 : int):sail_values$ii)))) then CapEx_UserDefViolation + else if (((l__32 = (( 9 : int):sail_values$ii)))) then CapEx_TLBNoStoreCap + else if (((l__32 = (( 10 : int):sail_values$ii)))) then CapEx_InexactBounds + else if (((l__32 = (( 11 : int):sail_values$ii)))) then CapEx_GlobalViolation + else if (((l__32 = (( 12 : int):sail_values$ii)))) then CapEx_PermitExecuteViolation + else if (((l__32 = (( 13 : int):sail_values$ii)))) then CapEx_PermitLoadViolation + else if (((l__32 = (( 14 : int):sail_values$ii)))) then CapEx_PermitStoreViolation + else if (((l__32 = (( 15 : int):sail_values$ii)))) then CapEx_PermitLoadCapViolation + else if (((l__32 = (( 16 : int):sail_values$ii)))) then CapEx_PermitStoreCapViolation + else if (((l__32 = (( 17 : int):sail_values$ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((l__32 = (( 18 : int):sail_values$ii)))) then CapEx_PermitSealViolation + else if (((l__32 = (( 19 : int):sail_values$ii)))) then CapEx_AccessSystemRegsViolation + else if (((l__32 = (( 20 : int):sail_values$ii)))) then CapEx_PermitCCallViolation + else if (((l__32 = (( 21 : int):sail_values$ii)))) then CapEx_AccessCCallIDCViolation + else CapEx_PermitUnsealViolation))`; + + +(*val num_of_CapEx : Cheri_sequential_types.CapEx -> Num.integer*) + +val _ = Define ` + ((num_of_CapEx:cheri_sequential_types$CapEx -> int) arg_= + ((case arg_ of + CapEx_None => (( 0 : int):sail_values$ii) + | CapEx_LengthViolation => (( 1 : int):sail_values$ii) + | CapEx_TagViolation => (( 2 : int):sail_values$ii) + | CapEx_SealViolation => (( 3 : int):sail_values$ii) + | CapEx_TypeViolation => (( 4 : int):sail_values$ii) + | CapEx_CallTrap => (( 5 : int):sail_values$ii) + | CapEx_ReturnTrap => (( 6 : int):sail_values$ii) + | CapEx_TSSUnderFlow => (( 7 : int):sail_values$ii) + | CapEx_UserDefViolation => (( 8 : int):sail_values$ii) + | CapEx_TLBNoStoreCap => (( 9 : int):sail_values$ii) + | CapEx_InexactBounds => (( 10 : int):sail_values$ii) + | CapEx_GlobalViolation => (( 11 : int):sail_values$ii) + | CapEx_PermitExecuteViolation => (( 12 : int):sail_values$ii) + | CapEx_PermitLoadViolation => (( 13 : int):sail_values$ii) + | CapEx_PermitStoreViolation => (( 14 : int):sail_values$ii) + | CapEx_PermitLoadCapViolation => (( 15 : int):sail_values$ii) + | CapEx_PermitStoreCapViolation => (( 16 : int):sail_values$ii) + | CapEx_PermitStoreLocalCapViolation => (( 17 : int):sail_values$ii) + | CapEx_PermitSealViolation => (( 18 : int):sail_values$ii) + | CapEx_AccessSystemRegsViolation => (( 19 : int):sail_values$ii) + | CapEx_PermitCCallViolation => (( 20 : int):sail_values$ii) + | CapEx_AccessCCallIDCViolation => (( 21 : int):sail_values$ii) + | CapEx_PermitUnsealViolation => (( 22 : int):sail_values$ii) + )))`; + + +(*val undefined_CapEx : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapEx*) + +val _ = Define ` + ((undefined_CapEx:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapEx),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = + (internal_pick + [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`; + + +(*val CapExCode : Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((CapExCode:cheri_sequential_types$CapEx ->(8)words$word) ex= + ((case ex of + CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) + | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) + | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) + | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : 8 words$word) + | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word) + | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) + | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) + | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) + | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0] : 8 words$word) + | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1] : 8 words$word) + | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1] : 8 words$word) + | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0] : 8 words$word) + | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1] : 8 words$word) + | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0] : 8 words$word) + | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1] : 8 words$word) + | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) + | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1] : 8 words$word) + | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0] : 8 words$word) + | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1] : 8 words$word) + )))`; + + +(*val undefined_CapCauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapCauseReg*) + +val _ = Define ` + ((undefined_CapCauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapCauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__0 : 16 words$word) . + internal_pick [Mk_CapCauseReg w__0])))`; + + +val _ = Define ` + ((get_CapCauseReg:cheri_sequential_types$CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))= v)`; + + +val _ = Define ` + ((set_CapCauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ r . + let r = (Mk_CapCauseReg v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; + + +val _ = Define ` + ((set_CapCauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . + let r = ((get_CapCauseReg w__0 : 16 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 16 words$word)) in + write_regS r_ref (Mk_CapCauseReg r))))`; + + +val _ = Define ` + ((update_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x= + (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 16 words$word))))`; + + +(*val _get_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_CapCauseReg_RegNum : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((set_CapCauseReg_RegNum:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . + let r = ((get_CapCauseReg w__0 : 16 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 16 words$word)) in + write_regS r_ref (Mk_CapCauseReg r))))`; + + +(*val _update_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*) + +val _ = Define ` + ((update_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x= + (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 16 words$word))))`; + + +(*val execute_branch_pcc : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_branch_pcc:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) newPCC= (seqS (seqS +(write_regS + delayedPC_ref + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapOffset newPCC)) : 64 words$word))) +(write_regS delayedPCC_ref ((capStructToCapReg newPCC : 257 words$word)))) +(write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + + +(*val ERETHook : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((ERETHook:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS C31_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS nextPCC_ref w__0) + (read_regS C31_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__1 : cheri_sequential_types$CapReg) . write_regS delayedPCC_ref w__1))))`; + + +(*val raise_c2_exception8 : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M 'o*) + +val _ = Define ` + ((raise_c2_exception8:cheri_sequential_types$CapEx ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum= (seqS (seqS +(set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx : 8 words$word))) +(set_CapCauseReg_RegNum CapCause_ref regnum)) +(let mipsEx = +(if ((((((capEx = CapEx_CallTrap))) \/ (((capEx = CapEx_ReturnTrap)))))) then C2Trap + else C2E) in + SignalException mipsEx)))`; + + +(*val raise_c2_exception : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M 'o*) + +val _ = Define ` + ((raise_c2_exception:cheri_sequential_types$CapEx ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum= + (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) regnum : 8 words$word)) in + if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then + raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 + else raise_c2_exception8 capEx reg8))`; + + +(*val raise_c2_exception_noreg : forall 'o. Cheri_sequential_types.CapEx -> Cheri_sequential_types.M 'o*) + +val _ = Define ` + ((raise_c2_exception_noreg:cheri_sequential_types$CapEx ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx= + (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)))`; + + +(*val pcc_access_system_regs : unit -> Cheri_sequential_types.M bool*) + +val _ = Define ` + ((pcc_access_system_regs:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . + let pcc = (capRegToCapStruct w__0) in + returnS pcc.CapStruct_access_system_regs)))`; + + +(*val register_inaccessible : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M bool*) + +val _ = Define ` + ((register_inaccessible:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r= (bindS + (read_regS inCCallDelay_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__0 : 1 words$word) . + if ((((((r = IDC))) /\ ((bits_to_bool w__0))))) then returnS T + else + let b__0 = r in + let (is_sys_reg : bool) = +(if (((b__0 = (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))) then T + else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))) then T + else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then T + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) then T + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))) then T + else F) in + if is_sys_reg then bindS (pcc_access_system_regs () ) (\ (w__1 : bool) . returnS ((~ w__1))) + else returnS F)))`; + + +(*val MEMr_tagged : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*) + +val _ = Define ` + ((MEMr_tagged:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr= (bindS (seqS +(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") +(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . bindS + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) cheri_sequential_types$M) (\ data . + let ((cast_0 : bool), (cast_1 : 256 words$word)) = (tag, (reverse_endianness data : 256 words$word)) in + returnS (cast_0, (words$w2w cast_1 : 256 words$word))))))`; + + +(*val MEMr_tagged_reserve : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*) + +val _ = Define ` + ((MEMr_tagged_reserve:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr= (bindS (seqS +(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") +(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . bindS + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) cheri_sequential_types$M) (\ data . + let ((cast_0 : bool), (cast_1 : 256 words$word)) = (tag, (reverse_endianness data : 256 words$word)) in + returnS (cast_0, (words$w2w cast_1 : 256 words$word))))))`; + + +(*val MEMw_tagged : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data= (seqS (seqS (seqS +(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") +(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) +(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`; + + +(*val MEMw_tagged_conditional : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M bool*) + +val _ = Define ` + ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data= (bindS (seqS (seqS +(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") +(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) +(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (\ success . seqS + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else returnS () ) (returnS success))))`; + + +val _ = Define ` + ((cap_addr_mask:(64)words$word)= + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((((pow2 (( 64 : int):sail_values$ii))) - cap_size)) + : 64 words$word)))`; + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data= + (let ledata = ((reverse_endianness data : 'p8_times_n_ words$word)) in + if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))) then seqS +(write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word))) +(write_regS UART_WRITTEN_ref (vec_of_bits [B1] : 1 words$word)) + else seqS (seqS (seqS +(assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + ((size1 - (( 1 : int):sail_values$ii))) + : 64 words$word)) + : 64 words$word)) cap_addr_mask + : 64 words$word))))) "") +(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) +(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F)))`; + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M bool*) + +val _ = Define ` + ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data= (bindS (seqS (seqS +(assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + ((size1 - (( 1 : int):sail_values$ii))) + : 64 words$word)) + : 64 words$word)) cap_addr_mask + : 64 words$word))))) "") +(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) +(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))) (\ success . seqS + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F + else returnS () ) +(returnS success))))`; + + +(*val addrWrapper : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.WordType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((addrWrapper:(64)words$word -> cheri_sequential_types$MemAccessType -> cheri_sequential_types$WordType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr accessType width= + (let capno = ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)) in bindS +(readCapReg capno) (\ cap . seqS (seqS + (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno + else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno + else returnS () ) + (case accessType of + Instruction => + if ((~ cap.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation capno + else returnS () + | LoadData => + if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno + else returnS () + | StoreData => + if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno + else returnS () + )) +(let cursor = (getCapCursor cap) in + let vAddr = (hardware_mod ((cursor + ((lem$w2ui addr)))) ((pow2 (( 64 : int):sail_values$ii)))) in + let size1 = (wordWidthBytes width) in + let base = (getCapBase cap) in + let top = (getCapTop cap) in + if ((((vAddr + size1)) > top)) then + (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) cheri_sequential_types$M) + else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) cheri_sequential_types$M) + else returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word))))))`; + + +(*val TranslatePC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((TranslatePC:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr= (bindS (seqS +(incrementCP0Count () ) + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__0 : 257 words$word) . + let pcc = (capRegToCapStruct w__0) in + let base = (getCapBase pcc) in + let top = (getCapTop pcc) in + let absPC = (base + ((lem$w2ui vAddr))) in + if (((((absPC % (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then + (SignalExceptionBadAddr AdEL + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) absPC : 64 words$word)) + : ( 64 words$word) cheri_sequential_types$M) + else if ((~ pcc.CapStruct_tag)) then + (raise_c2_exception_noreg CapEx_TagViolation : ( 64 words$word) cheri_sequential_types$M) + else if ((((absPC + (( 4 : int):sail_values$ii))) > top)) then + (raise_c2_exception_noreg CapEx_LengthViolation : ( 64 words$word) cheri_sequential_types$M) + else + (TLBTranslate ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) absPC : 64 words$word)) + Instruction + : ( 64 words$word) cheri_sequential_types$M))))`; + + +(*val checkCP2usable : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((checkCP2usable:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 2 : int):sail_values$ii))))))) then seqS +(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : 2 words$word)) (SignalException CpU) + else returnS () )))`; + + +val _ = Define ` + ((init_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = + (let defaultBits = ((capStructToCapReg default_cap : 257 words$word)) in seqS (seqS (seqS +(write_regS PCC_ref defaultBits) +(write_regS nextPCC_ref defaultBits)) +(write_regS delayedPCC_ref defaultBits)) + (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () + (\ i unit_var . + let idx = ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) in + writeCapReg idx default_cap))))`; + + +val _ = Define ` + ((cp2_next_pc:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS nextPCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS PCC_ref w__0) + (read_regS inBranchDelay_ref : ( 1 words$word) cheri_sequential_types$M)) (\ (w__1 : 1 words$word) . + if ((bits_to_bool w__1)) then bindS + (read_regS delayedPCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 : cheri_sequential_types$CapReg) . + write_regS nextPCC_ref w__2) + else write_regS inCCallDelay_ref (vec_of_bits [B0] : 1 words$word)))))`; + + +(*val capToString : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M string*) + +val _ = Define ` + ((capToString:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((string),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cap= (seqS +(skip () ) +(returnS ((STRCAT " t:" + ((STRCAT (if cap.CapStruct_tag then "1" else "0") + ((STRCAT " s:" + ((STRCAT (if cap.CapStruct_sealed then "1" else "0") + ((STRCAT " perms:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((getCapPerms cap : 31 words$word)) + : 32 words$word)))) + ((STRCAT " type:" + ((STRCAT ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype)) + ((STRCAT " offset:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + ((getCapOffset cap)) + : 64 words$word)))) + ((STRCAT " base:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):sail_values$ii) + : 64 itself)) + ((getCapBase cap)) + : 64 words$word)))) + ((STRCAT " length:" + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):sail_values$ii) + : 64 itself)) + ((int_min ((getCapLength cap)) + ((MAX0 (( 64 : int):sail_values$ii))))) + : 64 words$word)))))))))))))))))))))))))))))))))`; + + +val _ = Define ` + ((dump_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . bindS +(capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . + let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in + (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () + (\ i unit_var . bindS +(readCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word))) (\ (w__2 : + cheri_sequential_types$CapStruct) . bindS +(capToString w__2) (\ (w__3 : string) . + returnS (let _ = +(prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int + instance_Show_Show_Num_integer_dict i)) w__3))))) in + () )))))))))`; + + +(*val extendLoad : forall 'sz . Size 'sz => Machine_word.mword 'sz -> bool -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign= + (if sign then (sign_extend1 (( 64 : int):sail_values$ii) memResult : 64 words$word) + else (zero_extend1 (( 64 : int):sail_values$ii) memResult : 64 words$word)))`; + + +(*val TLBWriteEntry : Machine_word.mword Machine_word.ty6 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((TLBWriteEntry:(6)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx= (bindS + (read_regS TLBPageMask_ref : ( 16 words$word) cheri_sequential_types$M) (\ pagemask . + let b__0 = pagemask in seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) + then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + returnS () + else SignalException MCheck) +(let i = (lem$w2ui idx) in + let entry = (access_list_dec TLBEntries i) in bindS (seqS +(set_TLBEntry_pagemask entry pagemask) +(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS +(set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 : 2 words$word))) +(read_regS TLBEntryHi_ref)) (\ (w__1 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS +(set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 : 27 words$word))) +(read_regS TLBEntryHi_ref)) (\ (w__2 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS +(set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 : 8 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) . bindS +(read_regS TLBEntryLo1_ref) (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS (seqS +(set_TLBEntry_g entry + ((bool_to_bits + (((((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))) /\ ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word))))))) + : 1 words$word))) +(set_TLBEntry_valid entry ((cast_unit_vec0 B1 : 1 words$word)))) +(read_regS TLBEntryLo0_ref)) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__5 : 1 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__6 : 1 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__7 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__7 : 24 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__8 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__8 : 3 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__9 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__9 : 1 words$word))) +(read_regS TLBEntryLo0_ref)) (\ (w__10 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__10 : 1 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__11 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__11 : 1 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__12 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__12 : 1 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__13 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__13 : 24 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__14 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__14 : 3 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__15 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__15 : 1 words$word))) +(read_regS TLBEntryLo1_ref)) (\ (w__16 : cheri_sequential_types$TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__16 : 1 words$word)))))))))))))))))))))))`; + + +val _ = Define ` + ((decode:(32)words$word ->(cheri_sequential_types$ast)option) v__0= + (if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (DADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (DADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DADD (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (ADD (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (ADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DSUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DSUB (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SUB0 (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (AND (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ANDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (OR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ORI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (NOR (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (XOR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (XORI (rs,rt,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (LUI (rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSLL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DSLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRA32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (DSRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (SLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (SRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (SRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SLT (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SLTI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (SLTU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SLTIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (MOVN (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (MOVZ (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (MFHI rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (MFLO rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : 21 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + SOME (MTHI rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : 21 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + SOME (MTLO rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (MUL (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DMULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DMULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MADD (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MADDU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MSUB (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (MSUBU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DIV0 (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DIVU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DDIV (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (DDIVU (rs,rt)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 26 words$word)) in + SOME (J offset) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 26 words$word)) in + SOME (JAL offset) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + SOME (JR rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (JALR (rs,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,T)) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B0;B0;B1;B1;B0;B0] + : 32 words$word)))) then + SOME (SYSCALL_THREAD_START () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + SOME (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then + SOME (BREAK () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] + : 32 words$word)))) then + SOME (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LTU)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (B,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (B,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (H,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (H,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (W0,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (W0,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (D,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (W0,T,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Load (D,F,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (B,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (H,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (W0,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (D,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (W0,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (Store (D,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (LWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (LWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (LDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (LDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (SDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (CACHE (base,op,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word)))) then + let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (PREF (base,op,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then + SOME (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,T)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] + : 32 words$word)))) then + SOME (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : 32 words$word)))) then + SOME (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : 32 words$word)))) then + SOME (TLBR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : 11 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (RDHWR (rt,rd)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (ERET () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetPerm (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetType (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetBase (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetLen (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetTag (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetSealed (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) + then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetCause rd) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)))) then + SOME (CReturn () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetOffset (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetCause rt) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CAndPerm (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CToPtr (rd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CNE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CNEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CIncOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetBounds (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CClearTag (cd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CFromPtr (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CCheckPerm (cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CCheckType (cs,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CUnseal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CJALR (cd,cb,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetCause rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetCause rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetPCC cd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CCheckPerm (cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CCheckType (cs,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CClearTag (cd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CJALR (cd,cb,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetPerm (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetType (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetBase (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetLen (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetTag (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetSealed (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetOffset (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetPCCSetOffset (cd,rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CReadHwr (cd,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CWriteHwr (cb,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CGetAddr (cb,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CUnseal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CAndPerm (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetOffset (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetBounds (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSetBoundsExact (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CIncOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CBuildCap (cd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CCopyType (cd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CCSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CToPtr (rd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CFromPtr (cd,cb,rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word))))))) then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSub (rt,cb,cs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,rs,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,rs,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CNE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CNEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CTestSubset (rd,cb,ct)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (CBX (cd,imm,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (CBX (cd,imm,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (CBZ (cd,imm,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (CBZ (cd,imm,T)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 32 words$word)))) then + SOME (CReturn () ) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1] : 11 words$word)))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (selector : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in + SOME (CCall (cs,cb,selector)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 16 words$word)))) then + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ClearRegs (GPLo,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1] : 16 words$word)))) then + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ClearRegs (GPHi,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0] : 16 words$word)))) then + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ClearRegs (CLo,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1] : 16 words$word)))) then + let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in + SOME (ClearRegs (CHi,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in + SOME (CIncOffsetImmediate (cd,cb,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0] : 11 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in + SOME (CSetBoundsImmediate (cd,cb,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,D,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),F,B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),T,B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),F,H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),T,H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),F,W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),T,W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),F,D,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,D,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : 8 words$word),D,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word)))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in + SOME (CSC (cs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in + SOME (CSC (cs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 11 words$word),T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word)))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in + SOME (CLC (cd,cb,rt,offset,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in + SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 11 words$word),T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 16 words$word))))))) + then + let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in + SOME (C2Dump rt) + else SOME (RI () )))`; + + +(*val execute_XORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_XOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((xor_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_WAIT : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_WAIT:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__120= (bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS nextPC_ref w__0)))`; + + +(*val execute_TRAPREG : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TRAPREG:(5)words$word ->(5)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt cmp= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . + let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else returnS () ))))`; + + +(*val execute_TRAPIMM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TRAPIMM:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . + let (imm_val : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in + let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else returnS () )))`; + + +(*val execute_TLBWR : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TLBWR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__124= (bindS (seqS +(checkCP0Access () ) + (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBWI : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TLBWI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__123= (bindS (seqS +(checkCP0Access () ) + (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBR : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TLBR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__125= (bindS (seqS +(checkCP0Access () ) + (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : cheri_sequential_types$TLBIndexT) . + let i = (lem$w2ui w__0) in bindS +(read_regS ((access_list_dec TLBEntries i))) (\ entry . seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS +(write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) +(set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry : 2 words$word)))) +(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry : 27 words$word)))) +(set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry : 8 words$word)))) +(set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry : 1 words$word)))) +(set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry : 1 words$word)))) +(set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry : 24 words$word)))) +(set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry : 3 words$word)))) +(set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry : 1 words$word)))) +(set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry : 1 words$word)))) +(set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry : 1 words$word)))) +(set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry : 1 words$word)))) +(set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry : 1 words$word)))) +(set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry : 24 words$word)))) +(set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry : 3 words$word)))) +(set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry : 1 words$word)))) +(set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry : 1 words$word)))) +(set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry : 1 words$word)))))))`; + + +(*val execute_TLBP : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_TLBP:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__126= (bindS (seqS +(checkCP0Access () ) +(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . bindS + (tlbSearch ((get_TLBEntryHiReg w__0 : 64 words$word)) : ( ( 6 words$word)option) cheri_sequential_types$M) (\ result . + (case result of + SOME (idx) => seqS +(write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (write_regS TLBIndex_ref idx) + | NONE => seqS +(write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) + )))))`; + + +(*val execute_Store : Cheri_sequential_types.WordType -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_Store:cheri_sequential_types$WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width conditional base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData width + : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . + if conditional then bindS + (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) . bindS + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii) + ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii) + ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + | W0 => + MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii) + ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rt_val + ) + else returnS F) (\ (success : bool) . + wGPR rt ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rt_val + )))))))`; + + +(*val execute_SYSCALL_THREAD_START : unit -> unit*) + +val _ = Define ` + ((execute_SYSCALL_THREAD_START:unit -> unit) g__116= () )`; + + +(*val execute_SYSCALL : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SYSCALL:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__118= (SignalException Sys))`; + + +(*val execute_SYNC : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SYNC:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__121= (MEM_sync () ))`; + + +(*val execute_SWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData W0 + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . + let wordAddr = +((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__12 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in + if (((b__12 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + else if (((b__12 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + else if (((b__12 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + else MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))))))))`; + + +(*val execute_SWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData W0 + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__8 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in + if (((b__8 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + else if (((b__8 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) + else if (((b__8 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word))))))))`; + + +(*val execute_SUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 : int):sail_values$ii) + ((sub_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (temp33 : 33 cheri_sequential_types$bits) = +((sub_vec + ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):sail_values$ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec temp33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in + if ((NotWordVal temp)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . + if ((NotWordVal temp)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; + + +(*val execute_SRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in + if ((NotWordVal temp)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . + if ((NotWordVal temp)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; + + +(*val execute_SLTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . + wGPR rd + ((zero_extend1 (( 64 : int):sail_values$ii) + (if ((((lem$w2ui rs_val) < (lem$w2ui rt_val)))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLTIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . + let (immext : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in + wGPR rt + ((zero_extend1 (( 64 : int):sail_values$ii) + (if ((((lem$w2ui rs_val) < (lem$w2ui immext)))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLTI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= + (let imm_val = (integer_word$w2i imm) in bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs_val = (integer_word$w2i w__0) in + wGPR rt + ((zero_extend1 (( 64 : int):sail_values$ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd + ((zero_extend1 (( 64 : int):sail_values$ii) + (if ((((integer_word$w2i w__0) < (integer_word$w2i w__1)))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; + + +(*val execute_SDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData D + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let wordAddr = +((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) in + let b__40 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + if (((b__40 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + else if (((b__40 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) + else if (((b__40 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) + else MEMw_wrapper wordAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))))`; + + +(*val execute_SDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData D + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__32 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + if (((b__32 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) + else if (((b__32 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) + else if (((b__32 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word))))))))`; + + +(*val execute_RI : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_RI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__129= (SignalException ResI))`; + + +(*val execute_RDHWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_RDHWR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd= (bindS +(getAccessLevel () ) (\ accessLevel . + let (haveAccessLevel : bool) = (accessLevel = Kernel) in bindS +(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . + let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):sail_values$ii)))) in + let rdi = (lem$w2ui rd) in bindS + (read_regS CP0HWREna_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . + let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in seqS + (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI + else returnS () ) +(let b__146 = rd in bindS + (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then + returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) then + returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then bindS + (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 cheri_sequential_types$bits) . + returnS ((zero_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word))) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) then + returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then + (read_regS CP0UserLocal_ref : ( 64 words$word) cheri_sequential_types$M) + else (SignalException ResI : ( 64 words$word) cheri_sequential_types$M)) (\ (temp : 64 cheri_sequential_types$bits) . + wGPR rt temp)))))))`; + + +(*val execute_PREF : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> unit*) + +val _ = Define ` + ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm= () )`; + + +(*val execute_ORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_OR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((or_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_NOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 : 64 words$word)) : 64 words$word))))))`; + + +(*val execute_MULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 cheri_sequential_types$bits) . seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))`; + + +(*val execute_MULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 cheri_sequential_types$bits) . seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))`; + + +(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . + let (result : 64 cheri_sequential_types$bits) = +((sign_extend1 (( 64 : int):sail_values$ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (w__1 : 64 words$word) . + wGPR rd w__1)))))`; + + +(*val execute_MTLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MTLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS LO_ref w__0)))`; + + +(*val execute_MTHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MTHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS HI_ref w__0)))`; + + +(*val execute_MTC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double= (bindS (seqS +(checkCP0Access () ) + (rGPR rt : ( 64 words$word) cheri_sequential_types$M)) (\ reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + write_regS TLBIndex_ref + ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word)) else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + returnS () else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg TLBEntryLo0_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg TLBEntryLo1_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 : int): sail_values$ii) + (( 23 : int): sail_values$ii) : 41 words$word)) else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + write_regS CP0UserLocal_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + write_regS TLBPageMask_ref + ((subrange_vec_dec reg_val (( 28 : int): sail_values$ii) + (( 13 : int): sail_values$ii) : 16 words$word)) else + if ((((((b__108 = + (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + seqS + (write_regS TLBWired_ref + ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word))) + (write_regS TLBRandom_ref TLBIndexMax) else + if ((((((b__108 = + (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + write_regS CP0HWREna_ref + ((concat_vec + ((subrange_vec_dec reg_val + (( 31 : int): sail_values$ii) + (( 29 : int): sail_values$ii) : 3 words$word)) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] : 25 words$word) + ((subrange_vec_dec reg_val + (( 3 : int): sail_values$ii) + (( 0 : int): sail_values$ii) : 4 words$word)) + : 29 words$word)) : 32 words$word)) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + returnS () else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + write_regS CP0Count_ref + ((subrange_vec_dec reg_val + (( 31 : int): sail_values$ii) + (( 0 : int): sail_values$ii) : 32 words$word)) + else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + seqS + (seqS + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val + (( 63 : int): sail_values$ii) + (( 62 : int): sail_values$ii) : 2 words$word))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val + (( 39 : int): sail_values$ii) + (( 13 : int): sail_values$ii) : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val + (( 7 : int): sail_values$ii) + (( 0 : int): sail_values$ii) : 8 words$word))) + else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (seqS + (write_regS CP0Compare_ref + ((subrange_vec_dec reg_val + (( 31 : int): sail_values$ii) + (( 0 : int): sail_values$ii) : 32 words$word))) + (read_regS CP0Cause_ref)) + (\ (w__0 : cheri_sequential_types$CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec + ((get_CauseReg_IP w__0 : 8 words$word)) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) + : 8 words$word))) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + seqS + (seqS + (seqS + (seqS + (seqS + (seqS + (seqS + (seqS + (seqS + (set_StatusReg_CU + CP0Status_ref + ((subrange_vec_dec + reg_val + (( 31 : int): sail_values$ii) + (( 28 : int): sail_values$ii) : 4 words$word))) + (set_StatusReg_BEV + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( + 22 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_IM + CP0Status_ref + ((subrange_vec_dec + reg_val + (( 15 : int): sail_values$ii) + (( 8 : int): sail_values$ii) : 8 words$word)))) + (set_StatusReg_KX + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( 7 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_SX + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( 6 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 5 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_KSU CP0Status_ref + ((subrange_vec_dec reg_val + (( 4 : int): sail_values$ii) + (( 3 : int): sail_values$ii) : 2 words$word)))) + (set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 2 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 1 : int): sail_values$ii))) : 1 words$word)))) + (set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 0 : int): sail_values$ii))) : 1 words$word))) + else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (seqS + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 23 : int): sail_values$ii))) : 1 words$word))) + (read_regS CP0Cause_ref)) + (\ (w__1 : cheri_sequential_types$CauseReg) . + let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec + ((subrange_vec_dec ip + (( 7 : int): sail_values$ii) + (( 2 : int): sail_values$ii) : 6 words$word)) + ((subrange_vec_dec reg_val + (( 9 : int): sail_values$ii) + (( 8 : int): sail_values$ii) : 2 words$word)) + : 8 words$word))) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + write_regS CP0EPC_ref reg_val else + if ((((((b__108 = + (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + returnS () else + if ((((((b__108 = + (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_XContextReg_XPTEBase + TLBXContext_ref + ((subrange_vec_dec reg_val + (( 63 : int): sail_values$ii) + (( 33 : int): sail_values$ii) : 31 words$word)) + else write_regS CP0ErrorEPC_ref reg_val + ))))`; + + +(*val execute_MSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MSUBU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS + (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS + (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . + let result = +((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MSUB:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS + (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS + (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . + let result = +((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MOVZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))) then bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else returnS () )))`; + + +(*val execute_MOVN : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))) then bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else returnS () )))`; + + +(*val execute_MFLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MFLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS + (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MFHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS + (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double= (bindS (seqS +(checkCP0Access () ) (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M) + (\ (w__0 : cheri_sequential_types$TLBIndexT) . + let (idx : 31 cheri_sequential_types$bits) = ((zero_extend1 + (( 31 : int): sail_values$ii) + w__0 : 31 words$word)) in + bindS + (read_regS TLBProbe_ref : ( 1 words$word) cheri_sequential_types$M) + (\ (w__1 : 1 cheri_sequential_types$bits) . + returnS + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word) + ((concat_vec w__1 idx : 32 words$word)) : 64 words$word)))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) + (\ (w__2 : cheri_sequential_types$TLBIndexT) . + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) w__2 : 64 words$word))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS TLBEntryLo0_ref) + (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) . + returnS ((get_TLBEntryLoReg w__3 : 64 words$word))) else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS TLBEntryLo1_ref) + (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) . + returnS ((get_TLBEntryLoReg w__4 : 64 words$word))) else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS TLBContext_ref) + (\ (w__5 : cheri_sequential_types$ContextReg) . + returnS ((get_ContextReg w__5 : 64 words$word))) else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + (read_regS CP0UserLocal_ref : ( 64 words$word) cheri_sequential_types$M) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) + /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS TLBPageMask_ref : ( 16 words$word) cheri_sequential_types$M) + (\ (w__7 : 16 cheri_sequential_types$bits) . + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) + ((concat_vec w__7 + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 28 words$word)) : 64 words$word))) else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS TLBWired_ref : ( 6 words$word) cheri_sequential_types$M) + (\ (w__8 : cheri_sequential_types$TLBIndexT) . + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) w__8 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS CP0HWREna_ref : ( 32 words$word) cheri_sequential_types$M) + (\ (w__9 : 32 cheri_sequential_types$bits) . + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) w__9 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (read_regS CP0BadVAddr_ref : ( 64 words$word) cheri_sequential_types$M) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M) + (\ (w__11 : 32 cheri_sequential_types$bits) . + returnS + ((zero_extend1 (( 64 : int): sail_values$ii) + w__11 : 64 words$word))) else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS TLBEntryHi_ref) + (\ (w__12 : cheri_sequential_types$TLBEntryHiReg) . + returnS + ((get_TLBEntryHiReg w__12 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS CP0Compare_ref : ( 32 words$word) cheri_sequential_types$M) + (\ (w__13 : 32 cheri_sequential_types$bits) . + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) w__13 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS CP0Status_ref) + (\ (w__14 : cheri_sequential_types$StatusReg) . + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + ((get_StatusReg w__14 : 32 words$word)) : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + bindS (read_regS CP0Cause_ref) + (\ (w__15 : cheri_sequential_types$CauseReg) . + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + ((get_CauseReg w__15 : 32 words$word)) : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (read_regS CP0EPC_ref : ( 64 words$word) cheri_sequential_types$M) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 15 words$word) + ((concat_vec + (vec_of_bits + [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B1;B0] : 2 words$word) + ((concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B1] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 15 words$word)) + : 16 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B1] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + TLBIndexMax + ((concat_vec + (vec_of_bits + [B0;B0;B0] : 3 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0] : 3 words$word) + (( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + ( + bool_to_bits + have_cp2 : 1 words$word)) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + : 1 words$word) + ( + vec_of_bits + [B0] + : 1 words$word) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 16 words$word)) + : 19 words$word)) + : 22 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B1;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0] : 3 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ((concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + : 8 words$word)) + : 12 words$word)) + : 16 words$word)) + : 20 words$word)) + : 24 words$word)) + : 28 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B1;B1] : 3 words$word))))))) then + returnS + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] : 64 words$word) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B1;B0;B1] : 3 words$word))))))) then + returnS + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] : 64 words$word) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + (read_regS CP0LLAddr_ref : ( 64 words$word) cheri_sequential_types$M) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + (vec_of_bits + [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + ( + vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + returnS + ((zero_extend1 + (( 64 : int): sail_values$ii) + (vec_of_bits + [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + ( + vec_of_bits + [B1;B0;B1;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + ( + vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + bindS + (read_regS + TLBXContext_ref) + (\ (w__18 : cheri_sequential_types$XContextReg) . + returnS + ((get_XContextReg + w__18 : 64 words$word))) + else + (read_regS + CP0ErrorEPC_ref : ( 64 words$word) cheri_sequential_types$M) + )) (\ (result : 64 cheri_sequential_types$bits) . + wGPR rt + (if double then result + else + (sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; + + +(*val execute_MADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MADDU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS + (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS + (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . + let result = +((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_MADD:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) + else + returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS + (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS + (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . + let result = +((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in seqS +(write_regS + HI_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) +(write_regS + LO_ref + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_Load : Cheri_sequential_types.WordType -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_Load:cheri_sequential_types$WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width sign linked base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + width + : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) . + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (if linked then seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (case width of + B => bindS + (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 : 8 words$word) . + returnS ((extendLoad w__1 sign : 64 words$word))) + | H => bindS + (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 : 16 words$word) . + returnS ((extendLoad w__2 sign : 64 words$word))) + | W0 => bindS + (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 : 32 words$word) . + returnS ((extendLoad w__3 sign : 64 words$word))) + | D => bindS + (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__4 : 64 words$word) . + returnS ((extendLoad w__4 sign : 64 words$word))) + ) + else + (case width of + B => bindS + (MEMr_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__6 : 8 words$word) . + returnS ((extendLoad w__6 sign : 64 words$word))) + | H => bindS + (MEMr_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__7 : 16 words$word) . + returnS ((extendLoad w__7 sign : 64 words$word))) + | W0 => bindS + (MEMr_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__8 : 32 words$word) . + returnS ((extendLoad w__8 sign : 64 words$word))) + | D => bindS + (MEMr_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__9 : 64 words$word) . + returnS ((extendLoad w__9 sign : 64 words$word))) + )) (\ (memResult : 64 cheri_sequential_types$bits) . + wGPR rt memResult))))))`; + + +(*val execute_LWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + W0 + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):sail_values$ii) + : ( 32 words$word) cheri_sequential_types$M) (\ mem_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__4 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in + let (result : 32 cheri_sequential_types$bits) = +(if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) + : 32 words$word) + else mem_val) in + wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result : 64 words$word)))))))))`; + + +(*val execute_LWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + W0 + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):sail_values$ii) + : ( 32 words$word) cheri_sequential_types$M) (\ mem_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__0 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in + let (result : 32 cheri_sequential_types$bits) = +(if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + : 32 words$word) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + : 32 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + : 32 words$word)) in + wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result : 64 words$word)))))))))`; + + +(*val execute_LUI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_LUI:(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt imm= + (wGPR rt + ((sign_extend1 (( 64 : int):sail_values$ii) + ((concat_vec imm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word) + : 32 words$word)) + : 64 words$word))))`; + + +(*val execute_LDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + D + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):sail_values$ii) + : ( 64 words$word) cheri_sequential_types$M) (\ mem_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__24 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) + : 64 words$word) + else mem_val))))))))`; + + +(*val execute_LDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS + (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + D + : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):sail_values$ii) + : ( 64 words$word) cheri_sequential_types$M) (\ mem_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . + let b__16 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) + : 64 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) + : 64 words$word)))))))))`; + + +(*val execute_JR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_JR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; + + +(*val execute_JALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_JALR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS (seqS +(execute_branch w__0) + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec_int w__1 (( 8 : int):sail_values$ii) : 64 words$word))))))`; + + +(*val execute_JAL : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_JAL:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset= (bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . bindS (seqS +(execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii) : 64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word))) + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 words$word) . + wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) ((add_vec_int w__1 (( 8 : int):sail_values$ii) : 64 words$word))))))`; + + +(*val execute_J : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_J:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset= (bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii) : 64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word)))))`; + + +(*val execute_ImplementationDefinedStopFetching : unit -> unit*) + +val _ = Define ` + ((execute_ImplementationDefinedStopFetching:unit -> unit) g__117= () )`; + + +(*val execute_HCF : unit -> unit*) + +val _ = Define ` + ((execute_HCF:unit -> unit) g__122= () )`; + + +(*val execute_ERET : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ERET:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__127= (bindS (seqS (seqS (seqS +(checkCP0Access () ) +(ERETHook () )) +(write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word))) +(read_regS CP0Status_ref)) (\ (w__0 : cheri_sequential_types$StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then bindS + (read_regS CP0ErrorEPC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . seqS +(write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) + else bindS + (read_regS CP0EPC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . seqS +(write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word))))))`; + + +(*val execute_DSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((sub_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let (temp65 : 65 cheri_sequential_types$bits) = +((sub_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):sail_values$ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))`; + + +(*val execute_DSRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) in bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) in bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRA32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : + 64 words$word) . + wGPR rd w__2)))))`; + + +(*val execute_DSLL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) + : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd w__1))))`; + + +(*val execute_DSLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; + + +(*val execute_DMULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DMULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let result = ((mult_vec w__0 w__1 : 128 words$word)) in seqS +(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word))) +(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))))`; + + +(*val execute_DMULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DMULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let result = ((mults_vec w__0 w__1 : 128 words$word)) in seqS +(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word))) +(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))))`; + + +(*val execute_DIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))))))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . + returnS (w__0, w__1))) + else + let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in + let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (hardware_mod si ti) in + returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in seqS +(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r : 64 words$word))) +(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q : 64 words$word))))))))`; + + +(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))))))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . + returnS (w__0, w__1))) + else + let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in + let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (si - ((ti * qi))) in + returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in seqS +(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r : 64 words$word))) +(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q : 64 words$word))))))))`; + + +(*val execute_DDIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DDIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rsVal = (lem$w2ui w__0) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let rtVal = (lem$w2ui w__1) in bindS + (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . + returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (hardware_mod rsVal rtVal) in + returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in seqS +(write_regS LO_ref q) (write_regS HI_ref r))))))`; + + +(*val execute_DDIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DDIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rsVal = (integer_word$w2i w__0) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let rtVal = (integer_word$w2i w__1) in bindS + (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . + returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (rsVal - ((qi * rtVal))) in + returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in seqS +(write_regS LO_ref q) (write_regS HI_ref r))))))`; + + +(*val execute_DADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_DADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let (sum65 : 65 cheri_sequential_types$bits) = +((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) imm : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))`; + + +(*val execute_DADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let (sum65 : 65 cheri_sequential_types$bits) = +((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))`; + + +(*val execute_ClearRegs : Cheri_sequential_types.ClearRegSet -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ClearRegs:cheri_sequential_types$ClearRegSet ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) regset m= (seqS (seqS + (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () + else returnS () ) + (if (((regset = CHi))) then + (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () + (\ i unit_var . + let r = +((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) : 5 words$word)) in bindS +(register_inaccessible r) (\ (w__0 : bool) . + if (((((bit_to_bool ((access_vec_dec m i)))) /\ w__0))) then + raise_c2_exception CapEx_AccessSystemRegsViolation r + else returnS () ))) + else returnS () )) + (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () + (\ i unit_var . + if ((bit_to_bool ((access_vec_dec m i)))) then + (case regset of + GPLo => + wGPR ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) + ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)) + | GPHi => + wGPR + ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) + : 5 words$word)) ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)) + | CLo => + writeCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) null_cap + | CHi => + writeCapReg + ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) + : 5 words$word)) null_cap + ) + else returnS () ))))`; + + +(*val execute_CWriteHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb sel= (seqS +(checkCP2usable () ) +(let l__24 = (lem$w2ui sel) in bindS + (if (((l__24 = (( 0 : int):sail_values$ii)))) then returnS (F, F) + else if (((l__24 = (( 1 : int):sail_values$ii)))) then returnS (F, F) + else if (((l__24 = (( 8 : int):sail_values$ii)))) then returnS (F, T) + else if (((l__24 = (( 22 : int):sail_values$ii)))) then returnS (T, F) + else if (((l__24 = (( 23 : int):sail_values$ii)))) then returnS (T, F) + else if (((l__24 = (( 29 : int):sail_values$ii)))) then returnS (T, T) + else if (((l__24 = (( 30 : int):sail_values$ii)))) then returnS (T, T) + else if (((l__24 = (( 31 : int):sail_values$ii)))) then returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS +(register_inaccessible cb) (\ (w__8 : bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(pcc_access_system_regs () ) (\ (w__9 : bool) . + if (((needAccessSys /\ ((~ w__9))))) then + raise_c2_exception CapEx_AccessSystemRegsViolation sel + else bindS +(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . + if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then + raise_c2_exception CapEx_AccessSystemRegsViolation sel + else bindS +(readCapReg cb) (\ capVal . + let l__16 = (lem$w2ui sel) in + if (((l__16 = (( 0 : int):sail_values$ii)))) then writeCapReg DDC capVal + else if (((l__16 = (( 1 : int):sail_values$ii)))) then + write_regS CTLSU_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((l__16 = (( 8 : int):sail_values$ii)))) then + write_regS CTLSP_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((l__16 = (( 22 : int):sail_values$ii)))) then writeCapReg KR1C capVal + else if (((l__16 = (( 23 : int):sail_values$ii)))) then writeCapReg KR2C capVal + else if (((l__16 = (( 29 : int):sail_values$ii)))) then writeCapReg KCC capVal + else if (((l__16 = (( 30 : int):sail_values$ii)))) then writeCapReg KDC capVal + else if (((l__16 = (( 31 : int):sail_values$ii)))) then writeCapReg EPCC capVal + else assert_expS F "should be unreachable code"))))))))`; + + +(*val execute_CUnseal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if (((ct_cursor <> ((lem$w2ui cs_val.CapStruct_otype))))) then + raise_c2_exception CapEx_TypeViolation ct + else if ((~ ct_val.CapStruct_permit_unseal)) then + raise_c2_exception CapEx_PermitUnsealViolation ct + else if ((ct_cursor < ((getCapBase ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ((getCapTop ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else + writeCapReg cd + (cs_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); CapStruct_global := + (((cs_val.CapStruct_global /\ ct_val.CapStruct_global)))|>))))))))`; + + +(*val execute_CToPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg ct)) (\ ct_val . bindS +(readCapReg cb) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let cbBase = (getCapBase cb_val) in + let cbTop = (getCapTop cb_val) in + let ctBase = (getCapBase ct_val) in + let ctTop = (getCapTop ct_val) in + wGPR rd + (if (((((~ cb_val.CapStruct_tag)) \/ (((((cbBase < ctBase)) \/ ((cbTop > ctTop)))))))) then + (zeros (( 64 : int):sail_values$ii) () : 64 words$word) + else + (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + ((((getCapCursor cb_val)) - ctBase)) + : 64 words$word))))))))`; + + +(*val execute_CTestSubset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(readCapReg ct) (\ ct_val . + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in + let ct_perms = ((getCapPerms ct_val : 31 words$word)) in + let cb_top = (getCapTop cb_val) in + let cb_base = (getCapBase cb_val) in + let cb_perms = ((getCapPerms cb_val : 31 words$word)) in bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + let (result : 1 cheri_sequential_types$bits) = +(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then + (vec_of_bits [B0] : 1 words$word) + else if ((ct_base < cb_base)) then (vec_of_bits [B0] : 1 words$word) + else if ((ct_top > cb_top)) then (vec_of_bits [B0] : 1 words$word) + else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then + (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) result : 64 words$word))))))))`; + + +(*val execute_CSub : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg ct)) (\ ct_val . bindS +(readCapReg cb) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + wGPR rd + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) + : 64 words$word))))))))`; + + +(*val execute_CStore : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_store)) then + raise_c2_exception CapEx_PermitStoreViolation cb + else + let size1 = (wordWidthBytes width) in + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + size1)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 + else bindS + (TLBTranslate vAddr64 StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . + if conditional then bindS + (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__2 : 1 cheri_sequential_types$bits) . bindS + (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):sail_values$ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii) + ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii) + ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + | W0 => + MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii) + ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rs_val + ) + else returnS F) (\ (success : bool) . + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) + | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rs_val + ))))))))`; + + +(*val execute_CSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CSetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt= (bindS (seqS +(checkCP2usable () ) +(pcc_access_system_regs () )) (\ (w__0 : bool) . + if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . seqS +(set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word))) +(set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))))))`; + + +(*val execute_CSetBoundsImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . + let immU = (lem$w2ui imm) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + immU) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else (case + setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself)) + cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself)) + newTop : 65 words$word)) of + (_, newCap) => + writeCapReg cd newCap + ))))))`; + + +(*val execute_CSetBoundsExact : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rt_val = (lem$w2ui w__0) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + rt_val) in bindS +(register_inaccessible cd) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else + let (exact, newCap) = +(setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int):sail_values$ii) : 65 itself)) newTop : 65 words$word))) in + if ((~ exact)) then raise_c2_exception CapEx_InexactBounds cb + else writeCapReg cd newCap))))))`; + + +(*val execute_CSetBounds : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + let rt_val = (lem$w2ui w__0) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + rt_val) in bindS +(register_inaccessible cd) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else (case + setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself)) + cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself)) + newTop : 65 words$word)) of + (_, newCap) => + writeCapReg cd newCap + )))))))`; + + +(*val execute_CSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if ((~ ct_val.CapStruct_permit_seal)) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + let (success, newCap) = +(sealCap cs_val + ((to_bits ((make_the_value (( 24 : int):sail_values$ii) : 24 itself)) ct_cursor : 24 words$word))) in + if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd newCap)))))))`; + + +(*val execute_CSC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg cb) (\ cb_val . bindS +(register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_store)) then + raise_c2_exception CapEx_PermitStoreViolation cb + else if ((~ cb_val.CapStruct_permit_store_cap)) then + raise_c2_exception CapEx_PermitStoreCapViolation cb + else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then + raise_c2_exception CapEx_PermitStoreLocalCapViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then + SignalExceptionBadAddr AdES vAddr64 + else bindS + (TLBTranslateC vAddr64 StoreData : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (pAddr, noStoreCap) = varstup in + if (((cs_val.CapStruct_tag /\ noStoreCap))) then + raise_c2_exception CapEx_TLBNoStoreCap cs + else if conditional then bindS + (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__3 : 1 cheri_sequential_types$bits) . bindS + (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):sail_values$ii))))) then + MEMw_tagged_conditional pAddr cs_val.CapStruct_tag + ((capStructToMemBits cs_val : 256 words$word)) + else returnS F) (\ success . + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val : 256 words$word))))))))))`; + + +(*val execute_CReturn : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CReturn:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__128= (seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`; + + +(*val execute_CReadHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CReadHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd sel= (seqS +(checkCP2usable () ) +(let l__8 = (lem$w2ui sel) in bindS + (if (((l__8 = (( 0 : int):sail_values$ii)))) then returnS (F, F) + else if (((l__8 = (( 1 : int):sail_values$ii)))) then returnS (F, F) + else if (((l__8 = (( 8 : int):sail_values$ii)))) then returnS (F, T) + else if (((l__8 = (( 22 : int):sail_values$ii)))) then returnS (T, F) + else if (((l__8 = (( 23 : int):sail_values$ii)))) then returnS (T, F) + else if (((l__8 = (( 29 : int):sail_values$ii)))) then returnS (T, T) + else if (((l__8 = (( 30 : int):sail_values$ii)))) then returnS (T, T) + else if (((l__8 = (( 31 : int):sail_values$ii)))) then returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS +(register_inaccessible cd) (\ (w__8 : bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(pcc_access_system_regs () ) (\ (w__9 : bool) . + if (((needAccessSys /\ ((~ w__9))))) then + raise_c2_exception CapEx_AccessSystemRegsViolation sel + else bindS +(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . + if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then + raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + let l__0 = (lem$w2ui sel) in bindS + (if (((l__0 = (( 0 : int):sail_values$ii)))) then readCapReg DDC + else if (((l__0 = (( 1 : int):sail_values$ii)))) then bindS + (read_regS CTLSU_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__12 : 257 words$word) . + returnS ((capRegToCapStruct w__12))) + else if (((l__0 = (( 8 : int):sail_values$ii)))) then bindS + (read_regS CTLSP_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__13 : 257 words$word) . + returnS ((capRegToCapStruct w__13))) + else if (((l__0 = (( 22 : int):sail_values$ii)))) then readCapReg KR1C + else if (((l__0 = (( 23 : int):sail_values$ii)))) then readCapReg KR2C + else if (((l__0 = (( 29 : int):sail_values$ii)))) then readCapReg KCC + else if (((l__0 = (( 30 : int):sail_values$ii)))) then readCapReg KDC + else if (((l__0 = (( 31 : int):sail_values$ii)))) then readCapReg EPCC + else seqS (assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal : + cheri_sequential_types$CapStruct) . + writeCapReg cd capVal))))))))`; + + +(*val execute_CPtrCmp : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CPtrCmpOp -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> cheri_sequential_types$CPtrCmpOp ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct op= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else bindS +(readCapReg cb) (\ cb_val . bindS +(readCapReg ct) (\ ct_val . + let equal = F in + let ltu = F in + let lts = F in + let ((equal : bool), (lts : bool), (ltu : bool)) = +(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then + let ((lts : bool), (ltu : bool)) = +(if ((~ cb_val.CapStruct_tag)) then + let (ltu : bool) = T in + let (lts : bool) = T in + (lts, ltu) + else (lts, ltu)) in + (equal, lts, ltu) + else + let cursor1 = (getCapCursor cb_val) in + let cursor2 = (getCapCursor ct_val) in + let (equal : bool) = (cursor1 = cursor2) in + let (ltu : bool) = (cursor1 < cursor2) in + let (lts : bool) = +((integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor1 : 64 words$word))) < (integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor2 : 64 words$word)))) in + (equal, lts, ltu)) in + let (cmp : bool) = +((case op of + CEQ => equal + | CNE => ~ equal + | CLT => lts + | CLE => (lts \/ equal) + | CLTU => ltu + | CLEU => (ltu \/ equal) + | CEXEQ => (cb_val = ct_val) + | CNEXEQ => (cb_val <> ct_val) + )) in + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits cmp : 1 words$word)) : 64 words$word))))))))`; + + +(*val execute_CMOVX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt ismovn= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + if ((bits_to_bool + ((xor_vec + ((bool_to_bits (((w__2 = ((zeros (( 64 : int):sail_values$ii) () : 64 words$word))))) : 1 words$word)) + ((bool_to_bits ismovn : 1 words$word)) + : 1 words$word)))) then bindS +(readCapReg cb) (\ (w__3 : cheri_sequential_types$CapStruct) . writeCapReg cd w__3) + else returnS () )))))`; + + +(*val execute_CLoad : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> bool -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6= + (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in + (case merge_var of + (rd, cb, rt, offset, signext, B, linked) => bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 1 : int):sail_values$ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 + else bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (if linked then bindS (seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__2 : 8 words$word) . + returnS ((extendLoad w__2 signext : 64 words$word))) + else bindS + (MEMr_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__3 : 8 words$word) . + returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, D, linked) => bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 8 : int):sail_values$ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 + else bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (if linked then bindS (seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__2 : 64 words$word) . + returnS ((extendLoad w__2 signext : 64 words$word))) + else bindS + (MEMr_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . + returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, H, linked) => bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 2 : int):sail_values$ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 + else bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (if linked then bindS (seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M)) (\ (w__2 : 16 words$word) . + returnS ((extendLoad w__2 signext : 64 words$word))) + else bindS + (MEMr_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 : 16 words$word) . + returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, W0, linked) => bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 4 : int):sail_values$ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64 + else bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS + (if linked then bindS (seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__2 : 32 words$word) . + returnS ((extendLoad w__2 signext : 64 words$word))) + else bindS + (MEMr_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 : 32 words$word) . + returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . + wGPR rd memResult))))) + )))`; + + +(*val execute_CLC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt offset linked= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + let vAddr = +(hardware_mod + ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset)))))) + ((pow2 (( 64 : int):sail_values$ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then + SignalExceptionBadAddr AdEL vAddr64 + else bindS + (TLBTranslateC vAddr64 LoadData : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (pAddr, suppressTag) = varstup in + let cd = (lem$w2ui cd) in + if linked then bindS (seqS (seqS +(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) +(write_regS CP0LLAddr_ref pAddr)) + (MEMr_tagged_reserve pAddr : ((bool # 256 words$word)) cheri_sequential_types$M)) (\ varstup . let (tag, mem) = varstup in + write_regS + ((access_list_dec CapRegs cd : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) + ((memBitsToCapBits + (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) + mem + : 257 words$word))) + else bindS + (MEMr_tagged pAddr : ((bool # 256 words$word)) cheri_sequential_types$M) (\ varstup . let (tag, mem) = varstup in + write_regS + ((access_list_dec CapRegs cd : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) + ((memBitsToCapBits + (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) + mem + : 257 words$word))))))))))`; + + +(*val execute_CJALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb link= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . + let cb_ptr = (getCapCursor cb_val) in + let cb_top = (getCapTop cb_val) in + let cb_base = (getCapBase cb_val) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if (((link /\ w__0))) then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((((cb_ptr + (( 4 : int):sail_values$ii))) > cb_top)) then + raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod cb_ptr (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then SignalException AdEL + else seqS + (if link then bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 : 257 words$word) . + let pcc = (capRegToCapStruct w__2) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . + let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__3 (( 8 : int):sail_values$ii) : 64 words$word))) in + if success then writeCapReg cd linkCap + else assert_expS F "")) + else returnS () ) +(execute_branch_pcc cb_val))))))`; + + +(*val execute_CIncOffsetImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . + let (imm64 : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (incCapOffset cb_val imm64) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) imm64 + : 64 words$word)))))))))`; + + +(*val execute_CIncOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))))))))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (incCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CGetType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):sail_values$ii) capVal.CapStruct_otype : 64 words$word) + else (replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word))))))`; + + +(*val execute_CGetTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_tag : 1 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetSealed : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetSealed:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_sealed : 1 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms capVal : 31 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetPCCSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd rs= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . + let (success, newPCC) = (setCapOffset pcc rs_val) in + if success then writeCapReg cd newPCC + else writeCapReg cd ((int_to_cap rs_val)))))))`; + + +(*val execute_CGetPCC : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetPCC:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS + (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + let (success, pcc2) = (setCapOffset pcc w__2) in seqS +(assert_expS success "") (writeCapReg cd pcc2))))))`; + + +(*val execute_CGetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapOffset capVal)) : 64 words$word))))))`; + + +(*val execute_CGetLen : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetLen:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + let len65 = (getCapLength capVal) in + wGPR rd + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) + (if ((len65 > MAX_U64)) then MAX_U64 + else len65) + : 64 words$word))))))`; + + +(*val execute_CGetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS (seqS +(checkCP2usable () ) +(pcc_access_system_regs () )) (\ (w__0 : bool) . + if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else bindS +(read_regS CapCause_ref) (\ (w__1 : cheri_sequential_types$CapCauseReg) . + wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((get_CapCauseReg w__1 : 16 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetBase : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetBase:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase capVal)) : 64 words$word))))))`; + + +(*val execute_CGetAddr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CGetAddr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapCursor capVal)) : 64 words$word))))))`; + + +(*val execute_CFromPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then writeCapReg cd null_cap + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CCopyType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(readCapReg ct) (\ ct_val . + let cb_base = (getCapBase cb_val) in + let cb_top = (getCapTop cb_val) in + let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ct_val.CapStruct_sealed then + if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_otype >= cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else + let (success, cap) = +(setCapOffset cb_val + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((ct_otype - cb_base)) + : 64 words$word))) in seqS +(assert_expS success "") (writeCapReg cd cap) + else + writeCapReg cd + ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word)))))))))))`; + + +(*val execute_CClearTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CClearTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS (readCapReg cb) (\ cb_val . writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`; + + +(*val execute_CCheckType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CCheckType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg cb) (\ cb_val . bindS +(register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else returnS () ))))))`; + + +(*val execute_CCheckPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . + let (cs_perms : 64 cheri_sequential_types$bits) = +((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms cs_val : 31 words$word)) : 64 words$word)) in bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_perms . bindS +(register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if (((((and_vec cs_perms rt_perms : 64 words$word)) <> rt_perms))) then + raise_c2_exception CapEx_UserDefViolation cs + else returnS () )))))`; + + +(*val execute_CCall : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb b__151= + (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) then bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg cb) (\ cb_val . + let cs_cursor = (getCapCursor cs_val) in bindS +(register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((~ cs_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if cb_val.CapStruct_permit_execute then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor >= ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else raise_c2_exception CapEx_CallTrap cs)))) + else bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg cb) (\ cb_val . + let cs_cursor = (getCapCursor cs_val) in bindS +(register_inaccessible cs) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible cb) (\ (w__3 : bool) . + if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((~ cs_val.CapStruct_permit_ccall)) then + raise_c2_exception CapEx_PermitCCallViolation cs + else if ((~ cb_val.CapStruct_permit_ccall)) then + raise_c2_exception CapEx_PermitCCallViolation cb + else if ((~ cs_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if cb_val.CapStruct_permit_execute then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor >= ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else seqS (seqS +(execute_branch_pcc + (cs_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word))|>)) +(write_regS inCCallDelay_ref (vec_of_bits [B1] : 1 words$word))) +(write_regS + C26_ref + ((capStructToCapReg + (cb_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word))|>) + : 257 words$word)))))))))`; + + +(*val execute_CCSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cs)) (\ cs_val . bindS +(readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else bindS +(register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if (((((~ ct_val.CapStruct_tag)) \/ (((((getCapCursor ct_val)) = ((lem$w2ui ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word)))))))))) + then + writeCapReg cd cs_val + else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if ((~ ct_val.CapStruct_permit_seal)) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + let (success, newCap) = +(sealCap cs_val + ((to_bits ((make_the_value (( 24 : int):sail_values$ii) : 24 itself)) ct_cursor : 24 words$word))) in + if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd newCap)))))))`; + + +(*val execute_CBuildCap : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS +(readCapReg ct) (\ ct_val . + let cb_base = (getCapBase cb_val) in + let ct_base = (getCapBase ct_val) in + let cb_top = (getCapTop cb_val) in + let ct_top = (getCapTop ct_val) in + let cb_perms = ((getCapPerms cb_val : 31 words$word)) in + let ct_perms = ((getCapPerms ct_val : 31 words$word)) in + let ct_offset = (getCapOffset ct_val) in bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then + raise_c2_exception CapEx_UserDefViolation cb + else + let (exact, cd1) = +(setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ct_base : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int):sail_values$ii) : 65 itself)) ct_top : 65 words$word))) in + let (representable, cd2) = +(setCapOffset cd1 + ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ct_offset : 64 words$word))) in + let cd3 = (setCapPerms cd2 ct_perms) in seqS (seqS +(assert_expS exact "") (assert_expS representable "")) (writeCapReg cd cd3))))))))`; + + +(*val execute_CBZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notzero= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__1 = null_cap))) : 1 words$word)) + ((bool_to_bits notzero : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 cheri_sequential_types$bits) = +((add_vec_int + ((sign_extend1 (( 64 : int):sail_values$ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):sail_values$ii) + : 64 words$word)) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else returnS () ))))`; + + +(*val execute_CBX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notset= (bindS (seqS +(checkCP2usable () ) +(register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else bindS +(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits w__1.CapStruct_tag : 1 words$word)) + ((bool_to_bits notset : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 cheri_sequential_types$bits) = +((add_vec_int + ((sign_extend1 (( 64 : int):sail_values$ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):sail_values$ii) + : 64 words$word)) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else returnS () ))))`; + + +(*val execute_CAndPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS +(checkCP2usable () ) +(readCapReg cb)) (\ cb_val . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS +(register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else bindS +(register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else + let perms = ((getCapPerms cb_val : 31 words$word)) in + let newCap = +(setCapPerms cb_val + ((and_vec perms ((subrange_vec_dec rt_val (( 30 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 31 words$word)) : 31 words$word))) in + writeCapReg cd newCap))))))`; + + +(*val execute_CACHE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; + + +(*val execute_C2Dump : Machine_word.mword Machine_word.ty5 -> unit*) + +val _ = Define ` + ((execute_C2Dump:(5)words$word -> unit) rt= () )`; + + +(*val execute_BREAK : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_BREAK:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__119= (SignalException Bp))`; + + +(*val execute_BEQ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd imm ne likely= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rd : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) : 1 words$word)) + ((bool_to_bits ne : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 cheri_sequential_types$bits) = +((add_vec_int + ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):sail_values$ii) + : 64 words$word)) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else if likely then bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . + write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):sail_values$ii) : 64 words$word))) + else returnS () ))))`; + + +(*val execute_BCMPZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> bool -> bool -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_BCMPZ:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp link likely= (bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . + let linkVal = ((add_vec_int w__0 (( 8 : int):sail_values$ii) : 64 words$word)) in bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ regVal . + let condition = +(compare cmp regVal ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in seqS + (if condition then + let (offset : 64 cheri_sequential_types$bits) = +((add_vec_int + ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):sail_values$ii) + : 64 words$word)) in bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + execute_branch ((add_vec w__1 offset : 64 words$word))) + else if likely then bindS + (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . + write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):sail_values$ii) : 64 words$word))) + else returnS () ) +(if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) linkVal + else returnS () )))))`; + + +(*val execute_ANDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . + wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_AND : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . + wGPR rd ((and_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_ADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 : int):sail_values$ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_ADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . + if ((NotWordVal opA)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + wGPR rt + ((sign_extend1 (( 64 : int):sail_values$ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + ((sign_extend1 (( 32 : int):sail_values$ii) imm : 32 words$word)) + : 32 words$word)) + : 64 words$word)))))`; + + +(*val execute_ADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . + if ((NotWordVal opA)) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + let (sum33 : 33 cheri_sequential_types$bits) = +((add_vec + ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):sail_values$ii) imm : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then + SignalException Ov + else + wGPR rt + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; + + +(*val execute_ADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS + (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (opA : 64 cheri_sequential_types$bits) . bindS + (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (opB : 64 cheri_sequential_types$bits) . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (sum33 : 33 cheri_sequential_types$bits) = +((add_vec + ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))`; + + +val _ = Define ` + ((execute:cheri_sequential_types$ast ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) merge_var= + ((case merge_var of + DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm + | DADDU (rs,rt,rd) => execute_DADDU rs rt rd + | DADDI (rs,rt,imm) => execute_DADDI rs rt imm + | DADD (rs,rt,rd) => execute_DADD rs rt rd + | ADD (rs,rt,rd) => execute_ADD rs rt rd + | ADDI (rs,rt,imm) => execute_ADDI rs rt imm + | ADDU (rs,rt,rd) => execute_ADDU rs rt rd + | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm + | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd + | DSUB (rs,rt,rd) => execute_DSUB rs rt rd + | SUB0 (rs,rt,rd) => execute_SUB rs rt rd + | SUBU (rs,rt,rd) => execute_SUBU rs rt rd + | AND (rs,rt,rd) => execute_AND rs rt rd + | ANDI (rs,rt,imm) => execute_ANDI rs rt imm + | OR (rs,rt,rd) => execute_OR rs rt rd + | ORI (rs,rt,imm) => execute_ORI rs rt imm + | NOR (rs,rt,rd) => execute_NOR rs rt rd + | XOR (rs,rt,rd) => execute_XOR rs rt rd + | XORI (rs,rt,imm) => execute_XORI rs rt imm + | LUI (rt,imm) => execute_LUI rt imm + | DSLL (rt,rd,sa) => execute_DSLL rt rd sa + | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa + | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd + | DSRA (rt,rd,sa) => execute_DSRA rt rd sa + | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa + | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd + | DSRL (rt,rd,sa) => execute_DSRL rt rd sa + | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa + | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd + | SLL (rt,rd,sa) => execute_SLL rt rd sa + | SLLV (rs,rt,rd) => execute_SLLV rs rt rd + | SRA (rt,rd,sa) => execute_SRA rt rd sa + | SRAV (rs,rt,rd) => execute_SRAV rs rt rd + | SRL (rt,rd,sa) => execute_SRL rt rd sa + | SRLV (rs,rt,rd) => execute_SRLV rs rt rd + | SLT (rs,rt,rd) => execute_SLT rs rt rd + | SLTI (rs,rt,imm) => execute_SLTI rs rt imm + | SLTU (rs,rt,rd) => execute_SLTU rs rt rd + | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm + | MOVN (rs,rt,rd) => execute_MOVN rs rt rd + | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd + | MFHI (rd) => execute_MFHI rd + | MFLO (rd) => execute_MFLO rd + | MTHI (rs) => execute_MTHI rs + | MTLO (rs) => execute_MTLO rs + | MUL (rs,rt,rd) => execute_MUL rs rt rd + | MULT (rs,rt) => execute_MULT rs rt + | MULTU (rs,rt) => execute_MULTU rs rt + | DMULT (rs,rt) => execute_DMULT rs rt + | DMULTU (rs,rt) => execute_DMULTU rs rt + | MADD (rs,rt) => execute_MADD rs rt + | MADDU (rs,rt) => execute_MADDU rs rt + | MSUB (rs,rt) => execute_MSUB rs rt + | MSUBU (rs,rt) => execute_MSUBU rs rt + | DIV0 (rs,rt) => execute_DIV rs rt + | DIVU (rs,rt) => execute_DIVU rs rt + | DDIV (rs,rt) => execute_DDIV rs rt + | DDIVU (rs,rt) => execute_DDIVU rs rt + | J (offset) => execute_J offset + | JAL (offset) => execute_JAL offset + | JR (rs) => execute_JR rs + | JALR (rs,rd) => execute_JALR rs rd + | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely + | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely + | SYSCALL_THREAD_START (g__116) => returnS ((execute_SYSCALL_THREAD_START g__116)) + | ImplementationDefinedStopFetching (g__117) => + returnS ((execute_ImplementationDefinedStopFetching g__117)) + | SYSCALL (g__118) => execute_SYSCALL g__118 + | BREAK (g__119) => execute_BREAK g__119 + | WAIT (g__120) => execute_WAIT g__120 + | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp + | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp + | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset + | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset + | LWL (base,rt,offset) => execute_LWL base rt offset + | LWR (base,rt,offset) => execute_LWR base rt offset + | SWL (base,rt,offset) => execute_SWL base rt offset + | SWR (base,rt,offset) => execute_SWR base rt offset + | LDL (base,rt,offset) => execute_LDL base rt offset + | LDR (base,rt,offset) => execute_LDR base rt offset + | SDL (base,rt,offset) => execute_SDL base rt offset + | SDR (base,rt,offset) => execute_SDR base rt offset + | CACHE (base,op,imm) => execute_CACHE base op imm + | PREF (base,op,imm) => returnS ((execute_PREF base op imm)) + | SYNC (g__121) => execute_SYNC g__121 + | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double + | HCF (g__122) => returnS ((execute_HCF g__122)) + | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double + | TLBWI (g__123) => execute_TLBWI g__123 + | TLBWR (g__124) => execute_TLBWR g__124 + | TLBR (g__125) => execute_TLBR g__125 + | TLBP (g__126) => execute_TLBP g__126 + | RDHWR (rt,rd) => execute_RDHWR rt rd + | ERET (g__127) => execute_ERET g__127 + | CGetPerm (rd,cb) => execute_CGetPerm rd cb + | CGetType (rd,cb) => execute_CGetType rd cb + | CGetBase (rd,cb) => execute_CGetBase rd cb + | CGetOffset (rd,cb) => execute_CGetOffset rd cb + | CGetLen (rd,cb) => execute_CGetLen rd cb + | CGetTag (rd,cb) => execute_CGetTag rd cb + | CGetSealed (rd,cb) => execute_CGetSealed rd cb + | CGetAddr (rd,cb) => execute_CGetAddr rd cb + | CGetPCC (cd) => execute_CGetPCC cd + | CGetPCCSetOffset (cd,rs) => execute_CGetPCCSetOffset cd rs + | CGetCause (rd) => execute_CGetCause rd + | CSetCause (rt) => execute_CSetCause rt + | CReadHwr (cd,sel) => execute_CReadHwr cd sel + | CWriteHwr (cb,sel) => execute_CWriteHwr cb sel + | CAndPerm (cd,cb,rt) => execute_CAndPerm cd cb rt + | CToPtr (rd,cb,ct) => execute_CToPtr rd cb ct + | CSub (rd,cb,ct) => execute_CSub rd cb ct + | CPtrCmp (rd,cb,ct,op) => execute_CPtrCmp rd cb ct op + | CIncOffset (cd,cb,rt) => execute_CIncOffset cd cb rt + | CIncOffsetImmediate (cd,cb,imm) => execute_CIncOffsetImmediate cd cb imm + | CSetOffset (cd,cb,rt) => execute_CSetOffset cd cb rt + | CSetBounds (cd,cb,rt) => execute_CSetBounds cd cb rt + | CSetBoundsImmediate (cd,cb,imm) => execute_CSetBoundsImmediate cd cb imm + | CSetBoundsExact (cd,cb,rt) => execute_CSetBoundsExact cd cb rt + | CClearTag (cd,cb) => execute_CClearTag cd cb + | CMOVX (cd,cb,rt,ismovn) => execute_CMOVX cd cb rt ismovn + | ClearRegs (regset,m) => execute_ClearRegs regset m + | CFromPtr (cd,cb,rt) => execute_CFromPtr cd cb rt + | CBuildCap (cd,cb,ct) => execute_CBuildCap cd cb ct + | CCopyType (cd,cb,ct) => execute_CCopyType cd cb ct + | CCheckPerm (cs,rt) => execute_CCheckPerm cs rt + | CCheckType (cs,cb) => execute_CCheckType cs cb + | CTestSubset (rd,cb,ct) => execute_CTestSubset rd cb ct + | CSeal (cd,cs,ct) => execute_CSeal cd cs ct + | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct + | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct + | CCall (cs,cb,b__151) => execute_CCall cs cb b__151 + | CReturn (g__128) => execute_CReturn g__128 + | CBX (cb,imm,notset) => execute_CBX cb imm notset + | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero + | CJALR (cd,cb,link) => execute_CJALR cd cb link + | CLoad (rd,cb,rt,offset,signext,arg5,linked) => + execute_CLoad rd cb rt offset signext arg5 linked + | CStore (rs,cb,rt,rd,offset,width,conditional) => + execute_CStore rs cb rt rd offset width conditional + | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional + | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked + | C2Dump (rt) => returnS ((execute_C2Dump rt)) + | RI (g__129) => execute_RI g__129 + )))`; + + +(*val supported_instructions : Cheri_sequential_types.ast -> Maybe.maybe Cheri_sequential_types.ast*) + +val _ = Define ` + ((supported_instructions:cheri_sequential_types$ast ->(cheri_sequential_types$ast)option) instr= (SOME instr))`; + + +(*val initialize_registers : unit -> Cheri_sequential_types.M unit*) + +val _ = Define ` + ((initialize_registers:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS PC_ref w__0) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS nextPC_ref w__1) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__2 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS TLBProbe_ref w__2) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$TLBIndexT) . bindS (seqS +(write_regS TLBIndex_ref w__3) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__4 : cheri_sequential_types$TLBIndexT) . bindS (seqS +(write_regS TLBRandom_ref w__4) +(undefined_TLBEntryLoReg () )) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(write_regS TLBEntryLo0_ref w__5) +(undefined_TLBEntryLoReg () )) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS +(write_regS TLBEntryLo1_ref w__6) +(undefined_ContextReg () )) (\ (w__7 : cheri_sequential_types$ContextReg) . bindS (seqS +(write_regS TLBContext_ref w__7) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M)) (\ (w__8 : 16 cheri_sequential_types$bits) . bindS (seqS +(write_regS TLBPageMask_ref w__8) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__9 : cheri_sequential_types$TLBIndexT) . bindS (seqS +(write_regS TLBWired_ref w__9) +(undefined_TLBEntryHiReg () )) (\ (w__10 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS +(write_regS TLBEntryHi_ref w__10) +(undefined_XContextReg () )) (\ (w__11 : cheri_sequential_types$XContextReg) . bindS (seqS +(write_regS TLBXContext_ref w__11) +(undefined_TLBEntry () )) (\ (w__12 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry00_ref w__12) +(undefined_TLBEntry () )) (\ (w__13 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry01_ref w__13) +(undefined_TLBEntry () )) (\ (w__14 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry02_ref w__14) +(undefined_TLBEntry () )) (\ (w__15 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry03_ref w__15) +(undefined_TLBEntry () )) (\ (w__16 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry04_ref w__16) +(undefined_TLBEntry () )) (\ (w__17 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry05_ref w__17) +(undefined_TLBEntry () )) (\ (w__18 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry06_ref w__18) +(undefined_TLBEntry () )) (\ (w__19 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry07_ref w__19) +(undefined_TLBEntry () )) (\ (w__20 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry08_ref w__20) +(undefined_TLBEntry () )) (\ (w__21 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry09_ref w__21) +(undefined_TLBEntry () )) (\ (w__22 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry10_ref w__22) +(undefined_TLBEntry () )) (\ (w__23 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry11_ref w__23) +(undefined_TLBEntry () )) (\ (w__24 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry12_ref w__24) +(undefined_TLBEntry () )) (\ (w__25 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry13_ref w__25) +(undefined_TLBEntry () )) (\ (w__26 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry14_ref w__26) +(undefined_TLBEntry () )) (\ (w__27 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry15_ref w__27) +(undefined_TLBEntry () )) (\ (w__28 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry16_ref w__28) +(undefined_TLBEntry () )) (\ (w__29 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry17_ref w__29) +(undefined_TLBEntry () )) (\ (w__30 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry18_ref w__30) +(undefined_TLBEntry () )) (\ (w__31 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry19_ref w__31) +(undefined_TLBEntry () )) (\ (w__32 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry20_ref w__32) +(undefined_TLBEntry () )) (\ (w__33 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry21_ref w__33) +(undefined_TLBEntry () )) (\ (w__34 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry22_ref w__34) +(undefined_TLBEntry () )) (\ (w__35 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry23_ref w__35) +(undefined_TLBEntry () )) (\ (w__36 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry24_ref w__36) +(undefined_TLBEntry () )) (\ (w__37 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry25_ref w__37) +(undefined_TLBEntry () )) (\ (w__38 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry26_ref w__38) +(undefined_TLBEntry () )) (\ (w__39 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry27_ref w__39) +(undefined_TLBEntry () )) (\ (w__40 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry28_ref w__40) +(undefined_TLBEntry () )) (\ (w__41 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry29_ref w__41) +(undefined_TLBEntry () )) (\ (w__42 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry30_ref w__42) +(undefined_TLBEntry () )) (\ (w__43 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry31_ref w__43) +(undefined_TLBEntry () )) (\ (w__44 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry32_ref w__44) +(undefined_TLBEntry () )) (\ (w__45 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry33_ref w__45) +(undefined_TLBEntry () )) (\ (w__46 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry34_ref w__46) +(undefined_TLBEntry () )) (\ (w__47 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry35_ref w__47) +(undefined_TLBEntry () )) (\ (w__48 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry36_ref w__48) +(undefined_TLBEntry () )) (\ (w__49 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry37_ref w__49) +(undefined_TLBEntry () )) (\ (w__50 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry38_ref w__50) +(undefined_TLBEntry () )) (\ (w__51 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry39_ref w__51) +(undefined_TLBEntry () )) (\ (w__52 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry40_ref w__52) +(undefined_TLBEntry () )) (\ (w__53 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry41_ref w__53) +(undefined_TLBEntry () )) (\ (w__54 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry42_ref w__54) +(undefined_TLBEntry () )) (\ (w__55 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry43_ref w__55) +(undefined_TLBEntry () )) (\ (w__56 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry44_ref w__56) +(undefined_TLBEntry () )) (\ (w__57 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry45_ref w__57) +(undefined_TLBEntry () )) (\ (w__58 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry46_ref w__58) +(undefined_TLBEntry () )) (\ (w__59 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry47_ref w__59) +(undefined_TLBEntry () )) (\ (w__60 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry48_ref w__60) +(undefined_TLBEntry () )) (\ (w__61 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry49_ref w__61) +(undefined_TLBEntry () )) (\ (w__62 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry50_ref w__62) +(undefined_TLBEntry () )) (\ (w__63 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry51_ref w__63) +(undefined_TLBEntry () )) (\ (w__64 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry52_ref w__64) +(undefined_TLBEntry () )) (\ (w__65 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry53_ref w__65) +(undefined_TLBEntry () )) (\ (w__66 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry54_ref w__66) +(undefined_TLBEntry () )) (\ (w__67 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry55_ref w__67) +(undefined_TLBEntry () )) (\ (w__68 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry56_ref w__68) +(undefined_TLBEntry () )) (\ (w__69 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry57_ref w__69) +(undefined_TLBEntry () )) (\ (w__70 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry58_ref w__70) +(undefined_TLBEntry () )) (\ (w__71 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry59_ref w__71) +(undefined_TLBEntry () )) (\ (w__72 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry60_ref w__72) +(undefined_TLBEntry () )) (\ (w__73 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry61_ref w__73) +(undefined_TLBEntry () )) (\ (w__74 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry62_ref w__74) +(undefined_TLBEntry () )) (\ (w__75 : cheri_sequential_types$TLBEntry) . bindS (seqS +(write_regS TLBEntry63_ref w__75) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__76 : 32 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0Compare_ref w__76) +(undefined_CauseReg () )) (\ (w__77 : cheri_sequential_types$CauseReg) . bindS (seqS +(write_regS CP0Cause_ref w__77) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__78 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0EPC_ref w__78) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__79 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0ErrorEPC_ref w__79) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__80 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0LLBit_ref w__80) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__81 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0LLAddr_ref w__81) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__82 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0BadVAddr_ref w__82) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__83 : 32 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0Count_ref w__83) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__84 : 32 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0HWREna_ref w__84) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__85 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS CP0UserLocal_ref w__85) +(undefined_StatusReg () )) (\ (w__86 : cheri_sequential_types$StatusReg) . bindS (seqS +(write_regS CP0Status_ref w__86) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__87 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS branchPending_ref w__87) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__88 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS inBranchDelay_ref w__88) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__89 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS delayedPC_ref w__89) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__90 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS HI_ref w__90) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__91 : 64 cheri_sequential_types$bits) . bindS (seqS +(write_regS LO_ref w__91) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__92 : 64 words$word) . bindS + (undefined_vector (( 32 : int):sail_values$ii) w__92 : ( ( 64 words$word)list) cheri_sequential_types$M) (\ (w__93 : ( 64 cheri_sequential_types$bits) list) . bindS (seqS +(write_regS GPR_ref w__93) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__94 : 8 cheri_sequential_types$bits) . bindS (seqS +(write_regS UART_WDATA_ref w__94) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__95 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS UART_WRITTEN_ref w__95) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__96 : 8 cheri_sequential_types$bits) . bindS (seqS +(write_regS UART_RDATA_ref w__96) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__97 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS UART_RVALID_ref w__97) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__98 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS PCC_ref w__98) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__99 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS nextPCC_ref w__99) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__100 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS delayedPCC_ref w__100) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__101 : 1 cheri_sequential_types$bits) . bindS (seqS +(write_regS inCCallDelay_ref w__101) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__102 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C00_ref w__102) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__103 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C01_ref w__103) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__104 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C02_ref w__104) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__105 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C03_ref w__105) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__106 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C04_ref w__106) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__107 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C05_ref w__107) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__108 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C06_ref w__108) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__109 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C07_ref w__109) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__110 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C08_ref w__110) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__111 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C09_ref w__111) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__112 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C10_ref w__112) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__113 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C11_ref w__113) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__114 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C12_ref w__114) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__115 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C13_ref w__115) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__116 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C14_ref w__116) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__117 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C15_ref w__117) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__118 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C16_ref w__118) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__119 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C17_ref w__119) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__120 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C18_ref w__120) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__121 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C19_ref w__121) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__122 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C20_ref w__122) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__123 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C21_ref w__123) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__124 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C22_ref w__124) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__125 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C23_ref w__125) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__126 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C24_ref w__126) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__127 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C25_ref w__127) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__128 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C26_ref w__128) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__129 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C27_ref w__129) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__130 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C28_ref w__130) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__131 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C29_ref w__131) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__132 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C30_ref w__132) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__133 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS C31_ref w__133) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__134 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS CTLSU_ref w__134) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__135 : cheri_sequential_types$CapReg) . bindS (seqS +(write_regS CTLSP_ref w__135) +(undefined_CapCauseReg () )) (\ (w__136 : cheri_sequential_types$CapCauseReg) . write_regS CapCause_ref w__136)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml b/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml new file mode 100644 index 00000000..459c100e --- /dev/null +++ b/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml @@ -0,0 +1,2285 @@ +(*Generated by Lem from cheri_sequential_types.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "cheri_sequential_types" + +(*Generated by Sail from cheri_sequential.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import State_monad*) +(*open import State*) +val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); + + + +val _ = Hol_datatype ` + exception = + ISAException of (unit) + | Error_not_implemented of (string) + | Error_misaligned_access of (unit) + | Error_EBREAK of (unit) + | Error_internal_error of (unit)`; + + + + +val _ = Hol_datatype ` + CauseReg = Mk_CauseReg of ( 32 words$word)`; + + + + +val _ = Hol_datatype ` + CapCauseReg = Mk_CapCauseReg of ( 16 words$word)`; + + + + +val _ = Hol_datatype ` + TLBEntryLoReg = Mk_TLBEntryLoReg of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + TLBEntryHiReg = Mk_TLBEntryHiReg of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + ContextReg = Mk_ContextReg of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + XContextReg = Mk_XContextReg of ( 64 words$word)`; + + + + +val _ = type_abbrev( "TLBIndexT" , ``: 6 bits``); + +val _ = Hol_datatype ` + TLBEntry = Mk_TLBEntry of ( 117 words$word)`; + + + + +val _ = Hol_datatype ` + StatusReg = Mk_StatusReg of ( 32 words$word)`; + + + + +val _ = Hol_datatype ` + Exception = + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck`; + + + + +val _ = type_abbrev( "CapReg" , ``: 257 bits``); + +val _ = Hol_datatype ` + CapStruct = + <| CapStruct_tag : bool; + CapStruct_padding : 8 bits; + CapStruct_otype : 24 bits; + CapStruct_uperms : 16 bits; + CapStruct_perm_reserved11_14 : 4 bits; + CapStruct_access_system_regs : bool; + CapStruct_permit_unseal : bool; + CapStruct_permit_ccall : bool; + CapStruct_permit_seal : bool; + CapStruct_permit_store_local_cap : bool; + CapStruct_permit_store_cap : bool; + CapStruct_permit_load_cap : bool; + CapStruct_permit_store : bool; + CapStruct_permit_load : bool; + CapStruct_permit_execute : bool; + CapStruct_global : bool; + CapStruct_sealed : bool; + CapStruct_address : 64 bits; + CapStruct_base : 64 bits; + CapStruct_length : 64 bits |>`; + + + +val _ = Hol_datatype ` + MemAccessType = Instruction | LoadData | StoreData`; + + + + +val _ = Hol_datatype ` + AccessLevel = User | Supervisor | Kernel`; + + + + +val _ = type_abbrev( "regno" , ``: 5 bits``); + +val _ = type_abbrev( "imm16" , ``: 16 bits``); + +val _ = type_abbrev( "regregreg" , ``: (regno # regno # regno)``); + +val _ = type_abbrev( "regregimm16" , ``: (regno # regno # imm16)``); + +val _ = Hol_datatype ` + decode_failure = + No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error`; + + + + +val _ = Hol_datatype ` + Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU`; + + + + +val _ = Hol_datatype ` + WordType = B | H | W0 | D`; + + + + +val _ = type_abbrev( "CapLen" , ``: int``); + +val _ = type_abbrev( "uint64" , ``: int``); + +val _ = Hol_datatype ` + CPtrCmpOp = CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ`; + + + + +val _ = Hol_datatype ` + ClearRegSet = GPLo | GPHi | CLo | CHi`; + + + + +val _ = Hol_datatype ` + ast = + DADDIU of ((regno # regno # imm16)) + | DADDU of ((regno # regno # regno)) + | DADDI of ((regno # regno # 16 bits)) + | DADD of ((regno # regno # regno)) + | ADD of ((regno # regno # regno)) + | ADDI of ((regno # regno # 16 bits)) + | ADDU of ((regno # regno # regno)) + | ADDIU of ((regno # regno # 16 bits)) + | DSUBU of ((regno # regno # regno)) + | DSUB of ((regno # regno # regno)) + | SUB0 of ((regno # regno # regno)) + | SUBU of ((regno # regno # regno)) + | AND of ((regno # regno # regno)) + | ANDI of ((regno # regno # 16 bits)) + | OR of ((regno # regno # regno)) + | ORI of ((regno # regno # 16 bits)) + | NOR of ((regno # regno # regno)) + | XOR of ((regno # regno # regno)) + | XORI of ((regno # regno # 16 bits)) + | LUI of ((regno # imm16)) + | DSLL of ((regno # regno # regno)) + | DSLL32 of ((regno # regno # regno)) + | DSLLV of ((regno # regno # regno)) + | DSRA of ((regno # regno # regno)) + | DSRA32 of ((regno # regno # regno)) + | DSRAV of ((regno # regno # regno)) + | DSRL of ((regno # regno # regno)) + | DSRL32 of ((regno # regno # regno)) + | DSRLV of ((regno # regno # regno)) + | SLL of ((regno # regno # regno)) + | SLLV of ((regno # regno # regno)) + | SRA of ((regno # regno # regno)) + | SRAV of ((regno # regno # regno)) + | SRL of ((regno # regno # regno)) + | SRLV of ((regno # regno # regno)) + | SLT of ((regno # regno # regno)) + | SLTI of ((regno # regno # 16 bits)) + | SLTU of ((regno # regno # regno)) + | SLTIU of ((regno # regno # 16 bits)) + | MOVN of ((regno # regno # regno)) + | MOVZ of ((regno # regno # regno)) + | MFHI of (regno) + | MFLO of (regno) + | MTHI of (regno) + | MTLO of (regno) + | MUL of ((regno # regno # regno)) + | MULT of ((regno # regno)) + | MULTU of ((regno # regno)) + | DMULT of ((regno # regno)) + | DMULTU of ((regno # regno)) + | MADD of ((regno # regno)) + | MADDU of ((regno # regno)) + | MSUB of ((regno # regno)) + | MSUBU of ((regno # regno)) + | DIV0 of ((regno # regno)) + | DIVU of ((regno # regno)) + | DDIV of ((regno # regno)) + | DDIVU of ((regno # regno)) + | J of ( 26 bits) + | JAL of ( 26 bits) + | JR of (regno) + | JALR of ((regno # regno)) + | BEQ of ((regno # regno # imm16 # bool # bool)) + | BCMPZ of ((regno # imm16 # Comparison # bool # bool)) + | SYSCALL_THREAD_START of (unit) + | ImplementationDefinedStopFetching of (unit) + | SYSCALL of (unit) + | BREAK of (unit) + | WAIT of (unit) + | TRAPREG of ((regno # regno # Comparison)) + | TRAPIMM of ((regno # imm16 # Comparison)) + | Load of ((WordType # bool # bool # regno # regno # imm16)) + | Store of ((WordType # bool # regno # regno # imm16)) + | LWL of ((regno # regno # 16 bits)) + | LWR of ((regno # regno # 16 bits)) + | SWL of ((regno # regno # 16 bits)) + | SWR of ((regno # regno # 16 bits)) + | LDL of ((regno # regno # 16 bits)) + | LDR of ((regno # regno # 16 bits)) + | SDL of ((regno # regno # 16 bits)) + | SDR of ((regno # regno # 16 bits)) + | CACHE of ((regno # regno # 16 bits)) + | PREF of ((regno # regno # 16 bits)) + | SYNC of (unit) + | MFC0 of ((regno # regno # 3 bits # bool)) + | HCF of (unit) + | MTC0 of ((regno # regno # 3 bits # bool)) + | TLBWI of (unit) + | TLBWR of (unit) + | TLBR of (unit) + | TLBP of (unit) + | RDHWR of ((regno # regno)) + | ERET of (unit) + | CGetPerm of ((regno # regno)) + | CGetType of ((regno # regno)) + | CGetBase of ((regno # regno)) + | CGetLen of ((regno # regno)) + | CGetTag of ((regno # regno)) + | CGetSealed of ((regno # regno)) + | CGetOffset of ((regno # regno)) + | CGetAddr of ((regno # regno)) + | CGetPCC of (regno) + | CGetPCCSetOffset of ((regno # regno)) + | CGetCause of (regno) + | CSetCause of (regno) + | CReadHwr of ((regno # regno)) + | CWriteHwr of ((regno # regno)) + | CAndPerm of ((regno # regno # regno)) + | CToPtr of ((regno # regno # regno)) + | CSub of ((regno # regno # regno)) + | CPtrCmp of ((regno # regno # regno # CPtrCmpOp)) + | CIncOffset of ((regno # regno # regno)) + | CIncOffsetImmediate of ((regno # regno # 11 bits)) + | CSetOffset of ((regno # regno # regno)) + | CSetBounds of ((regno # regno # regno)) + | CSetBoundsImmediate of ((regno # regno # 11 bits)) + | CSetBoundsExact of ((regno # regno # regno)) + | CClearTag of ((regno # regno)) + | CMOVX of ((regno # regno # regno # bool)) + | ClearRegs of ((ClearRegSet # 16 bits)) + | CFromPtr of ((regno # regno # regno)) + | CBuildCap of ((regno # regno # regno)) + | CCopyType of ((regno # regno # regno)) + | CCheckPerm of ((regno # regno)) + | CCheckType of ((regno # regno)) + | CTestSubset of ((regno # regno # regno)) + | CSeal of ((regno # regno # regno)) + | CCSeal of ((regno # regno # regno)) + | CUnseal of ((regno # regno # regno)) + | CCall of ((regno # regno # 11 bits)) + | CReturn of (unit) + | CBX of ((regno # 16 bits # bool)) + | CBZ of ((regno # 16 bits # bool)) + | CJALR of ((regno # regno # bool)) + | CLoad of ((regno # regno # regno # 8 bits # bool # WordType # bool)) + | CStore of ((regno # regno # regno # regno # 8 bits # WordType # bool)) + | CSC of ((regno # regno # regno # regno # 11 bits # bool)) + | CLC of ((regno # regno # regno # 11 bits # bool)) + | C2Dump of (regno) + | RI of (unit)`; + + + + +val _ = Hol_datatype ` + CapEx = + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation`; + + + + +val _ = Hol_datatype ` + register_value = + Regval_vector of ((sail_values$ii # bool # register_value list)) + | Regval_list of ( register_value list) + | Regval_option of ( register_value option) + | Regval_CapCauseReg of (CapCauseReg) + | Regval_CauseReg of (CauseReg) + | Regval_ContextReg of (ContextReg) + | Regval_StatusReg of (StatusReg) + | Regval_TLBEntry of (TLBEntry) + | Regval_TLBEntryHiReg of (TLBEntryHiReg) + | Regval_TLBEntryLoReg of (TLBEntryLoReg) + | Regval_XContextReg of (XContextReg) + | Regval_vector_16_dec_bit of ( 16 words$word) + | Regval_vector_1_dec_bit of ( 1 words$word) + | Regval_vector_257_dec_bit of ( 257 words$word) + | Regval_vector_32_dec_bit of ( 32 words$word) + | Regval_vector_64_dec_bit of ( 64 words$word) + | Regval_vector_6_dec_bit of ( 6 words$word) + | Regval_vector_8_dec_bit of ( 8 words$word)`; + + + + +val _ = Hol_datatype ` + regstate = + <| CapCause : CapCauseReg; + CTLSP : 257 words$word; + CTLSU : 257 words$word; + C31 : 257 words$word; + C30 : 257 words$word; + C29 : 257 words$word; + C28 : 257 words$word; + C27 : 257 words$word; + C26 : 257 words$word; + C25 : 257 words$word; + C24 : 257 words$word; + C23 : 257 words$word; + C22 : 257 words$word; + C21 : 257 words$word; + C20 : 257 words$word; + C19 : 257 words$word; + C18 : 257 words$word; + C17 : 257 words$word; + C16 : 257 words$word; + C15 : 257 words$word; + C14 : 257 words$word; + C13 : 257 words$word; + C12 : 257 words$word; + C11 : 257 words$word; + C10 : 257 words$word; + C09 : 257 words$word; + C08 : 257 words$word; + C07 : 257 words$word; + C06 : 257 words$word; + C05 : 257 words$word; + C04 : 257 words$word; + C03 : 257 words$word; + C02 : 257 words$word; + C01 : 257 words$word; + C00 : 257 words$word; + inCCallDelay : 1 words$word; + delayedPCC : 257 words$word; + nextPCC : 257 words$word; + PCC : 257 words$word; + UART_RVALID : 1 words$word; + UART_RDATA : 8 words$word; + UART_WRITTEN : 1 words$word; + UART_WDATA : 8 words$word; + GPR : ( 64 words$word) list; + LO : 64 words$word; + HI : 64 words$word; + delayedPC : 64 words$word; + inBranchDelay : 1 words$word; + branchPending : 1 words$word; + CP0Status : StatusReg; + CP0UserLocal : 64 words$word; + CP0HWREna : 32 words$word; + CP0Count : 32 words$word; + CP0BadVAddr : 64 words$word; + CP0LLAddr : 64 words$word; + CP0LLBit : 1 words$word; + CP0ErrorEPC : 64 words$word; + CP0EPC : 64 words$word; + CP0Cause : CauseReg; + CP0Compare : 32 words$word; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : 6 words$word; + TLBPageMask : 16 words$word; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : 6 words$word; + TLBIndex : 6 words$word; + TLBProbe : 1 words$word; + nextPC : 64 words$word; + PC : 64 words$word |>`; + + + + + +(*val CapCauseReg_of_regval : register_value -> Maybe.maybe CapCauseReg*) + +val _ = Define ` + ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var= + ((case merge_var of Regval_CapCauseReg (v) => SOME v | g__113 => NONE )))`; + + +(*val regval_of_CapCauseReg : CapCauseReg -> register_value*) + +val _ = Define ` + ((regval_of_CapCauseReg:CapCauseReg -> register_value) v= (Regval_CapCauseReg v))`; + + +(*val CauseReg_of_regval : register_value -> Maybe.maybe CauseReg*) + +val _ = Define ` + ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var= + ((case merge_var of Regval_CauseReg (v) => SOME v | g__112 => NONE )))`; + + +(*val regval_of_CauseReg : CauseReg -> register_value*) + +val _ = Define ` + ((regval_of_CauseReg:CauseReg -> register_value) v= (Regval_CauseReg v))`; + + +(*val ContextReg_of_regval : register_value -> Maybe.maybe ContextReg*) + +val _ = Define ` + ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var= + ((case merge_var of Regval_ContextReg (v) => SOME v | g__111 => NONE )))`; + + +(*val regval_of_ContextReg : ContextReg -> register_value*) + +val _ = Define ` + ((regval_of_ContextReg:ContextReg -> register_value) v= (Regval_ContextReg v))`; + + +(*val StatusReg_of_regval : register_value -> Maybe.maybe StatusReg*) + +val _ = Define ` + ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var= + ((case merge_var of Regval_StatusReg (v) => SOME v | g__110 => NONE )))`; + + +(*val regval_of_StatusReg : StatusReg -> register_value*) + +val _ = Define ` + ((regval_of_StatusReg:StatusReg -> register_value) v= (Regval_StatusReg v))`; + + +(*val TLBEntry_of_regval : register_value -> Maybe.maybe TLBEntry*) + +val _ = Define ` + ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var= + ((case merge_var of Regval_TLBEntry (v) => SOME v | g__109 => NONE )))`; + + +(*val regval_of_TLBEntry : TLBEntry -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntry:TLBEntry -> register_value) v= (Regval_TLBEntry v))`; + + +(*val TLBEntryHiReg_of_regval : register_value -> Maybe.maybe TLBEntryHiReg*) + +val _ = Define ` + ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var= + ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__108 => NONE )))`; + + +(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntryHiReg:TLBEntryHiReg -> register_value) v= (Regval_TLBEntryHiReg v))`; + + +(*val TLBEntryLoReg_of_regval : register_value -> Maybe.maybe TLBEntryLoReg*) + +val _ = Define ` + ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var= + ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__107 => NONE )))`; + + +(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntryLoReg:TLBEntryLoReg -> register_value) v= (Regval_TLBEntryLoReg v))`; + + +(*val XContextReg_of_regval : register_value -> Maybe.maybe XContextReg*) + +val _ = Define ` + ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var= + ((case merge_var of Regval_XContextReg (v) => SOME v | g__106 => NONE )))`; + + +(*val regval_of_XContextReg : XContextReg -> register_value*) + +val _ = Define ` + ((regval_of_XContextReg:XContextReg -> register_value) v= (Regval_XContextReg v))`; + + +(*val vector_16_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty16)*) + +val _ = Define ` + ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var= + ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`; + + +(*val regval_of_vector_16_dec_bit : Machine_word.mword Machine_word.ty16 -> register_value*) + +val _ = Define ` + ((regval_of_vector_16_dec_bit:(16)words$word -> register_value) v= (Regval_vector_16_dec_bit v))`; + + +(*val vector_1_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty1)*) + +val _ = Define ` + ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= + ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`; + + +(*val regval_of_vector_1_dec_bit : Machine_word.mword Machine_word.ty1 -> register_value*) + +val _ = Define ` + ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v= (Regval_vector_1_dec_bit v))`; + + +(*val vector_257_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty257)*) + +val _ = Define ` + ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var= + ((case merge_var of Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`; + + +(*val regval_of_vector_257_dec_bit : Machine_word.mword Machine_word.ty257 -> register_value*) + +val _ = Define ` + ((regval_of_vector_257_dec_bit:(257)words$word -> register_value) v= (Regval_vector_257_dec_bit v))`; + + +(*val vector_32_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty32)*) + +val _ = Define ` + ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= + ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`; + + +(*val regval_of_vector_32_dec_bit : Machine_word.mword Machine_word.ty32 -> register_value*) + +val _ = Define ` + ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`; + + +(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`; + + +(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*) + +val _ = Define ` + ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; + + +(*val vector_6_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty6)*) + +val _ = Define ` + ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var= + ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`; + + +(*val regval_of_vector_6_dec_bit : Machine_word.mword Machine_word.ty6 -> register_value*) + +val _ = Define ` + ((regval_of_vector_6_dec_bit:(6)words$word -> register_value) v= (Regval_vector_6_dec_bit v))`; + + +(*val vector_8_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty8)*) + +val _ = Define ` + ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var= + ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`; + + +(*val regval_of_vector_8_dec_bit : Machine_word.mword Machine_word.ty8 -> register_value*) + +val _ = Define ` + ((regval_of_vector_8_dec_bit:(8)words$word -> register_value) v= (Regval_vector_8_dec_bit v))`; + + + + +(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +val _ = Define ` + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + (\x . (case x of + Regval_vector (_, _, v) => just_list (MAP of_regval v) + | _ => NONE + )))`; + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; + + +(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +val _ = Define ` + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + (\x . (case x of + Regval_list v => just_list (MAP of_regval v) + | _ => NONE + )))`; + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; + + +(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*) +val _ = Define ` + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= + (\x . (case x of Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`; + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*) +val _ = Define ` + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; + + + +val _ = Define ` + ((CapCause_ref:((regstate),(register_value),(CapCauseReg))sail_values$register_ref)= (<| + name := "CapCause"; + read_from := (\ s . s.CapCause); + write_to := (\ v s . (( s with<| CapCause := v |>))); + of_regval := (\ v . CapCauseReg_of_regval v); + regval_of := (\ v . regval_of_CapCauseReg v) |>))`; + + +val _ = Define ` + ((CTLSP_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "CTLSP"; + read_from := (\ s . s.CTLSP); + write_to := (\ v s . (( s with<| CTLSP := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((CTLSU_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "CTLSU"; + read_from := (\ s . s.CTLSU); + write_to := (\ v s . (( s with<| CTLSU := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C30_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C30"; + read_from := (\ s . s.C30); + write_to := (\ v s . (( s with<| C30 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C28_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C28"; + read_from := (\ s . s.C28); + write_to := (\ v s . (( s with<| C28 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C27_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C27"; + read_from := (\ s . s.C27); + write_to := (\ v s . (( s with<| C27 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C26_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C26"; + read_from := (\ s . s.C26); + write_to := (\ v s . (( s with<| C26 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C25_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C25"; + read_from := (\ s . s.C25); + write_to := (\ v s . (( s with<| C25 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C24_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C24"; + read_from := (\ s . s.C24); + write_to := (\ v s . (( s with<| C24 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C23_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C23"; + read_from := (\ s . s.C23); + write_to := (\ v s . (( s with<| C23 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C22_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C22"; + read_from := (\ s . s.C22); + write_to := (\ v s . (( s with<| C22 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C21_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C21"; + read_from := (\ s . s.C21); + write_to := (\ v s . (( s with<| C21 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C20_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C20"; + read_from := (\ s . s.C20); + write_to := (\ v s . (( s with<| C20 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C19_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C19"; + read_from := (\ s . s.C19); + write_to := (\ v s . (( s with<| C19 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C18_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C18"; + read_from := (\ s . s.C18); + write_to := (\ v s . (( s with<| C18 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C17_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C17"; + read_from := (\ s . s.C17); + write_to := (\ v s . (( s with<| C17 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C16_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C16"; + read_from := (\ s . s.C16); + write_to := (\ v s . (( s with<| C16 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C15_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C15"; + read_from := (\ s . s.C15); + write_to := (\ v s . (( s with<| C15 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C14_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C14"; + read_from := (\ s . s.C14); + write_to := (\ v s . (( s with<| C14 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C13_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C13"; + read_from := (\ s . s.C13); + write_to := (\ v s . (( s with<| C13 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C12_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C12"; + read_from := (\ s . s.C12); + write_to := (\ v s . (( s with<| C12 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C11_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C11"; + read_from := (\ s . s.C11); + write_to := (\ v s . (( s with<| C11 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C10_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C10"; + read_from := (\ s . s.C10); + write_to := (\ v s . (( s with<| C10 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C09_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C09"; + read_from := (\ s . s.C09); + write_to := (\ v s . (( s with<| C09 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C08_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C08"; + read_from := (\ s . s.C08); + write_to := (\ v s . (( s with<| C08 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C07_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C07"; + read_from := (\ s . s.C07); + write_to := (\ v s . (( s with<| C07 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C06_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C06"; + read_from := (\ s . s.C06); + write_to := (\ v s . (( s with<| C06 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C05_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C05"; + read_from := (\ s . s.C05); + write_to := (\ v s . (( s with<| C05 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C04_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C04"; + read_from := (\ s . s.C04); + write_to := (\ v s . (( s with<| C04 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C03_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C03"; + read_from := (\ s . s.C03); + write_to := (\ v s . (( s with<| C03 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C02_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C02"; + read_from := (\ s . s.C02); + write_to := (\ v s . (( s with<| C02 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C01_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C01"; + read_from := (\ s . s.C01); + write_to := (\ v s . (( s with<| C01 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C00_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C00"; + read_from := (\ s . s.C00); + write_to := (\ v s . (( s with<| C00 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((inCCallDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "inCCallDelay"; + read_from := (\ s . s.inCCallDelay); + write_to := (\ v s . (( s with<| inCCallDelay := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((nextPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "nextPCC"; + read_from := (\ s . s.nextPCC); + write_to := (\ v s . (( s with<| nextPCC := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((delayedPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "delayedPCC"; + read_from := (\ s . s.delayedPCC); + write_to := (\ v s . (( s with<| delayedPCC := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((PCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "PCC"; + read_from := (\ s . s.PCC); + write_to := (\ v s . (( s with<| PCC := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C31_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C31"; + read_from := (\ s . s.C31); + write_to := (\ v s . (( s with<| C31 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((C29_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + name := "C29"; + read_from := (\ s . s.C29); + write_to := (\ v s . (( s with<| C29 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "UART_RVALID"; + read_from := (\ s . s.UART_RVALID); + write_to := (\ v s . (( s with<| UART_RVALID := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)= (<| + name := "UART_RDATA"; + read_from := (\ s . s.UART_RDATA); + write_to := (\ v s . (( s with<| UART_RDATA := v |>))); + of_regval := (\ v . vector_8_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_8_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "UART_WRITTEN"; + read_from := (\ s . s.UART_WRITTEN); + write_to := (\ v s . (( s with<| UART_WRITTEN := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)= (<| + name := "UART_WDATA"; + read_from := (\ s . s.UART_WDATA); + write_to := (\ v s . (( s with<| UART_WDATA := v |>))); + of_regval := (\ v . vector_8_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_8_dec_bit v) |>))`; + + +val _ = Define ` + ((GPR_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)= (<| + name := "GPR"; + read_from := (\ s . s.GPR); + write_to := (\ v s . (( s with<| GPR := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`; + + +val _ = Define ` + ((LO_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "LO"; + read_from := (\ s . s.LO); + write_to := (\ v s . (( s with<| LO := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((HI_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "HI"; + read_from := (\ s . s.HI); + write_to := (\ v s . (( s with<| HI := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((delayedPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "delayedPC"; + read_from := (\ s . s.delayedPC); + write_to := (\ v s . (( s with<| delayedPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "inBranchDelay"; + read_from := (\ s . s.inBranchDelay); + write_to := (\ v s . (( s with<| inBranchDelay := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((branchPending_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "branchPending"; + read_from := (\ s . s.branchPending); + write_to := (\ v s . (( s with<| branchPending := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Status_ref:((regstate),(register_value),(StatusReg))sail_values$register_ref)= (<| + name := "CP0Status"; + read_from := (\ s . s.CP0Status); + write_to := (\ v s . (( s with<| CP0Status := v |>))); + of_regval := (\ v . StatusReg_of_regval v); + regval_of := (\ v . regval_of_StatusReg v) |>))`; + + +val _ = Define ` + ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "CP0UserLocal"; + read_from := (\ s . s.CP0UserLocal); + write_to := (\ v s . (( s with<| CP0UserLocal := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + name := "CP0HWREna"; + read_from := (\ s . s.CP0HWREna); + write_to := (\ v s . (( s with<| CP0HWREna := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Count_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + name := "CP0Count"; + read_from := (\ s . s.CP0Count); + write_to := (\ v s . (( s with<| CP0Count := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "CP0BadVAddr"; + read_from := (\ s . s.CP0BadVAddr); + write_to := (\ v s . (( s with<| CP0BadVAddr := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "CP0LLAddr"; + read_from := (\ s . s.CP0LLAddr); + write_to := (\ v s . (( s with<| CP0LLAddr := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "CP0LLBit"; + read_from := (\ s . s.CP0LLBit); + write_to := (\ v s . (( s with<| CP0LLBit := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "CP0ErrorEPC"; + read_from := (\ s . s.CP0ErrorEPC); + write_to := (\ v s . (( s with<| CP0ErrorEPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0EPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "CP0EPC"; + read_from := (\ s . s.CP0EPC); + write_to := (\ v s . (( s with<| CP0EPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Cause_ref:((regstate),(register_value),(CauseReg))sail_values$register_ref)= (<| + name := "CP0Cause"; + read_from := (\ s . s.CP0Cause); + write_to := (\ v s . (( s with<| CP0Cause := v |>))); + of_regval := (\ v . CauseReg_of_regval v); + regval_of := (\ v . regval_of_CauseReg v) |>))`; + + +val _ = Define ` + ((CP0Compare_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + name := "CP0Compare"; + read_from := (\ s . s.CP0Compare); + write_to := (\ v s . (( s with<| CP0Compare := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry63"; + read_from := (\ s . s.TLBEntry63); + write_to := (\ v s . (( s with<| TLBEntry63 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry62"; + read_from := (\ s . s.TLBEntry62); + write_to := (\ v s . (( s with<| TLBEntry62 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry61"; + read_from := (\ s . s.TLBEntry61); + write_to := (\ v s . (( s with<| TLBEntry61 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry60"; + read_from := (\ s . s.TLBEntry60); + write_to := (\ v s . (( s with<| TLBEntry60 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry59"; + read_from := (\ s . s.TLBEntry59); + write_to := (\ v s . (( s with<| TLBEntry59 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry58"; + read_from := (\ s . s.TLBEntry58); + write_to := (\ v s . (( s with<| TLBEntry58 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry57"; + read_from := (\ s . s.TLBEntry57); + write_to := (\ v s . (( s with<| TLBEntry57 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry56"; + read_from := (\ s . s.TLBEntry56); + write_to := (\ v s . (( s with<| TLBEntry56 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry55"; + read_from := (\ s . s.TLBEntry55); + write_to := (\ v s . (( s with<| TLBEntry55 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry54"; + read_from := (\ s . s.TLBEntry54); + write_to := (\ v s . (( s with<| TLBEntry54 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry53"; + read_from := (\ s . s.TLBEntry53); + write_to := (\ v s . (( s with<| TLBEntry53 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry52"; + read_from := (\ s . s.TLBEntry52); + write_to := (\ v s . (( s with<| TLBEntry52 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry51"; + read_from := (\ s . s.TLBEntry51); + write_to := (\ v s . (( s with<| TLBEntry51 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry50"; + read_from := (\ s . s.TLBEntry50); + write_to := (\ v s . (( s with<| TLBEntry50 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry49"; + read_from := (\ s . s.TLBEntry49); + write_to := (\ v s . (( s with<| TLBEntry49 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry48"; + read_from := (\ s . s.TLBEntry48); + write_to := (\ v s . (( s with<| TLBEntry48 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry47"; + read_from := (\ s . s.TLBEntry47); + write_to := (\ v s . (( s with<| TLBEntry47 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry46"; + read_from := (\ s . s.TLBEntry46); + write_to := (\ v s . (( s with<| TLBEntry46 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry45"; + read_from := (\ s . s.TLBEntry45); + write_to := (\ v s . (( s with<| TLBEntry45 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry44"; + read_from := (\ s . s.TLBEntry44); + write_to := (\ v s . (( s with<| TLBEntry44 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry43"; + read_from := (\ s . s.TLBEntry43); + write_to := (\ v s . (( s with<| TLBEntry43 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry42"; + read_from := (\ s . s.TLBEntry42); + write_to := (\ v s . (( s with<| TLBEntry42 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry41"; + read_from := (\ s . s.TLBEntry41); + write_to := (\ v s . (( s with<| TLBEntry41 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry40"; + read_from := (\ s . s.TLBEntry40); + write_to := (\ v s . (( s with<| TLBEntry40 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry39"; + read_from := (\ s . s.TLBEntry39); + write_to := (\ v s . (( s with<| TLBEntry39 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry38"; + read_from := (\ s . s.TLBEntry38); + write_to := (\ v s . (( s with<| TLBEntry38 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry37"; + read_from := (\ s . s.TLBEntry37); + write_to := (\ v s . (( s with<| TLBEntry37 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry36"; + read_from := (\ s . s.TLBEntry36); + write_to := (\ v s . (( s with<| TLBEntry36 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry35"; + read_from := (\ s . s.TLBEntry35); + write_to := (\ v s . (( s with<| TLBEntry35 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry34"; + read_from := (\ s . s.TLBEntry34); + write_to := (\ v s . (( s with<| TLBEntry34 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry33"; + read_from := (\ s . s.TLBEntry33); + write_to := (\ v s . (( s with<| TLBEntry33 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry32"; + read_from := (\ s . s.TLBEntry32); + write_to := (\ v s . (( s with<| TLBEntry32 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry31"; + read_from := (\ s . s.TLBEntry31); + write_to := (\ v s . (( s with<| TLBEntry31 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry30"; + read_from := (\ s . s.TLBEntry30); + write_to := (\ v s . (( s with<| TLBEntry30 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry29"; + read_from := (\ s . s.TLBEntry29); + write_to := (\ v s . (( s with<| TLBEntry29 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry28"; + read_from := (\ s . s.TLBEntry28); + write_to := (\ v s . (( s with<| TLBEntry28 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry27"; + read_from := (\ s . s.TLBEntry27); + write_to := (\ v s . (( s with<| TLBEntry27 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry26"; + read_from := (\ s . s.TLBEntry26); + write_to := (\ v s . (( s with<| TLBEntry26 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry25"; + read_from := (\ s . s.TLBEntry25); + write_to := (\ v s . (( s with<| TLBEntry25 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry24"; + read_from := (\ s . s.TLBEntry24); + write_to := (\ v s . (( s with<| TLBEntry24 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry23"; + read_from := (\ s . s.TLBEntry23); + write_to := (\ v s . (( s with<| TLBEntry23 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry22"; + read_from := (\ s . s.TLBEntry22); + write_to := (\ v s . (( s with<| TLBEntry22 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry21"; + read_from := (\ s . s.TLBEntry21); + write_to := (\ v s . (( s with<| TLBEntry21 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry20"; + read_from := (\ s . s.TLBEntry20); + write_to := (\ v s . (( s with<| TLBEntry20 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry19"; + read_from := (\ s . s.TLBEntry19); + write_to := (\ v s . (( s with<| TLBEntry19 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry18"; + read_from := (\ s . s.TLBEntry18); + write_to := (\ v s . (( s with<| TLBEntry18 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry17"; + read_from := (\ s . s.TLBEntry17); + write_to := (\ v s . (( s with<| TLBEntry17 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry16"; + read_from := (\ s . s.TLBEntry16); + write_to := (\ v s . (( s with<| TLBEntry16 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry15"; + read_from := (\ s . s.TLBEntry15); + write_to := (\ v s . (( s with<| TLBEntry15 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry14"; + read_from := (\ s . s.TLBEntry14); + write_to := (\ v s . (( s with<| TLBEntry14 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry13"; + read_from := (\ s . s.TLBEntry13); + write_to := (\ v s . (( s with<| TLBEntry13 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry12"; + read_from := (\ s . s.TLBEntry12); + write_to := (\ v s . (( s with<| TLBEntry12 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry11"; + read_from := (\ s . s.TLBEntry11); + write_to := (\ v s . (( s with<| TLBEntry11 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry10"; + read_from := (\ s . s.TLBEntry10); + write_to := (\ v s . (( s with<| TLBEntry10 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry09"; + read_from := (\ s . s.TLBEntry09); + write_to := (\ v s . (( s with<| TLBEntry09 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry08"; + read_from := (\ s . s.TLBEntry08); + write_to := (\ v s . (( s with<| TLBEntry08 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry07"; + read_from := (\ s . s.TLBEntry07); + write_to := (\ v s . (( s with<| TLBEntry07 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry06"; + read_from := (\ s . s.TLBEntry06); + write_to := (\ v s . (( s with<| TLBEntry06 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry05"; + read_from := (\ s . s.TLBEntry05); + write_to := (\ v s . (( s with<| TLBEntry05 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry04"; + read_from := (\ s . s.TLBEntry04); + write_to := (\ v s . (( s with<| TLBEntry04 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry03"; + read_from := (\ s . s.TLBEntry03); + write_to := (\ v s . (( s with<| TLBEntry03 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry02"; + read_from := (\ s . s.TLBEntry02); + write_to := (\ v s . (( s with<| TLBEntry02 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry01"; + read_from := (\ s . s.TLBEntry01); + write_to := (\ v s . (( s with<| TLBEntry01 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + name := "TLBEntry00"; + read_from := (\ s . s.TLBEntry00); + write_to := (\ v s . (( s with<| TLBEntry00 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBXContext_ref:((regstate),(register_value),(XContextReg))sail_values$register_ref)= (<| + name := "TLBXContext"; + read_from := (\ s . s.TLBXContext); + write_to := (\ v s . (( s with<| TLBXContext := v |>))); + of_regval := (\ v . XContextReg_of_regval v); + regval_of := (\ v . regval_of_XContextReg v) |>))`; + + +val _ = Define ` + ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))sail_values$register_ref)= (<| + name := "TLBEntryHi"; + read_from := (\ s . s.TLBEntryHi); + write_to := (\ v s . (( s with<| TLBEntryHi := v |>))); + of_regval := (\ v . TLBEntryHiReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryHiReg v) |>))`; + + +val _ = Define ` + ((TLBWired_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + name := "TLBWired"; + read_from := (\ s . s.TLBWired); + write_to := (\ v s . (( s with<| TLBWired := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))sail_values$register_ref)= (<| + name := "TLBPageMask"; + read_from := (\ s . s.TLBPageMask); + write_to := (\ v s . (( s with<| TLBPageMask := v |>))); + of_regval := (\ v . vector_16_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_16_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBContext_ref:((regstate),(register_value),(ContextReg))sail_values$register_ref)= (<| + name := "TLBContext"; + read_from := (\ s . s.TLBContext); + write_to := (\ v s . (( s with<| TLBContext := v |>))); + of_regval := (\ v . ContextReg_of_regval v); + regval_of := (\ v . regval_of_ContextReg v) |>))`; + + +val _ = Define ` + ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)= (<| + name := "TLBEntryLo1"; + read_from := (\ s . s.TLBEntryLo1); + write_to := (\ v s . (( s with<| TLBEntryLo1 := v |>))); + of_regval := (\ v . TLBEntryLoReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryLoReg v) |>))`; + + +val _ = Define ` + ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)= (<| + name := "TLBEntryLo0"; + read_from := (\ s . s.TLBEntryLo0); + write_to := (\ v s . (( s with<| TLBEntryLo0 := v |>))); + of_regval := (\ v . TLBEntryLoReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryLoReg v) |>))`; + + +val _ = Define ` + ((TLBRandom_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + name := "TLBRandom"; + read_from := (\ s . s.TLBRandom); + write_to := (\ v s . (( s with<| TLBRandom := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBIndex_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + name := "TLBIndex"; + read_from := (\ s . s.TLBIndex); + write_to := (\ v s . (( s with<| TLBIndex := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBProbe_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + name := "TLBProbe"; + read_from := (\ s . s.TLBProbe); + write_to := (\ v s . (( s with<| TLBProbe := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "nextPC"; + read_from := (\ s . s.nextPC); + write_to := (\ v s . (( s with<| nextPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "PC"; + read_from := (\ s . s.PC); + write_to := (\ v s . (( s with<| PC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +(*val get_regval : string -> regstate -> Maybe.maybe register_value*) +val _ = Define ` + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else + if reg_name = "CTLSP" then SOME (CTLSP_ref.regval_of (CTLSP_ref.read_from s)) else + if reg_name = "CTLSU" then SOME (CTLSU_ref.regval_of (CTLSU_ref.read_from s)) else + if reg_name = "C30" then SOME (C30_ref.regval_of (C30_ref.read_from s)) else + if reg_name = "C28" then SOME (C28_ref.regval_of (C28_ref.read_from s)) else + if reg_name = "C27" then SOME (C27_ref.regval_of (C27_ref.read_from s)) else + if reg_name = "C26" then SOME (C26_ref.regval_of (C26_ref.read_from s)) else + if reg_name = "C25" then SOME (C25_ref.regval_of (C25_ref.read_from s)) else + if reg_name = "C24" then SOME (C24_ref.regval_of (C24_ref.read_from s)) else + if reg_name = "C23" then SOME (C23_ref.regval_of (C23_ref.read_from s)) else + if reg_name = "C22" then SOME (C22_ref.regval_of (C22_ref.read_from s)) else + if reg_name = "C21" then SOME (C21_ref.regval_of (C21_ref.read_from s)) else + if reg_name = "C20" then SOME (C20_ref.regval_of (C20_ref.read_from s)) else + if reg_name = "C19" then SOME (C19_ref.regval_of (C19_ref.read_from s)) else + if reg_name = "C18" then SOME (C18_ref.regval_of (C18_ref.read_from s)) else + if reg_name = "C17" then SOME (C17_ref.regval_of (C17_ref.read_from s)) else + if reg_name = "C16" then SOME (C16_ref.regval_of (C16_ref.read_from s)) else + if reg_name = "C15" then SOME (C15_ref.regval_of (C15_ref.read_from s)) else + if reg_name = "C14" then SOME (C14_ref.regval_of (C14_ref.read_from s)) else + if reg_name = "C13" then SOME (C13_ref.regval_of (C13_ref.read_from s)) else + if reg_name = "C12" then SOME (C12_ref.regval_of (C12_ref.read_from s)) else + if reg_name = "C11" then SOME (C11_ref.regval_of (C11_ref.read_from s)) else + if reg_name = "C10" then SOME (C10_ref.regval_of (C10_ref.read_from s)) else + if reg_name = "C09" then SOME (C09_ref.regval_of (C09_ref.read_from s)) else + if reg_name = "C08" then SOME (C08_ref.regval_of (C08_ref.read_from s)) else + if reg_name = "C07" then SOME (C07_ref.regval_of (C07_ref.read_from s)) else + if reg_name = "C06" then SOME (C06_ref.regval_of (C06_ref.read_from s)) else + if reg_name = "C05" then SOME (C05_ref.regval_of (C05_ref.read_from s)) else + if reg_name = "C04" then SOME (C04_ref.regval_of (C04_ref.read_from s)) else + if reg_name = "C03" then SOME (C03_ref.regval_of (C03_ref.read_from s)) else + if reg_name = "C02" then SOME (C02_ref.regval_of (C02_ref.read_from s)) else + if reg_name = "C01" then SOME (C01_ref.regval_of (C01_ref.read_from s)) else + if reg_name = "C00" then SOME (C00_ref.regval_of (C00_ref.read_from s)) else + if reg_name = "inCCallDelay" then SOME (inCCallDelay_ref.regval_of (inCCallDelay_ref.read_from s)) else + if reg_name = "nextPCC" then SOME (nextPCC_ref.regval_of (nextPCC_ref.read_from s)) else + if reg_name = "delayedPCC" then SOME (delayedPCC_ref.regval_of (delayedPCC_ref.read_from s)) else + if reg_name = "PCC" then SOME (PCC_ref.regval_of (PCC_ref.read_from s)) else + if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else + if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else + if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else + if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else + if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else + if reg_name = "UART_WDATA" then SOME (UART_WDATA_ref.regval_of (UART_WDATA_ref.read_from s)) else + if reg_name = "GPR" then SOME (GPR_ref.regval_of (GPR_ref.read_from s)) else + if reg_name = "LO" then SOME (LO_ref.regval_of (LO_ref.read_from s)) else + if reg_name = "HI" then SOME (HI_ref.regval_of (HI_ref.read_from s)) else + if reg_name = "delayedPC" then SOME (delayedPC_ref.regval_of (delayedPC_ref.read_from s)) else + if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else + if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else + if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else + if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else + if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else + if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else + if reg_name = "CP0BadVAddr" then SOME (CP0BadVAddr_ref.regval_of (CP0BadVAddr_ref.read_from s)) else + if reg_name = "CP0LLAddr" then SOME (CP0LLAddr_ref.regval_of (CP0LLAddr_ref.read_from s)) else + if reg_name = "CP0LLBit" then SOME (CP0LLBit_ref.regval_of (CP0LLBit_ref.read_from s)) else + if reg_name = "CP0ErrorEPC" then SOME (CP0ErrorEPC_ref.regval_of (CP0ErrorEPC_ref.read_from s)) else + if reg_name = "CP0EPC" then SOME (CP0EPC_ref.regval_of (CP0EPC_ref.read_from s)) else + if reg_name = "CP0Cause" then SOME (CP0Cause_ref.regval_of (CP0Cause_ref.read_from s)) else + if reg_name = "CP0Compare" then SOME (CP0Compare_ref.regval_of (CP0Compare_ref.read_from s)) else + if reg_name = "TLBEntry63" then SOME (TLBEntry63_ref.regval_of (TLBEntry63_ref.read_from s)) else + if reg_name = "TLBEntry62" then SOME (TLBEntry62_ref.regval_of (TLBEntry62_ref.read_from s)) else + if reg_name = "TLBEntry61" then SOME (TLBEntry61_ref.regval_of (TLBEntry61_ref.read_from s)) else + if reg_name = "TLBEntry60" then SOME (TLBEntry60_ref.regval_of (TLBEntry60_ref.read_from s)) else + if reg_name = "TLBEntry59" then SOME (TLBEntry59_ref.regval_of (TLBEntry59_ref.read_from s)) else + if reg_name = "TLBEntry58" then SOME (TLBEntry58_ref.regval_of (TLBEntry58_ref.read_from s)) else + if reg_name = "TLBEntry57" then SOME (TLBEntry57_ref.regval_of (TLBEntry57_ref.read_from s)) else + if reg_name = "TLBEntry56" then SOME (TLBEntry56_ref.regval_of (TLBEntry56_ref.read_from s)) else + if reg_name = "TLBEntry55" then SOME (TLBEntry55_ref.regval_of (TLBEntry55_ref.read_from s)) else + if reg_name = "TLBEntry54" then SOME (TLBEntry54_ref.regval_of (TLBEntry54_ref.read_from s)) else + if reg_name = "TLBEntry53" then SOME (TLBEntry53_ref.regval_of (TLBEntry53_ref.read_from s)) else + if reg_name = "TLBEntry52" then SOME (TLBEntry52_ref.regval_of (TLBEntry52_ref.read_from s)) else + if reg_name = "TLBEntry51" then SOME (TLBEntry51_ref.regval_of (TLBEntry51_ref.read_from s)) else + if reg_name = "TLBEntry50" then SOME (TLBEntry50_ref.regval_of (TLBEntry50_ref.read_from s)) else + if reg_name = "TLBEntry49" then SOME (TLBEntry49_ref.regval_of (TLBEntry49_ref.read_from s)) else + if reg_name = "TLBEntry48" then SOME (TLBEntry48_ref.regval_of (TLBEntry48_ref.read_from s)) else + if reg_name = "TLBEntry47" then SOME (TLBEntry47_ref.regval_of (TLBEntry47_ref.read_from s)) else + if reg_name = "TLBEntry46" then SOME (TLBEntry46_ref.regval_of (TLBEntry46_ref.read_from s)) else + if reg_name = "TLBEntry45" then SOME (TLBEntry45_ref.regval_of (TLBEntry45_ref.read_from s)) else + if reg_name = "TLBEntry44" then SOME (TLBEntry44_ref.regval_of (TLBEntry44_ref.read_from s)) else + if reg_name = "TLBEntry43" then SOME (TLBEntry43_ref.regval_of (TLBEntry43_ref.read_from s)) else + if reg_name = "TLBEntry42" then SOME (TLBEntry42_ref.regval_of (TLBEntry42_ref.read_from s)) else + if reg_name = "TLBEntry41" then SOME (TLBEntry41_ref.regval_of (TLBEntry41_ref.read_from s)) else + if reg_name = "TLBEntry40" then SOME (TLBEntry40_ref.regval_of (TLBEntry40_ref.read_from s)) else + if reg_name = "TLBEntry39" then SOME (TLBEntry39_ref.regval_of (TLBEntry39_ref.read_from s)) else + if reg_name = "TLBEntry38" then SOME (TLBEntry38_ref.regval_of (TLBEntry38_ref.read_from s)) else + if reg_name = "TLBEntry37" then SOME (TLBEntry37_ref.regval_of (TLBEntry37_ref.read_from s)) else + if reg_name = "TLBEntry36" then SOME (TLBEntry36_ref.regval_of (TLBEntry36_ref.read_from s)) else + if reg_name = "TLBEntry35" then SOME (TLBEntry35_ref.regval_of (TLBEntry35_ref.read_from s)) else + if reg_name = "TLBEntry34" then SOME (TLBEntry34_ref.regval_of (TLBEntry34_ref.read_from s)) else + if reg_name = "TLBEntry33" then SOME (TLBEntry33_ref.regval_of (TLBEntry33_ref.read_from s)) else + if reg_name = "TLBEntry32" then SOME (TLBEntry32_ref.regval_of (TLBEntry32_ref.read_from s)) else + if reg_name = "TLBEntry31" then SOME (TLBEntry31_ref.regval_of (TLBEntry31_ref.read_from s)) else + if reg_name = "TLBEntry30" then SOME (TLBEntry30_ref.regval_of (TLBEntry30_ref.read_from s)) else + if reg_name = "TLBEntry29" then SOME (TLBEntry29_ref.regval_of (TLBEntry29_ref.read_from s)) else + if reg_name = "TLBEntry28" then SOME (TLBEntry28_ref.regval_of (TLBEntry28_ref.read_from s)) else + if reg_name = "TLBEntry27" then SOME (TLBEntry27_ref.regval_of (TLBEntry27_ref.read_from s)) else + if reg_name = "TLBEntry26" then SOME (TLBEntry26_ref.regval_of (TLBEntry26_ref.read_from s)) else + if reg_name = "TLBEntry25" then SOME (TLBEntry25_ref.regval_of (TLBEntry25_ref.read_from s)) else + if reg_name = "TLBEntry24" then SOME (TLBEntry24_ref.regval_of (TLBEntry24_ref.read_from s)) else + if reg_name = "TLBEntry23" then SOME (TLBEntry23_ref.regval_of (TLBEntry23_ref.read_from s)) else + if reg_name = "TLBEntry22" then SOME (TLBEntry22_ref.regval_of (TLBEntry22_ref.read_from s)) else + if reg_name = "TLBEntry21" then SOME (TLBEntry21_ref.regval_of (TLBEntry21_ref.read_from s)) else + if reg_name = "TLBEntry20" then SOME (TLBEntry20_ref.regval_of (TLBEntry20_ref.read_from s)) else + if reg_name = "TLBEntry19" then SOME (TLBEntry19_ref.regval_of (TLBEntry19_ref.read_from s)) else + if reg_name = "TLBEntry18" then SOME (TLBEntry18_ref.regval_of (TLBEntry18_ref.read_from s)) else + if reg_name = "TLBEntry17" then SOME (TLBEntry17_ref.regval_of (TLBEntry17_ref.read_from s)) else + if reg_name = "TLBEntry16" then SOME (TLBEntry16_ref.regval_of (TLBEntry16_ref.read_from s)) else + if reg_name = "TLBEntry15" then SOME (TLBEntry15_ref.regval_of (TLBEntry15_ref.read_from s)) else + if reg_name = "TLBEntry14" then SOME (TLBEntry14_ref.regval_of (TLBEntry14_ref.read_from s)) else + if reg_name = "TLBEntry13" then SOME (TLBEntry13_ref.regval_of (TLBEntry13_ref.read_from s)) else + if reg_name = "TLBEntry12" then SOME (TLBEntry12_ref.regval_of (TLBEntry12_ref.read_from s)) else + if reg_name = "TLBEntry11" then SOME (TLBEntry11_ref.regval_of (TLBEntry11_ref.read_from s)) else + if reg_name = "TLBEntry10" then SOME (TLBEntry10_ref.regval_of (TLBEntry10_ref.read_from s)) else + if reg_name = "TLBEntry09" then SOME (TLBEntry09_ref.regval_of (TLBEntry09_ref.read_from s)) else + if reg_name = "TLBEntry08" then SOME (TLBEntry08_ref.regval_of (TLBEntry08_ref.read_from s)) else + if reg_name = "TLBEntry07" then SOME (TLBEntry07_ref.regval_of (TLBEntry07_ref.read_from s)) else + if reg_name = "TLBEntry06" then SOME (TLBEntry06_ref.regval_of (TLBEntry06_ref.read_from s)) else + if reg_name = "TLBEntry05" then SOME (TLBEntry05_ref.regval_of (TLBEntry05_ref.read_from s)) else + if reg_name = "TLBEntry04" then SOME (TLBEntry04_ref.regval_of (TLBEntry04_ref.read_from s)) else + if reg_name = "TLBEntry03" then SOME (TLBEntry03_ref.regval_of (TLBEntry03_ref.read_from s)) else + if reg_name = "TLBEntry02" then SOME (TLBEntry02_ref.regval_of (TLBEntry02_ref.read_from s)) else + if reg_name = "TLBEntry01" then SOME (TLBEntry01_ref.regval_of (TLBEntry01_ref.read_from s)) else + if reg_name = "TLBEntry00" then SOME (TLBEntry00_ref.regval_of (TLBEntry00_ref.read_from s)) else + if reg_name = "TLBXContext" then SOME (TLBXContext_ref.regval_of (TLBXContext_ref.read_from s)) else + if reg_name = "TLBEntryHi" then SOME (TLBEntryHi_ref.regval_of (TLBEntryHi_ref.read_from s)) else + if reg_name = "TLBWired" then SOME (TLBWired_ref.regval_of (TLBWired_ref.read_from s)) else + if reg_name = "TLBPageMask" then SOME (TLBPageMask_ref.regval_of (TLBPageMask_ref.read_from s)) else + if reg_name = "TLBContext" then SOME (TLBContext_ref.regval_of (TLBContext_ref.read_from s)) else + if reg_name = "TLBEntryLo1" then SOME (TLBEntryLo1_ref.regval_of (TLBEntryLo1_ref.read_from s)) else + if reg_name = "TLBEntryLo0" then SOME (TLBEntryLo0_ref.regval_of (TLBEntryLo0_ref.read_from s)) else + if reg_name = "TLBRandom" then SOME (TLBRandom_ref.regval_of (TLBRandom_ref.read_from s)) else + if reg_name = "TLBIndex" then SOME (TLBIndex_ref.regval_of (TLBIndex_ref.read_from s)) else + if reg_name = "TLBProbe" then SOME (TLBProbe_ref.regval_of (TLBProbe_ref.read_from s)) else + if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else + if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else + NONE))`; + + +(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*) +val _ = Define ` + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "CapCause" then OPTION_MAP (\ v . CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else + if reg_name = "CTLSP" then OPTION_MAP (\ v . CTLSP_ref.write_to v s) (CTLSP_ref.of_regval v) else + if reg_name = "CTLSU" then OPTION_MAP (\ v . CTLSU_ref.write_to v s) (CTLSU_ref.of_regval v) else + if reg_name = "C30" then OPTION_MAP (\ v . C30_ref.write_to v s) (C30_ref.of_regval v) else + if reg_name = "C28" then OPTION_MAP (\ v . C28_ref.write_to v s) (C28_ref.of_regval v) else + if reg_name = "C27" then OPTION_MAP (\ v . C27_ref.write_to v s) (C27_ref.of_regval v) else + if reg_name = "C26" then OPTION_MAP (\ v . C26_ref.write_to v s) (C26_ref.of_regval v) else + if reg_name = "C25" then OPTION_MAP (\ v . C25_ref.write_to v s) (C25_ref.of_regval v) else + if reg_name = "C24" then OPTION_MAP (\ v . C24_ref.write_to v s) (C24_ref.of_regval v) else + if reg_name = "C23" then OPTION_MAP (\ v . C23_ref.write_to v s) (C23_ref.of_regval v) else + if reg_name = "C22" then OPTION_MAP (\ v . C22_ref.write_to v s) (C22_ref.of_regval v) else + if reg_name = "C21" then OPTION_MAP (\ v . C21_ref.write_to v s) (C21_ref.of_regval v) else + if reg_name = "C20" then OPTION_MAP (\ v . C20_ref.write_to v s) (C20_ref.of_regval v) else + if reg_name = "C19" then OPTION_MAP (\ v . C19_ref.write_to v s) (C19_ref.of_regval v) else + if reg_name = "C18" then OPTION_MAP (\ v . C18_ref.write_to v s) (C18_ref.of_regval v) else + if reg_name = "C17" then OPTION_MAP (\ v . C17_ref.write_to v s) (C17_ref.of_regval v) else + if reg_name = "C16" then OPTION_MAP (\ v . C16_ref.write_to v s) (C16_ref.of_regval v) else + if reg_name = "C15" then OPTION_MAP (\ v . C15_ref.write_to v s) (C15_ref.of_regval v) else + if reg_name = "C14" then OPTION_MAP (\ v . C14_ref.write_to v s) (C14_ref.of_regval v) else + if reg_name = "C13" then OPTION_MAP (\ v . C13_ref.write_to v s) (C13_ref.of_regval v) else + if reg_name = "C12" then OPTION_MAP (\ v . C12_ref.write_to v s) (C12_ref.of_regval v) else + if reg_name = "C11" then OPTION_MAP (\ v . C11_ref.write_to v s) (C11_ref.of_regval v) else + if reg_name = "C10" then OPTION_MAP (\ v . C10_ref.write_to v s) (C10_ref.of_regval v) else + if reg_name = "C09" then OPTION_MAP (\ v . C09_ref.write_to v s) (C09_ref.of_regval v) else + if reg_name = "C08" then OPTION_MAP (\ v . C08_ref.write_to v s) (C08_ref.of_regval v) else + if reg_name = "C07" then OPTION_MAP (\ v . C07_ref.write_to v s) (C07_ref.of_regval v) else + if reg_name = "C06" then OPTION_MAP (\ v . C06_ref.write_to v s) (C06_ref.of_regval v) else + if reg_name = "C05" then OPTION_MAP (\ v . C05_ref.write_to v s) (C05_ref.of_regval v) else + if reg_name = "C04" then OPTION_MAP (\ v . C04_ref.write_to v s) (C04_ref.of_regval v) else + if reg_name = "C03" then OPTION_MAP (\ v . C03_ref.write_to v s) (C03_ref.of_regval v) else + if reg_name = "C02" then OPTION_MAP (\ v . C02_ref.write_to v s) (C02_ref.of_regval v) else + if reg_name = "C01" then OPTION_MAP (\ v . C01_ref.write_to v s) (C01_ref.of_regval v) else + if reg_name = "C00" then OPTION_MAP (\ v . C00_ref.write_to v s) (C00_ref.of_regval v) else + if reg_name = "inCCallDelay" then OPTION_MAP (\ v . inCCallDelay_ref.write_to v s) (inCCallDelay_ref.of_regval v) else + if reg_name = "nextPCC" then OPTION_MAP (\ v . nextPCC_ref.write_to v s) (nextPCC_ref.of_regval v) else + if reg_name = "delayedPCC" then OPTION_MAP (\ v . delayedPCC_ref.write_to v s) (delayedPCC_ref.of_regval v) else + if reg_name = "PCC" then OPTION_MAP (\ v . PCC_ref.write_to v s) (PCC_ref.of_regval v) else + if reg_name = "C31" then OPTION_MAP (\ v . C31_ref.write_to v s) (C31_ref.of_regval v) else + if reg_name = "C29" then OPTION_MAP (\ v . C29_ref.write_to v s) (C29_ref.of_regval v) else + if reg_name = "UART_RVALID" then OPTION_MAP (\ v . UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else + if reg_name = "UART_RDATA" then OPTION_MAP (\ v . UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else + if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v . UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else + if reg_name = "UART_WDATA" then OPTION_MAP (\ v . UART_WDATA_ref.write_to v s) (UART_WDATA_ref.of_regval v) else + if reg_name = "GPR" then OPTION_MAP (\ v . GPR_ref.write_to v s) (GPR_ref.of_regval v) else + if reg_name = "LO" then OPTION_MAP (\ v . LO_ref.write_to v s) (LO_ref.of_regval v) else + if reg_name = "HI" then OPTION_MAP (\ v . HI_ref.write_to v s) (HI_ref.of_regval v) else + if reg_name = "delayedPC" then OPTION_MAP (\ v . delayedPC_ref.write_to v s) (delayedPC_ref.of_regval v) else + if reg_name = "inBranchDelay" then OPTION_MAP (\ v . inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else + if reg_name = "branchPending" then OPTION_MAP (\ v . branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else + if reg_name = "CP0Status" then OPTION_MAP (\ v . CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else + if reg_name = "CP0UserLocal" then OPTION_MAP (\ v . CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else + if reg_name = "CP0HWREna" then OPTION_MAP (\ v . CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else + if reg_name = "CP0Count" then OPTION_MAP (\ v . CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else + if reg_name = "CP0BadVAddr" then OPTION_MAP (\ v . CP0BadVAddr_ref.write_to v s) (CP0BadVAddr_ref.of_regval v) else + if reg_name = "CP0LLAddr" then OPTION_MAP (\ v . CP0LLAddr_ref.write_to v s) (CP0LLAddr_ref.of_regval v) else + if reg_name = "CP0LLBit" then OPTION_MAP (\ v . CP0LLBit_ref.write_to v s) (CP0LLBit_ref.of_regval v) else + if reg_name = "CP0ErrorEPC" then OPTION_MAP (\ v . CP0ErrorEPC_ref.write_to v s) (CP0ErrorEPC_ref.of_regval v) else + if reg_name = "CP0EPC" then OPTION_MAP (\ v . CP0EPC_ref.write_to v s) (CP0EPC_ref.of_regval v) else + if reg_name = "CP0Cause" then OPTION_MAP (\ v . CP0Cause_ref.write_to v s) (CP0Cause_ref.of_regval v) else + if reg_name = "CP0Compare" then OPTION_MAP (\ v . CP0Compare_ref.write_to v s) (CP0Compare_ref.of_regval v) else + if reg_name = "TLBEntry63" then OPTION_MAP (\ v . TLBEntry63_ref.write_to v s) (TLBEntry63_ref.of_regval v) else + if reg_name = "TLBEntry62" then OPTION_MAP (\ v . TLBEntry62_ref.write_to v s) (TLBEntry62_ref.of_regval v) else + if reg_name = "TLBEntry61" then OPTION_MAP (\ v . TLBEntry61_ref.write_to v s) (TLBEntry61_ref.of_regval v) else + if reg_name = "TLBEntry60" then OPTION_MAP (\ v . TLBEntry60_ref.write_to v s) (TLBEntry60_ref.of_regval v) else + if reg_name = "TLBEntry59" then OPTION_MAP (\ v . TLBEntry59_ref.write_to v s) (TLBEntry59_ref.of_regval v) else + if reg_name = "TLBEntry58" then OPTION_MAP (\ v . TLBEntry58_ref.write_to v s) (TLBEntry58_ref.of_regval v) else + if reg_name = "TLBEntry57" then OPTION_MAP (\ v . TLBEntry57_ref.write_to v s) (TLBEntry57_ref.of_regval v) else + if reg_name = "TLBEntry56" then OPTION_MAP (\ v . TLBEntry56_ref.write_to v s) (TLBEntry56_ref.of_regval v) else + if reg_name = "TLBEntry55" then OPTION_MAP (\ v . TLBEntry55_ref.write_to v s) (TLBEntry55_ref.of_regval v) else + if reg_name = "TLBEntry54" then OPTION_MAP (\ v . TLBEntry54_ref.write_to v s) (TLBEntry54_ref.of_regval v) else + if reg_name = "TLBEntry53" then OPTION_MAP (\ v . TLBEntry53_ref.write_to v s) (TLBEntry53_ref.of_regval v) else + if reg_name = "TLBEntry52" then OPTION_MAP (\ v . TLBEntry52_ref.write_to v s) (TLBEntry52_ref.of_regval v) else + if reg_name = "TLBEntry51" then OPTION_MAP (\ v . TLBEntry51_ref.write_to v s) (TLBEntry51_ref.of_regval v) else + if reg_name = "TLBEntry50" then OPTION_MAP (\ v . TLBEntry50_ref.write_to v s) (TLBEntry50_ref.of_regval v) else + if reg_name = "TLBEntry49" then OPTION_MAP (\ v . TLBEntry49_ref.write_to v s) (TLBEntry49_ref.of_regval v) else + if reg_name = "TLBEntry48" then OPTION_MAP (\ v . TLBEntry48_ref.write_to v s) (TLBEntry48_ref.of_regval v) else + if reg_name = "TLBEntry47" then OPTION_MAP (\ v . TLBEntry47_ref.write_to v s) (TLBEntry47_ref.of_regval v) else + if reg_name = "TLBEntry46" then OPTION_MAP (\ v . TLBEntry46_ref.write_to v s) (TLBEntry46_ref.of_regval v) else + if reg_name = "TLBEntry45" then OPTION_MAP (\ v . TLBEntry45_ref.write_to v s) (TLBEntry45_ref.of_regval v) else + if reg_name = "TLBEntry44" then OPTION_MAP (\ v . TLBEntry44_ref.write_to v s) (TLBEntry44_ref.of_regval v) else + if reg_name = "TLBEntry43" then OPTION_MAP (\ v . TLBEntry43_ref.write_to v s) (TLBEntry43_ref.of_regval v) else + if reg_name = "TLBEntry42" then OPTION_MAP (\ v . TLBEntry42_ref.write_to v s) (TLBEntry42_ref.of_regval v) else + if reg_name = "TLBEntry41" then OPTION_MAP (\ v . TLBEntry41_ref.write_to v s) (TLBEntry41_ref.of_regval v) else + if reg_name = "TLBEntry40" then OPTION_MAP (\ v . TLBEntry40_ref.write_to v s) (TLBEntry40_ref.of_regval v) else + if reg_name = "TLBEntry39" then OPTION_MAP (\ v . TLBEntry39_ref.write_to v s) (TLBEntry39_ref.of_regval v) else + if reg_name = "TLBEntry38" then OPTION_MAP (\ v . TLBEntry38_ref.write_to v s) (TLBEntry38_ref.of_regval v) else + if reg_name = "TLBEntry37" then OPTION_MAP (\ v . TLBEntry37_ref.write_to v s) (TLBEntry37_ref.of_regval v) else + if reg_name = "TLBEntry36" then OPTION_MAP (\ v . TLBEntry36_ref.write_to v s) (TLBEntry36_ref.of_regval v) else + if reg_name = "TLBEntry35" then OPTION_MAP (\ v . TLBEntry35_ref.write_to v s) (TLBEntry35_ref.of_regval v) else + if reg_name = "TLBEntry34" then OPTION_MAP (\ v . TLBEntry34_ref.write_to v s) (TLBEntry34_ref.of_regval v) else + if reg_name = "TLBEntry33" then OPTION_MAP (\ v . TLBEntry33_ref.write_to v s) (TLBEntry33_ref.of_regval v) else + if reg_name = "TLBEntry32" then OPTION_MAP (\ v . TLBEntry32_ref.write_to v s) (TLBEntry32_ref.of_regval v) else + if reg_name = "TLBEntry31" then OPTION_MAP (\ v . TLBEntry31_ref.write_to v s) (TLBEntry31_ref.of_regval v) else + if reg_name = "TLBEntry30" then OPTION_MAP (\ v . TLBEntry30_ref.write_to v s) (TLBEntry30_ref.of_regval v) else + if reg_name = "TLBEntry29" then OPTION_MAP (\ v . TLBEntry29_ref.write_to v s) (TLBEntry29_ref.of_regval v) else + if reg_name = "TLBEntry28" then OPTION_MAP (\ v . TLBEntry28_ref.write_to v s) (TLBEntry28_ref.of_regval v) else + if reg_name = "TLBEntry27" then OPTION_MAP (\ v . TLBEntry27_ref.write_to v s) (TLBEntry27_ref.of_regval v) else + if reg_name = "TLBEntry26" then OPTION_MAP (\ v . TLBEntry26_ref.write_to v s) (TLBEntry26_ref.of_regval v) else + if reg_name = "TLBEntry25" then OPTION_MAP (\ v . TLBEntry25_ref.write_to v s) (TLBEntry25_ref.of_regval v) else + if reg_name = "TLBEntry24" then OPTION_MAP (\ v . TLBEntry24_ref.write_to v s) (TLBEntry24_ref.of_regval v) else + if reg_name = "TLBEntry23" then OPTION_MAP (\ v . TLBEntry23_ref.write_to v s) (TLBEntry23_ref.of_regval v) else + if reg_name = "TLBEntry22" then OPTION_MAP (\ v . TLBEntry22_ref.write_to v s) (TLBEntry22_ref.of_regval v) else + if reg_name = "TLBEntry21" then OPTION_MAP (\ v . TLBEntry21_ref.write_to v s) (TLBEntry21_ref.of_regval v) else + if reg_name = "TLBEntry20" then OPTION_MAP (\ v . TLBEntry20_ref.write_to v s) (TLBEntry20_ref.of_regval v) else + if reg_name = "TLBEntry19" then OPTION_MAP (\ v . TLBEntry19_ref.write_to v s) (TLBEntry19_ref.of_regval v) else + if reg_name = "TLBEntry18" then OPTION_MAP (\ v . TLBEntry18_ref.write_to v s) (TLBEntry18_ref.of_regval v) else + if reg_name = "TLBEntry17" then OPTION_MAP (\ v . TLBEntry17_ref.write_to v s) (TLBEntry17_ref.of_regval v) else + if reg_name = "TLBEntry16" then OPTION_MAP (\ v . TLBEntry16_ref.write_to v s) (TLBEntry16_ref.of_regval v) else + if reg_name = "TLBEntry15" then OPTION_MAP (\ v . TLBEntry15_ref.write_to v s) (TLBEntry15_ref.of_regval v) else + if reg_name = "TLBEntry14" then OPTION_MAP (\ v . TLBEntry14_ref.write_to v s) (TLBEntry14_ref.of_regval v) else + if reg_name = "TLBEntry13" then OPTION_MAP (\ v . TLBEntry13_ref.write_to v s) (TLBEntry13_ref.of_regval v) else + if reg_name = "TLBEntry12" then OPTION_MAP (\ v . TLBEntry12_ref.write_to v s) (TLBEntry12_ref.of_regval v) else + if reg_name = "TLBEntry11" then OPTION_MAP (\ v . TLBEntry11_ref.write_to v s) (TLBEntry11_ref.of_regval v) else + if reg_name = "TLBEntry10" then OPTION_MAP (\ v . TLBEntry10_ref.write_to v s) (TLBEntry10_ref.of_regval v) else + if reg_name = "TLBEntry09" then OPTION_MAP (\ v . TLBEntry09_ref.write_to v s) (TLBEntry09_ref.of_regval v) else + if reg_name = "TLBEntry08" then OPTION_MAP (\ v . TLBEntry08_ref.write_to v s) (TLBEntry08_ref.of_regval v) else + if reg_name = "TLBEntry07" then OPTION_MAP (\ v . TLBEntry07_ref.write_to v s) (TLBEntry07_ref.of_regval v) else + if reg_name = "TLBEntry06" then OPTION_MAP (\ v . TLBEntry06_ref.write_to v s) (TLBEntry06_ref.of_regval v) else + if reg_name = "TLBEntry05" then OPTION_MAP (\ v . TLBEntry05_ref.write_to v s) (TLBEntry05_ref.of_regval v) else + if reg_name = "TLBEntry04" then OPTION_MAP (\ v . TLBEntry04_ref.write_to v s) (TLBEntry04_ref.of_regval v) else + if reg_name = "TLBEntry03" then OPTION_MAP (\ v . TLBEntry03_ref.write_to v s) (TLBEntry03_ref.of_regval v) else + if reg_name = "TLBEntry02" then OPTION_MAP (\ v . TLBEntry02_ref.write_to v s) (TLBEntry02_ref.of_regval v) else + if reg_name = "TLBEntry01" then OPTION_MAP (\ v . TLBEntry01_ref.write_to v s) (TLBEntry01_ref.of_regval v) else + if reg_name = "TLBEntry00" then OPTION_MAP (\ v . TLBEntry00_ref.write_to v s) (TLBEntry00_ref.of_regval v) else + if reg_name = "TLBXContext" then OPTION_MAP (\ v . TLBXContext_ref.write_to v s) (TLBXContext_ref.of_regval v) else + if reg_name = "TLBEntryHi" then OPTION_MAP (\ v . TLBEntryHi_ref.write_to v s) (TLBEntryHi_ref.of_regval v) else + if reg_name = "TLBWired" then OPTION_MAP (\ v . TLBWired_ref.write_to v s) (TLBWired_ref.of_regval v) else + if reg_name = "TLBPageMask" then OPTION_MAP (\ v . TLBPageMask_ref.write_to v s) (TLBPageMask_ref.of_regval v) else + if reg_name = "TLBContext" then OPTION_MAP (\ v . TLBContext_ref.write_to v s) (TLBContext_ref.of_regval v) else + if reg_name = "TLBEntryLo1" then OPTION_MAP (\ v . TLBEntryLo1_ref.write_to v s) (TLBEntryLo1_ref.of_regval v) else + if reg_name = "TLBEntryLo0" then OPTION_MAP (\ v . TLBEntryLo0_ref.write_to v s) (TLBEntryLo0_ref.of_regval v) else + if reg_name = "TLBRandom" then OPTION_MAP (\ v . TLBRandom_ref.write_to v s) (TLBRandom_ref.of_regval v) else + if reg_name = "TLBIndex" then OPTION_MAP (\ v . TLBIndex_ref.write_to v s) (TLBIndex_ref.of_regval v) else + if reg_name = "TLBProbe" then OPTION_MAP (\ v . TLBProbe_ref.write_to v s) (TLBProbe_ref.of_regval v) else + if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else + if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else + NONE))`; + + +val _ = Define ` + ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`; + + + +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``); +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml b/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml new file mode 100644 index 00000000..26c1d0a7 --- /dev/null +++ b/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml @@ -0,0 +1,235 @@ +(*Generated by Lem from /home/bcampbe2/local/rems/github/sail/mips/mips_extras_sequential.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory state_monadTheory stateTheory sail_operatorsTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "mips_extras_sequential" + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import State_monad*) +(*open import State*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*) + +val _ = Define ` + ((MEMr:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`; + +val _ = Define ` + ((MEMr_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`; + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> State_monad.monadS 'regval bool 'e*) +val _ = Define ` + ((read_tag_bool:'a sail_values$Bitvector_class -> 'a ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr= (bindS +(read_tagS dict_Sail_values_Bitvector_a addr) (\ t . + maybe_failS "read_tag_bool" (bool_of_bitU t))))`; + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> State_monad.monadS 'regval unit 'e*) +val _ = Define ` + ((write_tag_bool:'a sail_values$Bitvector_class -> 'a -> bool ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr t= (bindS (write_tagS + dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) + (\b . (case (b ) of ( _ ) => returnS () ))))`; + + +val _ = Define ` + ((MEMr_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (bindS +(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . bindS +(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . + returnS (t, v)))))`; + + +val _ = Define ` + ((MEMr_tag_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (bindS +(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . bindS +(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . + returnS (t, v)))))`; + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) + +val _ = Define ` + ((MEMea:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS + dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS + dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + +val _ = Define ` + ((MEMea_tag:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS + dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_tag_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS + dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval bool 'e*) + +val _ = Define ` + ((MEMval:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (bindS (write_mem_valS + dict_Sail_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => returnS () ))))`; + +val _ = Define ` + ((MEMval_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (bindS (write_mem_valS + dict_Sail_values_Bitvector_b v) (\ b . returnS (if b then T else F))))`; + +val _ = Define ` + ((MEMval_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (bindS (write_mem_valS + dict_Sail_values_Bitvector_b v) (\b . (case (b ) of + ( _ ) => bindS + (write_tag_bool dict_Sail_values_Bitvector_a addr t) + (\u . (case (u ) of ( _ ) => returnS () )) + ))))`; + +val _ = Define ` + ((MEMval_tag_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (bindS (write_mem_valS + dict_Sail_values_Bitvector_b v) (\ b . bindS (write_tag_bool + dict_Sail_values_Bitvector_a addr t) (\u . (case (u ) of ( _ ) => returnS (if b then T else F) )))))`; + + +(*val MEM_sync : forall 'regval 'e. unit -> State_monad.monadS 'regval unit 'e*) + +val _ = Define ` + ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () = (returnS () ))`; + (*barrier Barrier_MIPS_SYNC*) + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +val _ = Define ` + ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo= +( + (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in + let bs = (bools_of_int (hi +( 1 : int)) n) in + subrange_list F bs hi lo))`; + + +(*val get_slice_int : forall 'a. Bitvector 'a => Num.integer -> Num.integer -> Num.integer -> 'a*) +val _ = Define ` + ((get_slice_int:'a sail_values$Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= ( + dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; + + +val _ = Define ` + ((write_ram:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data= (seqS +(MEMea dict_Sail_values_Bitvector_b addr size1) +(MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`; + + +val _ = Define ` + ((read_ram:'a sail_values$Bitvector_class -> 'c sail_values$Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr= (MEMr + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`; + + +val _ = Define ` + ((string_of_bits:'a sail_values$Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs= (string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`; + +val _ = Define ` + ((string_of_int:'a lem_show$Show_class -> 'a -> string)dict_Show_Show_a= + (dict_Show_Show_a.show_method))`; + + +val _ = Define ` + ((sign_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( + dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`; + +val _ = Define ` + ((zero_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( + dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`; + + +val _ = Define ` + ((shift_bits_left:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + maybe_failS "shift_bits_left" r))`; + +val _ = Define ` + ((shift_bits_right:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_failS "shift_bits_right" r))`; + +val _ = Define ` + ((shift_bits_right_arith:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_failS "shift_bits_right_arith" r))`; + + +(* Use constants for undefined values for now *) +val _ = Define ` + ((internal_pick:'a list -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) vs= (returnS (HD vs)))`; + +val _ = Define ` + ((undefined_bool0:unit ->('c,(bool),'a)state_monad$monadS)= undefined_boolS)`; + +val _ = Define ` + ((undefined_string:unit -> 'b state_monad$sequential_state ->(((string),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS ""))`; + +val _ = Define ` + ((undefined_unit:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS () ))`; + +val _ = Define ` + ((undefined_int:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (( 0 : int):sail_values$ii)))`; + +(*val undefined_vector : forall 'rv 'a 'e. Num.integer -> 'a -> State_monad.monadS 'rv (list 'a) 'e*) +val _ = Define ` + ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u= (returnS (repeat [u] len)))`; + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*) +val _ = Define ` + ((undefined_bitvector:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a len= (returnS ( + dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`; + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*) +val _ = Define ` + ((undefined_bits:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a= + (undefined_bitvector dict_Sail_values_Bitvector_a))`; + +val _ = Define ` + ((undefined_bit:unit -> 'b state_monad$sequential_state ->(((sail_values$bitU),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS B0))`; + +val _ = Define ` + ((undefined_real:unit -> 'b state_monad$sequential_state ->(((real),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; + +val _ = Define ` + ((undefined_range:'a -> 'd -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i j= (returnS i))`; + +val _ = Define ` + ((undefined_atom:'a -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i= (returnS i))`; + +val _ = Define ` + ((undefined_nat:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (( 0 : int):sail_values$ii)))`; + + +val _ = Define ` + ((skip:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS () ))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile new file mode 100644 index 00000000..45ed41ff --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/Holmakefile @@ -0,0 +1,27 @@ +SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \ + sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \ + state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml + +EXTRA_CLEANS = $(SCRIPTS) + +THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS)) + +LEMDIR=../../../lem/hol-lib + +INCLUDES = $(LEMDIR) + +all: $(THYS) +.PHONY: all + +ifdef POLY +HOLHEAP = sail-heap +EXTRA_CLEANS = $(SCRIPTS) $(HOLHEAP) $(HOLHEAP).o + +BASE_HEAP = $(LEMDIR)/lemheap + +$(HOLHEAP): + $(protect $(HOLDIR)/bin/buildheap) -o $(HOLHEAP) -b $(BASE_HEAP) + +all: $(HOLHEAP) + +endif diff --git a/snapshots/hol4/sail/riscv/Holmakefile b/snapshots/hol4/sail/riscv/Holmakefile new file mode 100644 index 00000000..626e6f2f --- /dev/null +++ b/snapshots/hol4/sail/riscv/Holmakefile @@ -0,0 +1,11 @@ +LEMDIR=../../lem/hol-lib + +INCLUDES = $(LEMDIR) ../lib/hol + +all: riscv_sequentialTheory.uo +.PHONY: all + +ifdef POLY +BASE_HEAP = ../lib/hol/sail-heap + +endif diff --git a/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml new file mode 100644 index 00000000..541bc1d3 --- /dev/null +++ b/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml @@ -0,0 +1,127 @@ +(*Generated by Lem from riscv_extras_sequential.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "riscv_extras_sequential" + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import State_monad*) +(*open import State*) + +val _ = type_abbrev((* 'a *) "bitvector" , ``: 'a words$word``); + +(*val barrierS : forall 'rv 'e. Sail_instr_kinds.barrier_kind -> State_monad.monadS 'rv unit 'e*) +val _ = Define ` + ((barrierS:sail_instr_kinds$barrier_kind -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) _= (returnS () ))`; + + +val _ = Define ` + ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_rw_rw))`; + +val _ = Define ` + ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_r_rw))`; + +val _ = Define ` + ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_r_r))`; + +val _ = Define ` + ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_rw_w))`; + +val _ = Define ` + ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_w_w))`; + +val _ = Define ` + ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_i))`; + + +(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) + +val _ = Define ` + ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= +(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`; + + +(*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> State_monad.monadS 'rv unit 'e*) +val _ = Define ` + ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value= (bindS (seqS +(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1)) +(write_mem_valS instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b . (case (b ) of ( _ ) => returnS () ))))`; + + +(*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> State_monad.monadS 'rv (bitvector 'b) 'e*) +val _ = Define ` + ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address= + (read_memS instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; + + +val _ = Define ` + ((speculate_conditional_success:unit -> 'b state_monad$sequential_state ->(((bool),'a)state_monad$result#'b state_monad$sequential_state)set) () = (excl_resultS () ))`; + + +(*val get_slice_int : forall 'a. Size 'a => Num.integer -> Num.integer -> Num.integer -> bitvector 'a*) +val _ = Define ` + ((get_slice_int:int -> int -> int -> 'a words$word) len n lo= +( + (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in + let bits = (bits_of_int (hi +( 1 : int)) n) in + of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list F bits hi lo)))`; + + +(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +val _ = Define ` + ((shift_bits_right:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftr v (lem$w2ui m)))`; + +(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +val _ = Define ` + ((shift_bits_left:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftl v (lem$w2ui m)))`; + + +(*val print_string : string -> string -> unit*) +val _ = Define ` + ((print_string:string -> string -> unit) msg s= (prerr_endline ( STRCAT msg s)))`; + + +(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) +val _ = Define ` + ((print_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`; + + +val _ = Define ` + ((reg_deref0:('d,'c,'b)sail_values$register_ref ->('d,'b,'a)state_monad$monadS)= read_regS)`; +val _ = export_theory() + diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml b/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml new file mode 100644 index 00000000..463da979 --- /dev/null +++ b/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml @@ -0,0 +1,41 @@ +(*Generated by Lem from riscv_sequential.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory riscv_sequentialTheory; + +val _ = numLib.prefer_num(); + + + +open lemLib; +(* val _ = lemLib.run_interactive := true; *) +val _ = new_theory "riscv_sequentialAuxiliary" + + +(****************************************************) +(* *) +(* Termination Proofs *) +(* *) +(****************************************************) + +(* val gst = Defn.tgoal_no_defn (walk39_def, walk39_ind) *) +val (walk39_rw, walk39_ind_rw) = + Defn.tprove_no_defn ((walk39_def, walk39_ind), + cheat (* the termination proof *) + ) +val walk39_rw = save_thm ("walk39_rw", walk39_rw); +val walk39_ind_rw = save_thm ("walk39_ind_rw", walk39_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (execute_def, execute_ind) *) +val (execute_rw, execute_ind_rw) = + Defn.tprove_no_defn ((execute_def, execute_ind), + cheat (* the termination proof *) + ) +val execute_rw = save_thm ("execute_rw", execute_rw); +val execute_ind_rw = save_thm ("execute_ind_rw", execute_ind_rw); + + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml new file mode 100644 index 00000000..22d8e899 --- /dev/null +++ b/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml @@ -0,0 +1,7554 @@ +(*Generated by Lem from riscv_sequential.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "riscv_sequential" + +(*Generated by Sail from riscv_sequential.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import State_monad*) +(*open import State*) +(*open import Riscv_sequential_types*) +(*open import Riscv_extras_sequential*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*) + + + +(*val builtin_or_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. Num.integer -> Sail_values.ii -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Sail_values.ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*) + +val _ = Define ` + ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1= ((get_slice_int n m o1 : 'n words$word)))`; + + +(*val __raw_SetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Riscv_sequential_types.bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w*) + +(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val DecStr : Sail_values.ii -> string*) + +(*val HexStr : Sail_values.ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (seqS +(write_ram (( 64 : int):sail_values$ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) addr data) +(returnS T)))`; + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Maybe.maybe (Machine_word.mword 'int8_times_n))*) + +val _ = Define ` + ((RISCV_read:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= (bindS + (read_ram (( 64 : int):sail_values$ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) riscv_sequential_types$M) (\ (w__0 : 'int8_times_n words$word) . + returnS (SOME w__0))))`; + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*) + +(*val ex_nat : Sail_values.ii -> Num.integer*) + +val _ = Define ` + ((ex_nat:int -> int) n= n)`; + + +(*val ex_int : Sail_values.ii -> Num.integer*) + +val _ = Define ` + ((ex_int:int -> int) n= n)`; + + +(*val coerce_int_nat : Sail_values.ii -> Riscv_sequential_types.M Sail_values.ii*) + +val _ = Define ` + ((coerce_int_nat:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((int),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) x= (seqS (assert_expS T "") (returnS x)))`; + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) + +val _ = Define ` + ((EXTS:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend v m__tv : 'm words$word)))`; + + +val _ = Define ` + ((EXTZ:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend v m__tv : 'm words$word)))`; + + + + + + + + + + + + +(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val bit_to_bool : Sail_values.bitU -> bool*) + +val _ = Define ` + ((bit_to_bool:sail_values$bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; + + +(*val vector64 : Sail_values.ii -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((vector64:int ->(64)words$word) n= ((get_slice_int (( 64 : int):sail_values$ii) n (( 0 : int):sail_values$ii) : 64 words$word)))`; + + +(*val to_bits : forall 'l. Size 'l => Num.integer -> Sail_values.ii -> Machine_word.mword 'l*) + +val _ = Define ` + ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int l n (( 0 : int):sail_values$ii) : 'l words$word)))`; + + +(*val shift_right_arith64 : Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 riscv_sequential_types$bits) (shift : 6 riscv_sequential_types$bits)= + (let (v128 : 128 riscv_sequential_types$bits) = ((EXTS (( 128 : int):sail_values$ii) v : 128 words$word)) in + (subrange_vec_dec ((shift_bits_right v128 shift : 128 words$word)) (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))`; + + +(*val shift_right_arith32 : Machine_word.mword Machine_word.ty32 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty32*) + +val _ = Define ` + ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 riscv_sequential_types$bits) (shift : 5 riscv_sequential_types$bits)= + (let (v64 : 64 riscv_sequential_types$bits) = ((EXTS (( 64 : int):sail_values$ii) v : 64 words$word)) in + (subrange_vec_dec ((shift_bits_right v64 shift : 64 words$word)) (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)))`; + + +val _ = Define ` + ((xlen:int)= ((( 64 : int):sail_values$ii)))`; + + +val _ = Define ` + ((xlen_max_unsigned:int)= (((pow2 xlen)) - (( 1 : int):sail_values$ii)))`; + + +val _ = Define ` + ((xlen_max_signed:int)= (((pow2 ((xlen - (( 1 : int):sail_values$ii))))) - (( 1 : int):sail_values$ii)))`; + + +val _ = Define ` + ((xlen_min_signed:int)= ((( 0 : int):sail_values$ii) - ((pow2 ((xlen - (( 1 : int):sail_values$ii)))))))`; + + +(*val regbits_to_regno : Machine_word.mword Machine_word.ty5 -> Num.integer*) + +val _ = Define ` + ((regbits_to_regno:(5)words$word -> int) b= + (let r = (lem$w2ui b) in + r))`; + + +(*val creg2reg_bits : Machine_word.mword Machine_word.ty3 -> Machine_word.mword Machine_word.ty5*) + +val _ = Define ` + ((creg2reg_bits:(3)words$word ->(5)words$word) creg= ((concat_vec (vec_of_bits [B0;B1] : 2 words$word) creg : 5 words$word)))`; + + +val _ = Define ` +((zreg:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((ra:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))`; + + +val _ = Define ` +((sp:(5)words$word)= ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))`; + + +(*val rX : Num.integer -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((rX:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) l__81= + (if (((l__81 = (( 0 : int):sail_values$ii)))) then + returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word) + else bindS +(read_regS Xs_ref) (\ (w__0 : riscv_sequential_types$xlenbits list) . + returnS ((access_list_dec w__0 l__81 : 64 words$word)))))`; + + +(*val wX : Num.integer -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((wX:int ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r v= + (if (((r <> (( 0 : int):sail_values$ii)))) then bindS +(read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) . seqS +(write_regS Xs_ref ((update_list_dec w__0 r v : ( 64 words$word) list))) +(returnS ((prerr_endline + ((STRCAT "x" + ((STRCAT ((stringFromInteger r)) + ((STRCAT " <- " ((string_of_vec v)))))))))))) + else returnS () ))`; + + +(*val reg_name_abi : Machine_word.mword Machine_word.ty5 -> string*) + +val _ = Define ` + ((reg_name_abi:(5)words$word -> string) r= + (let b__0 = r in + if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then + "zero" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then + "ra" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then + "sp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then + "gp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + "tp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then + "t0" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then + "t1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then + "t2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + "fp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then + "s1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then + "a0" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then + "a1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + "a2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then + "a3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then + "a4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then + "a5" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + "a6" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then + "a7" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then + "s2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then + "s3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + "s4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then + "s5" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then + "s6" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then + "s7" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + "s8" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then + "s9" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then + "s10" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then + "s11" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then + "t3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then + "t4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then + "t5" + else "t6"))`; + + +(*val Architecture_of_num : Num.integer -> Riscv_sequential_types.Architecture*) + +val _ = Define ` + ((Architecture_of_num:int -> riscv_sequential_types$Architecture) arg_= + (let l__79 = arg_ in + if (((l__79 = (( 0 : int):sail_values$ii)))) then RV32 + else if (((l__79 = (( 1 : int):sail_values$ii)))) then RV64 + else RV128))`; + + +(*val num_of_Architecture : Riscv_sequential_types.Architecture -> Num.integer*) + +val _ = Define ` + ((num_of_Architecture:riscv_sequential_types$Architecture -> int) arg_= + ((case arg_ of RV32 => (( 0 : int):sail_values$ii) | RV64 => (( 1 : int):sail_values$ii) | RV128 => (( 2 : int):sail_values$ii) )))`; + + +(*val architecture : Machine_word.mword Machine_word.ty2 -> Maybe.maybe Riscv_sequential_types.Architecture*) + +val _ = Define ` + ((architecture:(2)words$word ->(riscv_sequential_types$Architecture)option) a= + (let b__0 = a in + if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then SOME RV32 + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then SOME RV64 + else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then SOME RV128 + else NONE))`; + + +(*val arch_to_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((arch_to_bits:riscv_sequential_types$Architecture ->(2)words$word) a= + ((case a of + RV32 => (vec_of_bits [B0;B1] : 2 words$word) + | RV64 => (vec_of_bits [B1;B0] : 2 words$word) + | RV128 => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val Privilege_of_num : Num.integer -> Riscv_sequential_types.Privilege*) + +val _ = Define ` + ((Privilege_of_num:int -> riscv_sequential_types$Privilege) arg_= + (let l__77 = arg_ in + if (((l__77 = (( 0 : int):sail_values$ii)))) then User + else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor + else Machine))`; + + +(*val num_of_Privilege : Riscv_sequential_types.Privilege -> Num.integer*) + +val _ = Define ` + ((num_of_Privilege:riscv_sequential_types$Privilege -> int) arg_= + ((case arg_ of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Machine => (( 2 : int):sail_values$ii) )))`; + + +(*val privLevel_to_bits : Riscv_sequential_types.Privilege -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((privLevel_to_bits:riscv_sequential_types$Privilege ->(2)words$word) p= + ((case p of + User => (vec_of_bits [B0;B0] : 2 words$word) + | Supervisor => (vec_of_bits [B0;B1] : 2 words$word) + | Machine => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val privLevel_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege*) + +val _ = Define ` + ((privLevel_of_bits:(2)words$word -> riscv_sequential_types$Privilege) p= + (let b__0 = p in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then User + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor + else Machine))`; + + +(*val privLevel_to_str : Riscv_sequential_types.Privilege -> string*) + +val _ = Define ` + ((privLevel_to_str:riscv_sequential_types$Privilege -> string) p= ((case p of User => "U" | Supervisor => "S" | Machine => "M" )))`; + + +(*val AccessType_of_num : Num.integer -> Riscv_sequential_types.AccessType*) + +val _ = Define ` + ((AccessType_of_num:int -> riscv_sequential_types$AccessType) arg_= + (let l__74 = arg_ in + if (((l__74 = (( 0 : int):sail_values$ii)))) then Read + else if (((l__74 = (( 1 : int):sail_values$ii)))) then Write + else if (((l__74 = (( 2 : int):sail_values$ii)))) then ReadWrite + else Execute))`; + + +(*val num_of_AccessType : Riscv_sequential_types.AccessType -> Num.integer*) + +val _ = Define ` + ((num_of_AccessType:riscv_sequential_types$AccessType -> int) arg_= + ((case arg_ of Read => (( 0 : int):sail_values$ii) | Write => (( 1 : int):sail_values$ii) | ReadWrite => (( 2 : int):sail_values$ii) | Execute => (( 3 : int):sail_values$ii) )))`; + + +(*val ReadType_of_num : Num.integer -> Riscv_sequential_types.ReadType*) + +val _ = Define ` + ((ReadType_of_num:int -> riscv_sequential_types$ReadType) arg_= + (let l__73 = arg_ in + if (((l__73 = (( 0 : int):sail_values$ii)))) then Instruction + else Data))`; + + +(*val num_of_ReadType : Riscv_sequential_types.ReadType -> Num.integer*) + +val _ = Define ` + ((num_of_ReadType:riscv_sequential_types$ReadType -> int) arg_= ((case arg_ of Instruction => (( 0 : int):sail_values$ii) | Data => (( 1 : int):sail_values$ii) )))`; + + +(*val ExceptionType_of_num : Num.integer -> Riscv_sequential_types.ExceptionType*) + +val _ = Define ` + ((ExceptionType_of_num:int -> riscv_sequential_types$ExceptionType) arg_= + (let l__58 = arg_ in + if (((l__58 = (( 0 : int):sail_values$ii)))) then E_Fetch_Addr_Align + else if (((l__58 = (( 1 : int):sail_values$ii)))) then E_Fetch_Access_Fault + else if (((l__58 = (( 2 : int):sail_values$ii)))) then E_Illegal_Instr + else if (((l__58 = (( 3 : int):sail_values$ii)))) then E_Breakpoint + else if (((l__58 = (( 4 : int):sail_values$ii)))) then E_Load_Addr_Align + else if (((l__58 = (( 5 : int):sail_values$ii)))) then E_Load_Access_Fault + else if (((l__58 = (( 6 : int):sail_values$ii)))) then E_SAMO_Addr_Align + else if (((l__58 = (( 7 : int):sail_values$ii)))) then E_SAMO_Access_Fault + else if (((l__58 = (( 8 : int):sail_values$ii)))) then E_U_EnvCall + else if (((l__58 = (( 9 : int):sail_values$ii)))) then E_S_EnvCall + else if (((l__58 = (( 10 : int):sail_values$ii)))) then E_Reserved_10 + else if (((l__58 = (( 11 : int):sail_values$ii)))) then E_M_EnvCall + else if (((l__58 = (( 12 : int):sail_values$ii)))) then E_Fetch_Page_Fault + else if (((l__58 = (( 13 : int):sail_values$ii)))) then E_Load_Page_Fault + else if (((l__58 = (( 14 : int):sail_values$ii)))) then E_Reserved_14 + else E_SAMO_Page_Fault))`; + + +(*val num_of_ExceptionType : Riscv_sequential_types.ExceptionType -> Num.integer*) + +val _ = Define ` + ((num_of_ExceptionType:riscv_sequential_types$ExceptionType -> int) arg_= + ((case arg_ of + E_Fetch_Addr_Align => (( 0 : int):sail_values$ii) + | E_Fetch_Access_Fault => (( 1 : int):sail_values$ii) + | E_Illegal_Instr => (( 2 : int):sail_values$ii) + | E_Breakpoint => (( 3 : int):sail_values$ii) + | E_Load_Addr_Align => (( 4 : int):sail_values$ii) + | E_Load_Access_Fault => (( 5 : int):sail_values$ii) + | E_SAMO_Addr_Align => (( 6 : int):sail_values$ii) + | E_SAMO_Access_Fault => (( 7 : int):sail_values$ii) + | E_U_EnvCall => (( 8 : int):sail_values$ii) + | E_S_EnvCall => (( 9 : int):sail_values$ii) + | E_Reserved_10 => (( 10 : int):sail_values$ii) + | E_M_EnvCall => (( 11 : int):sail_values$ii) + | E_Fetch_Page_Fault => (( 12 : int):sail_values$ii) + | E_Load_Page_Fault => (( 13 : int):sail_values$ii) + | E_Reserved_14 => (( 14 : int):sail_values$ii) + | E_SAMO_Page_Fault => (( 15 : int):sail_values$ii) + )))`; + + +(*val exceptionType_to_bits : Riscv_sequential_types.ExceptionType -> Machine_word.mword Machine_word.ty4*) + +val _ = Define ` + ((exceptionType_to_bits:riscv_sequential_types$ExceptionType ->(4)words$word) e= + ((case e of + E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : 4 words$word) + | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : 4 words$word) + | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : 4 words$word) + | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : 4 words$word) + | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : 4 words$word) + | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : 4 words$word) + )))`; + + +(*val exceptionType_to_str : Riscv_sequential_types.ExceptionType -> string*) + +val _ = Define ` + ((exceptionType_to_str:riscv_sequential_types$ExceptionType -> string) e= + ((case e of + E_Fetch_Addr_Align => "fisaligned-fetch" + | E_Fetch_Access_Fault => "fetch-access-fault" + | E_Illegal_Instr => "illegal-instruction" + | E_Breakpoint => "breakpoint" + | E_Load_Addr_Align => "misaligned-load" + | E_Load_Access_Fault => "load-access-fault" + | E_SAMO_Addr_Align => "misaliged-store/amo" + | E_SAMO_Access_Fault => "store/amo-access-fault" + | E_U_EnvCall => "u-call" + | E_S_EnvCall => "s-call" + | E_Reserved_10 => "reserved-0" + | E_M_EnvCall => "m-call" + | E_Fetch_Page_Fault => "fetch-page-fault" + | E_Load_Page_Fault => "load-page-fault" + | E_Reserved_14 => "reserved-1" + | E_SAMO_Page_Fault => "store/amo-page-fault" + )))`; + + +(*val InterruptType_of_num : Num.integer -> Riscv_sequential_types.InterruptType*) + +val _ = Define ` + ((InterruptType_of_num:int -> riscv_sequential_types$InterruptType) arg_= + (let l__50 = arg_ in + if (((l__50 = (( 0 : int):sail_values$ii)))) then I_U_Software + else if (((l__50 = (( 1 : int):sail_values$ii)))) then I_S_Software + else if (((l__50 = (( 2 : int):sail_values$ii)))) then I_M_Software + else if (((l__50 = (( 3 : int):sail_values$ii)))) then I_U_Timer + else if (((l__50 = (( 4 : int):sail_values$ii)))) then I_S_Timer + else if (((l__50 = (( 5 : int):sail_values$ii)))) then I_M_Timer + else if (((l__50 = (( 6 : int):sail_values$ii)))) then I_U_External + else if (((l__50 = (( 7 : int):sail_values$ii)))) then I_S_External + else I_M_External))`; + + +(*val num_of_InterruptType : Riscv_sequential_types.InterruptType -> Num.integer*) + +val _ = Define ` + ((num_of_InterruptType:riscv_sequential_types$InterruptType -> int) arg_= + ((case arg_ of + I_U_Software => (( 0 : int):sail_values$ii) + | I_S_Software => (( 1 : int):sail_values$ii) + | I_M_Software => (( 2 : int):sail_values$ii) + | I_U_Timer => (( 3 : int):sail_values$ii) + | I_S_Timer => (( 4 : int):sail_values$ii) + | I_M_Timer => (( 5 : int):sail_values$ii) + | I_U_External => (( 6 : int):sail_values$ii) + | I_S_External => (( 7 : int):sail_values$ii) + | I_M_External => (( 8 : int):sail_values$ii) + )))`; + + +(*val interruptType_to_bits : Riscv_sequential_types.InterruptType -> Machine_word.mword Machine_word.ty4*) + +val _ = Define ` + ((interruptType_to_bits:riscv_sequential_types$InterruptType ->(4)words$word) i= + ((case i of + I_U_Software => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + | I_U_External => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + | I_S_External => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + | I_M_External => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + )))`; + + +(*val TrapVectorMode_of_num : Num.integer -> Riscv_sequential_types.TrapVectorMode*) + +val _ = Define ` + ((TrapVectorMode_of_num:int -> riscv_sequential_types$TrapVectorMode) arg_= + (let l__48 = arg_ in + if (((l__48 = (( 0 : int):sail_values$ii)))) then TV_Direct + else if (((l__48 = (( 1 : int):sail_values$ii)))) then TV_Vector + else TV_Reserved))`; + + +(*val num_of_TrapVectorMode : Riscv_sequential_types.TrapVectorMode -> Num.integer*) + +val _ = Define ` + ((num_of_TrapVectorMode:riscv_sequential_types$TrapVectorMode -> int) arg_= + ((case arg_ of TV_Direct => (( 0 : int):sail_values$ii) | TV_Vector => (( 1 : int):sail_values$ii) | TV_Reserved => (( 2 : int):sail_values$ii) )))`; + + +(*val trapVectorMode_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.TrapVectorMode*) + +val _ = Define ` + ((trapVectorMode_of_bits:(2)words$word -> riscv_sequential_types$TrapVectorMode) m= + (let b__0 = m in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then TV_Direct + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then TV_Vector + else TV_Reserved))`; + + +(*val not_implemented : forall 'a. string -> Riscv_sequential_types.M 'a*) + +val _ = Define ` + ((not_implemented:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) message= (throwS (Error_not_implemented message)))`; + + +(*val internal_error : forall 'a. string -> Riscv_sequential_types.M 'a*) + +val _ = Define ` + ((internal_error:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) s= (seqS (assert_expS F s) (throwS (Error_internal_error () ))))`; + + +(*val ExtStatus_of_num : Num.integer -> Riscv_sequential_types.ExtStatus*) + +val _ = Define ` + ((ExtStatus_of_num:int -> riscv_sequential_types$ExtStatus) arg_= + (let l__45 = arg_ in + if (((l__45 = (( 0 : int):sail_values$ii)))) then Off + else if (((l__45 = (( 1 : int):sail_values$ii)))) then Initial + else if (((l__45 = (( 2 : int):sail_values$ii)))) then Clean + else Dirty))`; + + +(*val num_of_ExtStatus : Riscv_sequential_types.ExtStatus -> Num.integer*) + +val _ = Define ` + ((num_of_ExtStatus:riscv_sequential_types$ExtStatus -> int) arg_= + ((case arg_ of Off => (( 0 : int):sail_values$ii) | Initial => (( 1 : int):sail_values$ii) | Clean => (( 2 : int):sail_values$ii) | Dirty => (( 3 : int):sail_values$ii) )))`; + + +(*val extStatus_to_bits : Riscv_sequential_types.ExtStatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((extStatus_to_bits:riscv_sequential_types$ExtStatus ->(2)words$word) e= + ((case e of + Off => (vec_of_bits [B0;B0] : 2 words$word) + | Initial => (vec_of_bits [B0;B1] : 2 words$word) + | Clean => (vec_of_bits [B1;B0] : 2 words$word) + | Dirty => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val extStatus_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.ExtStatus*) + +val _ = Define ` + ((extStatus_of_bits:(2)words$word -> riscv_sequential_types$ExtStatus) e= + (let b__0 = e in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Off + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Initial + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then Clean + else Dirty))`; + + +(*val SATPMode_of_num : Num.integer -> Riscv_sequential_types.SATPMode*) + +val _ = Define ` + ((SATPMode_of_num:int -> riscv_sequential_types$SATPMode) arg_= + (let l__43 = arg_ in + if (((l__43 = (( 0 : int):sail_values$ii)))) then Sbare + else if (((l__43 = (( 1 : int):sail_values$ii)))) then Sv32 + else Sv39))`; + + +(*val num_of_SATPMode : Riscv_sequential_types.SATPMode -> Num.integer*) + +val _ = Define ` + ((num_of_SATPMode:riscv_sequential_types$SATPMode -> int) arg_= ((case arg_ of Sbare => (( 0 : int):sail_values$ii) | Sv32 => (( 1 : int):sail_values$ii) | Sv39 => (( 2 : int):sail_values$ii) )))`; + + +(*val satpMode_of_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty4 -> Maybe.maybe Riscv_sequential_types.SATPMode*) + +val _ = Define ` + ((satpMode_of_bits:riscv_sequential_types$Architecture ->(4)words$word ->(riscv_sequential_types$SATPMode)option) (a : riscv_sequential_types$Architecture) (m : riscv_sequential_types$satp_mode)= + ((case (a, m) of (g__113, b__0) => SOME Sbare )))`; + + +(*val uop_of_num : Num.integer -> Riscv_sequential_types.uop*) + +val _ = Define ` + ((uop_of_num:int -> riscv_sequential_types$uop) arg_= + (let l__42 = arg_ in + if (((l__42 = (( 0 : int):sail_values$ii)))) then RISCV_LUI + else RISCV_AUIPC))`; + + +(*val num_of_uop : Riscv_sequential_types.uop -> Num.integer*) + +val _ = Define ` + ((num_of_uop:riscv_sequential_types$uop -> int) arg_= ((case arg_ of RISCV_LUI => (( 0 : int):sail_values$ii) | RISCV_AUIPC => (( 1 : int):sail_values$ii) )))`; + + +(*val bop_of_num : Num.integer -> Riscv_sequential_types.bop*) + +val _ = Define ` + ((bop_of_num:int -> riscv_sequential_types$bop) arg_= + (let l__37 = arg_ in + if (((l__37 = (( 0 : int):sail_values$ii)))) then RISCV_BEQ + else if (((l__37 = (( 1 : int):sail_values$ii)))) then RISCV_BNE + else if (((l__37 = (( 2 : int):sail_values$ii)))) then RISCV_BLT + else if (((l__37 = (( 3 : int):sail_values$ii)))) then RISCV_BGE + else if (((l__37 = (( 4 : int):sail_values$ii)))) then RISCV_BLTU + else RISCV_BGEU))`; + + +(*val num_of_bop : Riscv_sequential_types.bop -> Num.integer*) + +val _ = Define ` + ((num_of_bop:riscv_sequential_types$bop -> int) arg_= + ((case arg_ of + RISCV_BEQ => (( 0 : int):sail_values$ii) + | RISCV_BNE => (( 1 : int):sail_values$ii) + | RISCV_BLT => (( 2 : int):sail_values$ii) + | RISCV_BGE => (( 3 : int):sail_values$ii) + | RISCV_BLTU => (( 4 : int):sail_values$ii) + | RISCV_BGEU => (( 5 : int):sail_values$ii) + )))`; + + +(*val iop_of_num : Num.integer -> Riscv_sequential_types.iop*) + +val _ = Define ` + ((iop_of_num:int -> riscv_sequential_types$iop) arg_= + (let l__32 = arg_ in + if (((l__32 = (( 0 : int):sail_values$ii)))) then RISCV_ADDI + else if (((l__32 = (( 1 : int):sail_values$ii)))) then RISCV_SLTI + else if (((l__32 = (( 2 : int):sail_values$ii)))) then RISCV_SLTIU + else if (((l__32 = (( 3 : int):sail_values$ii)))) then RISCV_XORI + else if (((l__32 = (( 4 : int):sail_values$ii)))) then RISCV_ORI + else RISCV_ANDI))`; + + +(*val num_of_iop : Riscv_sequential_types.iop -> Num.integer*) + +val _ = Define ` + ((num_of_iop:riscv_sequential_types$iop -> int) arg_= + ((case arg_ of + RISCV_ADDI => (( 0 : int):sail_values$ii) + | RISCV_SLTI => (( 1 : int):sail_values$ii) + | RISCV_SLTIU => (( 2 : int):sail_values$ii) + | RISCV_XORI => (( 3 : int):sail_values$ii) + | RISCV_ORI => (( 4 : int):sail_values$ii) + | RISCV_ANDI => (( 5 : int):sail_values$ii) + )))`; + + +(*val sop_of_num : Num.integer -> Riscv_sequential_types.sop*) + +val _ = Define ` + ((sop_of_num:int -> riscv_sequential_types$sop) arg_= + (let l__30 = arg_ in + if (((l__30 = (( 0 : int):sail_values$ii)))) then RISCV_SLLI + else if (((l__30 = (( 1 : int):sail_values$ii)))) then RISCV_SRLI + else RISCV_SRAI))`; + + +(*val num_of_sop : Riscv_sequential_types.sop -> Num.integer*) + +val _ = Define ` + ((num_of_sop:riscv_sequential_types$sop -> int) arg_= + ((case arg_ of RISCV_SLLI => (( 0 : int):sail_values$ii) | RISCV_SRLI => (( 1 : int):sail_values$ii) | RISCV_SRAI => (( 2 : int):sail_values$ii) )))`; + + +(*val rop_of_num : Num.integer -> Riscv_sequential_types.rop*) + +val _ = Define ` + ((rop_of_num:int -> riscv_sequential_types$rop) arg_= + (let l__21 = arg_ in + if (((l__21 = (( 0 : int):sail_values$ii)))) then RISCV_ADD + else if (((l__21 = (( 1 : int):sail_values$ii)))) then RISCV_SUB + else if (((l__21 = (( 2 : int):sail_values$ii)))) then RISCV_SLL + else if (((l__21 = (( 3 : int):sail_values$ii)))) then RISCV_SLT + else if (((l__21 = (( 4 : int):sail_values$ii)))) then RISCV_SLTU + else if (((l__21 = (( 5 : int):sail_values$ii)))) then RISCV_XOR + else if (((l__21 = (( 6 : int):sail_values$ii)))) then RISCV_SRL + else if (((l__21 = (( 7 : int):sail_values$ii)))) then RISCV_SRA + else if (((l__21 = (( 8 : int):sail_values$ii)))) then RISCV_OR + else RISCV_AND))`; + + +(*val num_of_rop : Riscv_sequential_types.rop -> Num.integer*) + +val _ = Define ` + ((num_of_rop:riscv_sequential_types$rop -> int) arg_= + ((case arg_ of + RISCV_ADD => (( 0 : int):sail_values$ii) + | RISCV_SUB => (( 1 : int):sail_values$ii) + | RISCV_SLL => (( 2 : int):sail_values$ii) + | RISCV_SLT => (( 3 : int):sail_values$ii) + | RISCV_SLTU => (( 4 : int):sail_values$ii) + | RISCV_XOR => (( 5 : int):sail_values$ii) + | RISCV_SRL => (( 6 : int):sail_values$ii) + | RISCV_SRA => (( 7 : int):sail_values$ii) + | RISCV_OR => (( 8 : int):sail_values$ii) + | RISCV_AND => (( 9 : int):sail_values$ii) + )))`; + + +(*val ropw_of_num : Num.integer -> Riscv_sequential_types.ropw*) + +val _ = Define ` + ((ropw_of_num:int -> riscv_sequential_types$ropw) arg_= + (let l__17 = arg_ in + if (((l__17 = (( 0 : int):sail_values$ii)))) then RISCV_ADDW + else if (((l__17 = (( 1 : int):sail_values$ii)))) then RISCV_SUBW + else if (((l__17 = (( 2 : int):sail_values$ii)))) then RISCV_SLLW + else if (((l__17 = (( 3 : int):sail_values$ii)))) then RISCV_SRLW + else RISCV_SRAW))`; + + +(*val num_of_ropw : Riscv_sequential_types.ropw -> Num.integer*) + +val _ = Define ` + ((num_of_ropw:riscv_sequential_types$ropw -> int) arg_= + ((case arg_ of + RISCV_ADDW => (( 0 : int):sail_values$ii) + | RISCV_SUBW => (( 1 : int):sail_values$ii) + | RISCV_SLLW => (( 2 : int):sail_values$ii) + | RISCV_SRLW => (( 3 : int):sail_values$ii) + | RISCV_SRAW => (( 4 : int):sail_values$ii) + )))`; + + +(*val amoop_of_num : Num.integer -> Riscv_sequential_types.amoop*) + +val _ = Define ` + ((amoop_of_num:int -> riscv_sequential_types$amoop) arg_= + (let l__9 = arg_ in + if (((l__9 = (( 0 : int):sail_values$ii)))) then AMOSWAP + else if (((l__9 = (( 1 : int):sail_values$ii)))) then AMOADD + else if (((l__9 = (( 2 : int):sail_values$ii)))) then AMOXOR + else if (((l__9 = (( 3 : int):sail_values$ii)))) then AMOAND + else if (((l__9 = (( 4 : int):sail_values$ii)))) then AMOOR + else if (((l__9 = (( 5 : int):sail_values$ii)))) then AMOMIN + else if (((l__9 = (( 6 : int):sail_values$ii)))) then AMOMAX + else if (((l__9 = (( 7 : int):sail_values$ii)))) then AMOMINU + else AMOMAXU))`; + + +(*val num_of_amoop : Riscv_sequential_types.amoop -> Num.integer*) + +val _ = Define ` + ((num_of_amoop:riscv_sequential_types$amoop -> int) arg_= + ((case arg_ of + AMOSWAP => (( 0 : int):sail_values$ii) + | AMOADD => (( 1 : int):sail_values$ii) + | AMOXOR => (( 2 : int):sail_values$ii) + | AMOAND => (( 3 : int):sail_values$ii) + | AMOOR => (( 4 : int):sail_values$ii) + | AMOMIN => (( 5 : int):sail_values$ii) + | AMOMAX => (( 6 : int):sail_values$ii) + | AMOMINU => (( 7 : int):sail_values$ii) + | AMOMAXU => (( 8 : int):sail_values$ii) + )))`; + + +(*val csrop_of_num : Num.integer -> Riscv_sequential_types.csrop*) + +val _ = Define ` + ((csrop_of_num:int -> riscv_sequential_types$csrop) arg_= + (let l__7 = arg_ in + if (((l__7 = (( 0 : int):sail_values$ii)))) then CSRRW + else if (((l__7 = (( 1 : int):sail_values$ii)))) then CSRRS + else CSRRC))`; + + +(*val num_of_csrop : Riscv_sequential_types.csrop -> Num.integer*) + +val _ = Define ` + ((num_of_csrop:riscv_sequential_types$csrop -> int) arg_= ((case arg_ of CSRRW => (( 0 : int):sail_values$ii) | CSRRS => (( 1 : int):sail_values$ii) | CSRRC => (( 2 : int):sail_values$ii) )))`; + + +(*val word_width_of_num : Num.integer -> Riscv_sequential_types.word_width*) + +val _ = Define ` + ((word_width_of_num:int -> riscv_sequential_types$word_width) arg_= + (let l__4 = arg_ in + if (((l__4 = (( 0 : int):sail_values$ii)))) then BYTE + else if (((l__4 = (( 1 : int):sail_values$ii)))) then HALF + else if (((l__4 = (( 2 : int):sail_values$ii)))) then WORD + else DOUBLE))`; + + +(*val num_of_word_width : Riscv_sequential_types.word_width -> Num.integer*) + +val _ = Define ` + ((num_of_word_width:riscv_sequential_types$word_width -> int) arg_= + ((case arg_ of BYTE => (( 0 : int):sail_values$ii) | HALF => (( 1 : int):sail_values$ii) | WORD => (( 2 : int):sail_values$ii) | DOUBLE => (( 3 : int):sail_values$ii) )))`; + + +(*val is_aligned_addr : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool*) + +val _ = Define ` + ((is_aligned_addr:(64)words$word -> int -> bool) (addr : riscv_sequential_types$xlenbits) (width : int)= + (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):sail_values$ii)))`; + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => Riscv_sequential_types.ReadType -> Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +val _ = Define ` + ((checked_mem_read:riscv_sequential_types$ReadType ->(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (t : riscv_sequential_types$ReadType) (addr : riscv_sequential_types$xlenbits) (width : int)= (bindS + (RISCV_read addr width : ( ( 'int8_times_n words$word)option) riscv_sequential_types$M) (\ (w__0 : + ( 'int8_times_n words$word)option) . + returnS ((case (t, w__0) of + (Instruction, NONE) => MemException E_Fetch_Access_Fault + | (Data, NONE) => MemException E_Load_Access_Fault + | (_, SOME (v)) => MemValue v + )))))`; + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +val _ = Define ` + ((MEMr:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +val _ = Define ` + ((MEMr_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +val _ = Define ` + ((MEMr_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +val _ = Define ` + ((MEMr_reserved:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +val _ = Define ` + ((MEMr_reserved_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +val _ = Define ` + ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; + + +(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) + +val _ = Define ` + ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl res= + (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then + returnS (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (F, F, F) => (MEMr addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + | (T, F, F) => (MEMr_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + | (F, F, T) => + (MEMr_reserved addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + | (T, F, T) => + (MEMr_reserved_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + | (F, T, F) => throwS (Error_not_implemented "load.rl") + | (T, T, F) => + (MEMr_strong_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + | (F, T, T) => throwS (Error_not_implemented "lr.rl") + | (T, T, T) => + (MEMr_reserved_strong_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + )))`; + + +(*val mem_write_ea : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => seqS (MEMea addr width) (returnS (MemValue () )) + | (F, T, F) => seqS (MEMea_release addr width) (returnS (MemValue () )) + | (F, F, T) => seqS (MEMea_conditional addr width) (returnS (MemValue () )) + | (F, T, T) => seqS (MEMea_conditional_release addr width) (returnS (MemValue () )) + | (T, F, F) => throwS (Error_not_implemented "store.aq") + | (T, T, F) => seqS (MEMea_strong_release addr width) (returnS (MemValue () )) + | (T, F, T) => throwS (Error_not_implemented "sc.aq") + | (T, T, T) => seqS (MEMea_conditional_strong_release addr width) (returnS (MemValue () )) + )))`; + + +(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +val _ = Define ` + ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (width : int) (data : 'int8_times_n riscv_sequential_types$bits)= (bindS +(RISCV_write addr width data) (\ (w__0 : bool) . + returnS (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault))))`; + + +(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +val _ = Define ` + ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width value aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => MEMval addr width value + | (F, T, F) => MEMval_release addr width value + | (F, F, T) => MEMval_conditional addr width value + | (F, T, T) => MEMval_conditional_release addr width value + | (T, F, F) => throwS (Error_not_implemented "store.aq") + | (T, T, F) => MEMval_strong_release addr width value + | (T, F, T) => throwS (Error_not_implemented "sc.aq") + | (T, T, T) => MEMval_conditional_strong_release addr width value + )))`; + + +(*val _get_Misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Misa:riscv_sequential_types$Misa ->(64)words$word) (Mk_Misa (v))= v)`; + + +(*val _set_Misa : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Misa v) in + write_regS r_ref r)))`; + + +(*val _get_SV39_PTE : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64*) + +(*val _set_SV39_PTE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Misa_MXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_MXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_Z:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_Z : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_Z:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_Z:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_Y:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_Y : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_Y:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_Y:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_X:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_X:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_W:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_W:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_V:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_V:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_U:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_U:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_T:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_T : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_T:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_T:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_S:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_S : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_S:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_S:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_R:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_R:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_Q:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_Q : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_Q:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_Q:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_P:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_P : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_P:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_P:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_O:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_O : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_O:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_O:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_N:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_N : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_N:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_N:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_M:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_M : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_M:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_M:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_L:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_L : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_L:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_L:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_K:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_K : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_K:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_K:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_J:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_J : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_J:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_J:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_I:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_I : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_I:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_I:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_H:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_H : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_H:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_H:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_G:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_G:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_F:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_F : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_F:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_F:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_E:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_E : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_E:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_E:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_D:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_D:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_C:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_C : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_C:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_C:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_B:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_B : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_B:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_B:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Misa_A:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Misa_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Misa_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((update_Misa_A:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) + +(*val _get_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) + +(*val _set_PTE_Bits_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val legalize_misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Misa*) + +val _ = Define ` + ((legalize_misa:riscv_sequential_types$Misa ->(64)words$word -> riscv_sequential_types$Misa) (m : riscv_sequential_types$Misa) (v : riscv_sequential_types$xlenbits)= m)`; + + +(*val _get_Mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Mstatus:riscv_sequential_types$Mstatus ->(64)words$word) (Mk_Mstatus (v))= v)`; + + +(*val _set_Mstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Mstatus v) in + write_regS r_ref r)))`; + + +(*val _get_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mstatus_SXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) + +(*val _set_Sstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TSR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_TSR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_TW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TVM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_TVM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MPRV : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_MPRV:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) + +(*val _set_Sstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) + +(*val _set_Sstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mstatus_MPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_MPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_MPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_MIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((update_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) + +(*val _get_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val legalize_mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((legalize_mstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (o1 : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)= + (let (m : riscv_sequential_types$Mstatus) = (Mk_Mstatus v) in + let m = (update_Mstatus_XS m ((extStatus_to_bits Off : 2 words$word))) in + let m = +(update_Mstatus_SD m + ((bool_to_bits + ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m : 2 words$word)))) + : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word))))) \/ (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m : 2 words$word)))) + : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) + : 1 words$word))) in + let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1 : 2 words$word))) in + let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1 : 2 words$word))) in + let m = (update_Mstatus_UPIE m ((bool_to_bits F : 1 words$word))) in + update_Mstatus_UIE m ((bool_to_bits F : 1 words$word))))`; + + +(*val cur_Architecture : unit -> Riscv_sequential_types.M Riscv_sequential_types.Architecture*) + +val _ = Define ` + ((cur_Architecture:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Architecture),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS + (case w__0 of + Machine => bindS +(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) . returnS ((get_Misa_MXL w__1 : 2 words$word))) + | Supervisor => bindS +(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . + returnS ((get_Mstatus_SXL w__2 : 2 words$word))) + | User => bindS +(read_regS mstatus_ref) (\ (w__3 : riscv_sequential_types$Mstatus) . + returnS ((get_Mstatus_UXL w__3 : 2 words$word))) + ) (\ (a : riscv_sequential_types$arch_xlen) . + (case ((architecture a)) of + SOME (a) => returnS a + | NONE => internal_error "Invalid current architecture" + )))))`; + + +(*val in32BitMode : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((in32BitMode:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (cur_Architecture () ) (\ (w__0 : riscv_sequential_types$Architecture) . returnS (((w__0 = RV32))))))`; + + +(*val haveAtomics : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((haveAtomics:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . + returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveRVC : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((haveRVC:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . + returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveMulDiv : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((haveMulDiv:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . + returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveFP : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((haveFP:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . bindS +(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) . + returnS ((((((((get_Misa_F w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ (((((get_Misa_D w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))))))`; + + +(*val _get_Minterrupts : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Minterrupts:riscv_sequential_types$Minterrupts ->(64)words$word) (Mk_Minterrupts (v))= v)`; + + +(*val _set_Minterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Minterrupts v) in + write_regS r_ref r)))`; + + +(*val _get_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_MEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_MTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_MSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Minterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) + +(*val _get_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sinterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val legalize_mip : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((legalize_mip:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= + (let v = (Mk_Minterrupts v) in + let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v : 1 words$word))) in + let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; + + +(*val legalize_mie : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((legalize_mie:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= + (let v = (Mk_Minterrupts v) in + let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v : 1 words$word))) in + let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v : 1 words$word))) in + let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v : 1 words$word))) in + let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v : 1 words$word))) in + let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; + + +(*val legalize_mideleg : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((legalize_mideleg:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= + (let m = (Mk_Minterrupts v) in + let m = (update_Minterrupts_MEI m ((bool_to_bits F : 1 words$word))) in + let m = (update_Minterrupts_MTI m ((bool_to_bits F : 1 words$word))) in + update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`; + + +(*val _get_Medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Medeleg:riscv_sequential_types$Medeleg ->(64)words$word) (Mk_Medeleg (v))= v)`; + + +(*val _set_Medeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Medeleg v) in + write_regS r_ref r)))`; + + +(*val _get_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_MEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_MEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_SEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val _get_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) + +(*val _get_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) + +(*val _set_Sedeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +(*val legalize_medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Medeleg*) + +val _ = Define ` + ((legalize_medeleg:riscv_sequential_types$Medeleg ->(64)words$word -> riscv_sequential_types$Medeleg) (o1 : riscv_sequential_types$Medeleg) (v : riscv_sequential_types$xlenbits)= + (let m = (Mk_Medeleg v) in + update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`; + + +(*val _get_Mtvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Mtvec:riscv_sequential_types$Mtvec ->(64)words$word) (Mk_Mtvec (v))= v)`; + + +(*val _set_Mtvec : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mtvec:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Mtvec v) in + write_regS r_ref r)))`; + + +(*val _get_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62*) + +val _ = Define ` + ((get_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)))`; + + +(*val _set_Mtvec_Base : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mtvec_Base:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(62)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . + let r = ((get_Mtvec w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mtvec r))))`; + + +(*val _update_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.Mtvec*) + +val _ = Define ` + ((update_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x= + (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_Mtvec_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mtvec_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . + let r = ((get_Mtvec w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mtvec r))))`; + + +(*val _update_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mtvec*) + +val _ = Define ` + ((update_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x= + (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _update_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.Satp64*) + +(*val _get_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4*) + +(*val _set_Satp64_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*) + +(*val legalize_tvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mtvec*) + +val _ = Define ` + ((legalize_tvec:riscv_sequential_types$Mtvec ->(64)words$word -> riscv_sequential_types$Mtvec) (o1 : riscv_sequential_types$Mtvec) (v : riscv_sequential_types$xlenbits)= + (let v = (Mk_Mtvec v) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v : 2 words$word)))) of + TV_Direct => v + | TV_Vector => v + | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 : 2 words$word)) + )))`; + + +(*val _get_Mcause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Mcause:riscv_sequential_types$Mcause ->(64)words$word) (Mk_Mcause (v))= v)`; + + +(*val _set_Mcause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mcause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Mcause v) in + write_regS r_ref r)))`; + + +(*val _get_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1*) + +val _ = Define ` + ((get_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; + + +(*val _set_Mcause_IsInterrupt : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mcause_IsInterrupt:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . + let r = ((get_Mcause w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mcause r))))`; + + +(*val _update_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mcause*) + +val _ = Define ` + ((update_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x= + (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63*) + +val _ = Define ` + ((get_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 63 words$word)))`; + + +(*val _set_Mcause_Cause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Mcause_Cause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(63)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . + let r = ((get_Mcause w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Mcause r))))`; + + +(*val _update_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.Mcause*) + +val _ = Define ` + ((update_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x= + (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val tvec_addr : Riscv_sequential_types.Mtvec -> Riscv_sequential_types.Mcause -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((tvec_addr:riscv_sequential_types$Mtvec -> riscv_sequential_types$Mcause ->((64)words$word)option) (m : riscv_sequential_types$Mtvec) (c : riscv_sequential_types$Mcause)= + (let (base : riscv_sequential_types$xlenbits) = +((concat_vec ((get_Mtvec_Base m : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m : 2 words$word)))) of + TV_Direct => SOME base + | TV_Vector => + if (((((get_Mcause_IsInterrupt c : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME ((add_vec base + ((shift_bits_left + ((EXTZ (( 64 : int):sail_values$ii) ((get_Mcause_Cause c : 63 words$word)) : 64 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 64 words$word)) + : 64 words$word)) + else SOME base + | TV_Reserved => NONE + )))`; + + +(*val legalize_xepc : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((legalize_xepc:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) v= (bindS +(haveRVC () ) (\ (w__0 : bool) . + returnS ((and_vec v + ((EXTS (( 64 : int):sail_values$ii) + (if w__0 then (vec_of_bits [B1;B1;B0] : 3 words$word) + else (vec_of_bits [B1;B0;B0] : 3 words$word)) + : 64 words$word)) + : 64 words$word)))))`; + + +(*val _get_Sstatus : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Sstatus:riscv_sequential_types$Sstatus ->(64)words$word) (Mk_Sstatus (v))= v)`; + + +(*val _set_Sstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Sstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Sstatus v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val lower_mstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus*) + +val _ = Define ` + ((lower_mstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus) m= + (let s = (Mk_Sstatus ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = (update_Sstatus_SD s ((get_Mstatus_SD m : 1 words$word))) in + let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m : 2 words$word))) in + let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m : 1 words$word))) in + let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m : 1 words$word))) in + let s = (update_Sstatus_XS s ((get_Mstatus_XS m : 2 words$word))) in + let s = (update_Sstatus_FS s ((get_Mstatus_FS m : 2 words$word))) in + let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m : 1 words$word))) in + let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m : 1 words$word))) in + let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m : 1 words$word))) in + let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m : 1 words$word))) in + update_Sstatus_UIE s ((get_Mstatus_UIE m : 1 words$word))))`; + + +(*val lift_sstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((lift_sstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (s : riscv_sequential_types$Sstatus)= + (let m = (update_Mstatus_SD m ((get_Sstatus_SD s : 1 words$word))) in + let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s : 2 words$word))) in + let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in + let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in + let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in + let m = (update_Mstatus_FS m ((get_Sstatus_FS s : 2 words$word))) in + let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s : 1 words$word))) in + let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s : 1 words$word))) in + let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s : 1 words$word))) in + let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s : 1 words$word))) in + update_Mstatus_UIE m ((get_Sstatus_UIE s : 1 words$word))))`; + + +(*val legalize_sstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*) + +val _ = Define ` + ((legalize_sstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)= (lift_sstatus m (Mk_Sstatus v)))`; + + +(*val _get_Sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word) (Mk_Sedeleg (v))= v)`; + + +(*val _set_Sedeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Sedeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Sedeleg v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val legalize_sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Sedeleg*) + +val _ = Define ` + ((legalize_sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word -> riscv_sequential_types$Sedeleg) (s : riscv_sequential_types$Sedeleg) (v : riscv_sequential_types$xlenbits)= + (Mk_Sedeleg ((EXTZ (( 64 : int):sail_values$ii) ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 9 words$word)) : 64 words$word))))`; + + +(*val _get_Sinterrupts : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Sinterrupts:riscv_sequential_types$Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))= v)`; + + +(*val _set_Sinterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Sinterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Sinterrupts v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val lower_mip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*) + +val _ = Define ` + ((lower_mip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)= + (let (s : riscv_sequential_types$Sinterrupts) = +(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = +(update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) + : 1 words$word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val lower_mie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*) + +val _ = Define ` + ((lower_mie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)= + (let (s : riscv_sequential_types$Sinterrupts) = +(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = +(update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + let s = +(update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) + : 1 words$word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val lift_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((lift_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)= + (let (m : riscv_sequential_types$Minterrupts) = o1 in + let m = +(update_Minterrupts_SSI m + ((and_vec ((get_Sinterrupts_SSI s : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let m = +(update_Minterrupts_UEI m + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + update_Minterrupts_USI m + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val legalize_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((legalize_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= + (lift_sip m d (Mk_Sinterrupts v)))`; + + +(*val lift_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((lift_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)= + (let (m : riscv_sequential_types$Minterrupts) = o1 in + let m = +(if (((((get_Minterrupts_SEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_SEI m ((get_Sinterrupts_SEI s : 1 words$word)) + else m) in + let m = +(if (((((get_Minterrupts_STI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_STI m ((get_Sinterrupts_STI s : 1 words$word)) + else m) in + let m = +(if (((((get_Minterrupts_SSI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_SSI m ((get_Sinterrupts_SSI s : 1 words$word)) + else m) in + let m = +(if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word)) + else m) in + let m = +(if (((((get_Minterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_UTI m ((get_Sinterrupts_UTI s : 1 words$word)) + else m) in + if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word)) + else m))`; + + +(*val legalize_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) + +val _ = Define ` + ((legalize_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= + (lift_sie m d (Mk_Sinterrupts v)))`; + + +(*val _get_Satp64 : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((get_Satp64:riscv_sequential_types$Satp64 ->(64)words$word) (Mk_Satp64 (v))= v)`; + + +(*val _set_Satp64 : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Satp64:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_Satp64 v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) : 4 words$word)))`; + + +val _ = Define ` + ((set_Satp64_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Satp64 r))))`; + + +val _ = Define ` + ((update_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16*) + +val _ = Define ` + ((get_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) : 16 words$word)))`; + + +(*val _set_Satp64_Asid : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Satp64_Asid:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(16)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Satp64 r))))`; + + +(*val _update_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.Satp64*) + +val _ = Define ` + ((update_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44*) + +val _ = Define ` + ((get_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 44 words$word)))`; + + +(*val _set_Satp64_PPN : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_Satp64_PPN:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_Satp64 r))))`; + + +(*val _update_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.Satp64*) + +val _ = Define ` + ((update_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val legalize_satp : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((legalize_satp:riscv_sequential_types$Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : riscv_sequential_types$Architecture) (o1 : riscv_sequential_types$xlenbits) (v : riscv_sequential_types$xlenbits)= + (let s = (Mk_Satp64 v) in + (case ((satpMode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of + NONE => o1 + | SOME (Sv32) => o1 + | SOME (_) => (get_Satp64 s : 64 words$word) + )))`; + + +(*val csr_name : Machine_word.mword Machine_word.ty12 -> string*) + +val _ = Define ` + ((csr_name:(12)words$word -> string) csr= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "ustatus" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "uie" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "utvec" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "fflags" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "frm" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "fcsr" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycle" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "time" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instret" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycleh" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "timeh" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instreth" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sstatus" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "sedeleg" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "sideleg" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sie" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "stvec" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "scounteren" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sscratch" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "sepc" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "scause" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "stval" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sip" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "satp" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + "mvendorid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + "marchid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + "mimpid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + "mhartid" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mstatus" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "misa" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "medeleg" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mideleg" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mie" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "mtvec" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "mcounteren" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mscratch" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "mepc" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "mcause" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mtval" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mip" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycle" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstret" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycleh" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstreth" + else "UNKNOWN"))`; + + +(*val csrAccess : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((csrAccess:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)))`; + + +(*val csrPriv : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((csrPriv:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 2 words$word)))`; + + +(*val is_CSR_defined : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool*) + +val _ = Define ` + ((is_CSR_defined:(12)words$word -> riscv_sequential_types$Privilege -> bool) (csr : 12 riscv_sequential_types$bits) (p : riscv_sequential_types$Privilege)= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else F))`; + + +(*val check_CSR_access : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege -> bool -> bool*) + +val _ = Define ` + ((check_CSR_access:(2)words$word ->(2)words$word -> riscv_sequential_types$Privilege -> bool -> bool) csrrw csrpr p isWrite= + (((~ ((((((((bool_to_bits isWrite : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((csrrw = (vec_of_bits [B1;B1] : 2 words$word))))))))) /\ ((((lem$w2ui ((privLevel_to_bits p : 2 words$word))) >= (lem$w2ui csrpr))))))`; + + +(*val check_TVM_SATP : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((check_TVM_SATP:(12)words$word -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege)= (bindS +(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + returnS ((~ ((((((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) /\ ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))) /\ (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))))))))))`; + + +(*val check_CSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((check_CSR:(12)words$word -> riscv_sequential_types$Privilege -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege) (isWrite : bool)= (bindS +(check_TVM_SATP csr p) (\ (w__0 : bool) . + returnS (((((is_CSR_defined csr p)) /\ (((((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p + isWrite)) /\ w__0)))))))))`; + + +(*val exception_delegatee : Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.Privilege*) + +val _ = Define ` + ((exception_delegatee:riscv_sequential_types$ExceptionType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Privilege),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (e : riscv_sequential_types$ExceptionType) (p : riscv_sequential_types$Privilege)= + (let idx = (num_of_ExceptionType e) in bindS +(read_regS medeleg_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . + let super = (access_vec_dec ((get_Medeleg w__0 : 64 words$word)) idx) in bindS +(read_regS sedeleg_ref) (\ (w__1 : riscv_sequential_types$Sedeleg) . + let user = (access_vec_dec ((get_Sedeleg w__1 : 64 words$word)) idx) in bindS +(read_regS misa_ref) (\ (w__2 : riscv_sequential_types$Misa) . + let deleg = +(if ((((((((get_Misa_S w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((bit_to_bool super))))) then + Supervisor + else Machine) in + returnS (if ((((lem$w2ui ((privLevel_to_bits deleg : 2 words$word))) < (lem$w2ui ((privLevel_to_bits p : 2 words$word)))))) then + p + else deleg))))))`; + + +(*val findPendingInterrupt : Machine_word.mword Machine_word.ty64 -> Maybe.maybe Riscv_sequential_types.InterruptType*) + +val _ = Define ` + ((findPendingInterrupt:(64)words$word ->(riscv_sequential_types$InterruptType)option) ip= + (let ip = (Mk_Minterrupts ip) in + if (((((get_Minterrupts_MEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + SOME I_M_External + else if (((((get_Minterrupts_MSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_M_Software + else if (((((get_Minterrupts_MTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_M_Timer + else if (((((get_Minterrupts_SEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_External + else if (((((get_Minterrupts_SSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_Software + else if (((((get_Minterrupts_STI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_Timer + else if (((((get_Minterrupts_UEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_External + else if (((((get_Minterrupts_USI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_Software + else if (((((get_Minterrupts_UTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_Timer + else NONE))`; + + +(*val curInterrupt : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.M (Maybe.maybe ((Riscv_sequential_types.InterruptType * Riscv_sequential_types.Privilege)))*) + +val _ = Define ` + ((curInterrupt:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((riscv_sequential_types$InterruptType#riscv_sequential_types$Privilege)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (pend : riscv_sequential_types$Minterrupts) (enbl : riscv_sequential_types$Minterrupts) (delg : riscv_sequential_types$Minterrupts)= + (let (en_mip : riscv_sequential_types$xlenbits) = +((and_vec ((get_Minterrupts pend : 64 words$word)) ((get_Minterrupts enbl : 64 words$word)) + : 64 words$word)) in + if (((en_mip = ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) then + returnS NONE + else + let eff_mip = +((and_vec en_mip ((not_vec ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) + : 64 words$word)) in + let eff_sip = ((and_vec en_mip ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) in bindS +(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + if ((((((((get_Mstatus_MIE w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((eff_mip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))) then + returnS ((case ((findPendingInterrupt eff_mip)) of + SOME (i) => + let r = (i, Machine) in + SOME r + | NONE => NONE + )) + else bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS +(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) . bindS +(read_regS cur_privilege_ref) (\ (w__3 : riscv_sequential_types$Privilege) . + returnS (if ((((((((get_Mstatus_SIE w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((eff_sip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) /\ ((((((((privLevel_to_bits w__2 : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))) \/ (((((privLevel_to_bits w__3 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))))))))))) then + (case ((findPendingInterrupt eff_sip)) of + SOME (i) => + let r = (i, Supervisor) in + SOME r + | NONE => NONE + ) + else NONE)))))))`; + + +(*val tval : Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Machine_word.mword Machine_word.ty64*) + +val _ = Define ` + ((tval:((64)words$word)option ->(64)words$word) excinfo= + ((case excinfo of + SOME (e) => e + | NONE => (EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word) + )))`; + + +(*val handle_trap : Riscv_sequential_types.Privilege -> bool -> Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty64 -> Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((handle_trap:riscv_sequential_types$Privilege -> bool ->(4)words$word ->(64)words$word ->(riscv_sequential_types$xlenbits)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (del_priv : riscv_sequential_types$Privilege) (intr : bool) (c : riscv_sequential_types$exc_code) (pc : riscv_sequential_types$xlenbits) (info : + riscv_sequential_types$xlenbits option)= + (let (_ : unit) = +(prerr_endline + ((STRCAT "handling " + ((STRCAT (if intr then "int#" else "exc#") + ((STRCAT ((string_of_vec c)) + ((STRCAT " at priv " ((privLevel_to_str del_priv))))))))))) in + (case del_priv of + Machine => bindS (seqS (seqS +(set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word))) +(set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):sail_values$ii) c : 63 words$word)))) +(read_regS mstatus_ref)) (\ (w__0 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word))) +(set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word)))) +(read_regS cur_privilege_ref)) (\ (w__1 : riscv_sequential_types$Privilege) . bindS (seqS (seqS (seqS (seqS +(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word))) +(write_regS mtval_ref ((tval info : 64 words$word)))) +(write_regS mepc_ref pc)) +(write_regS cur_privilege_ref del_priv)) +(read_regS mtvec_ref)) (\ (w__2 : riscv_sequential_types$Mtvec) . bindS +(read_regS mcause_ref) (\ (w__3 : riscv_sequential_types$Mcause) . + (case ((tvec_addr w__2 w__3 : ( 64 words$word)option)) of + SOME (epc) => returnS epc + | NONE => (internal_error "Invalid mtvec mode" : ( 64 words$word) riscv_sequential_types$M) + ))))) + | Supervisor => bindS (seqS (seqS +(set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))) +(set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):sail_values$ii) c : 63 words$word)))) +(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word))) +(set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word)))) +(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) . bindS + (case w__7 of + User => returnS ((bool_to_bits F : 1 words$word)) + | Supervisor => returnS ((bool_to_bits T : 1 words$word)) + | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) riscv_sequential_types$M) + ) (\ (w__9 : 1 words$word) . bindS (seqS (seqS (seqS (seqS +(set_Mstatus_SPP mstatus_ref w__9) +(write_regS stval_ref ((tval info : 64 words$word)))) +(write_regS sepc_ref pc)) +(write_regS cur_privilege_ref del_priv)) +(read_regS stvec_ref)) (\ (w__10 : riscv_sequential_types$Mtvec) . bindS +(read_regS scause_ref) (\ (w__11 : riscv_sequential_types$Mcause) . + (case ((tvec_addr w__10 w__11 : ( 64 words$word)option)) of + SOME (epc) => returnS epc + | NONE => (internal_error "Invalid stvec mode" : ( 64 words$word) riscv_sequential_types$M) + )))))) + | User => (internal_error "the N extension is currently unsupported" : ( 64 words$word) riscv_sequential_types$M) + )))`; + + +(*val handle_exception : Riscv_sequential_types.Privilege -> Riscv_sequential_types.ctl_result -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((handle_exception:riscv_sequential_types$Privilege -> riscv_sequential_types$ctl_result ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (cur_priv : riscv_sequential_types$Privilege) (ctl : riscv_sequential_types$ctl_result) (pc : riscv_sequential_types$xlenbits)= + ((case (cur_priv, ctl) of + (_, CTL_TRAP (e)) => bindS +(exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . + let (_ : unit) = +(prerr_endline + ((STRCAT "trapping from " + ((STRCAT ((privLevel_to_str cur_priv)) + ((STRCAT " to " + ((STRCAT ((privLevel_to_str del_priv)) + ((STRCAT " to handle " + ((exceptionType_to_str e.sync_exception_trap))))))))))))) in + (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap : 4 words$word)) pc + e.sync_exception_excinfo + : ( 64 words$word) riscv_sequential_types$M)) + | (_, CTL_MRET (_)) => bindS +(read_regS cur_privilege_ref) (\ prev_priv . bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word))) +(set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) +(read_regS mstatus_ref)) (\ (w__2 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) +(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User : 2 words$word)))) +(read_regS cur_privilege_ref)) (\ (w__3 : riscv_sequential_types$Privilege) . + let (_ : unit) = +(prerr_endline + ((STRCAT "ret-ing from " + ((STRCAT ((privLevel_to_str prev_priv)) + ((STRCAT " to " ((privLevel_to_str w__3))))))))) in + (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M))))) + | (_, CTL_SRET (_)) => bindS +(read_regS cur_privilege_ref) (\ prev_priv . bindS +(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 : 1 words$word))) +(set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) +(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS +(write_regS + cur_privilege_ref + (if (((((get_Mstatus_SPP w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + Supervisor + else User)) +(set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word)))) +(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) . + let (_ : unit) = +(prerr_endline + ((STRCAT "ret-ing from " + ((STRCAT ((privLevel_to_str prev_priv)) + ((STRCAT " to " ((privLevel_to_str w__7))))))))) in + (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M))))) + )))`; + + +(*val handle_mem_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((handle_mem_exception:(64)words$word -> riscv_sequential_types$ExceptionType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (e : riscv_sequential_types$ExceptionType)= + (let (t : riscv_sequential_types$sync_exception) = (<| sync_exception_trap := e; sync_exception_excinfo := (SOME addr) |>) in bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__2)))))`; + + +(*val handle_decode_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((handle_decode_exception:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) instbits= + (let (t : riscv_sequential_types$sync_exception) = +(<| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := (SOME instbits) |>) in bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__2)))))`; + + +(*val handle_interrupt : Riscv_sequential_types.InterruptType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((handle_interrupt:riscv_sequential_types$InterruptType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (i : riscv_sequential_types$InterruptType) (del_priv : riscv_sequential_types$Privilege)= (bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . bindS + (handle_trap del_priv T ((interruptType_to_bits i : 4 words$word)) w__0 NONE + : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__1))))`; + + +(*val handle_illegal : unit -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((handle_illegal:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = + (let (t : riscv_sequential_types$sync_exception) = +(<| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := NONE |>) in bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__2)))))`; + + +(*val init_sys : unit -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((init_sys:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (seqS (seqS (seqS (seqS (seqS +(write_regS cur_privilege_ref Machine) +(set_Misa_MXL misa_ref ((arch_to_bits RV64 : 2 words$word)))) +(set_Misa_C misa_ref ((bool_to_bits T : 1 words$word)))) +(set_Misa_U misa_ref ((bool_to_bits T : 1 words$word)))) +(set_Misa_S misa_ref ((bool_to_bits T : 1 words$word)))) +(read_regS misa_ref)) (\ (w__0 : riscv_sequential_types$Misa) . bindS (seqS +(set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 : 2 words$word))) +(read_regS misa_ref)) (\ (w__1 : riscv_sequential_types$Misa) . seqS (seqS +(set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 : 2 words$word))) +(set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word)))) +(write_regS mhartid_ref ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))`; + + +(*val tick_clock : unit -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((tick_clock:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):sail_values$ii) : 64 words$word)))))`; + + +val _ = Define ` + ((PAGESIZE_BITS:int)= ((( 12 : int):sail_values$ii)))`; + + +(*val _get_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_PTE_Bits:riscv_sequential_types$PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))= v)`; + + +(*val _set_PTE_Bits : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_PTE_Bits:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_PTE_Bits v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 8 words$word)) in + write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 8 words$word))))`; + + +(*val isPTEPtr : Machine_word.mword Machine_word.ty8 -> bool*) + +val _ = Define ` + ((isPTEPtr:(8)words$word -> bool) p= + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; + + +(*val isInvalidPTE : Machine_word.mword Machine_word.ty8 -> bool*) + +val _ = Define ` + ((isInvalidPTE:(8)words$word -> bool) p= + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_V a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; + + +(*val checkPTEPermission : Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((checkPTEPermission:riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> riscv_sequential_types$PTE_Bits ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (ac : riscv_sequential_types$AccessType) (priv : riscv_sequential_types$Privilege) (mxr : bool) (sum : bool) (p : riscv_sequential_types$PTE_Bits)= + ((case (ac, priv) of + (Read, User) => + returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + | (Write, User) => + returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (ReadWrite, User) => + returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + | (Execute, User) => + returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (Read, Supervisor) => + returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + | (Write, Supervisor) => + returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (ReadWrite, Supervisor) => + returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + | (Execute, Supervisor) => + returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (_, Machine) => internal_error "m-mode mem perm check" + )))`; + + +(*val update_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.AccessType -> Maybe.maybe Riscv_sequential_types.PTE_Bits*) + +val _ = Define ` + ((update_PTE_Bits:riscv_sequential_types$PTE_Bits -> riscv_sequential_types$AccessType ->(riscv_sequential_types$PTE_Bits)option) (p : riscv_sequential_types$PTE_Bits) (a : riscv_sequential_types$AccessType)= + (let update_d = + (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in + let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in + if (((update_d \/ update_a))) then + let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in + let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T : 1 words$word)) else np) in + SOME np + else NONE))`; + + +(*val PTW_Error_of_num : Num.integer -> Riscv_sequential_types.PTW_Error*) + +val _ = Define ` + ((PTW_Error_of_num:int -> riscv_sequential_types$PTW_Error) arg_= + (let l__0 = arg_ in + if (((l__0 = (( 0 : int):sail_values$ii)))) then PTW_Access + else if (((l__0 = (( 1 : int):sail_values$ii)))) then PTW_Invalid_PTE + else if (((l__0 = (( 2 : int):sail_values$ii)))) then PTW_No_Permission + else if (((l__0 = (( 3 : int):sail_values$ii)))) then PTW_Misaligned + else PTW_PTE_Update))`; + + +(*val num_of_PTW_Error : Riscv_sequential_types.PTW_Error -> Num.integer*) + +val _ = Define ` + ((num_of_PTW_Error:riscv_sequential_types$PTW_Error -> int) arg_= + ((case arg_ of + PTW_Access => (( 0 : int):sail_values$ii) + | PTW_Invalid_PTE => (( 1 : int):sail_values$ii) + | PTW_No_Permission => (( 2 : int):sail_values$ii) + | PTW_Misaligned => (( 3 : int):sail_values$ii) + | PTW_PTE_Update => (( 4 : int):sail_values$ii) + )))`; + + +(*val translationException : Riscv_sequential_types.AccessType -> Riscv_sequential_types.PTW_Error -> Riscv_sequential_types.ExceptionType*) + +val _ = Define ` + ((translationException:riscv_sequential_types$AccessType -> riscv_sequential_types$PTW_Error -> riscv_sequential_types$ExceptionType) (a : riscv_sequential_types$AccessType) (f : riscv_sequential_types$PTW_Error)= + ((case (a, f) of + (Read, PTW_Access) => E_Load_Access_Fault + | (Read, _) => E_Load_Page_Fault + | (Write, PTW_Access) => E_SAMO_Access_Fault + | (Write, _) => E_SAMO_Page_Fault + | (Fetch, PTW_Access) => E_Fetch_Access_Fault + | (Fetch, _) => E_Fetch_Page_Fault + )))`; + + +val _ = Define ` + ((SV39_LEVEL_BITS:int)= ((( 9 : int):sail_values$ii)))`; + + +val _ = Define ` + ((SV39_LEVELS:int)= ((( 3 : int):sail_values$ii)))`; + + +val _ = Define ` + ((PTE39_LOG_SIZE:int)= ((( 3 : int):sail_values$ii)))`; + + +val _ = Define ` + ((PTE39_SIZE:int)= ((( 8 : int):sail_values$ii)))`; + + +(*val _get_SV39_Vaddr : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39*) + +val _ = Define ` + ((get_SV39_Vaddr:riscv_sequential_types$SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))= v)`; + + +(*val _set_SV39_Vaddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_Vaddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_SV39_Vaddr v) in + write_regS r_ref r)))`; + + +(*val _get_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27*) + +val _ = Define ` + ((get_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 27 words$word)))`; + + +(*val _set_SV39_Vaddr_VPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_Vaddr_VPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(27)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . + let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in + let r = ((update_subrange_vec_dec r (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 39 words$word)) in + write_regS r_ref (Mk_SV39_Vaddr r))))`; + + +(*val _update_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.SV39_Vaddr*) + +val _ = Define ` + ((update_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= + (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 39 words$word))))`; + + +(*val _get_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12*) + +val _ = Define ` + ((get_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 12 words$word)))`; + + +(*val _set_SV39_Vaddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_Vaddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . + let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 39 words$word)) in + write_regS r_ref (Mk_SV39_Vaddr r))))`; + + +(*val _update_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Vaddr*) + +val _ = Define ` + ((update_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= + (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 39 words$word))))`; + + +(*val _update_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Paddr*) + +(*val _get_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12*) + +(*val _set_SV39_Paddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*) + +(*val _get_SV39_Paddr : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56*) + +val _ = Define ` + ((get_SV39_Paddr:riscv_sequential_types$SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))= v)`; + + +(*val _set_SV39_Paddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_Paddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_SV39_Paddr v) in + write_regS r_ref r)))`; + + +(*val _get_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44*) + +val _ = Define ` + ((get_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 44 words$word)))`; + + +(*val _set_SV39_Paddr_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_Paddr_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . + let r = ((get_SV39_Paddr w__0 : 56 words$word)) in + let r = ((update_subrange_vec_dec r (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 56 words$word)) in + write_regS r_ref (Mk_SV39_Paddr r))))`; + + +(*val _update_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_Paddr*) + +val _ = Define ` + ((update_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x= + (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 56 words$word))))`; + + +(*val _update_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_PTE*) + +(*val _get_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44*) + +(*val _set_SV39_PTE_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((get_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 12 words$word)))`; + + +val _ = Define ` + ((set_SV39_Paddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . + let r = ((get_SV39_Paddr w__0 : 56 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 56 words$word)) in + write_regS r_ref (Mk_SV39_Paddr r))))`; + + +val _ = Define ` + ((update_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x= + (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 56 words$word))))`; + + +val _ = Define ` + ((get_SV39_PTE:riscv_sequential_types$SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))= v)`; + + +val _ = Define ` + ((set_SV39_PTE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ r . + let r = (Mk_SV39_PTE v) in + write_regS r_ref r)))`; + + +val _ = Define ` + ((get_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 44 words$word)))`; + + +val _ = Define ` + ((set_SV39_PTE_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_SV39_PTE r))))`; + + +val _ = Define ` + ((update_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2*) + +val _ = Define ` + ((get_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 2 words$word)))`; + + +(*val _set_SV39_PTE_RSW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_PTE_RSW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_SV39_PTE r))))`; + + +(*val _update_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.SV39_PTE*) + +val _ = Define ` + ((update_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val _get_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8*) + +val _ = Define ` + ((get_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; + + +(*val _set_SV39_PTE_BITS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((set_SV39_PTE_BITS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS +(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in + write_regS r_ref (Mk_SV39_PTE r))))`; + + +(*val _update_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.SV39_PTE*) + +val _ = Define ` + ((update_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; + + +(*val curAsid64 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty16)*) + +val _ = Define ` + ((curAsid64:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((16)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let satp64 = (Mk_Satp64 w__0) in + returnS ((get_Satp64_Asid satp64 : 16 words$word)))))`; + + +(*val curPTB39 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty56)*) + +val _ = Define ` + ((curPTB39:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((56)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let satp64 = (Mk_Satp64 w__0) in + returnS ((EXTZ (( 56 : int):sail_values$ii) + ((shiftl ((get_Satp64_PPN satp64 : 44 words$word)) PAGESIZE_BITS : 44 words$word)) + : 56 words$word)))))`; + + +(*val walk39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M Riscv_sequential_types.PTW_Result*) + + val walk39_defn = Hol_defn "walk39" ` + ((walk39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$PTW_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vaddr ac priv mxr sum ptb level global= + (let va = (Mk_SV39_Vaddr vaddr) in + let (pt_ofs : riscv_sequential_types$paddr39) = +((shiftl + ((EXTZ (( 56 : int):sail_values$ii) + ((subrange_vec_dec + ((shiftr ((get_SV39_Vaddr_VPNi va : 27 words$word)) + ((level * SV39_LEVEL_BITS)) + : 27 words$word)) SV39_LEVEL_BITS (( 0 : int):sail_values$ii) + : 10 words$word)) + : 56 words$word)) PTE39_LOG_SIZE + : 56 words$word)) in + let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in bindS + (checked_mem_read Data ((EXTZ (( 64 : int):sail_values$ii) pte_addr : 64 words$word)) (( 8 : int):sail_values$ii) + : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__0 : ( 64 words$word) riscv_sequential_types$MemoryOpResult) . + (case w__0 of + MemException (_) => returnS (PTW_Failure PTW_Access) + | MemValue (v) => + let pte = (Mk_SV39_PTE v) in + let pbits = ((get_SV39_PTE_BITS pte : 8 words$word)) in + let pattr = (Mk_PTE_Bits pbits) in + let is_global = + (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in + if ((isInvalidPTE pbits)) then returnS (PTW_Failure PTW_Invalid_PTE) + else if ((isPTEPtr pbits)) then + if (((level = (( 0 : int):sail_values$ii)))) then returnS (PTW_Failure PTW_Invalid_PTE) + else + walk39 vaddr ac priv mxr sum + ((EXTZ (( 56 : int):sail_values$ii) ((get_SV39_PTE_PPNi pte : 44 words$word)) : 56 words$word)) + ((level - (( 1 : int):sail_values$ii))) is_global + else bindS +(checkPTEPermission ac priv mxr sum pattr) (\ (w__3 : bool) . + returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission + else if ((level > (( 0 : int):sail_values$ii))) then + let masked = +((and_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((EXTZ (( 44 : int):sail_values$ii) + ((sub_vec_int + ((shiftl (vec_of_bits [B1] : 1 words$word) + ((level * SV39_LEVEL_BITS)) + : 1 words$word)) (( 1 : int):sail_values$ii) + : 1 words$word)) + : 44 words$word)) + : 44 words$word)) in + if (((masked <> ((EXTZ (( 44 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 44 words$word))))) + then + PTW_Failure PTW_Misaligned + else + let ppn = +((or_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((and_vec + ((EXTZ (( 44 : int):sail_values$ii) ((get_SV39_Vaddr_VPNi va : 27 words$word)) : 44 words$word)) + ((EXTZ (( 44 : int):sail_values$ii) + ((sub_vec_int + ((shiftl (vec_of_bits [B1] : 1 words$word) + ((level * SV39_LEVEL_BITS)) + : 1 words$word)) (( 1 : int):sail_values$ii) + : 1 words$word)) + : 44 words$word)) + : 44 words$word)) + : 44 words$word)) in + PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va : 12 words$word)) + : 56 words$word),pte,pte_addr,level,is_global) + else + PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((get_SV39_Vaddr_PgOfs va : 12 words$word)) + : 56 words$word),pte,pte_addr,level,is_global))) + ))))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn; + +(*val make_TLB39_Entry : Machine_word.mword Machine_word.ty16 -> bool -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Sail_values.ii -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M Riscv_sequential_types.TLB39_Entry*) + +val _ = Define ` + ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE -> int ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TLB39_Entry),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr= + (let (shift : sail_values$ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in + let (vAddrMask : riscv_sequential_types$vaddr39) = +((sub_vec_int + ((shiftl ((EXTZ (( 39 : int):sail_values$ii) (vec_of_bits [B1] : 1 words$word) : 39 words$word)) shift : 39 words$word)) + (( 1 : int):sail_values$ii) + : 39 words$word)) in + let (vMatchMask : riscv_sequential_types$vaddr39) = ((not_vec vAddrMask : 39 words$word)) in bindS + (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) . + returnS (<| TLB39_Entry_asid := asid; + TLB39_Entry_global := global; + TLB39_Entry_pte := pte; + TLB39_Entry_pteAddr := pteAddr; + TLB39_Entry_vAddrMask := vAddrMask; + TLB39_Entry_vMatchMask := vMatchMask; + TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask : 39 words$word)); + TLB39_Entry_pAddr := + ((shiftl ((shiftr pAddr shift : 56 words$word)) shift : 56 words$word)); + TLB39_Entry_age := w__0 |>))))`; + + +val _ = Define ` + ((TLBEntries:int)= ((( 32 : int):sail_values$ii)))`; + + +(*val lookupTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M (Maybe.maybe ((Sail_values.ii * Riscv_sequential_types.TLB39_Entry)))*) + +val _ = Define ` + ((lookupTLB39:(16)words$word ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((int#riscv_sequential_types$TLB39_Entry)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vaddr= (bindS +(read_regS tlb39_ref) (\ (w__0 : riscv_sequential_types$TLB39_Entry option) . + returnS ((case w__0 of + NONE => NONE + | SOME (e) => + if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr : 39 words$word)))))))) then + SOME ((( 0 : int):sail_values$ii), e) + else NONE + )))))`; + + +(*val addToTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (bindS +(make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . + write_regS tlb39_ref (SOME ent))))`; + + +(*val writeTLB39 : Sail_values.ii -> Riscv_sequential_types.TLB39_Entry -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((writeTLB39:int -> riscv_sequential_types$TLB39_Entry ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (idx : sail_values$ii) (ent : riscv_sequential_types$TLB39_Entry)= (write_regS tlb39_ref (SOME ent)))`; + + +(*val flushTLB : Maybe.maybe (Machine_word.mword Machine_word.ty16) -> Maybe.maybe (Machine_word.mword Machine_word.ty39) -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((flushTLB:((16)words$word)option ->((39)words$word)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid addr= (bindS +(read_regS tlb39_ref) (\ (w__0 : riscv_sequential_types$TLB39_Entry option) . + let (ent : riscv_sequential_types$TLB39_Entry option) = +((case (w__0, asid, addr) of + (NONE, _, _) => NONE + | (SOME (e), NONE, NONE) => NONE + | (SOME (e), NONE, SOME (a)) => + if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a : 39 words$word))))) then + NONE + else SOME e + | (SOME (e), SOME (i), NONE) => + if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE + else SOME e + | (SOME (e), SOME (i), SOME (a)) => + if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask : 39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then + NONE + else SOME e + )) in + write_regS tlb39_ref ent)))`; + + +val _ = Define ` + ((enable_dirty_update:bool)= T)`; + + +(*val translate39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Sail_values.ii -> Riscv_sequential_types.M Riscv_sequential_types.TR39_Result*) + +val _ = Define ` + ((translate39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR39_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac priv mxr sum level= (bindS + (curAsid64 () : ( 16 words$word) riscv_sequential_types$M) (\ asid . bindS +(lookupTLB39 asid vAddr) (\ (w__0 : ((sail_values$ii # riscv_sequential_types$TLB39_Entry))option) . + (case w__0 of + SOME (idx,ent) => + let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte : 8 words$word))) in bindS +(checkPTEPermission ac priv mxr sum pteBits) (\ (w__1 : bool) . + if ((~ w__1)) then returnS (TR39_Failure PTW_No_Permission) + else + (case ((update_PTE_Bits pteBits ac)) of + NONE => + returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + ((EXTZ (( 56 : int):sail_values$ii) + ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) + : 56 words$word)) + : 56 words$word))) + | SOME (pbits) => + if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update) + else + let (n_ent : riscv_sequential_types$TLB39_Entry) = ent in + let n_ent = +((n_ent with<| + TLB39_Entry_pte := + ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits : 8 words$word))))|>)) in bindS (seqS +(writeTLB39 idx n_ent) +(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) ent.TLB39_Entry_pteAddr : 64 words$word)) (( 8 : int):sail_values$ii) + ((get_SV39_PTE ent.TLB39_Entry_pte : 64 words$word)))) (\ (w__2 : unit + riscv_sequential_types$MemoryOpResult) . seqS + (case w__2 of + MemValue (_) => returnS () + | MemException (e) => internal_error "invalid physical address in TLB" + ) +(returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + ((EXTZ (( 56 : int):sail_values$ii) + ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) + : 56 words$word)) + : 56 words$word))))) + )) + | NONE => bindS + (curPTB39 () : ( 56 words$word) riscv_sequential_types$M) (\ (w__6 : 56 words$word) . bindS +(walk39 vAddr ac priv mxr sum w__6 level F) (\ (w__7 : riscv_sequential_types$PTW_Result) . + (case w__7 of + PTW_Failure (f) => returnS (TR39_Failure f) + | PTW_Success (pAddr,pte,pteAddr,level,global) => + (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word))) ac)) of + NONE => seqS +(addToTLB39 asid vAddr pAddr pte pteAddr level global) (returnS (TR39_Address pAddr)) + | SOME (pbits) => + if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update) + else + let (w_pte : riscv_sequential_types$SV39_PTE) = +(update_SV39_PTE_BITS pte ((get_PTE_Bits pbits : 8 words$word))) in bindS +(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) pteAddr : 64 words$word)) (( 8 : int):sail_values$ii) + ((get_SV39_PTE w_pte : 64 words$word))) (\ (w__8 : unit riscv_sequential_types$MemoryOpResult) . + (case w__8 of + MemValue (_) => seqS +(addToTLB39 asid vAddr pAddr w_pte pteAddr level global) +(returnS (TR39_Address pAddr)) + | MemException (e) => returnS (TR39_Failure PTW_Access) + )) + ) + ))) + )))))`; + + +(*val translationMode : Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.SATPMode*) + +val _ = Define ` + ((translationMode:riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$SATPMode),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) priv= + (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) + then + returnS Sbare + else bindS +(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . + let arch = (architecture ((get_Mstatus_SXL w__0 : 2 words$word))) in + (case arch of + SOME (RV64) => bindS + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . + let (mbits : riscv_sequential_types$satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) : 4 words$word)) in + (case ((satpMode_of_bits RV64 mbits)) of + SOME (m) => returnS m + | NONE => internal_error "invalid RV64 translation mode in satp" + )) + | _ => internal_error "unsupported address translation arch" + ))))`; + + +(*val translateAddr : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.ReadType -> Riscv_sequential_types.M Riscv_sequential_types.TR_Result*) + +val _ = Define ` + ((translateAddr:(64)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$ReadType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac rt= (bindS + (case rt of + Instruction => read_regS cur_privilege_ref + | Data => bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . + if (((((get_Mstatus_MPRV w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then bindS +(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . + returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) + else read_regS cur_privilege_ref) + ) (\ (effPriv : riscv_sequential_types$Privilege) . bindS +(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) . + let (mxr : bool) = + (((get_Mstatus_MXR w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in bindS +(read_regS mstatus_ref) (\ (w__6 : riscv_sequential_types$Mstatus) . + let (sum : bool) = + (((get_Mstatus_SUM w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in bindS +(translationMode effPriv) (\ (mode : riscv_sequential_types$SATPMode) . + (case mode of + Sbare => returnS (TR_Address vAddr) + | SV39 => bindS + (translate39 + ((subrange_vec_dec vAddr (( 38 : int): sail_values$ii) + (( 0 : int): sail_values$ii) : 39 words$word)) + ac effPriv mxr sum + ((SV39_LEVELS - (( 1 : int): sail_values$ii)))) + (\ (w__7 : riscv_sequential_types$TR39_Result) . + returnS + ((case w__7 of + TR39_Address (pa) => TR_Address + ((EXTZ + (( 64 : int): sail_values$ii) + pa : 64 words$word)) + | TR39_Failure (f) => TR_Failure + ((translationException ac f)) + ))) + )))))))`; + + +(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Riscv_sequential_types.ast*) + +(*val decodeCompressed : Machine_word.mword Machine_word.ty16 -> Maybe.maybe Riscv_sequential_types.ast*) + +(*val execute : Riscv_sequential_types.ast -> Riscv_sequential_types.M unit*) + +(*val print_insn : Riscv_sequential_types.ast -> string*) + +(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((extend_value:bool ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult ->((64)words$word)riscv_sequential_types$MemoryOpResult) is_unsigned value= + ((case value of + MemValue (v) => + MemValue (if is_unsigned then (EXTZ (( 64 : int):sail_values$ii) v : 64 words$word) + else (EXTS (( 64 : int):sail_values$ii) v : 64 words$word)) + | MemException (e) => MemException e + )))`; + + +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> bool -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rd addr value is_unsigned= + ((case ((extend_value is_unsigned value : ( 64 words$word) riscv_sequential_types$MemoryOpResult)) of + MemValue (result) => wX ((regbits_to_regno rd)) result + | MemException (e) => handle_mem_exception addr e + )))`; + + +(*val process_loadres : forall 'int8_times_n . Riscv_sequential_types.regbits -> Riscv_sequential_types.xlenbits -> Riscv_sequential_types.MemoryOpResult (Riscv_sequential_types.bits 'int8_times_n) -> bool -> unit*) + +(*val readCSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((readCSR:(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + (read_regS mvendorid_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + (read_regS marchid_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + (read_regS mimpid_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + (read_regS mhartid_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS +(read_regS mstatus_ref) (\ (w__4 : riscv_sequential_types$Mstatus) . returnS ((get_Mstatus w__4 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS medeleg_ref) (\ (w__5 : riscv_sequential_types$Medeleg) . returnS ((get_Medeleg w__5 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS +(read_regS mideleg_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) . + returnS ((get_Minterrupts w__6 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mie_ref) (\ (w__7 : riscv_sequential_types$Minterrupts) . + returnS ((get_Minterrupts w__7 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS +(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) . returnS ((get_Mtvec w__8 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (read_regS mscratch_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS mcause_ref) (\ (w__11 : riscv_sequential_types$Mcause) . returnS ((get_Mcause w__11 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (read_regS mtval_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mip_ref) (\ (w__13 : riscv_sequential_types$Minterrupts) . + returnS ((get_Minterrupts w__13 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS +(read_regS mstatus_ref) (\ (w__14 : riscv_sequential_types$Mstatus) . + returnS ((get_Mstatus w__14 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS sedeleg_ref) (\ (w__15 : riscv_sequential_types$Sedeleg) . + returnS ((get_Sedeleg w__15 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS +(read_regS sideleg_ref) (\ (w__16 : riscv_sequential_types$Sinterrupts) . + returnS ((get_Sinterrupts w__16 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mie_ref) (\ (w__17 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mideleg_ref) (\ (w__18 : riscv_sequential_types$Minterrupts) . + returnS ((get_Sinterrupts ((lower_mie w__17 w__18)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS +(read_regS stvec_ref) (\ (w__19 : riscv_sequential_types$Mtvec) . returnS ((get_Mtvec w__19 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (read_regS sscratch_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS scause_ref) (\ (w__22 : riscv_sequential_types$Mcause) . returnS ((get_Mcause w__22 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (read_regS stval_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mip_ref) (\ (w__24 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mideleg_ref) (\ (w__25 : riscv_sequential_types$Minterrupts) . + returnS ((get_Sinterrupts ((lower_mip w__24 w__25)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (read_regS mtime_ref : ( 64 words$word) riscv_sequential_types$M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (read_regS minstret_ref : ( 64 words$word) riscv_sequential_types$M) + else + let (_ : unit) = (print_bits "unhandled read to CSR " csr) in + returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)))`; + + +(*val writeCSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((writeCSR:(12)words$word ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (value : riscv_sequential_types$xlenbits)= + (let b__0 = csr in bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS +(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . bindS (seqS +(write_regS mstatus_ref ((legalize_mstatus w__0 value))) +(read_regS mstatus_ref)) (\ (w__1 : riscv_sequential_types$Mstatus) . + returnS (SOME ((get_Mstatus w__1 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS medeleg_ref) (\ (w__2 : riscv_sequential_types$Medeleg) . bindS (seqS +(write_regS medeleg_ref ((legalize_medeleg w__2 value))) +(read_regS medeleg_ref)) (\ (w__3 : riscv_sequential_types$Medeleg) . + returnS (SOME ((get_Medeleg w__3 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS +(read_regS mideleg_ref) (\ (w__4 : riscv_sequential_types$Minterrupts) . bindS (seqS +(write_regS mideleg_ref ((legalize_mideleg w__4 value))) +(read_regS mideleg_ref)) (\ (w__5 : riscv_sequential_types$Minterrupts) . + returnS (SOME ((get_Minterrupts w__5 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mie_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) . bindS (seqS +(write_regS mie_ref ((legalize_mie w__6 value))) +(read_regS mie_ref)) (\ (w__7 : riscv_sequential_types$Minterrupts) . + returnS (SOME ((get_Minterrupts w__7 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS +(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) . bindS (seqS +(write_regS mtvec_ref ((legalize_tvec w__8 value))) +(read_regS mtvec_ref)) (\ (w__9 : riscv_sequential_types$Mtvec) . + returnS (SOME ((get_Mtvec w__9 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS (seqS +(write_regS mscratch_ref value) + (read_regS mscratch_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__10 : 64 words$word) . + returnS (SOME w__10)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then bindS + (legalize_xepc value : ( 64 words$word) riscv_sequential_types$M) (\ (w__11 : riscv_sequential_types$xlenbits) . bindS (seqS +(write_regS mepc_ref w__11) + (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__12 : 64 words$word) . returnS (SOME w__12))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS (seqS +(set_Mcause mcause_ref value) +(read_regS mcause_ref)) (\ (w__13 : riscv_sequential_types$Mcause) . + returnS (SOME ((get_Mcause w__13 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS +(write_regS mtval_ref value) + (read_regS mtval_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__14 : 64 words$word) . returnS (SOME w__14)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mip_ref) (\ (w__15 : riscv_sequential_types$Minterrupts) . bindS (seqS +(write_regS mip_ref ((legalize_mip w__15 value))) +(read_regS mip_ref)) (\ (w__16 : riscv_sequential_types$Minterrupts) . + returnS (SOME ((get_Minterrupts w__16 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS +(read_regS mstatus_ref) (\ (w__17 : riscv_sequential_types$Mstatus) . bindS (seqS +(write_regS mstatus_ref ((legalize_sstatus w__17 value))) +(read_regS mstatus_ref)) (\ (w__18 : riscv_sequential_types$Mstatus) . + returnS (SOME ((get_Mstatus w__18 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS +(read_regS sedeleg_ref) (\ (w__19 : riscv_sequential_types$Sedeleg) . bindS (seqS +(write_regS sedeleg_ref ((legalize_sedeleg w__19 value))) +(read_regS sedeleg_ref)) (\ (w__20 : riscv_sequential_types$Sedeleg) . + returnS (SOME ((get_Sedeleg w__20 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS +(set_Sinterrupts sideleg_ref value) +(read_regS sideleg_ref)) (\ (w__21 : riscv_sequential_types$Sinterrupts) . + returnS (SOME ((get_Sinterrupts w__21 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mie_ref) (\ (w__22 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mideleg_ref) (\ (w__23 : riscv_sequential_types$Minterrupts) . bindS (seqS +(write_regS mie_ref ((legalize_sie w__22 w__23 value))) +(read_regS mie_ref)) (\ (w__24 : riscv_sequential_types$Minterrupts) . + returnS (SOME ((get_Minterrupts w__24 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS +(read_regS stvec_ref) (\ (w__25 : riscv_sequential_types$Mtvec) . bindS (seqS +(write_regS stvec_ref ((legalize_tvec w__25 value))) +(read_regS stvec_ref)) (\ (w__26 : riscv_sequential_types$Mtvec) . + returnS (SOME ((get_Mtvec w__26 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS (seqS +(write_regS sscratch_ref value) + (read_regS sscratch_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__27 : 64 words$word) . + returnS (SOME w__27)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then bindS + (legalize_xepc value : ( 64 words$word) riscv_sequential_types$M) (\ (w__28 : riscv_sequential_types$xlenbits) . bindS (seqS +(write_regS sepc_ref w__28) + (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__29 : 64 words$word) . returnS (SOME w__29))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS (seqS +(set_Mcause scause_ref value) +(read_regS scause_ref)) (\ (w__30 : riscv_sequential_types$Mcause) . + returnS (SOME ((get_Mcause w__30 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS +(write_regS stval_ref value) + (read_regS stval_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__31 : 64 words$word) . returnS (SOME w__31)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS +(read_regS mip_ref) (\ (w__32 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mideleg_ref) (\ (w__33 : riscv_sequential_types$Minterrupts) . bindS (seqS +(write_regS mip_ref ((legalize_sip w__32 w__33 value))) +(read_regS mip_ref)) (\ (w__34 : riscv_sequential_types$Minterrupts) . + returnS (SOME ((get_Minterrupts w__34 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS +(cur_Architecture () ) (\ (w__35 : riscv_sequential_types$Architecture) . bindS + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__36 : 64 words$word) . bindS (seqS +(write_regS satp_ref ((legalize_satp w__35 w__36 value : 64 words$word))) + (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__37 : 64 words$word) . returnS (SOME w__37)))) + else returnS NONE) (\ (res : riscv_sequential_types$xlenbits option) . + returnS ((case res of + SOME (v) => + prerr_endline + ((STRCAT "CSR " + ((STRCAT ((csr_name csr)) + ((STRCAT " <- " + ((STRCAT ((string_of_vec v)) + ((STRCAT " (input: " + ((STRCAT ((string_of_vec value)) ")")))))))))))) + | NONE => print_bits "unhandled write to CSR " csr + )))))`; + + +(*val signalIllegalInstruction : unit -> Riscv_sequential_types.M unit*) + +val _ = Define ` + ((signalIllegalInstruction:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (not_implemented "illegal instruction"))`; + + +val _ = Define ` + ((decode:(32)words$word ->(riscv_sequential_types$ast)option) v__0= + (if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (UTYPE (imm,rd,RISCV_LUI)) + else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (UTYPE (imm,rd,RISCV_AUIPC)) + else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) + ((concat_vec + ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm (( 18 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 6 words$word)) + ((concat_vec + ((subrange_vec_dec imm (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 20 words$word)) + : 21 words$word),rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RISCV_JALR (imm,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BEQ)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BNE)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BLT)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BGE)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BLTU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BGEU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ADDI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_SLTI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_XORI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ORI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ANDI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_ADD)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SUB)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLL)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_XOR)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SRL)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SRA)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_OR)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_AND)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,DOUBLE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (ADDIW (imm,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,F,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (DIV0 (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (DIV0 (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (REM (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (REM (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (MULW (rs2,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (DIVW (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (DIVW (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (REMW (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (REMW (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : 20 words$word))))))) then + let (pred : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 27 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 4 words$word)) in + let (succ : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 23 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 4 words$word)) in + SOME (FENCE (pred,succ)) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : 32 words$word)))) then + SOME (FENCEI () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (ECALL () ) + else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (MRET () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (SRET () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (EBREAK () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (WFI () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word))))))) + then + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + SOME (SFENCE_VMA (rs1,rs2)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRW)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRS)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRC)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRW)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRS)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRC)) + else NONE))`; + + +val _ = Define ` + ((decodeCompressed:(16)words$word ->(riscv_sequential_types$ast)option) v__418= + (if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi1 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (nzi0 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + if ((((((nzi1 = (vec_of_bits [B0] : 1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) then + SOME (NOP () ) + else NONE + else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + SOME (ILLEGAL () ) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (nz54 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 2 words$word)) in + let (nz96 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 4 words$word)) in + let (nz2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in + let (nz3 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let nzimm = +((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word)) + : 8 words$word)) in + if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then NONE + else SOME (C_ADDI4SPN (rd,nzimm)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in + let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in + let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in + SOME (C_LW (uimm,rs1,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in + let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in + let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in + SOME (C_LD (uimm,rs1,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in + let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in + let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in + SOME (C_SW (uimm,rs1,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in + let (rs1 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in + let (rs2 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in + SOME (C_SD (uimm,rs1,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (nzi40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let nzi = ((concat_vec nzi5 nzi40 : 6 words$word)) in + if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_ADDI (nzi,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + SOME (C_ADDIW ((concat_vec imm5 imm40 : 6 words$word),rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LI ((concat_vec imm5 imm40 : 6 words$word),rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi9 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (nzi4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in + let (nzi6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in + let (nzi87 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in + let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in + let nzimm = +((concat_vec nzi9 + ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word)) + : 5 words$word)) + : 6 words$word)) in + if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_ADDI16SP nzimm) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm17 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (imm1612 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then + NONE + else SOME (C_LUI ((concat_vec imm17 imm1612 : 6 words$word),rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_SRLI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_SRAI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (i40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + SOME (C_ANDI ((concat_vec i5 i40 : 6 words$word),rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_SUB (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_XOR (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_OR (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_AND (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_SUBW (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + SOME (C_ADDW (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i11 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (i4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)) in + let (i98 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 2 words$word)) in + let (i10 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)) in + let (i6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)) in + let (i7 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in + let (i31 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 3 words$word)) in + let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in + SOME (C_J ((concat_vec i11 + ((concat_vec i10 + ((concat_vec i98 + ((concat_vec i7 + ((concat_vec i6 + ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 9 words$word)) + : 10 words$word)) + : 11 words$word))) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) in + let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in + let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in + let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in + SOME (C_BEQZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) + : 7 words$word)) + : 8 words$word),rs)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) in + let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in + let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in + let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in + SOME (C_BNEZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) + : 7 words$word)) + : 8 words$word),rs)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_SLLI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (ui42 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 3 words$word)) in + let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 3 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 2 words$word)) in + let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LWSP (uimm,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (ui43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in + let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in + let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LDSP (uimm,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui52 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 4 words$word)) in + let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 2 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ui52 : 6 words$word)) in + SOME (C_SWSP (uimm,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in + let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ui53 : 6 words$word)) in + SOME (C_SDSP (uimm,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_JR rs1) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_JALR rs1) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_MV (rd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in + let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in + if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_ADD (rsd,rs2)) + else NONE))`; + + +(*val execute_WFI : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_WFI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__110= (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . + (case w__0 of + Machine => returnS () + | Supervisor => bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . + if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + handle_illegal () + else returnS () ) + | User => handle_illegal () + ))))`; + + +(*val execute_UTYPE : Machine_word.mword Machine_word.ty20 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.uop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_UTYPE:(20)words$word ->(5)words$word -> riscv_sequential_types$uop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd op= + (let (off : riscv_sequential_types$xlenbits) = +((EXTS (( 64 : int):sail_values$ii) + ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 32 words$word)) + : 64 words$word)) in bindS + (case op of + RISCV_LUI => returnS off + | RISCV_AUIPC => bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + returnS ((add_vec w__0 off : 64 words$word))) + ) (\ (ret : riscv_sequential_types$xlenbits) . + wX ((regbits_to_regno rd)) ret)))`; + + +(*val execute_STORECON : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (bindS +(speculate_conditional_success () ) (\ (w__0 : bool) . + let (status : 1 riscv_sequential_types$bits) = +(if w__0 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in seqS +(wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):sail_values$ii) status : 64 words$word))) +(if (((status = (vec_of_bits [B1] : 1 words$word)))) then returnS () + else bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS +(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => bindS + (case width of + WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl T + | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . bindS + (case width of + WORD => + mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + aq rl T + | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . + (case res of + MemValue (_) => returnS () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))))`; + + +(*val execute_STORE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in bindS +(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => bindS + (case width of + BYTE => mem_write_ea addr (( 1 : int):sail_values$ii) aq rl F + | HALF => mem_write_ea addr (( 2 : int):sail_values$ii) aq rl F + | WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl F + | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl F + ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . bindS + (case width of + BYTE => + mem_write_value addr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) aq + rl F + | HALF => + mem_write_value addr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) aq + rl F + | WORD => + mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) aq + rl F + | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl F + ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . + (case res of + MemValue (_) => returnS () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))`; + + +(*val execute_SRET : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_SRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__108= (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . + (case w__0 of + User => handle_illegal () + | Supervisor => bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . + if (((((get_Mstatus_TSR w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + handle_illegal () + else bindS +(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . bindS + (handle_exception w__2 (CTL_SRET () ) w__3 : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__4)))) + | Machine => bindS +(read_regS cur_privilege_ref) (\ (w__5 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . bindS + (handle_exception w__5 (CTL_SRET () ) w__6 : ( 64 words$word) riscv_sequential_types$M) (\ (w__7 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__7))) + ))))`; + + +(*val execute_SHIFTW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in + let (result : 32 riscv_sequential_types$bits) = +((case op of + RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word) + | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result : 64 words$word)))))`; + + +(*val execute_SHIFTIOP : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . + let (result : riscv_sequential_types$xlenbits) = +((case op of + RISCV_SLLI => (shift_bits_left rs1_val shamt : 64 words$word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt : 64 words$word) + | RISCV_SRAI => (shift_right_arith64 rs1_val shamt : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result)))`; + + +(*val execute_SFENCE_VMA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs1 rs2= (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . + if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) + then + handle_illegal () + else bindS +(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS +(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . + let p__104 = + (architecture ((get_Mstatus_SXL w__1 : 2 words$word)), (get_Mstatus_TVM w__2 : 1 words$word)) in + (case p__104 of + (SOME (RV64), v_0) => + if (((v_0 = ((bool_to_bits T : 1 words$word))))) then handle_illegal () + else bindS + (if (((((regbits_to_regno rs1)) = (( 0 : int):sail_values$ii)))) then returnS NONE + else bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . + returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 39 words$word))))) (\ (addr : + riscv_sequential_types$vaddr39 option) . bindS + (if (((((regbits_to_regno rs2)) = (( 0 : int):sail_values$ii)))) then returnS NONE + else bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : 64 words$word) . + returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word))))) (\ (asid : + riscv_sequential_types$asid64 option) . + flushTLB asid addr)) + | (g__102, g__103) => internal_error "unimplemented sfence architecture" + ))))))`; + + +(*val execute_RTYPEW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.ropw -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$ropw ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in + let (result : 32 riscv_sequential_types$bits) = +((case op of + RISCV_ADDW => (add_vec rs1_val rs2_val : 32 words$word) + | RISCV_SUBW => (sub_vec rs1_val rs2_val : 32 words$word) + | RISCV_SLLW => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) + : 32 words$word) + | RISCV_SRLW => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) + : 32 words$word) + | RISCV_SRAW => + (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) + : 32 words$word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result : 64 words$word))))))`; + + +(*val execute_RTYPE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.rop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$rop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . + let (result : riscv_sequential_types$xlenbits) = +((case op of + RISCV_ADD => (add_vec rs1_val rs2_val : 64 words$word) + | RISCV_SUB => (sub_vec rs1_val rs2_val : 64 words$word) + | RISCV_SLL => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + : 64 words$word) + | RISCV_SLT => + (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val)))) : 1 words$word)) : 64 words$word) + | RISCV_SLTU => + (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui rs2_val)))) : 1 words$word)) : 64 words$word) + | RISCV_XOR => (xor_vec rs1_val rs2_val : 64 words$word) + | RISCV_SRL => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + : 64 words$word) + | RISCV_SRA => + (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) + : 64 words$word) + | RISCV_OR => (or_vec rs1_val rs2_val : 64 words$word) + | RISCV_AND => (and_vec rs1_val rs2_val : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_RISCV_JALR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd= (bindS + (read_regS nextPC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . bindS (seqS +(wX ((regbits_to_regno rd)) w__0) + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M)) (\ (w__1 : 64 words$word) . + let (newPC : riscv_sequential_types$xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in + write_regS + nextPC_ref + ((concat_vec ((subrange_vec_dec newPC (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 63 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 64 words$word))))))`; + + +(*val execute_RISCV_JAL : Machine_word.mword Machine_word.ty21 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd= (bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (pc : riscv_sequential_types$xlenbits) . bindS + (read_regS nextPC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . seqS +(wX ((regbits_to_regno rd)) w__0) +(let (offset : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) in + write_regS nextPC_ref ((add_vec pc offset : 64 words$word)))))))`; + + +(*val execute_REMW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in + let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) r : 32 words$word)) : 64 words$word))))))`; + + +(*val execute_REM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . + let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((to_bits xlen r : 64 words$word))))))`; + + +(*val execute_NOP : unit -> unit*) + + val _ = Define ` + ((execute_NOP:unit -> unit) g__111= () )`; + + +(*val execute_MULW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in + let (rs1_int : sail_values$ii) = (integer_word$w2i rs1_val) in + let (rs2_int : sail_values$ii) = (integer_word$w2i rs2_val) in + let result32 = +((subrange_vec_dec ((to_bits (( 64 : int):sail_values$ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):sail_values$ii) + (( 0 : int):sail_values$ii) + : 32 words$word)) in + let (result : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) result32 : 64 words$word)) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> bool -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . + let (rs1_int : sail_values$ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : sail_values$ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let result128 = ((to_bits (( 128 : int):sail_values$ii) ((rs1_int * rs2_int)) : 128 words$word)) in + let result = +(if high then (subrange_vec_dec result128 (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word) + else (subrange_vec_dec result128 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_MRET : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_MRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__107= (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . + if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) + then bindS +(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : 64 words$word) . bindS + (handle_exception w__1 (CTL_MRET () ) w__2 : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__3))) + else handle_illegal () )))`; + + +(*val execute_LOADRES : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_LOADRES:bool -> bool ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs1 width rd= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS +(translateAddr vaddr Read Data) (\ (w__0 : riscv_sequential_types$TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => bindS + (mem_read addr (( 4 : int):sail_values$ii) aq rl T : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__1 : ( 32 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd addr w__1 F) + | DOUBLE => bindS + (mem_read addr (( 8 : int):sail_values$ii) aq rl T : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 64 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd addr w__2 F) + | _ => internal_error "LOADRES expected WORD or DOUBLE" + ) + )))))`; + + +(*val execute_LOAD : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in bindS +(translateAddr vaddr Read Data) (\ (w__1 : riscv_sequential_types$TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => bindS + (mem_read addr (( 1 : int):sail_values$ii) aq rl F : ( ( 8 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 8 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => bindS + (mem_read addr (( 2 : int):sail_values$ii) aq rl F : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__3 : ( 16 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd vaddr w__3 is_unsigned) + | WORD => bindS + (mem_read addr (( 4 : int):sail_values$ii) aq rl F : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | DOUBLE => bindS + (mem_read addr (( 8 : int):sail_values$ii) aq rl F : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word) + riscv_sequential_types$MemoryOpResult) . + process_load rd vaddr w__5 is_unsigned) + ) + )))))`; + + +(*val execute_ITYPE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.iop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$iop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . + let (immext : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) in + let (result : riscv_sequential_types$xlenbits) = +((case op of + RISCV_ADDI => (add_vec rs1_val immext : 64 words$word) + | RISCV_SLTI => + (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i immext)))) : 1 words$word)) : 64 words$word) + | RISCV_SLTIU => + (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui immext)))) : 1 words$word)) : 64 words$word) + | RISCV_XORI => (xor_vec rs1_val immext : 64 words$word) + | RISCV_ORI => (or_vec rs1_val immext : 64 words$word) + | RISCV_ANDI => (and_vec rs1_val immext : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result)))`; + + +(*val execute_ILLEGAL : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_ILLEGAL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__112= (handle_illegal () ))`; + + +(*val execute_FENCEI : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_FENCEI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__105= (MEM_fence_i () ))`; + + +(*val execute_FENCE : Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_FENCE:(4)words$word ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) pred succ= + ((case (pred, succ) of + (b__0, b__1) => + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then + MEM_fence_rw_rw () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then + MEM_fence_r_rw () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then + MEM_fence_r_r () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then + MEM_fence_rw_w () else MEM_fence_w_w () + )))`; + + +(*val execute_ECALL : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_ECALL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__106= (bindS +(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . + let (t : riscv_sequential_types$sync_exception) = +(<| sync_exception_trap := + ((case w__0 of + User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + )); + sync_exception_excinfo := NONE |>) in bindS +(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : 64 words$word) . bindS + (handle_exception w__1 (CTL_TRAP t) w__2 : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . + write_regS nextPC_ref w__3))))))`; + + +(*val execute_EBREAK : unit -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_EBREAK:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__109= (throwS (Error_EBREAK () )))`; + + +(*val execute_DIVW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in + let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in + let (q' : sail_values$ii) = +(if (((s /\ ((q > ((((pow2 (( 31 : int):sail_values$ii))) - (( 1 : int):sail_values$ii)))))))) then + (( 0 : int):sail_values$ii) - ((ex_int ((pow0 (( 2 : int):sail_values$ii) (( 31 : int):sail_values$ii))))) + else q) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) q' : 32 words$word)) : 64 words$word))))))`; + + +(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . + let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in + let (q' : sail_values$ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in + wX ((regbits_to_regno rd)) ((to_bits xlen q' : 64 words$word))))))`; + + +(*val execute_C_ADDIW : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rsd= + (let (imm : 32 riscv_sequential_types$bits) = ((EXTS (( 32 : int):sail_values$ii) imm : 32 words$word)) in bindS + (rX ((regbits_to_regno rsd)) : ( 64 words$word) riscv_sequential_types$M) (\ rs_val . + let (res : 32 riscv_sequential_types$bits) = +((add_vec ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) imm : 32 words$word)) in + wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):sail_values$ii) res : 64 words$word)))))`; + + +(*val execute_CSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.csrop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$csrop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op= (bindS + (if is_imm then returnS ((EXTZ (( 64 : int):sail_values$ii) rs1 : 64 words$word)) + else (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M)) (\ (rs1_val : riscv_sequential_types$xlenbits) . + let (isWrite : bool) = +((case op of + CSRRW => T + | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):sail_values$ii)) else (((lem$w2ui rs1)) <> (( 0 : int):sail_values$ii)) + )) in bindS +(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS +(check_CSR csr w__1 isWrite) (\ (w__2 : bool) . + if ((~ w__2)) then handle_illegal () + else bindS + (readCSR csr : ( 64 words$word) riscv_sequential_types$M) (\ csr_val . seqS + (if isWrite then + let (new_val : riscv_sequential_types$xlenbits) = +((case op of + CSRRW => rs1_val + | CSRRS => (or_vec csr_val rs1_val : 64 words$word) + | CSRRC => (and_vec csr_val ((not_vec rs1_val : 64 words$word)) : 64 words$word) + )) in + writeCSR csr new_val + else returnS () ) +(wX ((regbits_to_regno rd)) csr_val)))))))`; + + +(*val execute_BTYPE : Machine_word.mword Machine_word.ty13 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.bop -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$bop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 op= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . + let (taken : bool) = +((case op of + RISCV_BEQ => (rs1_val = rs2_val) + | RISCV_BNE => (rs1_val <> rs2_val) + | RISCV_BLT => ((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val)) + | RISCV_BGE => ((integer_word$w2i rs1_val) >= (integer_word$w2i rs2_val)) + | RISCV_BLTU => ((lem$w2ui rs1_val) < (lem$w2ui rs2_val)) + | RISCV_BGEU => ((lem$w2ui rs1_val) >= (lem$w2ui rs2_val)) + )) in + if taken then bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word))) + else returnS () ))))`; + + +(*val execute_AMO : Riscv_sequential_types.amoop -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_AMO:riscv_sequential_types$amoop -> bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS +(translateAddr vaddr ReadWrite Data) (\ (w__0 : riscv_sequential_types$TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => bindS + (case width of + WORD => mem_write_ea addr (( 4 : int):sail_values$ii) (((aq /\ rl))) rl T + | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) (((aq /\ rl))) rl T + | _ => internal_error "AMO expected WORD or DOUBLE" + ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => bindS + (case width of + WORD => bindS + (mem_read addr (( 4 : int):sail_values$ii) aq (((aq /\ rl))) T : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word) + riscv_sequential_types$MemoryOpResult) . + returnS ((extend_value F w__4 : ( 64 words$word) riscv_sequential_types$MemoryOpResult))) + | DOUBLE => bindS + (mem_read addr (( 8 : int):sail_values$ii) aq (((aq /\ rl))) T : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word) + riscv_sequential_types$MemoryOpResult) . + returnS ((extend_value F w__5 : ( 64 words$word) riscv_sequential_types$MemoryOpResult))) + | _ => (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) + ) (\ (rval : riscv_sequential_types$xlenbits riscv_sequential_types$MemoryOpResult) . + (case rval of + MemException (e) => handle_mem_exception addr e + | MemValue (loaded) => bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (rs2_val : riscv_sequential_types$xlenbits) . + let (result : riscv_sequential_types$xlenbits) = +((case op of + AMOSWAP => rs2_val + | AMOADD => (add_vec rs2_val loaded : 64 words$word) + | AMOXOR => (xor_vec rs2_val loaded : 64 words$word) + | AMOAND => (and_vec rs2_val loaded : 64 words$word) + | AMOOR => (or_vec rs2_val loaded : 64 words$word) + | AMOMIN => (vector64 ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) + | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) + | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) + | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) + )) in bindS + (case width of + WORD => + mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) + (((aq /\ rl))) rl T + | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) result (((aq /\ rl))) rl T + | _ => internal_error "AMO expected WORD or DOUBLE" + ) (\ (wval : unit riscv_sequential_types$MemoryOpResult) . + (case wval of + MemValue (_) => wX ((regbits_to_regno rd)) loaded + | MemException (e) => handle_mem_exception addr e + ))) + )) + )) + )))))`; + + +(*val execute_ADDIW : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) + + val _ = Define ` + ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd= (bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . + let (result : riscv_sequential_types$xlenbits) = ((add_vec ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) w__0 : 64 words$word)) in + wX ((regbits_to_regno rd)) + ((EXTS (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; + + + val execute_defn = Hol_defn "execute" ` + ((execute:riscv_sequential_types$ast ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) merge_var= + ((case merge_var of + C_ADDI4SPN (rdc,nzimm) => + let (imm : 12 riscv_sequential_types$bits) = +((concat_vec (vec_of_bits [B0;B0] : 2 words$word) + ((concat_vec nzimm (vec_of_bits [B0;B0] : 2 words$word) : 10 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + execute (ITYPE (imm,sp,rd,RISCV_ADDI)) + | C_LW (uimm,rsc,rdc) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + let rs = ((creg2reg_bits rsc : 5 words$word)) in + execute (LOAD (imm,rs,rd,F,WORD,F,F)) + | C_LD (uimm,rsc,rdc) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + let rs = ((creg2reg_bits rsc : 5 words$word)) in + execute (LOAD (imm,rs,rd,F,DOUBLE,F,F)) + | C_SW (uimm,rsc1,rsc2) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) + : 12 words$word)) in + let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in + let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in + execute (STORE (imm,rs2,rs1,WORD,F,F)) + | C_SD (uimm,rsc1,rsc2) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) + : 12 words$word)) in + let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in + let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in + execute (STORE (imm,rs2,rs1,DOUBLE,F,F)) + | C_ADDI (nzi,rsd) => + let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) nzi : 12 words$word)) in + execute (ITYPE (imm,rsd,rsd,RISCV_ADDI)) + | C_JAL (imm) => + execute + (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) + : 21 words$word),ra)) + | C_LI (imm,rd) => + let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) imm : 12 words$word)) in + execute (ITYPE (imm,zreg,rd,RISCV_ADDI)) + | C_ADDI16SP (imm) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTS (( 12 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 10 words$word)) + : 12 words$word)) in + execute (ITYPE (imm,sp,sp,RISCV_ADDI)) + | C_LUI (imm,rd) => + let (res : 20 riscv_sequential_types$bits) = ((EXTS (( 20 : int):sail_values$ii) imm : 20 words$word)) in + execute (UTYPE (res,rd,RISCV_LUI)) + | C_SRLI (shamt,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI)) + | C_SRAI (shamt,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI)) + | C_ANDI (imm,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (ITYPE ((EXTS (( 12 : int):sail_values$ii) imm : 12 words$word),rsd,rsd,RISCV_ANDI)) + | C_SUB (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_SUB)) + | C_XOR (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_XOR)) + | C_OR (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_OR)) + | C_AND (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_AND)) + | C_SUBW (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW)) + | C_ADDW (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW)) + | C_J (imm) => + execute + (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) + : 21 words$word),zreg)) + | C_BEQZ (imm,rs) => + execute + (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) + : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BEQ)) + | C_BNEZ (imm,rs) => + execute + (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) + : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BNE)) + | C_SLLI (shamt,rsd) => execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI)) + | C_LWSP (uimm,rd) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) + : 12 words$word)) in + execute (LOAD (imm,sp,rd,F,WORD,F,F)) + | C_LDSP (uimm,rd) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) + : 12 words$word)) in + execute (LOAD (imm,sp,rd,F,DOUBLE,F,F)) + | C_SWSP (uimm,rs2) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) + : 12 words$word)) in + execute (STORE (imm,rs2,sp,WORD,F,F)) + | C_SDSP (uimm,rs2) => + let (imm : 12 riscv_sequential_types$bits) = +((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) + : 12 words$word)) in + execute (STORE (imm,rs2,sp,DOUBLE,F,F)) + | C_JR (rs1) => + execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,zreg)) + | C_JALR (rs1) => + execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,ra)) + | C_MV (rd,rs2) => execute (RTYPE (rs2,zreg,rd,RISCV_ADD)) + | C_ADD (rsd,rs2) => execute (RTYPE (rs2,rsd,rsd,RISCV_ADD)) + | UTYPE (imm,rd,op) => execute_UTYPE imm rd op + | RISCV_JAL (imm,rd) => execute_RISCV_JAL imm rd + | RISCV_JALR (imm,rs1,rd) => execute_RISCV_JALR imm rs1 rd + | BTYPE (imm,rs2,rs1,op) => execute_BTYPE imm rs2 rs1 op + | ITYPE (imm,rs1,rd,op) => execute_ITYPE imm rs1 rd op + | SHIFTIOP (shamt,rs1,rd,op) => execute_SHIFTIOP shamt rs1 rd op + | RTYPE (rs2,rs1,rd,op) => execute_RTYPE rs2 rs1 rd op + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => execute_LOAD imm rs1 rd is_unsigned width aq rl + | STORE (imm,rs2,rs1,width,aq,rl) => execute_STORE imm rs2 rs1 width aq rl + | ADDIW (imm,rs1,rd) => execute_ADDIW imm rs1 rd + | SHIFTW (shamt,rs1,rd,op) => execute_SHIFTW shamt rs1 rd op + | RTYPEW (rs2,rs1,rd,op) => execute_RTYPEW rs2 rs1 rd op + | MUL (rs2,rs1,rd,high,signed1,signed2) => execute_MUL rs2 rs1 rd high signed1 signed2 + | DIV0 (rs2,rs1,rd,s) => execute_DIV rs2 rs1 rd s + | REM (rs2,rs1,rd,s) => execute_REM rs2 rs1 rd s + | MULW (rs2,rs1,rd) => execute_MULW rs2 rs1 rd + | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s + | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s + | FENCE (pred,succ) => execute_FENCE pred succ + | FENCEI (g__105) => execute_FENCEI g__105 + | ECALL (g__106) => execute_ECALL g__106 + | MRET (g__107) => execute_MRET g__107 + | SRET (g__108) => execute_SRET g__108 + | EBREAK (g__109) => execute_EBREAK g__109 + | WFI (g__110) => execute_WFI g__110 + | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2 + | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd + | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd + | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd + | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op + | NOP (g__111) => returnS ((execute_NOP g__111)) + | ILLEGAL (g__112) => execute_ILLEGAL g__112 + | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn; + +val _ = Define ` + ((print_insn:riscv_sequential_types$ast -> string) merge_var= + ((case merge_var of + UTYPE (imm,rd,op) => + (case op of + RISCV_LUI => + STRCAT "lui " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | RISCV_AUIPC => + STRCAT "auipc " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + ) + | RISCV_JAL (imm,rd) => + STRCAT "jal " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | RISCV_JALR (imm,rs1,rd) => + STRCAT "jalr " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | BTYPE (imm,rs2,rs1,op) => + let (insn : string) = +((case op of + RISCV_BEQ => "beq " + | RISCV_BNE => "bne " + | RISCV_BLT => "blt " + | RISCV_BGE => "bge " + | RISCV_BLTU => "bltu " + | RISCV_BGEU => "bgeu " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rs1)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | ITYPE (imm,rs1,rd,op) => + let (insn : string) = +((case op of + RISCV_ADDI => "addi " + | RISCV_SLTI => "slti " + | RISCV_SLTIU => "sltiu " + | RISCV_XORI => "xori " + | RISCV_ORI => "ori " + | RISCV_ANDI => "andi " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | SHIFTIOP (shamt,rs1,rd,op) => + let (insn : string) = +((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + | RTYPE (rs2,rs1,rd,op) => + let (insn : string) = +((case op of + RISCV_ADD => "add " + | RISCV_SUB => "sub " + | RISCV_SLL => "sll " + | RISCV_SLT => "slt " + | RISCV_SLTU => "sltu " + | RISCV_XOR => "xor " + | RISCV_SRL => "srl " + | RISCV_SRA => "sra " + | RISCV_OR => "or " + | RISCV_AND => "and " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => + let (insn : string) = +((case (width, is_unsigned) of + (BYTE, F) => "lb " + | (BYTE, T) => "lbu " + | (HALF, F) => "lh " + | (HALF, T) => "lhu " + | (WORD, F) => "lw " + | (WORD, T) => "lwu " + | (_, _) => "ld.bad " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | STORE (imm,rs2,rs1,width,aq,rl) => + let (insn : string) = +((case width of + BYTE => "sb " + | HALF => "sh " + | WORD => "sw " + | DOUBLE => "sd " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rs2)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | ADDIW (imm,rs1,rd) => + STRCAT "addiw " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | SHIFTW (shamt,rs1,rd,op) => + let (insn : string) = +((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + | RTYPEW (rs2,rs1,rd,op) => + let (insn : string) = +((case op of + RISCV_ADDW => "addw " + | RISCV_SUBW => "subw " + | RISCV_SLLW => "sllw " + | RISCV_SRLW => "srlw " + | RISCV_SRAW => "sraw " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + let (insn : string) = +((case (high, signed1, signed2) of + (F, T, T) => "mul " + | (T, T, T) => "mulh " + | (T, T, F) => "mulhsu " + | (T, F, F) => "mulhu" + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | DIV0 (rs2,rs1,rd,s) => + let (insn : string) = (if s then "div " else "divu ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | REM (rs2,rs1,rd,s) => + let (insn : string) = (if s then "rem " else "remu ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | MULW (rs2,rs1,rd) => + STRCAT "mulw " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | DIVW (rs2,rs1,rd,s) => + let (insn : string) = (if s then "divw " else "divuw ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | REMW (rs2,rs1,rd,s) => + let (insn : string) = (if s then "remw " else "remuw ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | FENCE (pred,succ) => "fence" + | FENCEI (g__93) => "fence.i" + | ECALL (g__94) => "ecall" + | MRET (g__95) => "mret" + | SRET (g__96) => "sret" + | EBREAK (g__97) => "ebreak" + | WFI (g__98) => "wfi" + | SFENCE_VMA (rs1,rs2) => + STRCAT "sfence.vma " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))) + | LOADRES (aq,rl,rs1,width,rd) => + let (insn : string) = +((case width of WORD => "lr.w " | DOUBLE => "lr.d " | _ => "lr.bad " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1)))))) + | STORECON (aq,rl,rs2,rs1,width,rd) => + let (insn : string) = +((case width of WORD => "sc.w " | DOUBLE => "sc.d " | _ => "sc.bad " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + let (insn : string) = +((case (op, width) of + (AMOSWAP, WORD) => "amoswap.w " + | (AMOADD, WORD) => "amoadd.w " + | (AMOXOR, WORD) => "amoxor.w " + | (AMOAND, WORD) => "amoand.w " + | (AMOOR, WORD) => "amoor.w " + | (AMOMIN, WORD) => "amomin.w " + | (AMOMAX, WORD) => "amomax.w " + | (AMOMINU, WORD) => "amominu.w " + | (AMOMAXU, WORD) => "amomaxu.w " + | (AMOSWAP, DOUBLE) => "amoswap.d " + | (AMOADD, DOUBLE) => "amoadd.d " + | (AMOXOR, DOUBLE) => "amoxor.d " + | (AMOAND, DOUBLE) => "amoand.d " + | (AMOOR, DOUBLE) => "amoor.d " + | (AMOMIN, DOUBLE) => "amomin.d " + | (AMOMAX, DOUBLE) => "amomax.d " + | (AMOMINU, DOUBLE) => "amominu.d " + | (AMOMAXU, DOUBLE) => "amomaxu.d " + | (_, _) => "amo.bad " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | CSR (csr,rs1,rd,is_imm,op) => + let (insn : string) = +((case (op, is_imm) of + (CSRRW, T) => "csrrwi " + | (CSRRW, F) => "csrrw " + | (CSRRS, T) => "csrrsi " + | (CSRRS, F) => "csrrs " + | (CSRRC, T) => "csrrci " + | (CSRRC, F) => "csrrc " + )) in + let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr)))))))))) + | NOP (g__99) => "nop" + | ILLEGAL (g__100) => "illegal" + | C_ADDI4SPN (rdc,nzimm) => + STRCAT "c.addi4spn " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec nzimm)))))) + | C_LW (uimm,rsc,rdc) => + STRCAT "c.lw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_LD (uimm,rsc,rdc) => + STRCAT "c.ld " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_SW (uimm,rsc1,rsc2) => + STRCAT "c.sw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_SD (uimm,rsc1,rsc2) => + STRCAT "c.sd " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_ADDI (nzi,rsd) => + STRCAT "c.addi " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi)))))) + | C_JAL (imm) => STRCAT "c.jal " ((string_of_vec imm)) + | C_ADDIW (imm,rsd) => + STRCAT "c.addiw " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_LI (imm,rd) => + STRCAT "c.li " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_ADDI16SP (imm) => STRCAT "c.addi16sp " ((string_of_vec imm)) + | C_LUI (imm,rd) => + STRCAT "c.lui " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_SRLI (shamt,rsd) => + STRCAT "c.srli " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec shamt)))))) + | C_SRAI (shamt,rsd) => + STRCAT "c.srai " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec shamt)))))) + | C_ANDI (imm,rsd) => + STRCAT "c.andi " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_SUB (rsd,rs2) => + STRCAT "c.sub " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_XOR (rsd,rs2) => + STRCAT "c.xor " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_OR (rsd,rs2) => + STRCAT "c.or " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_AND (rsd,rs2) => + STRCAT "c.and " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_SUBW (rsd,rs2) => + STRCAT "c.subw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_ADDW (rsd,rs2) => + STRCAT "c.addw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_J (imm) => STRCAT "c.j " ((string_of_vec imm)) + | C_BEQZ (imm,rs) => + STRCAT "c.beqz " + ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_BNEZ (imm,rs) => + STRCAT "c.bnez " + ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_SLLI (shamt,rsd) => + STRCAT "c.slli " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt)))))) + | C_LWSP (uimm,rd) => + STRCAT "c.lwsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_LDSP (uimm,rd) => + STRCAT "c.ldsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_SWSP (uimm,rd) => + STRCAT "c.swsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_SDSP (uimm,rd) => + STRCAT "c.sdsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_JR (rs1) => STRCAT "c.jr " ((reg_name_abi rs1)) + | C_JALR (rs1) => STRCAT "c.jalr " ((reg_name_abi rs1)) + | C_MV (rd,rs2) => + STRCAT "c.mv " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs2)))))) + | C_ADD (rsd,rs2) => + STRCAT "c.add " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2)))))) + )))`; + + +(*val isRVC : Machine_word.mword Machine_word.ty16 -> bool*) + +val _ = Define ` + ((isRVC:(16)words$word -> bool) h= + (~ (((((subrange_vec_dec h (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))`; + + +(*val fetch : unit -> Riscv_sequential_types.M Riscv_sequential_types.FetchResult*) + +val _ = Define ` + ((fetch:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$FetchResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) . bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) . bindS +(haveRVC () ) (\ (w__2 : bool) . + if ((((((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):sail_values$ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))) \/ ((((((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):sail_values$ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))) /\ ((~ w__2)))))))) then bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . + returnS (F_Error (E_Fetch_Addr_Align,w__3))) + else bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : 64 words$word) . bindS +(translateAddr w__4 Execute Instruction) (\ (w__5 : riscv_sequential_types$TR_Result) . + (case w__5 of + TR_Failure (e) => bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . + returnS (F_Error (e,w__6))) + | TR_Address (ppclo) => bindS + (checked_mem_read Instruction ppclo (( 2 : int):sail_values$ii) : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__7 : ( 16 words$word) + riscv_sequential_types$MemoryOpResult) . + (case w__7 of + MemException (e) => bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 : 64 words$word) . + returnS (F_Error (E_Fetch_Access_Fault,w__8))) + | MemValue (ilo) => + if ((isRVC ilo)) then returnS (F_RVC ilo) + else bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__9 : 64 words$word) . + let (PChi : riscv_sequential_types$xlenbits) = ((add_vec_int w__9 (( 2 : int):sail_values$ii) : 64 words$word)) in bindS +(translateAddr PChi Execute Instruction) (\ (w__10 : riscv_sequential_types$TR_Result) . + (case w__10 of + TR_Failure (e) => returnS (F_Error (e,PChi)) + | TR_Address (ppchi) => bindS + (checked_mem_read Instruction ppchi (( 2 : int):sail_values$ii) : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__11 : ( 16 words$word) + riscv_sequential_types$MemoryOpResult) . + returnS ((case w__11 of + MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) + | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word)) + ))) + ))) + )) + ))))))))`; + + +(*val step : unit -> Riscv_sequential_types.M bool*) + +val _ = Define ` + ((step:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS +(read_regS mip_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mie_ref) (\ (w__1 : riscv_sequential_types$Minterrupts) . bindS +(read_regS mideleg_ref) (\ (w__2 : riscv_sequential_types$Minterrupts) . bindS +(curInterrupt w__0 w__1 w__2) (\ (w__3 : ((riscv_sequential_types$InterruptType # riscv_sequential_types$Privilege))option) . + (case w__3 of + SOME (intr,priv) => + let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr : 4 words$word))) in seqS +(handle_interrupt intr priv) (returnS F) + | NONE => bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . + let (_ : unit) = (print_bits "PC: " w__4) in bindS +(fetch () ) (\ (w__5 : riscv_sequential_types$FetchResult) . + (case w__5 of + F_Error (e,addr) => seqS (handle_mem_exception addr e) (returnS F) + | F_RVC (h) => + (case ((decodeCompressed h)) of + NONE => + let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec h)) " : "))) in seqS +(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) h : 64 words$word))) (returnS F) + | SOME (ast) => + let (_ : unit) = +(prerr_endline + ((STRCAT ((string_of_vec h)) ((STRCAT " : " ((print_insn ast))))))) in bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . seqS (seqS +(write_regS nextPC_ref ((add_vec_int w__6 (( 2 : int):sail_values$ii) : 64 words$word))) +(execute ast)) (returnS T)) + ) + | F_Base (w) => + (case ((decode w)) of + NONE => + let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec w)) " : "))) in seqS +(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) w : 64 words$word))) (returnS F) + | SOME (ast) => + let (_ : unit) = +(prerr_endline + ((STRCAT ((string_of_vec w)) ((STRCAT " : " ((print_insn ast))))))) in bindS + (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 : 64 words$word) . seqS (seqS +(write_regS nextPC_ref ((add_vec_int w__8 (( 4 : int):sail_values$ii) : 64 words$word))) +(execute ast)) (returnS T)) + ) + ))) + )))))))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml b/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml new file mode 100644 index 00000000..e9b73fd8 --- /dev/null +++ b/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml @@ -0,0 +1,1078 @@ +(*Generated by Lem from riscv_sequential_types.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "riscv_sequential_types" + +(*Generated by Sail from riscv_sequential.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import State_monad*) +(*open import State*) +val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); + + + +val _ = type_abbrev( "xlenbits" , ``: 64 bits``); + +val _ = type_abbrev( "half" , ``: 16 bits``); + +val _ = type_abbrev( "word" , ``: 32 bits``); + +val _ = type_abbrev((* 'n *) "regno" , ``: int``); + +val _ = type_abbrev( "regbits" , ``: 5 bits``); + +val _ = type_abbrev( "cregbits" , ``: 3 bits``); + +val _ = type_abbrev( "csreg" , ``: 12 bits``); + +val _ = type_abbrev( "opcode" , ``: 7 bits``); + +val _ = type_abbrev( "imm12" , ``: 12 bits``); + +val _ = type_abbrev( "imm20" , ``: 20 bits``); + +val _ = type_abbrev( "amo" , ``: 1 bits``); + +val _ = Hol_datatype ` + Architecture = RV32 | RV64 | RV128`; + + + + +val _ = type_abbrev( "arch_xlen" , ``: 2 bits``); + +val _ = type_abbrev( "priv_level" , ``: 2 bits``); + +val _ = Hol_datatype ` + Privilege = User | Supervisor | Machine`; + + + + +val _ = Hol_datatype ` + AccessType = Read | Write | ReadWrite | Execute`; + + + + +val _ = Hol_datatype ` + ReadType = Instruction | Data`; + + + + +val _ = type_abbrev( "exc_code" , ``: 4 bits``); + +val _ = Hol_datatype ` + ExceptionType = + E_Fetch_Addr_Align + | E_Fetch_Access_Fault + | E_Illegal_Instr + | E_Breakpoint + | E_Load_Addr_Align + | E_Load_Access_Fault + | E_SAMO_Addr_Align + | E_SAMO_Access_Fault + | E_U_EnvCall + | E_S_EnvCall + | E_Reserved_10 + | E_M_EnvCall + | E_Fetch_Page_Fault + | E_Load_Page_Fault + | E_Reserved_14 + | E_SAMO_Page_Fault`; + + + + +val _ = Hol_datatype ` + InterruptType = + I_U_Software + | I_S_Software + | I_M_Software + | I_U_Timer + | I_S_Timer + | I_M_Timer + | I_U_External + | I_S_External + | I_M_External`; + + + + +val _ = type_abbrev( "tv_mode" , ``: 2 bits``); + +val _ = Hol_datatype ` + TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved`; + + + + +val _ = Hol_datatype ` + exception = + Error_not_implemented of (string) + | Error_misaligned_access of (unit) + | Error_EBREAK of (unit) + | Error_internal_error of (unit)`; + + + + +val _ = type_abbrev( "ext_status" , ``: 2 bits``); + +val _ = Hol_datatype ` + ExtStatus = Off | Initial | Clean | Dirty`; + + + + +val _ = type_abbrev( "satp_mode" , ``: 4 bits``); + +val _ = Hol_datatype ` + SATPMode = Sbare | Sv32 | Sv39`; + + + + +val _ = type_abbrev( "csrRW" , ``: 2 bits``); + +val _ = Hol_datatype ` + uop = RISCV_LUI | RISCV_AUIPC`; + + + + +val _ = Hol_datatype ` + bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU`; + + + + +val _ = Hol_datatype ` + iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI`; + + + + +val _ = Hol_datatype ` + sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI`; + + + + +val _ = Hol_datatype ` + rop = + RISCV_ADD + | RISCV_SUB + | RISCV_SLL + | RISCV_SLT + | RISCV_SLTU + | RISCV_XOR + | RISCV_SRL + | RISCV_SRA + | RISCV_OR + | RISCV_AND`; + + + + +val _ = Hol_datatype ` + ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW`; + + + + +val _ = Hol_datatype ` + amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU`; + + + + +val _ = Hol_datatype ` + csrop = CSRRW | CSRRS | CSRRC`; + + + + +val _ = Hol_datatype ` + word_width = BYTE | HALF | WORD | DOUBLE`; + + + + +val _ = Hol_datatype ` + MemoryOpResult = MemValue of ('a) | MemException of (ExceptionType)`; + + + + +val _ = Hol_datatype ` + Misa = Mk_Misa of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + SV39_PTE = Mk_SV39_PTE of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + PTE_Bits = Mk_PTE_Bits of ( 8 words$word)`; + + + + +val _ = Hol_datatype ` + Mstatus = Mk_Mstatus of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Sstatus = Mk_Sstatus of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Minterrupts = Mk_Minterrupts of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Sinterrupts = Mk_Sinterrupts of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Medeleg = Mk_Medeleg of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Sedeleg = Mk_Sedeleg of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Mtvec = Mk_Mtvec of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Satp64 = Mk_Satp64 of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + Mcause = Mk_Mcause of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + sync_exception = + <| sync_exception_trap : ExceptionType; sync_exception_excinfo : xlenbits option |>`; + + + +val _ = Hol_datatype ` + ctl_result = CTL_TRAP of (sync_exception) | CTL_SRET of (unit) | CTL_MRET of (unit)`; + + + + +val _ = type_abbrev( "pteAttribs" , ``: 8 bits``); + +val _ = Hol_datatype ` + PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update`; + + + + +val _ = type_abbrev( "vaddr39" , ``: 39 bits``); + +val _ = type_abbrev( "paddr39" , ``: 56 bits``); + +val _ = type_abbrev( "pte39" , ``: xlenbits``); + +val _ = Hol_datatype ` + SV39_Vaddr = Mk_SV39_Vaddr of ( 39 words$word)`; + + + + +val _ = Hol_datatype ` + SV39_Paddr = Mk_SV39_Paddr of ( 56 words$word)`; + + + + +val _ = type_abbrev( "asid64" , ``: 16 bits``); + +val _ = Hol_datatype ` + PTW_Result = + PTW_Success of ((paddr39 # SV39_PTE # paddr39 # sail_values$ii # bool)) | PTW_Failure of (PTW_Error)`; + + + + +val _ = Hol_datatype ` + TLB39_Entry = + <| TLB39_Entry_asid : asid64; + TLB39_Entry_global : bool; + TLB39_Entry_vAddr : vaddr39; + TLB39_Entry_pAddr : paddr39; + TLB39_Entry_vMatchMask : vaddr39; + TLB39_Entry_vAddrMask : vaddr39; + TLB39_Entry_pte : SV39_PTE; + TLB39_Entry_pteAddr : paddr39; + TLB39_Entry_age : xlenbits |>`; + + + +val _ = Hol_datatype ` + TR39_Result = TR39_Address of (paddr39) | TR39_Failure of (PTW_Error)`; + + + + +val _ = Hol_datatype ` + TR_Result = TR_Address of (xlenbits) | TR_Failure of (ExceptionType)`; + + + + +val _ = Hol_datatype ` + ast = + UTYPE of (( 20 bits # regbits # uop)) + | RISCV_JAL of (( 21 bits # regbits)) + | RISCV_JALR of (( 12 bits # regbits # regbits)) + | BTYPE of (( 13 bits # regbits # regbits # bop)) + | ITYPE of (( 12 bits # regbits # regbits # iop)) + | SHIFTIOP of (( 6 bits # regbits # regbits # sop)) + | RTYPE of ((regbits # regbits # regbits # rop)) + | LOAD of (( 12 bits # regbits # regbits # bool # word_width # bool # bool)) + | STORE of (( 12 bits # regbits # regbits # word_width # bool # bool)) + | ADDIW of (( 12 bits # regbits # regbits)) + | SHIFTW of (( 5 bits # regbits # regbits # sop)) + | RTYPEW of ((regbits # regbits # regbits # ropw)) + | MUL of ((regbits # regbits # regbits # bool # bool # bool)) + | DIV0 of ((regbits # regbits # regbits # bool)) + | REM of ((regbits # regbits # regbits # bool)) + | MULW of ((regbits # regbits # regbits)) + | DIVW of ((regbits # regbits # regbits # bool)) + | REMW of ((regbits # regbits # regbits # bool)) + | FENCE of (( 4 bits # 4 bits)) + | FENCEI of (unit) + | ECALL of (unit) + | MRET of (unit) + | SRET of (unit) + | EBREAK of (unit) + | WFI of (unit) + | SFENCE_VMA of ((regbits # regbits)) + | LOADRES of ((bool # bool # regbits # word_width # regbits)) + | STORECON of ((bool # bool # regbits # regbits # word_width # regbits)) + | AMO of ((amoop # bool # bool # regbits # regbits # word_width # regbits)) + | CSR of (( 12 bits # regbits # regbits # bool # csrop)) + | NOP of (unit) + | ILLEGAL of (unit) + | C_ADDI4SPN of ((cregbits # 8 bits)) + | C_LW of (( 5 bits # cregbits # cregbits)) + | C_LD of (( 5 bits # cregbits # cregbits)) + | C_SW of (( 5 bits # cregbits # cregbits)) + | C_SD of (( 5 bits # cregbits # cregbits)) + | C_ADDI of (( 6 bits # regbits)) + | C_JAL of ( 11 bits) + | C_ADDIW of (( 6 bits # regbits)) + | C_LI of (( 6 bits # regbits)) + | C_ADDI16SP of ( 6 bits) + | C_LUI of (( 6 bits # regbits)) + | C_SRLI of (( 6 bits # cregbits)) + | C_SRAI of (( 6 bits # cregbits)) + | C_ANDI of (( 6 bits # cregbits)) + | C_SUB of ((cregbits # cregbits)) + | C_XOR of ((cregbits # cregbits)) + | C_OR of ((cregbits # cregbits)) + | C_AND of ((cregbits # cregbits)) + | C_SUBW of ((cregbits # cregbits)) + | C_ADDW of ((cregbits # cregbits)) + | C_J of ( 11 bits) + | C_BEQZ of (( 8 bits # cregbits)) + | C_BNEZ of (( 8 bits # cregbits)) + | C_SLLI of (( 6 bits # regbits)) + | C_LWSP of (( 6 bits # regbits)) + | C_LDSP of (( 6 bits # regbits)) + | C_SWSP of (( 6 bits # regbits)) + | C_SDSP of (( 6 bits # regbits)) + | C_JR of (regbits) + | C_JALR of (regbits) + | C_MV of ((regbits # regbits)) + | C_ADD of ((regbits # regbits))`; + + + + +val _ = Hol_datatype ` + FetchResult = F_Base of (word) | F_RVC of (half) | F_Error of ((ExceptionType # xlenbits))`; + + + + +val _ = Hol_datatype ` + register_value = + Regval_vector of ((sail_values$ii # bool # register_value list)) + | Regval_list of ( register_value list) + | Regval_option of ( register_value option) + | Regval_Mcause of (Mcause) + | Regval_Medeleg of (Medeleg) + | Regval_Minterrupts of (Minterrupts) + | Regval_Misa of (Misa) + | Regval_Mstatus of (Mstatus) + | Regval_Mtvec of (Mtvec) + | Regval_Privilege of (Privilege) + | Regval_Sedeleg of (Sedeleg) + | Regval_Sinterrupts of (Sinterrupts) + | Regval_TLB39_Entry of (TLB39_Entry) + | Regval_vector_64_dec_bit of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + regstate = + <| tlb39 : TLB39_Entry option; + stval : 64 words$word; + scause : Mcause; + sepc : 64 words$word; + sscratch : 64 words$word; + stvec : Mtvec; + satp : 64 words$word; + sideleg : Sinterrupts; + sedeleg : Sedeleg; + pmpcfg0 : 64 words$word; + pmpaddr0 : 64 words$word; + mhartid : 64 words$word; + marchid : 64 words$word; + mimpid : 64 words$word; + mvendorid : 64 words$word; + minstret : 64 words$word; + mtime : 64 words$word; + mcycle : 64 words$word; + mscratch : 64 words$word; + mtval : 64 words$word; + mepc : 64 words$word; + mcause : Mcause; + mtvec : Mtvec; + medeleg : Medeleg; + mideleg : Minterrupts; + mie : Minterrupts; + mip : Minterrupts; + mstatus : Mstatus; + misa : Misa; + cur_inst : 64 words$word; + cur_privilege : Privilege; + Xs : ( 64 words$word) list; + nextPC : 64 words$word; + PC : 64 words$word |>`; + + + + + +(*val Mcause_of_regval : register_value -> Maybe.maybe Mcause*) + +val _ = Define ` + ((Mcause_of_regval:register_value ->(Mcause)option) merge_var= + ((case merge_var of Regval_Mcause (v) => SOME v | g__92 => NONE )))`; + + +(*val regval_of_Mcause : Mcause -> register_value*) + +val _ = Define ` + ((regval_of_Mcause:Mcause -> register_value) v= (Regval_Mcause v))`; + + +(*val Medeleg_of_regval : register_value -> Maybe.maybe Medeleg*) + +val _ = Define ` + ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var= + ((case merge_var of Regval_Medeleg (v) => SOME v | g__91 => NONE )))`; + + +(*val regval_of_Medeleg : Medeleg -> register_value*) + +val _ = Define ` + ((regval_of_Medeleg:Medeleg -> register_value) v= (Regval_Medeleg v))`; + + +(*val Minterrupts_of_regval : register_value -> Maybe.maybe Minterrupts*) + +val _ = Define ` + ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var= + ((case merge_var of Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`; + + +(*val regval_of_Minterrupts : Minterrupts -> register_value*) + +val _ = Define ` + ((regval_of_Minterrupts:Minterrupts -> register_value) v= (Regval_Minterrupts v))`; + + +(*val Misa_of_regval : register_value -> Maybe.maybe Misa*) + +val _ = Define ` + ((Misa_of_regval:register_value ->(Misa)option) merge_var= + ((case merge_var of Regval_Misa (v) => SOME v | g__89 => NONE )))`; + + +(*val regval_of_Misa : Misa -> register_value*) + +val _ = Define ` + ((regval_of_Misa:Misa -> register_value) v= (Regval_Misa v))`; + + +(*val Mstatus_of_regval : register_value -> Maybe.maybe Mstatus*) + +val _ = Define ` + ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var= + ((case merge_var of Regval_Mstatus (v) => SOME v | g__88 => NONE )))`; + + +(*val regval_of_Mstatus : Mstatus -> register_value*) + +val _ = Define ` + ((regval_of_Mstatus:Mstatus -> register_value) v= (Regval_Mstatus v))`; + + +(*val Mtvec_of_regval : register_value -> Maybe.maybe Mtvec*) + +val _ = Define ` + ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= + ((case merge_var of Regval_Mtvec (v) => SOME v | g__87 => NONE )))`; + + +(*val regval_of_Mtvec : Mtvec -> register_value*) + +val _ = Define ` + ((regval_of_Mtvec:Mtvec -> register_value) v= (Regval_Mtvec v))`; + + +(*val Privilege_of_regval : register_value -> Maybe.maybe Privilege*) + +val _ = Define ` + ((Privilege_of_regval:register_value ->(Privilege)option) merge_var= + ((case merge_var of Regval_Privilege (v) => SOME v | g__86 => NONE )))`; + + +(*val regval_of_Privilege : Privilege -> register_value*) + +val _ = Define ` + ((regval_of_Privilege:Privilege -> register_value) v= (Regval_Privilege v))`; + + +(*val Sedeleg_of_regval : register_value -> Maybe.maybe Sedeleg*) + +val _ = Define ` + ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var= + ((case merge_var of Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`; + + +(*val regval_of_Sedeleg : Sedeleg -> register_value*) + +val _ = Define ` + ((regval_of_Sedeleg:Sedeleg -> register_value) v= (Regval_Sedeleg v))`; + + +(*val Sinterrupts_of_regval : register_value -> Maybe.maybe Sinterrupts*) + +val _ = Define ` + ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var= + ((case merge_var of Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`; + + +(*val regval_of_Sinterrupts : Sinterrupts -> register_value*) + +val _ = Define ` + ((regval_of_Sinterrupts:Sinterrupts -> register_value) v= (Regval_Sinterrupts v))`; + + +(*val TLB39_Entry_of_regval : register_value -> Maybe.maybe TLB39_Entry*) + +val _ = Define ` + ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var= + ((case merge_var of Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`; + + +(*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) + +val _ = Define ` + ((regval_of_TLB39_Entry:TLB39_Entry -> register_value) v= (Regval_TLB39_Entry v))`; + + +(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) + +val _ = Define ` + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`; + + +(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*) + +val _ = Define ` + ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; + + + + +(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +val _ = Define ` + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + (\x . (case x of + Regval_vector (_, _, v) => just_list (MAP of_regval v) + | _ => NONE + )))`; + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; + + +(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +val _ = Define ` + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + (\x . (case x of + Regval_list v => just_list (MAP of_regval v) + | _ => NONE + )))`; + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; + + +(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*) +val _ = Define ` + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= + (\x . (case x of Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`; + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*) +val _ = Define ` + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; + + + +val _ = Define ` + ((tlb39_ref:((regstate),(register_value),((TLB39_Entry)option))sail_values$register_ref)= (<| + name := "tlb39"; + read_from := (\ s . s.tlb39); + write_to := (\ v s . (( s with<| tlb39 := v |>))); + of_regval := (\ v . option_of_regval (\ v . TLB39_Entry_of_regval v) v); + regval_of := (\ v . regval_of_option (\ v . regval_of_TLB39_Entry v) v) |>))`; + + +val _ = Define ` + ((stval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "stval"; + read_from := (\ s . s.stval); + write_to := (\ v s . (( s with<| stval := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((scause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)= (<| + name := "scause"; + read_from := (\ s . s.scause); + write_to := (\ v s . (( s with<| scause := v |>))); + of_regval := (\ v . Mcause_of_regval v); + regval_of := (\ v . regval_of_Mcause v) |>))`; + + +val _ = Define ` + ((sepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "sepc"; + read_from := (\ s . s.sepc); + write_to := (\ v s . (( s with<| sepc := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((sscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "sscratch"; + read_from := (\ s . s.sscratch); + write_to := (\ v s . (( s with<| sscratch := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((stvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)= (<| + name := "stvec"; + read_from := (\ s . s.stvec); + write_to := (\ v s . (( s with<| stvec := v |>))); + of_regval := (\ v . Mtvec_of_regval v); + regval_of := (\ v . regval_of_Mtvec v) |>))`; + + +val _ = Define ` + ((satp_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "satp"; + read_from := (\ s . s.satp); + write_to := (\ v s . (( s with<| satp := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((sideleg_ref:((regstate),(register_value),(Sinterrupts))sail_values$register_ref)= (<| + name := "sideleg"; + read_from := (\ s . s.sideleg); + write_to := (\ v s . (( s with<| sideleg := v |>))); + of_regval := (\ v . Sinterrupts_of_regval v); + regval_of := (\ v . regval_of_Sinterrupts v) |>))`; + + +val _ = Define ` + ((sedeleg_ref:((regstate),(register_value),(Sedeleg))sail_values$register_ref)= (<| + name := "sedeleg"; + read_from := (\ s . s.sedeleg); + write_to := (\ v s . (( s with<| sedeleg := v |>))); + of_regval := (\ v . Sedeleg_of_regval v); + regval_of := (\ v . regval_of_Sedeleg v) |>))`; + + +val _ = Define ` + ((pmpcfg0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "pmpcfg0"; + read_from := (\ s . s.pmpcfg0); + write_to := (\ v s . (( s with<| pmpcfg0 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((pmpaddr0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "pmpaddr0"; + read_from := (\ s . s.pmpaddr0); + write_to := (\ v s . (( s with<| pmpaddr0 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mhartid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mhartid"; + read_from := (\ s . s.mhartid); + write_to := (\ v s . (( s with<| mhartid := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((marchid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "marchid"; + read_from := (\ s . s.marchid); + write_to := (\ v s . (( s with<| marchid := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mimpid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mimpid"; + read_from := (\ s . s.mimpid); + write_to := (\ v s . (( s with<| mimpid := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mvendorid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mvendorid"; + read_from := (\ s . s.mvendorid); + write_to := (\ v s . (( s with<| mvendorid := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((minstret_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "minstret"; + read_from := (\ s . s.minstret); + write_to := (\ v s . (( s with<| minstret := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mtime_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mtime"; + read_from := (\ s . s.mtime); + write_to := (\ v s . (( s with<| mtime := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mcycle_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mcycle"; + read_from := (\ s . s.mcycle); + write_to := (\ v s . (( s with<| mcycle := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mscratch"; + read_from := (\ s . s.mscratch); + write_to := (\ v s . (( s with<| mscratch := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mtval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mtval"; + read_from := (\ s . s.mtval); + write_to := (\ v s . (( s with<| mtval := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "mepc"; + read_from := (\ s . s.mepc); + write_to := (\ v s . (( s with<| mepc := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mcause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)= (<| + name := "mcause"; + read_from := (\ s . s.mcause); + write_to := (\ v s . (( s with<| mcause := v |>))); + of_regval := (\ v . Mcause_of_regval v); + regval_of := (\ v . regval_of_Mcause v) |>))`; + + +val _ = Define ` + ((mtvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)= (<| + name := "mtvec"; + read_from := (\ s . s.mtvec); + write_to := (\ v s . (( s with<| mtvec := v |>))); + of_regval := (\ v . Mtvec_of_regval v); + regval_of := (\ v . regval_of_Mtvec v) |>))`; + + +val _ = Define ` + ((medeleg_ref:((regstate),(register_value),(Medeleg))sail_values$register_ref)= (<| + name := "medeleg"; + read_from := (\ s . s.medeleg); + write_to := (\ v s . (( s with<| medeleg := v |>))); + of_regval := (\ v . Medeleg_of_regval v); + regval_of := (\ v . regval_of_Medeleg v) |>))`; + + +val _ = Define ` + ((mideleg_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + name := "mideleg"; + read_from := (\ s . s.mideleg); + write_to := (\ v s . (( s with<| mideleg := v |>))); + of_regval := (\ v . Minterrupts_of_regval v); + regval_of := (\ v . regval_of_Minterrupts v) |>))`; + + +val _ = Define ` + ((mie_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + name := "mie"; + read_from := (\ s . s.mie); + write_to := (\ v s . (( s with<| mie := v |>))); + of_regval := (\ v . Minterrupts_of_regval v); + regval_of := (\ v . regval_of_Minterrupts v) |>))`; + + +val _ = Define ` + ((mip_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + name := "mip"; + read_from := (\ s . s.mip); + write_to := (\ v s . (( s with<| mip := v |>))); + of_regval := (\ v . Minterrupts_of_regval v); + regval_of := (\ v . regval_of_Minterrupts v) |>))`; + + +val _ = Define ` + ((mstatus_ref:((regstate),(register_value),(Mstatus))sail_values$register_ref)= (<| + name := "mstatus"; + read_from := (\ s . s.mstatus); + write_to := (\ v s . (( s with<| mstatus := v |>))); + of_regval := (\ v . Mstatus_of_regval v); + regval_of := (\ v . regval_of_Mstatus v) |>))`; + + +val _ = Define ` + ((misa_ref:((regstate),(register_value),(Misa))sail_values$register_ref)= (<| + name := "misa"; + read_from := (\ s . s.misa); + write_to := (\ v s . (( s with<| misa := v |>))); + of_regval := (\ v . Misa_of_regval v); + regval_of := (\ v . regval_of_Misa v) |>))`; + + +val _ = Define ` + ((cur_inst_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "cur_inst"; + read_from := (\ s . s.cur_inst); + write_to := (\ v s . (( s with<| cur_inst := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((cur_privilege_ref:((regstate),(register_value),(Privilege))sail_values$register_ref)= (<| + name := "cur_privilege"; + read_from := (\ s . s.cur_privilege); + write_to := (\ v s . (( s with<| cur_privilege := v |>))); + of_regval := (\ v . Privilege_of_regval v); + regval_of := (\ v . regval_of_Privilege v) |>))`; + + +val _ = Define ` + ((Xs_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)= (<| + name := "Xs"; + read_from := (\ s . s.Xs); + write_to := (\ v s . (( s with<| Xs := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`; + + +val _ = Define ` + ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "nextPC"; + read_from := (\ s . s.nextPC); + write_to := (\ v s . (( s with<| nextPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + name := "PC"; + read_from := (\ s . s.PC); + write_to := (\ v s . (( s with<| PC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +(*val get_regval : string -> regstate -> Maybe.maybe register_value*) +val _ = Define ` + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else + if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else + if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else + if reg_name = "sepc" then SOME (sepc_ref.regval_of (sepc_ref.read_from s)) else + if reg_name = "sscratch" then SOME (sscratch_ref.regval_of (sscratch_ref.read_from s)) else + if reg_name = "stvec" then SOME (stvec_ref.regval_of (stvec_ref.read_from s)) else + if reg_name = "satp" then SOME (satp_ref.regval_of (satp_ref.read_from s)) else + if reg_name = "sideleg" then SOME (sideleg_ref.regval_of (sideleg_ref.read_from s)) else + if reg_name = "sedeleg" then SOME (sedeleg_ref.regval_of (sedeleg_ref.read_from s)) else + if reg_name = "pmpcfg0" then SOME (pmpcfg0_ref.regval_of (pmpcfg0_ref.read_from s)) else + if reg_name = "pmpaddr0" then SOME (pmpaddr0_ref.regval_of (pmpaddr0_ref.read_from s)) else + if reg_name = "mhartid" then SOME (mhartid_ref.regval_of (mhartid_ref.read_from s)) else + if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else + if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else + if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else + if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else + if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else + if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else + if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else + if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else + if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else + if reg_name = "mcause" then SOME (mcause_ref.regval_of (mcause_ref.read_from s)) else + if reg_name = "mtvec" then SOME (mtvec_ref.regval_of (mtvec_ref.read_from s)) else + if reg_name = "medeleg" then SOME (medeleg_ref.regval_of (medeleg_ref.read_from s)) else + if reg_name = "mideleg" then SOME (mideleg_ref.regval_of (mideleg_ref.read_from s)) else + if reg_name = "mie" then SOME (mie_ref.regval_of (mie_ref.read_from s)) else + if reg_name = "mip" then SOME (mip_ref.regval_of (mip_ref.read_from s)) else + if reg_name = "mstatus" then SOME (mstatus_ref.regval_of (mstatus_ref.read_from s)) else + if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else + if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else + if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else + if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else + if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else + if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else + NONE))`; + + +(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*) +val _ = Define ` + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "tlb39" then OPTION_MAP (\ v . tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else + if reg_name = "stval" then OPTION_MAP (\ v . stval_ref.write_to v s) (stval_ref.of_regval v) else + if reg_name = "scause" then OPTION_MAP (\ v . scause_ref.write_to v s) (scause_ref.of_regval v) else + if reg_name = "sepc" then OPTION_MAP (\ v . sepc_ref.write_to v s) (sepc_ref.of_regval v) else + if reg_name = "sscratch" then OPTION_MAP (\ v . sscratch_ref.write_to v s) (sscratch_ref.of_regval v) else + if reg_name = "stvec" then OPTION_MAP (\ v . stvec_ref.write_to v s) (stvec_ref.of_regval v) else + if reg_name = "satp" then OPTION_MAP (\ v . satp_ref.write_to v s) (satp_ref.of_regval v) else + if reg_name = "sideleg" then OPTION_MAP (\ v . sideleg_ref.write_to v s) (sideleg_ref.of_regval v) else + if reg_name = "sedeleg" then OPTION_MAP (\ v . sedeleg_ref.write_to v s) (sedeleg_ref.of_regval v) else + if reg_name = "pmpcfg0" then OPTION_MAP (\ v . pmpcfg0_ref.write_to v s) (pmpcfg0_ref.of_regval v) else + if reg_name = "pmpaddr0" then OPTION_MAP (\ v . pmpaddr0_ref.write_to v s) (pmpaddr0_ref.of_regval v) else + if reg_name = "mhartid" then OPTION_MAP (\ v . mhartid_ref.write_to v s) (mhartid_ref.of_regval v) else + if reg_name = "marchid" then OPTION_MAP (\ v . marchid_ref.write_to v s) (marchid_ref.of_regval v) else + if reg_name = "mimpid" then OPTION_MAP (\ v . mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else + if reg_name = "mvendorid" then OPTION_MAP (\ v . mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else + if reg_name = "minstret" then OPTION_MAP (\ v . minstret_ref.write_to v s) (minstret_ref.of_regval v) else + if reg_name = "mtime" then OPTION_MAP (\ v . mtime_ref.write_to v s) (mtime_ref.of_regval v) else + if reg_name = "mcycle" then OPTION_MAP (\ v . mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else + if reg_name = "mscratch" then OPTION_MAP (\ v . mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else + if reg_name = "mtval" then OPTION_MAP (\ v . mtval_ref.write_to v s) (mtval_ref.of_regval v) else + if reg_name = "mepc" then OPTION_MAP (\ v . mepc_ref.write_to v s) (mepc_ref.of_regval v) else + if reg_name = "mcause" then OPTION_MAP (\ v . mcause_ref.write_to v s) (mcause_ref.of_regval v) else + if reg_name = "mtvec" then OPTION_MAP (\ v . mtvec_ref.write_to v s) (mtvec_ref.of_regval v) else + if reg_name = "medeleg" then OPTION_MAP (\ v . medeleg_ref.write_to v s) (medeleg_ref.of_regval v) else + if reg_name = "mideleg" then OPTION_MAP (\ v . mideleg_ref.write_to v s) (mideleg_ref.of_regval v) else + if reg_name = "mie" then OPTION_MAP (\ v . mie_ref.write_to v s) (mie_ref.of_regval v) else + if reg_name = "mip" then OPTION_MAP (\ v . mip_ref.write_to v s) (mip_ref.of_regval v) else + if reg_name = "mstatus" then OPTION_MAP (\ v . mstatus_ref.write_to v s) (mstatus_ref.of_regval v) else + if reg_name = "misa" then OPTION_MAP (\ v . misa_ref.write_to v s) (misa_ref.of_regval v) else + if reg_name = "cur_inst" then OPTION_MAP (\ v . cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else + if reg_name = "cur_privilege" then OPTION_MAP (\ v . cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else + if reg_name = "Xs" then OPTION_MAP (\ v . Xs_ref.write_to v s) (Xs_ref.of_regval v) else + if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else + if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else + NONE))`; + + +val _ = Define ` + ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`; + + + +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``); +val _ = export_theory() + -- cgit v1.2.3 From 9b953f94a47b74ddf59798eb7fff68704a9ede8c Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 18:27:53 +0100 Subject: Add updated README file --- README | 236 -------------------------------------------------------------- README.md | 89 ++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 236 deletions(-) delete mode 100644 README create mode 100644 README.md diff --git a/README b/README deleted file mode 100644 index f5aaeeff..00000000 --- a/README +++ /dev/null @@ -1,236 +0,0 @@ -Sail README - -[Note that this describes the original Sail language, on the github master branch. The current development version, on the github sail2 branch, is somewhat different; documentation for that is in progress] - - -Kathryn E. Gray and Peter Sewell -15 March 2017 - -******************************************************************** -OVERVIEW - -Sail is a language for describing the instruction semantics of -processors. It has been used in several papers, available from -http://www.cl.cam.ac.uk/~pes20/sail/ - -This repository contains the implementation of Sail, together with -related tools and some Sail specifications: - -- a manual, manual.pdf - -- sail, the type checker and compiler for programs in the Sail - language; - -- a Sail specification of a MIPS ISA (in mips/) - -- a Sail specification of a Cheri ISA (in cheri/) - -- a Sail specification of part of the ARMv8 ISA (in arm/) - -- a sequential Sail interpreter, which evaluates an ELF binary for an - architecture that has been specified using Sail (for ABIs included - in our ELF specification); - -- machinery to interface with the PPCMEM concurrent evaluation - exploration tool; and - -- a formal definition of the Sail language and type system. - -- an emacs mode, including syntax highlighting - -We also have a substantial IBM POWER ISA specification, -which we can send by email. - - -************************************************************************** -BUILDING - -SAIL COMPILER - -The Sail compiler requires OCaml; it is tested on version 4.02.3. - -Run "make" in the top level sail directory; this will generate an executable -called sail in this directory and will compile the interpreter files. - -make clean will remove this executable as well as the build files in -subdirectories. - -SAIL INTERPRETER - -The Sail interpreter relies on external access to two external tools: - - Lem: a specification language that generates theorem prover code - for HOL4, Isabelle, and Coq, and executable OCaml code from a - specification. It is a publicly available Github repository - https://github.com/rems-project/lem - - Linksem: a formal specification of ELF that includes the facility - to read in an ELF file and represent them in uniform ways. It is - a public Github repository - https://github.com/rems-project/linksem - -The Sail build system expects to find these repositories in the same -directory as the sail repository by default. This can be changed with -make variables LEM, LEMLIBOCAML, and ELFDIR - -To build the interpreter, first build Lem and the Lem ocaml libraries. -Then call make interpreter from either the toplevel directory or the src -directory. - -The interpreter currently only evaluates binaries and requires modifications -to a file within the src/lem_interp directory to support new architectures. -There is 'bit-rotted' support for evaluating separate sail files and function -calls. - -MIPS SEQUENTIAL EVALUATOR - -With the sail interpreter and the linksem repository explained above, -the mips sequential interpreter can be build in the src/ subdirectory -with -make run_mips.native - -This will then evaluate any statically linked mips elf file (without -syscalls). Use --help for command line options - -Todo: describe interpreter commands - -************************************************************************** -EMACS MODE - -There is an emacs mode implementation very similar to the Tuareg mode in sail/editors - -************************************************************************** -To get started, one probably wants to develop a new definition by -analogy with the existing MIPS definition, using the sail executable -just to check that it is type-correct. After building sail (as -described below), this is done by: - -./sail mips/mips_prelude.sail mips/mips_wrappers.sail mips/mips_insts.sail mips/mips_epilogue.sail - -Sail treats multiple file arguments as though they wre concatenated -into a single large file (although error messages will give the -appropriate file and line number). For an explanation of how the MIPS -model is divided up see mips/README. - -Once sufficient instructions have been represented in a specification, -then one may also want to run executables sequentially, to debug the -specification and begin testing. For this, one would need to adapt the -sequential sail interpreter, which evaluates the specification on an -ELF file. - -Building the architecture for compilation to connect to the -interpreter, one uses the sail executable: - -./sail -lem_ast - -which will generate a mips.lem file in the current directory, which -will be linked with the sail interpreter (the output is a verbose -representation of the sail AST). - -To generate Lem specifications for theorem proving, one uses the sail -executable with flag: -./sail mips/mips.sail -lem - -To generate OCaml output for fast sequential evaluation, one uses the -sail executable with flag: -./sail mips/mips.sail -ocaml - -****************************************************************************** -LICENCES - -The Sail implementation, in src/, is distributed under the 2-clause -BSD licence in the headers of those files and in src/LICENCE, with the -exception of the library src/pprint, which is distributed under the -CeCILL-C free software licence in src/pprint/LICENSE. - -The ARMv8 model, in arm/, is distributed under the 2-clause BSD -licence in the headers of those files. - -The MIPS and CHERI models, in mips/ and cheri/, are distributed under -the 2-clause BSD licence in the headers of those files. - - - -****************************************************************************** -DIRECTORY STRUCTURE - -Sail sources and binaries are to be found in the directories of sail -(l2 is the previous working name of sail). - -Top level directories -src/ ML implementation of Sail frontend, Sail executable, subdirectories -language/ Ott definitions of source language, pdfs as well -mips/ Sail definition of a MIPS specification -cheri/ Sail definition of a Cheri specification -risc-v/ abandoned very partial attempt at RISC V specification -l3-to-l2/ abandoned but not GC-ed directory - -language directory -l2_parse.ott Grammar of Sail generated by parser, superset of source language -l2.ott Grammar of Sail source -l2_typ.ott Grammar of Internal structures used for type annotations -l2_rules.ott Rules for type system -type_system.tex Source of type system LaTeX document - -Relevant make commands: -make Builds pdfs for l2 and l2_parse, ml and lem files of grammars - -Generated files -l2.pdf combines grammar of l2.ott l2_typ.ott and rules of l2_rules.ott -l2_parse.pdf grammar of l2_parse.ott only -l2.ml grammar of l2.ott only, used by type checker -l2_parse.ml grammar of l2_parse.ott only, used by parser and initial check -l2.lem combines grammar of l2.ott and l2_typ.ott, used by interpreter - -src directory (including some generated files) -ast.ml symlink to language/l2.ml -demo.sh script for setting up a demo -finite_map.ml utility implementation -gen_lib/ source directory of libaries used by generated back ends -initial_check.ml translate l2_parse grammar to l2 grammar -initial_check_full.ml performs sames checks as above as to kind well-formedness but over l2 grammar -lem_interp/ source directory of interpreter -lexer.mll -myocamlbuild.ml -parse_ast.ml symlink to language/l2_parse.ml -parse.mly -pp.ml utility for printing -pprint/ library directory of someone else's pretty printing combinators -pre_lexer.mll First pass lexer, to identify type identifiers -pre_parser.mly First pass parser, to identify type identifiers for actual parsing -pretty_print.ml our printers; one to Sail source, one to Lem ast, one to Lem, and one to Ocaml -process_file.ml -reporting_basic.ml -rewriter.ml performs sail-to-sail transformations for various back ends -sail.ml main file -sail.native executable for Sail -sail_lib.ml treat some sail functions as a library, for idl/power generation -spec_analysis.ml analyses a fully type annotated ast, primarily used by rewriters -test/ directory of test suite -type_check.ml Main type checker -type_internal Structure of internal types, and type - type comparisons -util.ml - -Relevant make commands: -make Builds Sail executable (does not remake language files automatically) -make interpreter Builds sail interpeter -make run_mips.native Builds an executable sequential interpreter for MIPS Elf binaries -make clean - -lem_interp directory -instruction_extractor.lem processes a specification and identifies the ast nodes of instructions with appropriate tags to convert data types into/out of sail value type -interp.lem interpreter implementation -interp_ast.lem symlink to language/l2.lem -interp_inter_imp.lem implementation of externally visible interface -interp_interface.lem externally visible interface for memory -interp_lib.lem implementation of sail library functions -interp_utilities.lem commonly useful functions for interpreter -sail_impl_base.lem externally visible interface above interp_interface -pretty_interp.ml pretty printing for interperter forms -run_interp.ml interactive implementation for running interpreter with simple memory and registers, bitrotted -run_interp_model.ml interactive implementation for running sequential binaries -run_with_elf.ml hook run_interp_model up with elf support, main file of sequential interpreter -run_with_elf_cheri.ml as above but specific to cheri -run_with_elf_cheri128.ml -type_check.lem implementation to type check fully inferenced, annotated, ast nodes (not complete) - diff --git a/README.md b/README.md new file mode 100644 index 00000000..7ee92f93 --- /dev/null +++ b/README.md @@ -0,0 +1,89 @@ +Sail ISA specification language +=============================== + +Overview +======== + +Sail is a language for describing the instruction semantics of +processors. Sail aims to provide a engineer-friendly, +vendor-pseudocode-like language for describing instruction +semantics. It is an imperative language containing some advanced +features like dependent typing for numeric types and bitvector +lengths, which are automatically checked using Z3. It has been used +for several papers, available from http://www.cl.cam.ac.uk/~pes20/sail/ + +This repository contains the implementation of Sail, together with +some Sail specifications and related tools. + +* A manual, [manual.pdf] with source (in [doc/]) + +* The Sail source code (in [src/]) + +* A Sail specification of a MIPS ISA (in [mips/]) + +* A Sail specification of the CHERI MIPS ISA (in [cheri/]) + +* A Sail specification of ARMv8.3 generated from ARM's publically + released ASL specification (in [aarch64/]) + +* Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle] + +* Documentation for generating Isabelle and working with the ISA specs + in Isabelle in [snapshots/isabelle/manual.pdf] + +* A simple emacs mode with syntax highlighting (in [editors/]) + +* A test suite for Sail (in [test/]) + +We also have versions of IBM POWER, a fragment of x86, and a +hand-written fragment of ARM, but these are currently not up-to-date +with the latest version of Sail, which is the (default) sail2 branch +on Github. + +Building +======== + +See [INSTALL.md] for full details of how to build Sail from source +with all the required dependencies. + +OPAM Installation +================= + +See the Sail [wiki +page](https://github.com/rems-project/sail/wiki/OPAMInstall) for how +to get pre-built binaries of Sail using OPAM. + +Emacs Mode +========== + +[editors/sail2-mode.el] contains an Emacs mode for the most recent +version of Sail which provides some basic syntax +highlighting. [editors/sail-mode.el] Contains an emacs mode for +previous versions of the language. + +Licensing +========= + +The Sail implementation, in src/, as well as its tests in test/ and +other supporting files in lib/ and language/, is distributed under the +2-clause BSD licence in the headers of those files and in src/LICENCE, +with the exception of the library src/pprint, which is distributed +under the CeCILL-C free software licence in src/pprint/LICENSE. + +The ASL-derived ARMv8.3 model in aarch64/ is copyright ARM Ltd. See +https://github.com/meriac/archex + +The hand-written ARMv8 model, in arm/, is distributed under the +2-clause BSD licence in the headers of those files. + +The MIPS and CHERI models, in mips/ and cheri/, are distributed under +the 2-clause BSD licence in the headers of those files. + +The x86 model in x86/ is distributed under the 2-clause BSD licence in +the headers of those files. + +The POWER model in power/ is distributed under the 2-clause BSD licence in +the headers of those files. + +The RISC-V model in riscv/ model is also distributed under the +2-clause BSD licence. -- cgit v1.2.3 From 63d1b881a61086cde7b425ae59a8753a35614ae1 Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 18:32:38 +0100 Subject: Try to fix relative links in README.md --- README.md | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 7ee92f93..814d2196 100644 --- a/README.md +++ b/README.md @@ -15,25 +15,25 @@ for several papers, available from http://www.cl.cam.ac.uk/~pes20/sail/ This repository contains the implementation of Sail, together with some Sail specifications and related tools. -* A manual, [manual.pdf] with source (in [doc/]) +* A manual, [manual.pdf] with source (in [doc/](doc/)) -* The Sail source code (in [src/]) +* The Sail source code (in [src/](src/)) -* A Sail specification of a MIPS ISA (in [mips/]) +* A Sail specification of a MIPS ISA (in [mips/](mips/)) -* A Sail specification of the CHERI MIPS ISA (in [cheri/]) +* A Sail specification of the CHERI MIPS ISA (in [cheri/](cheri/)) * A Sail specification of ARMv8.3 generated from ARM's publically - released ASL specification (in [aarch64/]) + released ASL specification (in [aarch64/](aarch64/)) -* Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle] +* Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle](snapshots/isabelle) * Documentation for generating Isabelle and working with the ISA specs - in Isabelle in [snapshots/isabelle/manual.pdf] + in Isabelle in [snapshots/isabelle/manual.pdf](snapshots/isabelle/manual.pdf) -* A simple emacs mode with syntax highlighting (in [editors/]) +* A simple emacs mode with syntax highlighting (in [editors/](editors/)) -* A test suite for Sail (in [test/]) +* A test suite for Sail (in [test/](test/)) We also have versions of IBM POWER, a fragment of x86, and a hand-written fragment of ARM, but these are currently not up-to-date @@ -43,7 +43,7 @@ on Github. Building ======== -See [INSTALL.md] for full details of how to build Sail from source +See [INSTALL.md](INSTALL.md) for full details of how to build Sail from source with all the required dependencies. OPAM Installation @@ -56,7 +56,7 @@ to get pre-built binaries of Sail using OPAM. Emacs Mode ========== -[editors/sail2-mode.el] contains an Emacs mode for the most recent +[editors/sail2-mode.el](editors/sail2-mode.el) contains an Emacs mode for the most recent version of Sail which provides some basic syntax highlighting. [editors/sail-mode.el] Contains an emacs mode for previous versions of the language. -- cgit v1.2.3 From 29a98ea4f127f921b0b4abf800311fde325d06a7 Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 18:40:35 +0100 Subject: Fix some links and be more clear about licensing --- LICENCE | 8 ++++++-- README.md | 13 +++++++------ 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/LICENCE b/LICENCE index 451ce6c3..c3aa62aa 100644 --- a/LICENCE +++ b/LICENCE @@ -1,12 +1,16 @@ Sail Sail and the Sail architecture models here, comprising all files and -directories except the PPrint library, are subject to the BSD -two-clause licence below. +directories except the PPrint library, and ASL-derived Sail code in +the aarch64 directory, are subject to the BSD two-clause licence +below. The PPrint library, in src/pprint, is subject to the CeCILL-C free software licence agreement therein. +The ASL derived parts of the ARMv8.3 specification in +aarch64/no_vector and aarch64/full are copyright ARM Ltd. + Copyright (c) 2013-2018 Kathyrn Gray Shaked Flur diff --git a/README.md b/README.md index 814d2196..9da4d5d6 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ -Sail ISA specification language -=============================== +The Sail ISA specification language +=================================== Overview ======== @@ -29,7 +29,7 @@ some Sail specifications and related tools. * Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle](snapshots/isabelle) * Documentation for generating Isabelle and working with the ISA specs - in Isabelle in [snapshots/isabelle/manual.pdf](snapshots/isabelle/manual.pdf) + in Isabelle in [snapshots/isabelle/Manual.pdf](snapshots/isabelle/Manual.pdf) * A simple emacs mode with syntax highlighting (in [editors/](editors/)) @@ -49,7 +49,7 @@ with all the required dependencies. OPAM Installation ================= -See the Sail [wiki +See the following Sail [wiki page](https://github.com/rems-project/sail/wiki/OPAMInstall) for how to get pre-built binaries of Sail using OPAM. @@ -70,8 +70,9 @@ other supporting files in lib/ and language/, is distributed under the with the exception of the library src/pprint, which is distributed under the CeCILL-C free software licence in src/pprint/LICENSE. -The ASL-derived ARMv8.3 model in aarch64/ is copyright ARM Ltd. See -https://github.com/meriac/archex +The generated parts of the ASL-derived ARMv8.3 model in aarch64/ are +copyright ARM Ltd. See https://github.com/meriac/archex, and the +[README file](aarch64/README) in that directory. The hand-written ARMv8 model, in arm/, is distributed under the 2-clause BSD licence in the headers of those files. -- cgit v1.2.3 From 8429ef315cd1c58505863ee82cc1411635ca7162 Mon Sep 17 00:00:00 2001 From: Alasdair Armstrong Date: Fri, 11 May 2018 18:52:17 +0100 Subject: Fix last few links in README.md --- README.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 9da4d5d6..9de94d32 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ for several papers, available from http://www.cl.cam.ac.uk/~pes20/sail/ This repository contains the implementation of Sail, together with some Sail specifications and related tools. -* A manual, [manual.pdf] with source (in [doc/](doc/)) +* A manual, [manual.pdf](manual.pdf) with source (in [doc/](doc/)) * The Sail source code (in [src/](src/)) @@ -56,10 +56,10 @@ to get pre-built binaries of Sail using OPAM. Emacs Mode ========== -[editors/sail2-mode.el](editors/sail2-mode.el) contains an Emacs mode for the most recent -version of Sail which provides some basic syntax -highlighting. [editors/sail-mode.el] Contains an emacs mode for -previous versions of the language. +[editors/sail2-mode.el](editors/sail2-mode.el) contains an Emacs mode +for the most recent version of Sail which provides some basic syntax +highlighting. [editors/sail-mode.el](editors/sail-mode.el) contains an +emacs mode for previous versions of the language. Licensing ========= -- cgit v1.2.3 From 492d9cf0dff031f6a0cad9dcc4815f1d113579c7 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Fri, 11 May 2018 18:18:08 +0100 Subject: Add Isabelle snapshot of AArch64 with Brian's monomorphisation --- aarch64/mono/aarch64_extras.lem | 4 + snapshots/isabelle/aarch64/Aarch64.thy | 35928 ++++++++++++++++++++++++ snapshots/isabelle/aarch64/Aarch64_extras.thy | 194 + snapshots/isabelle/aarch64/Aarch64_lemmas.thy | 1075 + snapshots/isabelle/aarch64/Aarch64_types.thy | 2511 ++ 5 files changed, 39712 insertions(+) create mode 100644 snapshots/isabelle/aarch64/Aarch64.thy create mode 100644 snapshots/isabelle/aarch64/Aarch64_extras.thy create mode 100644 snapshots/isabelle/aarch64/Aarch64_lemmas.thy create mode 100644 snapshots/isabelle/aarch64/Aarch64_types.thy diff --git a/aarch64/mono/aarch64_extras.lem b/aarch64/mono/aarch64_extras.lem index e5da7f69..a50ba76f 100644 --- a/aarch64/mono/aarch64_extras.lem +++ b/aarch64/mono/aarch64_extras.lem @@ -128,3 +128,7 @@ val read_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c => let read_ram addrsize size hexRAM address = (*let _ = prerr_endline ("Reading " ^ (stringFromInteger size) ^ " bytes from address " ^ (stringFromInteger (unsigned address))) in*) read_mem Read_plain address size + +val elf_entry : unit -> integer +let elf_entry () = 0 +declare ocaml target_rep function elf_entry = `Elf_loader.elf_entry` diff --git a/snapshots/isabelle/aarch64/Aarch64.thy b/snapshots/isabelle/aarch64/Aarch64.thy new file mode 100644 index 00000000..a117b761 --- /dev/null +++ b/snapshots/isabelle/aarch64/Aarch64.thy @@ -0,0 +1,35928 @@ +chapter \Generated by Lem from aarch64.lem.\ + +theory "Aarch64" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Aarch64_types" + "Aarch64_extras" + +begin + +(*Generated by Sail from aarch64.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Aarch64_types*) +(*open import Aarch64_extras*) + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +definition neq_bool :: " bool \ bool \ bool " where + " neq_bool x y = ( \ (((x = y))))" + + +(*val vcons : forall 'a. 'a -> list 'a -> list 'a*) + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => itself 'n -> ii -> ii -> mword 'n*) + +definition GetSlice_int :: "('n::len)itself \ int \ int \('n::len)Word.word " where + " GetSlice_int n m o1 = ( + (let n = (size_itself_int n) in + (get_slice_int0 n m o1 :: ( 'n::len)Word.word)))" + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __TraceMemoryWrite : forall 'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*) + +(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*) + +definition InitRAM :: " int \ int \('m::len)Word.word \(8)Word.word \ unit " where + " InitRAM g__615 g__616 g__617 g__618 = ( () )" + + +(*val __TraceMemoryRead : forall 'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*) + +(*val ex_nat : ii -> integer*) + +definition ex_nat :: " int \ int " where + " ex_nat n = ( n )" + + +(*val ex_int : ii -> integer*) + +definition ex_int :: " int \ int " where + " ex_int n = ( n )" + + +(*val ex_range : integer -> integer*) + +(*val coerce_int_nat : ii -> M ii*) + +definition coerce_int_nat :: " int \((register_value),(int),(exception))monad " where + " coerce_int_nat x = ( assert_exp True (''Cannot coerce int to nat'') \ return x )" + + +(*val break : unit -> unit*) + +definition break :: " unit \ unit " where + " break _ = ( () )" + + +(*val undefined_exception : unit -> M exception*) + +definition undefined_exception :: " unit \((register_value),(exception),(exception))monad " where + " undefined_exception _ = ( + (undefined_unit () \ + undefined_string () ) \ (\ (w__0 :: string) . + undefined_string () \ (\ (w__1 :: string) . + (undefined_unit () \ + undefined_unit () ) \ + internal_pick + [Error_Undefined () ,Error_See w__0,Error_Implementation_Defined w__1,Error_ReservedEncoding () ,Error_ExceptionTaken () ])))" + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \('n::len)Word.word \('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \('n::len)Word.word \('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \ int \ int \('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \ int \ int \ bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \ int \ int \ bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word \ int \ int \('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \('n::len)Word.word \ int \ int \ int \('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \ int \ int \('n::len)Word.word \ int \ int \ bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word \ int \ int \('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) + j' + :: ( 'm::len)Word.word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) + ((j' - (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \('n::len)Word.word \ int \ int \ int \('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \('n::len)Word.word \ int \ int \ int \('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \ int \ int \ int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \ int \ int \ int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \ int \('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + +(*val boolean_of_num : integer -> boolean*) + +definition boolean_of_num :: " int \ boolean " where + " boolean_of_num arg0 = ( + (let l__595 = arg0 in + if (((l__595 = (( 0 :: int)::ii)))) then FALSE + else TRUE))" + + +(*val num_of_boolean : boolean -> integer*) + +fun num_of_boolean :: " boolean \ int " where + " num_of_boolean FALSE = ( (( 0 :: int)::ii))" +|" num_of_boolean TRUE = ( (( 1 :: int)::ii))" + + +(*val undefined_boolean : unit -> M boolean*) + +definition undefined_boolean :: " unit \((register_value),(boolean),(exception))monad " where + " undefined_boolean _ = ( internal_pick [FALSE,TRUE])" + + +(*val signal_of_num : integer -> signal*) + +definition signal_of_num :: " int \ signal " where + " signal_of_num arg0 = ( + (let l__594 = arg0 in + if (((l__594 = (( 0 :: int)::ii)))) then LOW + else HIGH))" + + +(*val num_of_signal : signal -> integer*) + +fun num_of_signal :: " signal \ int " where + " num_of_signal LOW = ( (( 0 :: int)::ii))" +|" num_of_signal HIGH = ( (( 1 :: int)::ii))" + + +(*val undefined_signal : unit -> M signal*) + +definition undefined_signal :: " unit \((register_value),(signal),(exception))monad " where + " undefined_signal _ = ( internal_pick [LOW,HIGH])" + + +(*val __RetCode_of_num : integer -> __RetCode*) + +definition RetCode_of_num :: " int \ RetCode " where + " RetCode_of_num arg0 = ( + (let l__586 = arg0 in + if (((l__586 = (( 0 :: int)::ii)))) then RC_OK + else if (((l__586 = (( 1 :: int)::ii)))) then RC_UNDEFINED + else if (((l__586 = (( 2 :: int)::ii)))) then RC_UNPREDICTABLE + else if (((l__586 = (( 3 :: int)::ii)))) then RC_SEE + else if (((l__586 = (( 4 :: int)::ii)))) then RC_IMPLEMENTATION_DEFINED + else if (((l__586 = (( 5 :: int)::ii)))) then RC_SUBARCHITECTURE_DEFINED + else if (((l__586 = (( 6 :: int)::ii)))) then RC_EXCEPTION_TAKEN + else if (((l__586 = (( 7 :: int)::ii)))) then RC_ASSERT_FAILED + else RC_UNMATCHED_CASE))" + + +(*val num_of___RetCode : __RetCode -> integer*) + +fun num_of___RetCode :: " RetCode \ int " where + " num_of___RetCode RC_OK = ( (( 0 :: int)::ii))" +|" num_of___RetCode RC_UNDEFINED = ( (( 1 :: int)::ii))" +|" num_of___RetCode RC_UNPREDICTABLE = ( (( 2 :: int)::ii))" +|" num_of___RetCode RC_SEE = ( (( 3 :: int)::ii))" +|" num_of___RetCode RC_IMPLEMENTATION_DEFINED = ( (( 4 :: int)::ii))" +|" num_of___RetCode RC_SUBARCHITECTURE_DEFINED = ( (( 5 :: int)::ii))" +|" num_of___RetCode RC_EXCEPTION_TAKEN = ( (( 6 :: int)::ii))" +|" num_of___RetCode RC_ASSERT_FAILED = ( (( 7 :: int)::ii))" +|" num_of___RetCode RC_UNMATCHED_CASE = ( (( 8 :: int)::ii))" + + +(*val undefined___RetCode : unit -> M __RetCode*) + +definition undefined___RetCode :: " unit \((register_value),(RetCode),(exception))monad " where + " undefined___RetCode _ = ( + internal_pick + [RC_OK,RC_UNDEFINED,RC_UNPREDICTABLE,RC_SEE,RC_IMPLEMENTATION_DEFINED,RC_SUBARCHITECTURE_DEFINED,RC_EXCEPTION_TAKEN,RC_ASSERT_FAILED,RC_UNMATCHED_CASE])" + + +(*val FPConvOp_of_num : integer -> FPConvOp*) + +definition FPConvOp_of_num :: " int \ FPConvOp " where + " FPConvOp_of_num arg0 = ( + (let l__582 = arg0 in + if (((l__582 = (( 0 :: int)::ii)))) then FPConvOp_CVT_FtoI + else if (((l__582 = (( 1 :: int)::ii)))) then FPConvOp_CVT_ItoF + else if (((l__582 = (( 2 :: int)::ii)))) then FPConvOp_MOV_FtoI + else if (((l__582 = (( 3 :: int)::ii)))) then FPConvOp_MOV_ItoF + else FPConvOp_CVT_FtoI_JS))" + + +(*val num_of_FPConvOp : FPConvOp -> integer*) + +fun num_of_FPConvOp :: " FPConvOp \ int " where + " num_of_FPConvOp FPConvOp_CVT_FtoI = ( (( 0 :: int)::ii))" +|" num_of_FPConvOp FPConvOp_CVT_ItoF = ( (( 1 :: int)::ii))" +|" num_of_FPConvOp FPConvOp_MOV_FtoI = ( (( 2 :: int)::ii))" +|" num_of_FPConvOp FPConvOp_MOV_ItoF = ( (( 3 :: int)::ii))" +|" num_of_FPConvOp FPConvOp_CVT_FtoI_JS = ( (( 4 :: int)::ii))" + + +(*val undefined_FPConvOp : unit -> M FPConvOp*) + +definition undefined_FPConvOp :: " unit \((register_value),(FPConvOp),(exception))monad " where + " undefined_FPConvOp _ = ( + internal_pick + [FPConvOp_CVT_FtoI,FPConvOp_CVT_ItoF,FPConvOp_MOV_FtoI,FPConvOp_MOV_ItoF,FPConvOp_CVT_FtoI_JS])" + + +(*val Exception_of_num : integer -> Exception*) + +definition Exception_of_num :: " int \ Exception " where + " Exception_of_num arg0 = ( + (let l__554 = arg0 in + if (((l__554 = (( 0 :: int)::ii)))) then Exception_Uncategorized + else if (((l__554 = (( 1 :: int)::ii)))) then Exception_WFxTrap + else if (((l__554 = (( 2 :: int)::ii)))) then Exception_CP15RTTrap + else if (((l__554 = (( 3 :: int)::ii)))) then Exception_CP15RRTTrap + else if (((l__554 = (( 4 :: int)::ii)))) then Exception_CP14RTTrap + else if (((l__554 = (( 5 :: int)::ii)))) then Exception_CP14DTTrap + else if (((l__554 = (( 6 :: int)::ii)))) then Exception_AdvSIMDFPAccessTrap + else if (((l__554 = (( 7 :: int)::ii)))) then Exception_FPIDTrap + else if (((l__554 = (( 8 :: int)::ii)))) then Exception_PACTrap + else if (((l__554 = (( 9 :: int)::ii)))) then Exception_CP14RRTTrap + else if (((l__554 = (( 10 :: int)::ii)))) then Exception_IllegalState + else if (((l__554 = (( 11 :: int)::ii)))) then Exception_SupervisorCall + else if (((l__554 = (( 12 :: int)::ii)))) then Exception_HypervisorCall + else if (((l__554 = (( 13 :: int)::ii)))) then Exception_MonitorCall + else if (((l__554 = (( 14 :: int)::ii)))) then Exception_SystemRegisterTrap + else if (((l__554 = (( 15 :: int)::ii)))) then Exception_ERetTrap + else if (((l__554 = (( 16 :: int)::ii)))) then Exception_InstructionAbort + else if (((l__554 = (( 17 :: int)::ii)))) then Exception_PCAlignment + else if (((l__554 = (( 18 :: int)::ii)))) then Exception_DataAbort + else if (((l__554 = (( 19 :: int)::ii)))) then Exception_SPAlignment + else if (((l__554 = (( 20 :: int)::ii)))) then Exception_FPTrappedException + else if (((l__554 = (( 21 :: int)::ii)))) then Exception_SError + else if (((l__554 = (( 22 :: int)::ii)))) then Exception_Breakpoint + else if (((l__554 = (( 23 :: int)::ii)))) then Exception_SoftwareStep + else if (((l__554 = (( 24 :: int)::ii)))) then Exception_Watchpoint + else if (((l__554 = (( 25 :: int)::ii)))) then Exception_SoftwareBreakpoint + else if (((l__554 = (( 26 :: int)::ii)))) then Exception_VectorCatch + else if (((l__554 = (( 27 :: int)::ii)))) then Exception_IRQ + else Exception_FIQ))" + + +(*val num_of_Exception : Exception -> integer*) + +fun num_of_Exception :: " Exception \ int " where + " num_of_Exception Exception_Uncategorized = ( (( 0 :: int)::ii))" +|" num_of_Exception Exception_WFxTrap = ( (( 1 :: int)::ii))" +|" num_of_Exception Exception_CP15RTTrap = ( (( 2 :: int)::ii))" +|" num_of_Exception Exception_CP15RRTTrap = ( (( 3 :: int)::ii))" +|" num_of_Exception Exception_CP14RTTrap = ( (( 4 :: int)::ii))" +|" num_of_Exception Exception_CP14DTTrap = ( (( 5 :: int)::ii))" +|" num_of_Exception Exception_AdvSIMDFPAccessTrap = ( (( 6 :: int)::ii))" +|" num_of_Exception Exception_FPIDTrap = ( (( 7 :: int)::ii))" +|" num_of_Exception Exception_PACTrap = ( (( 8 :: int)::ii))" +|" num_of_Exception Exception_CP14RRTTrap = ( (( 9 :: int)::ii))" +|" num_of_Exception Exception_IllegalState = ( (( 10 :: int)::ii))" +|" num_of_Exception Exception_SupervisorCall = ( (( 11 :: int)::ii))" +|" num_of_Exception Exception_HypervisorCall = ( (( 12 :: int)::ii))" +|" num_of_Exception Exception_MonitorCall = ( (( 13 :: int)::ii))" +|" num_of_Exception Exception_SystemRegisterTrap = ( (( 14 :: int)::ii))" +|" num_of_Exception Exception_ERetTrap = ( (( 15 :: int)::ii))" +|" num_of_Exception Exception_InstructionAbort = ( (( 16 :: int)::ii))" +|" num_of_Exception Exception_PCAlignment = ( (( 17 :: int)::ii))" +|" num_of_Exception Exception_DataAbort = ( (( 18 :: int)::ii))" +|" num_of_Exception Exception_SPAlignment = ( (( 19 :: int)::ii))" +|" num_of_Exception Exception_FPTrappedException = ( (( 20 :: int)::ii))" +|" num_of_Exception Exception_SError = ( (( 21 :: int)::ii))" +|" num_of_Exception Exception_Breakpoint = ( (( 22 :: int)::ii))" +|" num_of_Exception Exception_SoftwareStep = ( (( 23 :: int)::ii))" +|" num_of_Exception Exception_Watchpoint = ( (( 24 :: int)::ii))" +|" num_of_Exception Exception_SoftwareBreakpoint = ( (( 25 :: int)::ii))" +|" num_of_Exception Exception_VectorCatch = ( (( 26 :: int)::ii))" +|" num_of_Exception Exception_IRQ = ( (( 27 :: int)::ii))" +|" num_of_Exception Exception_FIQ = ( (( 28 :: int)::ii))" + + +(*val undefined_Exception : unit -> M Exception*) + +definition undefined_Exception :: " unit \((register_value),(Exception),(exception))monad " where + " undefined_Exception _ = ( + internal_pick + [Exception_Uncategorized,Exception_WFxTrap,Exception_CP15RTTrap,Exception_CP15RRTTrap,Exception_CP14RTTrap,Exception_CP14DTTrap,Exception_AdvSIMDFPAccessTrap,Exception_FPIDTrap,Exception_PACTrap,Exception_CP14RRTTrap,Exception_IllegalState,Exception_SupervisorCall,Exception_HypervisorCall,Exception_MonitorCall,Exception_SystemRegisterTrap,Exception_ERetTrap,Exception_InstructionAbort,Exception_PCAlignment,Exception_DataAbort,Exception_SPAlignment,Exception_FPTrappedException,Exception_SError,Exception_Breakpoint,Exception_SoftwareStep,Exception_Watchpoint,Exception_SoftwareBreakpoint,Exception_VectorCatch,Exception_IRQ,Exception_FIQ])" + + +(*val ArchVersion_of_num : integer -> ArchVersion*) + +definition ArchVersion_of_num :: " int \ ArchVersion " where + " ArchVersion_of_num arg0 = ( + (let l__551 = arg0 in + if (((l__551 = (( 0 :: int)::ii)))) then ARMv8p0 + else if (((l__551 = (( 1 :: int)::ii)))) then ARMv8p1 + else if (((l__551 = (( 2 :: int)::ii)))) then ARMv8p2 + else ARMv8p3))" + + +(*val num_of_ArchVersion : ArchVersion -> integer*) + +fun num_of_ArchVersion :: " ArchVersion \ int " where + " num_of_ArchVersion ARMv8p0 = ( (( 0 :: int)::ii))" +|" num_of_ArchVersion ARMv8p1 = ( (( 1 :: int)::ii))" +|" num_of_ArchVersion ARMv8p2 = ( (( 2 :: int)::ii))" +|" num_of_ArchVersion ARMv8p3 = ( (( 3 :: int)::ii))" + + +(*val undefined_ArchVersion : unit -> M ArchVersion*) + +definition undefined_ArchVersion :: " unit \((register_value),(ArchVersion),(exception))monad " where + " undefined_ArchVersion _ = ( internal_pick [ARMv8p0,ARMv8p1,ARMv8p2,ARMv8p3])" + + +(*val Unpredictable_of_num : integer -> Unpredictable*) + +definition Unpredictable_of_num :: " int \ Unpredictable " where + " Unpredictable_of_num arg0 = ( + (let l__507 = arg0 in + if (((l__507 = (( 0 :: int)::ii)))) then Unpredictable_WBOVERLAPLD + else if (((l__507 = (( 1 :: int)::ii)))) then Unpredictable_WBOVERLAPST + else if (((l__507 = (( 2 :: int)::ii)))) then Unpredictable_LDPOVERLAP + else if (((l__507 = (( 3 :: int)::ii)))) then Unpredictable_BASEOVERLAP + else if (((l__507 = (( 4 :: int)::ii)))) then Unpredictable_DATAOVERLAP + else if (((l__507 = (( 5 :: int)::ii)))) then Unpredictable_DEVPAGE2 + else if (((l__507 = (( 6 :: int)::ii)))) then Unpredictable_INSTRDEVICE + else if (((l__507 = (( 7 :: int)::ii)))) then Unpredictable_RESCPACR + else if (((l__507 = (( 8 :: int)::ii)))) then Unpredictable_RESMAIR + else if (((l__507 = (( 9 :: int)::ii)))) then Unpredictable_RESTEXCB + else if (((l__507 = (( 10 :: int)::ii)))) then Unpredictable_RESPRRR + else if (((l__507 = (( 11 :: int)::ii)))) then Unpredictable_RESDACR + else if (((l__507 = (( 12 :: int)::ii)))) then Unpredictable_RESVTCRS + else if (((l__507 = (( 13 :: int)::ii)))) then Unpredictable_RESTnSZ + else if (((l__507 = (( 14 :: int)::ii)))) then Unpredictable_OORTnSZ + else if (((l__507 = (( 15 :: int)::ii)))) then Unpredictable_LARGEIPA + else if (((l__507 = (( 16 :: int)::ii)))) then Unpredictable_ESRCONDPASS + else if (((l__507 = (( 17 :: int)::ii)))) then Unpredictable_ILZEROIT + else if (((l__507 = (( 18 :: int)::ii)))) then Unpredictable_ILZEROT + else if (((l__507 = (( 19 :: int)::ii)))) then Unpredictable_BPVECTORCATCHPRI + else if (((l__507 = (( 20 :: int)::ii)))) then Unpredictable_VCMATCHHALF + else if (((l__507 = (( 21 :: int)::ii)))) then Unpredictable_VCMATCHDAPA + else if (((l__507 = (( 22 :: int)::ii)))) then Unpredictable_WPMASKANDBAS + else if (((l__507 = (( 23 :: int)::ii)))) then Unpredictable_WPBASCONTIGUOUS + else if (((l__507 = (( 24 :: int)::ii)))) then Unpredictable_RESWPMASK + else if (((l__507 = (( 25 :: int)::ii)))) then Unpredictable_WPMASKEDBITS + else if (((l__507 = (( 26 :: int)::ii)))) then Unpredictable_RESBPWPCTRL + else if (((l__507 = (( 27 :: int)::ii)))) then Unpredictable_BPNOTIMPL + else if (((l__507 = (( 28 :: int)::ii)))) then Unpredictable_RESBPTYPE + else if (((l__507 = (( 29 :: int)::ii)))) then Unpredictable_BPNOTCTXCMP + else if (((l__507 = (( 30 :: int)::ii)))) then Unpredictable_BPMATCHHALF + else if (((l__507 = (( 31 :: int)::ii)))) then Unpredictable_BPMISMATCHHALF + else if (((l__507 = (( 32 :: int)::ii)))) then Unpredictable_RESTARTALIGNPC + else if (((l__507 = (( 33 :: int)::ii)))) then Unpredictable_RESTARTZEROUPPERPC + else if (((l__507 = (( 34 :: int)::ii)))) then Unpredictable_ZEROUPPER + else if (((l__507 = (( 35 :: int)::ii)))) then Unpredictable_ERETZEROUPPERPC + else if (((l__507 = (( 36 :: int)::ii)))) then Unpredictable_A32FORCEALIGNPC + else if (((l__507 = (( 37 :: int)::ii)))) then Unpredictable_SMD + else if (((l__507 = (( 38 :: int)::ii)))) then Unpredictable_AFUPDATE + else if (((l__507 = (( 39 :: int)::ii)))) then Unpredictable_IESBinDebug + else if (((l__507 = (( 40 :: int)::ii)))) then Unpredictable_ZEROPMSEVFR + else if (((l__507 = (( 41 :: int)::ii)))) then Unpredictable_NOOPTYPES + else if (((l__507 = (( 42 :: int)::ii)))) then Unpredictable_ZEROMINLATENCY + else if (((l__507 = (( 43 :: int)::ii)))) then Unpredictable_CLEARERRITEZERO + else Unpredictable_TBD))" + + +(*val num_of_Unpredictable : Unpredictable -> integer*) + +fun num_of_Unpredictable :: " Unpredictable \ int " where + " num_of_Unpredictable Unpredictable_WBOVERLAPLD = ( (( 0 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_WBOVERLAPST = ( (( 1 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_LDPOVERLAP = ( (( 2 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BASEOVERLAP = ( (( 3 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_DATAOVERLAP = ( (( 4 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_DEVPAGE2 = ( (( 5 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_INSTRDEVICE = ( (( 6 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESCPACR = ( (( 7 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESMAIR = ( (( 8 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESTEXCB = ( (( 9 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESPRRR = ( (( 10 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESDACR = ( (( 11 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESVTCRS = ( (( 12 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESTnSZ = ( (( 13 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_OORTnSZ = ( (( 14 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_LARGEIPA = ( (( 15 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ESRCONDPASS = ( (( 16 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ILZEROIT = ( (( 17 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ILZEROT = ( (( 18 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BPVECTORCATCHPRI = ( (( 19 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_VCMATCHHALF = ( (( 20 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_VCMATCHDAPA = ( (( 21 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_WPMASKANDBAS = ( (( 22 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_WPBASCONTIGUOUS = ( (( 23 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESWPMASK = ( (( 24 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_WPMASKEDBITS = ( (( 25 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESBPWPCTRL = ( (( 26 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BPNOTIMPL = ( (( 27 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESBPTYPE = ( (( 28 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BPNOTCTXCMP = ( (( 29 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BPMATCHHALF = ( (( 30 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_BPMISMATCHHALF = ( (( 31 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESTARTALIGNPC = ( (( 32 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_RESTARTZEROUPPERPC = ( (( 33 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ZEROUPPER = ( (( 34 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ERETZEROUPPERPC = ( (( 35 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_A32FORCEALIGNPC = ( (( 36 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_SMD = ( (( 37 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_AFUPDATE = ( (( 38 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_IESBinDebug = ( (( 39 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ZEROPMSEVFR = ( (( 40 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_NOOPTYPES = ( (( 41 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_ZEROMINLATENCY = ( (( 42 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_CLEARERRITEZERO = ( (( 43 :: int)::ii))" +|" num_of_Unpredictable Unpredictable_TBD = ( (( 44 :: int)::ii))" + + +(*val undefined_Unpredictable : unit -> M Unpredictable*) + +definition undefined_Unpredictable :: " unit \((register_value),(Unpredictable),(exception))monad " where + " undefined_Unpredictable _ = ( + internal_pick + [Unpredictable_WBOVERLAPLD,Unpredictable_WBOVERLAPST,Unpredictable_LDPOVERLAP,Unpredictable_BASEOVERLAP,Unpredictable_DATAOVERLAP,Unpredictable_DEVPAGE2,Unpredictable_INSTRDEVICE,Unpredictable_RESCPACR,Unpredictable_RESMAIR,Unpredictable_RESTEXCB,Unpredictable_RESPRRR,Unpredictable_RESDACR,Unpredictable_RESVTCRS,Unpredictable_RESTnSZ,Unpredictable_OORTnSZ,Unpredictable_LARGEIPA,Unpredictable_ESRCONDPASS,Unpredictable_ILZEROIT,Unpredictable_ILZEROT,Unpredictable_BPVECTORCATCHPRI,Unpredictable_VCMATCHHALF,Unpredictable_VCMATCHDAPA,Unpredictable_WPMASKANDBAS,Unpredictable_WPBASCONTIGUOUS,Unpredictable_RESWPMASK,Unpredictable_WPMASKEDBITS,Unpredictable_RESBPWPCTRL,Unpredictable_BPNOTIMPL,Unpredictable_RESBPTYPE,Unpredictable_BPNOTCTXCMP,Unpredictable_BPMATCHHALF,Unpredictable_BPMISMATCHHALF,Unpredictable_RESTARTALIGNPC,Unpredictable_RESTARTZEROUPPERPC,Unpredictable_ZEROUPPER,Unpredictable_ERETZEROUPPERPC,Unpredictable_A32FORCEALIGNPC,Unpredictable_SMD,Unpredictable_AFUPDATE,Unpredictable_IESBinDebug,Unpredictable_ZEROPMSEVFR,Unpredictable_NOOPTYPES,Unpredictable_ZEROMINLATENCY,Unpredictable_CLEARERRITEZERO,Unpredictable_TBD])" + + +(*val Constraint_of_num : integer -> Constraint*) + +definition Constraint_of_num :: " int \ Constraint " where + " Constraint_of_num arg0 = ( + (let l__493 = arg0 in + if (((l__493 = (( 0 :: int)::ii)))) then Constraint_NONE + else if (((l__493 = (( 1 :: int)::ii)))) then Constraint_UNKNOWN + else if (((l__493 = (( 2 :: int)::ii)))) then Constraint_UNDEF + else if (((l__493 = (( 3 :: int)::ii)))) then Constraint_UNDEFEL0 + else if (((l__493 = (( 4 :: int)::ii)))) then Constraint_NOP + else if (((l__493 = (( 5 :: int)::ii)))) then Constraint_TRUE + else if (((l__493 = (( 6 :: int)::ii)))) then Constraint_FALSE + else if (((l__493 = (( 7 :: int)::ii)))) then Constraint_DISABLED + else if (((l__493 = (( 8 :: int)::ii)))) then Constraint_UNCOND + else if (((l__493 = (( 9 :: int)::ii)))) then Constraint_COND + else if (((l__493 = (( 10 :: int)::ii)))) then Constraint_ADDITIONAL_DECODE + else if (((l__493 = (( 11 :: int)::ii)))) then Constraint_WBSUPPRESS + else if (((l__493 = (( 12 :: int)::ii)))) then Constraint_FAULT + else if (((l__493 = (( 13 :: int)::ii)))) then Constraint_FORCE + else Constraint_FORCENOSLCHECK))" + + +(*val num_of_Constraint : Constraint -> integer*) + +fun num_of_Constraint :: " Constraint \ int " where + " num_of_Constraint Constraint_NONE = ( (( 0 :: int)::ii))" +|" num_of_Constraint Constraint_UNKNOWN = ( (( 1 :: int)::ii))" +|" num_of_Constraint Constraint_UNDEF = ( (( 2 :: int)::ii))" +|" num_of_Constraint Constraint_UNDEFEL0 = ( (( 3 :: int)::ii))" +|" num_of_Constraint Constraint_NOP = ( (( 4 :: int)::ii))" +|" num_of_Constraint Constraint_TRUE = ( (( 5 :: int)::ii))" +|" num_of_Constraint Constraint_FALSE = ( (( 6 :: int)::ii))" +|" num_of_Constraint Constraint_DISABLED = ( (( 7 :: int)::ii))" +|" num_of_Constraint Constraint_UNCOND = ( (( 8 :: int)::ii))" +|" num_of_Constraint Constraint_COND = ( (( 9 :: int)::ii))" +|" num_of_Constraint Constraint_ADDITIONAL_DECODE = ( (( 10 :: int)::ii))" +|" num_of_Constraint Constraint_WBSUPPRESS = ( (( 11 :: int)::ii))" +|" num_of_Constraint Constraint_FAULT = ( (( 12 :: int)::ii))" +|" num_of_Constraint Constraint_FORCE = ( (( 13 :: int)::ii))" +|" num_of_Constraint Constraint_FORCENOSLCHECK = ( (( 14 :: int)::ii))" + + +(*val undefined_Constraint : unit -> M Constraint*) + +definition undefined_Constraint :: " unit \((register_value),(Constraint),(exception))monad " where + " undefined_Constraint _ = ( + internal_pick + [Constraint_NONE,Constraint_UNKNOWN,Constraint_UNDEF,Constraint_UNDEFEL0,Constraint_NOP,Constraint_TRUE,Constraint_FALSE,Constraint_DISABLED,Constraint_UNCOND,Constraint_COND,Constraint_ADDITIONAL_DECODE,Constraint_WBSUPPRESS,Constraint_FAULT,Constraint_FORCE,Constraint_FORCENOSLCHECK])" + + +(*val InstrSet_of_num : integer -> InstrSet*) + +definition InstrSet_of_num :: " int \ InstrSet " where + " InstrSet_of_num arg0 = ( + (let l__491 = arg0 in + if (((l__491 = (( 0 :: int)::ii)))) then InstrSet_A64 + else if (((l__491 = (( 1 :: int)::ii)))) then InstrSet_A32 + else InstrSet_T32))" + + +(*val num_of_InstrSet : InstrSet -> integer*) + +fun num_of_InstrSet :: " InstrSet \ int " where + " num_of_InstrSet InstrSet_A64 = ( (( 0 :: int)::ii))" +|" num_of_InstrSet InstrSet_A32 = ( (( 1 :: int)::ii))" +|" num_of_InstrSet InstrSet_T32 = ( (( 2 :: int)::ii))" + + +(*val undefined_InstrSet : unit -> M InstrSet*) + +definition undefined_InstrSet :: " unit \((register_value),(InstrSet),(exception))monad " where + " undefined_InstrSet _ = ( internal_pick [InstrSet_A64,InstrSet_A32,InstrSet_T32])" + + +(*val undefined_ProcState : unit -> M ProcState*) + +definition undefined_ProcState :: " unit \((register_value),(ProcState),(exception))monad " where + " undefined_ProcState _ = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__0 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__2 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__3 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__4 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__5 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__6 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__7 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__8 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__9 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__10 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__11 :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__12 :: 2 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__13 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__14 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__15 :: 1 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__16 :: 4 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (w__17 :: 8 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__18 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__19 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__20 :: 1 bits) . + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__21 :: 5 bits) . + return ((| ProcState_N = w__0, + ProcState_Z = w__1, + ProcState_C = w__2, + ProcState_V = w__3, + ProcState_D = w__4, + ProcState_A = w__5, + ProcState_I = w__6, + ProcState_F = w__7, + ProcState_PAN = w__8, + ProcState_UAO = w__9, + ProcState_SS = w__10, + ProcState_IL = w__11, + ProcState_EL = w__12, + ProcState_nRW = w__13, + ProcState_SP = w__14, + ProcState_Q = w__15, + ProcState_GE = w__16, + ProcState_IT = w__17, + ProcState_J = w__18, + ProcState_T = w__19, + ProcState_E = w__20, + ProcState_M = w__21 |)))))))))))))))))))))))))" + + +(*val BranchType_of_num : integer -> BranchType*) + +definition BranchType_of_num :: " int \ BranchType " where + " BranchType_of_num arg0 = ( + (let l__485 = arg0 in + if (((l__485 = (( 0 :: int)::ii)))) then BranchType_CALL + else if (((l__485 = (( 1 :: int)::ii)))) then BranchType_ERET + else if (((l__485 = (( 2 :: int)::ii)))) then BranchType_DBGEXIT + else if (((l__485 = (( 3 :: int)::ii)))) then BranchType_RET + else if (((l__485 = (( 4 :: int)::ii)))) then BranchType_JMP + else if (((l__485 = (( 5 :: int)::ii)))) then BranchType_EXCEPTION + else BranchType_UNKNOWN))" + + +(*val num_of_BranchType : BranchType -> integer*) + +fun num_of_BranchType :: " BranchType \ int " where + " num_of_BranchType BranchType_CALL = ( (( 0 :: int)::ii))" +|" num_of_BranchType BranchType_ERET = ( (( 1 :: int)::ii))" +|" num_of_BranchType BranchType_DBGEXIT = ( (( 2 :: int)::ii))" +|" num_of_BranchType BranchType_RET = ( (( 3 :: int)::ii))" +|" num_of_BranchType BranchType_JMP = ( (( 4 :: int)::ii))" +|" num_of_BranchType BranchType_EXCEPTION = ( (( 5 :: int)::ii))" +|" num_of_BranchType BranchType_UNKNOWN = ( (( 6 :: int)::ii))" + + +(*val undefined_BranchType : unit -> M BranchType*) + +definition undefined_BranchType :: " unit \((register_value),(BranchType),(exception))monad " where + " undefined_BranchType _ = ( + internal_pick + [BranchType_CALL,BranchType_ERET,BranchType_DBGEXIT,BranchType_RET,BranchType_JMP,BranchType_EXCEPTION,BranchType_UNKNOWN])" + + +(*val undefined_ExceptionRecord : unit -> M ExceptionRecord*) + +definition undefined_ExceptionRecord :: " unit \((register_value),(ExceptionRecord),(exception))monad " where + " undefined_ExceptionRecord _ = ( + undefined_Exception () \ (\ (w__0 :: Exception) . + (undefined_bitvector (( 25 :: int)::ii) :: ( 25 Word.word) M) \ (\ (w__1 :: 25 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + undefined_bool () \ (\ (w__3 :: bool) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (w__4 :: 52 bits) . + return ((| ExceptionRecord_typ = w__0, + ExceptionRecord_syndrome = w__1, + ExceptionRecord_vaddress = w__2, + ExceptionRecord_ipavalid = w__3, + ExceptionRecord_ipaddress = w__4 |))))))))" + + +(*val Fault_of_num : integer -> Fault*) + +definition Fault_of_num :: " int \ Fault " where + " Fault_of_num arg0 = ( + (let l__467 = arg0 in + if (((l__467 = (( 0 :: int)::ii)))) then Fault_None + else if (((l__467 = (( 1 :: int)::ii)))) then Fault_AccessFlag + else if (((l__467 = (( 2 :: int)::ii)))) then Fault_Alignment + else if (((l__467 = (( 3 :: int)::ii)))) then Fault_Background + else if (((l__467 = (( 4 :: int)::ii)))) then Fault_Domain + else if (((l__467 = (( 5 :: int)::ii)))) then Fault_Permission + else if (((l__467 = (( 6 :: int)::ii)))) then Fault_Translation + else if (((l__467 = (( 7 :: int)::ii)))) then Fault_AddressSize + else if (((l__467 = (( 8 :: int)::ii)))) then Fault_SyncExternal + else if (((l__467 = (( 9 :: int)::ii)))) then Fault_SyncExternalOnWalk + else if (((l__467 = (( 10 :: int)::ii)))) then Fault_SyncParity + else if (((l__467 = (( 11 :: int)::ii)))) then Fault_SyncParityOnWalk + else if (((l__467 = (( 12 :: int)::ii)))) then Fault_AsyncParity + else if (((l__467 = (( 13 :: int)::ii)))) then Fault_AsyncExternal + else if (((l__467 = (( 14 :: int)::ii)))) then Fault_Debug + else if (((l__467 = (( 15 :: int)::ii)))) then Fault_TLBConflict + else if (((l__467 = (( 16 :: int)::ii)))) then Fault_Lockdown + else if (((l__467 = (( 17 :: int)::ii)))) then Fault_Exclusive + else Fault_ICacheMaint))" + + +(*val num_of_Fault : Fault -> integer*) + +fun num_of_Fault :: " Fault \ int " where + " num_of_Fault Fault_None = ( (( 0 :: int)::ii))" +|" num_of_Fault Fault_AccessFlag = ( (( 1 :: int)::ii))" +|" num_of_Fault Fault_Alignment = ( (( 2 :: int)::ii))" +|" num_of_Fault Fault_Background = ( (( 3 :: int)::ii))" +|" num_of_Fault Fault_Domain = ( (( 4 :: int)::ii))" +|" num_of_Fault Fault_Permission = ( (( 5 :: int)::ii))" +|" num_of_Fault Fault_Translation = ( (( 6 :: int)::ii))" +|" num_of_Fault Fault_AddressSize = ( (( 7 :: int)::ii))" +|" num_of_Fault Fault_SyncExternal = ( (( 8 :: int)::ii))" +|" num_of_Fault Fault_SyncExternalOnWalk = ( (( 9 :: int)::ii))" +|" num_of_Fault Fault_SyncParity = ( (( 10 :: int)::ii))" +|" num_of_Fault Fault_SyncParityOnWalk = ( (( 11 :: int)::ii))" +|" num_of_Fault Fault_AsyncParity = ( (( 12 :: int)::ii))" +|" num_of_Fault Fault_AsyncExternal = ( (( 13 :: int)::ii))" +|" num_of_Fault Fault_Debug = ( (( 14 :: int)::ii))" +|" num_of_Fault Fault_TLBConflict = ( (( 15 :: int)::ii))" +|" num_of_Fault Fault_Lockdown = ( (( 16 :: int)::ii))" +|" num_of_Fault Fault_Exclusive = ( (( 17 :: int)::ii))" +|" num_of_Fault Fault_ICacheMaint = ( (( 18 :: int)::ii))" + + +(*val undefined_Fault : unit -> M Fault*) + +definition undefined_Fault :: " unit \((register_value),(Fault),(exception))monad " where + " undefined_Fault _ = ( + internal_pick + [Fault_None,Fault_AccessFlag,Fault_Alignment,Fault_Background,Fault_Domain,Fault_Permission,Fault_Translation,Fault_AddressSize,Fault_SyncExternal,Fault_SyncExternalOnWalk,Fault_SyncParity,Fault_SyncParityOnWalk,Fault_AsyncParity,Fault_AsyncExternal,Fault_Debug,Fault_TLBConflict,Fault_Lockdown,Fault_Exclusive,Fault_ICacheMaint])" + + +(*val AccType_of_num : integer -> AccType*) + +definition AccType_of_num :: " int \ AccType " where + " AccType_of_num arg0 = ( + (let l__452 = arg0 in + if (((l__452 = (( 0 :: int)::ii)))) then AccType_NORMAL + else if (((l__452 = (( 1 :: int)::ii)))) then AccType_VEC + else if (((l__452 = (( 2 :: int)::ii)))) then AccType_STREAM + else if (((l__452 = (( 3 :: int)::ii)))) then AccType_VECSTREAM + else if (((l__452 = (( 4 :: int)::ii)))) then AccType_ATOMIC + else if (((l__452 = (( 5 :: int)::ii)))) then AccType_ATOMICRW + else if (((l__452 = (( 6 :: int)::ii)))) then AccType_ORDERED + else if (((l__452 = (( 7 :: int)::ii)))) then AccType_ORDEREDRW + else if (((l__452 = (( 8 :: int)::ii)))) then AccType_LIMITEDORDERED + else if (((l__452 = (( 9 :: int)::ii)))) then AccType_UNPRIV + else if (((l__452 = (( 10 :: int)::ii)))) then AccType_IFETCH + else if (((l__452 = (( 11 :: int)::ii)))) then AccType_PTW + else if (((l__452 = (( 12 :: int)::ii)))) then AccType_DC + else if (((l__452 = (( 13 :: int)::ii)))) then AccType_IC + else if (((l__452 = (( 14 :: int)::ii)))) then AccType_DCZVA + else AccType_AT))" + + +(*val num_of_AccType : AccType -> integer*) + +fun num_of_AccType :: " AccType \ int " where + " num_of_AccType AccType_NORMAL = ( (( 0 :: int)::ii))" +|" num_of_AccType AccType_VEC = ( (( 1 :: int)::ii))" +|" num_of_AccType AccType_STREAM = ( (( 2 :: int)::ii))" +|" num_of_AccType AccType_VECSTREAM = ( (( 3 :: int)::ii))" +|" num_of_AccType AccType_ATOMIC = ( (( 4 :: int)::ii))" +|" num_of_AccType AccType_ATOMICRW = ( (( 5 :: int)::ii))" +|" num_of_AccType AccType_ORDERED = ( (( 6 :: int)::ii))" +|" num_of_AccType AccType_ORDEREDRW = ( (( 7 :: int)::ii))" +|" num_of_AccType AccType_LIMITEDORDERED = ( (( 8 :: int)::ii))" +|" num_of_AccType AccType_UNPRIV = ( (( 9 :: int)::ii))" +|" num_of_AccType AccType_IFETCH = ( (( 10 :: int)::ii))" +|" num_of_AccType AccType_PTW = ( (( 11 :: int)::ii))" +|" num_of_AccType AccType_DC = ( (( 12 :: int)::ii))" +|" num_of_AccType AccType_IC = ( (( 13 :: int)::ii))" +|" num_of_AccType AccType_DCZVA = ( (( 14 :: int)::ii))" +|" num_of_AccType AccType_AT = ( (( 15 :: int)::ii))" + + +(*val undefined_AccType : unit -> M AccType*) + +definition undefined_AccType :: " unit \((register_value),(AccType),(exception))monad " where + " undefined_AccType _ = ( + internal_pick + [AccType_NORMAL,AccType_VEC,AccType_STREAM,AccType_VECSTREAM,AccType_ATOMIC,AccType_ATOMICRW,AccType_ORDERED,AccType_ORDEREDRW,AccType_LIMITEDORDERED,AccType_UNPRIV,AccType_IFETCH,AccType_PTW,AccType_DC,AccType_IC,AccType_DCZVA,AccType_AT])" + + +(*val undefined_FaultRecord : unit -> M FaultRecord*) + +definition undefined_FaultRecord :: " unit \((register_value),(FaultRecord),(exception))monad " where + " undefined_FaultRecord _ = ( + undefined_Fault () \ (\ (w__0 :: Fault) . + undefined_AccType () \ (\ (w__1 :: AccType) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (w__2 :: 52 bits) . + undefined_bool () \ (\ (w__3 :: bool) . + undefined_bool () \ (\ (w__4 :: bool) . + undefined_int () \ (\ (w__5 :: ii) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__6 :: 1 bits) . + undefined_bool () \ (\ (w__7 :: bool) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__8 :: 4 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__9 :: 2 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__10 :: 4 bits) . + return ((| FaultRecord_typ = w__0, + FaultRecord_acctype = w__1, + FaultRecord_ipaddress = w__2, + FaultRecord_s2fs1walk = w__3, + FaultRecord_write = w__4, + FaultRecord_level = w__5, + FaultRecord_extflag = w__6, + FaultRecord_secondstage = w__7, + FaultRecord_domain = w__8, + FaultRecord_errortype = w__9, + FaultRecord_debugmoe = w__10 |))))))))))))))" + + +(*val MBReqDomain_of_num : integer -> MBReqDomain*) + +definition MBReqDomain_of_num :: " int \ MBReqDomain " where + " MBReqDomain_of_num arg0 = ( + (let l__449 = arg0 in + if (((l__449 = (( 0 :: int)::ii)))) then MBReqDomain_Nonshareable + else if (((l__449 = (( 1 :: int)::ii)))) then MBReqDomain_InnerShareable + else if (((l__449 = (( 2 :: int)::ii)))) then MBReqDomain_OuterShareable + else MBReqDomain_FullSystem))" + + +(*val num_of_MBReqDomain : MBReqDomain -> integer*) + +fun num_of_MBReqDomain :: " MBReqDomain \ int " where + " num_of_MBReqDomain MBReqDomain_Nonshareable = ( (( 0 :: int)::ii))" +|" num_of_MBReqDomain MBReqDomain_InnerShareable = ( (( 1 :: int)::ii))" +|" num_of_MBReqDomain MBReqDomain_OuterShareable = ( (( 2 :: int)::ii))" +|" num_of_MBReqDomain MBReqDomain_FullSystem = ( (( 3 :: int)::ii))" + + +(*val undefined_MBReqDomain : unit -> M MBReqDomain*) + +definition undefined_MBReqDomain :: " unit \((register_value),(MBReqDomain),(exception))monad " where + " undefined_MBReqDomain _ = ( + internal_pick + [MBReqDomain_Nonshareable,MBReqDomain_InnerShareable,MBReqDomain_OuterShareable,MBReqDomain_FullSystem])" + + +(*val MBReqTypes_of_num : integer -> MBReqTypes*) + +definition MBReqTypes_of_num :: " int \ MBReqTypes " where + " MBReqTypes_of_num arg0 = ( + (let l__447 = arg0 in + if (((l__447 = (( 0 :: int)::ii)))) then MBReqTypes_Reads + else if (((l__447 = (( 1 :: int)::ii)))) then MBReqTypes_Writes + else MBReqTypes_All))" + + +(*val num_of_MBReqTypes : MBReqTypes -> integer*) + +fun num_of_MBReqTypes :: " MBReqTypes \ int " where + " num_of_MBReqTypes MBReqTypes_Reads = ( (( 0 :: int)::ii))" +|" num_of_MBReqTypes MBReqTypes_Writes = ( (( 1 :: int)::ii))" +|" num_of_MBReqTypes MBReqTypes_All = ( (( 2 :: int)::ii))" + + +(*val undefined_MBReqTypes : unit -> M MBReqTypes*) + +definition undefined_MBReqTypes :: " unit \((register_value),(MBReqTypes),(exception))monad " where + " undefined_MBReqTypes _ = ( internal_pick [MBReqTypes_Reads,MBReqTypes_Writes,MBReqTypes_All])" + + +(*val MemType_of_num : integer -> MemType*) + +definition MemType_of_num :: " int \ MemType " where + " MemType_of_num arg0 = ( + (let l__446 = arg0 in + if (((l__446 = (( 0 :: int)::ii)))) then MemType_Normal + else MemType_Device))" + + +(*val num_of_MemType : MemType -> integer*) + +fun num_of_MemType :: " MemType \ int " where + " num_of_MemType MemType_Normal = ( (( 0 :: int)::ii))" +|" num_of_MemType MemType_Device = ( (( 1 :: int)::ii))" + + +(*val undefined_MemType : unit -> M MemType*) + +definition undefined_MemType :: " unit \((register_value),(MemType),(exception))monad " where + " undefined_MemType _ = ( internal_pick [MemType_Normal,MemType_Device])" + + +(*val DeviceType_of_num : integer -> DeviceType*) + +definition DeviceType_of_num :: " int \ DeviceType " where + " DeviceType_of_num arg0 = ( + (let l__443 = arg0 in + if (((l__443 = (( 0 :: int)::ii)))) then DeviceType_GRE + else if (((l__443 = (( 1 :: int)::ii)))) then DeviceType_nGRE + else if (((l__443 = (( 2 :: int)::ii)))) then DeviceType_nGnRE + else DeviceType_nGnRnE))" + + +(*val num_of_DeviceType : DeviceType -> integer*) + +fun num_of_DeviceType :: " DeviceType \ int " where + " num_of_DeviceType DeviceType_GRE = ( (( 0 :: int)::ii))" +|" num_of_DeviceType DeviceType_nGRE = ( (( 1 :: int)::ii))" +|" num_of_DeviceType DeviceType_nGnRE = ( (( 2 :: int)::ii))" +|" num_of_DeviceType DeviceType_nGnRnE = ( (( 3 :: int)::ii))" + + +(*val undefined_DeviceType : unit -> M DeviceType*) + +definition undefined_DeviceType :: " unit \((register_value),(DeviceType),(exception))monad " where + " undefined_DeviceType _ = ( + internal_pick [DeviceType_GRE,DeviceType_nGRE,DeviceType_nGnRE,DeviceType_nGnRnE])" + + +(*val undefined_MemAttrHints : unit -> M MemAttrHints*) + +definition undefined_MemAttrHints :: " unit \((register_value),(MemAttrHints),(exception))monad " where + " undefined_MemAttrHints _ = ( + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__0 :: 2 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__1 :: 2 bits) . + undefined_bool () \ (\ (w__2 :: bool) . + return ((| MemAttrHints_attrs = w__0, + MemAttrHints_hints = w__1, + MemAttrHints_transient = w__2 |))))))" + + +(*val undefined_MemoryAttributes : unit -> M MemoryAttributes*) + +definition undefined_MemoryAttributes :: " unit \((register_value),(MemoryAttributes),(exception))monad " where + " undefined_MemoryAttributes _ = ( + undefined_MemType () \ (\ (w__0 :: MemType) . + undefined_DeviceType () \ (\ (w__1 :: DeviceType) . + undefined_MemAttrHints () \ (\ (w__2 :: MemAttrHints) . + undefined_MemAttrHints () \ (\ (w__3 :: MemAttrHints) . + undefined_bool () \ (\ (w__4 :: bool) . + undefined_bool () \ (\ (w__5 :: bool) . + return ((| MemoryAttributes_typ = w__0, + MemoryAttributes_device = w__1, + MemoryAttributes_inner = w__2, + MemoryAttributes_outer = w__3, + MemoryAttributes_shareable = w__4, + MemoryAttributes_outershareable = w__5 |)))))))))" + + +(*val undefined_FullAddress : unit -> M FullAddress*) + +definition undefined_FullAddress :: " unit \((register_value),(FullAddress),(exception))monad " where + " undefined_FullAddress _ = ( + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (w__0 :: 52 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + return ((| FullAddress_physicaladdress = w__0, + FullAddress_NS = w__1 |)))))" + + +(*val undefined_AddressDescriptor : unit -> M AddressDescriptor*) + +definition undefined_AddressDescriptor :: " unit \((register_value),(AddressDescriptor),(exception))monad " where + " undefined_AddressDescriptor _ = ( + undefined_FaultRecord () \ (\ (w__0 :: FaultRecord) . + undefined_MemoryAttributes () \ (\ (w__1 :: MemoryAttributes) . + undefined_FullAddress () \ (\ (w__2 :: FullAddress) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((| AddressDescriptor_fault = w__0, + AddressDescriptor_memattrs = w__1, + AddressDescriptor_paddress = w__2, + AddressDescriptor_vaddress = w__3 |)))))))" + + +(*val undefined_DescriptorUpdate : unit -> M DescriptorUpdate*) + +definition undefined_DescriptorUpdate :: " unit \((register_value),(DescriptorUpdate),(exception))monad " where + " undefined_DescriptorUpdate _ = ( + undefined_bool () \ (\ (w__0 :: bool) . + undefined_bool () \ (\ (w__1 :: bool) . + undefined_AddressDescriptor () \ (\ (w__2 :: AddressDescriptor) . + return ((| DescriptorUpdate_AF = w__0, + DescriptorUpdate_AP = w__1, + DescriptorUpdate_descaddr = w__2 |))))))" + + +(*val MemAtomicOp_of_num : integer -> MemAtomicOp*) + +definition MemAtomicOp_of_num :: " int \ MemAtomicOp " where + " MemAtomicOp_of_num arg0 = ( + (let l__435 = arg0 in + if (((l__435 = (( 0 :: int)::ii)))) then MemAtomicOp_ADD + else if (((l__435 = (( 1 :: int)::ii)))) then MemAtomicOp_BIC + else if (((l__435 = (( 2 :: int)::ii)))) then MemAtomicOp_EOR + else if (((l__435 = (( 3 :: int)::ii)))) then MemAtomicOp_ORR + else if (((l__435 = (( 4 :: int)::ii)))) then MemAtomicOp_SMAX + else if (((l__435 = (( 5 :: int)::ii)))) then MemAtomicOp_SMIN + else if (((l__435 = (( 6 :: int)::ii)))) then MemAtomicOp_UMAX + else if (((l__435 = (( 7 :: int)::ii)))) then MemAtomicOp_UMIN + else MemAtomicOp_SWP))" + + +(*val num_of_MemAtomicOp : MemAtomicOp -> integer*) + +fun num_of_MemAtomicOp :: " MemAtomicOp \ int " where + " num_of_MemAtomicOp MemAtomicOp_ADD = ( (( 0 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_BIC = ( (( 1 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_EOR = ( (( 2 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_ORR = ( (( 3 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_SMAX = ( (( 4 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_SMIN = ( (( 5 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_UMAX = ( (( 6 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_UMIN = ( (( 7 :: int)::ii))" +|" num_of_MemAtomicOp MemAtomicOp_SWP = ( (( 8 :: int)::ii))" + + +(*val undefined_MemAtomicOp : unit -> M MemAtomicOp*) + +definition undefined_MemAtomicOp :: " unit \((register_value),(MemAtomicOp),(exception))monad " where + " undefined_MemAtomicOp _ = ( + internal_pick + [MemAtomicOp_ADD,MemAtomicOp_BIC,MemAtomicOp_EOR,MemAtomicOp_ORR,MemAtomicOp_SMAX,MemAtomicOp_SMIN,MemAtomicOp_UMAX,MemAtomicOp_UMIN,MemAtomicOp_SWP])" + + +(*val FPType_of_num : integer -> FPType*) + +definition FPType_of_num :: " int \ FPType " where + " FPType_of_num arg0 = ( + (let l__431 = arg0 in + if (((l__431 = (( 0 :: int)::ii)))) then FPType_Nonzero + else if (((l__431 = (( 1 :: int)::ii)))) then FPType_Zero + else if (((l__431 = (( 2 :: int)::ii)))) then FPType_Infinity + else if (((l__431 = (( 3 :: int)::ii)))) then FPType_QNaN + else FPType_SNaN))" + + +(*val num_of_FPType : FPType -> integer*) + +fun num_of_FPType :: " FPType \ int " where + " num_of_FPType FPType_Nonzero = ( (( 0 :: int)::ii))" +|" num_of_FPType FPType_Zero = ( (( 1 :: int)::ii))" +|" num_of_FPType FPType_Infinity = ( (( 2 :: int)::ii))" +|" num_of_FPType FPType_QNaN = ( (( 3 :: int)::ii))" +|" num_of_FPType FPType_SNaN = ( (( 4 :: int)::ii))" + + +(*val undefined_FPType : unit -> M FPType*) + +definition undefined_FPType :: " unit \((register_value),(FPType),(exception))monad " where + " undefined_FPType _ = ( + internal_pick [FPType_Nonzero,FPType_Zero,FPType_Infinity,FPType_QNaN,FPType_SNaN])" + + +(*val FPExc_of_num : integer -> FPExc*) + +definition FPExc_of_num :: " int \ FPExc " where + " FPExc_of_num arg0 = ( + (let l__426 = arg0 in + if (((l__426 = (( 0 :: int)::ii)))) then FPExc_InvalidOp + else if (((l__426 = (( 1 :: int)::ii)))) then FPExc_DivideByZero + else if (((l__426 = (( 2 :: int)::ii)))) then FPExc_Overflow + else if (((l__426 = (( 3 :: int)::ii)))) then FPExc_Underflow + else if (((l__426 = (( 4 :: int)::ii)))) then FPExc_Inexact + else FPExc_InputDenorm))" + + +(*val num_of_FPExc : FPExc -> integer*) + +fun num_of_FPExc :: " FPExc \ int " where + " num_of_FPExc FPExc_InvalidOp = ( (( 0 :: int)::ii))" +|" num_of_FPExc FPExc_DivideByZero = ( (( 1 :: int)::ii))" +|" num_of_FPExc FPExc_Overflow = ( (( 2 :: int)::ii))" +|" num_of_FPExc FPExc_Underflow = ( (( 3 :: int)::ii))" +|" num_of_FPExc FPExc_Inexact = ( (( 4 :: int)::ii))" +|" num_of_FPExc FPExc_InputDenorm = ( (( 5 :: int)::ii))" + + +(*val undefined_FPExc : unit -> M FPExc*) + +definition undefined_FPExc :: " unit \((register_value),(FPExc),(exception))monad " where + " undefined_FPExc _ = ( + internal_pick + [FPExc_InvalidOp,FPExc_DivideByZero,FPExc_Overflow,FPExc_Underflow,FPExc_Inexact,FPExc_InputDenorm])" + + +(*val FPRounding_of_num : integer -> FPRounding*) + +definition FPRounding_of_num :: " int \ FPRounding " where + " FPRounding_of_num arg0 = ( + (let l__421 = arg0 in + if (((l__421 = (( 0 :: int)::ii)))) then FPRounding_TIEEVEN + else if (((l__421 = (( 1 :: int)::ii)))) then FPRounding_POSINF + else if (((l__421 = (( 2 :: int)::ii)))) then FPRounding_NEGINF + else if (((l__421 = (( 3 :: int)::ii)))) then FPRounding_ZERO + else if (((l__421 = (( 4 :: int)::ii)))) then FPRounding_TIEAWAY + else FPRounding_ODD))" + + +(*val num_of_FPRounding : FPRounding -> integer*) + +fun num_of_FPRounding :: " FPRounding \ int " where + " num_of_FPRounding FPRounding_TIEEVEN = ( (( 0 :: int)::ii))" +|" num_of_FPRounding FPRounding_POSINF = ( (( 1 :: int)::ii))" +|" num_of_FPRounding FPRounding_NEGINF = ( (( 2 :: int)::ii))" +|" num_of_FPRounding FPRounding_ZERO = ( (( 3 :: int)::ii))" +|" num_of_FPRounding FPRounding_TIEAWAY = ( (( 4 :: int)::ii))" +|" num_of_FPRounding FPRounding_ODD = ( (( 5 :: int)::ii))" + + +(*val undefined_FPRounding : unit -> M FPRounding*) + +definition undefined_FPRounding :: " unit \((register_value),(FPRounding),(exception))monad " where + " undefined_FPRounding _ = ( + internal_pick + [FPRounding_TIEEVEN,FPRounding_POSINF,FPRounding_NEGINF,FPRounding_ZERO,FPRounding_TIEAWAY,FPRounding_ODD])" + + +(*val SysRegAccess_of_num : integer -> SysRegAccess*) + +definition SysRegAccess_of_num :: " int \ SysRegAccess " where + " SysRegAccess_of_num arg0 = ( + (let l__417 = arg0 in + if (((l__417 = (( 0 :: int)::ii)))) then SysRegAccess_OK + else if (((l__417 = (( 1 :: int)::ii)))) then SysRegAccess_UNDEFINED + else if (((l__417 = (( 2 :: int)::ii)))) then SysRegAccess_TrapToEL1 + else if (((l__417 = (( 3 :: int)::ii)))) then SysRegAccess_TrapToEL2 + else SysRegAccess_TrapToEL3))" + + +(*val num_of_SysRegAccess : SysRegAccess -> integer*) + +fun num_of_SysRegAccess :: " SysRegAccess \ int " where + " num_of_SysRegAccess SysRegAccess_OK = ( (( 0 :: int)::ii))" +|" num_of_SysRegAccess SysRegAccess_UNDEFINED = ( (( 1 :: int)::ii))" +|" num_of_SysRegAccess SysRegAccess_TrapToEL1 = ( (( 2 :: int)::ii))" +|" num_of_SysRegAccess SysRegAccess_TrapToEL2 = ( (( 3 :: int)::ii))" +|" num_of_SysRegAccess SysRegAccess_TrapToEL3 = ( (( 4 :: int)::ii))" + + +(*val undefined_SysRegAccess : unit -> M SysRegAccess*) + +definition undefined_SysRegAccess :: " unit \((register_value),(SysRegAccess),(exception))monad " where + " undefined_SysRegAccess _ = ( + internal_pick + [SysRegAccess_OK,SysRegAccess_UNDEFINED,SysRegAccess_TrapToEL1,SysRegAccess_TrapToEL2,SysRegAccess_TrapToEL3])" + + +(*val SRType_of_num : integer -> SRType*) + +definition SRType_of_num :: " int \ SRType " where + " SRType_of_num arg0 = ( + (let l__413 = arg0 in + if (((l__413 = (( 0 :: int)::ii)))) then SRType_LSL + else if (((l__413 = (( 1 :: int)::ii)))) then SRType_LSR + else if (((l__413 = (( 2 :: int)::ii)))) then SRType_ASR + else if (((l__413 = (( 3 :: int)::ii)))) then SRType_ROR + else SRType_RRX))" + + +(*val num_of_SRType : SRType -> integer*) + +fun num_of_SRType :: " SRType \ int " where + " num_of_SRType SRType_LSL = ( (( 0 :: int)::ii))" +|" num_of_SRType SRType_LSR = ( (( 1 :: int)::ii))" +|" num_of_SRType SRType_ASR = ( (( 2 :: int)::ii))" +|" num_of_SRType SRType_ROR = ( (( 3 :: int)::ii))" +|" num_of_SRType SRType_RRX = ( (( 4 :: int)::ii))" + + +(*val undefined_SRType : unit -> M SRType*) + +definition undefined_SRType :: " unit \((register_value),(SRType),(exception))monad " where + " undefined_SRType _ = ( internal_pick [SRType_LSL,SRType_LSR,SRType_ASR,SRType_ROR,SRType_RRX])" + + +(*val ShiftType_of_num : integer -> ShiftType*) + +definition ShiftType_of_num :: " int \ ShiftType " where + " ShiftType_of_num arg0 = ( + (let l__410 = arg0 in + if (((l__410 = (( 0 :: int)::ii)))) then ShiftType_LSL + else if (((l__410 = (( 1 :: int)::ii)))) then ShiftType_LSR + else if (((l__410 = (( 2 :: int)::ii)))) then ShiftType_ASR + else ShiftType_ROR))" + + +(*val num_of_ShiftType : ShiftType -> integer*) + +fun num_of_ShiftType :: " ShiftType \ int " where + " num_of_ShiftType ShiftType_LSL = ( (( 0 :: int)::ii))" +|" num_of_ShiftType ShiftType_LSR = ( (( 1 :: int)::ii))" +|" num_of_ShiftType ShiftType_ASR = ( (( 2 :: int)::ii))" +|" num_of_ShiftType ShiftType_ROR = ( (( 3 :: int)::ii))" + + +(*val undefined_ShiftType : unit -> M ShiftType*) + +definition undefined_ShiftType :: " unit \((register_value),(ShiftType),(exception))monad " where + " undefined_ShiftType _ = ( internal_pick [ShiftType_LSL,ShiftType_LSR,ShiftType_ASR,ShiftType_ROR])" + + +(*val PrefetchHint_of_num : integer -> PrefetchHint*) + +definition PrefetchHint_of_num :: " int \ PrefetchHint " where + " PrefetchHint_of_num arg0 = ( + (let l__408 = arg0 in + if (((l__408 = (( 0 :: int)::ii)))) then Prefetch_READ + else if (((l__408 = (( 1 :: int)::ii)))) then Prefetch_WRITE + else Prefetch_EXEC))" + + +(*val num_of_PrefetchHint : PrefetchHint -> integer*) + +fun num_of_PrefetchHint :: " PrefetchHint \ int " where + " num_of_PrefetchHint Prefetch_READ = ( (( 0 :: int)::ii))" +|" num_of_PrefetchHint Prefetch_WRITE = ( (( 1 :: int)::ii))" +|" num_of_PrefetchHint Prefetch_EXEC = ( (( 2 :: int)::ii))" + + +(*val undefined_PrefetchHint : unit -> M PrefetchHint*) + +definition undefined_PrefetchHint :: " unit \((register_value),(PrefetchHint),(exception))monad " where + " undefined_PrefetchHint _ = ( internal_pick [Prefetch_READ,Prefetch_WRITE,Prefetch_EXEC])" + + +(*val InterruptID_of_num : integer -> InterruptID*) + +definition InterruptID_of_num :: " int \ InterruptID " where + " InterruptID_of_num arg0 = ( + (let l__404 = arg0 in + if (((l__404 = (( 0 :: int)::ii)))) then InterruptID_PMUIRQ + else if (((l__404 = (( 1 :: int)::ii)))) then InterruptID_COMMIRQ + else if (((l__404 = (( 2 :: int)::ii)))) then InterruptID_CTIIRQ + else if (((l__404 = (( 3 :: int)::ii)))) then InterruptID_COMMRX + else InterruptID_COMMTX))" + + +(*val num_of_InterruptID : InterruptID -> integer*) + +fun num_of_InterruptID :: " InterruptID \ int " where + " num_of_InterruptID InterruptID_PMUIRQ = ( (( 0 :: int)::ii))" +|" num_of_InterruptID InterruptID_COMMIRQ = ( (( 1 :: int)::ii))" +|" num_of_InterruptID InterruptID_CTIIRQ = ( (( 2 :: int)::ii))" +|" num_of_InterruptID InterruptID_COMMRX = ( (( 3 :: int)::ii))" +|" num_of_InterruptID InterruptID_COMMTX = ( (( 4 :: int)::ii))" + + +(*val undefined_InterruptID : unit -> M InterruptID*) + +definition undefined_InterruptID :: " unit \((register_value),(InterruptID),(exception))monad " where + " undefined_InterruptID _ = ( + internal_pick + [InterruptID_PMUIRQ,InterruptID_COMMIRQ,InterruptID_CTIIRQ,InterruptID_COMMRX,InterruptID_COMMTX])" + + +(*val CrossTriggerOut_of_num : integer -> CrossTriggerOut*) + +definition CrossTriggerOut_of_num :: " int \ CrossTriggerOut " where + " CrossTriggerOut_of_num arg0 = ( + (let l__397 = arg0 in + if (((l__397 = (( 0 :: int)::ii)))) then CrossTriggerOut_DebugRequest + else if (((l__397 = (( 1 :: int)::ii)))) then CrossTriggerOut_RestartRequest + else if (((l__397 = (( 2 :: int)::ii)))) then CrossTriggerOut_IRQ + else if (((l__397 = (( 3 :: int)::ii)))) then CrossTriggerOut_RSVD3 + else if (((l__397 = (( 4 :: int)::ii)))) then CrossTriggerOut_TraceExtIn0 + else if (((l__397 = (( 5 :: int)::ii)))) then CrossTriggerOut_TraceExtIn1 + else if (((l__397 = (( 6 :: int)::ii)))) then CrossTriggerOut_TraceExtIn2 + else CrossTriggerOut_TraceExtIn3))" + + +(*val num_of_CrossTriggerOut : CrossTriggerOut -> integer*) + +fun num_of_CrossTriggerOut :: " CrossTriggerOut \ int " where + " num_of_CrossTriggerOut CrossTriggerOut_DebugRequest = ( (( 0 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_RestartRequest = ( (( 1 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_IRQ = ( (( 2 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_RSVD3 = ( (( 3 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_TraceExtIn0 = ( (( 4 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_TraceExtIn1 = ( (( 5 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_TraceExtIn2 = ( (( 6 :: int)::ii))" +|" num_of_CrossTriggerOut CrossTriggerOut_TraceExtIn3 = ( (( 7 :: int)::ii))" + + +(*val undefined_CrossTriggerOut : unit -> M CrossTriggerOut*) + +definition undefined_CrossTriggerOut :: " unit \((register_value),(CrossTriggerOut),(exception))monad " where + " undefined_CrossTriggerOut _ = ( + internal_pick + [CrossTriggerOut_DebugRequest,CrossTriggerOut_RestartRequest,CrossTriggerOut_IRQ,CrossTriggerOut_RSVD3,CrossTriggerOut_TraceExtIn0,CrossTriggerOut_TraceExtIn1,CrossTriggerOut_TraceExtIn2,CrossTriggerOut_TraceExtIn3])" + + +(*val CrossTriggerIn_of_num : integer -> CrossTriggerIn*) + +definition CrossTriggerIn_of_num :: " int \ CrossTriggerIn " where + " CrossTriggerIn_of_num arg0 = ( + (let l__390 = arg0 in + if (((l__390 = (( 0 :: int)::ii)))) then CrossTriggerIn_CrossHalt + else if (((l__390 = (( 1 :: int)::ii)))) then CrossTriggerIn_PMUOverflow + else if (((l__390 = (( 2 :: int)::ii)))) then CrossTriggerIn_RSVD2 + else if (((l__390 = (( 3 :: int)::ii)))) then CrossTriggerIn_RSVD3 + else if (((l__390 = (( 4 :: int)::ii)))) then CrossTriggerIn_TraceExtOut0 + else if (((l__390 = (( 5 :: int)::ii)))) then CrossTriggerIn_TraceExtOut1 + else if (((l__390 = (( 6 :: int)::ii)))) then CrossTriggerIn_TraceExtOut2 + else CrossTriggerIn_TraceExtOut3))" + + +(*val num_of_CrossTriggerIn : CrossTriggerIn -> integer*) + +fun num_of_CrossTriggerIn :: " CrossTriggerIn \ int " where + " num_of_CrossTriggerIn CrossTriggerIn_CrossHalt = ( (( 0 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_PMUOverflow = ( (( 1 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_RSVD2 = ( (( 2 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_RSVD3 = ( (( 3 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_TraceExtOut0 = ( (( 4 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_TraceExtOut1 = ( (( 5 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_TraceExtOut2 = ( (( 6 :: int)::ii))" +|" num_of_CrossTriggerIn CrossTriggerIn_TraceExtOut3 = ( (( 7 :: int)::ii))" + + +(*val undefined_CrossTriggerIn : unit -> M CrossTriggerIn*) + +definition undefined_CrossTriggerIn :: " unit \((register_value),(CrossTriggerIn),(exception))monad " where + " undefined_CrossTriggerIn _ = ( + internal_pick + [CrossTriggerIn_CrossHalt,CrossTriggerIn_PMUOverflow,CrossTriggerIn_RSVD2,CrossTriggerIn_RSVD3,CrossTriggerIn_TraceExtOut0,CrossTriggerIn_TraceExtOut1,CrossTriggerIn_TraceExtOut2,CrossTriggerIn_TraceExtOut3])" + + +(*val MemBarrierOp_of_num : integer -> MemBarrierOp*) + +definition MemBarrierOp_of_num :: " int \ MemBarrierOp " where + " MemBarrierOp_of_num arg0 = ( + (let l__388 = arg0 in + if (((l__388 = (( 0 :: int)::ii)))) then MemBarrierOp_DSB + else if (((l__388 = (( 1 :: int)::ii)))) then MemBarrierOp_DMB + else MemBarrierOp_ISB))" + + +(*val num_of_MemBarrierOp : MemBarrierOp -> integer*) + +fun num_of_MemBarrierOp :: " MemBarrierOp \ int " where + " num_of_MemBarrierOp MemBarrierOp_DSB = ( (( 0 :: int)::ii))" +|" num_of_MemBarrierOp MemBarrierOp_DMB = ( (( 1 :: int)::ii))" +|" num_of_MemBarrierOp MemBarrierOp_ISB = ( (( 2 :: int)::ii))" + + +(*val undefined_MemBarrierOp : unit -> M MemBarrierOp*) + +definition undefined_MemBarrierOp :: " unit \((register_value),(MemBarrierOp),(exception))monad " where + " undefined_MemBarrierOp _ = ( internal_pick [MemBarrierOp_DSB,MemBarrierOp_DMB,MemBarrierOp_ISB])" + + +(*val undefined_AccessDescriptor : unit -> M AccessDescriptor*) + +definition undefined_AccessDescriptor :: " unit \((register_value),(AccessDescriptor),(exception))monad " where + " undefined_AccessDescriptor _ = ( + undefined_AccType () \ (\ (w__0 :: AccType) . + undefined_bool () \ (\ (w__1 :: bool) . + undefined_bool () \ (\ (w__2 :: bool) . + undefined_bool () \ (\ (w__3 :: bool) . + undefined_int () \ (\ (w__4 :: ii) . + return ((| AccessDescriptor_acctype = w__0, + AccessDescriptor_page_table_walk = w__1, + AccessDescriptor_secondstage = w__2, + AccessDescriptor_s2fs1walk = w__3, + AccessDescriptor_level = w__4 |))))))))" + + +(*val undefined_Permissions : unit -> M Permissions*) + +definition undefined_Permissions :: " unit \((register_value),(Permissions),(exception))monad " where + " undefined_Permissions _ = ( + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (w__0 :: 3 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__2 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__3 :: 1 bits) . + return ((| Permissions_ap = w__0, + Permissions_xn = w__1, + Permissions_xxn = w__2, + Permissions_pxn = w__3 |)))))))" + + +(*val undefined_TLBRecord : unit -> M TLBRecord*) + +definition undefined_TLBRecord :: " unit \((register_value),(TLBRecord),(exception))monad " where + " undefined_TLBRecord _ = ( + undefined_Permissions () \ (\ (w__0 :: Permissions) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__2 :: 4 bits) . + undefined_bool () \ (\ (w__3 :: bool) . + undefined_int () \ (\ (w__4 :: ii) . + undefined_int () \ (\ (w__5 :: ii) . + undefined_DescriptorUpdate () \ (\ (w__6 :: DescriptorUpdate) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__7 :: 1 bits) . + undefined_AddressDescriptor () \ (\ (w__8 :: AddressDescriptor) . + return ((| TLBRecord_perms = w__0, + TLBRecord_nG = w__1, + TLBRecord_domain = w__2, + TLBRecord_contiguous = w__3, + TLBRecord_level = w__4, + TLBRecord_blocksize = w__5, + TLBRecord_descupdate = w__6, + TLBRecord_CnP = w__7, + TLBRecord_addrdesc = w__8 |))))))))))))" + + +(*val ImmediateOp_of_num : integer -> ImmediateOp*) + +definition ImmediateOp_of_num :: " int \ ImmediateOp " where + " ImmediateOp_of_num arg0 = ( + (let l__385 = arg0 in + if (((l__385 = (( 0 :: int)::ii)))) then ImmediateOp_MOVI + else if (((l__385 = (( 1 :: int)::ii)))) then ImmediateOp_MVNI + else if (((l__385 = (( 2 :: int)::ii)))) then ImmediateOp_ORR + else ImmediateOp_BIC))" + + +(*val num_of_ImmediateOp : ImmediateOp -> integer*) + +fun num_of_ImmediateOp :: " ImmediateOp \ int " where + " num_of_ImmediateOp ImmediateOp_MOVI = ( (( 0 :: int)::ii))" +|" num_of_ImmediateOp ImmediateOp_MVNI = ( (( 1 :: int)::ii))" +|" num_of_ImmediateOp ImmediateOp_ORR = ( (( 2 :: int)::ii))" +|" num_of_ImmediateOp ImmediateOp_BIC = ( (( 3 :: int)::ii))" + + +(*val undefined_ImmediateOp : unit -> M ImmediateOp*) + +definition undefined_ImmediateOp :: " unit \((register_value),(ImmediateOp),(exception))monad " where + " undefined_ImmediateOp _ = ( + internal_pick [ImmediateOp_MOVI,ImmediateOp_MVNI,ImmediateOp_ORR,ImmediateOp_BIC])" + + +(*val MoveWideOp_of_num : integer -> MoveWideOp*) + +definition MoveWideOp_of_num :: " int \ MoveWideOp " where + " MoveWideOp_of_num arg0 = ( + (let l__383 = arg0 in + if (((l__383 = (( 0 :: int)::ii)))) then MoveWideOp_N + else if (((l__383 = (( 1 :: int)::ii)))) then MoveWideOp_Z + else MoveWideOp_K))" + + +(*val num_of_MoveWideOp : MoveWideOp -> integer*) + +fun num_of_MoveWideOp :: " MoveWideOp \ int " where + " num_of_MoveWideOp MoveWideOp_N = ( (( 0 :: int)::ii))" +|" num_of_MoveWideOp MoveWideOp_Z = ( (( 1 :: int)::ii))" +|" num_of_MoveWideOp MoveWideOp_K = ( (( 2 :: int)::ii))" + + +(*val undefined_MoveWideOp : unit -> M MoveWideOp*) + +definition undefined_MoveWideOp :: " unit \((register_value),(MoveWideOp),(exception))monad " where + " undefined_MoveWideOp _ = ( internal_pick [MoveWideOp_N,MoveWideOp_Z,MoveWideOp_K])" + + +(*val SystemAccessType_of_num : integer -> SystemAccessType*) + +definition SystemAccessType_of_num :: " int \ SystemAccessType " where + " SystemAccessType_of_num arg0 = ( + (let l__381 = arg0 in + if (((l__381 = (( 0 :: int)::ii)))) then SystemAccessType_RT + else if (((l__381 = (( 1 :: int)::ii)))) then SystemAccessType_RRT + else SystemAccessType_DT))" + + +(*val num_of_SystemAccessType : SystemAccessType -> integer*) + +fun num_of_SystemAccessType :: " SystemAccessType \ int " where + " num_of_SystemAccessType SystemAccessType_RT = ( (( 0 :: int)::ii))" +|" num_of_SystemAccessType SystemAccessType_RRT = ( (( 1 :: int)::ii))" +|" num_of_SystemAccessType SystemAccessType_DT = ( (( 2 :: int)::ii))" + + +(*val undefined_SystemAccessType : unit -> M SystemAccessType*) + +definition undefined_SystemAccessType :: " unit \((register_value),(SystemAccessType),(exception))monad " where + " undefined_SystemAccessType _ = ( + internal_pick [SystemAccessType_RT,SystemAccessType_RRT,SystemAccessType_DT])" + + +(*val VBitOp_of_num : integer -> VBitOp*) + +definition VBitOp_of_num :: " int \ VBitOp " where + " VBitOp_of_num arg0 = ( + (let l__378 = arg0 in + if (((l__378 = (( 0 :: int)::ii)))) then VBitOp_VBIF + else if (((l__378 = (( 1 :: int)::ii)))) then VBitOp_VBIT + else if (((l__378 = (( 2 :: int)::ii)))) then VBitOp_VBSL + else VBitOp_VEOR))" + + +(*val num_of_VBitOp : VBitOp -> integer*) + +fun num_of_VBitOp :: " VBitOp \ int " where + " num_of_VBitOp VBitOp_VBIF = ( (( 0 :: int)::ii))" +|" num_of_VBitOp VBitOp_VBIT = ( (( 1 :: int)::ii))" +|" num_of_VBitOp VBitOp_VBSL = ( (( 2 :: int)::ii))" +|" num_of_VBitOp VBitOp_VEOR = ( (( 3 :: int)::ii))" + + +(*val undefined_VBitOp : unit -> M VBitOp*) + +definition undefined_VBitOp :: " unit \((register_value),(VBitOp),(exception))monad " where + " undefined_VBitOp _ = ( internal_pick [VBitOp_VBIF,VBitOp_VBIT,VBitOp_VBSL,VBitOp_VEOR])" + + +(*val TimeStamp_of_num : integer -> TimeStamp*) + +definition TimeStamp_of_num :: " int \ TimeStamp " where + " TimeStamp_of_num arg0 = ( + (let l__376 = arg0 in + if (((l__376 = (( 0 :: int)::ii)))) then TimeStamp_None + else if (((l__376 = (( 1 :: int)::ii)))) then TimeStamp_Virtual + else TimeStamp_Physical))" + + +(*val num_of_TimeStamp : TimeStamp -> integer*) + +fun num_of_TimeStamp :: " TimeStamp \ int " where + " num_of_TimeStamp TimeStamp_None = ( (( 0 :: int)::ii))" +|" num_of_TimeStamp TimeStamp_Virtual = ( (( 1 :: int)::ii))" +|" num_of_TimeStamp TimeStamp_Physical = ( (( 2 :: int)::ii))" + + +(*val undefined_TimeStamp : unit -> M TimeStamp*) + +definition undefined_TimeStamp :: " unit \((register_value),(TimeStamp),(exception))monad " where + " undefined_TimeStamp _ = ( internal_pick [TimeStamp_None,TimeStamp_Virtual,TimeStamp_Physical])" + + +(*val PrivilegeLevel_of_num : integer -> PrivilegeLevel*) + +definition PrivilegeLevel_of_num :: " int \ PrivilegeLevel " where + " PrivilegeLevel_of_num arg0 = ( + (let l__373 = arg0 in + if (((l__373 = (( 0 :: int)::ii)))) then PL3 + else if (((l__373 = (( 1 :: int)::ii)))) then PL2 + else if (((l__373 = (( 2 :: int)::ii)))) then PL1 + else PL0))" + + +(*val num_of_PrivilegeLevel : PrivilegeLevel -> integer*) + +fun num_of_PrivilegeLevel :: " PrivilegeLevel \ int " where + " num_of_PrivilegeLevel PL3 = ( (( 0 :: int)::ii))" +|" num_of_PrivilegeLevel PL2 = ( (( 1 :: int)::ii))" +|" num_of_PrivilegeLevel PL1 = ( (( 2 :: int)::ii))" +|" num_of_PrivilegeLevel PL0 = ( (( 3 :: int)::ii))" + + +(*val undefined_PrivilegeLevel : unit -> M PrivilegeLevel*) + +definition undefined_PrivilegeLevel :: " unit \((register_value),(PrivilegeLevel),(exception))monad " where + " undefined_PrivilegeLevel _ = ( internal_pick [PL3,PL2,PL1,PL0])" + + +(*val undefined_AArch32_SErrorSyndrome : unit -> M AArch32_SErrorSyndrome*) + +definition undefined_AArch32_SErrorSyndrome :: " unit \((register_value),(AArch32_SErrorSyndrome),(exception))monad " where + " undefined_AArch32_SErrorSyndrome _ = ( + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__0 :: 2 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + return ((| AArch32_SErrorSyndrome_AET = w__0, + AArch32_SErrorSyndrome_ExT = w__1 |)))))" + + +(*val SystemOp_of_num : integer -> SystemOp*) + +definition SystemOp_of_num :: " int \ SystemOp " where + " SystemOp_of_num arg0 = ( + (let l__369 = arg0 in + if (((l__369 = (( 0 :: int)::ii)))) then Sys_AT + else if (((l__369 = (( 1 :: int)::ii)))) then Sys_DC + else if (((l__369 = (( 2 :: int)::ii)))) then Sys_IC + else if (((l__369 = (( 3 :: int)::ii)))) then Sys_TLBI + else Sys_SYS))" + + +(*val num_of_SystemOp : SystemOp -> integer*) + +fun num_of_SystemOp :: " SystemOp \ int " where + " num_of_SystemOp Sys_AT = ( (( 0 :: int)::ii))" +|" num_of_SystemOp Sys_DC = ( (( 1 :: int)::ii))" +|" num_of_SystemOp Sys_IC = ( (( 2 :: int)::ii))" +|" num_of_SystemOp Sys_TLBI = ( (( 3 :: int)::ii))" +|" num_of_SystemOp Sys_SYS = ( (( 4 :: int)::ii))" + + +(*val undefined_SystemOp : unit -> M SystemOp*) + +definition undefined_SystemOp :: " unit \((register_value),(SystemOp),(exception))monad " where + " undefined_SystemOp _ = ( internal_pick [Sys_AT,Sys_DC,Sys_IC,Sys_TLBI,Sys_SYS])" + + +(*val undefined_PCSample : unit -> M PCSample*) + +definition undefined_PCSample :: " unit \((register_value),(PCSample),(exception))monad " where + " undefined_PCSample _ = ( + undefined_bool () \ (\ (w__0 :: bool) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__2 :: 2 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__3 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__4 :: 1 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__5 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (w__7 :: 16 bits) . + return ((| PCSample_valid_name = w__0, + PCSample_pc = w__1, + PCSample_el = w__2, + PCSample_rw = w__3, + PCSample_ns = w__4, + PCSample_contextidr = w__5, + PCSample_contextidr_el2 = w__6, + PCSample_vmid = w__7 |)))))))))))" + + +(*val ReduceOp_of_num : integer -> ReduceOp*) + +definition ReduceOp_of_num :: " int \ ReduceOp " where + " ReduceOp_of_num arg0 = ( + (let l__364 = arg0 in + if (((l__364 = (( 0 :: int)::ii)))) then ReduceOp_FMINNUM + else if (((l__364 = (( 1 :: int)::ii)))) then ReduceOp_FMAXNUM + else if (((l__364 = (( 2 :: int)::ii)))) then ReduceOp_FMIN + else if (((l__364 = (( 3 :: int)::ii)))) then ReduceOp_FMAX + else if (((l__364 = (( 4 :: int)::ii)))) then ReduceOp_FADD + else ReduceOp_ADD))" + + +(*val num_of_ReduceOp : ReduceOp -> integer*) + +fun num_of_ReduceOp :: " ReduceOp \ int " where + " num_of_ReduceOp ReduceOp_FMINNUM = ( (( 0 :: int)::ii))" +|" num_of_ReduceOp ReduceOp_FMAXNUM = ( (( 1 :: int)::ii))" +|" num_of_ReduceOp ReduceOp_FMIN = ( (( 2 :: int)::ii))" +|" num_of_ReduceOp ReduceOp_FMAX = ( (( 3 :: int)::ii))" +|" num_of_ReduceOp ReduceOp_FADD = ( (( 4 :: int)::ii))" +|" num_of_ReduceOp ReduceOp_ADD = ( (( 5 :: int)::ii))" + + +(*val undefined_ReduceOp : unit -> M ReduceOp*) + +definition undefined_ReduceOp :: " unit \((register_value),(ReduceOp),(exception))monad " where + " undefined_ReduceOp _ = ( + internal_pick + [ReduceOp_FMINNUM,ReduceOp_FMAXNUM,ReduceOp_FMIN,ReduceOp_FMAX,ReduceOp_FADD,ReduceOp_ADD])" + + +(*val LogicalOp_of_num : integer -> LogicalOp*) + +definition LogicalOp_of_num :: " int \ LogicalOp " where + " LogicalOp_of_num arg0 = ( + (let l__362 = arg0 in + if (((l__362 = (( 0 :: int)::ii)))) then LogicalOp_AND + else if (((l__362 = (( 1 :: int)::ii)))) then LogicalOp_EOR + else LogicalOp_ORR))" + + +(*val num_of_LogicalOp : LogicalOp -> integer*) + +fun num_of_LogicalOp :: " LogicalOp \ int " where + " num_of_LogicalOp LogicalOp_AND = ( (( 0 :: int)::ii))" +|" num_of_LogicalOp LogicalOp_EOR = ( (( 1 :: int)::ii))" +|" num_of_LogicalOp LogicalOp_ORR = ( (( 2 :: int)::ii))" + + +(*val undefined_LogicalOp : unit -> M LogicalOp*) + +definition undefined_LogicalOp :: " unit \((register_value),(LogicalOp),(exception))monad " where + " undefined_LogicalOp _ = ( internal_pick [LogicalOp_AND,LogicalOp_EOR,LogicalOp_ORR])" + + +(*val ExtendType_of_num : integer -> ExtendType*) + +definition ExtendType_of_num :: " int \ ExtendType " where + " ExtendType_of_num arg0 = ( + (let l__355 = arg0 in + if (((l__355 = (( 0 :: int)::ii)))) then ExtendType_SXTB + else if (((l__355 = (( 1 :: int)::ii)))) then ExtendType_SXTH + else if (((l__355 = (( 2 :: int)::ii)))) then ExtendType_SXTW + else if (((l__355 = (( 3 :: int)::ii)))) then ExtendType_SXTX + else if (((l__355 = (( 4 :: int)::ii)))) then ExtendType_UXTB + else if (((l__355 = (( 5 :: int)::ii)))) then ExtendType_UXTH + else if (((l__355 = (( 6 :: int)::ii)))) then ExtendType_UXTW + else ExtendType_UXTX))" + + +(*val num_of_ExtendType : ExtendType -> integer*) + +fun num_of_ExtendType :: " ExtendType \ int " where + " num_of_ExtendType ExtendType_SXTB = ( (( 0 :: int)::ii))" +|" num_of_ExtendType ExtendType_SXTH = ( (( 1 :: int)::ii))" +|" num_of_ExtendType ExtendType_SXTW = ( (( 2 :: int)::ii))" +|" num_of_ExtendType ExtendType_SXTX = ( (( 3 :: int)::ii))" +|" num_of_ExtendType ExtendType_UXTB = ( (( 4 :: int)::ii))" +|" num_of_ExtendType ExtendType_UXTH = ( (( 5 :: int)::ii))" +|" num_of_ExtendType ExtendType_UXTW = ( (( 6 :: int)::ii))" +|" num_of_ExtendType ExtendType_UXTX = ( (( 7 :: int)::ii))" + + +(*val undefined_ExtendType : unit -> M ExtendType*) + +definition undefined_ExtendType :: " unit \((register_value),(ExtendType),(exception))monad " where + " undefined_ExtendType _ = ( + internal_pick + [ExtendType_SXTB,ExtendType_SXTH,ExtendType_SXTW,ExtendType_SXTX,ExtendType_UXTB,ExtendType_UXTH,ExtendType_UXTW,ExtendType_UXTX])" + + +(*val SystemHintOp_of_num : integer -> SystemHintOp*) + +definition SystemHintOp_of_num :: " int \ SystemHintOp " where + " SystemHintOp_of_num arg0 = ( + (let l__348 = arg0 in + if (((l__348 = (( 0 :: int)::ii)))) then SystemHintOp_NOP + else if (((l__348 = (( 1 :: int)::ii)))) then SystemHintOp_YIELD + else if (((l__348 = (( 2 :: int)::ii)))) then SystemHintOp_WFE + else if (((l__348 = (( 3 :: int)::ii)))) then SystemHintOp_WFI + else if (((l__348 = (( 4 :: int)::ii)))) then SystemHintOp_SEV + else if (((l__348 = (( 5 :: int)::ii)))) then SystemHintOp_SEVL + else if (((l__348 = (( 6 :: int)::ii)))) then SystemHintOp_ESB + else SystemHintOp_PSB))" + + +(*val num_of_SystemHintOp : SystemHintOp -> integer*) + +fun num_of_SystemHintOp :: " SystemHintOp \ int " where + " num_of_SystemHintOp SystemHintOp_NOP = ( (( 0 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_YIELD = ( (( 1 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_WFE = ( (( 2 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_WFI = ( (( 3 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_SEV = ( (( 4 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_SEVL = ( (( 5 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_ESB = ( (( 6 :: int)::ii))" +|" num_of_SystemHintOp SystemHintOp_PSB = ( (( 7 :: int)::ii))" + + +(*val undefined_SystemHintOp : unit -> M SystemHintOp*) + +definition undefined_SystemHintOp :: " unit \((register_value),(SystemHintOp),(exception))monad " where + " undefined_SystemHintOp _ = ( + internal_pick + [SystemHintOp_NOP,SystemHintOp_YIELD,SystemHintOp_WFE,SystemHintOp_WFI,SystemHintOp_SEV,SystemHintOp_SEVL,SystemHintOp_ESB,SystemHintOp_PSB])" + + +(*val MemOp_of_num : integer -> MemOp*) + +definition MemOp_of_num :: " int \ MemOp " where + " MemOp_of_num arg0 = ( + (let l__346 = arg0 in + if (((l__346 = (( 0 :: int)::ii)))) then MemOp_LOAD + else if (((l__346 = (( 1 :: int)::ii)))) then MemOp_STORE + else MemOp_PREFETCH))" + + +(*val num_of_MemOp : MemOp -> integer*) + +fun num_of_MemOp :: " MemOp \ int " where + " num_of_MemOp MemOp_LOAD = ( (( 0 :: int)::ii))" +|" num_of_MemOp MemOp_STORE = ( (( 1 :: int)::ii))" +|" num_of_MemOp MemOp_PREFETCH = ( (( 2 :: int)::ii))" + + +(*val undefined_MemOp : unit -> M MemOp*) + +definition undefined_MemOp :: " unit \((register_value),(MemOp),(exception))monad " where + " undefined_MemOp _ = ( internal_pick [MemOp_LOAD,MemOp_STORE,MemOp_PREFETCH])" + + +(*val OpType_of_num : integer -> OpType*) + +definition OpType_of_num :: " int \ OpType " where + " OpType_of_num arg0 = ( + (let l__342 = arg0 in + if (((l__342 = (( 0 :: int)::ii)))) then OpType_Load + else if (((l__342 = (( 1 :: int)::ii)))) then OpType_Store + else if (((l__342 = (( 2 :: int)::ii)))) then OpType_LoadAtomic + else if (((l__342 = (( 3 :: int)::ii)))) then OpType_Branch + else OpType_Other))" + + +(*val num_of_OpType : OpType -> integer*) + +fun num_of_OpType :: " OpType \ int " where + " num_of_OpType OpType_Load = ( (( 0 :: int)::ii))" +|" num_of_OpType OpType_Store = ( (( 1 :: int)::ii))" +|" num_of_OpType OpType_LoadAtomic = ( (( 2 :: int)::ii))" +|" num_of_OpType OpType_Branch = ( (( 3 :: int)::ii))" +|" num_of_OpType OpType_Other = ( (( 4 :: int)::ii))" + + +(*val undefined_OpType : unit -> M OpType*) + +definition undefined_OpType :: " unit \((register_value),(OpType),(exception))monad " where + " undefined_OpType _ = ( + internal_pick [OpType_Load,OpType_Store,OpType_LoadAtomic,OpType_Branch,OpType_Other])" + + +(*val FPUnaryOp_of_num : integer -> FPUnaryOp*) + +definition FPUnaryOp_of_num :: " int \ FPUnaryOp " where + " FPUnaryOp_of_num arg0 = ( + (let l__339 = arg0 in + if (((l__339 = (( 0 :: int)::ii)))) then FPUnaryOp_ABS + else if (((l__339 = (( 1 :: int)::ii)))) then FPUnaryOp_MOV + else if (((l__339 = (( 2 :: int)::ii)))) then FPUnaryOp_NEG + else FPUnaryOp_SQRT))" + + +(*val num_of_FPUnaryOp : FPUnaryOp -> integer*) + +fun num_of_FPUnaryOp :: " FPUnaryOp \ int " where + " num_of_FPUnaryOp FPUnaryOp_ABS = ( (( 0 :: int)::ii))" +|" num_of_FPUnaryOp FPUnaryOp_MOV = ( (( 1 :: int)::ii))" +|" num_of_FPUnaryOp FPUnaryOp_NEG = ( (( 2 :: int)::ii))" +|" num_of_FPUnaryOp FPUnaryOp_SQRT = ( (( 3 :: int)::ii))" + + +(*val undefined_FPUnaryOp : unit -> M FPUnaryOp*) + +definition undefined_FPUnaryOp :: " unit \((register_value),(FPUnaryOp),(exception))monad " where + " undefined_FPUnaryOp _ = ( + internal_pick [FPUnaryOp_ABS,FPUnaryOp_MOV,FPUnaryOp_NEG,FPUnaryOp_SQRT])" + + +(*val CompareOp_of_num : integer -> CompareOp*) + +definition CompareOp_of_num :: " int \ CompareOp " where + " CompareOp_of_num arg0 = ( + (let l__335 = arg0 in + if (((l__335 = (( 0 :: int)::ii)))) then CompareOp_GT + else if (((l__335 = (( 1 :: int)::ii)))) then CompareOp_GE + else if (((l__335 = (( 2 :: int)::ii)))) then CompareOp_EQ + else if (((l__335 = (( 3 :: int)::ii)))) then CompareOp_LE + else CompareOp_LT))" + + +(*val num_of_CompareOp : CompareOp -> integer*) + +fun num_of_CompareOp :: " CompareOp \ int " where + " num_of_CompareOp CompareOp_GT = ( (( 0 :: int)::ii))" +|" num_of_CompareOp CompareOp_GE = ( (( 1 :: int)::ii))" +|" num_of_CompareOp CompareOp_EQ = ( (( 2 :: int)::ii))" +|" num_of_CompareOp CompareOp_LE = ( (( 3 :: int)::ii))" +|" num_of_CompareOp CompareOp_LT = ( (( 4 :: int)::ii))" + + +(*val undefined_CompareOp : unit -> M CompareOp*) + +definition undefined_CompareOp :: " unit \((register_value),(CompareOp),(exception))monad " where + " undefined_CompareOp _ = ( + internal_pick [CompareOp_GT,CompareOp_GE,CompareOp_EQ,CompareOp_LE,CompareOp_LT])" + + +(*val PSTATEField_of_num : integer -> PSTATEField*) + +definition PSTATEField_of_num :: " int \ PSTATEField " where + " PSTATEField_of_num arg0 = ( + (let l__331 = arg0 in + if (((l__331 = (( 0 :: int)::ii)))) then PSTATEField_DAIFSet + else if (((l__331 = (( 1 :: int)::ii)))) then PSTATEField_DAIFClr + else if (((l__331 = (( 2 :: int)::ii)))) then PSTATEField_PAN + else if (((l__331 = (( 3 :: int)::ii)))) then PSTATEField_UAO + else PSTATEField_SP))" + + +(*val num_of_PSTATEField : PSTATEField -> integer*) + +fun num_of_PSTATEField :: " PSTATEField \ int " where + " num_of_PSTATEField PSTATEField_DAIFSet = ( (( 0 :: int)::ii))" +|" num_of_PSTATEField PSTATEField_DAIFClr = ( (( 1 :: int)::ii))" +|" num_of_PSTATEField PSTATEField_PAN = ( (( 2 :: int)::ii))" +|" num_of_PSTATEField PSTATEField_UAO = ( (( 3 :: int)::ii))" +|" num_of_PSTATEField PSTATEField_SP = ( (( 4 :: int)::ii))" + + +(*val undefined_PSTATEField : unit -> M PSTATEField*) + +definition undefined_PSTATEField :: " unit \((register_value),(PSTATEField),(exception))monad " where + " undefined_PSTATEField _ = ( + internal_pick + [PSTATEField_DAIFSet,PSTATEField_DAIFClr,PSTATEField_PAN,PSTATEField_UAO,PSTATEField_SP])" + + +(*val FPMaxMinOp_of_num : integer -> FPMaxMinOp*) + +definition FPMaxMinOp_of_num :: " int \ FPMaxMinOp " where + " FPMaxMinOp_of_num arg0 = ( + (let l__328 = arg0 in + if (((l__328 = (( 0 :: int)::ii)))) then FPMaxMinOp_MAX + else if (((l__328 = (( 1 :: int)::ii)))) then FPMaxMinOp_MIN + else if (((l__328 = (( 2 :: int)::ii)))) then FPMaxMinOp_MAXNUM + else FPMaxMinOp_MINNUM))" + + +(*val num_of_FPMaxMinOp : FPMaxMinOp -> integer*) + +fun num_of_FPMaxMinOp :: " FPMaxMinOp \ int " where + " num_of_FPMaxMinOp FPMaxMinOp_MAX = ( (( 0 :: int)::ii))" +|" num_of_FPMaxMinOp FPMaxMinOp_MIN = ( (( 1 :: int)::ii))" +|" num_of_FPMaxMinOp FPMaxMinOp_MAXNUM = ( (( 2 :: int)::ii))" +|" num_of_FPMaxMinOp FPMaxMinOp_MINNUM = ( (( 3 :: int)::ii))" + + +(*val undefined_FPMaxMinOp : unit -> M FPMaxMinOp*) + +definition undefined_FPMaxMinOp :: " unit \((register_value),(FPMaxMinOp),(exception))monad " where + " undefined_FPMaxMinOp _ = ( + internal_pick [FPMaxMinOp_MAX,FPMaxMinOp_MIN,FPMaxMinOp_MAXNUM,FPMaxMinOp_MINNUM])" + + +(*val CountOp_of_num : integer -> CountOp*) + +definition CountOp_of_num :: " int \ CountOp " where + " CountOp_of_num arg0 = ( + (let l__326 = arg0 in + if (((l__326 = (( 0 :: int)::ii)))) then CountOp_CLZ + else if (((l__326 = (( 1 :: int)::ii)))) then CountOp_CLS + else CountOp_CNT))" + + +(*val num_of_CountOp : CountOp -> integer*) + +fun num_of_CountOp :: " CountOp \ int " where + " num_of_CountOp CountOp_CLZ = ( (( 0 :: int)::ii))" +|" num_of_CountOp CountOp_CLS = ( (( 1 :: int)::ii))" +|" num_of_CountOp CountOp_CNT = ( (( 2 :: int)::ii))" + + +(*val undefined_CountOp : unit -> M CountOp*) + +definition undefined_CountOp :: " unit \((register_value),(CountOp),(exception))monad " where + " undefined_CountOp _ = ( internal_pick [CountOp_CLZ,CountOp_CLS,CountOp_CNT])" + + +(*val VFPNegMul_of_num : integer -> VFPNegMul*) + +definition VFPNegMul_of_num :: " int \ VFPNegMul " where + " VFPNegMul_of_num arg0 = ( + (let l__324 = arg0 in + if (((l__324 = (( 0 :: int)::ii)))) then VFPNegMul_VNMLA + else if (((l__324 = (( 1 :: int)::ii)))) then VFPNegMul_VNMLS + else VFPNegMul_VNMUL))" + + +(*val num_of_VFPNegMul : VFPNegMul -> integer*) + +fun num_of_VFPNegMul :: " VFPNegMul \ int " where + " num_of_VFPNegMul VFPNegMul_VNMLA = ( (( 0 :: int)::ii))" +|" num_of_VFPNegMul VFPNegMul_VNMLS = ( (( 1 :: int)::ii))" +|" num_of_VFPNegMul VFPNegMul_VNMUL = ( (( 2 :: int)::ii))" + + +(*val undefined_VFPNegMul : unit -> M VFPNegMul*) + +definition undefined_VFPNegMul :: " unit \((register_value),(VFPNegMul),(exception))monad " where + " undefined_VFPNegMul _ = ( internal_pick [VFPNegMul_VNMLA,VFPNegMul_VNMLS,VFPNegMul_VNMUL])" + + +(*val VBitOps_of_num : integer -> VBitOps*) + +definition VBitOps_of_num :: " int \ VBitOps " where + " VBitOps_of_num arg0 = ( + (let l__322 = arg0 in + if (((l__322 = (( 0 :: int)::ii)))) then VBitOps_VBIF + else if (((l__322 = (( 1 :: int)::ii)))) then VBitOps_VBIT + else VBitOps_VBSL))" + + +(*val num_of_VBitOps : VBitOps -> integer*) + +fun num_of_VBitOps :: " VBitOps \ int " where + " num_of_VBitOps VBitOps_VBIF = ( (( 0 :: int)::ii))" +|" num_of_VBitOps VBitOps_VBIT = ( (( 1 :: int)::ii))" +|" num_of_VBitOps VBitOps_VBSL = ( (( 2 :: int)::ii))" + + +(*val undefined_VBitOps : unit -> M VBitOps*) + +definition undefined_VBitOps :: " unit \((register_value),(VBitOps),(exception))monad " where + " undefined_VBitOps _ = ( internal_pick [VBitOps_VBIF,VBitOps_VBIT,VBitOps_VBSL])" + + +(*val VCGEtype_of_num : integer -> VCGEtype*) + +definition VCGEtype_of_num :: " int \ VCGEtype " where + " VCGEtype_of_num arg0 = ( + (let l__320 = arg0 in + if (((l__320 = (( 0 :: int)::ii)))) then VCGEtype_signed + else if (((l__320 = (( 1 :: int)::ii)))) then VCGEtype_unsigned + else VCGEtype_fp))" + + +(*val num_of_VCGEtype : VCGEtype -> integer*) + +fun num_of_VCGEtype :: " VCGEtype \ int " where + " num_of_VCGEtype VCGEtype_signed = ( (( 0 :: int)::ii))" +|" num_of_VCGEtype VCGEtype_unsigned = ( (( 1 :: int)::ii))" +|" num_of_VCGEtype VCGEtype_fp = ( (( 2 :: int)::ii))" + + +(*val undefined_VCGEtype : unit -> M VCGEtype*) + +definition undefined_VCGEtype :: " unit \((register_value),(VCGEtype),(exception))monad " where + " undefined_VCGEtype _ = ( internal_pick [VCGEtype_signed,VCGEtype_unsigned,VCGEtype_fp])" + + +(*val VCGTtype_of_num : integer -> VCGTtype*) + +definition VCGTtype_of_num :: " int \ VCGTtype " where + " VCGTtype_of_num arg0 = ( + (let l__318 = arg0 in + if (((l__318 = (( 0 :: int)::ii)))) then VCGTtype_signed + else if (((l__318 = (( 1 :: int)::ii)))) then VCGTtype_unsigned + else VCGTtype_fp))" + + +(*val num_of_VCGTtype : VCGTtype -> integer*) + +fun num_of_VCGTtype :: " VCGTtype \ int " where + " num_of_VCGTtype VCGTtype_signed = ( (( 0 :: int)::ii))" +|" num_of_VCGTtype VCGTtype_unsigned = ( (( 1 :: int)::ii))" +|" num_of_VCGTtype VCGTtype_fp = ( (( 2 :: int)::ii))" + + +(*val undefined_VCGTtype : unit -> M VCGTtype*) + +definition undefined_VCGTtype :: " unit \((register_value),(VCGTtype),(exception))monad " where + " undefined_VCGTtype _ = ( internal_pick [VCGTtype_signed,VCGTtype_unsigned,VCGTtype_fp])" + + +(*val __InstrEnc_of_num : integer -> __InstrEnc*) + +definition InstrEnc_of_num :: " int \ InstrEnc " where + " InstrEnc_of_num arg0 = ( + (let l__315 = arg0 in + if (((l__315 = (( 0 :: int)::ii)))) then A64 + else if (((l__315 = (( 1 :: int)::ii)))) then A32 + else if (((l__315 = (( 2 :: int)::ii)))) then T16 + else T32))" + + +(*val num_of___InstrEnc : __InstrEnc -> integer*) + +fun num_of___InstrEnc :: " InstrEnc \ int " where + " num_of___InstrEnc A64 = ( (( 0 :: int)::ii))" +|" num_of___InstrEnc A32 = ( (( 1 :: int)::ii))" +|" num_of___InstrEnc T16 = ( (( 2 :: int)::ii))" +|" num_of___InstrEnc T32 = ( (( 3 :: int)::ii))" + + +(*val undefined___InstrEnc : unit -> M __InstrEnc*) + +definition undefined___InstrEnc :: " unit \((register_value),(InstrEnc),(exception))monad " where + " undefined___InstrEnc _ = ( internal_pick [A64,A32,T16,T32])" + + +(*val AArch64_CheckAndUpdateDescriptor_SecondStage : DescriptorUpdate -> FaultRecord -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +(*val AArch64_TranslationTableWalk_SecondStage : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> ii -> M TLBRecord*) + +(*val AArch64_SecondStageTranslate : AddressDescriptor -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> bool -> M AddressDescriptor*) + +(*val AArch64_CheckAndUpdateDescriptor : DescriptorUpdate -> FaultRecord -> bool -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +(*val __UNKNOWN_real : unit -> real*) + +definition UNKNOWN_real :: " unit \ real " where + " UNKNOWN_real _ = ( (realFromFrac(( 0 :: int))(( 10 :: int))))" + + +(*val __UNKNOWN_integer : unit -> ii*) + +definition UNKNOWN_integer :: " unit \ int " where + " UNKNOWN_integer _ = ( (( 0 :: int)::ii))" + + +(*val aget_PC : unit -> M (mword ty64)*) + +definition aget_PC :: " unit \((register_value),((64)Word.word),(exception))monad " where + " aget_PC _ = ( (read_reg PC_ref :: ( 64 Word.word) M))" + + +(*val UndefinedFault : unit -> M unit*) + +definition UndefinedFault :: " unit \((register_value),(unit),(exception))monad " where + " UndefinedFault _ = ( assert_exp False (''Undefined fault''))" + + +(*val ThisInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +definition ThisInstrAddr :: " int \ unit \((register_value),(('N::len)Word.word),(exception))monad " where + " ThisInstrAddr (N__tv :: int) _ = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + return ((slice0 w__0 (( 0 :: int)::ii) N__tv :: ( 'N::len)Word.word))))" + + +(*val ThisInstr : unit -> M (mword ty32)*) + +definition ThisInstr0 :: " unit \((register_value),((32)Word.word),(exception))monad " where + " ThisInstr0 _ = ( (read_reg ThisInstr_ref :: ( 32 Word.word) M))" + + +(*val __UNKNOWN_SystemHintOp : unit -> SystemHintOp*) + +definition UNKNOWN_SystemHintOp :: " unit \ SystemHintOp " where + " UNKNOWN_SystemHintOp _ = ( SystemHintOp_NOP )" + + +(*val SynchronizeContext : unit -> unit*) + +definition SynchronizeContext :: " unit \ unit " where + " SynchronizeContext _ = ( () )" + + +(*val SErrorPending : unit -> M bool*) + +definition SErrorPending :: " unit \((register_value),(bool),(exception))monad " where + " SErrorPending _ = ( read_reg PendingPhysicalSError_ref )" + + +(*val ResetExternalDebugRegisters : bool -> unit*) + +definition ResetExternalDebugRegisters :: " bool \ unit " where + " ResetExternalDebugRegisters cold_reset = ( () )" + + +(*val ProfilingSynchronizationBarrier : unit -> unit*) + +definition ProfilingSynchronizationBarrier :: " unit \ unit " where + " ProfilingSynchronizationBarrier _ = ( () )" + + +(*val ProcessorID : unit -> ii*) + +definition ProcessorID :: " unit \ int " where + " ProcessorID _ = ( (( 0 :: int)::ii))" + + +(*val __UNKNOWN_PrefetchHint : unit -> PrefetchHint*) + +definition UNKNOWN_PrefetchHint :: " unit \ PrefetchHint " where + " UNKNOWN_PrefetchHint _ = ( Prefetch_READ )" + + +(*val __UNKNOWN_PSTATEField : unit -> PSTATEField*) + +definition UNKNOWN_PSTATEField :: " unit \ PSTATEField " where + " UNKNOWN_PSTATEField _ = ( PSTATEField_DAIFSet )" + + +(*val PACCellShuffle : mword ty64 -> M (mword ty64)*) + +definition PACCellShuffle :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " PACCellShuffle indata = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (outdata :: 64 bits) . + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + return outdata))))))))))))))))))" + + +(*val PACCellInvShuffle : mword ty64 -> M (mword ty64)*) + +definition PACCellInvShuffle :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " PACCellInvShuffle indata = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (outdata :: 64 bits) . + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + return outdata))))))))))))))))))" + + +(*val __UNKNOWN_MoveWideOp : unit -> MoveWideOp*) + +definition UNKNOWN_MoveWideOp :: " unit \ MoveWideOp " where + " UNKNOWN_MoveWideOp _ = ( MoveWideOp_N )" + + +(*val __UNKNOWN_MemType : unit -> MemType*) + +definition UNKNOWN_MemType :: " unit \ MemType " where + " UNKNOWN_MemType _ = ( MemType_Normal )" + + +(*val __UNKNOWN_MemOp : unit -> MemOp*) + +definition UNKNOWN_MemOp :: " unit \ MemOp " where + " UNKNOWN_MemOp _ = ( MemOp_LOAD )" + + +definition MemHint_RWA :: "(2)Word.word " where + " MemHint_RWA = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +definition MemHint_RA :: "(2)Word.word " where + " MemHint_RA = ( (vec_of_bits [B1,B0] :: 2 Word.word))" + + +definition MemHint_No :: "(2)Word.word " where + " MemHint_No = ( (vec_of_bits [B0,B0] :: 2 Word.word))" + + +(*val __UNKNOWN_MemBarrierOp : unit -> MemBarrierOp*) + +definition UNKNOWN_MemBarrierOp :: " unit \ MemBarrierOp " where + " UNKNOWN_MemBarrierOp _ = ( MemBarrierOp_DSB )" + + +definition MemAttr_WT :: "(2)Word.word " where + " MemAttr_WT = ( (vec_of_bits [B1,B0] :: 2 Word.word))" + + +definition MemAttr_WB :: "(2)Word.word " where + " MemAttr_WB = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +definition MemAttr_NC :: "(2)Word.word " where + " MemAttr_NC = ( (vec_of_bits [B0,B0] :: 2 Word.word))" + + +(*val __UNKNOWN_MemAtomicOp : unit -> MemAtomicOp*) + +definition UNKNOWN_MemAtomicOp :: " unit \ MemAtomicOp " where + " UNKNOWN_MemAtomicOp _ = ( MemAtomicOp_ADD )" + + +(*val __UNKNOWN_MBReqTypes : unit -> MBReqTypes*) + +definition UNKNOWN_MBReqTypes :: " unit \ MBReqTypes " where + " UNKNOWN_MBReqTypes _ = ( MBReqTypes_Reads )" + + +(*val __UNKNOWN_MBReqDomain : unit -> MBReqDomain*) + +definition UNKNOWN_MBReqDomain :: " unit \ MBReqDomain " where + " UNKNOWN_MBReqDomain _ = ( MBReqDomain_Nonshareable )" + + +definition M32_User :: "(5)Word.word " where + " M32_User = ( (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))" + + +definition M32_Undef :: "(5)Word.word " where + " M32_Undef = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" + + +definition M32_System :: "(5)Word.word " where + " M32_System = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" + + +definition M32_Svc :: "(5)Word.word " where + " M32_Svc = ( (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word))" + + +definition M32_Monitor :: "(5)Word.word " where + " M32_Monitor = ( (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word))" + + +definition M32_IRQ :: "(5)Word.word " where + " M32_IRQ = ( (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word))" + + +definition M32_Hyp :: "(5)Word.word " where + " M32_Hyp = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" + + +definition M32_FIQ :: "(5)Word.word " where + " M32_FIQ = ( (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word))" + + +definition M32_Abort :: "(5)Word.word " where + " M32_Abort = ( (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word))" + + +(*val __UNKNOWN_LogicalOp : unit -> LogicalOp*) + +definition UNKNOWN_LogicalOp :: " unit \ LogicalOp " where + " UNKNOWN_LogicalOp _ = ( LogicalOp_AND )" + + +(*val IsExclusiveLocal : FullAddress -> ii -> ii -> M bool*) + +definition IsExclusiveLocal :: " FullAddress \ int \ int \((register_value),(bool),(exception))monad " where + " IsExclusiveLocal paddress processorid size1 = ( read_reg ExclusiveLocal_ref )" + + +(*val InterruptPending : unit -> M bool*) + +definition InterruptPending :: " unit \((register_value),(bool),(exception))monad " where + " InterruptPending _ = ( read_reg PendingInterrupt_ref )" + + +(*val asl_Int : forall 'N . Size 'N => mword 'N -> bool -> ii*) + +definition asl_Int :: "('N::len)Word.word \ bool \ int " where + " asl_Int x unsigned = ( if unsigned then Word.uint x else Word.sint x )" + + +(*val InstructionSynchronizationBarrier : unit -> unit*) + +definition InstructionSynchronizationBarrier :: " unit \ unit " where + " InstructionSynchronizationBarrier _ = ( () )" + + +(*val __UNKNOWN_InstrSet : unit -> InstrSet*) + +definition UNKNOWN_InstrSet :: " unit \ InstrSet " where + " UNKNOWN_InstrSet _ = ( InstrSet_A64 )" + + +(*val Hint_Yield : unit -> unit*) + +definition Hint_Yield :: " unit \ unit " where + " Hint_Yield _ = ( () )" + + +(*val Hint_Prefetch : mword ty64 -> PrefetchHint -> ii -> bool -> unit*) + +definition Hint_Prefetch :: "(64)Word.word \ PrefetchHint \ int \ bool \ unit " where + " Hint_Prefetch address hint target stream = ( () )" + + +(*val Hint_Branch : BranchType -> unit*) + +definition Hint_Branch :: " BranchType \ unit " where + " Hint_Branch hint = ( () )" + + +(*val HaveFP16Ext : unit -> bool*) + +definition HaveFP16Ext :: " unit \ bool " where + " HaveFP16Ext _ = ( True )" + + +(*val HaveAnyAArch32 : unit -> bool*) + +definition HaveAnyAArch32 :: " unit \ bool " where + " HaveAnyAArch32 _ = ( False )" + + +(*val __UNKNOWN_Fault : unit -> Fault*) + +definition UNKNOWN_Fault :: " unit \ Fault " where + " UNKNOWN_Fault _ = ( Fault_None )" + + +(*val __UNKNOWN_FPUnaryOp : unit -> FPUnaryOp*) + +definition UNKNOWN_FPUnaryOp :: " unit \ FPUnaryOp " where + " UNKNOWN_FPUnaryOp _ = ( FPUnaryOp_ABS )" + + +(*val __UNKNOWN_FPType : unit -> FPType*) + +definition UNKNOWN_FPType :: " unit \ FPType " where + " UNKNOWN_FPType _ = ( FPType_Nonzero )" + + +(*val __UNKNOWN_FPRounding : unit -> FPRounding*) + +definition UNKNOWN_FPRounding :: " unit \ FPRounding " where + " UNKNOWN_FPRounding _ = ( FPRounding_TIEEVEN )" + + +(*val __UNKNOWN_FPMaxMinOp : unit -> FPMaxMinOp*) + +definition UNKNOWN_FPMaxMinOp :: " unit \ FPMaxMinOp " where + " UNKNOWN_FPMaxMinOp _ = ( FPMaxMinOp_MAX )" + + +(*val FPDecodeRounding : mword ty2 -> FPRounding*) + +definition FPDecodeRounding :: "(2)Word.word \ FPRounding " where + " FPDecodeRounding rmode = ( + (let b__0 = rmode in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then FPRounding_TIEEVEN + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then FPRounding_POSINF + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then FPRounding_NEGINF + else FPRounding_ZERO))" + + +(*val FPRoundingMode : mword ty32 -> FPRounding*) + +definition FPRoundingMode :: "(32)Word.word \ FPRounding " where + " FPRoundingMode fpcr = ( FPDecodeRounding ((slice0 fpcr (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))" + + +(*val __UNKNOWN_FPConvOp : unit -> FPConvOp*) + +definition UNKNOWN_FPConvOp :: " unit \ FPConvOp " where + " UNKNOWN_FPConvOp _ = ( FPConvOp_CVT_FtoI )" + + +(*val __UNKNOWN_boolean : unit -> bool*) + +definition UNKNOWN_boolean :: " unit \ bool " where + " UNKNOWN_boolean _ = ( False )" + + +(*val __ResetInterruptState : unit -> M unit*) + +definition ResetInterruptState :: " unit \((register_value),(unit),(exception))monad " where + " ResetInterruptState _ = ( + write_reg PendingPhysicalSError_ref False \ write_reg PendingInterrupt_ref False )" + + +(*val __ResetExecuteState : unit -> M unit*) + +definition ResetExecuteState :: " unit \((register_value),(unit),(exception))monad " where + " ResetExecuteState _ = ( write_reg Sleeping_ref False )" + + +(*val Unreachable : unit -> M unit*) + +definition Unreachable :: " unit \((register_value),(unit),(exception))monad " where + " Unreachable _ = ( assert_exp False (''FALSE''))" + + +(*val RBankSelect : mword ty5 -> ii -> ii -> ii -> ii -> ii -> ii -> ii -> M ii*) + +definition RBankSelect :: "(5)Word.word \ int \ int \ int \ int \ int \ int \ int \((register_value),(int),(exception))monad " where + " RBankSelect mode usr fiq irq svc abt und hyp = ( + undefined_int () \ (\ (result :: ii) . + (let pat0 = mode in + if (((pat0 = M32_User))) then return usr + else if (((pat0 = M32_FIQ))) then return fiq + else if (((pat0 = M32_IRQ))) then return irq + else if (((pat0 = M32_Svc))) then return svc + else if (((pat0 = M32_Abort))) then return abt + else if (((pat0 = M32_Hyp))) then return hyp + else if (((pat0 = M32_Undef))) then return und + else if (((pat0 = M32_System))) then return usr + else Unreachable () \ return result)))" + + +(*val TakeUnmaskedSErrorInterrupts : unit -> M unit*) + +definition TakeUnmaskedSErrorInterrupts :: " unit \((register_value),(unit),(exception))monad " where + " TakeUnmaskedSErrorInterrupts _ = ( assert_exp False (''FALSE''))" + + +(*val TakeUnmaskedPhysicalSErrorInterrupts : bool -> M unit*) + +definition TakeUnmaskedPhysicalSErrorInterrupts :: " bool \((register_value),(unit),(exception))monad " where + " TakeUnmaskedPhysicalSErrorInterrupts iesb_req = ( assert_exp False (''FALSE''))" + + +(*val StopInstructionPrefetchAndEnableITR : unit -> M unit*) + +definition StopInstructionPrefetchAndEnableITR :: " unit \((register_value),(unit),(exception))monad " where + " StopInstructionPrefetchAndEnableITR _ = ( assert_exp False (''FALSE''))" + + +(*val SendEvent : unit -> M unit*) + +definition SendEvent :: " unit \((register_value),(unit),(exception))monad " where + " SendEvent _ = ( assert_exp False (''FALSE''))" + + +(*val MarkExclusiveLocal : FullAddress -> ii -> ii -> M unit*) + +definition MarkExclusiveLocal :: " FullAddress \ int \ int \((register_value),(unit),(exception))monad " where + " MarkExclusiveLocal paddress processorid size1 = ( write_reg ExclusiveLocal_ref False )" + + +(*val MarkExclusiveGlobal : FullAddress -> ii -> ii -> M unit*) + +definition MarkExclusiveGlobal :: " FullAddress \ int \ int \((register_value),(unit),(exception))monad " where + " MarkExclusiveGlobal paddress processorid size1 = ( assert_exp False (''FALSE''))" + + +(*val IsExclusiveGlobal : FullAddress -> ii -> ii -> M bool*) + +definition IsExclusiveGlobal :: " FullAddress \ int \ int \((register_value),(bool),(exception))monad " where + " IsExclusiveGlobal paddress processorid size1 = ( assert_exp False (''FALSE'') \ return False )" + + +(*val ExclusiveMonitorsStatus : unit -> M (mword ty1)*) + +definition ExclusiveMonitorsStatus :: " unit \((register_value),((1)Word.word),(exception))monad " where + " ExclusiveMonitorsStatus _ = ( assert_exp False (''FALSE'') \ return (vec_of_bits [B0] :: 1 Word.word))" + + +(*val __UNKNOWN_Exception : unit -> Exception*) + +definition UNKNOWN_Exception :: " unit \ Exception " where + " UNKNOWN_Exception _ = ( Exception_Uncategorized )" + + +(*val SendEventLocal : unit -> M unit*) + +definition SendEventLocal :: " unit \((register_value),(unit),(exception))monad " where + " SendEventLocal _ = ( write_reg EventRegister_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val ErrorSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*) + +definition ErrorSynchronizationBarrier :: " MBReqDomain \ MBReqTypes \ unit " where + " ErrorSynchronizationBarrier domain1 types1 = ( () )" + + +(*val EnterLowPowerState : unit -> M unit*) + +definition EnterLowPowerState :: " unit \((register_value),(unit),(exception))monad " where + " EnterLowPowerState _ = ( write_reg Sleeping_ref True )" + + +(*val WaitForInterrupt : unit -> M unit*) + +definition WaitForInterrupt :: " unit \((register_value),(unit),(exception))monad " where + " WaitForInterrupt _ = ( EnterLowPowerState () )" + + +(*val EndOfInstruction : unit -> M unit*) + +definition EndOfInstruction :: " unit \((register_value),(unit),(exception))monad " where + " EndOfInstruction _ = ( throw (Error_ExceptionTaken () ))" + + +(*val TweakCellRot : mword ty4 -> M (mword ty4)*) + +definition TweakCellRot :: "(4)Word.word \((register_value),((4)Word.word),(exception))monad " where + " TweakCellRot incell_name = ( + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (outcell :: 4 bits) . + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) + ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + return outcell))))))" + + +(*val TweakShuffle : mword ty64 -> M (mword ty64)*) + +definition TweakShuffle :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " TweakShuffle indata = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (outdata :: 64 bits) . + (let (outdata :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__0 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) w__0 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__1 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) w__1 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__2 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) w__2 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__3 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__3 :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__4 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) w__4 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__5 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) w__5 :: 64 Word.word)) in + (TweakCellRot ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__6 :: + 4 Word.word) . + (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in + return outdata)))))))))))))))))))))))))" + + +(*val TweakCellInvRot : mword ty4 -> M (mword ty4)*) + +definition TweakCellInvRot :: "(4)Word.word \((register_value),((4)Word.word),(exception))monad " where + " TweakCellInvRot incell_name = ( + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (outcell :: 4 bits) . + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) + (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + (let (outcell :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) + ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 4 Word.word)) in + return outcell))))))" + + +(*val TweakInvShuffle : mword ty64 -> M (mword ty64)*) + +definition TweakInvShuffle :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " TweakInvShuffle indata = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (outdata :: 64 bits) . + (TweakCellInvRot ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__0 :: + 4 Word.word) . + (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) w__0 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__1 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) w__1 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__2 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) w__2 :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__3 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) w__3 :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__4 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) w__4 :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__5 :: + 4 Word.word) . + (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__5 :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let outdata = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (TweakCellInvRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \ (\ (w__6 :: + 4 Word.word) . + (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in + return outdata)))))))))))))))))))))))))" + + +definition EL3 :: "(2)Word.word " where + " EL3 = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +definition EL2 :: "(2)Word.word " where + " EL2 = ( (vec_of_bits [B1,B0] :: 2 Word.word))" + + +definition EL1 :: "(2)Word.word " where + " EL1 = ( (vec_of_bits [B0,B1] :: 2 Word.word))" + + +definition EL0 :: "(2)Word.word " where + " EL0 = ( (vec_of_bits [B0,B0] :: 2 Word.word))" + + +(*val __UNKNOWN_DeviceType : unit -> DeviceType*) + +definition UNKNOWN_DeviceType :: " unit \ DeviceType " where + " UNKNOWN_DeviceType _ = ( DeviceType_GRE )" + + +(*val DecodeShift : mword ty2 -> ShiftType*) + +definition DecodeShift :: "(2)Word.word \ ShiftType " where + " DecodeShift op1 = ( + (let b__0 = op1 in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then ShiftType_LSL + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then ShiftType_LSR + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then ShiftType_ASR + else ShiftType_ROR))" + + +(*val DecodeRegExtend : mword ty3 -> ExtendType*) + +definition DecodeRegExtend :: "(3)Word.word \ ExtendType " where + " DecodeRegExtend op1 = ( + (let b__0 = op1 in + if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then ExtendType_UXTB + else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then ExtendType_UXTH + else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then ExtendType_UXTW + else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then ExtendType_UXTX + else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then ExtendType_SXTB + else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then ExtendType_SXTH + else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then ExtendType_SXTW + else ExtendType_SXTX))" + + +definition DebugHalt_Watchpoint :: "(6)Word.word " where + " DebugHalt_Watchpoint = ( (vec_of_bits [B1,B0,B1,B0,B1,B1] :: 6 Word.word))" + + +definition DebugHalt_HaltInstruction :: "(6)Word.word " where + " DebugHalt_HaltInstruction = ( (vec_of_bits [B1,B0,B1,B1,B1,B1] :: 6 Word.word))" + + +definition DebugHalt_Breakpoint :: "(6)Word.word " where + " DebugHalt_Breakpoint = ( (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))" + + +definition DebugException_VectorCatch :: "(4)Word.word " where + " DebugException_VectorCatch = ( (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word))" + + +(*val DataSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*) + +definition DataSynchronizationBarrier :: " MBReqDomain \ MBReqTypes \ unit " where + " DataSynchronizationBarrier domain1 types1 = ( () )" + + +(*val DataMemoryBarrier : MBReqDomain -> MBReqTypes -> unit*) + +definition DataMemoryBarrier :: " MBReqDomain \ MBReqTypes \ unit " where + " DataMemoryBarrier domain1 types1 = ( () )" + + +(*val aarch64_system_barriers : MBReqDomain -> MemBarrierOp -> MBReqTypes -> unit*) + +fun aarch64_system_barriers :: " MBReqDomain \ MemBarrierOp \ MBReqTypes \ unit " where + " aarch64_system_barriers domain1 MemBarrierOp_DSB types1 = ( DataSynchronizationBarrier domain1 types1 )" +|" aarch64_system_barriers domain1 MemBarrierOp_DMB types1 = ( DataMemoryBarrier domain1 types1 )" +|" aarch64_system_barriers domain1 MemBarrierOp_ISB types1 = ( InstructionSynchronizationBarrier () )" + + +(*val __UNKNOWN_Constraint : unit -> Constraint*) + +definition UNKNOWN_Constraint :: " unit \ Constraint " where + " UNKNOWN_Constraint _ = ( Constraint_NONE )" + + +(*val ConstrainUnpredictable : Unpredictable -> Constraint*) + +fun ConstrainUnpredictable :: " Unpredictable \ Constraint " where + " ConstrainUnpredictable Unpredictable_WBOVERLAPLD = ( Constraint_WBSUPPRESS )" +|" ConstrainUnpredictable Unpredictable_WBOVERLAPST = ( Constraint_NONE )" +|" ConstrainUnpredictable Unpredictable_LDPOVERLAP = ( Constraint_UNDEF )" +|" ConstrainUnpredictable Unpredictable_BASEOVERLAP = ( Constraint_NONE )" +|" ConstrainUnpredictable Unpredictable_DATAOVERLAP = ( Constraint_NONE )" +|" ConstrainUnpredictable Unpredictable_DEVPAGE2 = ( Constraint_FAULT )" +|" ConstrainUnpredictable Unpredictable_INSTRDEVICE = ( Constraint_NONE )" +|" ConstrainUnpredictable Unpredictable_RESCPACR = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESMAIR = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESTEXCB = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESDACR = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESPRRR = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESVTCRS = ( Constraint_UNKNOWN )" +|" ConstrainUnpredictable Unpredictable_RESTnSZ = ( Constraint_FORCE )" +|" ConstrainUnpredictable Unpredictable_OORTnSZ = ( Constraint_FORCE )" +|" ConstrainUnpredictable Unpredictable_LARGEIPA = ( Constraint_FORCE )" +|" ConstrainUnpredictable Unpredictable_ESRCONDPASS = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_ILZEROIT = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_ILZEROT = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_BPVECTORCATCHPRI = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_VCMATCHHALF = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_VCMATCHDAPA = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_WPMASKANDBAS = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_WPBASCONTIGUOUS = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_RESWPMASK = ( Constraint_DISABLED )" +|" ConstrainUnpredictable Unpredictable_WPMASKEDBITS = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_RESBPWPCTRL = ( Constraint_DISABLED )" +|" ConstrainUnpredictable Unpredictable_BPNOTIMPL = ( Constraint_DISABLED )" +|" ConstrainUnpredictable Unpredictable_RESBPTYPE = ( Constraint_DISABLED )" +|" ConstrainUnpredictable Unpredictable_BPNOTCTXCMP = ( Constraint_DISABLED )" +|" ConstrainUnpredictable Unpredictable_BPMATCHHALF = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_BPMISMATCHHALF = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_RESTARTALIGNPC = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_RESTARTZEROUPPERPC = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_ZEROUPPER = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_ERETZEROUPPERPC = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_A32FORCEALIGNPC = ( Constraint_FALSE )" +|" ConstrainUnpredictable Unpredictable_SMD = ( Constraint_UNDEF )" +|" ConstrainUnpredictable Unpredictable_AFUPDATE = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_IESBinDebug = ( Constraint_TRUE )" +|" ConstrainUnpredictable Unpredictable_CLEARERRITEZERO = ( Constraint_FALSE )" + + +(*val ClearPendingPhysicalSError : unit -> M unit*) + +definition ClearPendingPhysicalSError :: " unit \((register_value),(unit),(exception))monad " where + " ClearPendingPhysicalSError _ = ( write_reg PendingPhysicalSError_ref False )" + + +(*val ClearExclusiveLocal : ii -> M unit*) + +definition ClearExclusiveLocal :: " int \((register_value),(unit),(exception))monad " where + " ClearExclusiveLocal processorid = ( write_reg ExclusiveLocal_ref False )" + + +(*val aarch64_system_monitors : unit -> M unit*) + +definition aarch64_system_monitors :: " unit \((register_value),(unit),(exception))monad " where + " aarch64_system_monitors _ = ( ClearExclusiveLocal ((ProcessorID () )))" + + +(*val system_monitors_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition system_monitors_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_monitors_decode L op0 op1 CRn CRm op2 Rt = ( + write_reg unconditional_ref True \ aarch64_system_monitors () )" + + +(*val ClearExclusiveByAddress : FullAddress -> ii -> ii -> unit*) + +definition ClearExclusiveByAddress :: " FullAddress \ int \ int \ unit " where + " ClearExclusiveByAddress paddress processorid size1 = ( () )" + + +(*val ClearEventRegister : unit -> M unit*) + +definition ClearEventRegister :: " unit \((register_value),(unit),(exception))monad " where + " ClearEventRegister _ = ( write_reg EventRegister_ref (vec_of_bits [B0] :: 1 Word.word))" + + +(*val CTI_SignalEvent : CrossTriggerIn -> M unit*) + +definition CTI_SignalEvent :: " CrossTriggerIn \((register_value),(unit),(exception))monad " where + " CTI_SignalEvent id1 = ( assert_exp False (''FALSE''))" + + +(*val __UNKNOWN_BranchType : unit -> BranchType*) + +definition UNKNOWN_BranchType :: " unit \ BranchType " where + " UNKNOWN_BranchType _ = ( BranchType_CALL )" + + +(*val __UNKNOWN_AccType : unit -> AccType*) + +definition UNKNOWN_AccType :: " unit \ AccType " where + " UNKNOWN_AccType _ = ( AccType_NORMAL )" + + +(*val CreateAccessDescriptorPTW : AccType -> bool -> bool -> ii -> M AccessDescriptor*) + +definition CreateAccessDescriptorPTW :: " AccType \ bool \ bool \ int \((register_value),(AccessDescriptor),(exception))monad " where + " CreateAccessDescriptorPTW acctype secondstage s2fs1walk level = ( + undefined_AccessDescriptor () \ (\ (accdesc :: AccessDescriptor) . + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_acctype := acctype |))) in + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_page_table_walk := True |))) in + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_secondstage := s2fs1walk |))) in + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_secondstage := secondstage |))) in + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_level := level |))) in + return accdesc)))))))" + + +(*val CreateAccessDescriptor : AccType -> M AccessDescriptor*) + +definition CreateAccessDescriptor :: " AccType \((register_value),(AccessDescriptor),(exception))monad " where + " CreateAccessDescriptor acctype = ( + undefined_AccessDescriptor () \ (\ (accdesc :: AccessDescriptor) . + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_acctype := acctype |))) in + (let (accdesc :: AccessDescriptor) = ((accdesc (| AccessDescriptor_page_table_walk := False |))) in + return accdesc))))" + + +(*val aarch64_system_register_cpsr : PSTATEField -> mword ty4 -> M unit*) + +fun aarch64_system_register_cpsr :: " PSTATEField \(4)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_register_cpsr PSTATEField_SP operand = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + write_reg + PSTATE_ref + (w__0 (| ProcState_SP := ((vec_of_bits [access_vec_dec operand (( 0 :: int)::ii)] :: 1 Word.word))|))))" +|" aarch64_system_register_cpsr PSTATEField_DAIFSet operand = ( + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (write_reg + PSTATE_ref + (w__1 (| + ProcState_D := + ((or_vec(ProcState_D w__2) (vec_of_bits [access_vec_dec operand (( 3 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (write_reg + PSTATE_ref + (w__3 (| + ProcState_A := + ((or_vec(ProcState_A w__4) (vec_of_bits [access_vec_dec operand (( 2 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (write_reg + PSTATE_ref + (w__5 (| + ProcState_I := + ((or_vec(ProcState_I w__6) (vec_of_bits [access_vec_dec operand (( 1 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + write_reg + PSTATE_ref + (w__7 (| + ProcState_F := + ((or_vec(ProcState_F w__8) (vec_of_bits [access_vec_dec operand (( 0 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word))|)))))))))))" +|" aarch64_system_register_cpsr PSTATEField_DAIFClr operand = ( + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (write_reg + PSTATE_ref + (w__9 (| + ProcState_D := + ((and_vec(ProcState_D w__10) + ((not_vec (vec_of_bits [access_vec_dec operand (( 3 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + (write_reg + PSTATE_ref + (w__11 (| + ProcState_A := + ((and_vec(ProcState_A w__12) + ((not_vec (vec_of_bits [access_vec_dec operand (( 2 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__14 :: ProcState) . + (write_reg + PSTATE_ref + (w__13 (| + ProcState_I := + ((and_vec(ProcState_I w__14) + ((not_vec (vec_of_bits [access_vec_dec operand (( 1 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + write_reg + PSTATE_ref + (w__15 (| + ProcState_F := + ((and_vec(ProcState_F w__16) + ((not_vec (vec_of_bits [access_vec_dec operand (( 0 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + :: 1 Word.word))|)))))))))))" +|" aarch64_system_register_cpsr PSTATEField_PAN operand = ( + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + write_reg + PSTATE_ref + (w__17 (| ProcState_PAN := ((vec_of_bits [access_vec_dec operand (( 0 :: int)::ii)] :: 1 Word.word))|))))" +|" aarch64_system_register_cpsr PSTATEField_UAO operand = ( + read_reg PSTATE_ref \ (\ (w__18 :: ProcState) . + write_reg + PSTATE_ref + (w__18 (| ProcState_UAO := ((vec_of_bits [access_vec_dec operand (( 0 :: int)::ii)] :: 1 Word.word))|))))" + + +(*val AArch64_SysRegWrite : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*) + +definition AArch64_SysRegWrite :: " int \ int \ int \ int \ int \(64)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_SysRegWrite op0 op1 crn crm op2 val_name = ( assert_exp False (''FALSE''))" + + +(*val AArch64_SysRegRead : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*) + +definition AArch64_SysRegRead :: " int \ int \ int \ int \ int \((register_value),((64)Word.word),(exception))monad " where + " AArch64_SysRegRead arg0 arg1 arg2 arg3 arg4 = ( + (let g__614 = (arg0, arg1, arg2, arg3, arg4) in + assert_exp False (''Tried to read system register'') \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)))" + + +(*val AArch64_SysInstr : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*) + +definition AArch64_SysInstr :: " int \ int \ int \ int \ int \(64)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_SysInstr op0 op1 crn crm op2 val_name = ( assert_exp False (''FALSE''))" + + +(*val AArch64_ResetControlRegisters : bool -> unit*) + +definition AArch64_ResetControlRegisters :: " bool \ unit " where + " AArch64_ResetControlRegisters cold_reset = ( () )" + + +(*val AArch64_ReportDeferredSError : mword ty25 -> M (mword ty64)*) + +definition AArch64_ReportDeferredSError :: "(25)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AArch64_ReportDeferredSError syndrome = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (target :: 64 bits) . + (let (target :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) in + (let (target :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 24 :: int)::ii) + (vec_of_bits [access_vec_dec syndrome (( 24 :: int)::ii)] :: 1 Word.word) + :: 64 Word.word)) in + (let (target :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 24 :: int)::ii) target (( 0 :: int)::ii) ((slice0 syndrome (( 0 :: int)::ii) (( 24 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word)) in + return target)))))" + + +(*val AArch64_MarkExclusiveVA : mword ty64 -> ii -> ii -> M unit*) + +definition AArch64_MarkExclusiveVA :: "(64)Word.word \ int \ int \((register_value),(unit),(exception))monad " where + " AArch64_MarkExclusiveVA address processorid size1 = ( assert_exp False (''FALSE''))" + + +(*val AArch64_IsExclusiveVA : mword ty64 -> ii -> ii -> M bool*) + +definition AArch64_IsExclusiveVA :: "(64)Word.word \ int \ int \((register_value),(bool),(exception))monad " where + " AArch64_IsExclusiveVA address processorid size1 = ( assert_exp False (''FALSE'') \ return False )" + + +(*val AArch64_CreateFaultRecord : Fault -> mword ty52 -> ii -> AccType -> bool -> mword ty1 -> mword ty2 -> bool -> bool -> M FaultRecord*) + +definition AArch64_CreateFaultRecord :: " Fault \(52)Word.word \ int \ AccType \ bool \(1)Word.word \(2)Word.word \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CreateFaultRecord typ1 ipaddress level acctype write1 extflag errortype secondstage s2fs1walk = ( + undefined_FaultRecord () \ (\ (fault :: FaultRecord) . + (let fault = ((fault (| FaultRecord_typ := typ1 |))) in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__0 :: 4 bits) . + (let fault = ((fault (| FaultRecord_domain := w__0 |))) in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__1 :: 4 bits) . + (let (fault :: FaultRecord) = ((fault (| FaultRecord_debugmoe := w__1 |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_errortype := errortype |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_ipaddress := ipaddress |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_level := level |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_acctype := acctype |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_write := write1 |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_extflag := extflag |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_secondstage := secondstage |))) in + (let (fault :: FaultRecord) = ((fault (| FaultRecord_s2fs1walk := s2fs1walk |))) in + return fault)))))))))))))))" + + +(*val AArch64_TranslationFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +definition AArch64_TranslationFault :: "(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + AArch64_CreateFaultRecord Fault_Translation ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))" + + +(*val AArch64_PermissionFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +definition AArch64_PermissionFault :: "(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_PermissionFault ipaddress level acctype iswrite secondstage s2fs1walk = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + AArch64_CreateFaultRecord Fault_Permission ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))" + + +(*val AArch64_NoFault : unit -> M FaultRecord*) + +definition AArch64_NoFault :: " unit \((register_value),(FaultRecord),(exception))monad " where + " AArch64_NoFault _ = ( + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + undefined_int () \ (\ (level :: ii) . + (let (acctype :: AccType) = AccType_NORMAL in + undefined_bool () \ (\ (iswrite :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + (let (secondstage :: bool) = False in + (let (s2fs1walk :: bool) = False in + AArch64_CreateFaultRecord Fault_None ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))))))))" + + +(*val AArch64_DebugFault : AccType -> bool -> M FaultRecord*) + +definition AArch64_DebugFault :: " AccType \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_DebugFault acctype iswrite = ( + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + undefined_int () \ (\ (level :: ii) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (let (secondstage :: bool) = False in + (let (s2fs1walk :: bool) = False in + AArch64_CreateFaultRecord Fault_Debug ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))))))" + + +(*val AArch64_CheckUnallocatedSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M bool*) + +definition AArch64_CheckUnallocatedSystemAccess :: "(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(1)Word.word \((register_value),(bool),(exception))monad " where + " AArch64_CheckUnallocatedSystemAccess op0 op1 crn crm op2 read = ( + assert_exp False (''FALSE'') \ return False )" + + +(*val AArch64_CheckSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*) + +definition AArch64_CheckSystemRegisterTraps :: "(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(1)Word.word \((register_value),(bool*(2)Word.word),(exception))monad " where + " AArch64_CheckSystemRegisterTraps op0 op1 crn crm op2 read = ( + assert_exp False (''FALSE'') \ return (False, (vec_of_bits [B0,B0] :: 2 Word.word)))" + + +(*val AArch64_CheckAdvSIMDFPSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*) + +definition AArch64_CheckAdvSIMDFPSystemRegisterTraps :: "(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(1)Word.word \((register_value),(bool*(2)Word.word),(exception))monad " where + " AArch64_CheckAdvSIMDFPSystemRegisterTraps op0 op1 crn crm op2 read = ( + assert_exp False (''FALSE'') \ return (False, (vec_of_bits [B0,B0] :: 2 Word.word)))" + + +(*val AArch64_AlignmentFault : AccType -> bool -> bool -> M FaultRecord*) + +definition AArch64_AlignmentFault :: " AccType \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_AlignmentFault acctype iswrite secondstage = ( + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + undefined_int () \ (\ (level :: ii) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + undefined_bool () \ (\ (s2fs1walk :: bool) . + AArch64_CreateFaultRecord Fault_Alignment ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))))" + + +(*val AArch64_AddressSizeFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +definition AArch64_AddressSizeFault :: "(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + AArch64_CreateFaultRecord Fault_AddressSize ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))" + + +(*val AArch64_AccessFlagFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +definition AArch64_AccessFlagFault :: "(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_AccessFlagFault ipaddress level acctype iswrite secondstage s2fs1walk = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (extflag :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (errortype :: 2 bits) . + AArch64_CreateFaultRecord Fault_AccessFlag ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))" + + +(*val AArch32_CurrentCond : unit -> M (mword ty4)*) + +definition AArch32_CurrentCond :: " unit \((register_value),((4)Word.word),(exception))monad " where + " AArch32_CurrentCond _ = ( (read_reg currentCond_ref :: ( 4 Word.word) M))" + + +(*val aget_SP : forall 'width . Size 'width => integer -> unit -> M (mword 'width)*) + +definition aget_SP :: " int \ unit \((register_value),(('width::len)Word.word),(exception))monad " where + " aget_SP (width__tv :: int) _ = ( + (assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \ ((((((width__tv = (( 16 :: int)::ii)))) \ ((((((width__tv = (( 32 :: int)::ii)))) \ (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \ + read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + if ((((ProcState_SP w__0) = (vec_of_bits [B0] :: 1 Word.word)))) then + (read_reg SP_EL0_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + return ((slice0 w__1 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let p__613 = ((ProcState_EL w__2)) in + (let pat0 = p__613 in + if (((pat0 = EL0))) then + (read_reg SP_EL0_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((slice0 w__3 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else if (((pat0 = EL1))) then + (read_reg SP_EL1_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((slice0 w__4 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else if (((pat0 = EL2))) then + (read_reg SP_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((slice0 w__5 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else + (read_reg SP_EL3_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((slice0 w__6 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))))))" + + +(*val __IMPDEF_integer : string -> ii*) + +definition IMPDEF_integer :: " string \ int " where + " IMPDEF_integer x = ( + if (((x = (''Maximum Physical Address Size'')))) then (( 52 :: int)::ii) + else if (((x = (''Maximum Virtual Address Size'')))) then (( 56 :: int)::ii) + else (( 0 :: int)::ii))" + + +(*val VAMax : unit -> ii*) + +definition VAMax :: " unit \ int " where + " VAMax _ = ( IMPDEF_integer (''Maximum Virtual Address Size''))" + + +(*val PAMax : unit -> ii*) + +definition PAMax :: " unit \ int " where + " PAMax _ = ( IMPDEF_integer (''Maximum Physical Address Size''))" + + +(*val __IMPDEF_boolean : string -> bool*) + +definition IMPDEF_boolean :: " string \ bool " where + " IMPDEF_boolean x = ( + if (((x = (''Condition valid for trapped T32'')))) then True + else if (((x = (''Has Dot Product extension'')))) then True + else if (((x = (''Has RAS extension'')))) then True + else if (((x = (''Has SHA512 and SHA3 Crypto instructions'')))) then True + else if (((x = (''Has SM3 and SM4 Crypto instructions'')))) then True + else if (((x = (''Has basic Crypto instructions'')))) then True + else if (((x = (''Have CRC extension'')))) then True + else if (((x = (''Report I-cache maintenance fault in IFSR'')))) then True + else if (((x = (''Reserved Control Space EL0 Trapped'')))) then True + else if (((x = (''Translation fault on misprogrammed contiguous bit'')))) then True + else if (((x = (''UNDEF unallocated CP15 access at NS EL0'')))) then True + else if (((x = (''UNDEF unallocated CP15 access at NS EL0'')))) then True + else False )" + + +(*val WaitForEvent : unit -> M unit*) + +definition WaitForEvent :: " unit \((register_value),(unit),(exception))monad " where + " WaitForEvent _ = ( + (read_reg EventRegister_ref :: ( 1 Word.word) M) \ (\ (w__0 :: 1 bits) . + if (((w__0 = (vec_of_bits [B0] :: 1 Word.word)))) then EnterLowPowerState () + else return () ))" + + +(*val ThisInstrLength : unit -> M ii*) + +definition ThisInstrLength :: " unit \((register_value),(int),(exception))monad " where + " ThisInstrLength _ = ( + read_reg ThisInstrEnc_ref \ (\ (w__0 :: InstrEnc) . + return (if (((w__0 = T16))) then (( 16 :: int)::ii) + else (( 32 :: int)::ii))))" + + +(*val RoundTowardsZero : real -> ii*) + +definition RoundTowardsZero :: " real \ int " where + " RoundTowardsZero x = ( + if (((x = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then (( 0 :: int)::ii) + else if ((x \ (realFromFrac(( 0 :: int))(( 10 :: int))))) then floor x + else ceiling x )" + + +(*val Restarting : unit -> M bool*) + +definition Restarting :: " unit \((register_value),(bool),(exception))monad " where + " Restarting _ = ( + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))" + + +(*val PtrHasUpperAndLowerAddRanges : unit -> M bool*) + +definition PtrHasUpperAndLowerAddRanges :: " unit \((register_value),(bool),(exception))monad " where + " PtrHasUpperAndLowerAddRanges _ = ( + or_boolM + (or_boolM + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL1))))) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) = EL0)))))) + (and_boolM + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) = EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))))" + + +(*val MemAttrDefaults : MemoryAttributes -> M MemoryAttributes*) + +definition MemAttrDefaults :: " MemoryAttributes \((register_value),(MemoryAttributes),(exception))monad " where + " MemAttrDefaults memattrs__arg = ( + (let memattrs = memattrs__arg in + if ((((MemoryAttributes_typ memattrs) = MemType_Device))) then + undefined_MemAttrHints () \ (\ (w__0 :: MemAttrHints) . + (let memattrs = ((memattrs (| MemoryAttributes_inner := w__0 |))) in + undefined_MemAttrHints () \ (\ (w__1 :: MemAttrHints) . + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_outer := w__1 |))) in + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_shareable := True |))) in + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_outershareable := True |))) in + return memattrs)))))) + else + undefined_DeviceType () \ (\ (w__2 :: DeviceType) . + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_device := w__2 |))) in + (let (memattrs :: MemoryAttributes) = + (if (((((((MemAttrHints_attrs (MemoryAttributes_inner memattrs)) = MemAttr_NC))) \ ((((MemAttrHints_attrs (MemoryAttributes_outer memattrs)) = MemAttr_NC)))))) then + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_shareable := True |))) in + (memattrs (| MemoryAttributes_outershareable := True |))) + else memattrs) in + return memattrs)))))" + + +(*val IsEventRegisterSet : unit -> M bool*) + +definition IsEventRegisterSet :: " unit \((register_value),(bool),(exception))monad " where + " IsEventRegisterSet _ = ( + (read_reg EventRegister_ref :: ( 1 Word.word) M) \ (\ (w__0 :: 1 bits) . + return (((w__0 = (vec_of_bits [B1] :: 1 Word.word))))))" + + +(*val HaveEL : mword ty2 -> bool*) + +definition HaveEL :: "(2)Word.word \ bool " where + " HaveEL el = ( if ((((((el = EL1))) \ (((el = EL0)))))) then True else True )" + + +(*val HighestEL : unit -> mword ty2*) + +definition HighestEL :: " unit \(2)Word.word " where + " HighestEL _ = ( if ((HaveEL EL3)) then EL3 else if ((HaveEL EL2)) then EL2 else EL1 )" + + +(*val Have16bitVMID : unit -> bool*) + +definition Have16bitVMID :: " unit \ bool " where + " Have16bitVMID _ = ( HaveEL EL2 )" + + +(*val HasArchVersion : ArchVersion -> bool*) + +definition HasArchVersion :: " ArchVersion \ bool " where + " HasArchVersion version = ( + ((((version = ARMv8p0))) \ ((((((version = ARMv8p1))) \ ((((((version = ARMv8p2))) \ (((version = ARMv8p3)))))))))))" + + +(*val HaveVirtHostExt : unit -> bool*) + +definition HaveVirtHostExt :: " unit \ bool " where + " HaveVirtHostExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val HaveUAOExt : unit -> bool*) + +definition HaveUAOExt :: " unit \ bool " where + " HaveUAOExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val HaveTrapLoadStoreMultipleDeviceExt : unit -> bool*) + +definition HaveTrapLoadStoreMultipleDeviceExt :: " unit \ bool " where + " HaveTrapLoadStoreMultipleDeviceExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val HaveStatisticalProfiling : unit -> bool*) + +definition HaveStatisticalProfiling :: " unit \ bool " where + " HaveStatisticalProfiling _ = ( HasArchVersion ARMv8p2 )" + + +(*val HaveRASExt : unit -> bool*) + +definition HaveRASExt :: " unit \ bool " where + " HaveRASExt _ = ( (((HasArchVersion ARMv8p2)) \ ((IMPDEF_boolean (''Has RAS extension'')))))" + + +(*val HavePrivATExt : unit -> bool*) + +definition HavePrivATExt :: " unit \ bool " where + " HavePrivATExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val HavePANExt : unit -> bool*) + +definition HavePANExt :: " unit \ bool " where + " HavePANExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val HavePACExt : unit -> bool*) + +definition HavePACExt :: " unit \ bool " where + " HavePACExt _ = ( HasArchVersion ARMv8p3 )" + + +(*val HaveNVExt : unit -> bool*) + +definition HaveNVExt :: " unit \ bool " where + " HaveNVExt _ = ( HasArchVersion ARMv8p3 )" + + +(*val HaveFJCVTZSExt : unit -> bool*) + +definition HaveFJCVTZSExt :: " unit \ bool " where + " HaveFJCVTZSExt _ = ( HasArchVersion ARMv8p3 )" + + +(*val HaveExtendedExecuteNeverExt : unit -> bool*) + +definition HaveExtendedExecuteNeverExt :: " unit \ bool " where + " HaveExtendedExecuteNeverExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val HaveDirtyBitModifierExt : unit -> bool*) + +definition HaveDirtyBitModifierExt :: " unit \ bool " where + " HaveDirtyBitModifierExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val HaveCommonNotPrivateTransExt : unit -> bool*) + +definition HaveCommonNotPrivateTransExt :: " unit \ bool " where + " HaveCommonNotPrivateTransExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val HaveCRCExt : unit -> bool*) + +definition HaveCRCExt :: " unit \ bool " where + " HaveCRCExt _ = ( (((HasArchVersion ARMv8p1)) \ ((IMPDEF_boolean (''Have CRC extension'')))))" + + +(*val HaveAtomicExt : unit -> bool*) + +definition HaveAtomicExt :: " unit \ bool " where + " HaveAtomicExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val HaveAccessFlagUpdateExt : unit -> bool*) + +definition HaveAccessFlagUpdateExt :: " unit \ bool " where + " HaveAccessFlagUpdateExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val Have52BitVAExt : unit -> bool*) + +definition Have52BitVAExt :: " unit \ bool " where + " Have52BitVAExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val Have52BitPAExt : unit -> bool*) + +definition Have52BitPAExt :: " unit \ bool " where + " Have52BitPAExt _ = ( HasArchVersion ARMv8p2 )" + + +(*val AArch64_HaveHPDExt : unit -> bool*) + +definition AArch64_HaveHPDExt :: " unit \ bool " where + " AArch64_HaveHPDExt _ = ( HasArchVersion ARMv8p1 )" + + +(*val ExternalInvasiveDebugEnabled : unit -> M bool*) + +definition ExternalInvasiveDebugEnabled :: " unit \((register_value),(bool),(exception))monad " where + " ExternalInvasiveDebugEnabled _ = ( + read_reg DBGEN_ref \ (\ (w__0 :: signal) . return (((w__0 = HIGH)))))" + + +(*val ConstrainUnpredictableInteger : ii -> ii -> Unpredictable -> M (Constraint * ii)*) + +definition ConstrainUnpredictableInteger :: " int \ int \ Unpredictable \((register_value),(Constraint*int),(exception))monad " where + " ConstrainUnpredictableInteger low high which = ( + (let (c :: Constraint) = (ConstrainUnpredictable which) in + if (((c = Constraint_UNKNOWN))) then return (c, low) + else undefined_int () \ (\ (w__0 :: ii) . return (c, w__0))))" + + +(*val ConstrainUnpredictableBool : Unpredictable -> M bool*) + +definition ConstrainUnpredictableBool :: " Unpredictable \((register_value),(bool),(exception))monad " where + " ConstrainUnpredictableBool which = ( + (let (c :: Constraint) = (ConstrainUnpredictable which) in + assert_exp ((((((c = Constraint_TRUE))) \ (((c = Constraint_FALSE)))))) (''((c == Constraint_TRUE) || (c == Constraint_FALSE))'') \ + return (((c = Constraint_TRUE)))))" + + +(*val CombineS1S2Device : DeviceType -> DeviceType -> M DeviceType*) + +definition CombineS1S2Device :: " DeviceType \ DeviceType \((register_value),(DeviceType),(exception))monad " where + " CombineS1S2Device s1device s2device = ( + undefined_DeviceType () \ (\ (result :: DeviceType) . + (let (result :: DeviceType) = + (if ((((((s2device = DeviceType_nGnRnE))) \ (((s1device = DeviceType_nGnRnE)))))) then + DeviceType_nGnRnE + else if ((((((s2device = DeviceType_nGnRE))) \ (((s1device = DeviceType_nGnRE)))))) then + DeviceType_nGnRE + else if ((((((s2device = DeviceType_nGRE))) \ (((s1device = DeviceType_nGRE)))))) then + DeviceType_nGRE + else DeviceType_GRE) in + return result)))" + + +(*val CombineS1S2AttrHints : MemAttrHints -> MemAttrHints -> M MemAttrHints*) + +definition CombineS1S2AttrHints :: " MemAttrHints \ MemAttrHints \((register_value),(MemAttrHints),(exception))monad " where + " CombineS1S2AttrHints s1desc s2desc = ( + undefined_MemAttrHints () \ (\ (result :: MemAttrHints) . + (if (((((((MemAttrHints_attrs s2desc) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ ((((MemAttrHints_attrs s1desc) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__0 :: 2 bits) . + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := w__0 |))) in + return result)) + else + (let (result :: MemAttrHints) = + (if (((((((MemAttrHints_attrs s2desc) = MemAttr_NC))) \ ((((MemAttrHints_attrs s1desc) = MemAttr_NC)))))) then + (result (| MemAttrHints_attrs := MemAttr_NC |)) + else if (((((((MemAttrHints_attrs s2desc) = MemAttr_WT))) \ ((((MemAttrHints_attrs s1desc) = MemAttr_WT)))))) then + (result (| MemAttrHints_attrs := MemAttr_WT |)) + else (result (| MemAttrHints_attrs := MemAttr_WB |))) in + return result)) \ (\ (result :: MemAttrHints) . + (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := ((MemAttrHints_hints s1desc))|))) in + (let (result :: MemAttrHints) = + ((result (| MemAttrHints_transient := ((MemAttrHints_transient s1desc))|))) in + return result)))))" + + +(*val AArch64_InstructionDevice : AddressDescriptor -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M AddressDescriptor*) + +definition AArch64_InstructionDevice :: " AddressDescriptor \(64)Word.word \(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_InstructionDevice addrdesc__arg vaddress ipaddress level acctype iswrite secondstage s2fs1walk = ( + (let addrdesc = addrdesc__arg in + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_INSTRDEVICE) in + assert_exp ((((((c = Constraint_NONE))) \ (((c = Constraint_FAULT)))))) (''((c == Constraint_NONE) || (c == Constraint_FAULT))'') \ + (if (((c = Constraint_FAULT))) then + AArch64_PermissionFault ipaddress level acctype iswrite secondstage s2fs1walk \ (\ (w__0 :: + FaultRecord) . + (let (addrdesc :: AddressDescriptor) = ((addrdesc (| AddressDescriptor_fault := w__0 |))) in + return addrdesc)) + else + (let (tmp_120 :: MemoryAttributes) = ((AddressDescriptor_memattrs addrdesc)) in + (let tmp_120 = ((tmp_120 (| MemoryAttributes_typ := MemType_Normal |))) in + (let addrdesc = ((addrdesc (| AddressDescriptor_memattrs := tmp_120 |))) in + (let (tmp_130 :: MemAttrHints) = ((MemoryAttributes_inner (AddressDescriptor_memattrs addrdesc))) in + (let tmp_130 = ((tmp_130 (| MemAttrHints_attrs := MemAttr_NC |))) in + (let (tmp_140 :: MemoryAttributes) = ((AddressDescriptor_memattrs addrdesc)) in + (let tmp_140 = ((tmp_140 (| MemoryAttributes_inner := tmp_130 |))) in + (let addrdesc = ((addrdesc (| AddressDescriptor_memattrs := tmp_140 |))) in + (let (tmp_150 :: MemAttrHints) = ((MemoryAttributes_inner (AddressDescriptor_memattrs addrdesc))) in + (let tmp_150 = ((tmp_150 (| MemAttrHints_hints := MemHint_No |))) in + (let (tmp_160 :: MemoryAttributes) = ((AddressDescriptor_memattrs addrdesc)) in + (let tmp_160 = ((tmp_160 (| MemoryAttributes_inner := tmp_150 |))) in + (let addrdesc = ((addrdesc (| AddressDescriptor_memattrs := tmp_160 |))) in + (let (tmp_170 :: MemoryAttributes) = ((AddressDescriptor_memattrs addrdesc)) in + (let tmp_170 = + ((tmp_170 (| + MemoryAttributes_outer := ((MemoryAttributes_inner (AddressDescriptor_memattrs addrdesc)))|))) in + (let addrdesc = ((addrdesc (| AddressDescriptor_memattrs := tmp_170 |))) in + MemAttrDefaults(AddressDescriptor_memattrs addrdesc) \ (\ (w__1 :: MemoryAttributes) . + (let (addrdesc :: AddressDescriptor) = ((addrdesc (| AddressDescriptor_memattrs := w__1 |))) in + return addrdesc))))))))))))))))))))))" + + +(*val aget_Vpart : forall 'width . Size 'width => integer -> ii -> ii -> M (mword 'width)*) + +definition aget_Vpart :: " int \ int \ int \((register_value),(('width::len)Word.word),(exception))monad " where + " aget_Vpart (width__tv :: int) n part = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((part = (( 0 :: int)::ii)))) \ (((part = (( 1 :: int)::ii))))))) (''((part == 0) || (part == 1))'')) \ + (if (((part = (( 0 :: int)::ii)))) then + (assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \ ((((((width__tv = (( 16 :: int)::ii)))) \ ((((((width__tv = (( 32 :: int)::ii)))) \ (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \ + read_reg V_ref) \ (\ (w__0 :: ( 128 bits) list) . + return ((slice0 ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else + (assert_exp (((width__tv = (( 64 :: int)::ii)))) (''(width == 64)'') \ + read_reg V_ref) \ (\ (w__1 :: ( 128 bits) list) . + return ((Word.ucast + ((slice0 ((access_list_dec w__1 n :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: ( 'width::len)Word.word)) + :: ( 'width::len)Word.word)))))" + + +(*val aget_V : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*) + +definition aget_V :: " int \ int \((register_value),(('width::len)Word.word),(exception))monad " where + " aget_V (width__tv :: int) n = ( + ((assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \ ((((((width__tv = (( 16 :: int)::ii)))) \ ((((((width__tv = (( 32 :: int)::ii)))) \ ((((((width__tv = (( 64 :: int)::ii)))) \ (((width__tv = (( 128 :: int)::ii)))))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))'')) \ + read_reg V_ref) \ (\ (w__0 :: ( 128 bits) list) . + return ((slice0 ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))" + + +(*val LookUpRIndex : ii -> mword ty5 -> M ii*) + +definition LookUpRIndex :: " int \(5)Word.word \((register_value),(int),(exception))monad " where + " LookUpRIndex n mode = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 14 :: int)::ii)))))) (''((n >= 0) && (n <= 14))'') \ + undefined_int () ) \ (\ (result :: ii) . + (let l__308 = n in + if (((l__308 = (( 8 :: int)::ii)))) then RBankSelect mode (( 8 :: int)::ii) (( 24 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) + else if (((l__308 = (( 9 :: int)::ii)))) then + RBankSelect mode (( 9 :: int)::ii) (( 25 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) + else if (((l__308 = (( 10 :: int)::ii)))) then + RBankSelect mode (( 10 :: int)::ii) (( 26 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) + else if (((l__308 = (( 11 :: int)::ii)))) then + RBankSelect mode (( 11 :: int)::ii) (( 27 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) + else if (((l__308 = (( 12 :: int)::ii)))) then + RBankSelect mode (( 12 :: int)::ii) (( 28 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) + else if (((l__308 = (( 13 :: int)::ii)))) then + RBankSelect mode (( 13 :: int)::ii) (( 29 :: int)::ii) (( 17 :: int)::ii) (( 19 :: int)::ii) (( 21 :: int)::ii) (( 23 :: int)::ii) (( 15 :: int)::ii) + else if (((l__308 = (( 14 :: int)::ii)))) then + RBankSelect mode (( 14 :: int)::ii) (( 30 :: int)::ii) (( 16 :: int)::ii) (( 18 :: int)::ii) (( 20 :: int)::ii) (( 22 :: int)::ii) (( 14 :: int)::ii) + else return n)))" + + +(*val HighestSetBit : forall 'N . Size 'N => mword 'N -> M ii*) + +definition HighestSetBit :: "('N::len)Word.word \((register_value),(int),(exception))monad " where + " HighestSetBit x = ( + catch_early_return + ((foreachM (index_list ((((int (size x))) - (( 1 :: int)::ii))) (( 0 :: int)::ii) (- (( 1 :: int)::ii))) () + (\ i unit_var . + if ((((vec_of_bits [access_vec_dec x i] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (early_return i :: (unit, ii) MR) + else return () )) \ + return ((- (( 1 :: int)::ii)))))" + + +(*val CountLeadingZeroBits : forall 'N . Size 'N => mword 'N -> M ii*) + +definition CountLeadingZeroBits :: "('N::len)Word.word \((register_value),(int),(exception))monad " where + " CountLeadingZeroBits x = ( + HighestSetBit x \ (\ (w__0 :: ii) . + return ((((((int (size x))) - (( 1 :: int)::ii))) - ((ex_int w__0))))))" + + +(*val CountLeadingSignBits : forall 'N . Size 'N => mword 'N -> M ii*) + +definition CountLeadingSignBits :: "('N::len)Word.word \((register_value),(ii),(exception))monad " where + " CountLeadingSignBits x = ( + CountLeadingZeroBits + ((xor_vec ((shiftr x (( 1 :: int)::ii) :: ( 'N::len)Word.word)) + ((and_vec x ((slice_mask ((int (size x))) (( 0 :: int)::ii) ((int (size x))) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))" + + +(*val BitReverse : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +definition BitReverse :: "('N::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " BitReverse data = ( + (undefined_bitvector ((int (size data))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + (let (result :: 'N bits) = + (foreach (index_list (( 0 :: int)::ii) ((((int (size data))) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 ((int (size data))) (( 1 :: int)::ii) result + ((((((int (size data))) - i)) - (( 1 :: int)::ii))) + (vec_of_bits [access_vec_dec data i] :: 1 Word.word) + :: ( 'N::len)Word.word))) in + return result)))" + + +(*val NextInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +definition NextInstrAddr :: " int \ unit \((register_value),(('N::len)Word.word),(exception))monad " where + " NextInstrAddr (N__tv :: int) _ = ( + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + ThisInstrLength () \ (\ (w__1 :: ii) . + return ((slice0 ((add_vec_int w__0 ((((ex_int w__1)) div (( 8 :: int)::ii))) :: 64 Word.word)) (( 0 :: int)::ii) + N__tv + :: ( 'N::len)Word.word)))))" + + +(*val AArch32_ExceptionClass : Exception -> M (ii * mword ty1)*) + +definition AArch32_ExceptionClass :: " Exception \((register_value),(int*(1)Word.word),(exception))monad " where + " AArch32_ExceptionClass typ1 = ( + ThisInstrLength () \ (\ (w__0 :: ii) . + (let (il :: 1 bits) = + (if (((((ex_int w__0)) = (( 32 :: int)::ii)))) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + undefined_int () \ (\ (ec :: ii) . + (case typ1 of + Exception_Uncategorized => + (let (ec :: ii) = ((( 0 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_WFxTrap => + (let (ec :: ii) = ((( 1 :: int)::ii)) in + return (ec, il)) + | Exception_CP15RTTrap => + (let (ec :: ii) = ((( 3 :: int)::ii)) in + return (ec, il)) + | Exception_CP15RRTTrap => + (let (ec :: ii) = ((( 4 :: int)::ii)) in + return (ec, il)) + | Exception_CP14RTTrap => + (let (ec :: ii) = ((( 5 :: int)::ii)) in + return (ec, il)) + | Exception_CP14DTTrap => + (let (ec :: ii) = ((( 6 :: int)::ii)) in + return (ec, il)) + | Exception_AdvSIMDFPAccessTrap => + (let (ec :: ii) = ((( 7 :: int)::ii)) in + return (ec, il)) + | Exception_FPIDTrap => + (let (ec :: ii) = ((( 8 :: int)::ii)) in + return (ec, il)) + | Exception_CP14RRTTrap => + (let (ec :: ii) = ((( 12 :: int)::ii)) in + return (ec, il)) + | Exception_IllegalState => + (let (ec :: ii) = ((( 14 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_SupervisorCall => + (let (ec :: ii) = ((( 17 :: int)::ii)) in + return (ec, il)) + | Exception_HypervisorCall => + (let (ec :: ii) = ((( 18 :: int)::ii)) in + return (ec, il)) + | Exception_MonitorCall => + (let (ec :: ii) = ((( 19 :: int)::ii)) in + return (ec, il)) + | Exception_InstructionAbort => + (let (ec :: ii) = ((( 32 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_PCAlignment => + (let (ec :: ii) = ((( 34 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_DataAbort => + (let (ec :: ii) = ((( 36 :: int)::ii)) in + return (ec, il)) + | Exception_FPTrappedException => + (let (ec :: ii) = ((( 40 :: int)::ii)) in + return (ec, il)) + | _ => Unreachable () \ return (ec, il) + ) \ (\ varstup . (let ((ec :: ii), (il :: 1 bits)) = varstup in + and_boolM (return ((((((((ex_int ec)) = (( 32 :: int)::ii)))) \ (((((ex_int ec)) = (( 36 :: int)::ii)))))))) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) = EL2))))) \ (\ (w__2 :: + bool) . + (let (ec :: ii) = (if w__2 then ((ex_int ec)) + (( 1 :: int)::ii) else ec) in + return (ec, il)))))))))" + + +(*val RotCell : mword ty4 -> ii -> M (mword ty4)*) + +definition RotCell :: "(4)Word.word \ int \((register_value),((4)Word.word),(exception))monad " where + " RotCell incell_name amount = ( + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (tmp :: 8 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (outcell :: 4 bits) . + (let (tmp :: 8 bits) = + ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) tmp (( 0 :: int)::ii) + ((concat_vec ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 8 Word.word)) + :: 8 Word.word)) in + (let (outcell :: 4 bits) = ((slice0 tmp (((( 4 :: int)::ii) - amount)) (( 4 :: int)::ii) :: 4 Word.word)) in + return outcell)))))" + + +(*val FPNeg : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +definition FPNeg :: "('N::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPNeg op1 = ( + (let l__305 = (int (size op1)) in + if (((l__305 = (( 16 :: int)::ii)))) then + (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op1 (((( 16 :: int)::ii) - (( 1 :: int)::ii)))] + :: 1 Word.word) + :: 1 Word.word)) + ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else if (((l__305 = (( 32 :: int)::ii)))) then + (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op1 (((( 32 :: int)::ii) - (( 1 :: int)::ii)))] + :: 1 Word.word) + :: 1 Word.word)) + ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else if (((l__305 = (( 64 :: int)::ii)))) then + (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op1 (((( 64 :: int)::ii) - (( 1 :: int)::ii)))] + :: 1 Word.word) + :: 1 Word.word)) + ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val FPAbs : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +definition FPAbs :: "('N::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPAbs op1 = ( + (let l__302 = (int (size op1)) in + if (((l__302 = (( 16 :: int)::ii)))) then + (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else if (((l__302 = (( 32 :: int)::ii)))) then + (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else if (((l__302 = (( 64 :: int)::ii)))) then + (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + return ((Word.ucast + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val EncodeLDFSC : Fault -> ii -> M (mword ty6)*) + +definition EncodeLDFSC :: " Fault \ int \((register_value),((6)Word.word),(exception))monad " where + " EncodeLDFSC typ1 level = ( + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (result :: 6 bits) . + (case typ1 of + Fault_AddressSize => + (let result = + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 0 :: int)::ii)))) \ ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii))))))))))))) (''((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))'') \ + return result) + | Fault_AccessFlag => + (let result = + ((concat_vec (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii)))))))))) (''((level == 1) || ((level == 2) || (level == 3)))'') \ + return result) + | Fault_Permission => + (let result = + ((concat_vec (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii)))))))))) (''((level == 1) || ((level == 2) || (level == 3)))'') \ + return result) + | Fault_Translation => + (let result = + ((concat_vec (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 0 :: int)::ii)))) \ ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii))))))))))))) (''((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))'') \ + return result) + | Fault_SyncExternal => + (let (result :: 6 bits) = ((vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)) in + return result) + | Fault_SyncExternalOnWalk => + (let result = + ((concat_vec (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 0 :: int)::ii)))) \ ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii))))))))))))) (''((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))'') \ + return result) + | Fault_SyncParity => + (let (result :: 6 bits) = ((vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word)) in + return result) + | Fault_SyncParityOnWalk => + (let result = + ((concat_vec (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word) + ((GetSlice_int ((make_the_value (( 2 :: int)::ii) :: 2 itself)) level (( 0 :: int)::ii) :: 2 Word.word)) + :: 6 Word.word)) in + assert_exp ((((((level = (( 0 :: int)::ii)))) \ ((((((level = (( 1 :: int)::ii)))) \ ((((((level = (( 2 :: int)::ii)))) \ (((level = (( 3 :: int)::ii))))))))))))) (''((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))'') \ + return result) + | Fault_AsyncParity => + (let (result :: 6 bits) = ((vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word)) in + return result) + | Fault_AsyncExternal => + (let (result :: 6 bits) = ((vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word)) in + return result) + | Fault_Alignment => + (let (result :: 6 bits) = ((vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word)) in + return result) + | Fault_Debug => + (let (result :: 6 bits) = ((vec_of_bits [B1,B0,B0,B0,B1,B0] :: 6 Word.word)) in + return result) + | Fault_TLBConflict => + (let (result :: 6 bits) = ((vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word)) in + return result) + | Fault_Lockdown => + (let (result :: 6 bits) = ((vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word)) in + return result) + | Fault_Exclusive => + (let (result :: 6 bits) = ((vec_of_bits [B1,B1,B0,B1,B0,B1] :: 6 Word.word)) in + return result) + | _ => Unreachable () \ return result + )))" + + +(*val BigEndianReverse : forall 'width . Size 'width => mword 'width -> M (mword 'width)*) + +definition BigEndianReverse :: "('width::len)Word.word \((register_value),(('width::len)Word.word),(exception))monad " where + " BigEndianReverse value_name = ( + assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 64 :: int)::ii)))) \ (((((int (size value_name))) = (( 128 :: int)::ii)))))))))))))))) ('''') \ + ((let (result :: 'width bits) = + ((replicate_bits (vec_of_bits [B0] :: 1 Word.word) ((int (size value_name))) :: ( 'width::len)Word.word)) in + (let (result :: 'width bits) = + (foreach (index_list (( 0 :: int)::ii) ((((int (size result))) - (( 1 :: int)::ii))) (( 8 :: int)::ii)) result + (\ i result . + (update_subrange_vec_dec result ((i + (( 7 :: int)::ii))) i + ((subrange_vec_dec value_name + ((((((int (size result))) - i)) - (( 1 :: int)::ii))) + ((((((int (size result))) - i)) - (( 8 :: int)::ii))) + :: 8 Word.word)) + :: ( 'width::len)Word.word))) in + return result))))" + + +(*val AArch32_ReportHypEntry : ExceptionRecord -> M unit*) + +definition AArch32_ReportHypEntry :: " ExceptionRecord \((register_value),(unit),(exception))monad " where + " AArch32_ReportHypEntry exception = ( + (let (typ1 :: Exception) = ((ExceptionRecord_typ exception)) in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (il :: 1 bits) . + undefined_int () \ (\ (ec :: ii) . + (AArch32_ExceptionClass typ1 :: ((ii * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let ec = tup__0 in + (let il = tup__1 in + (let (iss :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (il :: 1 bits) = + (if (((((((((((ex_int ec)) = (( 36 :: int)::ii)))) \ (((((ex_int ec)) = (( 37 :: int)::ii))))))) \ ((((vec_of_bits [access_vec_dec iss (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (vec_of_bits [B1] :: 1 Word.word) + else il) in + (write_reg + HSR_ref + ((concat_vec + ((concat_vec + ((GetSlice_int ((make_the_value (( 6 :: int)::ii) :: 6 itself)) ec (( 0 :: int)::ii) :: 6 Word.word)) il + :: 7 Word.word)) iss + :: 32 Word.word)) \ + (if ((((((typ1 = Exception_InstructionAbort))) \ (((typ1 = Exception_PCAlignment)))))) then + (write_reg HIFAR_ref ((slice0(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__0 :: 32 bits) . + write_reg HDFAR_ref w__0) + else if (((typ1 = Exception_DataAbort))) then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + write_reg HIFAR_ref w__1 \ + write_reg HDFAR_ref ((slice0(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))) + else return () )) \ + (if(ExceptionRecord_ipavalid exception) then + (read_reg HPFAR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + write_reg + HPFAR_ref + ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii) + ((slice0(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 28 :: int)::ii) :: 28 Word.word)) + :: 32 Word.word))) + else + (read_reg HPFAR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (undefined_bitvector (( 28 :: int)::ii) :: ( 28 Word.word) M) \ (\ (w__4 :: 28 Word.word) . + write_reg HPFAR_ref ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4 :: 32 Word.word)))))))))))))))" + + +(*val aset_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> mword 'size -> M (mword 'N)*) + +(*val aset_Elem__1 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> mword 'size -> M (mword 'N)*) + +definition aset_Elem__0 :: "('N::len)Word.word \ int \('size::len)itself \('size::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " aset_Elem__0 vector_name__arg e size1 value_name = ( + (let size1 = (size_itself_int size1) in + (let vector_name = vector_name__arg in + assert_exp (((((e \ (( 0 :: int)::ii))) \ ((((((e + (( 1 :: int)::ii))) * size1)) \ ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \ + ((let (vector_name :: ( 'N::len)Word.word) = + ((set_slice0 ((int (size vector_name))) size1 vector_name ((e * size1)) value_name + :: ( 'N::len)Word.word)) in + return vector_name)))))" + + +definition aset_Elem__1 :: "('N::len)Word.word \ int \('size::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " aset_Elem__1 vector_name__arg e value_name = ( + (let vector_name = vector_name__arg in + (aset_Elem__0 vector_name e ((make_the_value ((int (size value_name))) :: ( 'size::len)itself)) value_name + :: (( 'N::len)Word.word) M)))" + + +(*val aget_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> M (mword 'size)*) + +(*val aget_Elem__1 : forall 'N 'size . Size 'N, Size 'size => integer -> mword 'N -> ii -> M (mword 'size)*) + +definition aget_Elem__0 :: "('N::len)Word.word \ int \('size::len)itself \((register_value),(('size::len)Word.word),(exception))monad " where + " aget_Elem__0 vector_name e size1 = ( + (let size1 = (size_itself_int size1) in + assert_exp (((((e \ (( 0 :: int)::ii))) \ ((((((e + (( 1 :: int)::ii))) * size1)) \ ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \ + return ((slice0 vector_name ((e * size1)) size1 :: ( 'size::len)Word.word))))" + + +definition aget_Elem__1 :: " int \('N::len)Word.word \ int \((register_value),(('size::len)Word.word),(exception))monad " where + " aget_Elem__1 (size__tv :: int) vector_name e = ( + (aget_Elem__0 vector_name e ((make_the_value size__tv :: ( 'size::len)itself)) :: (( 'size::len)Word.word) M))" + + +(*val UnsignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) + +definition UnsignedSatQ :: " int \('N::len)itself \((register_value),(('N::len)Word.word*bool),(exception))monad " where + " UnsignedSatQ i N = ( + (let N = (size_itself_int N) in + undefined_bool () \ (\ (saturated :: bool) . + undefined_int () \ (\ (result :: ii) . + (let ((result :: ii), (saturated :: bool)) = + (if ((i > ((((pow2 N)) - (( 1 :: int)::ii))))) then + (let (result :: ii) = (((pow2 N)) - (( 1 :: int)::ii)) in + (let (saturated :: bool) = True in + (result, saturated))) + else + (let ((result :: ii), (saturated :: bool)) = + (if ((i < (( 0 :: int)::ii))) then + (let (result :: ii) = ((( 0 :: int)::ii)) in + (let (saturated :: bool) = True in + (result, saturated))) + else + (let (result :: ii) = i in + (let (saturated :: bool) = False in + (result, saturated)))) in + (result, saturated))) in + return ((GetSlice_int ((make_the_value N :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" + + +(*val SignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) + +definition SignedSatQ :: " int \('N::len)itself \((register_value),(('N::len)Word.word*bool),(exception))monad " where + " SignedSatQ i N = ( + (let N = (size_itself_int N) in + undefined_bool () \ (\ (saturated :: bool) . + undefined_int () \ (\ (result :: ii) . + (let ((result :: ii), (saturated :: bool)) = + (if ((i > ((((pow2 ((N - (( 1 :: int)::ii))))) - (( 1 :: int)::ii))))) then + (let (result :: ii) = (((pow2 ((N - (( 1 :: int)::ii))))) - (( 1 :: int)::ii)) in + (let (saturated :: bool) = True in + (result, saturated))) + else + (let ((result :: ii), (saturated :: bool)) = + (if ((i < ((- ((pow2 ((N - (( 1 :: int)::ii))))))))) then + (let (result :: ii) = (- ((pow2 ((N - (( 1 :: int)::ii)))))) in + (let (saturated :: bool) = True in + (result, saturated))) + else + (let (result :: ii) = i in + (let (saturated :: bool) = False in + (result, saturated)))) in + (result, saturated))) in + return ((GetSlice_int ((make_the_value N :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" + + +(*val SatQ : forall 'N . Size 'N => ii -> itself 'N -> bool -> M (mword 'N * bool)*) + +definition SatQ :: " int \('N::len)itself \ bool \((register_value),(('N::len)Word.word*bool),(exception))monad " where + " SatQ i N unsigned = ( + (let N = (size_itself_int N) in + undefined_bool () \ (\ (sat :: bool) . + (undefined_bitvector N :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + (if unsigned then (UnsignedSatQ i ((make_the_value N :: ( 'N::len)itself)) :: ((( 'N::len)Word.word * bool)) M) + else (SignedSatQ i ((make_the_value N :: ( 'N::len)itself)) :: ((( 'N::len)Word.word * bool)) M)) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (result :: 'N bits) = tup__0 in + (let (sat :: bool) = tup__1 in + return (result, sat)))))))))" + + +(*val Replicate : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +definition Replicate :: " int \('M::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " Replicate (N__tv :: int) x = ( + assert_exp (((((N__tv mod ((int (size x))))) = (( 0 :: int)::ii)))) (''((N MOD M) == 0)'') \ + return ((replicate_bits x ((N__tv div ((int (size x))))) :: ( 'N::len)Word.word)))" + + +(*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) + +(*val Zeros__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*) + +definition Zeros__0 :: "('N::len)itself \('N::len)Word.word " where + " Zeros__0 N = ( + (let N = (size_itself_int N) in + (replicate_bits (vec_of_bits [B0] :: 1 Word.word) N :: ( 'N::len)Word.word)))" + + +definition Zeros__1 :: " int \ unit \('N::len)Word.word " where + " Zeros__1 (N__tv :: int) _ = ( (Zeros__0 ((make_the_value N__tv :: ( 'N::len)itself)) :: ( 'N::len)Word.word))" + + +(*val __ResetMemoryState : unit -> M unit*) + +definition ResetMemoryState :: " unit \((register_value),(unit),(exception))monad " where + " ResetMemoryState _ = ( + (read_reg Memory_ref :: ( 52 Word.word) M) \ (\ (w__0 :: 52 Word.word) . + (let (_ :: unit) = + (InitRAM (( 52 :: int)::ii) (( 1 :: int)::ii) w__0 ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word))) in + write_reg ExclusiveLocal_ref False)))" + + +(*val ZeroExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*) + +(*val ZeroExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +definition ZeroExtend__0 :: "('M::len)Word.word \('N::len)itself \((register_value),(('N::len)Word.word),(exception))monad " where + " ZeroExtend__0 x N = ( + (let N = (size_itself_int N) in + assert_exp ((N \ ((int (size x))))) ('''') \ return ((extzv N x :: ( 'N::len)Word.word))))" + + +definition ZeroExtend__1 :: " int \('M::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " ZeroExtend__1 (N__tv :: int) x = ( + (ZeroExtend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M))" + + +(*val aset_Vpart : forall 'width . Size 'width => ii -> ii -> mword 'width -> M unit*) + +definition aset_Vpart :: " int \ int \('width::len)Word.word \((register_value),(unit),(exception))monad " where + " aset_Vpart n part value_name = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((part = (( 0 :: int)::ii)))) \ (((part = (( 1 :: int)::ii))))))) (''((part == 0) || (part == 1))'')) \ + (if (((part = (( 0 :: int)::ii)))) then + (assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \ (((((int (size value_name))) = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \ + read_reg V_ref) \ (\ (w__0 :: ( 128 Word.word) list) . + (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \ (\ (w__1 :: 128 bits) . + write_reg V_ref ((update_list_dec w__0 n w__1 :: ( 128 Word.word) list)))) + else + (assert_exp (((((int (size value_name))) = (( 64 :: int)::ii)))) (''(width == 64)'') \ + read_reg V_ref) \ (\ (w__2 :: ( 128 bits) list) . + (let (tmp_2870 :: 128 bits) = ((access_list_dec w__2 n :: 128 Word.word)) in + (let tmp_2870 = + ((update_subrange_vec_dec tmp_2870 (( 127 :: int)::ii) (( 64 :: int)::ii) + ((subrange_vec_dec value_name (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg V_ref \ (\ (w__3 :: ( 128 Word.word) list) . + write_reg V_ref ((update_list_dec w__3 n tmp_2870 :: ( 128 Word.word) list))))))))" + + +(*val aset_V : forall 'width . Size 'width => ii -> mword 'width -> M unit*) + +definition aset_V :: " int \('width::len)Word.word \((register_value),(unit),(exception))monad " where + " aset_V n value_name = ( + ((assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \ ((((((((int (size value_name))) = (( 64 :: int)::ii)))) \ (((((int (size value_name))) = (( 128 :: int)::ii)))))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))'')) \ + read_reg V_ref) \ (\ (w__0 :: ( 128 Word.word) list) . + (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \ (\ (w__1 :: 128 bits) . + write_reg V_ref ((update_list_dec w__0 n w__1 :: ( 128 Word.word) list)))))" + + +(*val AArch64_ResetSIMDFPRegisters : unit -> M unit*) + +definition AArch64_ResetSIMDFPRegisters :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_ResetSIMDFPRegisters _ = ( + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . aset_V i w__0))))" + + +(*val aset_SP : forall 'width . Size 'width => mword 'width -> M unit*) + +definition aset_SP :: "('width::len)Word.word \((register_value),(unit),(exception))monad " where + " aset_SP value_name = ( + (assert_exp ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \ (((((int (size value_name))) = (( 64 :: int)::ii))))))) (''((width == 32) || (width == 64))'') \ + read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + if ((((ProcState_SP w__0) = (vec_of_bits [B0] :: 1 Word.word)))) then + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + write_reg SP_EL0_ref w__1) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let p__612 = ((ProcState_EL w__2)) in + (let pat0 = p__612 in + if (((pat0 = EL0))) then + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + write_reg SP_EL0_ref w__3) + else if (((pat0 = EL1))) then + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + write_reg SP_EL1_ref w__4) + else if (((pat0 = EL2))) then + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + write_reg SP_EL2_ref w__5) + else + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + write_reg SP_EL3_ref w__6))))))" + + +(*val LSR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +definition LSR_C :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where + " LSR_C x shift = ( + assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \ + ((let (result :: 'N bits) = ((shiftr x shift :: ( 'N::len)Word.word)) in + (let (carry_out :: 1 bits) = + (if ((shift > ((int (size result))))) then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [access_vec_dec x ((shift - (( 1 :: int)::ii)))] :: 1 Word.word)) in + return (result, carry_out)))))" + + +(*val LSR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +definition LSR :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " LSR x shift = ( + (assert_exp ((shift \ (( 0 :: int)::ii))) (''(shift >= 0)'') \ + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (anon10 :: 1 bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if (((shift = (( 0 :: int)::ii)))) then return x + else + (LSR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (result :: 'N bits) = tup__0 in + (let (anon10 :: 1 bits) = tup__1 in + return result)))))))" + + +(*val Poly32Mod2 : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword ty32)*) + +definition Poly32Mod2 :: "('N::len)Word.word \(32)Word.word \((register_value),((32)Word.word),(exception))monad " where + " Poly32Mod2 data__arg poly = ( + (let data = data__arg in + assert_exp ((((int (size data))) > (( 32 :: int)::ii))) (''(N > 32)'') \ + ((let (poly' :: 'N bits) = ((extzv ((int (size data))) poly :: ( 'N::len)Word.word)) in + (let (data :: ( 'N::len)Word.word) = + (foreach (index_list ((((int (size data))) - (( 1 :: int)::ii))) (( 32 :: int)::ii) (- (( 1 :: int)::ii))) data + (\ i data . + if ((((vec_of_bits [access_vec_dec data i] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (or_vec data ((sub_vec_int ((shiftl poly' i :: ( 'N::len)Word.word)) (( 32 :: int)::ii) :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word) + else data)) in + return ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))))))" + + +(*val LSL_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +definition LSL_C :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where + " LSL_C x shift = ( + assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \ + ((let (result :: 'N bits) = ((shiftl x shift :: ( 'N::len)Word.word)) in + (let (carry_out :: 1 bits) = + (if ((shift > ((int (size result))))) then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [access_vec_dec x ((((int (size result))) - shift))] :: 1 Word.word)) in + return (result, carry_out)))))" + + +(*val LSL : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +definition LSL :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " LSL x shift = ( + (assert_exp ((shift \ (( 0 :: int)::ii))) (''(shift >= 0)'') \ + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (anon10 :: 1 bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if (((shift = (( 0 :: int)::ii)))) then return x + else + (LSL_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (result :: 'N bits) = tup__0 in + (let (anon10 :: 1 bits) = tup__1 in + return result)))))))" + + +(*val AArch32_ITAdvance : unit -> M unit*) + +definition AArch32_ITAdvance :: " unit \((register_value),(unit),(exception))monad " where + " AArch32_ITAdvance _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + if (((((slice0(ProcState_IT w__0) (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + write_reg + PSTATE_ref + (w__1 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|))) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let (tmp_2760 :: 8 bits) = ((ProcState_IT w__2)) in + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (LSL ((slice0(ProcState_IT w__3) (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) (( 1 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__4 :: + 5 Word.word) . + (let tmp_2760 = ((set_slice0 (( 8 :: int)::ii) (( 5 :: int)::ii) tmp_2760 (( 0 :: int)::ii) w__4 :: 8 Word.word)) in + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + write_reg PSTATE_ref (w__5 (| ProcState_IT := tmp_2760 |))))))))))" + + +(*val LSInstructionSyndrome : unit -> M (mword ty11)*) + +definition LSInstructionSyndrome :: " unit \((register_value),((11)Word.word),(exception))monad " where + " LSInstructionSyndrome _ = ( + assert_exp False (''FALSE'') \ + return ((Zeros__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)))" + + +(*val IsZero : forall 'N . Size 'N => mword 'N -> bool*) + +definition IsZero :: "('N::len)Word.word \ bool " where + " IsZero x = ( (x = ((Zeros__0 ((make_the_value ((int (size x))) :: ( 'N::len)itself)) :: ( 'N::len)Word.word))))" + + +(*val IsZeroBit : forall 'N . Size 'N => mword 'N -> mword ty1*) + +definition IsZeroBit :: "('N::len)Word.word \(1)Word.word " where + " IsZeroBit x = ( + if ((IsZero x)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val AddWithCarry : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty1 -> (mword 'N * mword ty4)*) + +definition AddWithCarry :: "('N::len)Word.word \('N::len)Word.word \(1)Word.word \('N::len)Word.word*(4)Word.word " where + " AddWithCarry x y carry_in = ( + (let (unsigned_sum :: ii) = (((((Word.uint x)) + ((Word.uint y)))) + ((Word.uint carry_in))) in + (let (signed_sum :: ii) = (((((Word.sint x)) + ((Word.sint y)))) + ((Word.uint carry_in))) in + (let (result :: 'N bits) = + ((GetSlice_int ((make_the_value ((int (size x))) :: ( 'N::len)itself)) unsigned_sum (( 0 :: int)::ii) :: ( 'N::len)Word.word)) in + (let (n :: 1 bits) = + ((vec_of_bits [access_vec_dec result ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in + (let (z :: 1 bits) = + (if ((IsZero result)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + (let (c :: 1 bits) = + (if (((((Word.uint result)) = ((ex_int unsigned_sum))))) then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + (let (v :: 1 bits) = + (if (((((Word.sint result)) = ((ex_int signed_sum))))) then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + (result, + (concat_vec ((concat_vec ((concat_vec n z :: 2 Word.word)) c :: 3 Word.word)) v :: 4 Word.word))))))))))" + + +(*val GetPSRFromPSTATE : unit -> M (mword ty32)*) + +definition GetPSRFromPSTATE :: " unit \((register_value),((32)Word.word),(exception))monad " where + " GetPSRFromPSTATE _ = ( + (let (spsr :: 32 bits) = ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 31 :: int)::ii) (( 31 :: int)::ii)(ProcState_N w__0) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 30 :: int)::ii) (( 30 :: int)::ii)(ProcState_Z w__1) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 29 :: int)::ii) (( 29 :: int)::ii)(ProcState_C w__2) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 28 :: int)::ii) (( 28 :: int)::ii)(ProcState_V w__3) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 21 :: int)::ii) (( 21 :: int)::ii)(ProcState_SS w__4) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 20 :: int)::ii) (( 20 :: int)::ii)(ProcState_IL w__5) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + if ((((ProcState_nRW w__6) = (vec_of_bits [B1] :: 1 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 27 :: int)::ii) (( 27 :: int)::ii)(ProcState_Q w__7) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (let spsr = + ((update_subrange_vec_dec spsr (( 26 :: int)::ii) (( 25 :: int)::ii) + ((subrange_vec_dec(ProcState_IT w__8) (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 19 :: int)::ii) (( 16 :: int)::ii)(ProcState_GE w__9) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (let spsr = + ((update_subrange_vec_dec spsr (( 15 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec(ProcState_IT w__10) (( 7 :: int)::ii) (( 2 :: int)::ii) :: 6 Word.word)) + :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 9 :: int)::ii) (( 9 :: int)::ii)(ProcState_E w__11) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 8 :: int)::ii) (( 8 :: int)::ii)(ProcState_A w__12) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__13 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 7 :: int)::ii) (( 7 :: int)::ii)(ProcState_I w__13) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__14 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 6 :: int)::ii) (( 6 :: int)::ii)(ProcState_F w__14) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__15 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 5 :: int)::ii) (( 5 :: int)::ii)(ProcState_T w__15) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + (assert_exp ((((vec_of_bits [access_vec_dec(ProcState_M w__16) (( 4 :: int)::ii)] :: 1 Word.word) =(ProcState_nRW w__17)))) (''(((PSTATE).M)<4> == (PSTATE).nRW)'') \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (let (spsr :: 32 bits) = + ((update_subrange_vec_dec spsr (( 4 :: int)::ii) (( 0 :: int)::ii)(ProcState_M w__18) :: 32 Word.word)) in + return spsr)))))))))))))))))))))) + else + read_reg PSTATE_ref \ (\ (w__19 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 9 :: int)::ii) (( 9 :: int)::ii)(ProcState_D w__19) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__20 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 8 :: int)::ii) (( 8 :: int)::ii)(ProcState_A w__20) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__21 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 7 :: int)::ii) (( 7 :: int)::ii)(ProcState_I w__21) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__22 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 6 :: int)::ii) (( 6 :: int)::ii)(ProcState_F w__22) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__23 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 4 :: int)::ii) (( 4 :: int)::ii)(ProcState_nRW w__23) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__24 :: ProcState) . + (let spsr = ((update_subrange_vec_dec spsr (( 3 :: int)::ii) (( 2 :: int)::ii)(ProcState_EL w__24) :: 32 Word.word)) in + read_reg PSTATE_ref \ (\ (w__25 :: ProcState) . + (let (spsr :: 32 bits) = + ((update_subrange_vec_dec spsr (( 0 :: int)::ii) (( 0 :: int)::ii)(ProcState_SP w__25) :: 32 Word.word)) in + return spsr)))))))))))))))))))))))))))))" + + +(*val FPZero : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +definition FPZero :: " int \(1)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPZero (N__tv :: int) sign = ( + (let l__299 = N__tv in + if (((l__299 = (( 16 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 5 bits) = ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__299 = (( 32 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 8 bits) = ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__299 = (( 64 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 11 bits) = ((Zeros__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (frac :: 52 bits) = ((Zeros__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val ExceptionSyndrome : Exception -> M ExceptionRecord*) + +definition ExceptionSyndrome :: " Exception \((register_value),(ExceptionRecord),(exception))monad " where + " ExceptionSyndrome typ1 = ( + undefined_ExceptionRecord () \ (\ (r :: ExceptionRecord) . + (let (r :: ExceptionRecord) = ((r (| ExceptionRecord_typ := typ1 |))) in + (let (r :: ExceptionRecord) = + ((r (| ExceptionRecord_syndrome := ((Zeros__1 (( 25 :: int)::ii) () :: 25 Word.word))|))) in + (let (r :: ExceptionRecord) = + ((r (| ExceptionRecord_vaddress := ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word))|))) in + (let (r :: ExceptionRecord) = ((r (| ExceptionRecord_ipavalid := False |))) in + (let (r :: ExceptionRecord) = + ((r (| ExceptionRecord_ipaddress := ((Zeros__1 (( 52 :: int)::ii) () :: 52 Word.word))|))) in + return r)))))))" + + +(*val ConstrainUnpredictableBits : forall 'width . Size 'width => integer -> Unpredictable -> M (Constraint * mword 'width)*) + +definition ConstrainUnpredictableBits :: " int \ Unpredictable \((register_value),(Constraint*('width::len)Word.word),(exception))monad " where + " ConstrainUnpredictableBits (width__tv :: int) which = ( + (let (c :: Constraint) = (ConstrainUnpredictable which) in + if (((c = Constraint_UNKNOWN))) then + return (c, (Zeros__0 ((make_the_value width__tv :: ( 'width::len)itself)) :: ( 'width::len)Word.word)) + else + (undefined_bitvector width__tv :: (( 'width::len)Word.word) M) \ (\ (w__0 :: ( 'width::len)Word.word) . + return (c, w__0))))" + + +(*val AArch64_SysInstrWithResult : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*) + +definition AArch64_SysInstrWithResult :: " int \ int \ int \ int \ int \((register_value),((64)Word.word),(exception))monad " where + " AArch64_SysInstrWithResult op0 op1 crn crm op2 = ( + assert_exp False (''FALSE'') \ + return ((Zeros__0 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: 64 Word.word)))" + + +(*val AArch64_PhysicalSErrorSyndrome : bool -> M (mword ty25)*) + +definition AArch64_PhysicalSErrorSyndrome :: " bool \((register_value),((25)Word.word),(exception))monad " where + " AArch64_PhysicalSErrorSyndrome implicit_esb = ( + assert_exp False (''FALSE'') \ + return ((Zeros__0 ((make_the_value (( 25 :: int)::ii) :: 25 itself)) :: 25 Word.word)))" + + +(*val AArch32_PhysicalSErrorSyndrome : unit -> M AArch32_SErrorSyndrome*) + +definition AArch32_PhysicalSErrorSyndrome :: " unit \((register_value),(AArch32_SErrorSyndrome),(exception))monad " where + " AArch32_PhysicalSErrorSyndrome _ = ( + (assert_exp False (''FALSE'') \ + undefined_AArch32_SErrorSyndrome () ) \ (\ (r :: AArch32_SErrorSyndrome) . + (let (r :: AArch32_SErrorSyndrome) = + ((r (| + AArch32_SErrorSyndrome_AET := + ((Zeros__0 ((make_the_value (( 2 :: int)::ii) :: 2 itself)) :: 2 Word.word))|))) in + (let (r :: AArch32_SErrorSyndrome) = + ((r (| + AArch32_SErrorSyndrome_ExT := + ((Zeros__0 ((make_the_value (( 1 :: int)::ii) :: 1 itself)) :: 1 Word.word))|))) in + return r))))" + + +(*val VFPExpandImm : forall 'N . Size 'N => integer -> mword ty8 -> M (mword 'N)*) + +definition VFPExpandImm :: " int \(8)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " VFPExpandImm (N__tv :: int) imm8 = ( + (let l__296 = N__tv in + if (((l__296 = (( 16 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in + (let (exp :: 5 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) + (((( 5 :: int)::ii) - (( 3 :: int)::ii))) + :: 2 Word.word)) + :: 3 Word.word)) ((subrange_vec_dec imm8 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) + :: 5 Word.word)) in + (let (frac :: 10 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 6 itself)) :: 6 Word.word)) + :: 10 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else if (((l__296 = (( 32 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in + (let (exp :: 8 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) + (((( 8 :: int)::ii) - (( 3 :: int)::ii))) + :: 5 Word.word)) + :: 6 Word.word)) ((subrange_vec_dec imm8 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) + :: 8 Word.word)) in + (let (frac :: 23 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 19 itself)) :: 19 Word.word)) + :: 23 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else if (((l__296 = (( 64 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in + (let (exp :: 11 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) + (((( 11 :: int)::ii) - (( 3 :: int)::ii))) + :: 8 Word.word)) + :: 9 Word.word)) ((subrange_vec_dec imm8 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) + :: 11 Word.word)) in + (let (frac :: 52 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 48 itself)) :: 48 Word.word)) + :: 52 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val SignExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*) + +(*val SignExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +definition SignExtend__0 :: "('M::len)Word.word \('N::len)itself \((register_value),(('N::len)Word.word),(exception))monad " where + " SignExtend__0 x N = ( + (let N = (size_itself_int N) in + assert_exp ((N \ ((int (size x))))) ('''') \ return ((extsv N x :: ( 'N::len)Word.word))))" + + +definition SignExtend__1 :: " int \('M::len)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " SignExtend__1 (N__tv :: int) x = ( + (SignExtend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M))" + + +(*val Extend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> bool -> M (mword 'N)*) + +(*val Extend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> bool -> M (mword 'N)*) + +definition Extend__0 :: "('M::len)Word.word \('N::len)itself \ bool \((register_value),(('N::len)Word.word),(exception))monad " where + " Extend__0 x N unsigned = ( + (let N = (size_itself_int N) in + if unsigned then (ZeroExtend__0 x ((make_the_value N :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M) + else (SignExtend__0 x ((make_the_value N :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M)))" + + +definition Extend__1 :: " int \('M::len)Word.word \ bool \((register_value),(('N::len)Word.word),(exception))monad " where + " Extend__1 (N__tv :: int) x unsigned = ( + (Extend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) unsigned :: (( 'N::len)Word.word) M))" + + +(*val ASR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +definition ASR_C :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where + " ASR_C x shift = ( + assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \ + ((let (result :: 'N bits) = ((arith_shiftr x shift :: ( 'N::len)Word.word)) in + (let (carry_out :: 1 bits) = + (if ((shift > ((int (size result))))) then + (vec_of_bits [access_vec_dec x ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word) + else (vec_of_bits [access_vec_dec x ((shift - (( 1 :: int)::ii)))] :: 1 Word.word)) in + return (result, carry_out)))))" + + +(*val ASR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +definition ASR :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " ASR x shift = ( + (assert_exp ((shift \ (( 0 :: int)::ii))) (''(shift >= 0)'') \ + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (anon10 :: 1 bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if (((shift = (( 0 :: int)::ii)))) then return x + else + (ASR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (result :: 'N bits) = tup__0 in + (let (anon10 :: 1 bits) = tup__1 in + return result)))))))" + + +(*val Ones__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) + +(*val Ones__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*) + +definition Ones__0 :: "('N::len)itself \('N::len)Word.word " where + " Ones__0 N = ( + (let N = (size_itself_int N) in + (replicate_bits (vec_of_bits [B1] :: 1 Word.word) N :: ( 'N::len)Word.word)))" + + +definition Ones__1 :: " int \ unit \('N::len)Word.word " where + " Ones__1 (N__tv :: int) _ = ( (Ones__0 ((make_the_value N__tv :: ( 'N::len)itself)) :: ( 'N::len)Word.word))" + + +(*val IsOnes : forall 'N . Size 'N => mword 'N -> bool*) + +definition IsOnes :: "('N::len)Word.word \ bool " where + " IsOnes x = ( (x = ((Ones__0 ((make_the_value ((int (size x))) :: ( 'N::len)itself)) :: ( 'N::len)Word.word))))" + + +(*val FPMaxNormal : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +definition FPMaxNormal :: " int \(1)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMaxNormal (N__tv :: int) sign = ( + (let l__293 = N__tv in + if (((l__293 = (( 16 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 5 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 5 :: int)::ii) - (( 1 :: int)::ii))) :: 4 itself)) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) in + (let (frac :: 10 bits) = ((Ones__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__293 = (( 32 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 8 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 8 :: int)::ii) - (( 1 :: int)::ii))) :: 7 itself)) :: 7 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 8 Word.word)) in + (let (frac :: 23 bits) = ((Ones__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__293 = (( 64 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 11 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 11 :: int)::ii) - (( 1 :: int)::ii))) :: 10 itself)) :: 10 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 11 Word.word)) in + (let (frac :: 52 bits) = ((Ones__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val FPInfinity : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +definition FPInfinity :: " int \(1)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPInfinity (N__tv :: int) sign = ( + (let l__290 = N__tv in + if (((l__290 = (( 16 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__290 = (( 32 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else if (((l__290 = (( 64 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (frac :: 52 bits) = ((Zeros__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in + return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word)))))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val FPDefaultNaN : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +definition FPDefaultNaN :: " int \ unit \((register_value),(('N::len)Word.word),(exception))monad " where + " FPDefaultNaN (N__tv :: int) _ = ( + (let l__287 = N__tv in + if (((l__287 = (( 16 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (frac :: 10 bits) = + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 9 itself)) :: 9 Word.word)) + :: 10 Word.word)) in + return ((Word.ucast + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 6 Word.word)) frac + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else if (((l__287 = (( 32 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (frac :: 23 bits) = + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 22 itself)) :: 22 Word.word)) + :: 23 Word.word)) in + return ((Word.ucast + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 9 Word.word)) frac + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else if (((l__287 = (( 64 :: int)::ii)))) then + assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (frac :: 52 bits) = + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 51 itself)) :: 51 Word.word)) + :: 52 Word.word)) in + return ((Word.ucast + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 12 Word.word)) frac + :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))) + else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \ exit0 () ))" + + +(*val FPConvertNaN : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> M (mword 'M)*) + +definition FPConvertNaN :: " int \('N::len)Word.word \((register_value),(('M::len)Word.word),(exception))monad " where + " FPConvertNaN (M__tv :: int) op1 = ( + ((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + assert_exp ((((((M__tv = (( 16 :: int)::ii)))) \ ((((((M__tv = (( 32 :: int)::ii)))) \ (((M__tv = (( 64 :: int)::ii)))))))))) (''((M == 16) || ((M == 32) || (M == 64)))'')) \ + (undefined_bitvector M__tv :: (( 'M::len)Word.word) M)) \ (\ (result :: 'M bits) . + (undefined_bitvector (( 51 :: int)::ii) :: ( 51 Word.word) M) \ (\ (frac :: 51 bits) . + (let (sign :: 1 bits) = + ((vec_of_bits [access_vec_dec op1 ((((int (size op1))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in + (let l__281 = (int (size op1)) in + (let (frac :: 51 bits) = + (if (((l__281 = (( 64 :: int)::ii)))) then + (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in + (slice0 op1 (( 0 :: int)::ii) (( 51 :: int)::ii) :: 51 Word.word)) + else if (((l__281 = (( 32 :: int)::ii)))) then + (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in + (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + ((Zeros__0 ((make_the_value (( 29 :: int)::ii) :: 29 itself)) :: 29 Word.word)) + :: 51 Word.word)) + else + (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in + (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + ((Zeros__0 ((make_the_value (( 42 :: int)::ii) :: 42 itself)) :: 42 Word.word)) + :: 51 Word.word))) in + (let l__284 = (int (size result)) in + (let (result :: 'M bits) = + (if (((l__284 = (( 64 :: int)::ii)))) then + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 52 :: int)::ii))) )) :: 12 Word.word)) + :: 13 Word.word)) frac + :: ( 'M::len)Word.word) + else if (((l__284 = (( 32 :: int)::ii)))) then + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 23 :: int)::ii))) )) :: 9 Word.word)) + :: 10 Word.word)) ((slice0 frac (( 29 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + :: ( 'M::len)Word.word) + else + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value ((l__284 - (( 10 :: int)::ii))) )) :: 6 Word.word)) + :: 7 Word.word)) ((slice0 frac (( 42 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + :: ( 'M::len)Word.word)) in + return result))))))))" + + +(*val ExcVectorBase : unit -> M (mword ty32)*) + +definition ExcVectorBase :: " unit \((register_value),((32)Word.word),(exception))monad " where + " ExcVectorBase _ = ( + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__0 (( 13 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + return ((concat_vec ((Ones__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + :: 32 Word.word)) + else + (read_reg VBAR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((concat_vec ((slice0 w__1 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) + :: 32 Word.word)))))" + + +(*val PACSub : mword ty64 -> M (mword ty64)*) + +definition PACSub :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " PACSub Tinput = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (Toutput :: 64 bits) . + (let (Toutput :: 64 bits) = + (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput + (\ i Toutput . + (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in + if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word) + :: 64 Word.word)))) in + return Toutput)))" + + +(*val PACMult : mword ty64 -> M (mword ty64)*) + +definition PACMult :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " PACMult Sinput = ( + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (t0 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (t1 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (t2 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (t3 :: 4 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (Soutput :: 64 bits) . + (foreachM (index_list (( 0 :: int)::ii) (( 3 :: int)::ii) (( 1 :: int)::ii)) Soutput + (\ i Soutput . + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__0 :: 4 Word.word) . + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 2 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__1 :: 4 Word.word) . + (let t0 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) ((xor_vec w__0 w__1 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__2 :: 4 Word.word) . + (let t0 = + ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) + ((xor_vec ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__2 :: 4 Word.word)) + :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__3 :: 4 Word.word) . + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__4 :: 4 Word.word) . + (let t1 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) ((xor_vec w__3 w__4 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__5 :: 4 Word.word) . + (let t1 = + ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) + ((xor_vec ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__5 :: 4 Word.word)) + :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 2 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__6 :: 4 Word.word) . + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__7 :: 4 Word.word) . + (let t2 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) ((xor_vec w__6 w__7 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__8 :: 4 Word.word) . + (let t2 = + ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) + ((xor_vec ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__8 :: 4 Word.word)) + :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__9 :: 4 Word.word) . + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 2 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__10 :: 4 Word.word) . + (let t3 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) ((xor_vec w__9 w__10 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (( 1 :: int)::ii) + :: ( 4 Word.word) M) \ (\ (w__11 :: 4 Word.word) . + (let (t3 :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) + ((xor_vec ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__11 :: 4 Word.word)) + :: 4 Word.word)) in + (let (Soutput :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * i)) + ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (Soutput :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) + ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (Soutput :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) + ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + (let (Soutput :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) + ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word)) in + return Soutput))))))))))))))))))))))))))))))))" + + +(*val PACInvSub : mword ty64 -> M (mword ty64)*) + +definition PACInvSub :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " PACInvSub Tinput = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (Toutput :: 64 bits) . + (let (Toutput :: 64 bits) = + (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput + (\ i Toutput . + (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in + if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word) + :: 64 Word.word) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word) + :: 64 Word.word) + else + (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) + :: 64 Word.word)))) in + return Toutput)))" + + +(*val ComputePAC : mword ty64 -> mword ty64 -> mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition ComputePAC :: "(64)Word.word \(64)Word.word \(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " ComputePAC data modifier key0 key1 = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (workingval :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (runningmod :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (roundkey :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (modk0 :: 64 bits) . + (hex_slice (''0xC0AC29B7C97C50DD'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (Alpha :: 64 bits) . + read_reg RC_ref \ (\ (w__0 :: ( 64 Word.word) list) . + (hex_slice (''0x0'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (write_reg RC_ref ((update_list_dec w__0 (( 0 :: int)::ii) w__1 :: ( 64 Word.word) list)) \ + read_reg RC_ref) \ (\ (w__2 :: ( 64 Word.word) list) . + (hex_slice (''0x13198A2E03707344'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (write_reg RC_ref ((update_list_dec w__2 (( 1 :: int)::ii) w__3 :: ( 64 Word.word) list)) \ + read_reg RC_ref) \ (\ (w__4 :: ( 64 Word.word) list) . + (hex_slice (''0xA493822299F31D0'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . + (write_reg RC_ref ((update_list_dec w__4 (( 2 :: int)::ii) w__5 :: ( 64 Word.word) list)) \ + read_reg RC_ref) \ (\ (w__6 :: ( 64 Word.word) list) . + (hex_slice (''0x82EFA98EC4E6C89'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__7 :: 64 Word.word) . + (write_reg RC_ref ((update_list_dec w__6 (( 3 :: int)::ii) w__7 :: ( 64 Word.word) list)) \ + read_reg RC_ref) \ (\ (w__8 :: ( 64 Word.word) list) . + (hex_slice (''0x452821E638D01377'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__9 :: 64 Word.word) . + write_reg RC_ref ((update_list_dec w__8 (( 4 :: int)::ii) w__9 :: ( 64 Word.word) list)) \ + ((let modk0 = + ((concat_vec + ((concat_vec (vec_of_bits [access_vec_dec key0 (( 0 :: int)::ii)] :: 1 Word.word) + ((slice0 key0 (( 2 :: int)::ii) (( 62 :: int)::ii) :: 62 Word.word)) + :: 63 Word.word)) + ((xor_vec (vec_of_bits [access_vec_dec key0 (( 63 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec key0 (( 1 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 64 Word.word)) in + (let runningmod = modifier in + (let workingval = ((xor_vec data key0 :: 64 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) (roundkey, runningmod, workingval) + (\ i varstup . (let (roundkey, runningmod, workingval) = varstup in + (let roundkey = ((xor_vec key1 runningmod :: 64 Word.word)) in + (let workingval = ((xor_vec workingval roundkey :: 64 Word.word)) in + read_reg RC_ref \ (\ (w__10 :: ( 64 bits) list) . + (let workingval = ((xor_vec workingval ((access_list_dec w__10 i :: 64 Word.word)) :: 64 Word.word)) in + (if ((i > (( 0 :: int)::ii))) then + (PACCellShuffle workingval :: ( 64 Word.word) M) \ (\ (w__11 :: 64 bits) . + (let workingval = w__11 in + (PACMult workingval :: ( 64 Word.word) M))) + else return workingval) \ (\ (workingval :: 64 bits) . + (PACSub workingval :: ( 64 Word.word) M) \ (\ (w__13 :: 64 bits) . + (let workingval = w__13 in + (TweakShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \ (\ (w__14 :: 64 + bits) . + (let (runningmod :: 64 bits) = w__14 in + return (roundkey, runningmod, workingval))))))))))))) \ (\ varstup . (let ((roundkey :: 64 bits), (runningmod :: 64 + bits), (workingval :: 64 bits)) = varstup in + (let roundkey = ((xor_vec modk0 runningmod :: 64 Word.word)) in + (let workingval = ((xor_vec workingval roundkey :: 64 Word.word)) in + (PACCellShuffle workingval :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + (let workingval = w__15 in + (PACMult workingval :: ( 64 Word.word) M) \ (\ (w__16 :: 64 bits) . + (let workingval = w__16 in + (PACSub workingval :: ( 64 Word.word) M) \ (\ (w__17 :: 64 bits) . + (let workingval = w__17 in + (PACCellShuffle workingval :: ( 64 Word.word) M) \ (\ (w__18 :: 64 bits) . + (let workingval = w__18 in + (PACMult workingval :: ( 64 Word.word) M) \ (\ (w__19 :: 64 bits) . + (let workingval = w__19 in + (let workingval = ((xor_vec key1 workingval :: 64 Word.word)) in + (PACCellInvShuffle workingval :: ( 64 Word.word) M) \ (\ (w__20 :: 64 bits) . + (let workingval = w__20 in + (PACInvSub workingval :: ( 64 Word.word) M) \ (\ (w__21 :: 64 bits) . + (let workingval = w__21 in + (PACMult workingval :: ( 64 Word.word) M) \ (\ (w__22 :: 64 bits) . + (let workingval = w__22 in + (PACCellInvShuffle workingval :: ( 64 Word.word) M) \ (\ (w__23 :: 64 bits) . + (let workingval = w__23 in + (let workingval = ((xor_vec workingval key0 :: 64 Word.word)) in + (let workingval = ((xor_vec workingval runningmod :: 64 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) workingval + (\ i workingval . + (PACInvSub workingval :: ( 64 Word.word) M) \ (\ (w__24 :: 64 bits) . + (let workingval = w__24 in + (if ((i < (( 4 :: int)::ii))) then + (PACMult workingval :: ( 64 Word.word) M) \ (\ (w__25 :: 64 bits) . + (let workingval = w__25 in + (PACCellInvShuffle workingval :: ( 64 Word.word) M))) + else return workingval) \ (\ (workingval :: 64 bits) . + (TweakInvShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \ (\ (w__27 :: 64 + bits) . + (let runningmod = w__27 in + (let roundkey = ((xor_vec key1 runningmod :: 64 Word.word)) in + read_reg RC_ref \ (\ (w__28 :: ( 64 bits) list) . + (let (workingval :: 64 bits) = + ((xor_vec workingval ((access_list_dec w__28 (((( 4 :: int)::ii) - i)) :: 64 Word.word)) + :: 64 Word.word)) in + (let (workingval :: 64 bits) = ((xor_vec workingval roundkey :: 64 Word.word)) in + (let (workingval :: 64 bits) = ((xor_vec workingval Alpha :: 64 Word.word)) in + return workingval)))))))))))) \ (\ (workingval :: 64 bits) . + (let (workingval :: 64 bits) = ((xor_vec workingval modk0 :: 64 Word.word)) in + return workingval)))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val Align__0 : ii -> ii -> ii*) + +(*val Align__1 : forall 'N . Size 'N => mword 'N -> ii -> mword 'N*) + +definition Align__0 :: " int \ int \ int " where + " Align__0 x y = ( y * ((x div y)))" + + +definition Align__1 :: "('N::len)Word.word \ int \('N::len)Word.word " where + " Align__1 x y = ( + (GetSlice_int ((make_the_value ((int (size x))) :: ( 'N::len)itself)) ((Align__0 ((Word.uint x)) y)) (( 0 :: int)::ii) + :: ( 'N::len)Word.word))" + + +(*val aset__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> mword 'p8_times_size_ -> M unit*) + +definition aset__Mem :: " AddressDescriptor \ int \ AccessDescriptor \('p8_times_size_::len)Word.word \((register_value),(unit),(exception))monad " where + " aset__Mem desc size1 accdesc value_name = ( + assert_exp ((((((size1 = (( 1 :: int)::ii)))) \ ((((((size1 = (( 2 :: int)::ii)))) \ ((((((size1 = (( 4 :: int)::ii)))) \ ((((((size1 = (( 8 :: int)::ii)))) \ (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \ + ((let (address :: 52 bits) = ((FullAddress_physicaladdress (AddressDescriptor_paddress desc))) in + (assert_exp (((address = ((Align__1 address size1 :: 52 Word.word))))) (''(address == Align(address, size))'') \ + (hex_slice (''0x13000000'') (( 52 :: int)::ii) (( 0 :: int)::ii) :: ( 52 Word.word) M)) \ (\ (w__0 :: 52 Word.word) . + if (((address = w__0))) then + if (((((Word.uint value_name)) = (( 4 :: int)::ii)))) then + (let (_ :: unit) = (prerr_endline ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in + exit0 () ) + else return ((putchar ((Word.uint ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))))) + else + (read_reg Memory_ref :: ( 52 Word.word) M) \ (\ (w__1 :: 52 Word.word) . + write_ram (( 52 :: int)::ii) size1 w__1 address value_name)))))" + + +(*val aget__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> M (mword 'p8_times_size_)*) + +definition aget__Mem :: " AddressDescriptor \ int \ AccessDescriptor \((register_value),(('p8_times_size_::len)Word.word),(exception))monad " where + " aget__Mem desc size1 accdesc = ( + assert_exp ((((((size1 = (( 1 :: int)::ii)))) \ ((((((size1 = (( 2 :: int)::ii)))) \ ((((((size1 = (( 4 :: int)::ii)))) \ ((((((size1 = (( 8 :: int)::ii)))) \ (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \ + ((let (address :: 52 bits) = ((FullAddress_physicaladdress (AddressDescriptor_paddress desc))) in + (assert_exp (((address = ((Align__1 address size1 :: 52 Word.word))))) (''(address == Align(address, size))'') \ + (read_reg Memory_ref :: ( 52 Word.word) M)) \ (\ (w__0 :: 52 Word.word) . + (read_ram (( 52 :: int)::ii) size1 w__0 address :: (( 'p8_times_size_::len)Word.word) M)))))" + + +(*val aset_X : forall 'width . Size 'width => ii -> mword 'width -> M unit*) + +definition aset_X :: " int \('width::len)Word.word \((register_value),(unit),(exception))monad " where + " aset_X n value_name = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \ (((((int (size value_name))) = (( 64 :: int)::ii))))))) (''((width == 32) || (width == 64))'')) \ + (if (((n \ (( 31 :: int)::ii)))) then + read_reg R_ref \ (\ (w__0 :: ( 64 Word.word) list) . + (ZeroExtend__0 value_name ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + write_reg R_ref ((update_list_dec w__0 n w__1 :: ( 64 Word.word) list)))) + else return () ))" + + +(*val aarch64_integer_arithmetic_address_pcrel : ii -> mword ty64 -> bool -> M unit*) + +definition aarch64_integer_arithmetic_address_pcrel :: " int \(64)Word.word \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_address_pcrel d imm page = ( + (aget_PC () :: ( 64 Word.word) M) \ (\ (base :: 64 bits) . + (let (base :: 64 bits) = + (if page then + (set_slice0 (( 64 :: int)::ii) (( 12 :: int)::ii) base (( 0 :: int)::ii) + ((Zeros__0 ((make_the_value (( 12 :: int)::ii) :: 12 itself)) :: 12 Word.word)) + :: 64 Word.word) + else base) in + aset_X d ((add_vec base imm :: 64 Word.word)))))" + + +(*val integer_arithmetic_address_pcrel_decode : mword ty1 -> mword ty2 -> mword ty19 -> mword ty5 -> M unit*) + +definition integer_arithmetic_address_pcrel_decode :: "(1)Word.word \(2)Word.word \(19)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_address_pcrel_decode op1 immlo immhi Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (page :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (imm :: 64 bits) . + (if page then + (SignExtend__0 + ((concat_vec ((concat_vec immhi immlo :: 21 Word.word)) + ((Zeros__0 ((make_the_value (( 12 :: int)::ii) :: 12 itself)) :: 12 Word.word)) + :: 33 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) + else + (SignExtend__0 ((concat_vec immhi immlo :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M)) \ (\ (imm :: 64 bits) . + aarch64_integer_arithmetic_address_pcrel d imm page))))))" + + +(*val AArch64_ResetGeneralRegisters : unit -> M unit*) + +definition AArch64_ResetGeneralRegisters :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_ResetGeneralRegisters _ = ( + (foreachM (index_list (( 0 :: int)::ii) (( 30 :: int)::ii) (( 1 :: int)::ii)) () + (\ i unit_var . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . aset_X i w__0))))" + + +(*val aset_ELR__0 : mword ty2 -> mword ty64 -> M unit*) + +(*val aset_ELR__1 : mword ty64 -> M unit*) + +definition aset_ELR__0 :: "(2)Word.word \(64)Word.word \((register_value),(unit),(exception))monad " where + " aset_ELR__0 el value_name = ( + (let (r :: 64 bits) = value_name in + (let pat0 = el in + if (((pat0 = EL1))) then write_reg ELR_EL1_ref r + else if (((pat0 = EL2))) then write_reg ELR_EL2_ref r + else if (((pat0 = EL3))) then write_reg ELR_EL3_ref r + else Unreachable () )))" + + +definition aset_ELR__1 :: "(64)Word.word \((register_value),(unit),(exception))monad " where + " aset_ELR__1 value_name = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((ProcState_EL w__0) \ EL0))) ('''') \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . aset_ELR__0(ProcState_EL w__1) value_name)))" + + +(*val aget_X : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*) + +definition aget_X :: " int \ int \((register_value),(('width::len)Word.word),(exception))monad " where + " aget_X (width__tv :: int) n = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \ + assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \ ((((((width__tv = (( 16 :: int)::ii)))) \ ((((((width__tv = (( 32 :: int)::ii)))) \ (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'')) \ + (if (((n \ (( 31 :: int)::ii)))) then + read_reg R_ref \ (\ (w__0 :: ( 64 bits) list) . + return ((slice0 ((access_list_dec w__0 n :: 64 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + else return ((Zeros__0 ((make_the_value width__tv :: ( 'width::len)itself)) :: ( 'width::len)Word.word))))" + + +(*val aarch64_system_sysops : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_system_sysops :: " bool \ int \ int \ int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t = ( + if has_result then + (AArch64_SysInstrWithResult sys_op0 sys_op1 sys_crn sys_crm sys_op2 :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + aset_X t w__0) + else + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + AArch64_SysInstr sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1))" + + +(*val aarch64_system_register_system : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_system_register_system :: " bool \ int \ int \ int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t = ( + if read then + (AArch64_SysRegRead sys_op0 sys_op1 sys_crn sys_crm sys_op2 :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + aset_X t w__0) + else + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + AArch64_SysRegWrite sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1))" + + +(*val aarch64_integer_insext_insert_movewide : ii -> ii -> mword ty16 -> MoveWideOp -> ii -> M unit*) + +definition aarch64_integer_insext_insert_movewide :: " int \ int \(16)Word.word \ MoveWideOp \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_insext_insert_movewide d l__276 imm opcode pos = ( + if (((l__276 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (if (((opcode = MoveWideOp_K))) then (aget_X (( 8 :: int)::ii) d :: ( 8 Word.word) M) + else + (let (result :: 8 bits) = ((Zeros__1 (( 8 :: int)::ii) () :: 8 Word.word)) in + return result)) \ (\ (result :: 8 bits) . + (let result = ((set_slice0 (( 8 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 8 Word.word)) in + (let (result :: 8 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result :: 8 Word.word) + else result) in + aset_X d result))))) + else if (((l__276 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (if (((opcode = MoveWideOp_K))) then (aget_X (( 16 :: int)::ii) d :: ( 16 Word.word) M) + else + (let (result :: 16 bits) = ((Zeros__1 (( 16 :: int)::ii) () :: 16 Word.word)) in + return result)) \ (\ (result :: 16 bits) . + (let result = ((set_slice0 (( 16 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 16 Word.word)) in + (let (result :: 16 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result :: 16 Word.word) + else result) in + aset_X d result))))) + else if (((l__276 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (if (((opcode = MoveWideOp_K))) then (aget_X (( 32 :: int)::ii) d :: ( 32 Word.word) M) + else + (let (result :: 32 bits) = ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) in + return result)) \ (\ (result :: 32 bits) . + (let result = ((set_slice0 (( 32 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 32 Word.word)) in + (let (result :: 32 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result :: 32 Word.word) + else result) in + aset_X d result))))) + else if (((l__276 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (if (((opcode = MoveWideOp_K))) then (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) + else + (let (result :: 64 bits) = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in + return result)) \ (\ (result :: 64 bits) . + (let result = ((set_slice0 (( 64 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 64 Word.word)) in + (let (result :: 64 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result :: 64 Word.word) + else result) in + aset_X d result))))) + else if (((l__276 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (if (((opcode = MoveWideOp_K))) then (aget_X (( 128 :: int)::ii) d :: ( 128 Word.word) M) + else + (let (result :: 128 bits) = ((Zeros__1 (( 128 :: int)::ii) () :: 128 Word.word)) in + return result)) \ (\ (result :: 128 bits) . + (let result = ((set_slice0 (( 128 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 128 Word.word)) in + (let (result :: 128 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result :: 128 Word.word) + else result) in + aset_X d result))))) + else + (let dbytes = (ex_int ((l__276 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_integer_insext_extract_immediate : ii -> ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_integer_insext_extract_immediate :: " int \ int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_insext_extract_immediate d l__271 lsb1 m n = ( + if (((l__271 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (let (concat1 :: 16 bits) = ((concat_vec operand1 operand2 :: 16 Word.word)) in + (let result = ((slice0 concat1 lsb1 (( 8 :: int)::ii) :: 8 Word.word)) in + aset_X d result)))))) + else if (((l__271 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (let (concat1 :: 32 bits) = ((concat_vec operand1 operand2 :: 32 Word.word)) in + (let result = ((slice0 concat1 lsb1 (( 16 :: int)::ii) :: 16 Word.word)) in + aset_X d result)))))) + else if (((l__271 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (let (concat1 :: 64 bits) = ((concat_vec operand1 operand2 :: 64 Word.word)) in + (let result = ((slice0 concat1 lsb1 (( 32 :: int)::ii) :: 32 Word.word)) in + aset_X d result)))))) + else if (((l__271 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (let (concat1 :: 128 bits) = ((concat_vec operand1 operand2 :: 128 Word.word)) in + (let result = ((slice0 concat1 lsb1 (( 64 :: int)::ii) :: 64 Word.word)) in + aset_X d result)))))) + else if (((l__271 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (let (concat1 :: 256 bits) = ((concat_vec operand1 operand2 :: 256 Word.word)) in + (let result = ((slice0 concat1 lsb1 (( 128 :: int)::ii) :: 128 Word.word)) in + aset_X d result)))))) + else + (let dbytes = (ex_int ((l__271 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_integer_arithmetic_rev : ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_integer_arithmetic_rev :: " int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_rev container_size d l__266 n = ( + if (((l__266 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (result :: 8 bits) . + (let (containers :: ii) = ((( 8 :: int)::ii) div container_size) in + (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in + (let (index1 :: ii) = ((( 0 :: int)::ii)) in + undefined_int () \ (\ (rev_index :: ii) . + (let (result :: 8 bits) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ c result . + (let (rev_index :: ii) = + (((ex_int index1)) + + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ e result . + (let (result :: 8 bits) = + ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 8 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + result)))))))) in + aset_X d result)))))))) + else if (((l__266 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (result :: 16 bits) . + (let (containers :: ii) = ((( 16 :: int)::ii) div container_size) in + (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in + (let (index1 :: ii) = ((( 0 :: int)::ii)) in + undefined_int () \ (\ (rev_index :: ii) . + (let (result :: 16 bits) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ c result . + (let (rev_index :: ii) = + (((ex_int index1)) + + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ e result . + (let (result :: 16 bits) = + ((set_slice0 (( 16 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + result)))))))) in + aset_X d result)))))))) + else if (((l__266 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + (let (containers :: ii) = ((( 32 :: int)::ii) div container_size) in + (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in + (let (index1 :: ii) = ((( 0 :: int)::ii)) in + undefined_int () \ (\ (rev_index :: ii) . + (let (result :: 32 bits) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ c result . + (let (rev_index :: ii) = + (((ex_int index1)) + + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ e result . + (let (result :: 32 bits) = + ((set_slice0 (( 32 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + result)))))))) in + aset_X d result)))))))) + else if (((l__266 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (let (containers :: ii) = ((( 64 :: int)::ii) div container_size) in + (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in + (let (index1 :: ii) = ((( 0 :: int)::ii)) in + undefined_int () \ (\ (rev_index :: ii) . + (let (result :: 64 bits) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ c result . + (let (rev_index :: ii) = + (((ex_int index1)) + + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ e result . + (let (result :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + result)))))))) in + aset_X d result)))))))) + else if (((l__266 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (result :: 128 bits) . + (let (containers :: ii) = ((( 128 :: int)::ii) div container_size) in + (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in + (let (index1 :: ii) = ((( 0 :: int)::ii)) in + undefined_int () \ (\ (rev_index :: ii) . + (let (result :: 128 bits) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ c result . + (let (rev_index :: ii) = + (((ex_int index1)) + + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ e result . + (let (result :: 128 bits) = + ((set_slice0 (( 128 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 128 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + result)))))))) in + aset_X d result)))))))) + else + (let dbytes = (ex_int ((l__266 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_integer_arithmetic_rbit : ii -> ii -> ii -> M unit*) + +definition aarch64_integer_arithmetic_rbit :: " int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_rbit d l__261 n = ( + if (((l__261 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (result :: 8 bits) . + (let (result :: 8 bits) = + (foreach (index_list (( 0 :: int)::ii) (((( 8 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 (( 8 :: int)::ii) (( 1 :: int)::ii) result (((((( 8 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) + :: 8 Word.word))) in + aset_X d result)))) + else if (((l__261 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (result :: 16 bits) . + (let (result :: 16 bits) = + (foreach (index_list (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 (( 16 :: int)::ii) (( 1 :: int)::ii) result (((((( 16 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) + :: 16 Word.word))) in + aset_X d result)))) + else if (((l__261 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + (let (result :: 32 bits) = + (foreach (index_list (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) result (((((( 32 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) + :: 32 Word.word))) in + aset_X d result)))) + else if (((l__261 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (let (result :: 64 bits) = + (foreach (index_list (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) result (((((( 64 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) + :: 64 Word.word))) in + aset_X d result)))) + else if (((l__261 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (result :: 128 bits) . + (let (result :: 128 bits) = + (foreach (index_list (( 0 :: int)::ii) (((( 128 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result + (\ i result . + (set_slice0 (( 128 :: int)::ii) (( 1 :: int)::ii) result (((((( 128 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) + :: 128 Word.word))) in + aset_X d result)))) + else + (let dbytes = (ex_int ((l__261 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_arithmetic_rbit_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_rbit_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_rbit_decode sf S opcode2 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + aarch64_integer_arithmetic_rbit d datasize n)))))" + + +(*val aarch64_integer_arithmetic_mul_widening_64128hi : ii -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_mul_widening_64128hi d l__256 m n unsigned = ( + if (((l__256 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (let (result :: ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) + else if (((l__256 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (let (result :: ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) + else if (((l__256 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (let (result :: ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) + else if (((l__256 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (let (result :: ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) + else if (((l__256 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (let (result :: ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) + else + (let dbytes = (ex_int ((l__256 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_arithmetic_mul_widening_64128hi_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_mul_widening_64128hi_decode :: "(1)Word.word \(2)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_mul_widening_64128hi_decode sf op54 U Rm o0 Ra Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (a :: ii) = (Word.uint Ra) in + (let (destsize :: int) = ((( 64 :: int)::ii)) in + (let (datasize :: ii) = destsize in + (let (unsigned :: bool) = (U = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_arithmetic_mul_widening_64128hi d datasize m n unsigned)))))))))" + + +(*val aarch64_integer_arithmetic_mul_widening_3264 : ii -> ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \ int \ int \ int \ int \ int \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_mul_widening_3264 a d l__229 l__230 m n sub_op unsigned = ( + if ((((((l__229 = (( 8 :: int)::ii)))) \ (((l__230 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if ((((((l__229 = (( 8 :: int)::ii)))) \ (((l__230 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__229 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__229 = (( 16 :: int)::ii)))) \ (((l__230 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if ((((((l__229 = (( 16 :: int)::ii)))) \ (((l__230 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__229 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__229 = (( 32 :: int)::ii)))) \ (((l__230 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if ((((((l__229 = (( 32 :: int)::ii)))) \ (((l__230 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__229 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__229 = (( 64 :: int)::ii)))) \ (((l__230 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if ((((((l__229 = (( 64 :: int)::ii)))) \ (((l__230 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__229 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__229 = (( 128 :: int)::ii)))) \ (((l__230 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if ((((((l__229 = (( 128 :: int)::ii)))) \ (((l__230 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__229 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if (((l__230 = (( 32 :: int)::ii)))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))) + else if (((l__230 = (( 64 :: int)::ii)))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))) + else assert_exp True (''destsize constraint''))" + + +(*val integer_arithmetic_mul_widening_3264_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_mul_widening_3264_decode :: "(1)Word.word \(2)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_mul_widening_3264_decode sf op54 U Rm o0 Ra Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (a :: ii) = (Word.uint Ra) in + (let (destsize :: int) = ((( 64 :: int)::ii)) in + (let (datasize :: int) = ((( 32 :: int)::ii)) in + (let (sub_op :: bool) = (o0 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (unsigned :: bool) = (U = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_arithmetic_mul_widening_3264 a d datasize destsize m n sub_op unsigned))))))))))" + + +(*val aarch64_integer_arithmetic_mul_uniform_addsub : ii -> ii -> ii -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \ int \ int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_mul_uniform_addsub a d l__202 l__203 m n sub_op = ( + if ((((((l__202 = (( 8 :: int)::ii)))) \ (((l__203 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) + else if ((((((l__202 = (( 8 :: int)::ii)))) \ (((l__203 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__202 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__202 = (( 16 :: int)::ii)))) \ (((l__203 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) + else if ((((((l__202 = (( 16 :: int)::ii)))) \ (((l__203 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__202 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__202 = (( 32 :: int)::ii)))) \ (((l__203 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) + else if ((((((l__202 = (( 32 :: int)::ii)))) \ (((l__203 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__202 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__202 = (( 64 :: int)::ii)))) \ (((l__203 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) + else if ((((((l__202 = (( 64 :: int)::ii)))) \ (((l__203 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__202 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__202 = (( 128 :: int)::ii)))) \ (((l__203 = (( 32 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (aget_X (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operand3 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) + else if ((((((l__202 = (( 128 :: int)::ii)))) \ (((l__203 = (( 64 :: int)::ii))))))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (aget_X (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operand3 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if sub_op then + ((Word.uint operand3)) - ((((Word.uint operand1)) * ((Word.uint operand2)))) + else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) + else if (((l__202 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if (((l__203 = (( 32 :: int)::ii)))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))) + else if (((l__203 = (( 64 :: int)::ii)))) then + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))) + else assert_exp True (''destsize constraint''))" + + +(*val integer_arithmetic_mul_uniform_addsub_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_mul_uniform_addsub_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_mul_uniform_addsub_decode sf op54 op31 Rm o0 Ra Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (a :: ii) = (Word.uint Ra) in + (let (destsize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (datasize :: ii) = destsize in + (let (sub_op :: bool) = (o0 = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_arithmetic_mul_uniform_addsub a d datasize destsize m n sub_op)))))))))" + + +(*val aarch64_integer_arithmetic_div : ii -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_integer_arithmetic_div :: " int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_div d l__197 m n unsigned = ( + if (((l__197 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((IsZero operand2)) then (( 0 :: int)::ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) div + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii) :: 8 itself)) result (( 0 :: int)::ii) :: 8 Word.word))))))) + else if (((l__197 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((IsZero operand2)) then (( 0 :: int)::ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) div + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 16 :: int)::ii) :: 16 itself)) result (( 0 :: int)::ii) :: 16 Word.word))))))) + else if (((l__197 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((IsZero operand2)) then (( 0 :: int)::ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) div + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))) + else if (((l__197 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((IsZero operand2)) then (( 0 :: int)::ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) div + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))) + else if (((l__197 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((IsZero operand2)) then (( 0 :: int)::ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) div + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 128 :: int)::ii) :: 128 itself)) result (( 0 :: int)::ii) :: 128 Word.word))))))) + else + (let dbytes = (ex_int ((l__197 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_div_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_div_decode sf op1 S Rm opcode2 o1 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (unsigned :: bool) = (o1 = (vec_of_bits [B0] :: 1 Word.word)) in + aarch64_integer_arithmetic_div d datasize m n unsigned)))))))" + + +(*val aarch64_integer_arithmetic_cnt : ii -> ii -> ii -> CountOp -> M unit*) + +definition aarch64_integer_arithmetic_cnt :: " int \ int \ int \ CountOp \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_cnt d l__192 n opcode = ( + if (((l__192 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + undefined_int () ) \ (\ (result :: ii) . + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) \ (\ (result :: ii) . + aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii) :: 8 itself)) result (( 0 :: int)::ii) :: 8 Word.word)))))) + else if (((l__192 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + undefined_int () ) \ (\ (result :: ii) . + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) \ (\ (result :: ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 16 :: int)::ii) :: 16 itself)) result (( 0 :: int)::ii) :: 16 Word.word)))))) + else if (((l__192 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + undefined_int () ) \ (\ (result :: ii) . + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) \ (\ (result :: ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word)))))) + else if (((l__192 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + undefined_int () ) \ (\ (result :: ii) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) \ (\ (result :: ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word)))))) + else if (((l__192 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + undefined_int () ) \ (\ (result :: ii) . + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) \ (\ (result :: ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 128 :: int)::ii) :: 128 itself)) result (( 0 :: int)::ii) :: 128 Word.word)))))) + else + (let dbytes = (ex_int ((l__192 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_arithmetic_cnt_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_cnt_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_cnt_decode sf S opcode2 op1 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (opcode :: CountOp) = + (if (((op1 = (vec_of_bits [B0] :: 1 Word.word)))) then CountOp_CLZ + else CountOp_CLS) in + aarch64_integer_arithmetic_cnt d datasize n opcode))))))" + + +(*val aarch64_integer_arithmetic_addsub_carry : ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +definition aarch64_integer_arithmetic_addsub_carry :: " int \ int \ int \ int \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_addsub_carry d l__187 m n setflags sub_op = ( + if (((l__187 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (let (operand2 :: 8 bits) = (if sub_op then (not_vec operand2 :: 8 Word.word) else operand2) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2(ProcState_C w__0) :: ( 8 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + write_reg PSTATE_ref (w__4 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__187 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (let (operand2 :: 16 bits) = (if sub_op then (not_vec operand2 :: 16 Word.word) else operand2) in + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2(ProcState_C w__5) :: ( 16 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + (write_reg PSTATE_ref (w__7 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + write_reg PSTATE_ref (w__9 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__187 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (let (operand2 :: 32 bits) = (if sub_op then (not_vec operand2 :: 32 Word.word) else operand2) in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2(ProcState_C w__10) :: ( 32 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + write_reg PSTATE_ref (w__14 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__187 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (let (operand2 :: 64 bits) = (if sub_op then (not_vec operand2 :: 64 Word.word) else operand2) in + read_reg PSTATE_ref \ (\ (w__15 :: ProcState) . + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2(ProcState_C w__15) :: ( 64 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__187 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (let (operand2 :: 128 bits) = (if sub_op then (not_vec operand2 :: 128 Word.word) else operand2) in + read_reg PSTATE_ref \ (\ (w__20 :: ProcState) . + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2(ProcState_C w__20) :: ( 128 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__21 :: ProcState) . + (write_reg PSTATE_ref (w__21 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg PSTATE_ref (w__23 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + write_reg PSTATE_ref (w__24 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else + (let dbytes = (ex_int ((l__187 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_arithmetic_addsub_carry_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_addsub_carry_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_addsub_carry_decode sf op1 S Rm opcode2 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (setflags :: bool) = (S = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_arithmetic_addsub_carry d datasize m n setflags sub_op))))))))" + + +(*val ExtendReg : forall 'N . Size 'N => integer -> ii -> ExtendType -> ii -> M (mword 'N)*) + +definition ExtendReg :: " int \ int \ ExtendType \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " ExtendReg (N__tv :: int) reg typ1 shift = ( + (assert_exp (((((shift \ (( 0 :: int)::ii))) \ ((shift \ (( 4 :: int)::ii)))))) (''((shift >= 0) && (shift <= 4))'') \ + (aget_X N__tv reg :: (( 'N::len)Word.word) M)) \ (\ (val_name :: 'N bits) . + undefined_bool () \ (\ (unsigned :: bool) . + undefined_int () \ (\ (len :: ii) . + (let (len :: ii) = + ((case typ1 of + ExtendType_SXTB => + (let (unsigned :: bool) = False in + (( 8 :: int)::ii)) + | ExtendType_SXTH => + (let (unsigned :: bool) = False in + (( 16 :: int)::ii)) + | ExtendType_SXTW => + (let (unsigned :: bool) = False in + (( 32 :: int)::ii)) + | ExtendType_SXTX => + (let (unsigned :: bool) = False in + (( 64 :: int)::ii)) + | ExtendType_UXTB => + (let (unsigned :: bool) = True in + (( 8 :: int)::ii)) + | ExtendType_UXTH => + (let (unsigned :: bool) = True in + (( 16 :: int)::ii)) + | ExtendType_UXTW => + (let (unsigned :: bool) = True in + (( 32 :: int)::ii)) + | ExtendType_UXTX => + (let (unsigned :: bool) = True in + (( 64 :: int)::ii)) + )) in + (let len = (min len ((((int (size val_name))) - shift))) in + coerce_int_nat shift \ (\ shift2 . + (let (len2 :: int) = (ex_int len) in + assert_exp True (''hack'') \ + return ((place_subrange ((int (size val_name))) val_name ((len2 - (( 1 :: int)::ii))) (( 0 :: int)::ii) + ((ex_nat shift2)) + :: ( 'N::len)Word.word))))))))))" + + +(*val aget_ELR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_ELR__1 : unit -> M (mword ty64)*) + +definition aget_ELR__0 :: "(2)Word.word \((register_value),((64)Word.word),(exception))monad " where + " aget_ELR__0 el = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (r :: 64 bits) . + (let pat0 = el in + if (((pat0 = EL1))) then (read_reg ELR_EL1_ref :: ( 64 Word.word) M) + else if (((pat0 = EL2))) then (read_reg ELR_EL2_ref :: ( 64 Word.word) M) + else if (((pat0 = EL3))) then (read_reg ELR_EL3_ref :: ( 64 Word.word) M) + else Unreachable () \ return r)))" + + +definition aget_ELR__1 :: " unit \((register_value),((64)Word.word),(exception))monad " where + " aget_ELR__1 _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((ProcState_EL w__0) \ EL0))) ('''') \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (aget_ELR__0(ProcState_EL w__1) :: ( 64 Word.word) M))))" + + +(*val ROR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +definition ROR_C :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where + " ROR_C x shift = ( + assert_exp (((shift \ (( 0 :: int)::ii)))) (''(shift != 0)'') \ + ((let (m :: ii) = (shift mod ((int (size x)))) in + (LSR x m :: (( 'N::len)Word.word) M) \ (\ (w__0 :: ( 'N::len)Word.word) . + (LSL x ((((int (size x))) - ((ex_int m)))) :: (( 'N::len)Word.word) M) \ (\ (w__1 :: ( 'N::len)Word.word) . + (let (result :: 'N bits) = ((or_vec w__0 w__1 :: ( 'N::len)Word.word)) in + (let (carry_out :: 1 bits) = + ((vec_of_bits [access_vec_dec result ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in + return (result, carry_out))))))))" + + +(*val ROR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +definition ROR :: "('N::len)Word.word \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " ROR x shift = ( + (assert_exp ((shift \ (( 0 :: int)::ii))) (''(shift >= 0)'') \ + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (anon10 :: 1 bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if (((shift = (( 0 :: int)::ii)))) then return x + else + (ROR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (result :: 'N bits) = tup__0 in + (let (anon10 :: 1 bits) = tup__1 in + return result)))))))" + + +(*val aarch64_integer_bitfield : forall 'datasize. Size 'datasize => ii -> ii -> ii -> itself 'datasize -> bool -> bool -> ii -> mword 'datasize -> mword 'datasize -> M unit*) + +definition aarch64_integer_bitfield :: " int \ int \ int \('datasize::len)itself \ bool \ bool \ int \('datasize::len)Word.word \('datasize::len)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_integer_bitfield R1 S d datasize extend1 inzero n tmask wmask = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (if inzero then return ((Zeros__1 datasize () :: ( 'datasize::len)Word.word)) + else (aget_X datasize d :: (( 'datasize::len)Word.word) M))) \ (\ (dst :: 'datasize bits) . + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \ (\ (src :: 'datasize bits) . + (ROR src R1 :: (( 'datasize::len)Word.word) M) \ (\ (w__1 :: ( 'datasize::len)Word.word) . + (let (bot :: 'datasize bits) = + ((or_vec ((and_vec dst ((not_vec wmask :: ( 'datasize::len)Word.word)) :: ( 'datasize::len)Word.word)) + ((and_vec w__1 wmask :: ( 'datasize::len)Word.word)) + :: ( 'datasize::len)Word.word)) in + (if extend1 then + (Replicate ((int (size bot))) (vec_of_bits [access_vec_dec src S] :: 1 Word.word) + :: (( 'datasize::len)Word.word) M) + else return dst) \ (\ (top1 :: 'datasize bits) . + aset_X d + ((or_vec ((and_vec top1 ((not_vec tmask :: ( 'datasize::len)Word.word)) :: ( 'datasize::len)Word.word)) + ((and_vec bot tmask :: ( 'datasize::len)Word.word)) + :: ( 'datasize::len)Word.word))))))))))" + + +(*val ShiftReg : forall 'N . Size 'N => integer -> ii -> ShiftType -> ii -> M (mword 'N)*) + +definition ShiftReg :: " int \ int \ ShiftType \ int \((register_value),(('N::len)Word.word),(exception))monad " where + " ShiftReg (N__tv :: int) reg typ1 amount = ( + (aget_X N__tv reg :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + (case typ1 of + ShiftType_LSL => (LSL result amount :: (( 'N::len)Word.word) M) + | ShiftType_LSR => (LSR result amount :: (( 'N::len)Word.word) M) + | ShiftType_ASR => (ASR result amount :: (( 'N::len)Word.word) M) + | ShiftType_ROR => (ROR result amount :: (( 'N::len)Word.word) M) + )))" + + +(*val aarch64_integer_shift_variable : ii -> ii -> ii -> ii -> ShiftType -> M unit*) + +definition aarch64_integer_shift_variable :: " int \ int \ int \ int \ ShiftType \((register_value),(unit),(exception))monad " where + " aarch64_integer_shift_variable d l__182 m n shift_type = ( + if (((l__182 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (ShiftReg (( 8 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 8 :: int)::ii))) :: ( 8 Word.word) M) \ (\ (w__0 :: 8 + bits) . + (let result = w__0 in + aset_X d result))))) + else if (((l__182 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (ShiftReg (( 16 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 16 :: int)::ii))) :: ( 16 Word.word) M) \ (\ (w__1 :: 16 + bits) . + (let result = w__1 in + aset_X d result))))) + else if (((l__182 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (ShiftReg (( 32 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 32 :: int)::ii))) :: ( 32 Word.word) M) \ (\ (w__2 :: 32 + bits) . + (let result = w__2 in + aset_X d result))))) + else if (((l__182 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (ShiftReg (( 64 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 64 :: int)::ii))) :: ( 64 Word.word) M) \ (\ (w__3 :: 64 + bits) . + (let result = w__3 in + aset_X d result))))) + else if (((l__182 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (ShiftReg (( 128 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 128 :: int)::ii))) :: ( 128 Word.word) M) \ (\ (w__4 :: 128 + bits) . + (let result = w__4 in + aset_X d result))))) + else + (let dbytes = (ex_int ((l__182 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_shift_variable_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_shift_variable_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(4)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_shift_variable_decode sf op1 S Rm opcode2 op2 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (shift_type :: ShiftType) = (DecodeShift op2) in + aarch64_integer_shift_variable d datasize m n shift_type)))))))" + + +(*val aarch64_integer_logical_shiftedreg : ii -> ii -> bool -> ii -> ii -> LogicalOp -> bool -> ii -> ShiftType -> M unit*) + +definition aarch64_integer_logical_shiftedreg :: " int \ int \ bool \ int \ int \ LogicalOp \ bool \ int \ ShiftType \((register_value),(unit),(exception))monad " where + " aarch64_integer_logical_shiftedreg d l__177 invert m n op1 setflags shift_amount shift_type = ( + if (((l__177 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (ShiftReg (( 8 :: int)::ii) m shift_type shift_amount :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (let (operand2 :: 8 bits) = (if invert then (not_vec operand2 :: 8 Word.word) else operand2) in + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (result :: 8 bits) . + (let (result :: 8 bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: 8 Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: 8 Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: 8 Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 8 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + aset_X d result)))))) + else if (((l__177 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (ShiftReg (( 16 :: int)::ii) m shift_type shift_amount :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (let (operand2 :: 16 bits) = (if invert then (not_vec operand2 :: 16 Word.word) else operand2) in + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (result :: 16 bits) . + (let (result :: 16 bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: 16 Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: 16 Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: 16 Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 16 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + aset_X d result)))))) + else if (((l__177 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (ShiftReg (( 32 :: int)::ii) m shift_type shift_amount :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (let (operand2 :: 32 bits) = (if invert then (not_vec operand2 :: 32 Word.word) else operand2) in + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + (let (result :: 32 bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: 32 Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: 32 Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: 32 Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 32 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + aset_X d result)))))) + else if (((l__177 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (ShiftReg (( 64 :: int)::ii) m shift_type shift_amount :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (let (operand2 :: 64 bits) = (if invert then (not_vec operand2 :: 64 Word.word) else operand2) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (let (result :: 64 bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: 64 Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: 64 Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: 64 Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 64 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + (write_reg PSTATE_ref (w__14 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + aset_X d result)))))) + else if (((l__177 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (ShiftReg (( 128 :: int)::ii) m shift_type shift_amount :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (let (operand2 :: 128 bits) = (if invert then (not_vec operand2 :: 128 Word.word) else operand2) in + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (result :: 128 bits) . + (let (result :: 128 bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: 128 Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: 128 Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: 128 Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 128 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + aset_X d result)))))) + else + (let dbytes = (ex_int ((l__177 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_integer_arithmetic_addsub_shiftedreg : ii -> ii -> ii -> ii -> bool -> ii -> ShiftType -> bool -> M unit*) + +definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \ int \ int \ int \ bool \ int \ ShiftType \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_addsub_shiftedreg d l__172 m n setflags shift_amount shift_type sub_op = ( + if (((l__172 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (ShiftReg (( 8 :: int)::ii) m shift_type shift_amount :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 8 bits)) = + (if sub_op then + (let (operand2 :: 8 bits) = ((not_vec operand2 :: 8 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 8 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__172 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (ShiftReg (( 16 :: int)::ii) m shift_type shift_amount :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 16 bits)) = + (if sub_op then + (let (operand2 :: 16 bits) = ((not_vec operand2 :: 16 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 16 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__172 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (ShiftReg (( 32 :: int)::ii) m shift_type shift_amount :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 32 bits)) = + (if sub_op then + (let (operand2 :: 32 bits) = ((not_vec operand2 :: 32 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 32 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__172 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (ShiftReg (( 64 :: int)::ii) m shift_type shift_amount :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 64 bits)) = + (if sub_op then + (let (operand2 :: 64 bits) = ((not_vec operand2 :: 64 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 64 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + (write_reg PSTATE_ref (w__14 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else if (((l__172 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (ShiftReg (( 128 :: int)::ii) m shift_type shift_amount :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 128 bits)) = + (if sub_op then + (let (operand2 :: 128 bits) = ((not_vec operand2 :: 128 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 128 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |))))))) + else return () ) \ + aset_X d result)))))))))) + else + (let dbytes = (ex_int ((l__172 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val Prefetch : mword ty64 -> mword ty5 -> M unit*) + +definition Prefetch :: "(64)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " Prefetch address prfop = ( + undefined_PrefetchHint () \ (\ (hint :: PrefetchHint) . + undefined_int () \ (\ (target :: ii) . + undefined_bool () \ (\ (stream :: bool) . + (let b__0 = ((slice0 prfop (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (hint :: PrefetchHint) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Prefetch_READ + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Prefetch_EXEC + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Prefetch_WRITE + else hint) in + (let (target :: ii) = (Word.uint ((slice0 prfop (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let (stream :: bool) = + ((vec_of_bits [access_vec_dec prfop (( 0 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + (let (_ :: unit) = (Hint_Prefetch address hint target stream) in + return () )))))))))" + + +(*val IsSecondStage : FaultRecord -> M bool*) + +definition IsSecondStage :: " FaultRecord \((register_value),(bool),(exception))monad " where + " IsSecondStage fault = ( + assert_exp ((((FaultRecord_typ fault) \ Fault_None))) (''((fault).type != Fault_None)'') \ + return(FaultRecord_secondstage fault))" + + +(*val IsFault : AddressDescriptor -> bool*) + +definition IsFault :: " AddressDescriptor \ bool " where + " IsFault addrdesc = ( ((FaultRecord_typ (AddressDescriptor_fault addrdesc)) \ Fault_None))" + + +(*val CombineS1S2Desc : AddressDescriptor -> AddressDescriptor -> M AddressDescriptor*) + +definition CombineS1S2Desc :: " AddressDescriptor \ AddressDescriptor \((register_value),(AddressDescriptor),(exception))monad " where + " CombineS1S2Desc s1desc s2desc = ( + undefined_AddressDescriptor () \ (\ (result :: AddressDescriptor) . + (let result = ((result (| AddressDescriptor_paddress := ((AddressDescriptor_paddress s2desc))|))) in + (if (((((IsFault s1desc)) \ ((IsFault s2desc))))) then + (let (result :: AddressDescriptor) = (if ((IsFault s1desc)) then s1desc else s2desc) in + return result) + else if (((((((MemoryAttributes_typ (AddressDescriptor_memattrs s2desc)) = MemType_Device))) \ ((((MemoryAttributes_typ (AddressDescriptor_memattrs s1desc)) = MemType_Device)))))) then + (let (tmp_610 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let tmp_610 = ((tmp_610 (| MemoryAttributes_typ := MemType_Device |))) in + (let result = ((result (| AddressDescriptor_memattrs := tmp_610 |))) in + if ((((MemoryAttributes_typ (AddressDescriptor_memattrs s1desc)) = MemType_Normal))) then + (let (tmp_620 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let (tmp_620 :: MemoryAttributes) = + ((tmp_620 (| + MemoryAttributes_device := ((MemoryAttributes_device (AddressDescriptor_memattrs s2desc)))|))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_620 |))) in + return result))) + else if ((((MemoryAttributes_typ (AddressDescriptor_memattrs s2desc)) = MemType_Normal))) then + (let (tmp_630 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let (tmp_630 :: MemoryAttributes) = + ((tmp_630 (| + MemoryAttributes_device := ((MemoryAttributes_device (AddressDescriptor_memattrs s1desc)))|))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_630 |))) in + return result))) + else + (let (tmp_640 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + CombineS1S2Device(MemoryAttributes_device (AddressDescriptor_memattrs s1desc))(MemoryAttributes_device (AddressDescriptor_memattrs + s2desc)) \ (\ (w__0 :: DeviceType) . + (let (tmp_640 :: MemoryAttributes) = ((tmp_640 (| MemoryAttributes_device := w__0 |))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_640 |))) in + return result))))))) + else + (let (tmp_650 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let tmp_650 = ((tmp_650 (| MemoryAttributes_typ := MemType_Normal |))) in + (let result = ((result (| AddressDescriptor_memattrs := tmp_650 |))) in + (let (tmp_660 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + undefined_DeviceType () \ (\ (w__1 :: DeviceType) . + (let tmp_660 = ((tmp_660 (| MemoryAttributes_device := w__1 |))) in + (let result = ((result (| AddressDescriptor_memattrs := tmp_660 |))) in + (let (tmp_670 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + CombineS1S2AttrHints(MemoryAttributes_inner (AddressDescriptor_memattrs s1desc))(MemoryAttributes_inner (AddressDescriptor_memattrs + s2desc)) \ (\ (w__2 :: MemAttrHints) . + (let tmp_670 = ((tmp_670 (| MemoryAttributes_inner := w__2 |))) in + (let result = ((result (| AddressDescriptor_memattrs := tmp_670 |))) in + (let (tmp_680 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + CombineS1S2AttrHints(MemoryAttributes_outer (AddressDescriptor_memattrs s1desc))(MemoryAttributes_outer (AddressDescriptor_memattrs + s2desc)) \ (\ (w__3 :: MemAttrHints) . + (let (tmp_680 :: MemoryAttributes) = ((tmp_680 (| MemoryAttributes_outer := w__3 |))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_680 |))) in + (let (tmp_690 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let (tmp_690 :: MemoryAttributes) = + ((tmp_690 (| + MemoryAttributes_shareable := + ((((MemoryAttributes_shareable (AddressDescriptor_memattrs s1desc)) \(MemoryAttributes_shareable (AddressDescriptor_memattrs s2desc)))))|))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_690 |))) in + (let (tmp_700 :: MemoryAttributes) = ((AddressDescriptor_memattrs result)) in + (let (tmp_700 :: MemoryAttributes) = + ((tmp_700 (| + MemoryAttributes_outershareable := + ((((MemoryAttributes_outershareable (AddressDescriptor_memattrs s1desc)) \(MemoryAttributes_outershareable (AddressDescriptor_memattrs s2desc)))))|))) in + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := tmp_700 |))) in + return result)))))))))))))))))))))) \ (\ (result :: AddressDescriptor) . + MemAttrDefaults(AddressDescriptor_memattrs result) \ (\ (w__4 :: MemoryAttributes) . + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_memattrs := w__4 |))) in + return result))))))" + + +(*val IsExternalSyncAbort__0 : Fault -> M bool*) + +(*val IsExternalSyncAbort__1 : FaultRecord -> M bool*) + +definition IsExternalSyncAbort__0 :: " Fault \((register_value),(bool),(exception))monad " where + " IsExternalSyncAbort__0 typ1 = ( + assert_exp (((typ1 \ Fault_None))) ('''') \ + return ((((((typ1 = Fault_SyncExternal))) \ ((((((typ1 = Fault_SyncParity))) \ ((((((typ1 = Fault_SyncExternalOnWalk))) \ (((typ1 = Fault_SyncParityOnWalk)))))))))))))" + + +definition IsExternalSyncAbort__1 :: " FaultRecord \((register_value),(bool),(exception))monad " where + " IsExternalSyncAbort__1 fault = ( IsExternalSyncAbort__0(FaultRecord_typ fault))" + + +(*val IsExternalAbort__0 : Fault -> M bool*) + +(*val IsExternalAbort__1 : FaultRecord -> M bool*) + +definition IsExternalAbort__0 :: " Fault \((register_value),(bool),(exception))monad " where + " IsExternalAbort__0 typ1 = ( + assert_exp (((typ1 \ Fault_None))) ('''') \ + return ((((((typ1 = Fault_SyncExternal))) \ ((((((typ1 = Fault_SyncParity))) \ ((((((typ1 = Fault_SyncExternalOnWalk))) \ ((((((typ1 = Fault_SyncParityOnWalk))) \ ((((((typ1 = Fault_AsyncExternal))) \ (((typ1 = Fault_AsyncParity)))))))))))))))))))" + + +definition IsExternalAbort__1 :: " FaultRecord \((register_value),(bool),(exception))monad " where + " IsExternalAbort__1 fault = ( IsExternalAbort__0(FaultRecord_typ fault))" + + +(*val IsDebugException : FaultRecord -> M bool*) + +definition IsDebugException :: " FaultRecord \((register_value),(bool),(exception))monad " where + " IsDebugException fault = ( + assert_exp ((((FaultRecord_typ fault) \ Fault_None))) (''((fault).type != Fault_None)'') \ + return ((((FaultRecord_typ fault) = Fault_Debug))))" + + +(*val IPAValid : FaultRecord -> M bool*) + +definition IPAValid :: " FaultRecord \((register_value),(bool),(exception))monad " where + " IPAValid fault = ( + assert_exp ((((FaultRecord_typ fault) \ Fault_None))) (''((fault).type != Fault_None)'') \ + return (if(FaultRecord_s2fs1walk fault) then + (((((FaultRecord_typ fault) = Fault_AccessFlag))) \ (((((((FaultRecord_typ fault) = Fault_Permission))) \ (((((((FaultRecord_typ fault) = Fault_Translation))) \ ((((FaultRecord_typ fault) = Fault_AddressSize)))))))))) + else if(FaultRecord_secondstage fault) then + (((((FaultRecord_typ fault) = Fault_AccessFlag))) \ (((((((FaultRecord_typ fault) = Fault_Translation))) \ ((((FaultRecord_typ fault) = Fault_AddressSize))))))) + else False))" + + +(*val aarch64_integer_logical_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> LogicalOp -> bool -> M unit*) + +definition aarch64_integer_logical_immediate :: " int \('datasize::len)itself \('datasize::len)Word.word \ int \ LogicalOp \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_logical_immediate d datasize imm n op1 setflags = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \ (\ (result :: 'datasize bits) . + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \ (\ (operand1 :: 'datasize bits) . + (let (operand2 :: 'datasize bits) = imm in + (let (result :: 'datasize bits) = + ((case op1 of + LogicalOp_AND => (and_vec operand1 operand2 :: ( 'datasize::len)Word.word) + | LogicalOp_ORR => (or_vec operand1 operand2 :: ( 'datasize::len)Word.word) + | LogicalOp_EOR => (xor_vec operand1 operand2 :: ( 'datasize::len)Word.word) + )) in + (if setflags then + (let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result ((datasize - (( 1 :: int)::ii)))] :: 1 Word.word) + ((IsZeroBit result :: 1 Word.word)) + :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))" + + +(*val aarch64_integer_arithmetic_addsub_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> bool -> bool -> M unit*) + +definition aarch64_integer_arithmetic_addsub_immediate :: " int \('datasize::len)itself \('datasize::len)Word.word \ int \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_addsub_immediate d datasize imm n setflags sub_op = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \ (\ (result :: 'datasize bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP datasize () :: (( 'datasize::len)Word.word) M) + else (aget_X datasize n :: (( 'datasize::len)Word.word) M)) \ (\ (operand1 :: 'datasize bits) . + (let (operand2 :: 'datasize bits) = imm in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 'datasize bits)) = + (if sub_op then + (let (operand2 :: 'datasize bits) = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: (( 'datasize::len)Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + write_reg PSTATE_ref (w__5 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result)))))))))))))" + + +(*val aarch64_integer_arithmetic_addsub_extendedreg : ii -> ii -> ExtendType -> ii -> ii -> bool -> ii -> bool -> M unit*) + +definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \ int \ ExtendType \ int \ int \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_arithmetic_addsub_extendedreg d l__167 extend_type m n setflags shift sub_op = ( + if (((l__167 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP (( 8 :: int)::ii) () :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (ExtendReg (( 8 :: int)::ii) m extend_type shift :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 8 bits)) = + (if sub_op then + (let (operand2 :: 8 bits) = ((not_vec operand2 :: 8 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 8 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + write_reg PSTATE_ref (w__5 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))))) + else if (((l__167 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP (( 16 :: int)::ii) () :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (ExtendReg (( 16 :: int)::ii) m extend_type shift :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 16 bits)) = + (if sub_op then + (let (operand2 :: 16 bits) = ((not_vec operand2 :: 16 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 16 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))))) + else if (((l__167 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP (( 32 :: int)::ii) () :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (ExtendReg (( 32 :: int)::ii) m extend_type shift :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 32 bits)) = + (if sub_op then + (let (operand2 :: 32 bits) = ((not_vec operand2 :: 32 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 32 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__14 :: ProcState) . + (write_reg PSTATE_ref (w__14 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + (write_reg PSTATE_ref (w__15 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + write_reg PSTATE_ref (w__17 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))))) + else if (((l__167 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 64 bits)) = + (if sub_op then + (let (operand2 :: 64 bits) = ((not_vec operand2 :: 64 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 64 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__20 :: ProcState) . + (write_reg PSTATE_ref (w__20 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__21 :: ProcState) . + (write_reg PSTATE_ref (w__21 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + write_reg PSTATE_ref (w__23 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))))) + else if (((l__167 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (if (((n = (( 31 :: int)::ii)))) then (aget_SP (( 128 :: int)::ii) () :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (ExtendReg (( 128 :: int)::ii) m extend_type shift :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (nzcv :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (carry_in :: 1 bits) . + (let ((carry_in :: 1 bits), (operand2 :: 128 bits)) = + (if sub_op then + (let (operand2 :: 128 bits) = ((not_vec operand2 :: 128 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (carry_in, operand2))) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 128 Word.word * 4 Word.word))) in + (let result = tup__0 in + (let nzcv = tup__1 in + (if setflags then + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec nzcv (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + (write_reg PSTATE_ref (w__27 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__28 :: ProcState) . + (write_reg PSTATE_ref (w__28 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__29 :: ProcState) . + write_reg PSTATE_ref (w__29 (| ProcState_V := tup__3 |))))))) + else return () ) \ + (if ((((((d = (( 31 :: int)::ii)))) \ ((\ setflags))))) then aset_SP result + else aset_X d result))))))))))) + else + (let dbytes = (ex_int ((l__167 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val RestoredITBits : mword ty32 -> M (mword ty8)*) + +definition RestoredITBits :: "(32)Word.word \((register_value),((8)Word.word),(exception))monad " where + " RestoredITBits spsr = ( + (let (it :: 8 bits) = + ((concat_vec ((subrange_vec_dec spsr (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) + ((subrange_vec_dec spsr (( 26 :: int)::ii) (( 25 :: int)::ii) :: 2 Word.word)) + :: 8 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + if ((((ProcState_IL w__0) = (vec_of_bits [B1] :: 1 Word.word)))) then + ConstrainUnpredictableBool Unpredictable_ILZEROIT \ (\ (w__1 :: bool) . + return (if w__1 then (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + else it)) + else if (((((\ ((IsZero ((subrange_vec_dec it (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) \ ((IsZero ((subrange_vec_dec it (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word))))))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (if ((((ProcState_EL w__2) = EL2))) then + (read_reg HSCTLR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__3 (( 7 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__4 (( 7 :: int)::ii)] :: 1 Word.word))) \ (\ (itd :: 1 bits) . + return (if ((((((((((vec_of_bits [access_vec_dec spsr (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((\ ((IsZero it))))))) \ ((((((itd = (vec_of_bits [B1] :: 1 Word.word)))) \ ((\ ((IsZero ((subrange_vec_dec it (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)))))))))))) + then + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + else it))))))" + + +(*val IsEL1TransRegimeRegs : unit -> M bool*) + +definition IsEL1TransRegimeRegs :: " unit \((register_value),(bool),(exception))monad " where + " IsEL1TransRegimeRegs _ = ( + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL1)))))) + (and_boolM + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL0))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))))))" + + +(*val CalculateTBI : mword ty64 -> bool -> M bool*) + +definition CalculateTBI :: "(64)Word.word \ bool \((register_value),(bool),(exception))monad " where + " CalculateTBI ptr data = ( + (let (tbi :: bool) = False in + PtrHasUpperAndLowerAddRanges () \ (\ (w__0 :: bool) . + if w__0 then + IsEL1TransRegimeRegs () \ (\ (w__1 :: bool) . + if w__1 then + if data then + if ((((vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else if ((((vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + and_boolM + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + else + and_boolM + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + else if data then + if ((((vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else if ((((vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + and_boolM + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__15 (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + else + and_boolM + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__17 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__17 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + else + read_reg PSTATE_ref \ (\ (w__20 :: ProcState) . + if ((((ProcState_EL w__20) = EL2))) then + if data then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__21 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__21 (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else + and_boolM + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__22 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__22 (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__23 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 29 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + else + read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + if ((((ProcState_EL w__26) = EL3))) then + if data then + (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__27 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__27 (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + else + and_boolM + ((read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__28 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__28 (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__29 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__29 (( 29 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + else return tbi)))))" + + +(*val CalculateBottomPACBit : mword ty64 -> mword ty1 -> M ii*) + +definition CalculateBottomPACBit :: "(64)Word.word \(1)Word.word \((register_value),(int),(exception))monad " where + " CalculateBottomPACBit ptr top_bit = ( + undefined_int () \ (\ (tsz_field :: ii) . + undefined_bool () \ (\ (using64k :: bool) . + PtrHasUpperAndLowerAddRanges () \ (\ (w__0 :: bool) . + (if w__0 then + IsEL1TransRegimeRegs () \ (\ (w__1 :: bool) . + if w__1 then + (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((Word.uint ((slice0 w__2 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + else + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((Word.uint ((slice0 w__3 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \ (\ (w__4 :: ii) . + (let tsz_field = w__4 in + (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return (((((slice0 w__5 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + else + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return (((((slice0 w__6 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \ (\ (w__7 :: bool) . + (let (using64k :: bool) = w__7 in + return (tsz_field, using64k))))) + else + (assert_exp ((HaveEL EL2)) (''HaveEL(EL2)'') \ + (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((Word.uint ((slice0 w__8 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((Word.uint ((slice0 w__9 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))))) \ (\ (w__10 :: ii) . + (let tsz_field = w__10 in + (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__11 :: 64 bits) . + return (((((slice0 w__11 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return (((((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \ (\ (w__13 :: bool) . + (let (using64k :: bool) = w__13 in + return (tsz_field, using64k)))))) + else + read_reg PSTATE_ref \ (\ (w__14 :: ProcState) . + (if ((((ProcState_EL w__14) = EL2))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + return ((Word.uint ((slice0 w__15 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + else + (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__16 :: 32 bits) . + return ((Word.uint ((slice0 w__16 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \ (\ (w__17 :: ii) . + (let tsz_field = w__17 in + read_reg PSTATE_ref \ (\ (w__18 :: ProcState) . + (if ((((ProcState_EL w__18) = EL2))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__19 :: 64 bits) . + return (((((slice0 w__19 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + else + (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__20 :: 32 bits) . + return (((((slice0 w__20 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \ (\ (w__21 :: bool) . + (let (using64k :: bool) = w__21 in + return (tsz_field, using64k)))))))) \ (\ varstup . (let ((tsz_field :: ii), (using64k :: bool)) = varstup in + (let (max_limit_tsz_field :: ii) = ((( 39 :: int)::ii)) in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((ex_int tsz_field)) > ((ex_int max_limit_tsz_field)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_NONE)))))) (''((c == Constraint_FORCE) || (c == Constraint_NONE))'') \ + ((let (tsz_field :: ii) = (if (((c = Constraint_FORCE))) then max_limit_tsz_field else tsz_field) in + return (c, tsz_field)))) + else return (c, tsz_field)) \ (\ varstup . (let ((c :: Constraint), (tsz_field :: ii)) = varstup in + (let (tszmin :: ii) = + (if (((using64k \ (((((ex_int ((VAMax () )))) = (( 52 :: int)::ii))))))) then (( 12 :: int)::ii) + else (( 16 :: int)::ii)) in + (if ((((ex_int tsz_field)) < ((ex_int tszmin)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_NONE)))))) (''((c == Constraint_FORCE) || (c == Constraint_NONE))'') \ + ((let (tsz_field :: ii) = (if (((c = Constraint_FORCE))) then tszmin else tsz_field) in + return tsz_field))) + else return tsz_field) \ (\ (tsz_field :: ii) . + return (((( 64 :: int)::ii) - ((ex_int tsz_field))))))))))))))))" + + +(*val Auth : mword ty64 -> mword ty64 -> mword ty128 -> bool -> mword ty1 -> M (mword ty64)*) + +definition Auth :: "(64)Word.word \(64)Word.word \(128)Word.word \ bool \(1)Word.word \((register_value),((64)Word.word),(exception))monad " where + " Auth ptr modifier K data keynumber = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (PAC :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (original_ptr :: 64 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (error_code :: 2 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (extfield :: 64 bits) . + CalculateTBI ptr data \ (\ (tbi :: bool) . + CalculateBottomPACBit ptr (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) \ (\ (w__0 :: + ii) . + (let bottom_PAC_bit = (ex_int w__0) in + assert_exp True ('''') \ + ((let extfield = + ((replicate_bits (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) (( 64 :: int)::ii) :: 64 Word.word)) in + (let (original_ptr :: 64 bits) = + (if tbi then + (concat_vec ((subrange_vec_dec ptr (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + ((subrange_subrange_concat + ((((((((((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) - + (( 1 :: int)::ii))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) + + + ((bottom_PAC_bit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) + extfield + ((((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) - (( 1 :: int)::ii))) (( 0 :: int)::ii) + ptr ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 56 Word.word)) + :: 64 Word.word) + else + (subrange_subrange_concat ((int (size PAC))) extfield + ((((((- bottom_PAC_bit)) + (( 64 :: int)::ii))) - (( 1 :: int)::ii))) (( 0 :: int)::ii) ptr + ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 64 Word.word)) in + (ComputePAC original_ptr modifier ((subrange_vec_dec K (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((subrange_vec_dec K (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (PAC :: 64 bits) = w__1 in + (let (result :: 64 bits) = + (if tbi then + if ((subrange_subrange_eq PAC + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - (( 1 :: int)::ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - (( 1 :: int)::ii))) + + + bottom_PAC_bit)) bottom_PAC_bit)) then + original_ptr + else + (let (error_code :: 2 bits) = + ((concat_vec keynumber ((not_vec keynumber :: 1 Word.word)) :: 2 Word.word)) in + (concat_vec + ((concat_vec ((subrange_vec_dec original_ptr (( 63 :: int)::ii) (( 55 :: int)::ii) :: 9 Word.word)) error_code + :: 11 Word.word)) ((subrange_vec_dec original_ptr (( 52 :: int)::ii) (( 0 :: int)::ii) :: 53 Word.word)) + :: 64 Word.word)) + else if (((((subrange_subrange_eq PAC + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) bottom_PAC_bit ptr + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) bottom_PAC_bit)) \ (((((subrange_vec_dec PAC (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) = ((subrange_vec_dec ptr (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)))))))) then + original_ptr + else + (let (error_code :: 2 bits) = + ((concat_vec keynumber ((not_vec keynumber :: 1 Word.word)) :: 2 Word.word)) in + (concat_vec + ((concat_vec (vec_of_bits [access_vec_dec original_ptr (( 63 :: int)::ii)] :: 1 Word.word) error_code + :: 3 Word.word)) ((subrange_vec_dec original_ptr (( 60 :: int)::ii) (( 0 :: int)::ii) :: 61 Word.word)) + :: 64 Word.word))) in + return result)))))))))))))))" + + +(*val HighestELUsingAArch32 : unit -> bool*) + +definition HighestELUsingAArch32 :: " unit \ bool " where + " HighestELUsingAArch32 _ = ( if ((\ ((HaveAnyAArch32 () )))) then False else False )" + + +(*val aget_SCR_GEN : unit -> M (mword ty32)*) + +definition aget_SCR_GEN :: " unit \((register_value),((32)Word.word),(exception))monad " where + " aget_SCR_GEN _ = ( + (assert_exp ((HaveEL EL3)) (''HaveEL(EL3)'') \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (r :: 32 bits) . + if ((HighestELUsingAArch32 () )) then (read_reg SCR_ref :: ( 32 Word.word) M) + else (read_reg SCR_EL3_ref :: ( 32 Word.word) M)))" + + +(*val IsSecureBelowEL3 : unit -> M bool*) + +definition IsSecureBelowEL3 :: " unit \((register_value),(bool),(exception))monad " where + " IsSecureBelowEL3 _ = ( + if ((HaveEL EL3)) then + (aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__0 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))) + else return (if ((HaveEL EL2)) then False else False))" + + +(*val UsingAArch32 : unit -> M bool*) + +definition UsingAArch32 :: " unit \((register_value),(bool),(exception))monad " where + " UsingAArch32 _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (let (aarch32 :: bool) = ((ProcState_nRW w__0) = (vec_of_bits [B1] :: 1 Word.word)) in + ((if ((\ ((HaveAnyAArch32 () )))) then assert_exp ((\ aarch32)) (''!(aarch32)'') + else return () ) \ + (if ((HighestELUsingAArch32 () )) then assert_exp aarch32 (''aarch32'') + else return () )) \ + return aarch32)))" + + +(*val aset_SPSR : mword ty32 -> M unit*) + +definition aset_SPSR :: "(32)Word.word \((register_value),(unit),(exception))monad " where + " aset_SPSR value_name = ( + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let p__611 = ((ProcState_M w__1)) in + (let pat0 = p__611 in + if (((pat0 = M32_FIQ))) then write_reg SPSR_fiq_ref value_name + else if (((pat0 = M32_IRQ))) then write_reg SPSR_irq_ref value_name + else if (((pat0 = M32_Svc))) then write_reg SPSR_svc_ref value_name + else if (((pat0 = M32_Monitor))) then write_reg SPSR_mon_ref value_name + else if (((pat0 = M32_Abort))) then write_reg SPSR_abt_ref value_name + else if (((pat0 = M32_Hyp))) then write_reg SPSR_hyp_ref value_name + else if (((pat0 = M32_Undef))) then write_reg SPSR_und_ref value_name + else Unreachable () ))) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let p__610 = ((ProcState_EL w__2)) in + (let pat0 = p__610 in + if (((pat0 = EL1))) then write_reg SPSR_EL1_ref value_name + else if (((pat0 = EL2))) then write_reg SPSR_EL2_ref value_name + else if (((pat0 = EL3))) then write_reg SPSR_EL3_ref value_name + else Unreachable () )))))" + + +(*val aget_SPSR : unit -> M (mword ty32)*) + +definition aget_SPSR :: " unit \((register_value),((32)Word.word),(exception))monad " where + " aget_SPSR _ = ( + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let p__609 = ((ProcState_M w__1)) in + (let pat0 = p__609 in + if (((pat0 = M32_FIQ))) then (read_reg SPSR_fiq_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_IRQ))) then (read_reg SPSR_irq_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_Svc))) then (read_reg SPSR_svc_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_Monitor))) then (read_reg SPSR_mon_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_Abort))) then (read_reg SPSR_abt_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_Hyp))) then (read_reg SPSR_hyp_ref :: ( 32 Word.word) M) + else if (((pat0 = M32_Undef))) then (read_reg SPSR_und_ref :: ( 32 Word.word) M) + else Unreachable () \ return result))) + else + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + (let p__608 = ((ProcState_EL w__9)) in + (let pat0 = p__608 in + if (((pat0 = EL1))) then (read_reg SPSR_EL1_ref :: ( 32 Word.word) M) + else if (((pat0 = EL2))) then (read_reg SPSR_EL2_ref :: ( 32 Word.word) M) + else if (((pat0 = EL3))) then (read_reg SPSR_EL3_ref :: ( 32 Word.word) M) + else Unreachable () \ return result))))))" + + +(*val IsSecure : unit -> M bool*) + +definition IsSecure :: " unit \((register_value),(bool),(exception))monad " where + " IsSecure _ = ( + and_boolM + (and_boolM (return ((HaveEL EL3))) + (UsingAArch32 () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL3))))) \ (\ (w__3 :: + bool) . + if w__3 then return True + else + and_boolM (and_boolM (return ((HaveEL EL3))) ((UsingAArch32 () ))) + (read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + return ((((ProcState_M w__6) = M32_Monitor))))) \ (\ (w__7 :: bool) . + if w__7 then return True + else IsSecureBelowEL3 () )))" + + +(*val FPProcessException : FPExc -> mword ty32 -> M unit*) + +definition FPProcessException :: " FPExc \(32)Word.word \((register_value),(unit),(exception))monad " where + " FPProcessException exception fpcr = ( + undefined_int () \ (\ (cumul :: ii) . + (let (cumul :: ii) = + ((case exception of + FPExc_InvalidOp => (( 0 :: int)::ii) + | FPExc_DivideByZero => (( 1 :: int)::ii) + | FPExc_Overflow => (( 2 :: int)::ii) + | FPExc_Underflow => (( 3 :: int)::ii) + | FPExc_Inexact => (( 4 :: int)::ii) + | FPExc_InputDenorm => (( 7 :: int)::ii) + )) in + (let (enable :: ii) = (((ex_int cumul)) + (( 8 :: int)::ii)) in + if ((((vec_of_bits [access_vec_dec fpcr enable] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + throw (Error_Implementation_Defined (''floating-point trap handling'')) + else + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + (read_reg FPSCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + write_reg + FPSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + else + (read_reg FPSR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + write_reg + FPSR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))))))))" + + +(*val FPRoundBase : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +definition FPRoundBase :: " int \ real \(32)Word.word \ FPRounding \((register_value),(('N::len)Word.word),(exception))monad " where + " FPRoundBase (N__tv :: int) op1 fpcr rounding = ( + (let l__164 = N__tv in + if (((l__164 = (( 16 :: int)::ii)))) then + (((assert_exp True ('''') \ + assert_exp (((op1 \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \ + assert_exp (((rounding \ FPRounding_TIEAWAY))) ('''')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + undefined_int () \ (\ (F_mut :: ii) . + undefined_int () \ (\ (E_mut :: ii) . + undefined_int () \ (\ (minimum_exp :: ii) . + (let minimum_exp = (- (( 14 :: int)::ii)) in + (let E_mut = ((( 5 :: int)::ii)) in + (let F_mut = ((( 10 :: int)::ii)) in + (assert_exp True ('''') \ + undefined_real () ) \ (\ (mantissa :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + (let ((mantissa :: real), (sign :: 1 bits)) = + (if ((op1 < (realFromFrac(( 0 :: int))(( 10 :: int))))) then + (let (sign :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (let (mantissa :: real) = (- op1) in + (mantissa, sign))) + else + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (mantissa :: real) = op1 in + (mantissa, sign)))) in + (let (exponent :: ii) = ((( 0 :: int)::ii)) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa * (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) - (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa \ (realFromFrac(( 20 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa div (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) + (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ False))) \ (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ True)))))) \ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then + UsingAArch32 () \ (\ (w__0 :: bool) . + ((if w__0 then + (read_reg FPSCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + write_reg + FPSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + else + (read_reg FPSR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + write_reg + FPSR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \ + (FPZero (( 16 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \ (\ (w__3 :: ( 'N::len)Word.word) . + return ((Word.ucast w__3 :: ( 'N::len)Word.word)))) + else + (let (biased_exp :: ii) = + (max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 :: int)::ii))) + (( 0 :: int)::ii)) in + (let (mantissa :: real) = + (if (((((ex_int biased_exp)) = (( 0 :: int)::ii)))) then + mantissa div + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + (let (int_mant :: ii) = + (floor ((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 10 :: int)::ii)))))) in + (let (error :: real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 10 :: int)::ii))))) - + (((real_of_int int_mant)))) in + ((if ((((((((ex_int biased_exp)) = (( 0 :: int)::ii)))) \ ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((vec_of_bits [access_vec_dec fpcr (( 11 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else return () ) \ + undefined_bool () ) \ (\ (overflow_to_inf :: bool) . + undefined_bool () \ (\ (round_up :: bool) . + (let ((overflow_to_inf :: bool), (round_up :: bool)) = + ((case rounding of + FPRounding_TIEEVEN => + (let (round_up :: bool) = + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) int_mant (( 0 :: int)::ii) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))) in + (let (overflow_to_inf :: bool) = True in + (overflow_to_inf, round_up))) + | FPRounding_POSINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B0] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B0] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_NEGINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B1] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B1] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_ZERO => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + | FPRounding_ODD => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + )) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if round_up then + (let (int_mant :: ii) = (((ex_int int_mant)) + (( 1 :: int)::ii)) in + (let (biased_exp :: ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 10 :: int)::ii)))))) then (( 1 :: int)::ii) + else biased_exp) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 11 :: int)::ii)))))) then + (let (biased_exp :: ii) = (((ex_int biased_exp)) + (( 1 :: int)::ii)) in + (let (int_mant :: ii) = (((ex_int int_mant)) div (( 2 :: int)::ii)) in + (biased_exp, int_mant))) + else (biased_exp, int_mant)) in + (biased_exp, int_mant)))) + else (biased_exp, int_mant)) in + (let (int_mant :: ii) = + (if ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((rounding = FPRounding_ODD)))))) then + set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + else int_mant) in + (if (((False \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + if ((((ex_int biased_exp)) \ ((((pow2 (( 5 :: int)::ii))) - (( 1 :: int)::ii))))) then + (if overflow_to_inf then (FPInfinity (( 16 :: int)::ii) sign :: ( 16 Word.word) M) + else (FPMaxNormal (( 16 :: int)::ii) sign :: ( 16 Word.word) M)) \ (\ (w__6 :: 16 Word.word) . + (let result = w__6 in + FPProcessException FPExc_Overflow fpcr \ + ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in + return (error, result))))) + else + (let (result :: 16 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 16 :: int)::ii) - (( 10 :: int)::ii))) - (( 1 :: int)::ii))) + :: 5 itself)) biased_exp (( 0 :: int)::ii) + :: 5 Word.word)) + :: 6 Word.word)) + ((GetSlice_int ((make_the_value (( 10 :: int)::ii) :: 10 itself)) int_mant (( 0 :: int)::ii) + :: 10 Word.word)) + :: 16 Word.word)) in + return (error, result)) + else if ((((ex_int biased_exp)) \ ((pow2 (( 5 :: int)::ii))))) then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 itself)) + :: 15 Word.word)) + :: 16 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ + ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + return (error, result)))) + else + (let (result :: 16 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 16 :: int)::ii) - (( 10 :: int)::ii))) - (( 1 :: int)::ii))) + :: 5 itself)) biased_exp (( 0 :: int)::ii) + :: 5 Word.word)) + :: 6 Word.word)) + ((GetSlice_int ((make_the_value (( 10 :: int)::ii) :: 10 itself)) int_mant (( 0 :: int)::ii) + :: 10 Word.word)) + :: 16 Word.word)) in + return (error, result))) \ (\ varstup . (let ((error :: real), (result :: 16 bits)) = varstup in + (if (((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr + else return () ) \ + return ((Word.ucast result :: ( 'N::len)Word.word)))))))))))))))))))))))))) + else if (((l__164 = (( 32 :: int)::ii)))) then + (((assert_exp True ('''') \ + assert_exp (((op1 \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \ + assert_exp (((rounding \ FPRounding_TIEAWAY))) ('''')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + undefined_int () \ (\ (F_mut :: ii) . + undefined_int () \ (\ (E_mut :: ii) . + undefined_int () \ (\ (minimum_exp :: ii) . + (let minimum_exp = (- (( 126 :: int)::ii)) in + (let E_mut = ((( 8 :: int)::ii)) in + (let F_mut = ((( 23 :: int)::ii)) in + (assert_exp True ('''') \ + undefined_real () ) \ (\ (mantissa :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + (let ((mantissa :: real), (sign :: 1 bits)) = + (if ((op1 < (realFromFrac(( 0 :: int))(( 10 :: int))))) then + (let (sign :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (let (mantissa :: real) = (- op1) in + (mantissa, sign))) + else + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (mantissa :: real) = op1 in + (mantissa, sign)))) in + (let (exponent :: ii) = ((( 0 :: int)::ii)) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa * (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) - (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa \ (realFromFrac(( 20 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa div (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) + (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ True))) \ (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ False)))))) \ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then + UsingAArch32 () \ (\ (w__8 :: bool) . + ((if w__8 then + (read_reg FPSCR_ref :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + write_reg + FPSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + else + (read_reg FPSR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + write_reg + FPSR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \ + (FPZero (( 32 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \ (\ (w__11 :: ( 'N::len)Word.word) . + return ((Word.ucast w__11 :: ( 'N::len)Word.word)))) + else + (let (biased_exp :: ii) = + (max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 :: int)::ii))) + (( 0 :: int)::ii)) in + (let (mantissa :: real) = + (if (((((ex_int biased_exp)) = (( 0 :: int)::ii)))) then + mantissa div + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + (let (int_mant :: ii) = + (floor ((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 23 :: int)::ii)))))) in + (let (error :: real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 23 :: int)::ii))))) - + (((real_of_int int_mant)))) in + ((if ((((((((ex_int biased_exp)) = (( 0 :: int)::ii)))) \ ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((vec_of_bits [access_vec_dec fpcr (( 11 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else return () ) \ + undefined_bool () ) \ (\ (overflow_to_inf :: bool) . + undefined_bool () \ (\ (round_up :: bool) . + (let ((overflow_to_inf :: bool), (round_up :: bool)) = + ((case rounding of + FPRounding_TIEEVEN => + (let (round_up :: bool) = + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) int_mant (( 0 :: int)::ii) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))) in + (let (overflow_to_inf :: bool) = True in + (overflow_to_inf, round_up))) + | FPRounding_POSINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B0] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B0] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_NEGINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B1] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B1] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_ZERO => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + | FPRounding_ODD => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + )) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if round_up then + (let (int_mant :: ii) = (((ex_int int_mant)) + (( 1 :: int)::ii)) in + (let (biased_exp :: ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 23 :: int)::ii)))))) then (( 1 :: int)::ii) + else biased_exp) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 24 :: int)::ii)))))) then + (let (biased_exp :: ii) = (((ex_int biased_exp)) + (( 1 :: int)::ii)) in + (let (int_mant :: ii) = (((ex_int int_mant)) div (( 2 :: int)::ii)) in + (biased_exp, int_mant))) + else (biased_exp, int_mant)) in + (biased_exp, int_mant)))) + else (biased_exp, int_mant)) in + (let (int_mant :: ii) = + (if ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((rounding = FPRounding_ODD)))))) then + set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + else int_mant) in + (if (((True \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + if ((((ex_int biased_exp)) \ ((((pow2 (( 8 :: int)::ii))) - (( 1 :: int)::ii))))) then + (if overflow_to_inf then (FPInfinity (( 32 :: int)::ii) sign :: ( 32 Word.word) M) + else (FPMaxNormal (( 32 :: int)::ii) sign :: ( 32 Word.word) M)) \ (\ (w__14 :: 32 Word.word) . + (let result = w__14 in + FPProcessException FPExc_Overflow fpcr \ + ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in + return (error, result))))) + else + (let (result :: 32 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 32 :: int)::ii) - (( 23 :: int)::ii))) - (( 1 :: int)::ii))) + :: 8 itself)) biased_exp (( 0 :: int)::ii) + :: 8 Word.word)) + :: 9 Word.word)) + ((GetSlice_int ((make_the_value (( 23 :: int)::ii) :: 23 itself)) int_mant (( 0 :: int)::ii) + :: 23 Word.word)) + :: 32 Word.word)) in + return (error, result)) + else if ((((ex_int biased_exp)) \ ((pow2 (( 8 :: int)::ii))))) then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 itself)) + :: 31 Word.word)) + :: 32 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ + ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + return (error, result)))) + else + (let (result :: 32 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 32 :: int)::ii) - (( 23 :: int)::ii))) - (( 1 :: int)::ii))) + :: 8 itself)) biased_exp (( 0 :: int)::ii) + :: 8 Word.word)) + :: 9 Word.word)) + ((GetSlice_int ((make_the_value (( 23 :: int)::ii) :: 23 itself)) int_mant (( 0 :: int)::ii) + :: 23 Word.word)) + :: 32 Word.word)) in + return (error, result))) \ (\ varstup . (let ((error :: real), (result :: 32 bits)) = varstup in + (if (((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr + else return () ) \ + return ((Word.ucast result :: ( 'N::len)Word.word)))))))))))))))))))))))))) + else if (((l__164 = (( 64 :: int)::ii)))) then + (((assert_exp True ('''') \ + assert_exp (((op1 \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \ + assert_exp (((rounding \ FPRounding_TIEAWAY))) ('''')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + undefined_int () \ (\ (F_mut :: ii) . + undefined_int () \ (\ (E_mut :: ii) . + undefined_int () \ (\ (minimum_exp :: ii) . + (let minimum_exp = (- (( 1022 :: int)::ii)) in + (let E_mut = ((( 11 :: int)::ii)) in + (let F_mut = ((( 52 :: int)::ii)) in + (assert_exp True ('''') \ + undefined_real () ) \ (\ (mantissa :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + (let ((mantissa :: real), (sign :: 1 bits)) = + (if ((op1 < (realFromFrac(( 0 :: int))(( 10 :: int))))) then + (let (sign :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (let (mantissa :: real) = (- op1) in + (mantissa, sign))) + else + (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (mantissa :: real) = op1 in + (mantissa, sign)))) in + (let (exponent :: ii) = ((( 0 :: int)::ii)) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa * (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) - (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + (let ((exponent :: ii), (mantissa :: real)) = + (while (exponent, mantissa) + (\ varstup . (let (exponent, mantissa) = varstup in mantissa \ (realFromFrac(( 20 :: int))(( 10 :: int))))) + (\ varstup . (let (exponent, mantissa) = varstup in + (let (mantissa :: real) = (mantissa div (realFromFrac(( 20 :: int))(( 10 :: int)))) in + (let (exponent :: ii) = (((ex_int exponent)) + (( 1 :: int)::ii)) in + (exponent, mantissa)))))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ True))) \ (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ False)))))) \ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then + UsingAArch32 () \ (\ (w__16 :: bool) . + ((if w__16 then + (read_reg FPSCR_ref :: ( 32 Word.word) M) \ (\ (w__17 :: 32 Word.word) . + write_reg + FPSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + else + (read_reg FPSR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + write_reg + FPSR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \ + (FPZero (( 64 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \ (\ (w__19 :: ( 'N::len)Word.word) . + return ((Word.ucast w__19 :: ( 'N::len)Word.word)))) + else + (let (biased_exp :: ii) = + (max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 :: int)::ii))) + (( 0 :: int)::ii)) in + (let (mantissa :: real) = + (if (((((ex_int biased_exp)) = (( 0 :: int)::ii)))) then + mantissa div + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + (let (int_mant :: ii) = + (floor ((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 52 :: int)::ii)))))) in + (let (error :: real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 52 :: int)::ii))))) - + (((real_of_int int_mant)))) in + ((if ((((((((ex_int biased_exp)) = (( 0 :: int)::ii)))) \ ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((vec_of_bits [access_vec_dec fpcr (( 11 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else return () ) \ + undefined_bool () ) \ (\ (overflow_to_inf :: bool) . + undefined_bool () \ (\ (round_up :: bool) . + (let ((overflow_to_inf :: bool), (round_up :: bool)) = + ((case rounding of + FPRounding_TIEEVEN => + (let (round_up :: bool) = + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) int_mant (( 0 :: int)::ii) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))) in + (let (overflow_to_inf :: bool) = True in + (overflow_to_inf, round_up))) + | FPRounding_POSINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B0] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B0] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_NEGINF => + (let (round_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((sign = (vec_of_bits [B1] :: 1 Word.word))))) in + (let (overflow_to_inf :: bool) = (sign = (vec_of_bits [B1] :: 1 Word.word)) in + (overflow_to_inf, round_up))) + | FPRounding_ZERO => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + | FPRounding_ODD => + (let (round_up :: bool) = False in + (let (overflow_to_inf :: bool) = False in + (overflow_to_inf, round_up))) + )) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if round_up then + (let (int_mant :: ii) = (((ex_int int_mant)) + (( 1 :: int)::ii)) in + (let (biased_exp :: ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 52 :: int)::ii)))))) then (( 1 :: int)::ii) + else biased_exp) in + (let ((biased_exp :: ii), (int_mant :: ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 53 :: int)::ii)))))) then + (let (biased_exp :: ii) = (((ex_int biased_exp)) + (( 1 :: int)::ii)) in + (let (int_mant :: ii) = (((ex_int int_mant)) div (( 2 :: int)::ii)) in + (biased_exp, int_mant))) + else (biased_exp, int_mant)) in + (biased_exp, int_mant)))) + else (biased_exp, int_mant)) in + (let (int_mant :: ii) = + (if ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ (((rounding = FPRounding_ODD)))))) then + set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + else int_mant) in + (if (((True \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + if ((((ex_int biased_exp)) \ ((((pow2 (( 11 :: int)::ii))) - (( 1 :: int)::ii))))) then + (if overflow_to_inf then (FPInfinity (( 64 :: int)::ii) sign :: ( 64 Word.word) M) + else (FPMaxNormal (( 64 :: int)::ii) sign :: ( 64 Word.word) M)) \ (\ (w__22 :: 64 Word.word) . + (let result = w__22 in + FPProcessException FPExc_Overflow fpcr \ + ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in + return (error, result))))) + else + (let (result :: 64 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 64 :: int)::ii) - (( 52 :: int)::ii))) - (( 1 :: int)::ii))) + :: 11 itself)) biased_exp (( 0 :: int)::ii) + :: 11 Word.word)) + :: 12 Word.word)) + ((GetSlice_int ((make_the_value (( 52 :: int)::ii) :: 52 itself)) int_mant (( 0 :: int)::ii) + :: 52 Word.word)) + :: 64 Word.word)) in + return (error, result)) + else if ((((ex_int biased_exp)) \ ((pow2 (( 11 :: int)::ii))))) then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 itself)) + :: 63 Word.word)) + :: 64 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ + ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + return (error, result)))) + else + (let (result :: 64 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 64 :: int)::ii) - (( 52 :: int)::ii))) - (( 1 :: int)::ii))) + :: 11 itself)) biased_exp (( 0 :: int)::ii) + :: 11 Word.word)) + :: 12 Word.word)) + ((GetSlice_int ((make_the_value (( 52 :: int)::ii) :: 52 itself)) int_mant (( 0 :: int)::ii) + :: 52 Word.word)) + :: 64 Word.word)) in + return (error, result))) \ (\ varstup . (let ((error :: real), (result :: 64 bits)) = varstup in + (if (((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr + else return () ) \ + return ((Word.ucast result :: ( 'N::len)Word.word)))))))))))))))))))))))))) + else assert_exp False ('''') \ exit0 () ))" + + +(*val FPRoundCV : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +definition FPRoundCV :: " int \ real \(32)Word.word \ FPRounding \((register_value),(('N::len)Word.word),(exception))monad " where + " FPRoundCV (N__tv :: int) op1 fpcr__arg rounding = ( + (let fpcr = fpcr__arg in + (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (FPRoundBase N__tv op1 fpcr rounding :: (( 'N::len)Word.word) M))))" + + +(*val FPRound__0 : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +(*val FPRound__1 : forall 'N . Size 'N => integer -> real -> mword ty32 -> M (mword 'N)*) + +definition FPRound__0 :: " int \ real \(32)Word.word \ FPRounding \((register_value),(('N::len)Word.word),(exception))monad " where + " FPRound__0 (N__tv :: int) op1 fpcr__arg rounding = ( + (let fpcr = fpcr__arg in + (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (FPRoundBase N__tv op1 fpcr rounding :: (( 'N::len)Word.word) M))))" + + +definition FPRound__1 :: " int \ real \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPRound__1 (N__tv :: int) op1 fpcr = ( + (FPRound__0 N__tv op1 fpcr ((FPRoundingMode fpcr)) :: (( 'N::len)Word.word) M))" + + +(*val FixedToFP : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'N)*) + +definition FixedToFP :: " int \('M::len)Word.word \ int \ bool \(32)Word.word \ FPRounding \((register_value),(('N::len)Word.word),(exception))monad " where + " FixedToFP (N__tv :: int) op1 fbits unsigned fpcr rounding = ( + ((assert_exp ((((((N__tv = (( 16 :: int)::ii)))) \ ((((((N__tv = (( 32 :: int)::ii)))) \ (((N__tv = (( 64 :: int)::ii)))))))))) ('''') \ + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \ + (undefined_bitvector N__tv :: (( 'N::len)Word.word) M)) \ (\ (result :: 'N bits) . + (assert_exp ((fbits \ (( 0 :: int)::ii))) ('''') \ + assert_exp (((rounding \ FPRounding_ODD))) ('''')) \ + ((let (int_operand :: ii) = (asl_Int op1 unsigned) in + (let (real_operand :: real) = + ((((real_of_int int_operand))) div ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) fbits))) in + if (((real_operand = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then + (FPZero ((int (size result))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else (FPRound__0 ((int (size result))) real_operand fpcr rounding :: (( 'N::len)Word.word) M))))))" + + +(*val FPProcessNaN : forall 'N . Size 'N => FPType -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPProcessNaN :: " FPType \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPProcessNaN typ1 op1 fpcr = ( + ((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + assert_exp ((((((typ1 = FPType_QNaN))) \ (((typ1 = FPType_SNaN)))))) (''((type == FPType_QNaN) || (type == FPType_SNaN))'')) \ + undefined_int () ) \ (\ (topfrac :: ii) . + (let l__161 = (int (size op1)) in + (let (topfrac :: ii) = + (if (((l__161 = (( 16 :: int)::ii)))) then + (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in + (( 9 :: int)::ii)) + else if (((l__161 = (( 32 :: int)::ii)))) then + (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in + (( 22 :: int)::ii)) + else + (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in + (( 51 :: int)::ii))) in + (let (result :: 'N bits) = op1 in + (if (((typ1 = FPType_SNaN))) then + (let result = + ((set_slice0 ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1] :: 1 Word.word) :: ( 'N::len)Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ return result) + else return result) \ (\ (result :: 'N bits) . + if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) + else return result))))))" + + +(*val FPProcessNaNs3 : forall 'N . Size 'N => FPType -> FPType -> FPType -> mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*) + +definition FPProcessNaNs3 :: " FPType \ FPType \ FPType \('N::len)Word.word \('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(bool*('N::len)Word.word),(exception))monad " where + " FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + if (((type1 = FPType_SNaN))) then + (let done1 = True in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let (result :: 'N bits) = w__0 in + return (done1, result)))) + else if (((type2 = FPType_SNaN))) then + (let done1 = True in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__1 :: 'N bits) . + (let (result :: 'N bits) = w__1 in + return (done1, result)))) + else if (((type3 = FPType_SNaN))) then + (let done1 = True in + (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__2 :: 'N bits) . + (let (result :: 'N bits) = w__2 in + return (done1, result)))) + else if (((type1 = FPType_QNaN))) then + (let done1 = True in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__3 :: 'N bits) . + (let (result :: 'N bits) = w__3 in + return (done1, result)))) + else if (((type2 = FPType_QNaN))) then + (let done1 = True in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__4 :: 'N bits) . + (let (result :: 'N bits) = w__4 in + return (done1, result)))) + else if (((type3 = FPType_QNaN))) then + (let done1 = True in + (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__5 :: 'N bits) . + (let (result :: 'N bits) = w__5 in + return (done1, result)))) + else + (let (done1 :: bool) = False in + (let (result :: 'N bits) = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in + return (done1, result))))))" + + +(*val FPProcessNaNs : forall 'N . Size 'N => FPType -> FPType -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*) + +definition FPProcessNaNs :: " FPType \ FPType \('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(bool*('N::len)Word.word),(exception))monad " where + " FPProcessNaNs type1 type2 op1 op2 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + if (((type1 = FPType_SNaN))) then + (let done1 = True in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let (result :: 'N bits) = w__0 in + return (done1, result)))) + else if (((type2 = FPType_SNaN))) then + (let done1 = True in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__1 :: 'N bits) . + (let (result :: 'N bits) = w__1 in + return (done1, result)))) + else if (((type1 = FPType_QNaN))) then + (let done1 = True in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__2 :: 'N bits) . + (let (result :: 'N bits) = w__2 in + return (done1, result)))) + else if (((type2 = FPType_QNaN))) then + (let done1 = True in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \ (\ (w__3 :: 'N bits) . + (let (result :: 'N bits) = w__3 in + return (done1, result)))) + else + (let (done1 :: bool) = False in + (let (result :: 'N bits) = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in + return (done1, result))))))" + + +(*val CurrentInstrSet : unit -> M InstrSet*) + +definition CurrentInstrSet :: " unit \((register_value),(InstrSet),(exception))monad " where + " CurrentInstrSet _ = ( + undefined_InstrSet () \ (\ (result :: InstrSet) . + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let (result :: InstrSet) = + (if ((((ProcState_T w__1) = (vec_of_bits [B0] :: 1 Word.word)))) then InstrSet_A32 + else InstrSet_T32) in + return result)) + else return InstrSet_A64)))" + + +(*val AArch32_ExecutingLSMInstr : unit -> M bool*) + +definition AArch32_ExecutingLSMInstr :: " unit \((register_value),(bool),(exception))monad " where + " AArch32_ExecutingLSMInstr _ = ( + (ThisInstr0 () :: ( 32 Word.word) M) \ (\ (instr :: 32 bits) . + CurrentInstrSet () \ (\ (instr_set :: InstrSet) . + assert_exp ((((((instr_set = InstrSet_A32))) \ (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \ + (if (((instr_set = InstrSet_A32))) then + return ((((((((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) \ (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))) \ (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) + else + ThisInstrLength () \ (\ (w__0 :: ii) . + return (if (((((ex_int w__0)) = (( 16 :: int)::ii)))) then + (((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)) + else + ((((((slice0 instr (( 25 :: int)::ii) (( 7 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0] :: 7 Word.word)))) \ ((((vec_of_bits [access_vec_dec instr (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))))))))" + + +(*val AArch32_ExecutingCP10or11Instr : unit -> M bool*) + +definition AArch32_ExecutingCP10or11Instr :: " unit \((register_value),(bool),(exception))monad " where + " AArch32_ExecutingCP10or11Instr _ = ( + (ThisInstr0 () :: ( 32 Word.word) M) \ (\ (instr :: 32 bits) . + CurrentInstrSet () \ (\ (instr_set :: InstrSet) . + assert_exp ((((((instr_set = InstrSet_A32))) \ (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \ + return (if (((instr_set = InstrSet_A32))) then + (((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \ (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) \ (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 4 Word.word)) = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word))))) + else + (((((((((and_vec ((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \ ((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \ (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))))))))) \ (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 4 Word.word)) = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))))))))" + + +(*val HaveAnyAArch64 : unit -> bool*) + +definition HaveAnyAArch64 :: " unit \ bool " where + " HaveAnyAArch64 _ = ( \ ((HighestELUsingAArch32 () )))" + + +(*val AArch32_ReportDeferredSError : mword ty2 -> mword ty1 -> M (mword ty32)*) + +definition AArch32_ReportDeferredSError :: "(2)Word.word \(1)Word.word \((register_value),((32)Word.word),(exception))monad " where + " AArch32_ReportDeferredSError AET ExT = ( + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (target :: 32 bits) . + (let (target :: 32 bits) = + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) in + (let (syndrome :: 16 bits) = ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (if ((((ProcState_EL w__0) = EL2))) then + (let (syndrome :: 16 bits) = + ((update_subrange_vec_dec syndrome (( 11 :: int)::ii) (( 10 :: int)::ii) AET :: 16 Word.word)) in + (let (syndrome :: 16 bits) = + ((update_subrange_vec_dec syndrome (( 9 :: int)::ii) (( 9 :: int)::ii) ExT :: 16 Word.word)) in + (let (syndrome :: 16 bits) = + ((update_subrange_vec_dec syndrome (( 5 :: int)::ii) (( 0 :: int)::ii) + (vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word) + :: 16 Word.word)) in + return syndrome))) + else + (let syndrome = ((update_subrange_vec_dec syndrome (( 15 :: int)::ii) (( 14 :: int)::ii) AET :: 16 Word.word)) in + (let syndrome = ((update_subrange_vec_dec syndrome (( 12 :: int)::ii) (( 12 :: int)::ii) ExT :: 16 Word.word)) in + (read_reg TTBCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + (let syndrome = + ((update_subrange_vec_dec syndrome (( 9 :: int)::ii) (( 9 :: int)::ii) + (vec_of_bits [access_vec_dec w__1 (( 31 :: int)::ii)] :: 1 Word.word) + :: 16 Word.word)) in + (read_reg TTBCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + (let (syndrome :: 16 bits) = + (if ((((vec_of_bits [access_vec_dec w__2 (( 31 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (update_subrange_vec_dec syndrome (( 5 :: int)::ii) (( 0 :: int)::ii) + (vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word) + :: 16 Word.word) + else + (let (tup__0, tup__1) = + ((vec_of_bits [B1] :: 1 Word.word), (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)) in + (let (syndrome :: 16 bits) = + ((update_subrange_vec_dec syndrome (( 10 :: int)::ii) (( 10 :: int)::ii) tup__0 :: 16 Word.word)) in + (update_subrange_vec_dec syndrome (( 3 :: int)::ii) (( 0 :: int)::ii) tup__1 :: 16 Word.word)))) in + return syndrome))))))) \ (\ (syndrome :: 16 bits) . + if ((HaveAnyAArch64 () )) then + (ZeroExtend__0 syndrome ((make_the_value (( 25 :: int)::ii) :: 25 itself)) :: ( 25 Word.word) M) \ (\ (w__3 :: + 25 Word.word) . + (let (target :: 32 bits) = ((update_subrange_vec_dec target (( 24 :: int)::ii) (( 0 :: int)::ii) w__3 :: 32 Word.word)) in + return target)) + else + (let (target :: 32 bits) = + ((update_subrange_vec_dec target (( 15 :: int)::ii) (( 0 :: int)::ii) syndrome :: 32 Word.word)) in + return target)))))))" + + +(*val HaveAArch32EL : mword ty2 -> bool*) + +definition HaveAArch32EL :: "(2)Word.word \ bool " where + " HaveAArch32EL el = ( + if ((\ ((HaveEL el)))) then False + else if ((\ ((HaveAnyAArch32 () )))) then False + else if ((HighestELUsingAArch32 () )) then True + else if (((el = ((HighestEL () :: 2 Word.word))))) then False + else if (((el = EL0))) then True + else True )" + + +(*val AArch64_ResetSpecialRegisters : unit -> M unit*) + +definition AArch64_ResetSpecialRegisters :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_ResetSpecialRegisters _ = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (write_reg SP_EL0_ref w__0 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 bits) . + (write_reg SP_EL1_ref w__1 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__2 :: 32 bits) . + (write_reg SPSR_EL1_ref w__2 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__3 :: 64 bits) . + ((((write_reg ELR_EL1_ref w__3 \ + (if ((HaveEL EL2)) then + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + (write_reg SP_EL2_ref w__4 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__5 :: 32 bits) . + (write_reg SPSR_EL2_ref w__5 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__6 :: 64 bits) . + write_reg ELR_EL2_ref w__6))) + else return () )) \ + (if ((HaveEL EL3)) then + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + (write_reg SP_EL3_ref w__7 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__8 :: 32 bits) . + (write_reg SPSR_EL3_ref w__8 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__9 :: 64 bits) . + write_reg ELR_EL3_ref w__9))) + else return () )) \ + (if ((HaveAArch32EL EL1)) then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + (write_reg SPSR_fiq_ref w__10 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__11 :: 32 bits) . + (write_reg SPSR_irq_ref w__11 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__12 :: 32 bits) . + (write_reg SPSR_abt_ref w__12 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__13 :: 32 bits) . + write_reg SPSR_und_ref w__13)))) + else return () )) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__14 :: 64 bits) . + (write_reg DLR_EL0_ref w__14 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__15 :: 32 bits) . + write_reg DSPSR_EL0_ref w__15)))))))" + + +(*val Halted : unit -> M bool*) + +definition Halted :: " unit \((register_value),(bool),(exception))monad " where + " Halted _ = ( + or_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))))) + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return (((((slice0 w__1 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))))) \ (\ (w__2 :: bool) . + return ((\ w__2))))" + + +(*val FPUnpackBase : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +definition FPUnpackBase :: "('N::len)Word.word \(32)Word.word \((register_value),(FPType*(1)Word.word*real),(exception))monad " where + " FPUnpackBase fpval fpcr = ( + (assert_exp ((((((((int (size fpval))) = (( 16 :: int)::ii)))) \ ((((((((int (size fpval))) = (( 32 :: int)::ii)))) \ (((((int (size fpval))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \ (\ (frac64 :: 52 bits) . + (undefined_bitvector (( 11 :: int)::ii) :: ( 11 Word.word) M) \ (\ (exp64 :: 11 bits) . + (undefined_bitvector (( 23 :: int)::ii) :: ( 23 Word.word) M) \ (\ (frac32 :: 23 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (exp32 :: 8 bits) . + undefined_real () \ (\ (value_name :: real) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (undefined_bitvector (( 10 :: int)::ii) :: ( 10 Word.word) M) \ (\ (frac16 :: 10 bits) . + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (exp16 :: 5 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + (if (((((int (size fpval))) = (( 16 :: int)::ii)))) then + (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (exp16 :: 5 bits) = ((slice0 fpval (( 10 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (frac16 :: 10 bits) = ((slice0 fpval (( 0 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) in + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsZero exp16)) then + (let ((typ1 :: FPType), (value_name :: real)) = + (if (((((IsZero frac16)) \ ((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let (typ1 :: FPType) = FPType_Zero in + (let (value_name :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (typ1, value_name))) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 14 :: int)::ii))))) * + (((((real_of_int ((Word.uint frac16))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 10 :: int)::ii)))))))) in + (typ1, value_name)))) in + (typ1, value_name)) + else + (let ((typ1 :: FPType), (value_name :: real)) = + (if (((((IsOnes exp16)) \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsZero frac16)) then + (let (typ1 :: FPType) = FPType_Infinity in + (let (value_name :: real) = (realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 1000000 :: int)::ii)) in + (typ1, value_name))) + else + (let (typ1 :: FPType) = + (if ((((vec_of_bits [access_vec_dec frac16 (( 9 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + FPType_QNaN + else FPType_SNaN) in + (let (value_name :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (typ1, value_name)))) in + (typ1, value_name)) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((((Word.uint exp16)) - (( 15 :: int)::ii))))) + * + (((realFromFrac(( 10 :: int))(( 10 :: int))) + + (((((real_of_int ((Word.uint frac16))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 10 :: int)::ii)))))))))) in + (typ1, value_name)))) in + (typ1, value_name))) in + return (sign, typ1, value_name))))) + else if (((((int (size fpval))) = (( 32 :: int)::ii)))) then + (let sign = ((vec_of_bits [access_vec_dec fpval (( 31 :: int)::ii)] :: 1 Word.word)) in + (let exp32 = ((slice0 fpval (( 23 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let frac32 = ((slice0 fpval (( 0 :: int)::ii) (( 23 :: int)::ii) :: 23 Word.word)) in + (if ((IsZero exp32)) then + if (((((IsZero frac32)) \ ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let typ1 = FPType_Zero in + (let value_name = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (if ((\ ((IsZero frac32)))) then FPProcessException FPExc_InputDenorm fpcr + else return () ) \ + return (typ1, value_name))) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 126 :: int)::ii))))) * + (((((real_of_int ((Word.uint frac32))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 23 :: int)::ii)))))))) in + return (typ1, value_name))) + else + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsOnes exp32)) then + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsZero frac32)) then + (let (typ1 :: FPType) = FPType_Infinity in + (let (value_name :: real) = (realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 1000000 :: int)::ii)) in + (typ1, value_name))) + else + (let (typ1 :: FPType) = + (if ((((vec_of_bits [access_vec_dec frac32 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + FPType_QNaN + else FPType_SNaN) in + (let (value_name :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (typ1, value_name)))) in + (typ1, value_name)) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((((Word.uint exp32)) - (( 127 :: int)::ii))))) + * + (((realFromFrac(( 10 :: int))(( 10 :: int))) + + (((((real_of_int ((Word.uint frac32))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 23 :: int)::ii)))))))))) in + (typ1, value_name)))) in + return (typ1, value_name))) \ (\ varstup . (let ((typ1 :: FPType), (value_name :: real)) = varstup in + return (sign, typ1, value_name)))))) + else + (let sign = ((vec_of_bits [access_vec_dec fpval (( 63 :: int)::ii)] :: 1 Word.word)) in + (let exp64 = ((slice0 fpval (( 52 :: int)::ii) (( 11 :: int)::ii) :: 11 Word.word)) in + (let frac64 = ((slice0 fpval (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in + (if ((IsZero exp64)) then + if (((((IsZero frac64)) \ ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let typ1 = FPType_Zero in + (let value_name = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (if ((\ ((IsZero frac64)))) then FPProcessException FPExc_InputDenorm fpcr + else return () ) \ + return (typ1, value_name))) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 1022 :: int)::ii))))) * + (((((real_of_int ((Word.uint frac64))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 52 :: int)::ii)))))))) in + return (typ1, value_name))) + else + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsOnes exp64)) then + (let ((typ1 :: FPType), (value_name :: real)) = + (if ((IsZero frac64)) then + (let (typ1 :: FPType) = FPType_Infinity in + (let (value_name :: real) = (realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) (( 1000000 :: int)::ii)) in + (typ1, value_name))) + else + (let (typ1 :: FPType) = + (if ((((vec_of_bits [access_vec_dec frac64 (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + FPType_QNaN + else FPType_SNaN) in + (let (value_name :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in + (typ1, value_name)))) in + (typ1, value_name)) + else + (let (typ1 :: FPType) = FPType_Nonzero in + (let (value_name :: real) = + (((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((((Word.uint exp64)) - (( 1023 :: int)::ii))))) + * + (((realFromFrac(( 10 :: int))(( 10 :: int))) + + (((((real_of_int ((Word.uint frac64))))) * + ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 52 :: int)::ii)))))))))) in + (typ1, value_name)))) in + return (typ1, value_name))) \ (\ varstup . (let ((typ1 :: FPType), (value_name :: real)) = varstup in + return (sign, typ1, value_name))))))) \ (\ varstup . (let ((sign :: 1 bits), (typ1 :: FPType), (value_name :: + real)) = varstup in + (let (value_name :: real) = + (if (((sign = (vec_of_bits [B1] :: 1 Word.word)))) then - value_name + else value_name) in + return (typ1, sign, value_name))))))))))))))" + + +(*val FPUnpackCV : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +definition FPUnpackCV :: "('N::len)Word.word \(32)Word.word \((register_value),(FPType*(1)Word.word*real),(exception))monad " where + " FPUnpackCV fpval fpcr__arg = ( + (let fpcr = fpcr__arg in + (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (fp_type :: FPType) . + (FPUnpackBase fpval fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let (fp_type :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + return (fp_type, sign, value_name))))))))))))" + + +(*val FPConvert__0 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> FPRounding -> M (mword 'M)*) + +(*val FPConvert__1 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> M (mword 'M)*) + +definition FPConvert__0 :: " int \('N::len)Word.word \(32)Word.word \ FPRounding \((register_value),(('M::len)Word.word),(exception))monad " where + " FPConvert__0 (M__tv :: int) op1 fpcr rounding = ( + (let l__158 = M__tv in + if (((l__158 = (( 16 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpackCV op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (let (alt_hp :: bool) = + (True \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) in + (if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + (if alt_hp then (FPZero (( 16 :: int)::ii) sign :: ( 16 Word.word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (FPDefaultNaN (( 16 :: int)::ii) () :: ( 16 Word.word) M) + else (FPConvertNaN (( 16 :: int)::ii) op1 :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (if ((((((typ1 = FPType_SNaN))) \ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else return () ) \ + return result) + else if (((typ1 = FPType_Infinity))) then + if alt_hp then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 itself)) + :: 15 Word.word)) + :: 16 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ return result) + else (FPInfinity (( 16 :: int)::ii) sign :: ( 16 Word.word) M) + else if (((typ1 = FPType_Zero))) then (FPZero (( 16 :: int)::ii) sign :: ( 16 Word.word) M) + else (FPRoundCV (( 16 :: int)::ii) value_name fpcr rounding :: ( 16 Word.word) M)) \ (\ (result :: 16 + bits) . + return ((Word.ucast result :: ( 'M::len)Word.word))))))))))))) + else if (((l__158 = (( 32 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpackCV op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (let (alt_hp :: bool) = + (False \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) in + (if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + (if alt_hp then (FPZero (( 32 :: int)::ii) sign :: ( 32 Word.word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (FPDefaultNaN (( 32 :: int)::ii) () :: ( 32 Word.word) M) + else (FPConvertNaN (( 32 :: int)::ii) op1 :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (if ((((((typ1 = FPType_SNaN))) \ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else return () ) \ + return result) + else if (((typ1 = FPType_Infinity))) then + if alt_hp then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 itself)) + :: 31 Word.word)) + :: 32 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ return result) + else (FPInfinity (( 32 :: int)::ii) sign :: ( 32 Word.word) M) + else if (((typ1 = FPType_Zero))) then (FPZero (( 32 :: int)::ii) sign :: ( 32 Word.word) M) + else (FPRoundCV (( 32 :: int)::ii) value_name fpcr rounding :: ( 32 Word.word) M)) \ (\ (result :: 32 + bits) . + return ((Word.ucast result :: ( 'M::len)Word.word))))))))))))) + else if (((l__158 = (( 64 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpackCV op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (let (alt_hp :: bool) = + (False \ ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) in + (if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + (if alt_hp then (FPZero (( 64 :: int)::ii) sign :: ( 64 Word.word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (FPDefaultNaN (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (FPConvertNaN (( 64 :: int)::ii) op1 :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (if ((((((typ1 = FPType_SNaN))) \ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else return () ) \ + return result) + else if (((typ1 = FPType_Infinity))) then + if alt_hp then + (let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 itself)) + :: 63 Word.word)) + :: 64 Word.word)) in + FPProcessException FPExc_InvalidOp fpcr \ return result) + else (FPInfinity (( 64 :: int)::ii) sign :: ( 64 Word.word) M) + else if (((typ1 = FPType_Zero))) then (FPZero (( 64 :: int)::ii) sign :: ( 64 Word.word) M) + else (FPRoundCV (( 64 :: int)::ii) value_name fpcr rounding :: ( 64 Word.word) M)) \ (\ (result :: 64 + bits) . + return ((Word.ucast result :: ( 'M::len)Word.word))))))))))))) + else assert_exp False ('''') \ exit0 () ))" + + +definition FPConvert__1 :: " int \('N::len)Word.word \(32)Word.word \((register_value),(('M::len)Word.word),(exception))monad " where + " FPConvert__1 (M__tv :: int) op1 fpcr = ( + (FPConvert__0 M__tv op1 fpcr ((FPRoundingMode fpcr)) :: (( 'M::len)Word.word) M))" + + +(*val FPUnpack : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +definition FPUnpack :: "('N::len)Word.word \(32)Word.word \((register_value),(FPType*(1)Word.word*real),(exception))monad " where + " FPUnpack fpval fpcr__arg = ( + (let fpcr = fpcr__arg in + (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (fp_type :: FPType) . + (FPUnpackBase fpval fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let (fp_type :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + return (fp_type, sign, value_name))))))))))))" + + +(*val FPToFixedJS : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> mword ty32 -> bool -> M (mword 'N)*) + +definition FPToFixedJS :: " int \('M::len)Word.word \(32)Word.word \ bool \((register_value),(('N::len)Word.word),(exception))monad " where + " FPToFixedJS (N__tv :: int) op1 fpcr Is64 = ( + (assert_exp ((((((((int (size op1))) = (( 64 :: int)::ii)))) \ (((N__tv = (( 32 :: int)::ii))))))) (''((M == 64) && (N == 32))'') \ + undefined_real () ) \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (let (Z :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + FPProcessException FPExc_InvalidOp fpcr \ + ((let (Z :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + return Z)) + else return Z) \ (\ (Z :: 1 bits) . + (let (int_result :: ii) = (floor value_name) in + (let (error :: real) = (value_name - (((real_of_int int_result)))) in + (let (round_it_up :: bool) = + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((ex_int int_result)) < (( 0 :: int)::ii)))) in + (let (int_result :: ii) = + (if round_it_up then ((ex_int int_result)) + (( 1 :: int)::ii) + else int_result) in + undefined_int () \ (\ (result :: ii) . + (let (result :: ii) = + (if ((((ex_int int_result)) < (( 0 :: int)::ii))) then + ((ex_int int_result)) - + ((((pow2 (( 32 :: int)::ii))) * + ((ex_int + ((ceiling + (((((real_of_int int_result))) div (((real_of_int ((pow2 (( 32 :: int)::ii)))))))))))))) + else + ((ex_int int_result)) - + ((((pow2 (( 32 :: int)::ii))) * + ((ex_int + ((floor + (((((real_of_int int_result))) div (((real_of_int ((pow2 (( 32 :: int)::ii))))))))))))))) in + (if (((((((ex_int int_result)) < ((- ((pow2 (( 31 :: int)::ii))))))) \ ((((ex_int int_result)) > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then + FPProcessException FPExc_InvalidOp fpcr \ + ((let (Z :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + return Z)) + else if (((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) then + FPProcessException FPExc_Inexact fpcr \ + ((let (Z :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + return Z)) + else return Z) \ (\ (Z :: 1 bits) . + (let (Z :: 1 bits) = + (if ((((((sign = (vec_of_bits [B1] :: 1 Word.word)))) \ (((value_name = (realFromFrac(( 0 :: int))(( 10 :: int))))))))) then + (vec_of_bits [B0] :: 1 Word.word) + else Z) in + (let (result :: ii) = (if (((typ1 = FPType_Infinity))) then (( 0 :: int)::ii) else result) in + (if Is64 then + (let split_vec = + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) Z :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))) + else + (read_reg FPSCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + write_reg + FPSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii) + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) Z :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word)) + :: 32 Word.word)))) \ + return ((Word.ucast + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word)) + :: ( 'N::len)Word.word))))))))))))))))))))))" + + +(*val FPToFixed : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'M)*) + +definition FPToFixed :: " int \('N::len)Word.word \ int \ bool \(32)Word.word \ FPRounding \((register_value),(('M::len)Word.word),(exception))monad " where + " FPToFixed (M__tv :: int) op1 fbits unsigned fpcr rounding = ( + ((((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + assert_exp ((((((M__tv = (( 16 :: int)::ii)))) \ ((((((M__tv = (( 32 :: int)::ii)))) \ (((M__tv = (( 64 :: int)::ii)))))))))) (''((M == 16) || ((M == 32) || (M == 64)))'')) \ + assert_exp ((fbits \ (( 0 :: int)::ii))) (''(fbits >= 0)'')) \ + assert_exp (((rounding \ FPRounding_ODD))) (''(rounding != FPRounding_ODD)'')) \ + undefined_real () ) \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + FPProcessException FPExc_InvalidOp fpcr + else return () ) \ + ((let value_name = (value_name * ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) fbits))) in + (let (int_result :: ii) = (floor value_name) in + (let (error :: real) = (value_name - (((real_of_int int_result)))) in + undefined_bool () \ (\ (round_up :: bool) . + (let (round_up :: bool) = + ((case rounding of + FPRounding_TIEEVEN => + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) int_result (( 0 :: int)::ii) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))) + | FPRounding_POSINF => (error \ (realFromFrac(( 0 :: int))(( 10 :: int)))) + | FPRounding_NEGINF => False + | FPRounding_ZERO => + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((ex_int int_result)) < (( 0 :: int)::ii)))) + | FPRounding_TIEAWAY => + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ ((((ex_int int_result)) \ (( 0 :: int)::ii))))))) + )) in + (let (int_result :: ii) = (if round_up then ((ex_int int_result)) + (( 1 :: int)::ii) else int_result) in + undefined_bool () \ (\ (overflow :: bool) . + (undefined_bitvector M__tv :: (( 'M::len)Word.word) M) \ (\ (result :: 'M bits) . + (SatQ int_result ((make_the_value ((int (size result))) :: ( 'M::len)itself)) unsigned + :: ((( 'M::len)Word.word * bool)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in + (let overflow = tup__1 in + (if overflow then FPProcessException FPExc_InvalidOp fpcr + else if (((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr + else return () ) \ + return result))))))))))))))))))))))" + + +(*val FPSqrt : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPSqrt :: "('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPSqrt op1 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + (FPProcessNaN typ1 op1 fpcr :: (( 'N::len)Word.word) M) + else if (((typ1 = FPType_Zero))) then (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else if ((((((typ1 = FPType_Infinity))) \ (((sign = (vec_of_bits [B0] :: 1 Word.word))))))) + then + (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else if (((sign = (vec_of_bits [B1] :: 1 Word.word)))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \ (\ (w__3 :: 'N bits) . + (let result = w__3 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else (FPRound__1 ((int (size op1))) ((sqrt value_name)) fpcr :: (( 'N::len)Word.word) M)))))))))))" + + +(*val FPRoundInt : forall 'N . Size 'N => mword 'N -> mword ty32 -> FPRounding -> bool -> M (mword 'N)*) + +definition FPRoundInt :: "('N::len)Word.word \(32)Word.word \ FPRounding \ bool \((register_value),(('N::len)Word.word),(exception))monad " where + " FPRoundInt op1 fpcr rounding exact = ( + ((assert_exp (((rounding \ FPRounding_ODD))) (''(rounding != FPRounding_ODD)'') \ + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'')) \ + undefined_real () ) \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typ1 = tup__0 in + (let sign = tup__1 in + (let value_name = tup__2 in + undefined_real () \ (\ (real_result :: real) . + undefined_bool () \ (\ (round_up :: bool) . + undefined_real () \ (\ (error :: real) . + undefined_int () \ (\ (int_result :: ii) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + if ((((((typ1 = FPType_SNaN))) \ (((typ1 = FPType_QNaN)))))) then + (FPProcessNaN typ1 op1 fpcr :: (( 'N::len)Word.word) M) + else if (((typ1 = FPType_Infinity))) then (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else if (((typ1 = FPType_Zero))) then (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else + (let int_result = (floor value_name) in + (let error = (value_name - (((real_of_int int_result)))) in + (let (round_up :: bool) = + ((case rounding of + FPRounding_TIEEVEN => + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) int_result (( 0 :: int)::ii) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))) + | FPRounding_POSINF => (error \ (realFromFrac(( 0 :: int))(( 10 :: int)))) + | FPRounding_NEGINF => False + | FPRounding_ZERO => + ((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ ((((ex_int int_result)) < (( 0 :: int)::ii)))) + | FPRounding_TIEAWAY => + (((error > (realFromFrac(( 5 :: int))(( 10 :: int))))) \ ((((((error = (realFromFrac(( 5 :: int))(( 10 :: int)))))) \ ((((ex_int int_result)) \ (( 0 :: int)::ii))))))) + )) in + (let (int_result :: ii) = + (if round_up then ((ex_int int_result)) + (( 1 :: int)::ii) + else int_result) in + (let real_result = ((real_of_int int_result)) in + (if (((real_result = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else (FPRound__0 ((int (size op1))) real_result fpcr FPRounding_ZERO :: (( 'N::len)Word.word) M)) \ (\ (result :: 'N + bits) . + (if ((((((error \ (realFromFrac(( 0 :: int))(( 10 :: int)))))) \ exact))) then + FPProcessException FPExc_Inexact fpcr + else return () ) \ + return result))))))))))))))))))))" + + +(*val FPCompare : forall 'N . Size 'N => mword 'N -> mword 'N -> bool -> mword ty32 -> M (mword ty4)*) + +definition FPCompare :: "('N::len)Word.word \('N::len)Word.word \ bool \(32)Word.word \((register_value),((4)Word.word),(exception))monad " where + " FPCompare op1 op2 signal_nans fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (result :: 4 bits) . + if ((((((((((((type1 = FPType_SNaN))) \ (((type1 = FPType_QNaN)))))) \ (((type2 = FPType_SNaN)))))) \ (((type2 = FPType_QNaN)))))) then + (let result = ((vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)) in + (if (((((((((type1 = FPType_SNaN))) \ (((type2 = FPType_SNaN)))))) \ signal_nans))) then + FPProcessException FPExc_InvalidOp fpcr + else return () ) \ + return result) + else + (let (result :: 4 bits) = + (if (((value1_name = value2_name))) then (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word) + else if ((value1_name < value2_name)) then (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word) + else (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)) in + return result)))))))))))))))))))" + + +(*val FPSub : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPSub :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPSub op1 op2 fpcr = ( + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (rounding :: FPRounding) = (FPRoundingMode fpcr) in + undefined_real () \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (result_sign :: 1 bits) . + undefined_real () \ (\ (result_value :: real) . + undefined_bool () \ (\ (zero2 :: bool) . + undefined_bool () \ (\ (zero1 :: bool) . + undefined_bool () \ (\ (inf2 :: bool) . + undefined_bool () \ (\ (inf1 :: bool) . + if ((\ done1)) then + (let inf1 = (type1 = FPType_Infinity) in + (let inf2 = (type2 = FPType_Infinity) in + (let zero1 = (type1 = FPType_Zero) in + (let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 \ inf2))) \ (((sign1 = sign2)))))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let result = w__0 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else if ((((((inf1 \ (((sign1 = (vec_of_bits [B0] :: 1 Word.word))))))) \ (((inf2 \ (((sign2 = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((inf1 \ (((sign1 = (vec_of_bits [B1] :: 1 Word.word))))))) \ (((inf2 \ (((sign2 = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B1] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((zero1 \ zero2))) \ (((sign1 = ((not_vec sign2 :: 1 Word.word)))))))) + then + (FPZero ((int (size op1))) sign1 :: (( 'N::len)Word.word) M) + else + (let result_value = (value1_name - value2_name) in + if (((result_value = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then + (let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + (FPZero ((int (size op1))) result_sign :: (( 'N::len)Word.word) M)) + else (FPRound__0 ((int (size op1))) result_value fpcr rounding :: (( 'N::len)Word.word) M)))))) + else return result)))))))))))))))))))))))))))))))" + + +(*val FPMulAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMulAdd :: "('N::len)Word.word \('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMulAdd addend op1 op2 fpcr = ( + assert_exp ((((((((int (size addend))) = (( 16 :: int)::ii)))) \ ((((((((int (size addend))) = (( 32 :: int)::ii)))) \ (((((int (size addend))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (rounding :: FPRounding) = (FPRoundingMode fpcr) in + undefined_real () \ (\ (valueA_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (signA :: 1 bits) . + undefined_FPType () \ (\ (typeA :: FPType) . + (FPUnpack addend fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let typeA = tup__0 in + (let signA = tup__1 in + (let valueA_name = tup__2 in + undefined_real () \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (let (inf1 :: bool) = (type1 = FPType_Infinity) in + (let (zero1 :: bool) = (type1 = FPType_Zero) in + (let (inf2 :: bool) = (type2 = FPType_Infinity) in + (let (zero2 :: bool) = (type2 = FPType_Zero) in + (undefined_bitvector ((int (size addend))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs3 typeA type1 type2 addend op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + (if ((((((typeA = FPType_QNaN))) \ ((((((inf1 \ zero2))) \ (((zero1 \ inf2))))))))) then + (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let result = w__0 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else return result) \ (\ (result :: 'N bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (result_sign :: 1 bits) . + undefined_real () \ (\ (result_value :: real) . + undefined_bool () \ (\ (zeroP :: bool) . + undefined_bool () \ (\ (infP :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (signP :: 1 bits) . + undefined_bool () \ (\ (zeroA :: bool) . + undefined_bool () \ (\ (infA :: bool) . + if ((\ done1)) then + (let infA = (typeA = FPType_Infinity) in + (let zeroA = (typeA = FPType_Zero) in + (let signP = ((xor_vec sign1 sign2 :: 1 Word.word)) in + (let infP = (inf1 \ inf2) in + (let zeroP = (zero1 \ zero2) in + if (((((((((inf1 \ zero2))) \ (((zero1 \ inf2)))))) \ ((((((infA \ infP))) \ (((signA \ signP))))))))) then + (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \ (\ (w__1 :: 'N bits) . + (let result = w__1 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else if ((((((infA \ (((signA = (vec_of_bits [B0] :: 1 Word.word))))))) \ (((infP \ (((signP = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size addend))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((infA \ (((signA = (vec_of_bits [B1] :: 1 Word.word))))))) \ (((infP \ (((signP = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size addend))) (vec_of_bits [B1] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((zeroA \ zeroP))) \ (((signA = signP)))))) then + (FPZero ((int (size addend))) signA :: (( 'N::len)Word.word) M) + else + (let result_value = (valueA_name + ((value1_name * value2_name))) in + if (((result_value = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then + (let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + (FPZero ((int (size addend))) result_sign :: (( 'N::len)Word.word) M)) + else (FPRound__1 ((int (size addend))) result_value fpcr :: (( 'N::len)Word.word) M))))))) + else return result)))))))))))))))))))))))))))))))))))))))))))))" + + +(*val FPMul : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMul :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMul op1 op2 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + undefined_bool () \ (\ (zero2 :: bool) . + undefined_bool () \ (\ (zero1 :: bool) . + undefined_bool () \ (\ (inf2 :: bool) . + undefined_bool () \ (\ (inf1 :: bool) . + if ((\ done1)) then + (let inf1 = (type1 = FPType_Infinity) in + (let inf2 = (type2 = FPType_Infinity) in + (let zero1 = (type1 = FPType_Zero) in + (let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 \ zero2))) \ (((zero1 \ inf2)))))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let result = w__0 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else if (((inf1 \ inf2))) then + (FPInfinity ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) + else if (((zero1 \ zero2))) then + (FPZero ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) + else (FPRound__1 ((int (size op1))) ((value1_name * value2_name)) fpcr :: (( 'N::len)Word.word) M))))) + else return result)))))))))))))))))))))))))))" + + +(*val FPMin : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMin :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMin op1 op2 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + if ((\ done1)) then + (let ((sign :: 1 bits), (typ1 :: FPType), (value_name :: real)) = + (if ((value1_name < value2_name)) then + (let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in + (let (typ1 :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + (sign, typ1, value_name))))) + else + (let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in + (let (typ1 :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + (sign, typ1, value_name)))))) in + if (((typ1 = FPType_Infinity))) then (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else if (((typ1 = FPType_Zero))) then + (let sign = ((or_vec sign1 sign2 :: 1 Word.word)) in + (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M)) + else (FPRound__1 ((int (size op1))) value_name fpcr :: (( 'N::len)Word.word) M)) + else return result))))))))))))))))))))))))))" + + +(*val FPMinNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMinNum :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMinNum op1__arg op2__arg fpcr = ( + (let op1 = op1__arg in + (let op2 = op2__arg in + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (anon20 :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (anon10 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let anon10 = tup__1 in + (let anon20 = tup__2 in + undefined_real () \ (\ (anon40 :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (anon30 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let anon30 = tup__1 in + (let anon40 = tup__2 in + (if ((((((type1 = FPType_QNaN))) \ (((type2 \ FPType_QNaN)))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) \ (\ (w__0 :: + ( 'N::len)Word.word) . + (let (op1 :: ( 'N::len)Word.word) = w__0 in + return (op1, op2))) + else + (if ((((((type1 \ FPType_QNaN))) \ (((type2 = FPType_QNaN)))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else return op2) \ (\ (op2 :: ( 'N::len)Word.word) . + return (op1, op2))) \ (\ varstup . (let ((op1 :: ( 'N::len)Word.word), (op2 :: ( 'N::len)Word.word)) = varstup in + (FPMin op1 op2 fpcr :: (( 'N::len)Word.word) M))))))))))))))))))))))" + + +(*val FPMax : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMax :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMax op1 op2 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + undefined_real () \ (\ (value_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign :: 1 bits) . + undefined_FPType () \ (\ (typ1 :: FPType) . + if ((\ done1)) then + (let ((sign :: 1 bits), (typ1 :: FPType), (value_name :: real)) = + (if ((value1_name > value2_name)) then + (let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in + (let (typ1 :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + (sign, typ1, value_name))))) + else + (let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in + (let (typ1 :: FPType) = tup__0 in + (let (sign :: 1 bits) = tup__1 in + (let (value_name :: real) = tup__2 in + (sign, typ1, value_name)))))) in + if (((typ1 = FPType_Infinity))) then (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) + else if (((typ1 = FPType_Zero))) then + (let sign = ((and_vec sign1 sign2 :: 1 Word.word)) in + (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M)) + else (FPRound__1 ((int (size op1))) value_name fpcr :: (( 'N::len)Word.word) M)) + else return result))))))))))))))))))))))))))" + + +(*val FPMaxNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPMaxNum :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPMaxNum op1__arg op2__arg fpcr = ( + (let op1 = op1__arg in + (let op2 = op2__arg in + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (anon20 :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (anon10 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let anon10 = tup__1 in + (let anon20 = tup__2 in + undefined_real () \ (\ (anon40 :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (anon30 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let anon30 = tup__1 in + (let anon40 = tup__2 in + (if ((((((type1 = FPType_QNaN))) \ (((type2 \ FPType_QNaN)))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B1] :: 1 Word.word) :: (( 'N::len)Word.word) M) \ (\ (w__0 :: + ( 'N::len)Word.word) . + (let (op1 :: ( 'N::len)Word.word) = w__0 in + return (op1, op2))) + else + (if ((((((type1 \ FPType_QNaN))) \ (((type2 = FPType_QNaN)))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B1] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else return op2) \ (\ (op2 :: ( 'N::len)Word.word) . + return (op1, op2))) \ (\ varstup . (let ((op1 :: ( 'N::len)Word.word), (op2 :: ( 'N::len)Word.word)) = varstup in + (FPMax op1 op2 fpcr :: (( 'N::len)Word.word) M))))))))))))))))))))))" + + +(*val FPDiv : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPDiv :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPDiv op1 op2 fpcr = ( + (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + undefined_real () ) \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + undefined_bool () \ (\ (zero2 :: bool) . + undefined_bool () \ (\ (zero1 :: bool) . + undefined_bool () \ (\ (inf2 :: bool) . + undefined_bool () \ (\ (inf1 :: bool) . + if ((\ done1)) then + (let inf1 = (type1 = FPType_Infinity) in + (let inf2 = (type2 = FPType_Infinity) in + (let zero1 = (type1 = FPType_Zero) in + (let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 \ inf2))) \ (((zero1 \ zero2)))))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let result = w__0 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else if (((inf1 \ zero2))) then + (FPInfinity ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) \ (\ (w__1 :: 'N + bits) . + (let result = w__1 in + (if ((\ inf1)) then FPProcessException FPExc_DivideByZero fpcr + else return () ) \ + return result)) + else if (((zero1 \ inf2))) then + (FPZero ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) + else (FPRound__1 ((int (size op1))) ((value1_name div value2_name)) fpcr :: (( 'N::len)Word.word) M))))) + else return result)))))))))))))))))))))))))))" + + +(*val FPAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +definition FPAdd :: "('N::len)Word.word \('N::len)Word.word \(32)Word.word \((register_value),(('N::len)Word.word),(exception))monad " where + " FPAdd op1 op2 fpcr = ( + assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \ ((((((((int (size op1))) = (( 32 :: int)::ii)))) \ (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \ + ((let (rounding :: FPRounding) = (FPRoundingMode fpcr) in + undefined_real () \ (\ (value1_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign1 :: 1 bits) . + undefined_FPType () \ (\ (type1 :: FPType) . + (FPUnpack op1 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type1 = tup__0 in + (let sign1 = tup__1 in + (let value1_name = tup__2 in + undefined_real () \ (\ (value2_name :: real) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (sign2 :: 1 bits) . + undefined_FPType () \ (\ (type2 :: FPType) . + (FPUnpack op2 fpcr :: ((FPType * 1 Word.word * real)) M) \ (\ varstup . (let (tup__0, tup__1, tup__2) = varstup in + (let type2 = tup__0 in + (let sign2 = tup__1 in + (let value2_name = tup__2 in + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \ (\ (result :: 'N bits) . + undefined_bool () \ (\ (done1 :: bool) . + (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let done1 = tup__0 in + (let result = tup__1 in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (result_sign :: 1 bits) . + undefined_real () \ (\ (result_value :: real) . + undefined_bool () \ (\ (zero2 :: bool) . + undefined_bool () \ (\ (zero1 :: bool) . + undefined_bool () \ (\ (inf2 :: bool) . + undefined_bool () \ (\ (inf1 :: bool) . + if ((\ done1)) then + (let inf1 = (type1 = FPType_Infinity) in + (let inf2 = (type2 = FPType_Infinity) in + (let zero1 = (type1 = FPType_Zero) in + (let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 \ inf2))) \ (((sign1 = ((not_vec sign2 :: 1 Word.word)))))))) then + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \ (\ (w__0 :: 'N bits) . + (let result = w__0 in + FPProcessException FPExc_InvalidOp fpcr \ return result)) + else if ((((((inf1 \ (((sign1 = (vec_of_bits [B0] :: 1 Word.word))))))) \ (((inf2 \ (((sign2 = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B0] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((inf1 \ (((sign1 = (vec_of_bits [B1] :: 1 Word.word))))))) \ (((inf2 \ (((sign2 = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (FPInfinity ((int (size op1))) (vec_of_bits [B1] :: 1 Word.word) :: (( 'N::len)Word.word) M) + else if ((((((zero1 \ zero2))) \ (((sign1 = sign2)))))) then + (FPZero ((int (size op1))) sign1 :: (( 'N::len)Word.word) M) + else + (let result_value = (value1_name + value2_name) in + if (((result_value = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then + (let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + (FPZero ((int (size op1))) result_sign :: (( 'N::len)Word.word) M)) + else (FPRound__0 ((int (size op1))) result_value fpcr rounding :: (( 'N::len)Word.word) M)))))) + else return result)))))))))))))))))))))))))))))))" + + +(*val ExternalSecureInvasiveDebugEnabled : unit -> M bool*) + +definition ExternalSecureInvasiveDebugEnabled :: " unit \((register_value),(bool),(exception))monad " where + " ExternalSecureInvasiveDebugEnabled _ = ( + and_boolM (return ((\ ((HaveEL EL3))))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: bool) . + if w__1 then return False + else + and_boolM ((ExternalInvasiveDebugEnabled () )) + (read_reg SPIDEN_ref \ (\ (w__3 :: signal) . return (((w__3 = HIGH)))))))" + + +(*val ExternalDebugInterruptsDisabled : mword ty2 -> M bool*) + +definition ExternalDebugInterruptsDisabled :: "(2)Word.word \((register_value),(bool),(exception))monad " where + " ExternalDebugInterruptsDisabled target = ( + undefined_bool () \ (\ (int_dis :: bool) . + (let pat0 = target in + if (((pat0 = EL3))) then + and_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return (((((slice0 w__0 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () )) + else if (((pat0 = EL2))) then + and_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 bits) . + return (((((and_vec ((slice0 w__3 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))) + ((ExternalInvasiveDebugEnabled () )) + else + IsSecure () \ (\ (w__6 :: bool) . + if w__6 then + and_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + return (((((and_vec ((slice0 w__7 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))) + ((ExternalSecureInvasiveDebugEnabled () )) + else + and_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + return (((((slice0 w__10 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \ (vec_of_bits [B0,B0] :: 2 Word.word)))))) ((ExternalInvasiveDebugEnabled () ))))))" + + +(*val ELStateUsingAArch32K : mword ty2 -> bool -> M (bool * bool)*) + +definition ELStateUsingAArch32K :: "(2)Word.word \ bool \((register_value),(bool*bool),(exception))monad " where + " ELStateUsingAArch32K el secure = ( + undefined_bool () \ (\ (aarch32 :: bool) . + (let (known :: bool) = True in + undefined_bool () \ (\ (aarch32_at_el1 :: bool) . + undefined_bool () \ (\ (aarch32_below_el3 :: bool) . + (if ((\ ((HaveAArch32EL el)))) then + (let (aarch32 :: bool) = False in + return (aarch32, known)) + else if ((HighestELUsingAArch32 () )) then + (let (aarch32 :: bool) = True in + return (aarch32, known)) + else + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__1 :: bool) . + (let aarch32_below_el3 = w__1 in + or_boolM (return aarch32_below_el3) + (and_boolM + (and_boolM (return (((((HaveEL EL2)) \ ((\ secure)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 31 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (and_boolM + (and_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) (return ((HaveVirtHostExt () ))) \ (\ (w__7 :: + bool) . + return ((\ w__7))))) \ (\ (w__9 :: bool) . + (let aarch32_at_el1 = w__9 in + if ((((((el = EL0))) \ ((\ aarch32_at_el1))))) then + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + if ((((ProcState_EL w__10) = EL0))) then + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (let (aarch32 :: bool) = ((ProcState_nRW w__11) = (vec_of_bits [B1] :: 1 Word.word)) in + return (aarch32, known))) + else + (let (known :: bool) = False in + return (aarch32, known))) + else + (let (aarch32 :: bool) = + ((((aarch32_below_el3 \ (((el \ EL3)))))) \ (((aarch32_at_el1 \ ((((((el = EL1))) \ (((el = EL0)))))))))) in + return (aarch32, known))))))) \ (\ varstup . (let ((aarch32 :: bool), (known :: bool)) = varstup in + (if ((\ known)) then undefined_bool () + else return aarch32) \ (\ (aarch32 :: bool) . + return (known, aarch32)))))))))" + + +(*val ELUsingAArch32K : mword ty2 -> M (bool * bool)*) + +definition ELUsingAArch32K :: "(2)Word.word \((register_value),(bool*bool),(exception))monad " where + " ELUsingAArch32K el = ( IsSecureBelowEL3 () \ (\ (w__0 :: bool) . ELStateUsingAArch32K el w__0))" + + +(*val ELStateUsingAArch32 : mword ty2 -> bool -> M bool*) + +definition ELStateUsingAArch32 :: "(2)Word.word \ bool \((register_value),(bool),(exception))monad " where + " ELStateUsingAArch32 el secure = ( + undefined_bool () \ (\ (aarch32 :: bool) . + undefined_bool () \ (\ (known :: bool) . + ELStateUsingAArch32K el secure \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let known = tup__0 in + (let aarch32 = tup__1 in + assert_exp known (''known'') \ return aarch32)))))))" + + +(*val ELUsingAArch32 : mword ty2 -> M bool*) + +definition ELUsingAArch32 :: "(2)Word.word \((register_value),(bool),(exception))monad " where + " ELUsingAArch32 el = ( IsSecureBelowEL3 () \ (\ (w__0 :: bool) . ELStateUsingAArch32 el w__0))" + + +(*val UpdateEDSCRFields : unit -> M unit*) + +definition UpdateEDSCRFields :: " unit \((register_value),(unit),(exception))monad " where + " UpdateEDSCRFields _ = ( + Halted () \ (\ (w__0 :: bool) . + if ((\ w__0)) then + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (write_reg + EDSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 32 Word.word)) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__2 :: 32 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__3 :: 1 Word.word) . + (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3 :: 32 Word.word)) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__4 :: 32 Word.word) . + write_reg + EDSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) + :: 32 Word.word)))))) + else + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__5 :: 32 Word.word) . + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL w__6) :: 32 Word.word)) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__7 :: 32 Word.word) . + IsSecure () \ (\ (w__8 :: bool) . + (write_reg + EDSCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__7 (( 18 :: int)::ii) + (if w__8 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 32 Word.word)) \ + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \ (\ (RW :: 4 bits) . + ELUsingAArch32 EL1 \ (\ (w__9 :: bool) . + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 1 :: int)::ii) + (if w__9 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 4 Word.word)) in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (if ((((ProcState_EL w__10) \ EL0))) then + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + return RW) + else + UsingAArch32 () \ (\ (w__11 :: bool) . + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) + (if w__11 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 4 Word.word)) in + return RW))) \ (\ (RW :: 4 bits) . + or_boolM (return ((\ ((HaveEL EL2))))) + (and_boolM (return ((HaveEL EL3))) + ((aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__12 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__14 :: bool) . + (if w__14 then + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + return RW) + else + ELUsingAArch32 EL2 \ (\ (w__15 :: bool) . + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) + (if w__15 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 4 Word.word)) in + return RW))) \ (\ (RW :: 4 bits) . + (if ((\ ((HaveEL EL3)))) then + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)] :: 1 Word.word) + :: 4 Word.word)) in + return RW) + else + ELUsingAArch32 EL3 \ (\ (w__16 :: bool) . + (let (RW :: 4 bits) = + ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) + (if w__16 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 4 Word.word)) in + return RW))) \ (\ (RW :: 4 bits) . + (if ((((vec_of_bits [access_vec_dec RW (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (w__17 :: 3 Word.word) . + (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 3 :: int)::ii) RW (( 0 :: int)::ii) w__17 :: 4 Word.word)) in + return RW)) + else if ((((vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__18 :: 2 Word.word) . + (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 2 :: int)::ii) RW (( 0 :: int)::ii) w__18 :: 4 Word.word)) in + return RW)) + else if ((((vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__19 :: 1 Word.word) . + (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19 :: 4 Word.word)) in + return RW)) + else return RW) \ (\ (RW :: 4 bits) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__20 :: 32 Word.word) . + write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW :: 32 Word.word))))))))))))))))))" + + +(*val Halt : mword ty6 -> M unit*) + +definition Halt :: "(6)Word.word \((register_value),(unit),(exception))monad " where + " Halt reason = ( + (CTI_SignalEvent CrossTriggerIn_CrossHalt \ + UsingAArch32 () ) \ (\ (w__0 :: bool) . + ((if w__0 then + (ThisInstrAddr (( 32 :: int)::ii) () :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + (write_reg DLR_ref w__1 \ + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \ (\ (w__2 :: 32 bits) . + (write_reg DSPSR_ref w__2 \ + (read_reg DSPSR_ref :: ( 32 Word.word) M)) \ (\ (w__3 :: 32 Word.word) . + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + write_reg + DSPSR_ref + ((update_subrange_vec_dec w__3 (( 21 :: int)::ii) (( 21 :: int)::ii)(ProcState_SS w__4) :: 32 Word.word)))))) + else + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + (write_reg DLR_EL0_ref w__5 \ + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \ (\ (w__6 :: 32 bits) . + (write_reg DSPSR_EL0_ref w__6 \ + (read_reg DSPSR_EL0_ref :: ( 32 Word.word) M)) \ (\ (w__7 :: 32 Word.word) . + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + write_reg + DSPSR_EL0_ref + ((update_subrange_vec_dec w__7 (( 21 :: int)::ii) (( 21 :: int)::ii)(ProcState_SS w__8) :: 32 Word.word))))))) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__9 :: 32 Word.word) . + (write_reg + EDSCR_ref + ((update_subrange_vec_dec w__9 (( 24 :: int)::ii) (( 24 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__10 :: 32 Word.word) . + (write_reg + EDSCR_ref + ((update_subrange_vec_dec w__10 (( 28 :: int)::ii) (( 28 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) \ + IsSecure () ) \ (\ (w__11 :: bool) . + ((if w__11 then + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + write_reg + EDSCR_ref + ((update_subrange_vec_dec w__12 (( 16 :: int)::ii) (( 16 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) + :: 32 Word.word))) + else if ((HaveEL EL3)) then + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__13 :: 32 Word.word) . + ExternalSecureInvasiveDebugEnabled () \ (\ (w__14 :: bool) . + write_reg + EDSCR_ref + ((update_subrange_vec_dec w__13 (( 16 :: int)::ii) (( 16 :: int)::ii) + (if w__14 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) + :: 32 Word.word)))) + else + (read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__15 :: 32 bits) . + assert_exp ((((vec_of_bits [access_vec_dec w__15 (( 16 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) ([(CHR ''(''), (CHR ''(''), (CHR ''E''), (CHR ''D''), (CHR ''S''), (CHR ''C''), (CHR ''R''), (CHR '')''), (CHR ''.''), (CHR ''S''), (CHR ''D''), (CHR ''D''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')'')]))) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__16 :: 32 Word.word) . + (write_reg + EDSCR_ref + ((update_subrange_vec_dec w__16 (( 20 :: int)::ii) (( 20 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) \ + UsingAArch32 () ) \ (\ (w__17 :: bool) . + ((if w__17 then + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__18 :: 4 bits) . + (let split_vec = w__18 in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__19 :: ProcState) . + (write_reg PSTATE_ref (w__19 (| ProcState_SS := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__20 :: ProcState) . + (write_reg PSTATE_ref (w__20 (| ProcState_A := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__21 :: ProcState) . + (write_reg PSTATE_ref (w__21 (| ProcState_I := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_F := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg + PSTATE_ref + (w__23 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + write_reg PSTATE_ref (w__24 (| ProcState_T := ((vec_of_bits [B1] :: 1 Word.word))|))))))))))) + else + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (w__25 :: 5 bits) . + (let split_vec = w__25 in + (let (tup__0, tup__1, tup__2, tup__3, tup__4) = + ((subrange_vec_dec split_vec (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_SS := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + (write_reg PSTATE_ref (w__27 (| ProcState_D := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__28 :: ProcState) . + (write_reg PSTATE_ref (w__28 (| ProcState_A := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__29 :: ProcState) . + (write_reg PSTATE_ref (w__29 (| ProcState_I := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__30 :: ProcState) . + write_reg PSTATE_ref (w__30 (| ProcState_F := tup__4 |))))))))))) \ + read_reg PSTATE_ref) \ (\ (w__31 :: ProcState) . + ((write_reg PSTATE_ref (w__31 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + StopInstructionPrefetchAndEnableITR () ) \ + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \ (\ (w__32 :: 32 Word.word) . + write_reg EDSCR_ref ((update_subrange_vec_dec w__32 (( 5 :: int)::ii) (( 0 :: int)::ii) reason :: 32 Word.word)) \ + UpdateEDSCRFields () )))))))))" + + +(*val aarch64_system_exceptions_debug_halt : unit -> M unit*) + +definition aarch64_system_exceptions_debug_halt :: " unit \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_debug_halt _ = ( Halt DebugHalt_HaltInstruction )" + + +(*val S2CacheDisabled : AccType -> M bool*) + +definition S2CacheDisabled :: " AccType \((register_value),(bool),(exception))monad " where + " S2CacheDisabled acctype = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (disable :: 1 bits) . + ELUsingAArch32 EL2 \ (\ (w__0 :: bool) . + (if w__0 then + if (((acctype = AccType_IFETCH))) then + (read_reg HCR2_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__1 (( 1 :: int)::ii)] :: 1 Word.word)) + else + (read_reg HCR2_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__2 (( 0 :: int)::ii)] :: 1 Word.word)) + else if (((acctype = AccType_IFETCH))) then + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__4 (( 33 :: int)::ii)] :: 1 Word.word)) + else + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__5 (( 32 :: int)::ii)] :: 1 Word.word))) \ (\ (disable :: 1 bits) . + return (((disable = (vec_of_bits [B1] :: 1 Word.word))))))))" + + +(*val S2ConvertAttrsHints : mword ty2 -> AccType -> M MemAttrHints*) + +definition S2ConvertAttrsHints :: "(2)Word.word \ AccType \((register_value),(MemAttrHints),(exception))monad " where + " S2ConvertAttrsHints attr acctype = ( + (assert_exp ((\ ((IsZero attr)))) (''!(IsZero(attr))'') \ + undefined_MemAttrHints () ) \ (\ (result :: MemAttrHints) . + S2CacheDisabled acctype \ (\ (w__0 :: bool) . + (let (result :: MemAttrHints) = + (if w__0 then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (result (| MemAttrHints_hints := MemHint_No |))) + else + (let b__0 = attr in + if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (result (| MemAttrHints_hints := MemHint_No |))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WT |))) in + (result (| MemAttrHints_hints := MemHint_RWA |))) + else + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WB |))) in + (result (| MemAttrHints_hints := MemHint_RWA |))))) in + (let (result :: MemAttrHints) = ((result (| MemAttrHints_transient := False |))) in + return result)))))" + + +(*val S2AttrDecode : mword ty2 -> mword ty4 -> AccType -> M MemoryAttributes*) + +definition S2AttrDecode :: "(2)Word.word \(4)Word.word \ AccType \((register_value),(MemoryAttributes),(exception))monad " where + " S2AttrDecode SH attr acctype = ( + undefined_MemoryAttributes () \ (\ (memattrs :: MemoryAttributes) . + (if (((((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_typ := MemType_Device |))) in + (let b__0 = ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (memattrs :: MemoryAttributes) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (memattrs (| MemoryAttributes_device := DeviceType_nGnRnE |)) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (memattrs (| MemoryAttributes_device := DeviceType_nGnRE |)) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (memattrs (| MemoryAttributes_device := DeviceType_nGRE |)) + else (memattrs (| MemoryAttributes_device := DeviceType_GRE |))) in + return memattrs))) + else if (((((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \ (vec_of_bits [B0,B0] :: 2 Word.word)))) + then + (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Normal |))) in + S2ConvertAttrsHints ((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \ (\ (w__0 :: + MemAttrHints) . + (let memattrs = ((memattrs (| MemoryAttributes_outer := w__0 |))) in + S2ConvertAttrsHints ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \ (\ (w__1 :: + MemAttrHints) . + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_inner := w__1 |))) in + (let (memattrs :: MemoryAttributes) = + ((memattrs (| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))|))) in + (let (memattrs :: MemoryAttributes) = + ((memattrs (| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1,B0] :: 2 Word.word))))|))) in + return memattrs))))))) + else undefined_MemoryAttributes () ) \ (\ (memattrs :: MemoryAttributes) . + MemAttrDefaults memattrs)))" + + +(*val ELIsInHost : mword ty2 -> M bool*) + +definition ELIsInHost :: "(2)Word.word \((register_value),(bool),(exception))monad " where + " ELIsInHost el = ( + and_boolM + (and_boolM + (and_boolM + (and_boolM (IsSecureBelowEL3 () \ (\ (w__0 :: bool) . return ((\ w__0)))) + (return ((HaveVirtHostExt () )))) + (ELUsingAArch32 EL2 \ (\ (w__2 :: bool) . return ((\ w__2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (or_boolM (return (((el = EL2)))) + (and_boolM (return (((el = EL0)))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))))" + + +(*val S1TranslationRegime__0 : mword ty2 -> M (mword ty2)*) + +(*val S1TranslationRegime__1 : unit -> M (mword ty2)*) + +definition S1TranslationRegime__0 :: "(2)Word.word \((register_value),((2)Word.word),(exception))monad " where + " S1TranslationRegime__0 el = ( + if (((el \ EL0))) then return el + else + and_boolM (and_boolM (return ((HaveEL EL3))) ((ELUsingAArch32 EL3))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__3 :: bool) . + if w__3 then return EL3 + else + and_boolM (return ((HaveVirtHostExt () ))) ((ELIsInHost el)) \ (\ (w__5 :: bool) . + return (if w__5 then EL2 + else EL1))))" + + +definition S1TranslationRegime__1 :: " unit \((register_value),((2)Word.word),(exception))monad " where + " S1TranslationRegime__1 _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (S1TranslationRegime__0(ProcState_EL w__0) :: ( 2 Word.word) M)))" + + +(*val aset_FAR__0 : mword ty2 -> mword ty64 -> M unit*) + +(*val aset_FAR__1 : mword ty64 -> M unit*) + +definition aset_FAR__0 :: "(2)Word.word \(64)Word.word \((register_value),(unit),(exception))monad " where + " aset_FAR__0 regime value_name = ( + (let (r :: 64 bits) = value_name in + (let pat0 = regime in + if (((pat0 = EL1))) then write_reg FAR_EL1_ref r + else if (((pat0 = EL2))) then write_reg FAR_EL2_ref r + else if (((pat0 = EL3))) then write_reg FAR_EL3_ref r + else Unreachable () )))" + + +definition aset_FAR__1 :: "(64)Word.word \((register_value),(unit),(exception))monad " where + " aset_FAR__1 value_name = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + aset_FAR__0 w__0 value_name))" + + +(*val aset_ESR__0 : mword ty2 -> mword ty32 -> M unit*) + +(*val aset_ESR__1 : mword ty32 -> M unit*) + +definition aset_ESR__0 :: "(2)Word.word \(32)Word.word \((register_value),(unit),(exception))monad " where + " aset_ESR__0 regime value_name = ( + (let (r :: 32 bits) = value_name in + (let pat0 = regime in + if (((pat0 = EL1))) then write_reg ESR_EL1_ref r + else if (((pat0 = EL2))) then write_reg ESR_EL2_ref r + else if (((pat0 = EL3))) then write_reg ESR_EL3_ref r + else Unreachable () )))" + + +definition aset_ESR__1 :: "(32)Word.word \((register_value),(unit),(exception))monad " where + " aset_ESR__1 value_name = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + aset_ESR__0 w__0 value_name))" + + +(*val aget_VBAR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_VBAR__1 : unit -> M (mword ty64)*) + +definition aget_VBAR__0 :: "(2)Word.word \((register_value),((64)Word.word),(exception))monad " where + " aget_VBAR__0 regime = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (r :: 64 bits) . + (let pat0 = regime in + if (((pat0 = EL1))) then (read_reg VBAR_EL1_ref :: ( 64 Word.word) M) + else if (((pat0 = EL2))) then (read_reg VBAR_EL2_ref :: ( 64 Word.word) M) + else if (((pat0 = EL3))) then (read_reg VBAR_EL3_ref :: ( 64 Word.word) M) + else Unreachable () \ return r)))" + + +definition aget_VBAR__1 :: " unit \((register_value),((64)Word.word),(exception))monad " where + " aget_VBAR__1 _ = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + (aget_VBAR__0 w__0 :: ( 64 Word.word) M)))" + + +(*val aget_SCTLR__0 : mword ty2 -> M (mword ty32)*) + +(*val aget_SCTLR__1 : unit -> M (mword ty32)*) + +definition aget_SCTLR__0 :: "(2)Word.word \((register_value),((32)Word.word),(exception))monad " where + " aget_SCTLR__0 regime = ( + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (r :: 32 bits) . + (let pat0 = regime in + if (((pat0 = EL1))) then (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) + else if (((pat0 = EL2))) then (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) + else if (((pat0 = EL3))) then (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) + else Unreachable () \ return r)))" + + +definition aget_SCTLR__1 :: " unit \((register_value),((32)Word.word),(exception))monad " where + " aget_SCTLR__1 _ = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + (aget_SCTLR__0 w__0 :: ( 32 Word.word) M)))" + + +(*val BigEndian : unit -> M bool*) + +definition BigEndian :: " unit \((register_value),(bool),(exception))monad " where + " BigEndian _ = ( + undefined_bool () \ (\ (bigend :: bool) . + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let (bigend :: bool) = ((ProcState_E w__1) \ (vec_of_bits [B0] :: 1 Word.word)) in + return bigend)) + else + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + if ((((ProcState_EL w__2) = EL0))) then + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (let (bigend :: bool) = + ((vec_of_bits [access_vec_dec w__3 (( 24 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + return bigend)) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (let (bigend :: bool) = + ((vec_of_bits [access_vec_dec w__4 (( 25 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + return bigend))))))" + + +(*val aget_MAIR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_MAIR__1 : unit -> M (mword ty64)*) + +definition aget_MAIR__0 :: "(2)Word.word \((register_value),((64)Word.word),(exception))monad " where + " aget_MAIR__0 regime = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (r :: 64 bits) . + (let pat0 = regime in + if (((pat0 = EL1))) then (read_reg MAIR_EL1_ref :: ( 64 Word.word) M) + else if (((pat0 = EL2))) then (read_reg MAIR_EL2_ref :: ( 64 Word.word) M) + else if (((pat0 = EL3))) then (read_reg MAIR_EL3_ref :: ( 64 Word.word) M) + else Unreachable () \ return r)))" + + +definition aget_MAIR__1 :: " unit \((register_value),((64)Word.word),(exception))monad " where + " aget_MAIR__1 _ = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + (aget_MAIR__0 w__0 :: ( 64 Word.word) M)))" + + +(*val S1CacheDisabled : AccType -> M bool*) + +definition S1CacheDisabled :: " AccType \((register_value),(bool),(exception))monad " where + " S1CacheDisabled acctype = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (enable :: 1 bits) . + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (if w__1 then + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + if ((((ProcState_EL w__2) = EL2))) then + if (((acctype = AccType_IFETCH))) then + (read_reg HSCTLR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__3 (( 12 :: int)::ii)] :: 1 Word.word)) + else + (read_reg HSCTLR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__4 (( 2 :: int)::ii)] :: 1 Word.word)) + else if (((acctype = AccType_IFETCH))) then + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 12 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 2 :: int)::ii)] :: 1 Word.word))) + else if (((acctype = AccType_IFETCH))) then + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + return (vec_of_bits [access_vec_dec w__9 (( 12 :: int)::ii)] :: 1 Word.word)) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + return (vec_of_bits [access_vec_dec w__10 (( 2 :: int)::ii)] :: 1 Word.word))) \ (\ (enable :: 1 bits) . + return (((enable = (vec_of_bits [B0] :: 1 Word.word)))))))))" + + +(*val ShortConvertAttrsHints : mword ty2 -> AccType -> bool -> M MemAttrHints*) + +definition ShortConvertAttrsHints :: "(2)Word.word \ AccType \ bool \((register_value),(MemAttrHints),(exception))monad " where + " ShortConvertAttrsHints RGN acctype secondstage = ( + undefined_MemAttrHints () \ (\ (result :: MemAttrHints) . + or_boolM (and_boolM (return ((\ secondstage))) ((S1CacheDisabled acctype))) + (and_boolM (return secondstage) ((S2CacheDisabled acctype))) \ (\ (w__4 :: bool) . + (let (result :: MemAttrHints) = + (if w__4 then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (result (| MemAttrHints_hints := MemHint_No |))) + else + (let b__0 = RGN in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (result (| MemAttrHints_hints := MemHint_No |))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WB |))) in + (result (| MemAttrHints_hints := MemHint_RWA |))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WT |))) in + (result (| MemAttrHints_hints := MemHint_RA |))) + else + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WB |))) in + (result (| MemAttrHints_hints := MemHint_RA |))))) in + (let (result :: MemAttrHints) = ((result (| MemAttrHints_transient := False |))) in + return result)))))" + + +(*val WalkAttrDecode : mword ty2 -> mword ty2 -> mword ty2 -> bool -> M MemoryAttributes*) + +definition WalkAttrDecode :: "(2)Word.word \(2)Word.word \(2)Word.word \ bool \((register_value),(MemoryAttributes),(exception))monad " where + " WalkAttrDecode SH ORGN IRGN secondstage = ( + undefined_MemoryAttributes () \ (\ (memattrs :: MemoryAttributes) . + (let (acctype :: AccType) = AccType_NORMAL in + (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Normal |))) in + ShortConvertAttrsHints IRGN acctype secondstage \ (\ (w__0 :: MemAttrHints) . + (let memattrs = ((memattrs (| MemoryAttributes_inner := w__0 |))) in + ShortConvertAttrsHints ORGN acctype secondstage \ (\ (w__1 :: MemAttrHints) . + (let memattrs = ((memattrs (| MemoryAttributes_outer := w__1 |))) in + (let memattrs = + ((memattrs (| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))|))) in + (let memattrs = + ((memattrs (| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1,B0] :: 2 Word.word))))|))) in + MemAttrDefaults memattrs))))))))))" + + +(*val LongConvertAttrsHints : mword ty4 -> AccType -> M MemAttrHints*) + +definition LongConvertAttrsHints :: "(4)Word.word \ AccType \((register_value),(MemAttrHints),(exception))monad " where + " LongConvertAttrsHints attrfield acctype = ( + (assert_exp ((\ ((IsZero attrfield)))) (''!(IsZero(attrfield))'') \ + undefined_MemAttrHints () ) \ (\ (result :: MemAttrHints) . + S1CacheDisabled acctype \ (\ (w__0 :: bool) . + (let (result :: MemAttrHints) = + (if w__0 then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (result (| MemAttrHints_hints := MemHint_No |))) + else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WT |))) in + (let (result :: MemAttrHints) = + ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + (result (| MemAttrHints_transient := True |)))) + else if (((((slice0 attrfield (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in + (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemHint_No |))) in + (result (| MemAttrHints_transient := False |)))) + else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (result :: MemAttrHints) = + ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemAttr_WB |))) in + (result (| MemAttrHints_transient := True |)))) + else + (let (result :: MemAttrHints) = + ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + (let (result :: MemAttrHints) = + ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + (result (| MemAttrHints_transient := False |))))) in + return result))))" + + +(*val AArch64_S1AttrDecode : mword ty2 -> mword ty3 -> AccType -> M MemoryAttributes*) + +definition AArch64_S1AttrDecode :: "(2)Word.word \(3)Word.word \ AccType \((register_value),(MemoryAttributes),(exception))monad " where + " AArch64_S1AttrDecode SH attr acctype = ( + (let uattr = (ex_nat ((Word.uint attr))) in + undefined_MemoryAttributes () \ (\ (memattrs :: MemoryAttributes) . + (aget_MAIR__1 () :: ( 64 Word.word) M) \ (\ (mair :: 64 bits) . + (let (index1 :: int) = ((( 8 :: int)::ii) * uattr) in + (let (attrfield :: 8 bits) = + ((subrange_vec_dec mair (((( 7 :: int)::ii) + index1)) index1 :: 8 Word.word)) in + undefined_Constraint () \ (\ (anon10 :: Constraint) . + (if (((((((((((subrange_vec_dec attrfield (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) \ (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \ (((((subrange_vec_dec attrfield (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))))))) \ ((((((((subrange_vec_dec attrfield (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \ (((((and_vec ((subrange_vec_dec attrfield (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) + :: 4 Word.word)) \ (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))))))))) then + (ConstrainUnpredictableBits (( 8 :: int)::ii) Unpredictable_RESMAIR :: ((Constraint * 8 Word.word)) M) \ (\ (w__0 :: + (Constraint * 8 bits)) . + (let (tup__0, tup__1) = w__0 in + (let (anon10 :: Constraint) = tup__0 in + return tup__1))) + else return attrfield) \ (\ (attrfield :: 8 bits) . + (if (((((subrange_vec_dec attrfield (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Device |))) in + (let b__0 = ((subrange_vec_dec attrfield (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in + if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (memattrs :: MemoryAttributes) = + ((memattrs (| MemoryAttributes_device := DeviceType_nGnRnE |))) in + return memattrs) + else if (((b__0 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (memattrs :: MemoryAttributes) = + ((memattrs (| MemoryAttributes_device := DeviceType_nGnRE |))) in + return memattrs) + else if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (memattrs :: MemoryAttributes) = + ((memattrs (| MemoryAttributes_device := DeviceType_nGRE |))) in + return memattrs) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then + (let (memattrs :: MemoryAttributes) = + ((memattrs (| MemoryAttributes_device := DeviceType_GRE |))) in + return memattrs) + else Unreachable () \ return memattrs)) + else if (((((subrange_vec_dec attrfield (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) \ (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Normal |))) in + LongConvertAttrsHints ((subrange_vec_dec attrfield (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) acctype \ (\ (w__1 :: + MemAttrHints) . + (let memattrs = ((memattrs (| MemoryAttributes_outer := w__1 |))) in + LongConvertAttrsHints ((subrange_vec_dec attrfield (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) acctype \ (\ (w__2 :: + MemAttrHints) . + (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_inner := w__2 |))) in + (let (memattrs :: MemoryAttributes) = + ((memattrs (| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))|))) in + (let (memattrs :: MemoryAttributes) = + ((memattrs (| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1,B0] :: 2 Word.word))))|))) in + return memattrs))))))) + else Unreachable () \ return memattrs) \ (\ (memattrs :: MemoryAttributes) . + MemAttrDefaults memattrs)))))))))" + + +(*val IsInHost : unit -> M bool*) + +definition IsInHost :: " unit \((register_value),(bool),(exception))monad " where + " IsInHost _ = ( read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . ELIsInHost(ProcState_EL w__0)))" + + +(*val aget_CPACR : unit -> M (mword ty32)*) + +definition aget_CPACR :: " unit \((register_value),((32)Word.word),(exception))monad " where + " aget_CPACR _ = ( + IsInHost () \ (\ (w__0 :: bool) . + if w__0 then (read_reg CPTR_EL2_ref :: ( 32 Word.word) M) + else (read_reg CPACR_EL1_ref :: ( 32 Word.word) M)))" + + +(*val HasS2Translation : unit -> M bool*) + +definition HasS2Translation :: " unit \((register_value),(bool),(exception))monad " where + " HasS2Translation _ = ( + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (IsInHost () \ (\ (w__2 :: bool) . return ((\ w__2))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . return ((((ProcState_EL w__4) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . return ((((ProcState_EL w__5) = EL1)))))))" + + +(*val AArch64_SecondStageWalk : AddressDescriptor -> mword ty64 -> AccType -> bool -> ii -> bool -> M AddressDescriptor*) + +definition AArch64_CheckAndUpdateDescriptor_SecondStage :: " DescriptorUpdate \ FaultRecord \(64)Word.word \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckAndUpdateDescriptor_SecondStage result fault vaddress acctype iswrite s2fs1walk hwupdatewalk__arg = ( + (let hwupdatewalk = hwupdatewalk__arg in + undefined_bool () \ (\ (hw_update_AF :: bool) . + (let (hw_update_AF :: bool) = + (if(DescriptorUpdate_AF result) then + if ((((FaultRecord_typ fault) = Fault_None))) then True + else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True + else False + else hw_update_AF) in + undefined_bool () \ (\ (hw_update_AP :: bool) . + undefined_bool () \ (\ (write_perm_req :: bool) . + (let (hw_update_AP :: bool) = + (if ((((DescriptorUpdate_AP result) \ ((((FaultRecord_typ fault) = Fault_None)))))) then + (let (write_perm_req :: bool) = + ((((iswrite \ ((((((acctype = AccType_ATOMICRW))) \ (((acctype = AccType_ORDEREDRW))))))))) \ ((\ s2fs1walk))) in + ((((write_perm_req \ ((\ ((((((acctype = AccType_AT))) \ (((acctype = AccType_DC))))))))))) \ hwupdatewalk)) + else False) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (desc :: 64 bits) . + undefined_AccessDescriptor () \ (\ (accdesc :: AccessDescriptor) . + undefined_AddressDescriptor () \ (\ (descaddr2 :: AddressDescriptor) . + (if (((hw_update_AF \ hw_update_AP))) then + (let descaddr2 = ((DescriptorUpdate_descaddr result)) in + CreateAccessDescriptor AccType_ATOMICRW \ (\ (w__0 :: AccessDescriptor) . + (let accdesc = w__0 in + (aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let desc = w__1 in + (let (desc :: 64 bits) = + (if hw_update_AF then + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + else desc) in + (let (desc :: 64 bits) = + (if hw_update_AP then + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + else desc) in + aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc))))))) + else return () ) \ + return fault))))))))))" + + +(*val AArch64_CheckS2Permission : Permissions -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +definition AArch64_CheckS2Permission :: " Permissions \(64)Word.word \(52)Word.word \ int \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckS2Permission perms vaddress ipaddress level acctype iswrite s2fs1walk hwupdatewalk = ( + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (ELUsingAArch32 EL2 \ (\ (w__2 :: bool) . return ((\ w__2))))) ((HasS2Translation () )) \ (\ (w__5 :: + bool) . + assert_exp w__5 (''(((HaveEL(EL2) && !(IsSecure())) && !(ELUsingAArch32(EL2))) && HasS2Translation())'') \ + ((let (r :: bool) = + ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (w :: bool) = + ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + undefined_bool () \ (\ (xn :: bool) . + (if ((HaveExtendedExecuteNeverExt () )) then + (let b__0 = ((concat_vec(Permissions_xn perms)(Permissions_xxn perms) :: 2 Word.word)) in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return False + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (let (xn :: bool) = ((ProcState_EL w__6) = EL1) in + return xn)) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return True + else + read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + (let (xn :: bool) = ((ProcState_EL w__7) = EL0) in + return xn))) + else + (let (xn :: bool) = ((Permissions_xn perms) = (vec_of_bits [B1] :: 1 Word.word)) in + return xn)) \ (\ (xn :: bool) . + undefined_bool () \ (\ (failedread :: bool) . + undefined_bool () \ (\ (fail1 :: bool) . + (let ((fail1 :: bool), (failedread :: bool)) = + (if ((((((acctype = AccType_IFETCH))) \ ((\ s2fs1walk))))) then + (let (fail1 :: bool) = xn in + (let (failedread :: bool) = True in + (fail1, failedread))) + else + (let ((fail1 :: bool), (failedread :: bool)) = + (if (((((((((acctype = AccType_ATOMICRW))) \ (((acctype = AccType_ORDEREDRW)))))) \ ((\ s2fs1walk))))) then + (let (fail1 :: bool) = (((\ r)) \ ((\ w))) in + (let (failedread :: bool) = (\ r) in + (fail1, failedread))) + else + (let ((fail1 :: bool), (failedread :: bool)) = + (if (((iswrite \ ((\ s2fs1walk))))) then + (let (fail1 :: bool) = (\ w) in + (let (failedread :: bool) = False in + (fail1, failedread))) + else + (let ((fail1 :: bool), (failedread :: bool)) = + (if hwupdatewalk then + (let (fail1 :: bool) = (\ w) in + (let (failedread :: bool) = (\ iswrite) in + (fail1, failedread))) + else + (let (fail1 :: bool) = (\ r) in + (let (failedread :: bool) = (\ iswrite) in + (fail1, failedread)))) in + (fail1, failedread))) in + (fail1, failedread))) in + (fail1, failedread))) in + undefined_bool () \ (\ (secondstage :: bool) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (domain1 :: 4 bits) . + if fail1 then + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__8 :: 4 bits) . + (let domain1 = w__8 in + (let secondstage = True in + AArch64_PermissionFault ipaddress level acctype ((\ failedread)) secondstage s2fs1walk))) + else AArch64_NoFault () ))))))))))))" + + +(*val IsZero_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +definition IsZero_slice :: "('n::len)Word.word \ int \ int \((register_value),(bool),(exception))monad " where + " IsZero_slice xs i l = ( + assert_exp True ('''') \ + return ((IsZero ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)))))" + + +(*val ZeroExtend_slice_append : forall 'n 'm 'o . Size 'm, Size 'n, Size 'o => integer -> mword 'n -> ii -> ii -> mword 'm -> M (mword 'o)*) + +definition ZeroExtend_slice_append :: " int \('n::len)Word.word \ int \ int \('m::len)Word.word \((register_value),(('o::len)Word.word),(exception))monad " where + " ZeroExtend_slice_append (o__tv :: int) xs i l ys = ( + assert_exp True ('''') \ + ((let xs = ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) in + (ZeroExtend__1 o__tv ((shiftr xs i :: ( 'n::len)Word.word)) :: (( 'o::len)Word.word) M) \ (\ (w__0 :: ( 'o::len)Word.word) . + (let (xs :: 'o bits) = ((shiftl w__0 ((int (size ys))) :: ( 'o::len)Word.word)) in + (ZeroExtend__1 ((int (size xs))) ys :: (( 'o::len)Word.word) M) \ (\ (ys :: 'o bits) . + return ((or_vec xs ys :: ( 'o::len)Word.word))))))))" + + +definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \(64)Word.word \ AccType \ bool \ bool \ int \((register_value),(TLBRecord),(exception))monad " where + " AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1 = ( + catch_early_return + (and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (liftR (IsSecure () ) \ (\ (w__0 :: bool) . return ((\ w__0))))) + (liftR (ELUsingAArch32 EL2) \ (\ (w__2 :: bool) . return ((\ w__2))))) + (liftR ((HasS2Translation () ))) \ (\ (w__5 :: bool) . + (liftR (assert_exp w__5 ('''')) \ + liftR (undefined_TLBRecord () )) \ (\ (result :: TLBRecord) . + liftR (undefined_AddressDescriptor () ) \ (\ (descaddr :: AddressDescriptor) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (baseregister :: 64 bits) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (inputaddr :: 64 bits) . + (let (tmp_180 :: MemoryAttributes) = ((AddressDescriptor_memattrs descaddr)) in + (let tmp_180 = ((tmp_180 (| MemoryAttributes_typ := MemType_Normal |))) in + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := tmp_180 |))) in + liftR (undefined_int () ) \ (\ (startsizecheck :: ii) . + liftR (undefined_int () ) \ (\ (inputsizecheck :: ii) . + liftR (undefined_int () ) \ (\ (startlevel :: ii) . + liftR (undefined_int () ) \ (\ (level :: ii) . + liftR (undefined_int () ) \ (\ (stride :: ii) . + liftR (undefined_int () ) \ (\ (firstblocklevel :: ii) . + liftR (undefined_int () ) \ (\ (grainsize :: ii) . + liftR (undefined_bool () ) \ (\ (hierattrsdisabled :: bool) . + liftR (undefined_bool () ) \ (\ (update_AP :: bool) . + liftR (undefined_bool () ) \ (\ (update_AF :: bool) . + liftR (undefined_bool () ) \ (\ (singlepriv :: bool) . + liftR (undefined_bool () ) \ (\ (lookupsecure :: bool) . + liftR (undefined_bool () ) \ (\ (reversedescriptors :: bool) . + liftR (undefined_bool () ) \ (\ (disabled :: bool) . + liftR (undefined_bool () ) \ (\ (basefound :: bool) . + liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \ (\ (ps :: 3 bits) . + liftR (undefined_int () ) \ (\ (inputsize_min :: ii) . + liftR (undefined_Constraint () ) \ (\ (c :: Constraint) . + liftR (undefined_int () ) \ (\ (inputsize_max :: ii) . + liftR (undefined_int () ) \ (\ (inputsize :: ii) . + liftR (undefined_bool () ) \ (\ (midgrain :: bool) . + liftR (undefined_bool () ) \ (\ (largegrain :: bool) . + liftR (undefined_int () ) \ (\ (top1 :: ii) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \ (\ (w__6 :: 64 bits) . + (let inputaddr = w__6 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__7 :: 32 bits) . + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__7 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__8 :: 32 bits) . + (let largegrain = + (((slice0 w__8 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__9 :: 32 bits) . + (let midgrain = + (((slice0 w__9 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (let inputsize_max = (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__10 :: 32 bits) . + (let ps = ((slice0 w__10 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((- ((ex_int inputsize)))) + (( 64 :: int)::ii)))))) \ (\ (w__12 :: + bool) . + (let basefound = w__12 in + (let disabled = False in + liftR ((read_reg VTTBR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__13 :: 64 bits) . + (let baseregister = w__13 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__14 :: 32 bits) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__15 :: 32 bits) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__16 :: 32 bits) . + liftR (WalkAttrDecode ((slice0 w__14 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__15 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__16 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) True) \ (\ (w__17 :: MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__17 |))) in + liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__18 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__18 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let lookupsecure = False in + (let singlepriv = True in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__19 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__19 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__20 :: bool) . + (let update_AF = w__20 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__21 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__21 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__22 :: bool) . + (let update_AP = w__22 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__23 :: 32 bits) . + (let startlevel = (Word.uint ((slice0 w__23 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = + (if largegrain then + (let (grainsize :: ii) = ((( 16 :: int)::ii)) in + (let (level :: ii) = ((( 3 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = (if ((Have52BitPAExt () )) then (( 1 :: int)::ii) else (( 2 :: int)::ii)) in + (firstblocklevel, grainsize, level)))) + else + (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = + (if midgrain then + (let (grainsize :: ii) = ((( 14 :: int)::ii)) in + (let (level :: ii) = ((( 3 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = ((( 2 :: int)::ii)) in + (firstblocklevel, grainsize, level)))) + else + (let (grainsize :: ii) = ((( 12 :: int)::ii)) in + (let (level :: ii) = ((( 2 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = ((( 1 :: int)::ii)) in + (firstblocklevel, grainsize, level))))) in + (firstblocklevel, grainsize, level))) in + (let stride = (((ex_int grainsize)) - (( 3 :: int)::ii)) in + (let (basefound :: bool) = + (if largegrain then + if ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 42 :: int)::ii))))))))) + then + False + else basefound + else if midgrain then + if ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 40 :: int)::ii))))))))) + then + False + else basefound + else if (((((((ex_int level)) < (( 0 :: int)::ii))) \ ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 42 :: int)::ii))))))))) then + False + else basefound) in + (let inputsizecheck = inputsize in + and_boolM (return ((((ex_int inputsize)) > ((ex_int ((PAMax () ))))))) + (or_boolM (liftR (ELUsingAArch32 EL1) \ (\ (w__24 :: bool) . return ((\ w__24)))) + (return ((((ex_int inputsize)) > (( 40 :: int)::ii))))) \ (\ (w__26 :: bool) . + (if w__26 then + (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of + Constraint_FORCE => + (let (inputsize :: ii) = (PAMax () ) in + (let (inputsizecheck :: ii) = (PAMax () ) in + return (basefound, inputsize, inputsizecheck))) + | Constraint_FORCENOSLCHECK => + (let (inputsize :: ii) = (PAMax () ) in + return (basefound, inputsize, inputsizecheck)) + | Constraint_FAULT => + (let (basefound :: bool) = False in + return (basefound, inputsize, inputsizecheck)) + | _ => liftR (Unreachable () ) \ return (basefound, inputsize, inputsizecheck) + ) + else return (basefound, inputsize, inputsizecheck)) \ (\ varstup . (let ((basefound :: bool), (inputsize :: + ii), (inputsizecheck :: ii)) = varstup in + (let startsizecheck = + (((ex_int inputsizecheck)) - + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + ((ex_int grainsize))))) in + (let (basefound :: bool) = + (if (((((((ex_int startsizecheck)) < (( 1 :: int)::ii))) \ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 :: int)::ii)))))))) then + False + else basefound) in + if (((((\ basefound)) \ disabled))) then + (let level = ((( 0 :: int)::ii)) in + (let (tmp_190 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__27 :: + FaultRecord) . + (let (tmp_190 :: AddressDescriptor) = ((tmp_190 (| AddressDescriptor_fault := w__27 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_190 |))) in + return result))))) + else + liftR (undefined_int () ) \ (\ (outputsize :: ii) . + (let b__0 = ps in + (let (outputsize :: ii) = + (if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then (( 36 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then (( 40 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then (( 42 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then (( 44 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then (( 48 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + if (((((Have52BitPAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii) + else (( 48 :: int)::ii)) in + (let (outputsize :: ii) = + (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () + else outputsize) in + and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice baseregister outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__28 :: + bool) . + return ((\ w__28)))) \ (\ (w__29 :: bool) . + if w__29 then + (let level = ((( 0 :: int)::ii)) in + (let (tmp_200 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__30 :: + FaultRecord) . + (let (tmp_200 :: AddressDescriptor) = ((tmp_200 (| AddressDescriptor_fault := w__30 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_200 |))) in + return result))))) + else + (let baselowerbound = + ((((( 3 :: int)::ii) + ((ex_int inputsize)))) - + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))) in + (liftR (assert_exp True ('''')) \ + liftR ((undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M))) \ (\ (baseaddress :: 52 bits) . + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in + liftR (assert_exp True ('''')) \ + ((let (baseaddress :: 52 bits) = + ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z)) + baseregister z ((((- z)) + (( 48 :: int)::ii))) z + :: 48 Word.word)) + :: 52 Word.word)) in + return baseaddress))) + else + (let (baseaddress :: 52 bits) = + ((place_slice (( 52 :: int)::ii) baseregister baselowerbound + ((((- baselowerbound)) + (( 48 :: int)::ii))) baselowerbound + :: 52 Word.word)) in + return baseaddress)) \ (\ (baseaddress :: 52 bits) . + (let (ns_table :: 1 bits) = + (if lookupsecure then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + (let (ap_table :: 2 bits) = ((vec_of_bits [B0,B0] :: 2 Word.word)) in + (let (xn_table :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (pxn_table :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (addrselecttop :: ii) = (((ex_int inputsize)) - (( 1 :: int)::ii)) in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + (liftR ((read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__31 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__31 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (liftR ((read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__33 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__33 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (apply_nvnv1_effect :: bool) . + liftR (undefined_bool () ) \ (\ (blocktranslate :: bool) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (desc :: 64 bits) . + liftR (undefined_AccessDescriptor () ) \ (\ (accdesc :: AccessDescriptor) . + liftR (undefined_bool () ) \ (\ (hwupdatewalk :: bool) . + liftR (undefined_AddressDescriptor () ) \ (\ (descaddr2 :: AddressDescriptor) . + liftR (undefined_int () ) \ (\ (addrselectbottom :: ii) . + (untilM (addrselectbottom, desc, descaddr, level, result) + (\ varstup . (let (addrselectbottom, desc, descaddr, level, result) = varstup in + return blocktranslate)) + (\ varstup . (let (addrselectbottom, desc, descaddr, level, result) = varstup in + (let addrselectbottom = + ((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))) in + liftR ((ZeroExtend_slice_append (( 52 :: int)::ii) inputaddr addrselectbottom + ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom)))) + + + (( 1 :: int)::ii))) (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: ( 52 Word.word) M)) \ (\ (index1 :: 52 bits) . + (let (tmp_210 :: FullAddress) = ((AddressDescriptor_paddress descaddr)) in + (let tmp_210 = + ((tmp_210 (| + FullAddress_physicaladdress := ((or_vec baseaddress index1 :: 52 Word.word))|))) in + (let descaddr = ((descaddr (| AddressDescriptor_paddress := tmp_210 |))) in + (let (tmp_220 :: FullAddress) = ((AddressDescriptor_paddress descaddr)) in + (let tmp_220 = ((tmp_220 (| FullAddress_NS := ns_table |))) in + (let descaddr = ((descaddr (| AddressDescriptor_paddress := tmp_220 |))) in + (let descaddr2 = descaddr in + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \ (\ (w__34 :: 64 bits) . + (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__34 |))) in + liftR (CreateAccessDescriptorPTW acctype True s2fs1walk level) \ (\ (w__35 :: + AccessDescriptor) . + (let accdesc = w__35 in + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \ (\ (w__36 :: 64 + bits) . + (let desc = w__36 in + (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) + else return desc) \ (\ (desc :: 64 bits) . + (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((ex_int level)) = (( 3 :: int)::ii)))))))))) + then + (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__38 :: + FaultRecord) . + (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__38 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return (level, result))))) + else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((ex_int level)) = (( 3 :: int)::ii))))))) + then + (let (blocktranslate :: bool) = True in + return (level, result)) + else + or_boolM + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \ largegrain))) \ ((\ ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice desc outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__39 :: + bool) . + return ((\ w__39))))) \ (\ (w__41 :: bool) . + if w__41 then + (let (tmp_250 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__42 :: + FaultRecord) . + (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__42 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return (level, result))))) + else + (let gsz = grainsize in + liftR (assert_exp True ('''')) \ + ((let (_ :: unit) = + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (let (baseaddress :: 52 bits) = + ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat + ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc + gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz + :: 48 Word.word)) + :: 52 Word.word)) in + () ) + else + (let (baseaddress :: 52 bits) = + ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) + gsz + :: 52 Word.word)) in + () )) in + (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in + (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in + (let (blocktranslate :: bool) = False in + return (level, result))))))))) \ (\ varstup . (let ((level :: ii), (result :: TLBRecord)) = varstup in + return (addrselectbottom, desc, descaddr, level, result)))))))))))))))))))))) \ (\ varstup . (let ((addrselectbottom :: + ii), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (result :: + TLBRecord)) = varstup in + if ((((ex_int level)) < ((ex_int firstblocklevel)))) then + (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__43 :: + FaultRecord) . + (let (tmp_260 :: AddressDescriptor) = ((tmp_260 (| AddressDescriptor_fault := w__43 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_260 |))) in + return result)))) + else + liftR (undefined_bool () ) \ (\ (contiguousbitcheck :: bool) . + (let (contiguousbitcheck :: bool) = + (if largegrain then + ((((((ex_int level)) = (( 2 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 34 :: int)::ii)))) + else if midgrain then + ((((((ex_int level)) = (( 2 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 30 :: int)::ii)))) + else ((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 34 :: int)::ii))))) in + (if (((contiguousbitcheck \ ((((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + liftR (undefined_bool () ) \ (\ (w__44 :: bool) . + if w__44 then + (let (tmp_270 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__45 :: + FaultRecord) . + (let tmp_270 = ((tmp_270 (| AddressDescriptor_fault := w__45 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_270 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return result)))) + else return result) + else return result) \ (\ (result :: TLBRecord) . + or_boolM + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \ largegrain))) \ ((\ ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice desc outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__46 :: + bool) . + return ((\ w__46))))) \ (\ (w__48 :: bool) . + if w__48 then + (let (tmp_280 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__49 :: + FaultRecord) . + (let (tmp_280 :: AddressDescriptor) = ((tmp_280 (| AddressDescriptor_fault := w__49 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_280 |))) in + return result)))) + else + liftR ((undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \ (\ (outputaddress :: 52 + bits) . + (let asb = addrselectbottom in + liftR (assert_exp True ('''')) \ + ((let (outputaddress :: 52 bits) = + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_slice_concat (( 48 :: int)::ii) desc asb + ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb + :: 48 Word.word)) + :: 52 Word.word) + else + (slice_slice_concat (( 52 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii))) + inputaddr (( 0 :: int)::ii) asb + :: 52 Word.word)) in + (if ((((vec_of_bits [access_vec_dec desc (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + if ((\ update_AF)) then + (let (tmp_290 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AccessFlagFault ipaddress level acctype iswrite True s2fs1walk) \ (\ (w__50 :: + FaultRecord) . + (let tmp_290 = ((tmp_290 (| AddressDescriptor_fault := w__50 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_290 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return result)))) + else + (let (tmp_300 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let (tmp_300 :: DescriptorUpdate) = ((tmp_300 (| DescriptorUpdate_AF := True |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_descupdate := tmp_300 |))) in + return result))) + else return result) \ (\ (result :: TLBRecord) . + (let ((desc :: 64 bits), (result :: TLBRecord)) = + (if (((update_AP \ ((((vec_of_bits [access_vec_dec desc (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let ((desc :: 64 bits), (result :: TLBRecord)) = + (if ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (desc :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 64 Word.word)) in + (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let (tmp_320 :: DescriptorUpdate) = + ((tmp_320 (| DescriptorUpdate_AP := True |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_descupdate := tmp_320 |))) in + (desc, result))))) + else (desc, result)) in + (desc, result)) + else (desc, result)) in + (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in + (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in + liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (xn :: 1 bits) . + liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (pxn :: 1 bits) . + (let (xn :: 1 bits) = + (if apply_nvnv1_effect then + (let (pxn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 :: int)::ii)] :: 1 Word.word)) in + (vec_of_bits [B0] :: 1 Word.word)) + else + (let (xn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 :: int)::ii)] :: 1 Word.word)) in + (let (pxn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 :: int)::ii)] :: 1 Word.word)) in + xn))) in + (let (contiguousbit :: 1 bits) = + ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word)) in + (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)] :: 1 Word.word)) in + (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \ (\ (ap :: 3 bits) . + (let (ap :: 3 bits) = + (if apply_nvnv1_effect then + (concat_vec (vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 3 Word.word) + else + (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \ (\ (w__51 :: 4 bits) . + (let result = ((result (| TLBRecord_domain := w__51 |))) in + (let result = ((result (| TLBRecord_level := level |))) in + (let result = + ((result (| + TLBRecord_blocksize := + ((pow2 + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))))|))) in + (let (tmp_480 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_480 = + ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + :: 3 Word.word)) in + (let (tmp_490 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in + (let result = ((result (| TLBRecord_perms := tmp_490 |))) in + (let (tmp_500 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_500 = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (tmp_510 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in + (let result = ((result (| TLBRecord_perms := tmp_510 |))) in + (let (tmp_520 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_520 = ((tmp_520 (| Permissions_xn := xn |))) in + (let result = ((result (| TLBRecord_perms := tmp_520 |))) in + (let (result :: TLBRecord) = + (if ((HaveExtendedExecuteNeverExt () )) then + (let (tmp_530 :: Permissions) = ((TLBRecord_perms result)) in + (let (tmp_530 :: Permissions) = + ((tmp_530 (| + Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 :: int)::ii)] :: 1 Word.word))|))) in + (result (| TLBRecord_perms := tmp_530 |)))) + else result) in + (let (tmp_540 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_540 = ((tmp_540 (| Permissions_pxn := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_540 |))) in + (let result = ((result (| TLBRecord_nG := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let (tmp_550 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (S2AttrDecode sh memattr acctype) \ (\ (w__52 :: MemoryAttributes) . + (let tmp_550 = ((tmp_550 (| AddressDescriptor_memattrs := w__52 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_550 |))) in + (let (tmp_560 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let tmp_560 = ((tmp_560 (| FullAddress_NS := ((vec_of_bits [B1] :: 1 Word.word))|))) in + (let (tmp_570 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_570 = ((tmp_570 (| AddressDescriptor_paddress := tmp_560 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_570 |))) in + (let (tmp_580 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let tmp_580 = ((tmp_580 (| FullAddress_physicaladdress := outputaddress |))) in + (let (tmp_590 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_590 = ((tmp_590 (| AddressDescriptor_paddress := tmp_580 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_590 |))) in + (let (tmp_600 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_NoFault () ) \ (\ (w__53 :: FaultRecord) . + (let (tmp_600 :: AddressDescriptor) = ((tmp_600 (| AddressDescriptor_fault := w__53 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_600 |))) in + (let (result :: TLBRecord) = + ((result (| + TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1] :: 1 Word.word))))|))) in + (let (result :: TLBRecord) = + (if ((HaveCommonNotPrivateTransExt () )) then + (result (| + TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 :: int)::ii)] :: 1 Word.word))|)) + else result) in + return result)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +definition AArch64_SecondStageTranslate :: " AddressDescriptor \(64)Word.word \ AccType \ bool \ bool \ bool \ int \ bool \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk = ( + HasS2Translation () \ (\ (w__0 :: bool) . + (assert_exp w__0 (''HasS2Translation()'') \ + or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 12 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (s2_enabled :: bool) . + (let (secondstage :: bool) = True in + undefined_AddressDescriptor () \ (\ (result :: AddressDescriptor) . + undefined_TLBRecord () \ (\ (S2 :: TLBRecord) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + if s2_enabled then + (let ipaddress = + ((slice0(FullAddress_physicaladdress (AddressDescriptor_paddress S1)) (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in + AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1 \ (\ (w__3 :: + TLBRecord) . + (let S2 = w__3 in + (if ((((((((((((((\ wasaligned)) \ (((acctype \ AccType_IFETCH)))))) \ (((acctype = AccType_DCZVA)))))) \ ((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S2))) = MemType_Device)))))) \ ((\ ((IsFault(TLBRecord_addrdesc S2)))))))) then + (let (tmp_710 :: AddressDescriptor) = ((TLBRecord_addrdesc S2)) in + AArch64_AlignmentFault acctype iswrite secondstage \ (\ (w__4 :: FaultRecord) . + (let (tmp_710 :: AddressDescriptor) = ((tmp_710 (| AddressDescriptor_fault := w__4 |))) in + (let (S2 :: TLBRecord) = ((S2 (| TLBRecord_addrdesc := tmp_710 |))) in + return S2)))) + else return S2) \ (\ (S2 :: TLBRecord) . + (if ((\ ((IsFault(TLBRecord_addrdesc S2))))) then + (let (tmp_720 :: AddressDescriptor) = ((TLBRecord_addrdesc S2)) in + AArch64_CheckS2Permission(TLBRecord_perms S2) vaddress ipaddress(TLBRecord_level S2) acctype + iswrite s2fs1walk hwupdatewalk \ (\ (w__5 :: FaultRecord) . + (let (tmp_720 :: AddressDescriptor) = ((tmp_720 (| AddressDescriptor_fault := w__5 |))) in + (let (S2 :: TLBRecord) = ((S2 (| TLBRecord_addrdesc := tmp_720 |))) in + return S2)))) + else return S2) \ (\ (S2 :: TLBRecord) . + (if (((((((((((\ s2fs1walk)) \ ((\ ((IsFault(TLBRecord_addrdesc S2)))))))) \ ((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S2))) = MemType_Device)))))) \ (((acctype = AccType_IFETCH)))))) then + AArch64_InstructionDevice(TLBRecord_addrdesc S2) vaddress ipaddress(TLBRecord_level S2) + acctype iswrite secondstage s2fs1walk \ (\ (w__6 :: AddressDescriptor) . + (let (S2 :: TLBRecord) = ((S2 (| TLBRecord_addrdesc := w__6 |))) in + return S2)) + else return S2) \ (\ (S2 :: TLBRecord) . + and_boolM + (and_boolM (return (((s2fs1walk \ ((\ ((IsFault(TLBRecord_addrdesc S2))))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (return ((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S2))) = MemType_Device)))) \ (\ (w__9 :: bool) . + (if w__9 then + (let (tmp_730 :: AddressDescriptor) = ((TLBRecord_addrdesc S2)) in + AArch64_PermissionFault ipaddress(TLBRecord_level S2) acctype iswrite secondstage s2fs1walk \ (\ (w__10 :: + FaultRecord) . + (let (tmp_730 :: AddressDescriptor) = ((tmp_730 (| AddressDescriptor_fault := w__10 |))) in + (let (S2 :: TLBRecord) = ((S2 (| TLBRecord_addrdesc := tmp_730 |))) in + return S2)))) + else return S2) \ (\ (S2 :: TLBRecord) . + (let (tmp_740 :: AddressDescriptor) = ((TLBRecord_addrdesc S2)) in + AArch64_CheckAndUpdateDescriptor_SecondStage(TLBRecord_descupdate S2)(AddressDescriptor_fault (TLBRecord_addrdesc + S2)) vaddress acctype iswrite s2fs1walk hwupdatewalk \ (\ (w__11 :: + FaultRecord) . + (let tmp_740 = ((tmp_740 (| AddressDescriptor_fault := w__11 |))) in + (let S2 = ((S2 (| TLBRecord_addrdesc := tmp_740 |))) in + CombineS1S2Desc S1(TLBRecord_addrdesc S2))))))))))))) + else return S1)))))))" + + +definition AArch64_SecondStageWalk :: " AddressDescriptor \(64)Word.word \ AccType \ bool \ int \ bool \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_SecondStageWalk S1 vaddress acctype iswrite size1 hwupdatewalk = ( + HasS2Translation () \ (\ (w__0 :: bool) . + assert_exp w__0 (''HasS2Translation()'') \ + ((let (s2fs1walk :: bool) = True in + (let (wasaligned :: bool) = True in + AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk)))))" + + +(*val DoubleLockStatus : unit -> M bool*) + +definition DoubleLockStatus :: " unit \((register_value),(bool),(exception))monad " where + " DoubleLockStatus _ = ( + ELUsingAArch32 EL1 \ (\ (w__0 :: bool) . + if w__0 then + and_boolM + (and_boolM + ((read_reg DBGOSDLR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg DBGPRCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (Halted () \ (\ (w__4 :: bool) . return ((\ w__4)))) + else + and_boolM + (and_boolM + ((read_reg OSDLR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg DBGPRCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (Halted () \ (\ (w__9 :: bool) . return ((\ w__9))))))" + + +(*val HaltingAllowed : unit -> M bool*) + +definition HaltingAllowed :: " unit \((register_value),(bool),(exception))monad " where + " HaltingAllowed _ = ( + or_boolM ((Halted () )) ((DoubleLockStatus () )) \ (\ (w__2 :: bool) . + if w__2 then return False + else + IsSecure () \ (\ (w__3 :: bool) . + if w__3 then ExternalSecureInvasiveDebugEnabled () + else ExternalInvasiveDebugEnabled () )))" + + +(*val system_exceptions_debug_halt_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_debug_halt_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_debug_halt_decode opc imm16 op2 LL = ( + (write_reg unconditional_ref True \ + or_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 14 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + (HaltingAllowed () \ (\ (w__1 :: bool) . return ((\ w__1))))) \ (\ (w__2 :: bool) . + (if w__2 then UndefinedFault () else return () ) \ aarch64_system_exceptions_debug_halt () ))" + + +(*val HaltOnBreakpointOrWatchpoint : unit -> M bool*) + +definition HaltOnBreakpointOrWatchpoint :: " unit \((register_value),(bool),(exception))monad " where + " HaltOnBreakpointOrWatchpoint _ = ( + and_boolM + (and_boolM ((HaltingAllowed () )) + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 14 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg OSLSR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))))" + + +(*val DebugTargetFrom : bool -> M (mword ty2)*) + +definition DebugTargetFrom :: " bool \((register_value),((2)Word.word),(exception))monad " where + " DebugTargetFrom secure = ( + undefined_bool () \ (\ (route_to_el2 :: bool) . + (if (((((HaveEL EL2)) \ ((\ secure))))) then + ELUsingAArch32 EL2 \ (\ (w__0 :: bool) . + if w__0 then + or_boolM + ((read_reg HDCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg HCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + else + or_boolM + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + else return False) \ (\ (route_to_el2 :: bool) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (target :: 2 bits) . + (let (target :: 2 bits) = + (if route_to_el2 then EL2 + else if ((((((((HaveEL EL3)) \ ((HighestELUsingAArch32 () ))))) \ secure))) then EL3 + else EL1) in + return target)))))" + + +(*val DebugTarget : unit -> M (mword ty2)*) + +definition DebugTarget :: " unit \((register_value),((2)Word.word),(exception))monad " where + " DebugTarget _ = ( + IsSecure () \ (\ (secure :: bool) . (DebugTargetFrom secure :: ( 2 Word.word) M)))" + + +(*val SSAdvance : unit -> M unit*) + +definition SSAdvance :: " unit \((register_value),(unit),(exception))monad " where + " SSAdvance _ = ( + (DebugTarget () :: ( 2 Word.word) M) \ (\ (target :: 2 bits) . + and_boolM (ELUsingAArch32 target \ (\ (w__0 :: bool) . return ((\ w__0)))) + ((read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (step_enabled :: bool) . + and_boolM (return step_enabled) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + return ((((ProcState_SS w__2) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (active_not_pending :: + bool) . + if active_not_pending then + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|))) + else return () ))))" + + +(*val ConditionHolds : mword ty4 -> M bool*) + +definition ConditionHolds :: "(4)Word.word \((register_value),(bool),(exception))monad " where + " ConditionHolds cond = ( + undefined_bool () \ (\ (result :: bool) . + (let b__0 = ((slice0 cond (( 1 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (let (result :: bool) = ((ProcState_Z w__0) = (vec_of_bits [B1] :: 1 Word.word)) in + return result)) + else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (let (result :: bool) = ((ProcState_C w__1) = (vec_of_bits [B1] :: 1 Word.word)) in + return result)) + else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (let (result :: bool) = ((ProcState_N w__2) = (vec_of_bits [B1] :: 1 Word.word)) in + return result)) + else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (let (result :: bool) = ((ProcState_V w__3) = (vec_of_bits [B1] :: 1 Word.word)) in + return result)) + else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + and_boolM + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_C w__4) = (vec_of_bits [B1] :: 1 Word.word)))))) + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_Z w__5) = (vec_of_bits [B0] :: 1 Word.word)))))) + else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (let (result :: bool) = ((ProcState_N w__7) =(ProcState_V w__8)) in + return result))) + else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + and_boolM + (read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + return ((((ProcState_N w__9) =(ProcState_V w__10))))))) + (read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + return ((((ProcState_Z w__11) = (vec_of_bits [B0] :: 1 Word.word)))))) + else return True) \ (\ (result :: bool) . + (let (result :: bool) = + (if (((((((vec_of_bits [access_vec_dec cond (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((cond \ (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word))))))) then + \ result + else result) in + return result)))))" + + +(*val aarch64_integer_conditional_select : mword ty4 -> ii -> ii -> bool -> bool -> ii -> ii -> M unit*) + +definition aarch64_integer_conditional_select :: "(4)Word.word \ int \ int \ bool \ bool \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_conditional_select condition d l__153 else_inc else_inv m n = ( + if (((l__153 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + ConditionHolds condition \ (\ (w__0 :: bool) . + (let (result :: 8 bits) = + (if w__0 then operand1 + else + (let (result :: 8 bits) = operand2 in + (let (result :: 8 bits) = (if else_inv then (not_vec result :: 8 Word.word) else result) in + if else_inc then (add_vec_int result (( 1 :: int)::ii) :: 8 Word.word) + else result))) in + aset_X d result)))))) + else if (((l__153 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + ConditionHolds condition \ (\ (w__1 :: bool) . + (let (result :: 16 bits) = + (if w__1 then operand1 + else + (let (result :: 16 bits) = operand2 in + (let (result :: 16 bits) = (if else_inv then (not_vec result :: 16 Word.word) else result) in + if else_inc then (add_vec_int result (( 1 :: int)::ii) :: 16 Word.word) + else result))) in + aset_X d result)))))) + else if (((l__153 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + ConditionHolds condition \ (\ (w__2 :: bool) . + (let (result :: 32 bits) = + (if w__2 then operand1 + else + (let (result :: 32 bits) = operand2 in + (let (result :: 32 bits) = (if else_inv then (not_vec result :: 32 Word.word) else result) in + if else_inc then (add_vec_int result (( 1 :: int)::ii) :: 32 Word.word) + else result))) in + aset_X d result)))))) + else if (((l__153 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + ConditionHolds condition \ (\ (w__3 :: bool) . + (let (result :: 64 bits) = + (if w__3 then operand1 + else + (let (result :: 64 bits) = operand2 in + (let (result :: 64 bits) = (if else_inv then (not_vec result :: 64 Word.word) else result) in + if else_inc then (add_vec_int result (( 1 :: int)::ii) :: 64 Word.word) + else result))) in + aset_X d result)))))) + else if (((l__153 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + ConditionHolds condition \ (\ (w__4 :: bool) . + (let (result :: 128 bits) = + (if w__4 then operand1 + else + (let (result :: 128 bits) = operand2 in + (let (result :: 128 bits) = (if else_inv then (not_vec result :: 128 Word.word) else result) in + if else_inc then (add_vec_int result (( 1 :: int)::ii) :: 128 Word.word) + else result))) in + aset_X d result)))))) + else + (let dbytes = (ex_int ((l__153 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_conditional_select_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_conditional_select_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_conditional_select_decode sf op1 S Rm cond o2 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (condition :: 4 bits) = cond in + (let (else_inv :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (else_inc :: bool) = (o2 = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_conditional_select condition d datasize else_inc else_inv m n)))))))))" + + +(*val aarch64_integer_conditional_compare_register : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*) + +definition aarch64_integer_conditional_compare_register :: "(4)Word.word \ int \(4)Word.word \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_conditional_compare_register condition l__148 flags__arg m n sub_op = ( + if (((l__148 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (anon10 :: 8 bits) . + ConditionHolds condition \ (\ (w__0 :: bool) . + (let (flags :: 4 Word.word) = + (if w__0 then + (let ((carry_in :: 1 bits), (operand2 :: 8 bits)) = + (if sub_op then + (let (operand2 :: 8 bits) = ((not_vec operand2 :: 8 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: ( 8 Word.word * 4 Word.word))) in + (let (anon10 :: 8 bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + write_reg PSTATE_ref (w__4 (| ProcState_V := tup__3 |)))))))))))))))) + else if (((l__148 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (anon10 :: 16 bits) . + ConditionHolds condition \ (\ (w__5 :: bool) . + (let (flags :: 4 Word.word) = + (if w__5 then + (let ((carry_in :: 1 bits), (operand2 :: 16 bits)) = + (if sub_op then + (let (operand2 :: 16 bits) = ((not_vec operand2 :: 16 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in :: ( 16 Word.word * 4 Word.word))) in + (let (anon10 :: 16 bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + (write_reg PSTATE_ref (w__7 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + write_reg PSTATE_ref (w__9 (| ProcState_V := tup__3 |)))))))))))))))) + else if (((l__148 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (anon10 :: 32 bits) . + ConditionHolds condition \ (\ (w__10 :: bool) . + (let (flags :: 4 Word.word) = + (if w__10 then + (let ((carry_in :: 1 bits), (operand2 :: 32 bits)) = + (if sub_op then + (let (operand2 :: 32 bits) = ((not_vec operand2 :: 32 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in :: ( 32 Word.word * 4 Word.word))) in + (let (anon10 :: 32 bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + write_reg PSTATE_ref (w__14 (| ProcState_V := tup__3 |)))))))))))))))) + else if (((l__148 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (anon10 :: 64 bits) . + ConditionHolds condition \ (\ (w__15 :: bool) . + (let (flags :: 4 Word.word) = + (if w__15 then + (let ((carry_in :: 1 bits), (operand2 :: 64 bits)) = + (if sub_op then + (let (operand2 :: 64 bits) = ((not_vec operand2 :: 64 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in :: ( 64 Word.word * 4 Word.word))) in + (let (anon10 :: 64 bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |)))))))))))))))) + else if (((l__148 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (anon10 :: 128 bits) . + ConditionHolds condition \ (\ (w__20 :: bool) . + (let (flags :: 4 Word.word) = + (if w__20 then + (let ((carry_in :: 1 bits), (operand2 :: 128 bits)) = + (if sub_op then + (let (operand2 :: 128 bits) = ((not_vec operand2 :: 128 Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in :: ( 128 Word.word * 4 Word.word))) in + (let (anon10 :: 128 bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__21 :: ProcState) . + (write_reg PSTATE_ref (w__21 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg PSTATE_ref (w__23 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + write_reg PSTATE_ref (w__24 (| ProcState_V := tup__3 |)))))))))))))))) + else + (let dbytes = (ex_int ((l__148 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val integer_conditional_compare_register_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +definition integer_conditional_compare_register_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(4)Word.word \((register_value),(unit),(exception))monad " where + " integer_conditional_compare_register_decode sf op1 S Rm cond o2 Rn o3 nzcv = ( + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (condition :: 4 bits) = cond in + (let (flags :: 4 bits) = nzcv in + aarch64_integer_conditional_compare_register condition datasize flags m n sub_op))))))))" + + +(*val aarch64_integer_conditional_compare_immediate : forall 'datasize. Size 'datasize => mword ty4 -> itself 'datasize -> mword ty4 -> mword 'datasize -> ii -> bool -> M unit*) + +definition aarch64_integer_conditional_compare_immediate :: "(4)Word.word \('datasize::len)itself \(4)Word.word \('datasize::len)Word.word \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_conditional_compare_immediate condition datasize flags__arg imm n sub_op = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \ (\ (operand1 :: 'datasize bits) . + (let (operand2 :: 'datasize bits) = imm in + (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (anon10 :: 'datasize bits) . + ConditionHolds condition \ (\ (w__0 :: bool) . + (let (flags :: 4 Word.word) = + (if w__0 then + (let ((carry_in :: 1 bits), (operand2 :: 'datasize bits)) = + (if sub_op then + (let (operand2 :: 'datasize bits) = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in + (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + (carry_in, operand2))) + else (carry_in, operand2)) in + (let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in :: (( 'datasize::len)Word.word * 4 Word.word))) in + (let (anon10 :: 'datasize bits) = tup__0 in + tup__1))) + else flags) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + write_reg PSTATE_ref (w__4 (| ProcState_V := tup__3 |))))))))))))))))))" + + +(*val integer_conditional_compare_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +definition integer_conditional_compare_immediate_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(4)Word.word \((register_value),(unit),(exception))monad " where + " integer_conditional_compare_immediate_decode b__0 op1 S imm5 cond o2 Rn o3 nzcv = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (condition :: 4 bits) = cond in + (let (flags :: 4 bits) = nzcv in + (ZeroExtend__0 imm5 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (imm :: 32 + bits) . + aarch64_integer_conditional_compare_immediate condition + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) flags imm n sub_op)))))) + else + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (condition :: 4 bits) = cond in + (let (flags :: 4 bits) = nzcv in + (ZeroExtend__0 imm5 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (imm :: 64 + bits) . + aarch64_integer_conditional_compare_immediate condition + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) flags imm n sub_op)))))))" + + +(*val ConditionSyndrome : unit -> M (mword ty5)*) + +definition ConditionSyndrome :: " unit \((register_value),((5)Word.word),(exception))monad " where + " ConditionSyndrome _ = ( + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \ (\ (syndrome :: 5 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (cond :: 4 bits) . + UsingAArch32 () \ (\ (w__0 :: bool) . + if w__0 then + (AArch32_CurrentCond () :: ( 4 Word.word) M) \ (\ (w__1 :: 4 bits) . + (let cond = w__1 in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + if ((((ProcState_T w__2) = (vec_of_bits [B0] :: 1 Word.word)))) then + (let syndrome = + ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + and_boolM ((ConditionHolds cond)) ((ConstrainUnpredictableBool Unpredictable_ESRCONDPASS)) \ (\ (w__5 :: + bool) . + (let (syndrome :: 5 bits) = + (if w__5 then + (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 5 Word.word) + else (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in + return syndrome))) + else if ((IMPDEF_boolean (''Condition valid for trapped T32''))) then + (let (syndrome :: 5 bits) = + ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in + return syndrome)) + else + (let syndrome = + ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__6 :: 4 Word.word) . + (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) w__6 :: 5 Word.word)) in + return syndrome)))))) + else + (let (syndrome :: 5 bits) = + ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + (let (syndrome :: 5 bits) = + ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + :: 5 Word.word)) in + return syndrome))))))" + + +(*val BranchToAddr : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*) + +definition BranchToAddr :: "('N::len)Word.word \ BranchType \((register_value),(unit),(exception))monad " where + " BranchToAddr target branch_type = ( + write_reg BranchTaken_ref True \ + ((let (_ :: unit) = (Hint_Branch branch_type) in + if (((((int (size target))) = (( 32 :: int)::ii)))) then + UsingAArch32 () \ (\ (w__0 :: bool) . + (assert_exp w__0 (''UsingAArch32()'') \ + (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 bits) . + write_reg PC_ref w__1)) + else + and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) + (UsingAArch32 () \ (\ (w__2 :: bool) . return ((\ w__2)))) \ (\ (w__3 :: bool) . + assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \ + write_reg PC_ref ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word))))))" + + +(*val BadMode : mword ty5 -> M bool*) + +definition BadMode :: "(5)Word.word \((register_value),(bool),(exception))monad " where + " BadMode mode = ( + undefined_bool () \ (\ (valid_name :: bool) . + (let pat0 = mode in + (let (valid_name :: bool) = + (if (((pat0 = M32_Monitor))) then HaveAArch32EL EL3 + else if (((pat0 = M32_Hyp))) then HaveAArch32EL EL2 + else if (((pat0 = M32_FIQ))) then HaveAArch32EL EL1 + else if (((pat0 = M32_IRQ))) then HaveAArch32EL EL1 + else if (((pat0 = M32_Svc))) then HaveAArch32EL EL1 + else if (((pat0 = M32_Abort))) then HaveAArch32EL EL1 + else if (((pat0 = M32_Undef))) then HaveAArch32EL EL1 + else if (((pat0 = M32_System))) then HaveAArch32EL EL1 + else if (((pat0 = M32_User))) then HaveAArch32EL EL0 + else False) in + return ((\ valid_name))))))" + + +(*val aset_Rmode : ii -> mword ty5 -> mword ty32 -> M unit*) + +definition aset_Rmode :: " int \(5)Word.word \(32)Word.word \((register_value),(unit),(exception))monad " where + " aset_Rmode n mode value_name = ( + (assert_exp (((((n \ (( 0 :: int)::ii))) \ ((n \ (( 14 :: int)::ii)))))) (''((n >= 0) && (n <= 14))'') \ + IsSecure () ) \ (\ (w__0 :: bool) . + ((if ((\ w__0)) then assert_exp (((mode \ M32_Monitor))) (''(mode != M32_Monitor)'') + else return () ) \ + BadMode mode) \ (\ (w__1 :: bool) . + assert_exp ((\ w__1)) (''!(BadMode(mode))'') \ + (if (((mode = M32_Monitor))) then + if (((n = (( 13 :: int)::ii)))) then write_reg SP_mon_ref value_name + else if (((n = (( 14 :: int)::ii)))) then write_reg LR_mon_ref value_name + else + read_reg R_ref \ (\ (w__2 :: ( 64 bits) list) . + (let (tmp_10 :: 64 bits) = ((access_list_dec w__2 n :: 64 Word.word)) in + (let tmp_10 = ((update_subrange_vec_dec tmp_10 (( 31 :: int)::ii) (( 0 :: int)::ii) value_name :: 64 Word.word)) in + read_reg R_ref \ (\ (w__3 :: ( 64 Word.word) list) . + write_reg R_ref ((update_list_dec w__3 n tmp_10 :: ( 64 Word.word) list)))))) + else + and_boolM (return ((\ ((HighestELUsingAArch32 () ))))) + ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER)) \ (\ (w__5 :: bool) . + if w__5 then + read_reg R_ref \ (\ (w__6 :: ( 64 Word.word) list) . + LookUpRIndex n mode \ (\ (w__7 :: ii) . + (ZeroExtend__0 value_name ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__8 :: + 64 Word.word) . + write_reg R_ref ((update_list_dec w__6 w__7 w__8 :: ( 64 Word.word) list))))) + else + read_reg R_ref \ (\ (w__9 :: ( 64 bits) list) . + LookUpRIndex n mode \ (\ (w__10 :: ii) . + (let (tmp_20 :: 64 bits) = ((access_list_dec w__9 w__10 :: 64 Word.word)) in + (let tmp_20 = ((update_subrange_vec_dec tmp_20 (( 31 :: int)::ii) (( 0 :: int)::ii) value_name :: 64 Word.word)) in + read_reg R_ref \ (\ (w__11 :: ( 64 Word.word) list) . + LookUpRIndex n mode \ (\ (w__12 :: ii) . + write_reg R_ref ((update_list_dec w__11 w__12 tmp_20 :: ( 64 Word.word) list)))))))))))))" + + +(*val aset_R : ii -> mword ty32 -> M unit*) + +definition aset_R :: " int \(32)Word.word \((register_value),(unit),(exception))monad " where + " aset_R n value_name = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . aset_Rmode n(ProcState_M w__0) value_name))" + + +(*val set_LR : mword ty32 -> M unit*) + +definition set_LR :: "(32)Word.word \((register_value),(unit),(exception))monad " where + " set_LR value_name = ( aset_R (( 14 :: int)::ii) value_name )" + + +(*val ELFromM32 : mword ty5 -> M (bool * mword ty2)*) + +definition ELFromM32 :: "(5)Word.word \((register_value),(bool*(2)Word.word),(exception))monad " where + " ELFromM32 mode = ( + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (el :: 2 bits) . + BadMode mode \ (\ (w__0 :: bool) . + (let (valid_name :: bool) = (\ w__0) in + (let pat0 = mode in + (if (((pat0 = M32_Monitor))) then + (let (el :: 2 bits) = EL3 in + return (el, valid_name)) + else if (((pat0 = M32_Hyp))) then + (let el = EL2 in + and_boolM (return valid_name) + (or_boolM (return ((\ ((HaveEL EL3))))) + ((aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__1 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (w__3 :: bool) . + (let (valid_name :: bool) = w__3 in + return (el, valid_name)))) + else if (((pat0 = M32_FIQ))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__5 :: bool) . + (let (el :: 2 bits) = (if w__5 then EL3 else EL1) in + return (el, valid_name))) + else if (((pat0 = M32_IRQ))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__7 :: bool) . + (let (el :: 2 bits) = (if w__7 then EL3 else EL1) in + return (el, valid_name))) + else if (((pat0 = M32_Svc))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__9 :: bool) . + (let (el :: 2 bits) = (if w__9 then EL3 else EL1) in + return (el, valid_name))) + else if (((pat0 = M32_Abort))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__10 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__11 :: bool) . + (let (el :: 2 bits) = (if w__11 then EL3 else EL1) in + return (el, valid_name))) + else if (((pat0 = M32_Undef))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__13 :: bool) . + (let (el :: 2 bits) = (if w__13 then EL3 else EL1) in + return (el, valid_name))) + else if (((pat0 = M32_System))) then + and_boolM (return (((((HaveEL EL3)) \ ((HighestELUsingAArch32 () )))))) + ((read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__15 :: bool) . + (let (el :: 2 bits) = (if w__15 then EL3 else EL1) in + return (el, valid_name))) + else + (let ((el :: 2 bits), (valid_name :: bool)) = + (if (((pat0 = M32_User))) then + (let (el :: 2 bits) = EL0 in + (el, valid_name)) + else + (let (valid_name :: bool) = False in + (el, valid_name))) in + return (el, valid_name))) \ (\ varstup . (let ((el :: 2 bits), (valid_name :: bool)) = varstup in + (if ((\ valid_name)) then (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) + else return el) \ (\ (el :: 2 bits) . + return (valid_name, el)))))))))" + + +(*val ELFromSPSR : mword ty32 -> M (bool * mword ty2)*) + +definition ELFromSPSR :: "(32)Word.word \((register_value),(bool*(2)Word.word),(exception))monad " where + " ELFromSPSR spsr = ( + undefined_bool () \ (\ (valid_name :: bool) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (el :: 2 bits) . + (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + (let el = ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (if ((HighestELUsingAArch32 () )) then return False + else if ((\ ((HaveEL el)))) then return False + else if ((((vec_of_bits [access_vec_dec spsr (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + return False + else if ((((((el = EL0))) \ ((((vec_of_bits [access_vec_dec spsr (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + return False + else + and_boolM (return ((((((el = EL2))) \ ((HaveEL EL3)))))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (w__1 :: bool) . + (let (valid_name :: bool) = (if w__1 then False else True) in + return valid_name))) \ (\ (valid_name :: bool) . + return (el, valid_name))) + else if ((\ ((HaveAnyAArch32 () )))) then + (let (valid_name :: bool) = False in + return (el, valid_name)) + else + (ELFromM32 ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) :: ((bool * 2 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let (valid_name :: bool) = tup__0 in + (let (el :: 2 bits) = tup__1 in + return (el, valid_name)))))) \ (\ varstup . (let ((el :: 2 bits), (valid_name :: bool)) = varstup in + (if ((\ valid_name)) then (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) + else return el) \ (\ (el :: 2 bits) . + return (valid_name, el)))))))" + + +(*val IllegalExceptionReturn : mword ty32 -> M bool*) + +definition IllegalExceptionReturn :: "(32)Word.word \((register_value),(bool),(exception))monad " where + " IllegalExceptionReturn spsr = ( + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (target :: 2 bits) . + undefined_bool () \ (\ (valid_name :: bool) . + (ELFromSPSR spsr :: ((bool * 2 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let valid_name = tup__0 in + (let target = tup__1 in + if ((\ valid_name)) then return True + else + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + if ((((Word.uint target)) > ((Word.uint(ProcState_EL w__0))))) then return True + else + (let (spsr_mode_is_aarch32 :: bool) = + ((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + undefined_bool () \ (\ (target_el_is_aarch32 :: bool) . + undefined_bool () \ (\ (known :: bool) . + ELUsingAArch32K target \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let known = tup__0 in + (let target_el_is_aarch32 = tup__1 in + or_boolM (return known) + (and_boolM (return (((target = EL0)))) + (ELUsingAArch32 EL1 \ (\ (w__1 :: bool) . return ((\ w__1))))) \ (\ (w__3 :: bool) . + assert_exp w__3 (''(known || ((target == EL0) && !(ELUsingAArch32(EL1))))'') \ + (if (((known \ ((neq_bool spsr_mode_is_aarch32 target_el_is_aarch32))))) then return True + else + and_boolM ((UsingAArch32 () )) (return ((\ spsr_mode_is_aarch32))) \ (\ (w__5 :: bool) . + if w__5 then return True + else + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ (((target = EL1))))))) + (IsSecureBelowEL3 () \ (\ (w__6 :: bool) . return ((\ w__6))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__9 :: bool) . + return (if w__9 then True + else False))))))))))))))))))))" + + +(*val AArch32_WriteMode : mword ty5 -> M unit*) + +definition AArch32_WriteMode :: "(5)Word.word \((register_value),(unit),(exception))monad " where + " AArch32_WriteMode mode = ( + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (el :: 2 bits) . + undefined_bool () \ (\ (valid_name :: bool) . + (ELFromM32 mode :: ((bool * 2 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let valid_name = tup__0 in + (let el = tup__1 in + (assert_exp valid_name (''valid'') \ + read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_M := mode |)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_EL := el |)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_nRW := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + write_reg + PSTATE_ref + (w__3 (| + ProcState_SP := + (if ((((((mode = M32_User))) \ (((mode = M32_System)))))) then + (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word))|)))))))))))))" + + +(*val AddrTop : mword ty64 -> bool -> mword ty2 -> M ii*) + +definition AddrTop :: "(64)Word.word \ bool \(2)Word.word \((register_value),(int),(exception))monad " where + " AddrTop address IsInstr el = ( + (assert_exp ((HaveEL el)) (''HaveEL(el)'') \ + (S1TranslationRegime__0 el :: ( 2 Word.word) M)) \ (\ (regime :: 2 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (tbid :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (tbi :: 1 bits) . + ELUsingAArch32 regime \ (\ (w__0 :: bool) . + if w__0 then return (( 31 :: int)::ii) + else + (let pat0 = regime in + (if (((pat0 = EL1))) then + (if ((((vec_of_bits [access_vec_dec address (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__1 (( 38 :: int)::ii)] :: 1 Word.word)) + else + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__2 (( 37 :: int)::ii)] :: 1 Word.word))) \ (\ (w__3 :: + 1 Word.word) . + (let tbi = w__3 in + (if ((HavePACExt () )) then + if ((((vec_of_bits [access_vec_dec address (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__4 (( 52 :: int)::ii)] :: 1 Word.word)) + else + (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__5 (( 51 :: int)::ii)] :: 1 Word.word)) + else return tbid) \ (\ (tbid :: 1 bits) . + return (tbi, tbid)))) + else if (((pat0 = EL2))) then + and_boolM (return ((HaveVirtHostExt () ))) ((ELIsInHost el)) \ (\ (w__8 :: bool) . + if w__8 then + (if ((((vec_of_bits [access_vec_dec address (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__9 (( 38 :: int)::ii)] :: 1 Word.word)) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__10 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__10 (( 37 :: int)::ii)] :: 1 Word.word))) \ (\ (w__11 :: + 1 Word.word) . + (let tbi = w__11 in + (if ((HavePACExt () )) then + if ((((vec_of_bits [access_vec_dec address (( 55 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__12 (( 52 :: int)::ii)] :: 1 Word.word)) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__13 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__13 (( 51 :: int)::ii)] :: 1 Word.word)) + else return tbid) \ (\ (tbid :: 1 bits) . + return (tbi, tbid)))) + else + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + (let tbi = ((vec_of_bits [access_vec_dec w__15 (( 20 :: int)::ii)] :: 1 Word.word)) in + (if ((HavePACExt () )) then + (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__16 :: 64 bits) . + (let (tbid :: 1 bits) = ((vec_of_bits [access_vec_dec w__16 (( 29 :: int)::ii)] :: 1 Word.word)) in + return tbid)) + else return tbid) \ (\ (tbid :: 1 bits) . + return (tbi, tbid))))) + else + (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__17 :: 32 bits) . + (let tbi = ((vec_of_bits [access_vec_dec w__17 (( 20 :: int)::ii)] :: 1 Word.word)) in + (if ((HavePACExt () )) then + (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 bits) . + (let (tbid :: 1 bits) = ((vec_of_bits [access_vec_dec w__18 (( 29 :: int)::ii)] :: 1 Word.word)) in + return tbid)) + else return tbid) \ (\ (tbid :: 1 bits) . + return (tbi, tbid))))) \ (\ varstup . (let ((tbi :: 1 bits), (tbid :: 1 bits)) = varstup in + return (if ((((((tbi = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((\ ((HavePACExt () )))) \ (((tbid = (vec_of_bits [B0] :: 1 Word.word))))))) \ ((\ IsInstr)))))))) + then + (( 55 :: int)::ii) + else (( 63 :: int)::ii))))))))))" + + +(*val AddPAC : mword ty64 -> mword ty64 -> mword ty128 -> bool -> M (mword ty64)*) + +definition AddPAC :: "(64)Word.word \(64)Word.word \(128)Word.word \ bool \((register_value),((64)Word.word),(exception))monad " where + " AddPAC ptr modifier K data = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (PAC :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (ext_ptr :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (extfield :: 64 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (selbit :: 1 bits) . + CalculateTBI ptr data \ (\ (tbi :: bool) . + (let (top_bit :: int) = (if tbi then (( 55 :: int)::ii) else (( 63 :: int)::ii)) in + PtrHasUpperAndLowerAddRanges () \ (\ (w__0 :: bool) . + (if w__0 then + IsEL1TransRegimeRegs () \ (\ (w__1 :: bool) . + if w__1 then + if data then + or_boolM + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__4 :: bool) . + (let (selbit :: 1 bits) = + (if w__4 then (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) + else (vec_of_bits [access_vec_dec ptr (( 63 :: int)::ii)] :: 1 Word.word)) in + return selbit)) + else + or_boolM + (and_boolM + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (and_boolM + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__11 :: bool) . + (let (selbit :: 1 bits) = + (if w__11 then (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) + else (vec_of_bits [access_vec_dec ptr (( 63 :: int)::ii)] :: 1 Word.word)) in + return selbit)) + else if data then + or_boolM + (and_boolM (return ((HaveEL EL2))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (and_boolM (return ((HaveEL EL2))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (w__16 :: bool) . + (let (selbit :: 1 bits) = + (if w__16 then (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) + else (vec_of_bits [access_vec_dec ptr (( 63 :: int)::ii)] :: 1 Word.word)) in + return selbit)) + else + or_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__17 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__17 (( 38 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__19 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__19 (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (and_boolM + (and_boolM (return ((HaveEL EL2))) + ((read_reg TCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__21 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__21 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg TCR_EL1_ref :: ( 64 Word.word) M) \ (\ (w__23 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__25 :: bool) . + (let (selbit :: 1 bits) = + (if w__25 then (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) + else (vec_of_bits [access_vec_dec ptr (( 63 :: int)::ii)] :: 1 Word.word)) in + return selbit))) + else + (let (selbit :: 1 bits) = + (if tbi then (vec_of_bits [access_vec_dec ptr (( 55 :: int)::ii)] :: 1 Word.word) + else (vec_of_bits [access_vec_dec ptr (( 63 :: int)::ii)] :: 1 Word.word)) in + return selbit)) \ (\ (selbit :: 1 bits) . + CalculateBottomPACBit ptr selbit \ (\ (w__26 :: ii) . + (let (bottom_PAC_bit :: int) = (ex_int w__26) in + assert_exp True ('''') \ + ((let extfield = ((replicate_bits selbit (( 64 :: int)::ii) :: 64 Word.word)) in + (let (ext_ptr :: 64 bits) = + (if tbi then + (concat_vec ((subrange_vec_dec ptr (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + ((subrange_subrange_concat + ((((((((((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) - + (( 1 :: int)::ii))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) + + + ((bottom_PAC_bit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) + extfield + ((((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) - (( 1 :: int)::ii))) (( 0 :: int)::ii) + ptr ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 56 Word.word)) + :: 64 Word.word) + else + (subrange_subrange_concat ((int (size PAC))) extfield + ((((((- bottom_PAC_bit)) + (( 64 :: int)::ii))) - (( 1 :: int)::ii))) (( 0 :: int)::ii) ptr + ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 64 Word.word)) in + (ComputePAC ext_ptr modifier ((subrange_vec_dec K (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((subrange_vec_dec K (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: ( 64 Word.word) M) \ (\ (w__27 :: 64 bits) . + (let (PAC :: 64 bits) = w__27 in + (let (PAC :: 64 bits) = + (if (((((\ ((is_zero_subrange ptr + ((((((((top_bit - bottom_PAC_bit)) + (( 1 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) bottom_PAC_bit)))) \ ((\ ((is_ones_subrange ptr + ((((((((top_bit - bottom_PAC_bit)) + (( 1 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) bottom_PAC_bit))))))) then + (update_subrange_vec_dec PAC ((top_bit - (( 1 :: int)::ii))) ((top_bit - (( 1 :: int)::ii))) + ((not_vec (vec_of_bits [access_vec_dec PAC ((top_bit - (( 1 :: int)::ii)))] :: 1 Word.word) + :: 1 Word.word)) + :: 64 Word.word) + else PAC) in + (let (result :: 64 bits) = + (if tbi then + (concat_vec + ((concat_vec ((subrange_vec_dec ptr (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) selbit :: 9 Word.word)) + ((subrange_subrange_concat + ((((((((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) + - ((bottom_PAC_bit - (( 1 :: int)::ii))))) + + + ((bottom_PAC_bit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) PAC + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - (( 1 :: int)::ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 55 Word.word)) + :: 64 Word.word) + else + (concat_vec + ((concat_vec ((subrange_vec_dec PAC (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) selbit :: 9 Word.word)) + ((subrange_subrange_concat + ((((((((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - + (( 1 :: int)::ii))) + + bottom_PAC_bit)) + - ((bottom_PAC_bit - (( 1 :: int)::ii))))) + + + ((bottom_PAC_bit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) PAC + ((((((((- bottom_PAC_bit)) + (( 55 :: int)::ii))) - (( 1 :: int)::ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 55 Word.word)) + :: 64 Word.word)) in + return result)))))))))))))))))))" + + +(*val AArch64_vESBOperation : unit -> M unit*) + +definition AArch64_vESBOperation :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_vESBOperation _ = ( + and_boolM + (and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) = EL1)))))) \ (\ (w__5 :: + bool) . + (assert_exp w__5 (''((HaveEL(EL2) && !(IsSecure())) && (((PSTATE).EL == EL0) || ((PSTATE).EL == EL1)))'') \ + and_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (vSEI_enabled :: bool) . + and_boolM (return vSEI_enabled) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (vSEI_pending :: bool) . + or_boolM ((Halted () )) ((ExternalDebugInterruptsDisabled EL1)) \ (\ (vintdis :: bool) . + or_boolM (return vintdis) + (read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + return ((((ProcState_A w__11) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (vmasked :: bool) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (VDISR_EL2 :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (VDISR :: 32 bits) . + if (((vSEI_pending \ vmasked))) then + ELUsingAArch32 EL1 \ (\ (w__12 :: bool) . + ((if w__12 then + (read_reg VDFSR_ref :: ( 32 Word.word) M) \ (\ (w__13 :: 32 bits) . + (read_reg VDFSR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 bits) . + (AArch32_ReportDeferredSError ((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [access_vec_dec w__14 (( 12 :: int)::ii)] :: 1 Word.word) + :: ( 32 Word.word) M) \ (\ (w__15 :: 32 bits) . + (let (VDISR :: 32 bits) = w__15 in + return () )))) + else + (read_reg VSESR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__16 :: 32 bits) . + (AArch64_ReportDeferredSError ((slice0 w__16 (( 0 :: int)::ii) (( 25 :: int)::ii) :: 25 Word.word)) :: ( 64 Word.word) M) \ (\ (w__17 :: 64 + bits) . + (let (VDISR_EL2 :: 64 bits) = w__17 in + return () )))) \ + (read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__18 :: 64 Word.word) . + write_reg + HCR_EL2_ref + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))) + else return () ))))))))" + + +(*val AArch64_WatchpointByteMatch : ii -> mword ty64 -> M bool*) + +definition AArch64_WatchpointByteMatch :: " int \(64)Word.word \((register_value),(bool),(exception))monad " where + " AArch64_WatchpointByteMatch n vaddress = ( + catch_early_return + (liftR (read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + liftR (AddrTop vaddress False(ProcState_EL w__0)) \ (\ (top1 :: int) . + liftR (read_reg DBGWVR_EL1_ref) \ (\ (w__1 :: ( 64 bits) list) . + (let (bottom :: ii) = + (if ((((vec_of_bits [access_vec_dec ((access_list_dec w__1 n :: 64 Word.word)) (( 2 :: int)::ii)] + :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (( 2 :: int)::ii) + else (( 3 :: int)::ii)) in + liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__2 :: ( 32 bits) list) . + (let (byte_select_match :: bool) = + ((vec_of_bits [access_vec_dec + ((subrange_vec_dec ((access_list_dec w__2 n :: 32 Word.word)) (( 12 :: int)::ii) (( 5 :: int)::ii) + :: 8 Word.word)) + ((unsigned_subrange vaddress ((((ex_int bottom)) - (( 1 :: int)::ii))) + (( 0 :: int)::ii)))] + :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__3 :: ( 32 bits) list) . + (let (mask1 :: ii) = + (Word.uint ((subrange_vec_dec ((access_list_dec w__3 n :: 32 Word.word)) (( 28 :: int)::ii) (( 24 :: int)::ii) :: 5 Word.word))) in + liftR ((undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (MSB :: 8 bits) . + liftR ((undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (LSB :: 8 bits) . + and_boolM (return ((((ex_int mask1)) > (( 0 :: int)::ii)))) + (liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__4 :: ( 32 bits) list) . + return ((\ ((IsOnes + ((subrange_vec_dec ((access_list_dec w__4 n :: 32 Word.word)) (( 12 :: int)::ii) (( 5 :: int)::ii) + :: 8 Word.word)))))))) \ (\ (w__5 :: bool) . + (if w__5 then + liftR (ConstrainUnpredictableBool Unpredictable_WPMASKANDBAS) \ (\ (w__6 :: bool) . + (let (byte_select_match :: bool) = w__6 in + return (bottom, byte_select_match))) + else + liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__7 :: ( 32 bits) list) . + liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__8 :: ( 32 bits) list) . + (let LSB = + ((and_vec + ((subrange_vec_dec ((access_list_dec w__7 n :: 32 Word.word)) (( 12 :: int)::ii) (( 5 :: int)::ii) + :: 8 Word.word)) + ((not_vec + ((sub_vec_int + ((subrange_vec_dec ((access_list_dec w__8 n :: 32 Word.word)) (( 12 :: int)::ii) (( 5 :: int)::ii) + :: 8 Word.word)) (( 1 :: int)::ii) + :: 8 Word.word)) + :: 8 Word.word)) + :: 8 Word.word)) in + liftR (read_reg DBGWCR_EL1_ref) \ (\ (w__9 :: ( 32 bits) list) . + (let MSB = + ((add_vec + ((subrange_vec_dec ((access_list_dec w__9 n :: 32 Word.word)) (( 12 :: int)::ii) (( 5 :: int)::ii) + :: 8 Word.word)) LSB + :: 8 Word.word)) in + if ((\ ((IsZero ((and_vec MSB ((sub_vec_int MSB (( 1 :: int)::ii) :: 8 Word.word)) :: 8 Word.word)))))) + then + liftR (ConstrainUnpredictableBool Unpredictable_WPBASCONTIGUOUS) \ (\ (w__10 :: bool) . + (let (byte_select_match :: bool) = w__10 in + (let (bottom :: ii) = ((( 3 :: int)::ii)) in + return (bottom, byte_select_match)))) + else return (bottom, byte_select_match))))))) \ (\ varstup . (let ((bottom :: ii), (byte_select_match :: + bool)) = varstup in + liftR (undefined_Constraint () ) \ (\ (c :: Constraint) . + (if (((((((ex_int mask1)) > (( 0 :: int)::ii))) \ ((((ex_int mask1)) \ (( 2 :: int)::ii)))))) then + liftR (ConstrainUnpredictableInteger (( 3 :: int)::ii) (( 31 :: int)::ii) Unpredictable_RESWPMASK) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let c = tup__0 in + (let mask1 = tup__1 in + liftR (assert_exp ((((((c = Constraint_DISABLED))) \ ((((((c = Constraint_NONE))) \ (((c = Constraint_UNKNOWN))))))))) (''((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))'')) \ + (case c of + Constraint_DISABLED => (early_return False :: (unit, bool) MR) \ return mask1 + | Constraint_NONE => return (( 0 :: int)::ii) + ))))) + else return mask1) \ (\ (mask1 :: ii) . + liftR (undefined_bool () ) \ (\ (WVR_match :: bool) . + (let (mask2 :: int) = (ex_int mask1) in + (let (bottom2 :: int) = (ex_int bottom) in + (if ((((ex_int mask1)) > ((ex_int bottom)))) then + (liftR (assert_exp True ('''')) \ + liftR (read_reg DBGWVR_EL1_ref)) \ (\ (w__11 :: ( 64 bits) list) . + (let WVR_match = + (subrange_subrange_eq vaddress + ((((((((top1 - mask2)) + (( 1 :: int)::ii))) - (( 1 :: int)::ii))) + + mask2)) mask2 ((access_list_dec w__11 n :: 64 Word.word)) + ((((((((top1 - mask2)) + (( 1 :: int)::ii))) - (( 1 :: int)::ii))) + + mask2)) mask2) in + and_boolM (return WVR_match) + (liftR (read_reg DBGWVR_EL1_ref) \ (\ (w__12 :: ( 64 bits) list) . + return ((\ ((is_zero_subrange ((access_list_dec w__12 n :: 64 Word.word)) + ((((((mask2 - bottom2)) - (( 1 :: int)::ii))) + + bottom2)) bottom2)))))) \ (\ (w__13 :: bool) . + if w__13 then liftR (ConstrainUnpredictableBool Unpredictable_WPMASKEDBITS) + else return WVR_match))) + else + liftR (read_reg DBGWVR_EL1_ref) \ (\ (w__15 :: ( 64 bits) list) . + (let (WVR_match :: bool) = + (subrange_subrange_eq vaddress + ((((((((top1 - bottom2)) + (( 1 :: int)::ii))) - (( 1 :: int)::ii))) + + bottom2)) bottom2 ((access_list_dec w__15 n :: 64 Word.word)) + ((((((((top1 - bottom2)) + (( 1 :: int)::ii))) - (( 1 :: int)::ii))) + + bottom2)) bottom2) in + return WVR_match))) \ (\ (WVR_match :: bool) . + return (((WVR_match \ byte_select_match))))))))))))))))))))))))" + + +(*val IsOnes_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +definition IsOnes_slice :: "('n::len)Word.word \ int \ int \((register_value),(bool),(exception))monad " where + " IsOnes_slice xs i l = ( + assert_exp True ('''') \ + ((let (m :: 'n bits) = ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) in + return (((((and_vec xs m :: ( 'n::len)Word.word)) = m))))))" + + +(*val AArch64_TranslationTableWalk : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> M TLBRecord*) + +definition AArch64_TranslationTableWalk :: "(52)Word.word \(64)Word.word \ AccType \ bool \ bool \ bool \ int \((register_value),(TLBRecord),(exception))monad " where + " AArch64_TranslationTableWalk ipaddress vaddress acctype iswrite secondstage s2fs1walk size1 = ( + catch_early_return + (((if ((\ secondstage)) then + liftR ((S1TranslationRegime__1 () :: ( 2 Word.word) M)) \ (\ (w__0 :: 2 Word.word) . + liftR (ELUsingAArch32 w__0) \ (\ (w__1 :: bool) . liftR (assert_exp ((\ w__1)) ('''')))) + else + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (liftR (IsSecure () ) \ (\ (w__2 :: bool) . return ((\ w__2))))) + (liftR (ELUsingAArch32 EL2) \ (\ (w__4 :: bool) . return ((\ w__4))))) + (liftR ((HasS2Translation () ))) \ (\ (w__7 :: bool) . + liftR (assert_exp w__7 ('''')))) \ + liftR (undefined_TLBRecord () )) \ (\ (result :: TLBRecord) . + liftR (undefined_AddressDescriptor () ) \ (\ (descaddr :: AddressDescriptor) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (baseregister :: 64 bits) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (inputaddr :: 64 bits) . + (let (tmp_180 :: MemoryAttributes) = ((AddressDescriptor_memattrs descaddr)) in + (let tmp_180 = ((tmp_180 (| MemoryAttributes_typ := MemType_Normal |))) in + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := tmp_180 |))) in + liftR (undefined_int () ) \ (\ (startsizecheck :: ii) . + liftR (undefined_int () ) \ (\ (inputsizecheck :: ii) . + liftR (undefined_int () ) \ (\ (startlevel :: ii) . + liftR (undefined_int () ) \ (\ (level :: ii) . + liftR (undefined_int () ) \ (\ (stride :: ii) . + liftR (undefined_int () ) \ (\ (firstblocklevel :: ii) . + liftR (undefined_int () ) \ (\ (grainsize :: ii) . + liftR (undefined_bool () ) \ (\ (hierattrsdisabled :: bool) . + liftR (undefined_bool () ) \ (\ (update_AP :: bool) . + liftR (undefined_bool () ) \ (\ (update_AF :: bool) . + liftR (undefined_bool () ) \ (\ (singlepriv :: bool) . + liftR (undefined_bool () ) \ (\ (lookupsecure :: bool) . + liftR (undefined_bool () ) \ (\ (reversedescriptors :: bool) . + liftR (undefined_bool () ) \ (\ (disabled :: bool) . + liftR (undefined_bool () ) \ (\ (basefound :: bool) . + liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \ (\ (ps :: 3 bits) . + liftR (undefined_int () ) \ (\ (inputsize_min :: ii) . + liftR (undefined_Constraint () ) \ (\ (c :: Constraint) . + liftR (undefined_int () ) \ (\ (inputsize_max :: ii) . + liftR (undefined_int () ) \ (\ (inputsize :: ii) . + liftR (undefined_bool () ) \ (\ (midgrain :: bool) . + liftR (undefined_bool () ) \ (\ (largegrain :: bool) . + liftR (undefined_int () ) \ (\ (top1 :: ii) . + (if ((\ secondstage)) then + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \ (\ (w__8 :: 64 bits) . + (let inputaddr = w__8 in + liftR (read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + liftR (AddrTop inputaddr (((acctype = AccType_IFETCH)))(ProcState_EL w__9)) \ (\ (w__10 :: + ii) . + (let top1 = w__10 in + liftR (read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + (if ((((ProcState_EL w__11) = EL3))) then + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__12 :: 32 bits) . + (let largegrain = + (((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__13 :: 32 bits) . + (let midgrain = + (((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__14 :: 32 bits) . + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__14 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__15 :: 32 bits) . + (let ps = ((slice0 w__15 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + (( 1 :: int)::ii)))))) \ (\ (w__17 :: + bool) . + (let basefound = w__17 in + (let disabled = False in + liftR ((read_reg TTBR0_EL3_ref :: ( 64 Word.word) M)) \ (\ (w__18 :: 64 bits) . + (let baseregister = w__18 in + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__19 :: 32 bits) . + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__20 :: 32 bits) . + liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__21 :: 32 bits) . + liftR (WalkAttrDecode ((slice0 w__19 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__20 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__21 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__22 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__22 |))) in + liftR ((read_reg SCTLR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__23 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__23 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let lookupsecure = True in + (let singlepriv = True in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__24 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__24 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__25 :: bool) . + (let update_AF = w__25 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__26 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__26 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__27 :: bool) . + (let update_AP = w__27 in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__28 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__28 (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__29 :: bool) . + (let (hierattrsdisabled :: bool) = w__29 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP)))))))))))))))))))))))))))))))))) + else + liftR (IsInHost () ) \ (\ (w__30 :: bool) . + if w__30 then + (if ((((vec_of_bits [access_vec_dec inputaddr top1] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__31 :: 64 bits) . + (let largegrain = + (((slice0 w__31 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__32 :: 64 bits) . + (let midgrain = + (((slice0 w__32 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__33 :: 64 bits) . + (let inputsize = + ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__33 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: + ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + + (( 1 :: int)::ii)))))) \ (\ (w__35 :: bool) . + (let basefound = w__35 in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__36 :: 64 bits) . + (let disabled = + ((vec_of_bits [access_vec_dec w__36 (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR ((read_reg TTBR0_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__37 :: 64 bits) . + (let baseregister = w__37 in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__38 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__39 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__40 :: 64 bits) . + liftR (WalkAttrDecode ((slice0 w__38 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__39 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__40 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__41 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__41 |))) in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__42 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__42 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__43 :: bool) . + (let (hierattrsdisabled :: bool) = w__43 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain))))))))))))))))))))))))) + else + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__44 :: 64 bits) . + (let inputsize = + ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__44 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__45 :: 64 bits) . + (let largegrain = + (((slice0 w__45 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__46 :: 64 bits) . + (let midgrain = + (((slice0 w__46 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: + ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsOnes_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + + (( 1 :: int)::ii)))))) \ (\ (w__48 :: bool) . + (let basefound = w__48 in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__49 :: 64 bits) . + (let disabled = + ((vec_of_bits [access_vec_dec w__49 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR ((read_reg TTBR1_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__50 :: 64 bits) . + (let baseregister = w__50 in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__51 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__52 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__53 :: 64 bits) . + liftR (WalkAttrDecode ((slice0 w__51 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__52 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__53 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__54 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__54 |))) in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__55 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__55 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__56 :: bool) . + (let (hierattrsdisabled :: bool) = w__56 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain)))))))))))))))))))))))))) \ (\ varstup . (let ((basefound :: bool), (baseregister :: 64 + bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled :: + bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__57 :: 64 bits) . + (let ps = ((slice0 w__57 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__58 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__58 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let lookupsecure = False in + (let singlepriv = False in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__59 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__59 (( 39 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__60 :: bool) . + (let update_AF = w__60 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__61 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__61 (( 40 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__62 :: bool) . + (let (update_AP :: bool) = w__62 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP))))))))))))) + else + liftR (read_reg PSTATE_ref) \ (\ (w__63 :: ProcState) . + if ((((ProcState_EL w__63) = EL2))) then + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__64 :: 64 bits) . + (let inputsize = + ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__64 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__65 :: 64 bits) . + (let largegrain = + (((slice0 w__65 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__66 :: 64 bits) . + (let midgrain = + (((slice0 w__66 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: + ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__67 :: 64 bits) . + (let ps = ((slice0 w__67 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + + (( 1 :: int)::ii)))))) \ (\ (w__69 :: bool) . + (let basefound = w__69 in + (let disabled = False in + liftR ((read_reg TTBR0_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__70 :: 64 bits) . + (let baseregister = w__70 in + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__71 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__72 :: 64 bits) . + liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__73 :: 64 bits) . + liftR (WalkAttrDecode ((slice0 w__71 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__72 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__73 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__74 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__74 |))) in + liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__75 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__75 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let lookupsecure = False in + (let singlepriv = True in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__76 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__76 (( 39 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__77 :: bool) . + (let update_AF = w__77 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__78 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__78 (( 40 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__79 :: bool) . + (let update_AP = w__79 in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__80 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__80 (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__81 :: bool) . + (let (hierattrsdisabled :: bool) = w__81 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP)))))))))))))))))))))))))))))))))) + else + (if ((((vec_of_bits [access_vec_dec inputaddr top1] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__82 :: 64 bits) . + (let inputsize = + ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__82 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__83 :: 64 bits) . + (let largegrain = + (((slice0 w__83 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__84 :: 64 bits) . + (let midgrain = + (((slice0 w__84 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: + ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + + (( 1 :: int)::ii)))))) \ (\ (w__86 :: bool) . + (let basefound = w__86 in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__87 :: 64 bits) . + (let disabled = + ((vec_of_bits [access_vec_dec w__87 (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR ((read_reg TTBR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__88 :: 64 bits) . + (let baseregister = w__88 in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__89 :: 64 bits) . + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__90 :: 64 bits) . + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__91 :: 64 bits) . + liftR (WalkAttrDecode ((slice0 w__89 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__90 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__91 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__92 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__92 |))) in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__93 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__93 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__94 :: bool) . + (let (hierattrsdisabled :: bool) = w__94 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain))))))))))))))))))))))))) + else + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__95 :: 64 bits) . + (let inputsize = + ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__95 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__96 :: 64 bits) . + (let largegrain = + (((slice0 w__96 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__97 :: 64 bits) . + (let midgrain = + (((slice0 w__97 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: + ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsOnes_slice inputaddr inputsize + ((((((ex_int top1)) - ((ex_int inputsize)))) + + (( 1 :: int)::ii)))))) \ (\ (w__99 :: bool) . + (let basefound = w__99 in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__100 :: 64 bits) . + (let disabled = + ((vec_of_bits [access_vec_dec w__100 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR ((read_reg TTBR1_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__101 :: 64 bits) . + (let baseregister = w__101 in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__102 :: 64 bits) . + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__103 :: 64 bits) . + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__104 :: 64 bits) . + liftR (WalkAttrDecode ((slice0 w__102 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__103 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__104 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__105 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__105 |))) in + and_boolM (return ((AArch64_HaveHPDExt () ))) + (liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__106 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__106 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__107 :: bool) . + (let (hierattrsdisabled :: bool) = w__107 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain)))))))))))))))))))))))))) \ (\ varstup . (let ((basefound :: bool), (baseregister :: 64 + bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled :: + bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in + liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__108 :: 64 bits) . + (let ps = ((slice0 w__108 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + liftR ((read_reg SCTLR_EL1_ref :: ( 32 Word.word) M)) \ (\ (w__109 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__109 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR (IsSecure () ) \ (\ (w__110 :: bool) . + (let lookupsecure = w__110 in + (let singlepriv = False in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__111 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__111 (( 39 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__112 :: bool) . + (let update_AF = w__112 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__113 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__113 (( 40 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__114 :: bool) . + (let (update_AP :: bool) = w__114 in + return (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP))))))))))))))))) \ (\ varstup . (let ((basefound :: bool), (baseregister :: 64 + bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled :: bool), (inputsize :: + ii), (largegrain :: bool), (lookupsecure :: bool), (midgrain :: bool), (ps :: 3 bits), (reversedescriptors :: + bool), (singlepriv :: bool), (update_AF :: bool), (update_AP :: bool)) = varstup in + (let ((firstblocklevel :: ii), (grainsize :: ii)) = + (if largegrain then + (let (grainsize :: ii) = ((( 16 :: int)::ii)) in + (let (firstblocklevel :: ii) = (if ((Have52BitPAExt () )) then (( 1 :: int)::ii) else (( 2 :: int)::ii)) in + (firstblocklevel, grainsize))) + else + (let ((firstblocklevel :: ii), (grainsize :: ii)) = + (if midgrain then + (let (grainsize :: ii) = ((( 14 :: int)::ii)) in + (let (firstblocklevel :: ii) = ((( 2 :: int)::ii)) in + (firstblocklevel, grainsize))) + else + (let (grainsize :: ii) = ((( 12 :: int)::ii)) in + (let (firstblocklevel :: ii) = ((( 1 :: int)::ii)) in + (firstblocklevel, grainsize)))) in + (firstblocklevel, grainsize))) in + (let (stride :: ii) = (((ex_int grainsize)) - (( 3 :: int)::ii)) in + (let (level :: ii) = + ((( 4 :: int)::ii) - + ((ex_int + ((ceiling + (((((real_of_int ((((ex_int inputsize)) - ((ex_int grainsize))))))) + div + (((real_of_int stride)))))))))) in + return (basefound, + baseregister, + descaddr, + disabled, + firstblocklevel, + grainsize, + hierattrsdisabled, + inputaddr, + inputsize, + largegrain, + level, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + stride, + update_AF, + update_AP)))))))))))) + else + liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \ (\ (w__115 :: 64 bits) . + (let inputaddr = w__115 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__116 :: 32 bits) . + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__116 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__117 :: 32 bits) . + (let largegrain = + (((slice0 w__117 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__118 :: 32 bits) . + (let midgrain = + (((slice0 w__118 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (let inputsize_max = + (if (((((Have52BitVAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii)) in + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + return (c, inputsize)))) + else return (c, inputsize)) \ (\ varstup . (let ((c :: Constraint), (inputsize :: ii)) = varstup in + (let inputsize_min = ((( 64 :: int)::ii) - (( 39 :: int)::ii)) in + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in + liftR (assert_exp ((((((c = Constraint_FORCE))) \ (((c = Constraint_FAULT)))))) ('''')) \ + ((let (inputsize :: ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + return inputsize))) + else return inputsize) \ (\ (inputsize :: ii) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__119 :: 32 bits) . + (let ps = ((slice0 w__119 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + and_boolM + (return (((((((ex_int inputsize)) \ ((ex_int inputsize_min)))) \ ((((ex_int inputsize)) \ ((ex_int inputsize_max)))))))) + (liftR ((IsZero_slice inputaddr inputsize + ((((- ((ex_int inputsize)))) + (( 64 :: int)::ii)))))) \ (\ (w__121 :: + bool) . + (let basefound = w__121 in + (let disabled = False in + liftR ((read_reg VTTBR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__122 :: 64 bits) . + (let baseregister = w__122 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__123 :: 32 bits) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__124 :: 32 bits) . + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__125 :: 32 bits) . + liftR (WalkAttrDecode ((slice0 w__123 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__124 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice0 w__125 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \ (\ (w__126 :: + MemoryAttributes) . + (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__126 |))) in + liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__127 :: 32 bits) . + (let reversedescriptors = + ((vec_of_bits [access_vec_dec w__127 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let lookupsecure = False in + (let singlepriv = True in + and_boolM (return ((HaveAccessFlagUpdateExt () ))) + (liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__128 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__128 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__129 :: bool) . + (let update_AF = w__129 in + and_boolM (return (((((HaveDirtyBitModifierExt () )) \ update_AF)))) + (liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__130 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__130 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__131 :: bool) . + (let update_AP = w__131 in + liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \ (\ (w__132 :: 32 bits) . + (let startlevel = (Word.uint ((slice0 w__132 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = + (if largegrain then + (let (grainsize :: ii) = ((( 16 :: int)::ii)) in + (let (level :: ii) = ((( 3 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = (if ((Have52BitPAExt () )) then (( 1 :: int)::ii) else (( 2 :: int)::ii)) in + (firstblocklevel, grainsize, level)))) + else + (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = + (if midgrain then + (let (grainsize :: ii) = ((( 14 :: int)::ii)) in + (let (level :: ii) = ((( 3 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = ((( 2 :: int)::ii)) in + (firstblocklevel, grainsize, level)))) + else + (let (grainsize :: ii) = ((( 12 :: int)::ii)) in + (let (level :: ii) = ((( 2 :: int)::ii) - ((ex_int startlevel))) in + (let (firstblocklevel :: ii) = ((( 1 :: int)::ii)) in + (firstblocklevel, grainsize, level))))) in + (firstblocklevel, grainsize, level))) in + (let stride = (((ex_int grainsize)) - (( 3 :: int)::ii)) in + (let (basefound :: bool) = + (if largegrain then + if ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 42 :: int)::ii))))))))) then + False + else basefound + else if midgrain then + if ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 40 :: int)::ii))))))))) then + False + else basefound + else if (((((((ex_int level)) < (( 0 :: int)::ii))) \ ((((((((ex_int level)) = (( 0 :: int)::ii)))) \ ((((ex_int ((PAMax () )))) \ (( 42 :: int)::ii))))))))) then + False + else basefound) in + (let inputsizecheck = inputsize in + and_boolM (return ((((ex_int inputsize)) > ((ex_int ((PAMax () ))))))) + (or_boolM (liftR (ELUsingAArch32 EL1) \ (\ (w__133 :: bool) . return ((\ w__133)))) + (return ((((ex_int inputsize)) > (( 40 :: int)::ii))))) \ (\ (w__135 :: bool) . + (if w__135 then + (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of + Constraint_FORCE => + (let (inputsize :: ii) = (PAMax () ) in + (let (inputsizecheck :: ii) = (PAMax () ) in + return (basefound, inputsize, inputsizecheck))) + | Constraint_FORCENOSLCHECK => + (let (inputsize :: ii) = (PAMax () ) in + return (basefound, inputsize, inputsizecheck)) + | Constraint_FAULT => + (let (basefound :: bool) = False in + return (basefound, inputsize, inputsizecheck)) + | _ => liftR (Unreachable () ) \ return (basefound, inputsize, inputsizecheck) + ) + else return (basefound, inputsize, inputsizecheck)) \ (\ varstup . (let ((basefound :: + bool), (inputsize :: ii), (inputsizecheck :: ii)) = varstup in + (let (startsizecheck :: ii) = + (((ex_int inputsizecheck)) - + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + ((ex_int grainsize))))) in + (let (basefound :: bool) = + (if (((((((ex_int startsizecheck)) < (( 1 :: int)::ii))) \ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 :: int)::ii)))))))) then + False + else basefound) in + return (basefound, + baseregister, + descaddr, + disabled, + firstblocklevel, + grainsize, + hierattrsdisabled, + inputaddr, + inputsize, + largegrain, + level, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + stride, + update_AF, + update_AP)))))))))))))))))))))))))))))))))))))))))))))) \ (\ varstup . (let ((basefound :: bool), (baseregister :: 64 bits), (descaddr :: + AddressDescriptor), (disabled :: bool), (firstblocklevel :: ii), (grainsize :: ii), (hierattrsdisabled :: + bool), (inputaddr :: 64 bits), (inputsize :: ii), (largegrain :: bool), (level :: ii), (lookupsecure :: + bool), (midgrain :: bool), (ps :: 3 bits), (reversedescriptors :: bool), (singlepriv :: bool), (stride :: + ii), (update_AF :: bool), (update_AP :: bool)) = varstup in + if (((((\ basefound)) \ disabled))) then + (let level = ((( 0 :: int)::ii)) in + (let (tmp_190 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk) \ (\ (w__136 :: + FaultRecord) . + (let (tmp_190 :: AddressDescriptor) = ((tmp_190 (| AddressDescriptor_fault := w__136 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_190 |))) in + return result))))) + else + liftR (undefined_int () ) \ (\ (outputsize :: ii) . + (let b__0 = ps in + (let (outputsize :: ii) = + (if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then (( 36 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then (( 40 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then (( 42 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then (( 44 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then (( 48 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + if (((((Have52BitPAExt () )) \ largegrain))) then (( 52 :: int)::ii) + else (( 48 :: int)::ii) + else (( 48 :: int)::ii)) in + (let (outputsize :: ii) = + (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () + else outputsize) in + and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice baseregister outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__137 :: + bool) . + return ((\ w__137)))) \ (\ (w__138 :: bool) . + if w__138 then + (let level = ((( 0 :: int)::ii)) in + (let (tmp_200 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk) \ (\ (w__139 :: + FaultRecord) . + (let (tmp_200 :: AddressDescriptor) = ((tmp_200 (| AddressDescriptor_fault := w__139 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_200 |))) in + return result))))) + else + (let baselowerbound = + ((((( 3 :: int)::ii) + ((ex_int inputsize)))) - + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))) in + (liftR (assert_exp True ('''')) \ + liftR ((undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M))) \ (\ (baseaddress :: 52 bits) . + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in + liftR (assert_exp True ('''')) \ + ((let (baseaddress :: 52 bits) = + ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z)) + baseregister z ((((- z)) + (( 48 :: int)::ii))) z + :: 48 Word.word)) + :: 52 Word.word)) in + return baseaddress))) + else + (let (baseaddress :: 52 bits) = + ((place_slice (( 52 :: int)::ii) baseregister baselowerbound + ((((- baselowerbound)) + (( 48 :: int)::ii))) baselowerbound + :: 52 Word.word)) in + return baseaddress)) \ (\ (baseaddress :: 52 bits) . + (let (ns_table :: 1 bits) = + (if lookupsecure then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + (let (ap_table :: 2 bits) = ((vec_of_bits [B0,B0] :: 2 Word.word)) in + (let (xn_table :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (pxn_table :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (let (addrselecttop :: ii) = (((ex_int inputsize)) - (( 1 :: int)::ii)) in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + (liftR ((read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__140 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__140 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (liftR ((read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \ (\ (w__142 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__142 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (apply_nvnv1_effect :: bool) . + liftR (undefined_bool () ) \ (\ (blocktranslate :: bool) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (desc :: 64 bits) . + liftR (undefined_AccessDescriptor () ) \ (\ (accdesc :: AccessDescriptor) . + liftR (undefined_bool () ) \ (\ (hwupdatewalk :: bool) . + liftR (undefined_AddressDescriptor () ) \ (\ (descaddr2 :: AddressDescriptor) . + liftR (undefined_int () ) \ (\ (addrselectbottom :: ii) . + (untilM (addrselectbottom, + ap_table, + desc, + descaddr, + level, + ns_table, + pxn_table, + result, + xn_table) + (\ varstup . + (let (addrselectbottom, + ap_table, + desc, + descaddr, + level, + ns_table, + pxn_table, + result, + xn_table) = varstup in + return blocktranslate)) + (\ varstup . + (let (addrselectbottom, + ap_table, + desc, + descaddr, + level, + ns_table, + pxn_table, + result, + xn_table) = varstup in + (let addrselectbottom = + ((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))) in + liftR ((ZeroExtend_slice_append (( 52 :: int)::ii) inputaddr addrselectbottom + ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom)))) + + + (( 1 :: int)::ii))) (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: ( 52 Word.word) M)) \ (\ (index1 :: 52 bits) . + (let (tmp_210 :: FullAddress) = ((AddressDescriptor_paddress descaddr)) in + (let tmp_210 = + ((tmp_210 (| + FullAddress_physicaladdress := ((or_vec baseaddress index1 :: 52 Word.word))|))) in + (let descaddr = ((descaddr (| AddressDescriptor_paddress := tmp_210 |))) in + (let (tmp_220 :: FullAddress) = ((AddressDescriptor_paddress descaddr)) in + (let tmp_220 = ((tmp_220 (| FullAddress_NS := ns_table |))) in + (let descaddr = ((descaddr (| AddressDescriptor_paddress := tmp_220 |))) in + or_boolM (return secondstage) + (liftR (HasS2Translation () ) \ (\ (w__143 :: bool) . return ((\ w__143)))) \ (\ (w__144 :: + bool) . + (if w__144 then + (let (descaddr2 :: AddressDescriptor) = descaddr in + return (descaddr2, result)) + else + (let hwupdatewalk = False in + liftR (AArch64_SecondStageWalk descaddr vaddress acctype iswrite (( 8 :: int)::ii) + hwupdatewalk) \ (\ (w__145 :: AddressDescriptor) . + (let descaddr2 = w__145 in + (if ((IsFault descaddr2)) then + (let (tmp_230 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_230 = + ((tmp_230 (| AddressDescriptor_fault := ((AddressDescriptor_fault descaddr2))|))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_230 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return result))) + else return result) \ (\ (result :: TLBRecord) . + return (descaddr2, result)))))) \ (\ varstup . (let ((descaddr2 :: AddressDescriptor), (result :: + TLBRecord)) = varstup in + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \ (\ (w__146 :: 64 bits) . + (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__146 |))) in + liftR (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level) \ (\ (w__147 :: + AccessDescriptor) . + (let accdesc = w__147 in + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \ (\ (w__148 :: 64 + bits) . + (let desc = w__148 in + (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) + else return desc) \ (\ (desc :: 64 bits) . + (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((ex_int level)) = (( 3 :: int)::ii)))))))))) + then + (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage + s2fs1walk) \ (\ (w__150 :: FaultRecord) . + (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__150 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in + (early_return result :: (unit, TLBRecord) MR) \ + return (ap_table, level, ns_table, pxn_table, result, xn_table))))) + else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((ex_int level)) = (( 3 :: int)::ii))))))) + then + (let (blocktranslate :: bool) = True in + return (ap_table, level, ns_table, pxn_table, result, xn_table)) + else + or_boolM + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \ largegrain))) \ ((\ ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice desc outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__151 :: + bool) . + return ((\ w__151))))) \ (\ (w__153 :: bool) . + if w__153 then + (let (tmp_250 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage + s2fs1walk) \ (\ (w__154 :: FaultRecord) . + (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__154 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in + (early_return result :: (unit, TLBRecord) MR) \ + return (ap_table, level, ns_table, pxn_table, result, xn_table))))) + else + (let gsz = grainsize in + liftR (assert_exp True ('''')) \ + ((let (_ :: unit) = + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (let (baseaddress :: 52 bits) = + ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat + ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc + gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz + :: 48 Word.word)) + :: 52 Word.word)) in + () ) + else + (let (baseaddress :: 52 bits) = + ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) + gsz + :: 52 Word.word)) in + () )) in + (let (ns_table :: 1 bits) = + (if ((\ secondstage)) then + (or_vec ns_table (vec_of_bits [access_vec_dec desc (( 63 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word) + else ns_table) in + (let ((ap_table :: 2 bits), (pxn_table :: 1 bits), (xn_table :: 1 bits)) = + (if (((((\ secondstage)) \ ((\ hierattrsdisabled))))) then + (let (ap_table :: 2 bits) = + ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 1 :: int)::ii) + ((or_vec (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec desc (( 62 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 2 Word.word)) in + (let ((pxn_table :: 1 bits), (xn_table :: 1 bits)) = + (if apply_nvnv1_effect then + (let (pxn_table :: 1 bits) = + ((or_vec pxn_table + (vec_of_bits [access_vec_dec desc (( 60 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) in + (pxn_table, xn_table)) + else + (let (xn_table :: 1 bits) = + ((or_vec xn_table + (vec_of_bits [access_vec_dec desc (( 60 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) in + (pxn_table, xn_table))) in + (let ((ap_table :: 2 bits), (pxn_table :: 1 bits)) = + (if ((\ singlepriv)) then + (let ((ap_table :: 2 bits), (pxn_table :: 1 bits)) = + (if ((\ apply_nvnv1_effect)) then + (let (pxn_table :: 1 bits) = + ((or_vec pxn_table + (vec_of_bits [access_vec_dec desc (( 59 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) in + (let (ap_table :: 2 bits) = + ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 0 :: int)::ii) + ((or_vec + (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec desc (( 61 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 2 Word.word)) in + (ap_table, pxn_table))) + else (ap_table, pxn_table)) in + (ap_table, pxn_table)) + else (ap_table, pxn_table)) in + (ap_table, pxn_table, xn_table)))) + else (ap_table, pxn_table, xn_table)) in + (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in + (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in + (let (blocktranslate :: bool) = False in + return (ap_table, level, ns_table, pxn_table, result, xn_table))))))))))) \ (\ varstup . (let ((ap_table :: 2 + bits), (level :: ii), (ns_table :: 1 bits), (pxn_table :: 1 bits), (result :: + TLBRecord), (xn_table :: 1 bits)) = varstup in + return (addrselectbottom, + ap_table, + desc, + descaddr, + level, + ns_table, + pxn_table, + result, + xn_table)))))))))))))))))))))))) \ (\ varstup . (let ((addrselectbottom :: ii), (ap_table :: 2 + bits), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (ns_table :: 1 + bits), (pxn_table :: 1 bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in + if ((((ex_int level)) < ((ex_int firstblocklevel)))) then + (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk) \ (\ (w__155 :: + FaultRecord) . + (let (tmp_260 :: AddressDescriptor) = ((tmp_260 (| AddressDescriptor_fault := w__155 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_260 |))) in + return result)))) + else + liftR (undefined_bool () ) \ (\ (contiguousbitcheck :: bool) . + (let (contiguousbitcheck :: bool) = + (if largegrain then + ((((((ex_int level)) = (( 2 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 34 :: int)::ii)))) + else if midgrain then + ((((((ex_int level)) = (( 2 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 30 :: int)::ii)))) + else ((((((ex_int level)) = (( 1 :: int)::ii)))) \ ((((ex_int inputsize)) < (( 34 :: int)::ii))))) in + (if (((contiguousbitcheck \ ((((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + liftR (undefined_bool () ) \ (\ (w__156 :: bool) . + if w__156 then + (let (tmp_270 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage + s2fs1walk) \ (\ (w__157 :: FaultRecord) . + (let tmp_270 = ((tmp_270 (| AddressDescriptor_fault := w__157 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_270 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return result)))) + else return result) + else return result) \ (\ (result :: TLBRecord) . + or_boolM + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \ largegrain))) \ ((\ ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) + (liftR (IsZero_slice desc outputsize + ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \ (\ (w__158 :: + bool) . + return ((\ w__158))))) \ (\ (w__160 :: bool) . + if w__160 then + (let (tmp_280 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk) \ (\ (w__161 :: + FaultRecord) . + (let (tmp_280 :: AddressDescriptor) = + ((tmp_280 (| AddressDescriptor_fault := w__161 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_280 |))) in + return result)))) + else + liftR ((undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \ (\ (outputaddress :: 52 + bits) . + (let asb = addrselectbottom in + liftR (assert_exp True ('''')) \ + ((let (outputaddress :: 52 bits) = + (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then + (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_slice_concat (( 48 :: int)::ii) desc asb + ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb + :: 48 Word.word)) + :: 52 Word.word) + else + (slice_slice_concat (( 52 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii))) + inputaddr (( 0 :: int)::ii) asb + :: 52 Word.word)) in + (if ((((vec_of_bits [access_vec_dec desc (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + if ((\ update_AF)) then + (let (tmp_290 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_AccessFlagFault ipaddress level acctype iswrite secondstage + s2fs1walk) \ (\ (w__162 :: FaultRecord) . + (let tmp_290 = ((tmp_290 (| AddressDescriptor_fault := w__162 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_290 |))) in + (early_return result :: (unit, TLBRecord) MR) \ return result)))) + else + (let (tmp_300 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let (tmp_300 :: DescriptorUpdate) = ((tmp_300 (| DescriptorUpdate_AF := True |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_descupdate := tmp_300 |))) in + return result))) + else return result) \ (\ (result :: TLBRecord) . + (let ((desc :: 64 bits), (result :: TLBRecord)) = + (if (((update_AP \ ((((vec_of_bits [access_vec_dec desc (( 51 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let ((desc :: 64 bits), (result :: TLBRecord)) = + (if (((((\ secondstage)) \ ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let (desc :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) + :: 64 Word.word)) in + (let (tmp_310 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let (tmp_310 :: DescriptorUpdate) = + ((tmp_310 (| DescriptorUpdate_AP := True |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_descupdate := tmp_310 |))) in + (desc, result))))) + else + (let ((desc :: 64 bits), (result :: TLBRecord)) = + (if (((secondstage \ ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (desc :: 64 bits) = + ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 64 Word.word)) in + (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let (tmp_320 :: DescriptorUpdate) = + ((tmp_320 (| DescriptorUpdate_AP := True |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_descupdate := tmp_320 |))) in + (desc, result))))) + else (desc, result)) in + (desc, result))) in + (desc, result)) + else (desc, result)) in + (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in + (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in + liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (xn :: 1 bits) . + liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (pxn :: 1 bits) . + (let ((pxn :: 1 bits), (xn :: 1 bits)) = + (if apply_nvnv1_effect then + (let (pxn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 :: int)::ii)] :: 1 Word.word)) in + (let (xn :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (pxn, xn))) + else + (let (xn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 :: int)::ii)] :: 1 Word.word)) in + (let (pxn :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 :: int)::ii)] :: 1 Word.word)) in + (pxn, xn)))) in + (let (contiguousbit :: 1 bits) = + ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word)) in + (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)] :: 1 Word.word)) in + (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \ (\ (ap :: 3 bits) . + (let (ap :: 3 bits) = + (if apply_nvnv1_effect then + (concat_vec (vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 3 Word.word) + else + (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \ (\ (w__163 :: 4 bits) . + (let result = ((result (| TLBRecord_domain := w__163 |))) in + (let result = ((result (| TLBRecord_level := level |))) in + (let result = + ((result (| + TLBRecord_blocksize := + ((pow2 + (((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))))|))) in + (if ((\ secondstage)) then + (let (tmp_340 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_340 = + ((tmp_340 (| Permissions_xn := ((or_vec xn xn_table :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_340 |))) in + (let (tmp_350 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_350 = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_350 (( 2 :: int)::ii) + ((or_vec (vec_of_bits [access_vec_dec ap (( 2 :: int)::ii)] :: 1 Word.word) + (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 3 Word.word)) in + (let (tmp_360 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_360 = ((tmp_360 (| Permissions_ap := tmp_350 |))) in + (let result = ((result (| TLBRecord_perms := tmp_360 |))) in + (if ((\ singlepriv)) then + (let (tmp_370 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_370 = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_370 (( 1 :: int)::ii) + ((and_vec (vec_of_bits [access_vec_dec ap (( 1 :: int)::ii)] :: 1 Word.word) + ((not_vec (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)] :: 1 Word.word) + :: 1 Word.word)) + :: 1 Word.word)) + :: 3 Word.word)) in + (let (tmp_380 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_380 = ((tmp_380 (| Permissions_ap := tmp_370 |))) in + (let result = ((result (| TLBRecord_perms := tmp_380 |))) in + (let (tmp_390 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_390 = + ((tmp_390 (| Permissions_pxn := ((or_vec pxn pxn_table :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_390 |))) in + liftR (IsSecure () ) \ (\ (w__164 :: bool) . + (let (result :: TLBRecord) = + (if w__164 then + (result (| TLBRecord_nG := ((or_vec nG ns_table :: 1 Word.word))|)) + else (result (| TLBRecord_nG := nG |))) in + return result)))))))))) + else + (let (tmp_400 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let (tmp_400 :: 3 bits) = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_400 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (tmp_410 :: Permissions) = ((TLBRecord_perms result)) in + (let (tmp_410 :: Permissions) = ((tmp_410 (| Permissions_ap := tmp_400 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_perms := tmp_410 |))) in + (let (tmp_420 :: Permissions) = ((TLBRecord_perms result)) in + (let (tmp_420 :: Permissions) = + ((tmp_420 (| Permissions_pxn := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_perms := tmp_420 |))) in + (let (result :: TLBRecord) = + ((result (| TLBRecord_nG := ((vec_of_bits [B0] :: 1 Word.word))|))) in + return result)))))))))) \ (\ (result :: TLBRecord) . + (let (tmp_430 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_430 = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_430 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (tmp_440 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_440 = ((tmp_440 (| Permissions_ap := tmp_430 |))) in + (let result = ((result (| TLBRecord_perms := tmp_440 |))) in + (let (tmp_450 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_S1AttrDecode sh ((slice0 memattr (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) acctype) \ (\ (w__165 :: + MemoryAttributes) . + (let (tmp_450 :: AddressDescriptor) = + ((tmp_450 (| AddressDescriptor_memattrs := w__165 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_450 |))) in + (let (tmp_460 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let (tmp_460 :: FullAddress) = + ((tmp_460 (| + FullAddress_NS := + ((or_vec (vec_of_bits [access_vec_dec memattr (( 3 :: int)::ii)] :: 1 Word.word) ns_table + :: 1 Word.word))|))) in + (let (tmp_470 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_470 :: AddressDescriptor) = + ((tmp_470 (| AddressDescriptor_paddress := tmp_460 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_470 |))) in + return result))))))))))))))))))))))) + else + (let (tmp_480 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_480 = + ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + :: 3 Word.word)) in + (let (tmp_490 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in + (let result = ((result (| TLBRecord_perms := tmp_490 |))) in + (let (tmp_500 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in + (let tmp_500 = + ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word)) in + (let (tmp_510 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in + (let result = ((result (| TLBRecord_perms := tmp_510 |))) in + (let (tmp_520 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_520 = ((tmp_520 (| Permissions_xn := xn |))) in + (let result = ((result (| TLBRecord_perms := tmp_520 |))) in + (let (result :: TLBRecord) = + (if ((HaveExtendedExecuteNeverExt () )) then + (let (tmp_530 :: Permissions) = ((TLBRecord_perms result)) in + (let (tmp_530 :: Permissions) = + ((tmp_530 (| + Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 :: int)::ii)] :: 1 Word.word))|))) in + (result (| TLBRecord_perms := tmp_530 |)))) + else result) in + (let (tmp_540 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_540 = ((tmp_540 (| Permissions_pxn := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_540 |))) in + (let result = ((result (| TLBRecord_nG := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let (tmp_550 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (S2AttrDecode sh memattr acctype) \ (\ (w__166 :: MemoryAttributes) . + (let (tmp_550 :: AddressDescriptor) = + ((tmp_550 (| AddressDescriptor_memattrs := w__166 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_550 |))) in + (let (tmp_560 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let (tmp_560 :: FullAddress) = + ((tmp_560 (| FullAddress_NS := ((vec_of_bits [B1] :: 1 Word.word))|))) in + (let (tmp_570 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_570 :: AddressDescriptor) = + ((tmp_570 (| AddressDescriptor_paddress := tmp_560 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_570 |))) in + return result)))))))))))))))))))))))))))) \ (\ (result :: TLBRecord) . + (let (tmp_580 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let tmp_580 = ((tmp_580 (| FullAddress_physicaladdress := outputaddress |))) in + (let (tmp_590 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_590 = ((tmp_590 (| AddressDescriptor_paddress := tmp_580 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_590 |))) in + (let (tmp_600 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + liftR (AArch64_NoFault () ) \ (\ (w__167 :: FaultRecord) . + (let (tmp_600 :: AddressDescriptor) = + ((tmp_600 (| AddressDescriptor_fault := w__167 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_600 |))) in + (let (result :: TLBRecord) = + ((result (| + TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1] :: 1 Word.word))))|))) in + (let (result :: TLBRecord) = + (if ((HaveCommonNotPrivateTransExt () )) then + (result (| + TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 :: int)::ii)] :: 1 Word.word))|)) + else result) in + return result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val IsZero_slice2 : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +definition IsZero_slice2 :: "('n::len)Word.word \ int \ int \((register_value),(bool),(exception))monad " where + " IsZero_slice2 xs i l = ( + assert_exp True ('''') \ + return ((IsZero ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)))))" + + +(*val AArch64_TranslateAddressS1Off : mword ty64 -> AccType -> bool -> M TLBRecord*) + +definition AArch64_TranslateAddressS1Off :: "(64)Word.word \ AccType \ bool \((register_value),(TLBRecord),(exception))monad " where + " AArch64_TranslateAddressS1Off vaddress acctype iswrite = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (assert_exp ((\ w__1)) ('''') \ + undefined_TLBRecord () ) \ (\ (result :: TLBRecord) . + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + AddrTop vaddress False(ProcState_EL w__2) \ (\ (Top :: ii) . + undefined_bool () \ (\ (s2fs1walk :: bool) . + undefined_bool () \ (\ (secondstage :: bool) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + undefined_int () \ (\ (level :: ii) . + IsZero_slice2 vaddress ((PAMax () )) + ((((((ex_int Top)) + (( 1 :: int)::ii))) - ((ex_int ((PAMax () )))))) \ (\ (w__3 :: + bool) . + if ((\ w__3)) then + (let level = ((( 0 :: int)::ii)) in + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (w__4 :: 52 bits) . + (let ipaddress = w__4 in + (let secondstage = False in + (let s2fs1walk = False in + (let (tmp_1980 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk \ (\ (w__5 :: + FaultRecord) . + (let (tmp_1980 :: AddressDescriptor) = ((tmp_1980 (| AddressDescriptor_fault := w__5 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_1980 |))) in + return result))))))))) + else + and_boolM ((HasS2Translation () )) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 12 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (default_cacheable :: bool) . + undefined_bool () \ (\ (cacheable :: bool) . + (if default_cacheable then + (let (tmp_1990 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_1990 :: MemoryAttributes) = + ((tmp_1990 (| MemoryAttributes_typ := MemType_Normal |))) in + (let (tmp_2000 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2000 :: AddressDescriptor) = + ((tmp_2000 (| AddressDescriptor_memattrs := tmp_1990 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2000 |))) in + (let (tmp_2010 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2010 :: MemAttrHints) = ((tmp_2010 (| MemAttrHints_attrs := MemAttr_WB |))) in + (let (tmp_2020 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2020 :: MemoryAttributes) = ((tmp_2020 (| MemoryAttributes_inner := tmp_2010 |))) in + (let (tmp_2030 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2030 :: AddressDescriptor) = + ((tmp_2030 (| AddressDescriptor_memattrs := tmp_2020 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2030 |))) in + (let (tmp_2040 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2040 :: MemAttrHints) = ((tmp_2040 (| MemAttrHints_hints := MemHint_RWA |))) in + (let (tmp_2050 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2050 :: MemoryAttributes) = ((tmp_2050 (| MemoryAttributes_inner := tmp_2040 |))) in + (let (tmp_2060 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2060 :: AddressDescriptor) = + ((tmp_2060 (| AddressDescriptor_memattrs := tmp_2050 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2060 |))) in + (let (tmp_2070 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2070 :: MemoryAttributes) = ((tmp_2070 (| MemoryAttributes_shareable := False |))) in + (let (tmp_2080 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2080 :: AddressDescriptor) = + ((tmp_2080 (| AddressDescriptor_memattrs := tmp_2070 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2080 |))) in + (let (tmp_2090 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2090 :: MemoryAttributes) = + ((tmp_2090 (| MemoryAttributes_outershareable := False |))) in + (let (tmp_2100 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2100 :: AddressDescriptor) = + ((tmp_2100 (| AddressDescriptor_memattrs := tmp_2090 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2100 |))) in + return result))))))))))))))))))))))))))))) + else if (((acctype \ AccType_IFETCH))) then + (let (tmp_2110 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let tmp_2110 = ((tmp_2110 (| MemoryAttributes_typ := MemType_Device |))) in + (let (tmp_2120 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_2120 = ((tmp_2120 (| AddressDescriptor_memattrs := tmp_2110 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2120 |))) in + (let (tmp_2130 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let tmp_2130 = ((tmp_2130 (| MemoryAttributes_device := DeviceType_nGnRnE |))) in + (let (tmp_2140 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_2140 = ((tmp_2140 (| AddressDescriptor_memattrs := tmp_2130 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2140 |))) in + (let (tmp_2150 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + undefined_MemAttrHints () \ (\ (w__8 :: MemAttrHints) . + (let (tmp_2150 :: MemoryAttributes) = ((tmp_2150 (| MemoryAttributes_inner := w__8 |))) in + (let (tmp_2160 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2160 :: AddressDescriptor) = + ((tmp_2160 (| AddressDescriptor_memattrs := tmp_2150 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2160 |))) in + return result)))))))))))))))) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + (let (cacheable :: bool) = + ((vec_of_bits [access_vec_dec w__9 (( 12 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (tmp_2170 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2170 :: MemoryAttributes) = + ((tmp_2170 (| MemoryAttributes_typ := MemType_Normal |))) in + (let (tmp_2180 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2180 :: AddressDescriptor) = + ((tmp_2180 (| AddressDescriptor_memattrs := tmp_2170 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2180 |))) in + (let (result :: TLBRecord) = + (if cacheable then + (let (tmp_2190 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2190 :: MemAttrHints) = ((tmp_2190 (| MemAttrHints_attrs := MemAttr_WT |))) in + (let (tmp_2200 :: MemoryAttributes) = + ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2200 :: MemoryAttributes) = + ((tmp_2200 (| MemoryAttributes_inner := tmp_2190 |))) in + (let (tmp_2210 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2210 :: AddressDescriptor) = + ((tmp_2210 (| AddressDescriptor_memattrs := tmp_2200 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2210 |))) in + (let (tmp_2220 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2220 :: MemAttrHints) = ((tmp_2220 (| MemAttrHints_hints := MemHint_RA |))) in + (let (tmp_2230 :: MemoryAttributes) = + ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2230 :: MemoryAttributes) = + ((tmp_2230 (| MemoryAttributes_inner := tmp_2220 |))) in + (let (tmp_2240 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2240 :: AddressDescriptor) = + ((tmp_2240 (| AddressDescriptor_memattrs := tmp_2230 |))) in + (result (| TLBRecord_addrdesc := tmp_2240 |))))))))))))))) + else + (let (tmp_2250 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2250 :: MemAttrHints) = ((tmp_2250 (| MemAttrHints_attrs := MemAttr_NC |))) in + (let (tmp_2260 :: MemoryAttributes) = + ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2260 :: MemoryAttributes) = + ((tmp_2260 (| MemoryAttributes_inner := tmp_2250 |))) in + (let (tmp_2270 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2270 :: AddressDescriptor) = + ((tmp_2270 (| AddressDescriptor_memattrs := tmp_2260 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2270 |))) in + (let (tmp_2280 :: MemAttrHints) = + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result)))) in + (let (tmp_2280 :: MemAttrHints) = ((tmp_2280 (| MemAttrHints_hints := MemHint_No |))) in + (let (tmp_2290 :: MemoryAttributes) = + ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2290 :: MemoryAttributes) = + ((tmp_2290 (| MemoryAttributes_inner := tmp_2280 |))) in + (let (tmp_2300 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2300 :: AddressDescriptor) = + ((tmp_2300 (| AddressDescriptor_memattrs := tmp_2290 |))) in + (result (| TLBRecord_addrdesc := tmp_2300 |)))))))))))))))) in + (let (tmp_2310 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2310 :: MemoryAttributes) = ((tmp_2310 (| MemoryAttributes_shareable := True |))) in + (let (tmp_2320 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2320 :: AddressDescriptor) = + ((tmp_2320 (| AddressDescriptor_memattrs := tmp_2310 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2320 |))) in + (let (tmp_2330 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let (tmp_2330 :: MemoryAttributes) = + ((tmp_2330 (| MemoryAttributes_outershareable := True |))) in + (let (tmp_2340 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let (tmp_2340 :: AddressDescriptor) = + ((tmp_2340 (| AddressDescriptor_memattrs := tmp_2330 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2340 |))) in + return result))))))))))))))))))) \ (\ (result :: TLBRecord) . + (let (tmp_2350 :: MemoryAttributes) = ((AddressDescriptor_memattrs (TLBRecord_addrdesc result))) in + (let tmp_2350 = + ((tmp_2350 (| + MemoryAttributes_outer := + ((MemoryAttributes_inner (AddressDescriptor_memattrs (TLBRecord_addrdesc result))))|))) in + (let (tmp_2360 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_2360 = ((tmp_2360 (| AddressDescriptor_memattrs := tmp_2350 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2360 |))) in + (let (tmp_2370 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + MemAttrDefaults(AddressDescriptor_memattrs (TLBRecord_addrdesc result)) \ (\ (w__10 :: + MemoryAttributes) . + (let tmp_2370 = ((tmp_2370 (| AddressDescriptor_memattrs := w__10 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2370 |))) in + (let (tmp_2380 :: Permissions) = ((TLBRecord_perms result)) in + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (w__11 :: 3 bits) . + (let tmp_2380 = ((tmp_2380 (| Permissions_ap := w__11 |))) in + (let result = ((result (| TLBRecord_perms := tmp_2380 |))) in + (let (tmp_2390 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_2390 = ((tmp_2390 (| Permissions_xn := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_2390 |))) in + (let (tmp_2400 :: Permissions) = ((TLBRecord_perms result)) in + (let tmp_2400 = ((tmp_2400 (| Permissions_pxn := ((vec_of_bits [B0] :: 1 Word.word))|))) in + (let result = ((result (| TLBRecord_perms := tmp_2400 |))) in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__12 :: 1 bits) . + (let result = ((result (| TLBRecord_nG := w__12 |))) in + undefined_bool () \ (\ (w__13 :: bool) . + (let result = ((result (| TLBRecord_contiguous := w__13 |))) in + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (w__14 :: 4 bits) . + (let result = ((result (| TLBRecord_domain := w__14 |))) in + undefined_int () \ (\ (w__15 :: ii) . + (let result = ((result (| TLBRecord_level := w__15 |))) in + undefined_int () \ (\ (w__16 :: ii) . + (let result = ((result (| TLBRecord_blocksize := w__16 |))) in + (let (tmp_2410 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + (let tmp_2410 = + ((tmp_2410 (| + FullAddress_physicaladdress := ((slice0 vaddress (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word))|))) in + (let (tmp_2420 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_2420 = ((tmp_2420 (| AddressDescriptor_paddress := tmp_2410 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2420 |))) in + (let (tmp_2430 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in + IsSecure () \ (\ (w__17 :: bool) . + (let tmp_2430 = + ((tmp_2430 (| + FullAddress_NS := + (if w__17 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word))|))) in + (let (tmp_2440 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + (let tmp_2440 = ((tmp_2440 (| AddressDescriptor_paddress := tmp_2430 |))) in + (let result = ((result (| TLBRecord_addrdesc := tmp_2440 |))) in + (let (tmp_2450 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in + AArch64_NoFault () \ (\ (w__18 :: FaultRecord) . + (let (tmp_2450 :: AddressDescriptor) = ((tmp_2450 (| AddressDescriptor_fault := w__18 |))) in + (let (result :: TLBRecord) = ((result (| TLBRecord_addrdesc := tmp_2450 |))) in + return result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val AArch64_MaybeZeroRegisterUppers : unit -> M unit*) + +definition AArch64_MaybeZeroRegisterUppers :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_MaybeZeroRegisterUppers _ = ( + UsingAArch32 () \ (\ (w__0 :: bool) . + (assert_exp w__0 (''UsingAArch32()'') \ + undefined_bool () ) \ (\ (include_R15_name :: bool) . + undefined_int () \ (\ (last1 :: ii) . + undefined_int () \ (\ (first1 :: ii) . + and_boolM + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) = EL0))))) + (ELUsingAArch32 EL1 \ (\ (w__2 :: bool) . return ((\ w__2)))) \ (\ (w__3 :: bool) . + (if w__3 then + (let (first1 :: ii) = ((( 0 :: int)::ii)) in + (let (last1 :: ii) = ((( 14 :: int)::ii)) in + (let (include_R15_name :: bool) = False in + return (first1, include_R15_name, last1)))) + else + and_boolM + (and_boolM + (and_boolM + (or_boolM + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_EL w__4) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_EL w__5) = EL1)))))) (return ((HaveEL EL2)))) + (IsSecure () \ (\ (w__8 :: bool) . return ((\ w__8))))) + (ELUsingAArch32 EL2 \ (\ (w__10 :: bool) . return ((\ w__10)))) \ (\ (w__11 :: bool) . + (let ((first1 :: ii), (include_R15_name :: bool), (last1 :: ii)) = + (if w__11 then + (let (first1 :: ii) = ((( 0 :: int)::ii)) in + (let (last1 :: ii) = ((( 30 :: int)::ii)) in + (let (include_R15_name :: bool) = False in + (first1, include_R15_name, last1)))) + else + (let (first1 :: ii) = ((( 0 :: int)::ii)) in + (let (last1 :: ii) = ((( 30 :: int)::ii)) in + (let (include_R15_name :: bool) = True in + (first1, include_R15_name, last1))))) in + return (first1, include_R15_name, last1)))) \ (\ varstup . (let ((first1 :: ii), (include_R15_name :: + bool), (last1 :: ii)) = varstup in + (foreachM (index_list first1 last1 (( 1 :: int)::ii)) () + (\ n unit_var . + and_boolM (return ((((((n \ (( 15 :: int)::ii)))) \ include_R15_name)))) + ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER)) \ (\ (w__13 :: bool) . + if w__13 then + read_reg R_ref \ (\ (w__14 :: ( 64 bits) list) . + (let (tmp_30 :: 64 bits) = ((access_list_dec w__14 n :: 64 Word.word)) in + (let tmp_30 = + ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) + :: 64 Word.word)) in + read_reg R_ref \ (\ (w__15 :: ( 64 Word.word) list) . + write_reg R_ref ((update_list_dec w__15 n tmp_30 :: ( 64 Word.word) list)))))) + else return () )))))))))))" + + +(*val DCPSInstruction : mword ty2 -> M unit*) + +definition DCPSInstruction :: "(2)Word.word \((register_value),(unit),(exception))monad " where + " DCPSInstruction target_el = ( + (let (_ :: unit) = (SynchronizeContext () ) in + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (handle_el :: 2 bits) . + (let pat0 = target_el in + (if (((pat0 = EL1))) then + or_boolM + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL2))))) + (and_boolM + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + return ((((ProcState_EL w__1) = EL3))))) + (UsingAArch32 () \ (\ (w__2 :: bool) . return ((\ w__2))))) \ (\ (w__4 :: bool) . + if w__4 then + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + (let (handle_el :: 2 bits) = ((ProcState_EL w__5)) in + return handle_el)) + else + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__6 :: bool) . return ((\ w__6))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__9 :: bool) . + if w__9 then UndefinedFault () \ return handle_el + else return EL1)) + else if (((pat0 = EL2))) then + if ((\ ((HaveEL EL2)))) then UndefinedFault () \ return handle_el + else + and_boolM + (read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + return ((((ProcState_EL w__10) = EL3))))) + (UsingAArch32 () \ (\ (w__11 :: bool) . return ((\ w__11)))) \ (\ (w__12 :: bool) . + if w__12 then return EL3 + else + IsSecure () \ (\ (w__13 :: bool) . + if w__13 then UndefinedFault () \ return handle_el + else return EL2)) + else if (((pat0 = EL3))) then + or_boolM + ((read_reg EDSCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 16 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) (return ((\ ((HaveEL EL3))))) \ (\ (w__15 :: + bool) . + (if w__15 then UndefinedFault () else return () ) \ return EL3) + else Unreachable () \ return handle_el) \ (\ (handle_el :: 2 bits) . + IsSecure () \ (\ (from_secure :: bool) . + ELUsingAArch32 handle_el \ (\ (w__16 :: bool) . + (((if w__16 then + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + ((if ((((ProcState_M w__17) = M32_Monitor))) then + (read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + write_reg + SCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + else return () ) \ + UsingAArch32 () ) \ (\ (w__19 :: bool) . + assert_exp w__19 (''UsingAArch32()'') \ + ((let pat0 = handle_el in + (((if (((pat0 = EL1))) then + (AArch32_WriteMode M32_Svc \ + and_boolM (return ((HavePANExt () ))) + ((read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__21 :: bool) . + if w__21 then + read_reg PSTATE_ref \ (\ (w__22 :: ProcState) . + write_reg PSTATE_ref (w__22 (| ProcState_PAN := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) + else if (((pat0 = EL2))) then AArch32_WriteMode M32_Hyp + else + AArch32_WriteMode M32_Monitor \ + (if ((HavePANExt () )) then + if ((\ from_secure)) then + read_reg PSTATE_ref \ (\ (w__23 :: ProcState) . + write_reg PSTATE_ref (w__23 (| ProcState_PAN := ((vec_of_bits [B0] :: 1 Word.word))|))) + else + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__24 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__24 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__25 :: ProcState) . + write_reg PSTATE_ref (w__25 (| ProcState_PAN := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) + else return () )) \ + (if (((handle_el = EL2))) then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__26 :: 32 bits) . + (write_reg ELR_hyp_ref w__26 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__27 :: 32 bits) . + write_reg HSR_ref w__27)) + else + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__28 :: 32 Word.word) . + set_LR w__28))) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__29 :: 32 Word.word) . + (aset_SPSR w__29 \ + read_reg PSTATE_ref) \ (\ (w__30 :: ProcState) . + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__31 :: 32 Word.word) . + (write_reg + PSTATE_ref + (w__30 (| ProcState_E := ((vec_of_bits [access_vec_dec w__31 (( 25 :: int)::ii)] :: 1 Word.word))|)) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__32 :: 32 bits) . + (write_reg DLR_ref w__32 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__33 :: 32 bits) . + write_reg DSPSR_ref w__33))))))))) + else + UsingAArch32 () \ (\ (w__34 :: bool) . + ((if w__34 then AArch64_MaybeZeroRegisterUppers () + else return () ) \ + read_reg PSTATE_ref) \ (\ (w__35 :: ProcState) . + (write_reg PSTATE_ref (w__35 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__36 :: ProcState) . + (write_reg PSTATE_ref (w__36 (| ProcState_SP := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__37 :: ProcState) . + (write_reg PSTATE_ref (w__37 (| ProcState_EL := handle_el |)) \ + and_boolM (return ((HavePANExt () ))) + (or_boolM + (and_boolM (return (((handle_el = EL1)))) + ((read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__38 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__38 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + (and_boolM + (and_boolM + (and_boolM (return (((handle_el = EL2)))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__40 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__40 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__42 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__42 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__44 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__44 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))))) \ (\ (w__47 :: bool) . + ((if w__47 then + read_reg PSTATE_ref \ (\ (w__48 :: ProcState) . + write_reg PSTATE_ref (w__48 (| ProcState_PAN := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__49 :: 64 Word.word) . + (aset_ELR__1 w__49 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__50 :: 32 Word.word) . + (aset_SPSR w__50 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__51 :: 32 Word.word) . + (aset_ESR__1 w__51 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__52 :: 64 bits) . + (write_reg DLR_EL0_ref w__52 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__53 :: 32 bits) . + write_reg DSPSR_EL0_ref w__53 \ + (if ((HaveUAOExt () )) then + read_reg PSTATE_ref \ (\ (w__54 :: ProcState) . + write_reg PSTATE_ref (w__54 (| ProcState_UAO := ((vec_of_bits [B0] :: 1 Word.word))|))) + else return () )))))))))))) \ + UpdateEDSCRFields () ) \ + and_boolM + (and_boolM (return ((HaveRASExt () ))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__55 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__55 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((ConstrainUnpredictableBool Unpredictable_IESBinDebug))) \ (\ (w__58 :: bool) . + (let (_ :: unit) = + (if w__58 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All + else () ) in + return () )))))))))" + + +(*val aarch64_system_exceptions_debug_exception : mword ty2 -> M unit*) + +definition aarch64_system_exceptions_debug_exception :: "(2)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_debug_exception target_level = ( DCPSInstruction target_level )" + + +(*val AArch64_GenerateDebugExceptionsFrom : mword ty2 -> bool -> mword ty1 -> M bool*) + +definition AArch64_GenerateDebugExceptionsFrom :: "(2)Word.word \ bool \(1)Word.word \((register_value),(bool),(exception))monad " where + " AArch64_GenerateDebugExceptionsFrom from1 secure mask1 = ( + or_boolM + (or_boolM + ((read_reg OSLSR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) ((DoubleLockStatus () ))) ((Halted () )) \ (\ (w__4 :: + bool) . + if w__4 then return False + else + and_boolM (return (((((HaveEL EL2)) \ ((\ secure)))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (route_to_el2 :: bool) . + (let (target :: 2 bits) = (if route_to_el2 then EL2 else EL1) in + or_boolM (return (((((\ ((HaveEL EL3)))) \ ((\ secure)))))) + ((read_reg MDCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 16 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \ (\ (enabled :: bool) . + if (((from1 = target))) then + and_boolM + (and_boolM (return enabled) + ((read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__9 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 13 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (return (((mask1 = (vec_of_bits [B0] :: 1 Word.word))))) + else + (let (enabled :: bool) = (enabled \ ((((Word.uint target)) > ((Word.uint from1))))) in + return enabled))))))" + + +(*val AArch64_GenerateDebugExceptions : unit -> M bool*) + +definition AArch64_GenerateDebugExceptions :: " unit \((register_value),(bool),(exception))monad " where + " AArch64_GenerateDebugExceptions _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + IsSecure () \ (\ (w__1 :: bool) . + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + AArch64_GenerateDebugExceptionsFrom(ProcState_EL w__0) w__1(ProcState_D w__2)))))" + + +(*val AArch64_FaultSyndrome : bool -> FaultRecord -> M (mword ty25)*) + +definition AArch64_FaultSyndrome :: " bool \ FaultRecord \((register_value),((25)Word.word),(exception))monad " where + " AArch64_FaultSyndrome d_side fault = ( + assert_exp ((((FaultRecord_typ fault) \ Fault_None))) (''((fault).type != Fault_None)'') \ + ((let (iss :: 25 bits) = ((Zeros__1 (( 25 :: int)::ii) () :: 25 Word.word)) in + and_boolM (return ((HaveRASExt () ))) ((IsExternalSyncAbort__1 fault)) \ (\ (w__1 :: bool) . + (let (iss :: 25 bits) = + (if w__1 then (set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) iss (( 11 :: int)::ii)(FaultRecord_errortype fault) :: 25 Word.word) + else iss) in + (if d_side then + and_boolM ((IsSecondStage fault)) (return ((\(FaultRecord_s2fs1walk fault)))) \ (\ (w__3 :: + bool) . + (if w__3 then + (LSInstructionSyndrome () :: ( 11 Word.word) M) \ (\ (w__4 :: 11 Word.word) . + (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 11 :: int)::ii) iss (( 14 :: int)::ii) w__4 :: 25 Word.word)) in + return iss)) + else return iss) \ (\ (iss :: 25 bits) . + (let (iss :: 25 bits) = + (if (((((((FaultRecord_acctype fault) = AccType_DC))) \ (((((((FaultRecord_acctype fault) = AccType_IC))) \ ((((FaultRecord_acctype fault) = AccType_AT))))))))) then + (let (iss :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 8 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in + (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) + else + (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) + (if(FaultRecord_write fault) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 25 Word.word)) in + return iss))) + else return iss) \ (\ (iss :: 25 bits) . + IsExternalAbort__1 fault \ (\ (w__5 :: bool) . + (let (iss :: 25 bits) = + (if w__5 then (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 9 :: int)::ii)(FaultRecord_extflag fault) :: 25 Word.word) + else iss) in + (let iss = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 7 :: int)::ii) + (if(FaultRecord_s2fs1walk fault) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 25 Word.word)) in + (EncodeLDFSC(FaultRecord_typ fault)(FaultRecord_level fault) :: ( 6 Word.word) M) \ (\ (w__6 :: + 6 Word.word) . + (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 6 :: int)::ii) iss (( 0 :: int)::ii) w__6 :: 25 Word.word)) in + return iss)))))))))))" + + +(*val AArch64_AbortSyndrome : Exception -> FaultRecord -> mword ty64 -> M ExceptionRecord*) + +definition AArch64_AbortSyndrome :: " Exception \ FaultRecord \(64)Word.word \((register_value),(ExceptionRecord),(exception))monad " where + " AArch64_AbortSyndrome typ1 fault vaddress = ( + ExceptionSyndrome typ1 \ (\ (exception :: ExceptionRecord) . + (let (d_side :: bool) = ((((typ1 = Exception_DataAbort))) \ (((typ1 = Exception_Watchpoint)))) in + (AArch64_FaultSyndrome d_side fault :: ( 25 Word.word) M) \ (\ (w__0 :: 25 bits) . + (let exception = ((exception (| ExceptionRecord_syndrome := w__0 |))) in + (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let exception = ((exception (| ExceptionRecord_vaddress := w__1 |))) in + IPAValid fault \ (\ (w__2 :: bool) . + (let (exception :: ExceptionRecord) = + (if w__2 then + (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_ipavalid := True |))) in + (exception (| ExceptionRecord_ipaddress := ((FaultRecord_ipaddress fault))|))) + else (exception (| ExceptionRecord_ipavalid := False |))) in + return exception)))))))))" + + +(*val AArch64_ExecutingATS1xPInstr : unit -> M bool*) + +definition AArch64_ExecutingATS1xPInstr :: " unit \((register_value),(bool),(exception))monad " where + " AArch64_ExecutingATS1xPInstr _ = ( + if ((\ ((HavePrivATExt () )))) then return False + else + (ThisInstr0 () :: ( 32 Word.word) M) \ (\ (instr :: 32 bits) . + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (op2 :: 3 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (CRm :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \ (\ (CRn :: 4 bits) . + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \ (\ (op1 :: 3 bits) . + (let (w__0 :: bool) = + (if (((((slice0 instr (( 22 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0] :: 10 Word.word)))) then + (let (op1 :: 3 bits) = ((slice0 instr (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((slice0 instr (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + ((((((((((op1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((CRn = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))))))) \ (((CRm = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))))))) \ ((((((op2 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((op2 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))))))))))) + else False) in + return w__0)))))))" + + +(*val AArch64_ExceptionClass : Exception -> mword ty2 -> M (ii * mword ty1)*) + +definition AArch64_ExceptionClass :: " Exception \(2)Word.word \((register_value),(int*(1)Word.word),(exception))monad " where + " AArch64_ExceptionClass typ1 target_el = ( + ThisInstrLength () \ (\ (w__0 :: ii) . + (let (il :: 1 bits) = + (if (((((ex_int w__0)) = (( 32 :: int)::ii)))) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) in + UsingAArch32 () \ (\ (from_32 :: bool) . + (assert_exp (((from_32 \ (((il = (vec_of_bits [B1] :: 1 Word.word))))))) ([(CHR ''(''), (CHR ''f''), (CHR ''r''), (CHR ''o''), (CHR ''m''), (CHR ''_''), (CHR ''3''), (CHR ''2''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''i''), (CHR ''l''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '')'')]) \ + undefined_int () ) \ (\ (ec :: ii) . + (case typ1 of + Exception_Uncategorized => + (let (ec :: ii) = ((( 0 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_WFxTrap => + (let (ec :: ii) = ((( 1 :: int)::ii)) in + return (ec, il)) + | Exception_CP15RTTrap => + (let ec = ((( 3 :: int)::ii)) in + assert_exp from_32 (''from_32'') \ return (ec, il)) + | Exception_CP15RRTTrap => + (let ec = ((( 4 :: int)::ii)) in + assert_exp from_32 (''from_32'') \ return (ec, il)) + | Exception_CP14RTTrap => + (let ec = ((( 5 :: int)::ii)) in + assert_exp from_32 (''from_32'') \ return (ec, il)) + | Exception_CP14DTTrap => + (let ec = ((( 6 :: int)::ii)) in + assert_exp from_32 (''from_32'') \ return (ec, il)) + | Exception_AdvSIMDFPAccessTrap => + (let (ec :: ii) = ((( 7 :: int)::ii)) in + return (ec, il)) + | Exception_FPIDTrap => + (let (ec :: ii) = ((( 8 :: int)::ii)) in + return (ec, il)) + | Exception_CP14RRTTrap => + (let ec = ((( 12 :: int)::ii)) in + assert_exp from_32 (''from_32'') \ return (ec, il)) + | Exception_IllegalState => + (let (ec :: ii) = ((( 14 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_SupervisorCall => + (let (ec :: ii) = ((( 17 :: int)::ii)) in + return (ec, il)) + | Exception_HypervisorCall => + (let (ec :: ii) = ((( 18 :: int)::ii)) in + return (ec, il)) + | Exception_MonitorCall => + (let (ec :: ii) = ((( 19 :: int)::ii)) in + return (ec, il)) + | Exception_SystemRegisterTrap => + (let ec = ((( 24 :: int)::ii)) in + assert_exp ((\ from_32)) (''!(from_32)'') \ return (ec, il)) + | Exception_InstructionAbort => + (let (ec :: ii) = ((( 32 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_PCAlignment => + (let (ec :: ii) = ((( 34 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_DataAbort => + (let (ec :: ii) = ((( 36 :: int)::ii)) in + return (ec, il)) + | Exception_SPAlignment => + (let ec = ((( 38 :: int)::ii)) in + (let il = ((vec_of_bits [B1] :: 1 Word.word)) in + assert_exp ((\ from_32)) (''!(from_32)'') \ return (ec, il))) + | Exception_FPTrappedException => + (let (ec :: ii) = ((( 40 :: int)::ii)) in + return (ec, il)) + | Exception_SError => + (let (ec :: ii) = ((( 47 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_Breakpoint => + (let (ec :: ii) = ((( 48 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_SoftwareStep => + (let (ec :: ii) = ((( 50 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_Watchpoint => + (let (ec :: ii) = ((( 52 :: int)::ii)) in + (let (il :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + return (ec, il))) + | Exception_SoftwareBreakpoint => + (let (ec :: ii) = ((( 56 :: int)::ii)) in + return (ec, il)) + | Exception_VectorCatch => + (let ec = ((( 58 :: int)::ii)) in + (let il = ((vec_of_bits [B1] :: 1 Word.word)) in + assert_exp from_32 (''from_32'') \ return (ec, il))) + | _ => Unreachable () \ return (ec, il) + ) \ (\ varstup . (let ((ec :: ii), (il :: 1 bits)) = varstup in + and_boolM + (return ((((((((ex_int ec)) = (( 32 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 36 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 48 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 50 :: int)::ii)))) \ (((((ex_int ec)) = (( 52 :: int)::ii))))))))))))))))) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + return (((target_el =(ProcState_EL w__1)))))) \ (\ (w__2 :: bool) . + (let (ec :: ii) = (if w__2 then ((ex_int ec)) + (( 1 :: int)::ii) else ec) in + (let (ec :: ii) = + (if (((((((((((ex_int ec)) = (( 17 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 18 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 19 :: int)::ii)))) \ ((((((((ex_int ec)) = (( 40 :: int)::ii)))) \ (((((ex_int ec)) = (( 56 :: int)::ii)))))))))))))))) \ ((\ from_32))))) then + ((ex_int ec)) + (( 4 :: int)::ii) + else ec) in + return (ec, il)))))))))))" + + +(*val AArch64_ReportException : ExceptionRecord -> mword ty2 -> M unit*) + +definition AArch64_ReportException :: " ExceptionRecord \(2)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_ReportException exception target_el = ( + (let (typ1 :: Exception) = ((ExceptionRecord_typ exception)) in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (il :: 1 bits) . + undefined_int () \ (\ (ec :: ii) . + (AArch64_ExceptionClass typ1 target_el :: ((ii * 1 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let ec = tup__0 in + (let il = tup__1 in + (let (iss :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (il :: 1 bits) = + (if (((((((((((ex_int ec)) = (( 36 :: int)::ii)))) \ (((((ex_int ec)) = (( 37 :: int)::ii))))))) \ ((((vec_of_bits [access_vec_dec iss (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (vec_of_bits [B1] :: 1 Word.word) + else il) in + (aset_ESR__0 target_el + ((concat_vec + ((concat_vec + ((GetSlice_int ((make_the_value (( 6 :: int)::ii) :: 6 itself)) ec (( 0 :: int)::ii) :: 6 Word.word)) il + :: 7 Word.word)) iss + :: 32 Word.word)) \ + (if ((((((typ1 = Exception_InstructionAbort))) \ ((((((typ1 = Exception_PCAlignment))) \ ((((((typ1 = Exception_DataAbort))) \ (((typ1 = Exception_Watchpoint)))))))))))) then + aset_FAR__0 target_el(ExceptionRecord_vaddress exception) + else + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + aset_FAR__0 target_el w__0))) \ + (if (((target_el = EL2))) then + if(ExceptionRecord_ipavalid exception) then + (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + write_reg + HPFAR_EL2_ref + ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii) + ((slice0(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 40 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word))) + else + (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (undefined_bitvector (( 40 :: int)::ii) :: ( 40 Word.word) M) \ (\ (w__3 :: 40 Word.word) . + write_reg HPFAR_EL2_ref ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3 :: 64 Word.word)))) + else return () )))))))))))" + + +(*val AArch64_ESBOperation : unit -> M unit*) + +definition AArch64_ESBOperation :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_ESBOperation _ = ( + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (route_to_el3 :: bool) . + and_boolM + (and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (route_to_el2 :: bool) . + (let (target :: 2 bits) = (if route_to_el3 then EL3 else if route_to_el2 then EL2 else EL1) in + undefined_bool () \ (\ (mask_active :: bool) . + (if (((target = EL1))) then + or_boolM + (read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . return ((((ProcState_EL w__6) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . return ((((ProcState_EL w__7) = EL1))))) + else + and_boolM (return (((((HaveVirtHostExt () )) \ (((target = EL2))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__10 :: 64 bits) . + return ((((access_vec_dec w__9 (( 34 :: int)::ii), access_vec_dec w__10 (( 27 :: int)::ii)) = (B1, B1))))))) \ (\ (w__11 :: + bool) . + if w__11 then + or_boolM + (read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + return ((((ProcState_EL w__12) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__13 :: ProcState) . + return ((((ProcState_EL w__13) = EL2))))) + else + read_reg PSTATE_ref \ (\ (w__15 :: ProcState) . + (let (mask_active :: bool) = ((ProcState_EL w__15) = target) in + return mask_active)))) \ (\ (mask_active :: bool) . + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + (let (mask_set :: bool) = ((ProcState_A w__16) = (vec_of_bits [B1] :: 1 Word.word)) in + or_boolM ((Halted () )) ((ExternalDebugInterruptsDisabled target)) \ (\ (intdis :: bool) . + or_boolM + (or_boolM + (read_reg PSTATE_ref \ (\ (w__19 :: ProcState) . + return ((((Word.uint target)) < ((Word.uint(ProcState_EL w__19))))))) (return intdis)) + (return (((mask_active \ mask_set)))) \ (\ (masked :: bool) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (DISR_EL1 :: 64 bits) . + (undefined_bitvector (( 25 :: int)::ii) :: ( 25 Word.word) M) \ (\ (syndrome64 :: 25 bits) . + undefined_bool () \ (\ (implicit_esb :: bool) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (DISR :: 32 bits) . + undefined_AArch32_SErrorSyndrome () \ (\ (syndrome32 :: AArch32_SErrorSyndrome) . + and_boolM ((SErrorPending () )) (return masked) \ (\ (w__22 :: bool) . + if w__22 then + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__23 :: 2 Word.word) . + ELUsingAArch32 w__23 \ (\ (w__24 :: bool) . + (if w__24 then + AArch32_PhysicalSErrorSyndrome () \ (\ (w__25 :: AArch32_SErrorSyndrome) . + (let syndrome32 = w__25 in + (AArch32_ReportDeferredSError(AArch32_SErrorSyndrome_AET syndrome32)(AArch32_SErrorSyndrome_ExT + syndrome32) + :: ( 32 Word.word) M) \ (\ (w__26 :: 32 bits) . + (let (DISR :: 32 bits) = w__26 in + return () )))) + else + (let implicit_esb = False in + (AArch64_PhysicalSErrorSyndrome implicit_esb :: ( 25 Word.word) M) \ (\ (w__27 :: 25 bits) . + (let syndrome64 = w__27 in + (AArch64_ReportDeferredSError syndrome64 :: ( 64 Word.word) M) \ (\ (w__28 :: 64 bits) . + (let (DISR_EL1 :: 64 bits) = w__28 in + return () )))))) \ + ClearPendingPhysicalSError () )) + else return () ))))))))))))))))" + + +definition AArch64_CheckAndUpdateDescriptor :: " DescriptorUpdate \ FaultRecord \ bool \(64)Word.word \ AccType \ bool \ bool \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckAndUpdateDescriptor result fault secondstage vaddress acctype iswrite s2fs1walk hwupdatewalk__arg = ( + catch_early_return + ((let hwupdatewalk = hwupdatewalk__arg in + liftR (undefined_bool () ) \ (\ (hw_update_AF :: bool) . + (let (hw_update_AF :: bool) = + (if(DescriptorUpdate_AF result) then + if ((((FaultRecord_typ fault) = Fault_None))) then True + else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True + else False + else hw_update_AF) in + liftR (undefined_bool () ) \ (\ (hw_update_AP :: bool) . + liftR (undefined_bool () ) \ (\ (write_perm_req :: bool) . + (let (hw_update_AP :: bool) = + (if ((((DescriptorUpdate_AP result) \ ((((FaultRecord_typ fault) = Fault_None)))))) then + (let (write_perm_req :: bool) = + ((((iswrite \ ((((((acctype = AccType_ATOMICRW))) \ (((acctype = AccType_ORDEREDRW))))))))) \ ((\ s2fs1walk))) in + ((((write_perm_req \ ((\ ((((((acctype = AccType_AT))) \ (((acctype = AccType_DC))))))))))) \ hwupdatewalk)) + else False) in + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (desc :: 64 bits) . + liftR (undefined_AccessDescriptor () ) \ (\ (accdesc :: AccessDescriptor) . + liftR (undefined_AddressDescriptor () ) \ (\ (descaddr2 :: AddressDescriptor) . + (if (((hw_update_AF \ hw_update_AP))) then + or_boolM (return secondstage) + (liftR (HasS2Translation () ) \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: + bool) . + (if w__1 then + (let (descaddr2 :: AddressDescriptor) = ((DescriptorUpdate_descaddr result)) in + return descaddr2) + else + (let hwupdatewalk = True in + liftR (AArch64_SecondStageWalk(DescriptorUpdate_descaddr result) vaddress acctype iswrite + (( 8 :: int)::ii) hwupdatewalk) \ (\ (w__2 :: AddressDescriptor) . + (let descaddr2 = w__2 in + (if ((IsFault descaddr2)) then + (early_return(AddressDescriptor_fault descaddr2) :: (unit, FaultRecord) MR) + else return () ) \ + return descaddr2)))) \ (\ (descaddr2 :: AddressDescriptor) . + liftR (CreateAccessDescriptor AccType_ATOMICRW) \ (\ (w__3 :: AccessDescriptor) . + (let accdesc = w__3 in + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \ (\ (w__4 :: 64 bits) . + (let desc = w__4 in + (let (desc :: 64 bits) = + (if hw_update_AF then + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + else desc) in + (let (desc :: 64 bits) = + (if hw_update_AP then + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) + (if secondstage then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word) + else desc) in + liftR (aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc))))))))) + else return () ) \ + return fault)))))))))))" + + +(*val AArch64_BreakpointValueMatch : ii -> mword ty64 -> bool -> bool*) + +definition AArch64_BreakpointValueMatch :: " int \(64)Word.word \ bool \ bool " where + " AArch64_BreakpointValueMatch n__arg vaddress linked_to = ( False )" + + +(*val AArch64_StateMatch : mword ty2 -> mword ty1 -> mword ty2 -> bool -> mword ty4 -> bool -> bool -> M bool*) + +definition AArch64_StateMatch :: "(2)Word.word \(1)Word.word \(2)Word.word \ bool \(4)Word.word \ bool \ bool \((register_value),(bool),(exception))monad " where + " AArch64_StateMatch SSC__arg HMC__arg PxC__arg linked__arg LBN isbreakpnt ispriv = ( + catch_early_return + ((let HMC = HMC__arg in + (let PxC = PxC__arg in + (let SSC = SSC__arg in + (let linked = linked__arg in + liftR (undefined_Constraint () ) \ (\ (c :: Constraint) . + (if ((((((((((((((((((((and_vec + ((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC + :: 5 Word.word)) (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word) + :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) \ ((((((((and_vec + ((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC + :: 5 Word.word)) + (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word) + :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \ ((((((((and_vec + ((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC + :: 5 Word.word)) + (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word) + :: 5 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) \ ((((((((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC + :: 5 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))) \ ((((((((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) + PxC + :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) \ (((((and_vec + ((concat_vec + ((concat_vec HMC SSC :: 3 Word.word)) PxC + :: 5 Word.word)) + (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word) + :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))))))))))))))))))) \ (((((((((HMC = (vec_of_bits [B0] :: 1 Word.word)))) \ (((PxC = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \ (((((\ isbreakpnt)) \ ((\ ((HaveAArch32EL EL1))))))))))))) \ (((((((((SSC = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((SSC = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \ ((\ ((HaveEL EL3)))))))))) \ ((((((((((((((concat_vec HMC SSC :: 3 Word.word)) \ (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((((concat_vec HMC SSC :: 3 Word.word)) \ (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) \ ((\ ((HaveEL EL3))))))) \ ((\ ((HaveEL EL2)))))))))) \ ((((((((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))) \ ((\ ((HaveEL EL2)))))))))) then + liftR ((undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M)) \ (\ (tmp_50 :: 5 bits) . + liftR ((ConstrainUnpredictableBits (( 5 :: int)::ii) Unpredictable_RESBPWPCTRL + :: ((Constraint * 5 Word.word)) M)) \ (\ (w__0 :: (Constraint * 5 bits)) . + (let (tup__0, tup__1) = w__0 in + (let c = tup__0 in + (let tmp_50 = tup__1 in + (let (tmp_60 :: 5 bits) = tmp_50 in + (let HMC = ((vec_of_bits [access_vec_dec tmp_60 (( 4 :: int)::ii)] :: 1 Word.word)) in + (let (tmp_70 :: 4 bits) = ((slice0 tmp_60 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let SSC = ((slice0 tmp_70 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let PxC = ((slice0 tmp_70 (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (liftR (assert_exp ((((((c = Constraint_DISABLED))) \ (((c = Constraint_UNKNOWN)))))) (''((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))'')) \ + (if (((c = Constraint_DISABLED))) then (early_return False :: (unit, bool) MR) + else return () )) \ + return (HMC, PxC, SSC, c))))))))))) + else return (HMC, PxC, SSC, c)) \ (\ varstup . (let ((HMC :: 1 Word.word), (PxC :: 2 Word.word), (SSC :: + 2 Word.word), (c :: Constraint)) = varstup in + (let (EL3_match :: bool) = + ((((((HaveEL EL3)) \ (((HMC = (vec_of_bits [B1] :: 1 Word.word))))))) \ ((((vec_of_bits [access_vec_dec SSC (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))) in + (let (EL2_match :: bool) = (((HaveEL EL2)) \ (((HMC = (vec_of_bits [B1] :: 1 Word.word))))) in + (let (EL1_match :: bool) = + ((vec_of_bits [access_vec_dec PxC (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (EL0_match :: bool) = + ((vec_of_bits [access_vec_dec PxC (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + liftR (undefined_bool () ) \ (\ (priv_match :: bool) . + (if (((((\ ispriv)) \ ((\ isbreakpnt))))) then return EL0_match + else + liftR (read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (let (priv_match :: bool) = + ((case (ProcState_EL w__1) of EL31 => EL3_match )) in + return priv_match))) \ (\ (priv_match :: bool) . + liftR (undefined_bool () ) \ (\ (security_state_match :: bool) . + (let b__0 = SSC in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return True + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + liftR (IsSecure () ) \ (\ (w__2 :: bool) . + (let (security_state_match :: bool) = (\ w__2) in + return security_state_match)) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then liftR (IsSecure () ) + else return True) \ (\ (security_state_match :: bool) . + liftR (undefined_int () ) \ (\ (last_ctx_cmp :: ii) . + liftR (undefined_int () ) \ (\ (first_ctx_cmp :: ii) . + liftR (undefined_int () ) \ (\ (lbn :: ii) . + (if linked then + (let lbn = (Word.uint LBN) in + liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__4 :: 64 bits) . + liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__5 :: 64 bits) . + (let first_ctx_cmp = + (((Word.uint ((slice0 w__4 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) - + ((Word.uint ((slice0 w__5 (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))))) in + liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__6 :: 64 bits) . + (let last_ctx_cmp = (Word.uint ((slice0 w__6 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))) in + if (((((((ex_int lbn)) < ((ex_int first_ctx_cmp)))) \ ((((ex_int lbn)) > ((ex_int last_ctx_cmp))))))) then + liftR (ConstrainUnpredictableInteger first_ctx_cmp last_ctx_cmp Unpredictable_BPNOTCTXCMP) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let c = tup__0 in + (let lbn = tup__1 in + (liftR (assert_exp ((((((c = Constraint_DISABLED))) \ ((((((c = Constraint_NONE))) \ (((c = Constraint_UNKNOWN))))))))) (''((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))'')) \ + (case c of + Constraint_DISABLED => (early_return False :: (unit, bool) MR) \ return linked + | Constraint_NONE => return False + )) \ (\ (linked :: bool) . + return (lbn, linked)))))) + else return (lbn, linked))))))) + else return (lbn, linked)) \ (\ varstup . (let ((lbn :: ii), (linked :: bool)) = varstup in + liftR (undefined_bool () ) \ (\ (linked_match :: bool) . + liftR (undefined_bool () ) \ (\ (linked_to :: bool) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (vaddress :: 64 bits) . + (if linked then + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__7 :: 64 bits) . + (let (vaddress :: 64 bits) = w__7 in + (let (linked_to :: bool) = True in + (let (linked_match :: bool) = (AArch64_BreakpointValueMatch lbn vaddress linked_to) in + return linked_match)))) + else return linked_match) \ (\ (linked_match :: bool) . + return ((((((priv_match \ security_state_match))) \ (((((\ linked)) \ linked_match)))))))))))))))))))))))))))))))))" + + +(*val AArch64_WatchpointMatch : ii -> mword ty64 -> ii -> bool -> bool -> M bool*) + +definition AArch64_WatchpointMatch :: " int \(64)Word.word \ int \ bool \ bool \((register_value),(bool),(exception))monad " where + " AArch64_WatchpointMatch n vaddress size1 ispriv iswrite = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (assert_exp ((\ w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \ + (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__2 :: 64 bits) . + (assert_exp ((n \ ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).WRPs))'') \ + read_reg DBGWCR_EL1_ref) \ (\ (w__3 :: ( 32 bits) list) . + (let (enabled :: bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n :: 32 Word.word)) (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + read_reg DBGWCR_EL1_ref \ (\ (w__4 :: ( 32 bits) list) . + (let (linked :: bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__4 n :: 32 Word.word)) (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (isbreakpnt :: bool) = False in + read_reg DBGWCR_EL1_ref \ (\ (w__5 :: ( 32 bits) list) . + read_reg DBGWCR_EL1_ref \ (\ (w__6 :: ( 32 bits) list) . + read_reg DBGWCR_EL1_ref \ (\ (w__7 :: ( 32 bits) list) . + read_reg DBGWCR_EL1_ref \ (\ (w__8 :: ( 32 bits) list) . + AArch64_StateMatch ((slice0 ((access_list_dec w__5 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [access_vec_dec ((access_list_dec w__6 n :: 32 Word.word)) (( 13 :: int)::ii)] :: 1 Word.word) + ((slice0 ((access_list_dec w__7 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked + ((slice0 ((access_list_dec w__8 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt + ispriv \ (\ (state_match :: bool) . + read_reg DBGWCR_EL1_ref \ (\ (w__9 :: ( 32 bits) list) . + (let (ls_match :: bool) = + ((vec_of_bits [access_vec_dec + ((slice0 ((access_list_dec w__9 n :: 32 Word.word)) (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (if iswrite then (( 1 :: int)::ii) + else (( 0 :: int)::ii))] + :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (value_match_name :: bool) = False in + (foreachM (index_list (( 0 :: int)::ii) ((size1 - (( 1 :: int)::ii))) (( 1 :: int)::ii)) value_match_name + (\ byte value_match_name . + or_boolM (return value_match_name) + ((AArch64_WatchpointByteMatch n ((add_vec_int vaddress byte :: 64 Word.word)))))) \ (\ (value_match_name :: + bool) . + return (((((((((value_match_name \ state_match))) \ ls_match))) \ enabled)))))))))))))))))))))" + + +(*val AArch64_BreakpointMatch : ii -> mword ty64 -> ii -> M bool*) + +definition AArch64_BreakpointMatch :: " int \(64)Word.word \ int \((register_value),(bool),(exception))monad " where + " AArch64_BreakpointMatch n vaddress size1 = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (assert_exp ((\ w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \ + (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \ (\ (w__2 :: 64 bits) . + (assert_exp ((n \ ((Word.uint ((slice0 w__2 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).BRPs))'') \ + read_reg DBGBCR_EL1_ref) \ (\ (w__3 :: ( 32 bits) list) . + (let (enabled :: bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n :: 32 Word.word)) (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (let (ispriv :: bool) = ((ProcState_EL w__4) \ EL0) in + read_reg DBGBCR_EL1_ref \ (\ (w__5 :: ( 32 bits) list) . + (let (linked :: bool) = + (((and_vec ((slice0 ((access_list_dec w__5 n :: 32 Word.word)) (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) + :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)) in + (let (isbreakpnt :: bool) = True in + (let (linked_to :: bool) = False in + read_reg DBGBCR_EL1_ref \ (\ (w__6 :: ( 32 bits) list) . + read_reg DBGBCR_EL1_ref \ (\ (w__7 :: ( 32 bits) list) . + read_reg DBGBCR_EL1_ref \ (\ (w__8 :: ( 32 bits) list) . + read_reg DBGBCR_EL1_ref \ (\ (w__9 :: ( 32 bits) list) . + AArch64_StateMatch ((slice0 ((access_list_dec w__6 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (vec_of_bits [access_vec_dec ((access_list_dec w__7 n :: 32 Word.word)) (( 13 :: int)::ii)] :: 1 Word.word) + ((slice0 ((access_list_dec w__8 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked + ((slice0 ((access_list_dec w__9 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt + ispriv \ (\ (state_match :: bool) . + (let (value_match_name :: bool) = (AArch64_BreakpointValueMatch n vaddress linked_to) in + undefined_bool () \ (\ (match_i :: bool) . + (if (((((HaveAnyAArch32 () )) \ (((size1 = (( 4 :: int)::ii))))))) then + (let match_i = + (AArch64_BreakpointValueMatch n ((add_vec_int vaddress (( 2 :: int)::ii) :: 64 Word.word)) linked_to) in + if (((((\ value_match_name)) \ match_i))) then + ConstrainUnpredictableBool Unpredictable_BPMATCHHALF + else return value_match_name) + else return value_match_name) \ (\ (value_match_name :: bool) . + and_boolM + (return ((((vec_of_bits [access_vec_dec vaddress (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) + (read_reg DBGBCR_EL1_ref \ (\ (w__11 :: ( 32 bits) list) . + return (((((slice0 ((access_list_dec w__11 n :: 32 Word.word)) (( 5 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))))) \ (\ (w__12 :: bool) . + (if w__12 then + if value_match_name then ConstrainUnpredictableBool Unpredictable_BPMATCHHALF + else return value_match_name + else return value_match_name) \ (\ (value_match_name :: bool) . + (let (val_match :: bool) = ((((value_match_name \ state_match))) \ enabled) in + return val_match)))))))))))))))))))))))" + + +(*val AArch64_CheckBreakpoint : mword ty64 -> ii -> M FaultRecord*) + +definition AArch64_CheckBreakpoint :: "(64)Word.word \ int \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckBreakpoint vaddress size1 = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (assert_exp ((\ w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \ + or_boolM + (and_boolM ((UsingAArch32 () )) (return ((((((size1 = (( 2 :: int)::ii)))) \ (((size1 = (( 4 :: int)::ii))))))))) + (return (((size1 = (( 4 :: int)::ii)))))) \ (\ (w__4 :: bool) . + assert_exp w__4 (''((UsingAArch32() && ((size == 2) || (size == 4))) || (size == 4))'') \ + ((let (val_match :: bool) = False in + undefined_bool () \ (\ (match_i :: bool) . + (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__5 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) val_match + (\ i val_match . + AArch64_BreakpointMatch i vaddress size1 \ (\ (w__6 :: bool) . + (let (match_i :: bool) = w__6 in + (let (val_match :: bool) = (val_match \ match_i) in + return val_match))))) \ (\ (val_match :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + undefined_AccType () \ (\ (acctype :: AccType) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (reason :: 6 bits) . + and_boolM (return val_match) ((HaltOnBreakpointOrWatchpoint () )) \ (\ (w__8 :: bool) . + if w__8 then + (let reason = DebugHalt_Breakpoint in + (Halt reason \ undefined_FaultRecord () ) \ (\ (w__9 :: FaultRecord) . return w__9)) + else + and_boolM + (and_boolM (return val_match) + ((read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__10 (( 15 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((AArch64_GenerateDebugExceptions () )) \ (\ (w__13 :: + bool) . + if w__13 then + (let acctype = AccType_IFETCH in + (let iswrite = False in + AArch64_DebugFault acctype iswrite)) + else AArch64_NoFault () ))))))))))))))" + + +(*val AArch64_BranchAddr : mword ty64 -> M (mword ty64)*) + +definition AArch64_BranchAddr :: "(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AArch64_BranchAddr vaddress = ( + UsingAArch32 () \ (\ (w__0 :: bool) . + (assert_exp ((\ w__0)) (''!(UsingAArch32())'') \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + AddrTop vaddress True(ProcState_EL w__1) \ (\ (w__2 :: ii) . + coerce_int_nat w__2 \ (\ (msbit :: ii) . + if (((((ex_nat msbit)) = (( 63 :: int)::ii)))) then return vaddress + else + and_boolM + (or_boolM + (or_boolM + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + return ((((ProcState_EL w__3) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_EL w__4) = EL1)))))) ((IsInHost () ))) + (return ((((vec_of_bits [access_vec_dec vaddress msbit] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) \ (\ (w__8 :: bool) . + return (if w__8 then + (sext_slice (( 64 :: int)::ii) vaddress (( 0 :: int)::ii) ((((ex_nat msbit)) + (( 1 :: int)::ii))) + :: 64 Word.word) + else + (zext_slice (( 64 :: int)::ii) vaddress (( 0 :: int)::ii) ((((ex_nat msbit)) + (( 1 :: int)::ii))) + :: 64 Word.word))))))))" + + +(*val BranchTo : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*) + +definition BranchTo :: "('N::len)Word.word \ BranchType \((register_value),(unit),(exception))monad " where + " BranchTo target branch_type = ( + write_reg BranchTaken_ref True \ + ((let (_ :: unit) = (Hint_Branch branch_type) in + if (((((int (size target))) = (( 32 :: int)::ii)))) then + UsingAArch32 () \ (\ (w__0 :: bool) . + (assert_exp w__0 (''UsingAArch32()'') \ + (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 bits) . + write_reg PC_ref w__1)) + else + and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) + (UsingAArch32 () \ (\ (w__2 :: bool) . return ((\ w__2)))) \ (\ (w__3 :: bool) . + (assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \ + (AArch64_BranchAddr ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M)) \ (\ (w__4 :: 64 + bits) . + write_reg PC_ref w__4)))))" + + +(*val aarch64_branch_unconditional_immediate : BranchType -> mword ty64 -> M unit*) + +definition aarch64_branch_unconditional_immediate :: " BranchType \(64)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_branch_unconditional_immediate branch_type offset = ( + ((if (((branch_type = BranchType_CALL))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + aset_X (( 30 :: int)::ii) ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word))) + else return () ) \ + (aget_PC () :: ( 64 Word.word) M)) \ (\ (w__1 :: 64 Word.word) . + BranchTo ((add_vec w__1 offset :: 64 Word.word)) branch_type))" + + +(*val branch_unconditional_immediate_decode : mword ty1 -> mword ty26 -> M unit*) + +definition branch_unconditional_immediate_decode :: "(1)Word.word \(26)Word.word \((register_value),(unit),(exception))monad " where + " branch_unconditional_immediate_decode op1 imm26 = ( + write_reg unconditional_ref True \ + ((let (branch_type :: BranchType) = + (if (((op1 = (vec_of_bits [B1] :: 1 Word.word)))) then BranchType_CALL + else BranchType_JMP) in + (SignExtend__0 ((concat_vec imm26 (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_branch_unconditional_immediate branch_type offset))))" + + +(*val aarch64_branch_conditional_test : ii -> mword ty1 -> ii -> mword ty64 -> ii -> M unit*) + +definition aarch64_branch_conditional_test :: " int \(1)Word.word \ int \(64)Word.word \ int \((register_value),(unit),(exception))monad " where + " aarch64_branch_conditional_test bit_pos bit_val l__143 offset t = ( + if (((l__143 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (operand :: 8 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] :: 1 Word.word) = bit_val))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + BranchTo ((add_vec w__0 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__143 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (operand :: 16 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] :: 1 Word.word) = bit_val))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + BranchTo ((add_vec w__1 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__143 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (operand :: 32 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] :: 1 Word.word) = bit_val))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + BranchTo ((add_vec w__2 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__143 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (operand :: 64 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] :: 1 Word.word) = bit_val))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + BranchTo ((add_vec w__3 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__143 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (operand :: 128 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] :: 1 Word.word) = bit_val))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + BranchTo ((add_vec w__4 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else + (let dbytes = (ex_int ((l__143 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val branch_conditional_test_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty14 -> mword ty5 -> M unit*) + +definition branch_conditional_test_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(14)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " branch_conditional_test_decode b5 op1 b40 imm14 Rt = ( + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (datasize :: int) = + (if (((b5 = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (bit_pos :: ii) = (Word.uint ((concat_vec b5 b40 :: 6 Word.word))) in + (let (bit_val :: 1 bits) = op1 in + (SignExtend__0 ((concat_vec imm14 (vec_of_bits [B0,B0] :: 2 Word.word) :: 16 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_branch_conditional_test bit_pos bit_val datasize offset t)))))))" + + +(*val aarch64_branch_conditional_cond : mword ty4 -> mword ty64 -> M unit*) + +definition aarch64_branch_conditional_cond :: "(4)Word.word \(64)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_branch_conditional_cond condition offset = ( + ConditionHolds condition \ (\ (w__0 :: bool) . + if w__0 then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + BranchTo ((add_vec w__1 offset :: 64 Word.word)) BranchType_JMP) + else return () ))" + + +(*val branch_conditional_cond_decode : mword ty1 -> mword ty19 -> mword ty1 -> mword ty4 -> M unit*) + +definition branch_conditional_cond_decode :: "(1)Word.word \(19)Word.word \(1)Word.word \(4)Word.word \((register_value),(unit),(exception))monad " where + " branch_conditional_cond_decode o1 imm19 o0 cond = ( + (write_reg unconditional_ref True \ + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (let (condition :: 4 bits) = cond in + aarch64_branch_conditional_cond condition offset)))" + + +(*val aarch64_branch_conditional_compare : ii -> bool -> mword ty64 -> ii -> M unit*) + +definition aarch64_branch_conditional_compare :: " int \ bool \(64)Word.word \ int \((register_value),(unit),(exception))monad " where + " aarch64_branch_conditional_compare l__138 iszero1 offset t = ( + if (((l__138 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + if (((((IsZero operand1)) = iszero1))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + BranchTo ((add_vec w__0 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__138 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + if (((((IsZero operand1)) = iszero1))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + BranchTo ((add_vec w__1 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__138 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + if (((((IsZero operand1)) = iszero1))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + BranchTo ((add_vec w__2 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__138 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + if (((((IsZero operand1)) = iszero1))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + BranchTo ((add_vec w__3 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else if (((l__138 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + if (((((IsZero operand1)) = iszero1))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + BranchTo ((add_vec w__4 offset :: 64 Word.word)) BranchType_JMP) + else return () )) + else + (let dbytes = (ex_int ((l__138 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val branch_conditional_compare_decode : mword ty1 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +definition branch_conditional_compare_decode :: "(1)Word.word \(1)Word.word \(19)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " branch_conditional_compare_decode sf op1 imm19 Rt = ( + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (iszero1 :: bool) = (op1 = (vec_of_bits [B0] :: 1 Word.word)) in + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_branch_conditional_compare datasize iszero1 offset t))))))" + + +(*val AArch64_TakeReset : bool -> M unit*) + +definition AArch64_TakeReset :: " bool \((register_value),(unit),(exception))monad " where + " AArch64_TakeReset cold_reset = ( + (assert_exp ((\ ((HighestELUsingAArch32 () )))) (''!(HighestELUsingAArch32())'') \ + read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + (if ((HaveEL EL3)) then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + write_reg PSTATE_ref (w__1 (| ProcState_EL := EL3 |))) + else if ((HaveEL EL2)) then + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + write_reg PSTATE_ref (w__2 (| ProcState_EL := EL2 |))) + else + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_EL := EL1 |))))) \ + ((let (_ :: unit) = (AArch64_ResetControlRegisters cold_reset) in + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + write_reg PSTATE_ref (w__4 (| ProcState_SP := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + ((let split_vec = ((vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_D := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_A := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + (write_reg PSTATE_ref (w__7 (| ProcState_I := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_F := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + (((write_reg PSTATE_ref (w__10 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + AArch64_ResetGeneralRegisters () ) \ + AArch64_ResetSIMDFPRegisters () ) \ + AArch64_ResetSpecialRegisters () ) \ + ((let (_ :: unit) = (ResetExternalDebugRegisters cold_reset) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (rv :: 64 bits) . + (if ((HaveEL EL3)) then (read_reg RVBAR_EL3_ref :: ( 64 Word.word) M) + else if ((HaveEL EL2)) then (read_reg RVBAR_EL2_ref :: ( 64 Word.word) M) + else (read_reg RVBAR_EL1_ref :: ( 64 Word.word) M)) \ (\ (rv :: 64 bits) . + and_boolM ((IsZero_slice rv ((PAMax () )) (((( 64 :: int)::ii) - ((ex_int ((PAMax () )))))))) + ((IsZero_slice rv (( 0 :: int)::ii) (( 2 :: int)::ii))) \ (\ (w__16 :: bool) . + assert_exp w__16 (''(IsZero((rv)) && IsZero((rv)<0+:((1 - 0) + 1)>))'') \ + BranchTo rv BranchType_UNKNOWN)))))))))))))))))))" + + +(*val __TakeColdReset : unit -> M unit*) + +definition TakeColdReset :: " unit \((register_value),(unit),(exception))monad " where + " TakeColdReset _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (write_reg PSTATE_ref (w__0 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (((write_reg PSTATE_ref (w__1 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + ResetInterruptState () ) \ + ResetMemoryState () ) \ ResetExecuteState () ) \ AArch64_TakeReset True)))" + + +(*val AArch64_TakeException : mword ty2 -> ExceptionRecord -> mword ty64 -> ii -> M unit*) + +definition AArch64_TakeException :: "(2)Word.word \ ExceptionRecord \(64)Word.word \ int \((register_value),(unit),(exception))monad " where + " AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg = ( + (let (vect_offset :: ii) = vect_offset__arg in + (let (_ :: unit) = (SynchronizeContext () ) in + and_boolM + (and_boolM (return ((HaveEL target_el))) + (ELUsingAArch32 target_el \ (\ (w__0 :: bool) . return ((\ w__0))))) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + return ((((Word.uint target_el)) \ ((Word.uint(ProcState_EL w__2))))))) \ (\ (w__3 :: bool) . + (assert_exp w__3 (''((HaveEL(target_el) && !(ELUsingAArch32(target_el))) && (UInt(target_el) >= UInt((PSTATE).EL)))'') \ + UsingAArch32 () ) \ (\ (from_32 :: bool) . + ((if from_32 then AArch64_MaybeZeroRegisterUppers () + else return () ) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (if ((((Word.uint target_el)) > ((Word.uint(ProcState_EL w__4))))) then + undefined_bool () \ (\ (lower_32 :: bool) . + (if (((target_el = EL3))) then + and_boolM (IsSecure () \ (\ (w__5 :: bool) . return ((\ w__5)))) + (return ((HaveEL EL2))) \ (\ (w__6 :: bool) . + if w__6 then ELUsingAArch32 EL2 + else ELUsingAArch32 EL1) + else + and_boolM + (and_boolM ((IsInHost () )) + (read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + return ((((ProcState_EL w__10) = EL0)))))) (return (((target_el = EL2)))) \ (\ (w__12 :: + bool) . + if w__12 then ELUsingAArch32 EL0 + else ELUsingAArch32 ((sub_vec_int target_el (( 1 :: int)::ii) :: 2 Word.word)))) \ (\ (lower_32 :: bool) . + (let (vect_offset :: ii) = (vect_offset + (if lower_32 then (( 1536 :: int)::ii) else (( 1024 :: int)::ii))) in + return vect_offset))) + else + read_reg PSTATE_ref \ (\ (w__15 :: ProcState) . + (let (vect_offset :: ii) = + (if ((((ProcState_SP w__15) = (vec_of_bits [B1] :: 1 Word.word)))) then + ((ex_int vect_offset)) + (( 512 :: int)::ii) + else vect_offset) in + return vect_offset))) \ (\ (vect_offset :: ii) . + (GetPSRFromPSTATE () :: ( 32 Word.word) M) \ (\ (spsr :: 32 bits) . + (((if ((HaveUAOExt () )) then + read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + write_reg PSTATE_ref (w__16 (| ProcState_UAO := ((vec_of_bits [B0] :: 1 Word.word))|))) + else return () ) \ + (if ((\ (((((((ExceptionRecord_typ exception) = Exception_IRQ))) \ ((((ExceptionRecord_typ exception) = Exception_FIQ)))))))) then + AArch64_ReportException exception target_el + else return () )) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_EL := target_el |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + (((write_reg PSTATE_ref (w__19 (| ProcState_SP := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + aset_SPSR spsr) \ + aset_ELR__1 preferred_exception_return) \ + read_reg PSTATE_ref) \ (\ (w__20 :: ProcState) . + write_reg PSTATE_ref (w__20 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + ((let split_vec = ((vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__21 :: ProcState) . + (write_reg PSTATE_ref (w__21 (| ProcState_D := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_A := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg PSTATE_ref (w__23 (| ProcState_I := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + (write_reg PSTATE_ref (w__24 (| ProcState_F := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__25 :: ProcState) . + ((write_reg PSTATE_ref (w__25 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + (if from_32 then + read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + (write_reg + PSTATE_ref + (w__26 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + write_reg PSTATE_ref (w__27 (| ProcState_T := ((vec_of_bits [B0] :: 1 Word.word))|)))) + else return () )) \ + and_boolM + (and_boolM (return ((HavePANExt () ))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__28 :: ProcState) . + return ((((ProcState_EL w__28) = EL1))))) + (and_boolM + (read_reg PSTATE_ref \ (\ (w__29 :: ProcState) . + return ((((ProcState_EL w__29) = EL2))))) ((ELIsInHost EL0))))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__34 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__34 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__35 :: bool) . + ((if w__35 then + read_reg PSTATE_ref \ (\ (w__36 :: ProcState) . + write_reg PSTATE_ref (w__36 (| ProcState_PAN := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + (aget_VBAR__1 () :: ( 64 Word.word) M)) \ (\ (w__37 :: 64 Word.word) . + (BranchTo + ((concat_vec ((slice0 w__37 (( 11 :: int)::ii) (( 53 :: int)::ii) :: 53 Word.word)) + ((GetSlice_int ((make_the_value (( 11 :: int)::ii) :: 11 itself)) vect_offset (( 0 :: int)::ii) :: 11 Word.word)) + :: 64 Word.word)) BranchType_EXCEPTION \ + undefined_bool () ) \ (\ (iesb_req :: bool) . + and_boolM (return ((HaveRASExt () ))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__38 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__38 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__39 :: bool) . + (if w__39 then + (let (_ :: unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in + (let iesb_req = True in + TakeUnmaskedPhysicalSErrorInterrupts iesb_req)) + else return () ) \ + EndOfInstruction () ))))))))))))))))))))))))" + + +(*val TrapPACUse : mword ty2 -> M unit*) + +definition TrapPACUse :: "(2)Word.word \((register_value),(unit),(exception))monad " where + " TrapPACUse target_el = ( + and_boolM (return (((((HaveEL target_el)) \ (((target_el \ EL0))))))) + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + return ((((Word.uint target_el)) \ ((Word.uint(ProcState_EL w__0))))))) \ (\ (w__1 :: bool) . + (assert_exp w__1 (''((HaveEL(target_el) && (target_el != EL0)) && (UInt(target_el) >= UInt((PSTATE).EL)))'') \ + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + undefined_ExceptionRecord () \ (\ (exception :: ExceptionRecord) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_PACTrap \ (\ (w__2 :: ExceptionRecord) . + (let exception = w__2 in + AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))" + + +(*val Strip : mword ty64 -> bool -> M (mword ty64)*) + +definition Strip :: "(64)Word.word \ bool \((register_value),((64)Word.word),(exception))monad " where + " Strip A data = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (original_ptr :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (extfield :: 64 bits) . + CalculateTBI A data \ (\ (tbi :: bool) . + CalculateBottomPACBit A (vec_of_bits [access_vec_dec A (( 55 :: int)::ii)] :: 1 Word.word) \ (\ (w__0 :: ii) . + (let bottom_PAC_bit = (ex_int w__0) in + assert_exp True ('''') \ + ((let extfield = + ((replicate_bits (vec_of_bits [access_vec_dec A (( 55 :: int)::ii)] :: 1 Word.word) (( 64 :: int)::ii) :: 64 Word.word)) in + (let (original_ptr :: 64 bits) = + (if tbi then + (concat_vec ((slice0 A (( 56 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + ((slice_slice_concat (( 56 :: int)::ii) extfield (( 0 :: int)::ii) + ((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit + :: 56 Word.word)) + :: 64 Word.word) + else + (slice_slice_concat (( 64 :: int)::ii) extfield (( 0 :: int)::ii) + ((((- bottom_PAC_bit)) + (( 64 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit + :: 64 Word.word)) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + (case (ProcState_EL w__1) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__2 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__4 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__5 :: bool) . return ((\ w__5))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__7 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__7 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__8 :: bool) . + (let TrapEL2 = w__8 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__9 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__9 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__10 :: bool) . + (let (TrapEL3 :: bool) = w__10 in return (TrapEL2, TrapEL3)))))) + ) \ (\ varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else return original_ptr))))))))))))))" + + +(*val aarch64_integer_pac_strip_dp_1src : ii -> bool -> M unit*) + +definition aarch64_integer_pac_strip_dp_1src :: " int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_strip_dp_1src d data = ( + if ((HavePACExt () )) then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (Strip w__0 data :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . aset_X d w__1)) + else return () )" + + +(*val integer_pac_strip_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition integer_pac_strip_hint_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_strip_hint_decode L op0 op1 CRn CRm op2 Rt = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = ((( 30 :: int)::ii)) in + (let (data :: bool) = False in + aarch64_integer_pac_strip_dp_1src d data))))" + + +(*val AuthIB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AuthIB :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AuthIB X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APIBKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APIBKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APIBKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (Auth X Y APIBKey_EL1 False (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_autib_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_autib_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_autib_dp_1src d n source_is_sp = ( + if ((HavePACExt () )) then + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AuthIB w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthIB w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))) + else return () )" + + +(*val integer_pac_autib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition integer_pac_autib_hint_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autib_hint_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + undefined_int () ) \ (\ (d :: ii) . + undefined_int () \ (\ (n :: ii) . + (let (source_is_sp :: bool) = False in + (let b__0 = ((concat_vec CRm op2 :: 7 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (n :: ii) = ((( 31 :: int)::ii)) in + return (d, n, source_is_sp))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (source_is_sp :: bool) = True in + return (d, n, source_is_sp))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 17 :: int)::ii)) in + (let (n :: ii) = ((( 16 :: int)::ii)) in + return (d, n))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + throw (Error_See (''AUTIA'')) + else throw (Error_See (''XPACLRI''))) \ + return (d, n)) \ (\ varstup . (let ((d :: ii), (n :: ii)) = varstup in + return (d, n, source_is_sp)))) \ (\ varstup . (let ((d :: ii), (n :: ii), (source_is_sp :: bool)) = varstup in + aarch64_integer_pac_autib_dp_1src d n source_is_sp)))))))" + + +(*val AuthIA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AuthIA :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AuthIA X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APIAKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APIAKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APIAKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (Auth X Y APIAKey_EL1 False (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_autia_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_autia_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_autia_dp_1src d n source_is_sp = ( + if ((HavePACExt () )) then + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AuthIA w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthIA w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))) + else return () )" + + +(*val integer_pac_autia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition integer_pac_autia_hint_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autia_hint_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + undefined_int () ) \ (\ (d :: ii) . + undefined_int () \ (\ (n :: ii) . + (let (source_is_sp :: bool) = False in + (let b__0 = ((concat_vec CRm op2 :: 7 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (n :: ii) = ((( 31 :: int)::ii)) in + return (d, n, source_is_sp))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (source_is_sp :: bool) = True in + return (d, n, source_is_sp))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 17 :: int)::ii)) in + (let (n :: ii) = ((( 16 :: int)::ii)) in + return (d, n))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + throw (Error_See (''AUTIB'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1] :: 7 Word.word)))) then + throw (Error_See (''XPACLRI'')) + else throw (Error_See (''HINT''))) \ + return (d, n)) \ (\ varstup . (let ((d :: ii), (n :: ii)) = varstup in + return (d, n, source_is_sp)))) \ (\ varstup . (let ((d :: ii), (n :: ii), (source_is_sp :: bool)) = varstup in + aarch64_integer_pac_autia_dp_1src d n source_is_sp)))))))" + + +(*val aarch64_branch_unconditional_register : BranchType -> ii -> ii -> bool -> bool -> bool -> M unit*) + +definition aarch64_branch_unconditional_register :: " BranchType \ int \ int \ bool \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_branch_unconditional_register branch_type m n pac source_is_sp use_key_a = ( + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (target :: 64 bits) . + (if pac then + (if source_is_sp then (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M)) \ (\ (modifier :: 64 bits) . + if use_key_a then (AuthIA target modifier :: ( 64 Word.word) M) + else (AuthIB target modifier :: ( 64 Word.word) M)) + else return target) \ (\ (target :: 64 bits) . + (if (((branch_type = BranchType_CALL))) then + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + aset_X (( 30 :: int)::ii) ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word))) + else return () ) \ + BranchTo target branch_type)))" + + +(*val AuthDB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AuthDB :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AuthDB X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APDBKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APDBKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APDBKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (Auth X Y APDBKey_EL1 True (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_autdb_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_autdb_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_autdb_dp_1src d n source_is_sp = ( + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AuthDB w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthDB w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))))" + + +(*val AuthDA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AuthDA :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AuthDA X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APDAKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APDAKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APDAKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (Auth X Y APDAKey_EL1 True (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_autda_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_autda_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_autda_dp_1src d n source_is_sp = ( + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AuthDA w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthDA w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))))" + + +(*val AddPACIB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AddPACIB :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AddPACIB X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APIBKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APIBKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APIBKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (AddPAC X Y APIBKey_EL1 False :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_pacib_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_pacib_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_pacib_dp_1src d n source_is_sp = ( + if ((HavePACExt () )) then + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AddPACIB w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AddPACIB w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))) + else return () )" + + +(*val integer_pac_pacib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition integer_pac_pacib_hint_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacib_hint_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + undefined_int () ) \ (\ (d :: ii) . + undefined_int () \ (\ (n :: ii) . + (let (source_is_sp :: bool) = False in + (let b__0 = ((concat_vec CRm op2 :: 7 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (n :: ii) = ((( 31 :: int)::ii)) in + return (d, n, source_is_sp))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (source_is_sp :: bool) = True in + return (d, n, source_is_sp))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 17 :: int)::ii)) in + (let (n :: ii) = ((( 16 :: int)::ii)) in + return (d, n))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIA'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + throw (Error_See (''PACIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + throw (Error_See (''AUTIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + throw (Error_See (''AUTIB'')) + else throw (Error_See (''XPACLRI''))) \ + return (d, n)) \ (\ varstup . (let ((d :: ii), (n :: ii)) = varstup in + return (d, n, source_is_sp)))) \ (\ varstup . (let ((d :: ii), (n :: ii), (source_is_sp :: bool)) = varstup in + aarch64_integer_pac_pacib_dp_1src d n source_is_sp)))))))" + + +(*val AddPACIA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AddPACIA :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AddPACIA X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APIAKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APIAKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APIAKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (AddPAC X Y APIAKey_EL1 False :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_pacia_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_pacia_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_pacia_dp_1src d n source_is_sp = ( + if ((HavePACExt () )) then + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AddPACIA w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AddPACIA w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))) + else return () )" + + +(*val integer_pac_pacia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition integer_pac_pacia_hint_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacia_hint_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + undefined_int () ) \ (\ (d :: ii) . + undefined_int () \ (\ (n :: ii) . + (let (source_is_sp :: bool) = False in + (let b__0 = ((concat_vec CRm op2 :: 7 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (n :: ii) = ((( 31 :: int)::ii)) in + return (d, n, source_is_sp))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B1] :: 7 Word.word)))) then + (let (d :: ii) = ((( 30 :: int)::ii)) in + (let (source_is_sp :: bool) = True in + return (d, n, source_is_sp))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))) then + (let (d :: ii) = ((( 17 :: int)::ii)) in + (let (n :: ii) = ((( 16 :: int)::ii)) in + return (d, n))) + else + (if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIA'')) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B0] :: 7 Word.word)))) then + throw (Error_See (''AUTIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + throw (Error_See (''PACIB'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + throw (Error_See (''AUTIA'')) + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 1 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + throw (Error_See (''AUTIB'')) + else throw (Error_See (''XPACLRI''))) \ + return (d, n)) \ (\ varstup . (let ((d :: ii), (n :: ii)) = varstup in + return (d, n, source_is_sp)))) \ (\ varstup . (let ((d :: ii), (n :: ii), (source_is_sp :: bool)) = varstup in + aarch64_integer_pac_pacia_dp_1src d n source_is_sp)))))))" + + +(*val AddPACGA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AddPACGA :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AddPACGA X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (read_reg APGAKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APGAKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APGAKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__6 :: bool) . return ((\ w__6))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__8 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__8 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__9 :: bool) . + (let TrapEL2 = w__9 in + (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__10 :: 32 bits) . + (let (TrapEL3 :: bool) = + ((vec_of_bits [access_vec_dec w__10 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)) in + return (TrapEL2, TrapEL3)))))) + ) \ (\ varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (ComputePAC X Y ((slice0 APGAKey_EL1 (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 APGAKey_EL1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: ( 64 Word.word) M) \ (\ (w__21 :: 64 Word.word) . + return ((concat_vec ((slice0 w__21 (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 64 Word.word))))))))))))" + + +(*val aarch64_integer_pac_pacga_dp_2src : ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_pacga_dp_2src :: " int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_pacga_dp_2src d m n source_is_sp = ( + if source_is_sp then + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AddPACGA w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AddPACGA w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))))" + + +(*val AddPACDB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AddPACDB :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AddPACDB X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APDBKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APDBKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APDBKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (AddPAC X Y APDBKey_EL1 True :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_pacdb_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_pacdb_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_pacdb_dp_1src d n source_is_sp = ( + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AddPACDB w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AddPACDB w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))))" + + +(*val AddPACDA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +definition AddPACDA :: "(64)Word.word \(64)Word.word \((register_value),((64)Word.word),(exception))monad " where + " AddPACDA X Y = ( + undefined_bool () \ (\ (TrapEL2 :: bool) . + undefined_bool () \ (\ (TrapEL3 :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (Enable :: 1 bits) . + (read_reg APDAKeyHi_EL1_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (read_reg APDAKeyLo_EL1_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (APDAKey_EL1 :: 128 bits) = + ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + :: 128 Word.word)) in + read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + (case (ProcState_EL w__2) of + EL01 => + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__3 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__5 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (IsEL1Regime :: bool) . + ( + if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ + (\ (w__6 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ + (\ (w__7 :: 32 bits) . + return + (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word))) + \ + (\ (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \ IsEL1Regime)))) + (IsSecure () \ + (\ (w__9 :: bool) . return ((\ w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ + (\ (w__11 :: 64 bits) . + return + ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ + (\ (w__13 :: 32 bits) . + return + ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) + = (vec_of_bits [B0] :: 1 Word.word)))))) \ + (\ (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + ) \ (\ varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X + else if TrapEL2 then TrapPACUse EL2 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if TrapEL3 then TrapPACUse EL3 \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (AddPAC X Y APDAKey_EL1 True :: ( 64 Word.word) M)))))))))))" + + +(*val aarch64_integer_pac_pacda_dp_1src : ii -> ii -> bool -> M unit*) + +definition aarch64_integer_pac_pacda_dp_1src :: " int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_integer_pac_pacda_dp_1src d n source_is_sp = ( + if source_is_sp then + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AddPACDA w__0 w__1 :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . aset_X d w__2))) + else + (aget_X (( 64 :: int)::ii) d :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AddPACDA w__3 w__4 :: ( 64 Word.word) M) \ (\ (w__5 :: 64 Word.word) . aset_X d w__5))))" + + +(*val AArch64_WatchpointException : mword ty64 -> FaultRecord -> M unit*) + +definition AArch64_WatchpointException :: "(64)Word.word \ FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_WatchpointException vaddress fault = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((ProcState_EL w__0) \ EL3))) (''((PSTATE).EL != EL3)'') \ + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + return ((((ProcState_EL w__3) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_EL w__4) = EL1))))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))) \ (\ (route_to_el2 :: bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + AArch64_AbortSyndrome Exception_Watchpoint fault vaddress \ (\ (exception :: ExceptionRecord) . + or_boolM + (read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . return ((((ProcState_EL w__10) = EL2))))) + (return route_to_el2) \ (\ (w__11 :: bool) . + if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))" + + +(*val AArch64_WFxTrap : mword ty2 -> bool -> M unit*) + +definition AArch64_WFxTrap :: "(2)Word.word \ bool \((register_value),(unit),(exception))monad " where + " AArch64_WFxTrap target_el is_wfe = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((Word.uint target_el)) > ((Word.uint(ProcState_EL w__0))))) (''(UInt(target_el) > UInt((PSTATE).EL))'') \ + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_WFxTrap \ (\ (exception :: ExceptionRecord) . + (let (tmp_2720 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (ConditionSyndrome () :: ( 5 Word.word) M) \ (\ (w__1 :: 5 Word.word) . + (let tmp_2720 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2720 (( 20 :: int)::ii) w__1 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2720 |))) in + (let (tmp_2730 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2730 = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2730 (( 0 :: int)::ii) + (if is_wfe then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2730 |))) in + and_boolM + (and_boolM (return ((((((target_el = EL1))) \ ((HaveEL EL2)))))) + (IsSecure () \ (\ (w__2 :: bool) . return ((\ w__2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__5 :: bool) . + if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))))))))" + + +(*val AArch64_CheckForWFxTrap : mword ty2 -> bool -> M unit*) + +definition AArch64_CheckForWFxTrap :: "(2)Word.word \ bool \((register_value),(unit),(exception))monad " where + " AArch64_CheckForWFxTrap target_el is_wfe = ( + (assert_exp ((HaveEL target_el)) (''HaveEL(target_el)'') \ + undefined_bool () ) \ (\ (trap :: bool) . + (let pat0 = target_el in + (if (((pat0 = EL1))) then + (if is_wfe then + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + return (vec_of_bits [access_vec_dec w__0 (( 18 :: int)::ii)] :: 1 Word.word)) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + return (vec_of_bits [access_vec_dec w__1 (( 16 :: int)::ii)] :: 1 Word.word))) \ (\ (w__2 :: 1 Word.word) . + (let (trap :: bool) = (w__2 = (vec_of_bits [B0] :: 1 Word.word)) in + return trap)) + else if (((pat0 = EL2))) then + (if is_wfe then + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__3 (( 14 :: int)::ii)] :: 1 Word.word)) + else + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return (vec_of_bits [access_vec_dec w__4 (( 13 :: int)::ii)] :: 1 Word.word))) \ (\ (w__5 :: 1 Word.word) . + (let (trap :: bool) = (w__5 = (vec_of_bits [B1] :: 1 Word.word)) in + return trap)) + else + (if is_wfe then + (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 13 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 12 :: int)::ii)] :: 1 Word.word))) \ (\ (w__8 :: 1 Word.word) . + (let (trap :: bool) = (w__8 = (vec_of_bits [B1] :: 1 Word.word)) in + return trap))) \ (\ (trap :: bool) . + if trap then AArch64_WFxTrap target_el is_wfe + else return () ))))" + + +(*val aarch64_system_hints : SystemHintOp -> M unit*) + +fun aarch64_system_hints :: " SystemHintOp \((register_value),(unit),(exception))monad " where + " aarch64_system_hints SystemHintOp_YIELD = ( return ((Hint_Yield () )))" +|" aarch64_system_hints SystemHintOp_WFE = ( + IsEventRegisterSet () \ (\ (w__0 :: bool) . + if w__0 then ClearEventRegister () + else + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + ((if ((((ProcState_EL w__1) = EL0))) then AArch64_CheckForWFxTrap EL1 True + else return () ) \ + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__2 :: bool) . return ((\ w__2))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_EL w__4) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_EL w__5) = EL1))))))) + (IsInHost () \ (\ (w__8 :: bool) . return ((\ w__8))))) \ (\ (w__9 :: bool) . + ((if w__9 then AArch64_CheckForWFxTrap EL2 True + else return () ) \ + and_boolM (return ((HaveEL EL3))) + (read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + return ((((ProcState_EL w__10) \ EL3)))))) \ (\ (w__11 :: bool) . + (if w__11 then AArch64_CheckForWFxTrap EL3 True else return () ) \ WaitForEvent () )))))" +|" aarch64_system_hints SystemHintOp_WFI = ( + InterruptPending () \ (\ (w__12 :: bool) . + if ((\ w__12)) then + read_reg PSTATE_ref \ (\ (w__13 :: ProcState) . + ((if ((((ProcState_EL w__13) = EL0))) then AArch64_CheckForWFxTrap EL1 False + else return () ) \ + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__14 :: bool) . return ((\ w__14))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__16 :: ProcState) . + return ((((ProcState_EL w__16) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + return ((((ProcState_EL w__17) = EL1))))))) + (IsInHost () \ (\ (w__20 :: bool) . return ((\ w__20))))) \ (\ (w__21 :: bool) . + ((if w__21 then AArch64_CheckForWFxTrap EL2 False + else return () ) \ + and_boolM (return ((HaveEL EL3))) + (read_reg PSTATE_ref \ (\ (w__22 :: ProcState) . + return ((((ProcState_EL w__22) \ EL3)))))) \ (\ (w__23 :: bool) . + (if w__23 then AArch64_CheckForWFxTrap EL3 False else return () ) \ WaitForInterrupt () ))) + else return () ))" +|" aarch64_system_hints SystemHintOp_SEV = ( SendEvent () )" +|" aarch64_system_hints SystemHintOp_SEVL = ( SendEventLocal () )" +|" aarch64_system_hints SystemHintOp_ESB = ( + (let (_ :: unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in + (AArch64_ESBOperation () \ + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__24 :: bool) . return ((\ w__24))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + return ((((ProcState_EL w__26) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__27 :: ProcState) . + return ((((ProcState_EL w__27) = EL1))))))) \ (\ (w__29 :: bool) . + (if w__29 then AArch64_vESBOperation () else return () ) \ TakeUnmaskedSErrorInterrupts () )))" +|" aarch64_system_hints SystemHintOp_PSB = ( return ((ProfilingSynchronizationBarrier () )))" +|" aarch64_system_hints _ = ( return () )" + + +(*val system_hints_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition system_hints_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_hints_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + undefined_SystemHintOp () ) \ (\ (op1 :: SystemHintOp) . + (let b__0 = ((concat_vec CRm op2 :: 7 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) then + return SystemHintOp_NOP + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) then + return SystemHintOp_YIELD + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))) then + return SystemHintOp_WFE + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word)))) then + return SystemHintOp_WFI + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B0,B0] :: 7 Word.word)))) then + return SystemHintOp_SEV + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B0,B1] :: 7 Word.word)))) then + return SystemHintOp_SEVL + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1] :: 7 Word.word)))) then + throw (Error_See (''XPACLRI'')) \ return op1 + else if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 3 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then + throw (Error_See (''PACIA1716, PACIB1716, AUTIA1716, AUTIB1716'')) \ return op1 + else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B0,B0,B0] :: 7 Word.word)))) then + (if ((\ ((HaveRASExt () )))) then EndOfInstruction () + else return () ) \ + return SystemHintOp_ESB + else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B0,B0,B1] :: 7 Word.word)))) then + (if ((\ ((HaveStatisticalProfiling () )))) then EndOfInstruction () + else return () ) \ + return SystemHintOp_PSB + else + (if (((((subrange_vec_dec b__0 (( 6 :: int)::ii) (( 3 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + throw (Error_See (''PACIAZ, PACIASP, PACIBZ, PACIBSP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP'')) + else EndOfInstruction () ) \ + return op1) \ (\ (op1 :: SystemHintOp) . + aarch64_system_hints op1))))" + + +(*val AArch64_VectorCatchException : FaultRecord -> M unit*) + +definition AArch64_VectorCatchException :: " FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_VectorCatchException fault = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((ProcState_EL w__0) \ EL2))) (''((PSTATE).EL != EL2)'') \ + and_boolM + (and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))) \ (\ (w__6 :: bool) . + (assert_exp w__6 ([(CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''a''), (CHR ''v''), (CHR ''e''), (CHR ''E''), (CHR ''L''), (CHR ''(''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''!''), (CHR ''(''), (CHR ''I''), (CHR ''s''), (CHR ''S''), (CHR ''e''), (CHR ''c''), (CHR ''u''), (CHR ''r''), (CHR ''e''), (CHR ''(''), (CHR '')''), (CHR '')''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''G''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''M''), (CHR ''D''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''D''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '')''), (CHR '')'')]) \ + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (vaddress :: 64 bits) . + AArch64_AbortSyndrome Exception_VectorCatch fault vaddress \ (\ (exception :: ExceptionRecord) . + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))" + + +(*val AArch64_UndefinedFault : unit -> M unit*) + +definition AArch64_UndefinedFault :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_UndefinedFault _ = ( + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL0)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (route_to_el2 :: bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_Uncategorized \ (\ (exception :: ExceptionRecord) . + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + if ((((Word.uint(ProcState_EL w__5))) > ((Word.uint EL1)))) then + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + AArch64_TakeException(ProcState_EL w__6) exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))" + + +(*val AArch64_SystemRegisterTrap : mword ty2 -> mword ty2 -> mword ty3 -> mword ty3 -> mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> M unit*) + +definition AArch64_SystemRegisterTrap :: "(2)Word.word \(2)Word.word \(3)Word.word \(3)Word.word \(4)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_SystemRegisterTrap target_el op0 op2 op1 crn rt crm dir = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((Word.uint target_el)) \ ((Word.uint(ProcState_EL w__0))))) (''(UInt(target_el) >= UInt((PSTATE).EL))'') \ + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_SystemRegisterTrap \ (\ (exception :: ExceptionRecord) . + (let (tmp_2800 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2800 = ((set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) tmp_2800 (( 20 :: int)::ii) op0 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2800 |))) in + (let (tmp_2810 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2810 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2810 (( 17 :: int)::ii) op2 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2810 |))) in + (let (tmp_2820 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2820 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2820 (( 14 :: int)::ii) op1 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2820 |))) in + (let (tmp_2830 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2830 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2830 (( 10 :: int)::ii) crn :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2830 |))) in + (let (tmp_2840 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2840 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2840 (( 5 :: int)::ii) rt :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2840 |))) in + (let (tmp_2850 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2850 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2850 (( 1 :: int)::ii) crm :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2850 |))) in + (let (tmp_2860 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2860 = ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2860 (( 0 :: int)::ii) dir :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2860 |))) in + and_boolM + (and_boolM (return ((((((target_el = EL1))) \ ((HaveEL EL2)))))) + (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__4 :: bool) . + if w__4 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))))))))))))))))))))))" + + +(*val AArch64_SoftwareBreakpoint : mword ty16 -> M unit*) + +definition AArch64_SoftwareBreakpoint :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_SoftwareBreakpoint immediate = ( + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . + return ((((ProcState_EL w__2) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + return ((((ProcState_EL w__3) = EL1))))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (route_to_el2 :: bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_SoftwareBreakpoint \ (\ (exception :: ExceptionRecord) . + (let (tmp_2710 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2710 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2710 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2710 |))) in + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + if ((((Word.uint(ProcState_EL w__9))) > ((Word.uint EL1)))) then + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + AArch64_TakeException(ProcState_EL w__10) exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))))" + + +(*val aarch64_system_exceptions_debug_breakpoint : mword ty16 -> M unit*) + +definition aarch64_system_exceptions_debug_breakpoint :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_debug_breakpoint comment = ( AArch64_SoftwareBreakpoint comment )" + + +(*val system_exceptions_debug_breakpoint_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_debug_breakpoint_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_debug_breakpoint_decode opc imm16 op2 LL = ( + write_reg unconditional_ref True \ + ((let (comment :: 16 bits) = imm16 in + aarch64_system_exceptions_debug_breakpoint comment)))" + + +(*val AArch64_SPAlignmentFault : unit -> M unit*) + +definition AArch64_SPAlignmentFault :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_SPAlignmentFault _ = ( + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_SPAlignment \ (\ (exception :: ExceptionRecord) . + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + if ((((Word.uint(ProcState_EL w__0))) > ((Word.uint EL1)))) then + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + AArch64_TakeException(ProcState_EL w__1) exception preferred_exception_return vect_offset) + else + and_boolM + (and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__2 :: bool) . return ((\ w__2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__5 :: bool) . + if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))" + + +(*val CheckSPAlignment : unit -> M unit*) + +definition CheckSPAlignment :: " unit \((register_value),(unit),(exception))monad " where + " CheckSPAlignment _ = ( + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (sp :: 64 bits) . + undefined_bool () \ (\ (stack_align_check :: bool) . + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (if ((((ProcState_EL w__0) = EL0))) then + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (let (stack_align_check :: bool) = + ((vec_of_bits [access_vec_dec w__1 (( 4 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + return stack_align_check)) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (let (stack_align_check :: bool) = + ((vec_of_bits [access_vec_dec w__2 (( 3 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)) in + return stack_align_check))) \ (\ (stack_align_check :: bool) . + if (((stack_align_check \ (((sp \ ((Align__1 sp (( 16 :: int)::ii) :: 64 Word.word)))))))) then + AArch64_SPAlignmentFault () + else return () )))))" + + +(*val AArch64_InstructionAbort : mword ty64 -> FaultRecord -> M unit*) + +definition AArch64_InstructionAbort :: "(64)Word.word \ FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_InstructionAbort vaddress fault = ( + and_boolM + (and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((IsExternalAbort__1 fault)) \ (\ (route_to_el3 :: + bool) . + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__3 :: bool) . return ((\ w__3))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_EL w__5) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + return ((((ProcState_EL w__6) = EL1))))))) + (or_boolM + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) ((IsSecondStage fault))) + (and_boolM + (and_boolM (return ((HaveRASExt () ))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((IsExternalAbort__1 fault)))) \ (\ (route_to_el2 :: + bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + AArch64_AbortSyndrome Exception_InstructionAbort fault vaddress \ (\ (exception :: + ExceptionRecord) . + or_boolM + (read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . return ((((ProcState_EL w__17) = EL3))))) + (return route_to_el3) \ (\ (w__18 :: bool) . + if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else + or_boolM + (read_reg PSTATE_ref \ (\ (w__19 :: ProcState) . return ((((ProcState_EL w__19) = EL2))))) + (return route_to_el2) \ (\ (w__20 :: bool) . + if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))" + + +(*val AArch64_DataAbort : mword ty64 -> FaultRecord -> M unit*) + +definition AArch64_DataAbort :: "(64)Word.word \ FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_DataAbort vaddress fault = ( + and_boolM + (and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((IsExternalAbort__1 fault)) \ (\ (route_to_el3 :: + bool) . + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__3 :: bool) . return ((\ w__3))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_EL w__5) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + return ((((ProcState_EL w__6) = EL1))))))) + (or_boolM + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) ((IsSecondStage fault))) + (and_boolM + (and_boolM (return ((HaveRASExt () ))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 37 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((IsExternalAbort__1 fault)))) \ (\ (route_to_el2 :: + bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + AArch64_AbortSyndrome Exception_DataAbort fault vaddress \ (\ (exception :: ExceptionRecord) . + or_boolM + (read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . return ((((ProcState_EL w__17) = EL3))))) + (return route_to_el3) \ (\ (w__18 :: bool) . + if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else + or_boolM + (read_reg PSTATE_ref \ (\ (w__19 :: ProcState) . return ((((ProcState_EL w__19) = EL2))))) + (return route_to_el2) \ (\ (w__20 :: bool) . + if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))" + + +(*val AArch64_CheckForERetTrap : bool -> bool -> M unit*) + +definition AArch64_CheckForERetTrap :: " bool \ bool \((register_value),(unit),(exception))monad " where + " AArch64_CheckForERetTrap eret_with_pac pac_uses_key_a = ( + and_boolM + (and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL1)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (route_to_el2 :: bool) . + undefined_int () \ (\ (vect_offset :: ii) . + if route_to_el2 then + undefined_ExceptionRecord () \ (\ (exception :: ExceptionRecord) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let vect_offset = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_ERetTrap \ (\ (w__5 :: ExceptionRecord) . + (let exception = w__5 in + (let (tmp_2550 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (ZeroExtend__0 (vec_of_bits [B0] :: 1 Word.word) ((make_the_value (( 23 :: int)::ii) :: 23 itself)) + :: ( 23 Word.word) M) \ (\ (w__6 :: 23 Word.word) . + (let tmp_2550 = ((set_slice0 (( 25 :: int)::ii) (( 23 :: int)::ii) tmp_2550 (( 2 :: int)::ii) w__6 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2550 |))) in + (let (exception :: ExceptionRecord) = + (if ((\ eret_with_pac)) then + (let (tmp_2560 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (tmp_2560 :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2560 (( 1 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in + (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2560 |))) in + (let (tmp_2570 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (tmp_2570 :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2570 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in + (exception (| ExceptionRecord_syndrome := tmp_2570 |))))))) + else + (let (tmp_2580 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (tmp_2580 :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2580 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in + (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2580 |))) in + if pac_uses_key_a then + (let (tmp_2590 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (tmp_2590 :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2590 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) + :: 25 Word.word)) in + (exception (| ExceptionRecord_syndrome := tmp_2590 |)))) + else + (let (tmp_2600 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let (tmp_2600 :: 25 bits) = + ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2600 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + :: 25 Word.word)) in + (exception (| ExceptionRecord_syndrome := tmp_2600 |)))))))) in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))))) + else return () )))" + + +(*val AArch64_CallSupervisor : mword ty16 -> M unit*) + +definition AArch64_CallSupervisor :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_CallSupervisor immediate = ( + UsingAArch32 () \ (\ (w__0 :: bool) . + (((if w__0 then AArch32_ITAdvance () + else return () ) \ + SSAdvance () ) \ + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) = EL0)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (route_to_el2 :: bool) . + (NextInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_SupervisorCall \ (\ (exception :: ExceptionRecord) . + (let (tmp_2770 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2770 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2770 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2770 |))) in + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + if ((((Word.uint(ProcState_EL w__6))) > ((Word.uint EL1)))) then + read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + AArch64_TakeException(ProcState_EL w__7) exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))))" + + +(*val aarch64_system_exceptions_runtime_svc : mword ty16 -> M unit*) + +definition aarch64_system_exceptions_runtime_svc :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_runtime_svc imm = ( AArch64_CallSupervisor imm )" + + +(*val system_exceptions_runtime_svc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_runtime_svc_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_runtime_svc_decode opc imm16 op2 LL = ( + write_reg unconditional_ref True \ + ((let (imm :: 16 bits) = imm16 in + aarch64_system_exceptions_runtime_svc imm)))" + + +(*val AArch64_CallSecureMonitor : mword ty16 -> M unit*) + +definition AArch64_CallSecureMonitor :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_CallSecureMonitor immediate = ( + and_boolM (return ((HaveEL EL3))) + (ELUsingAArch32 EL3 \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: bool) . + (assert_exp w__1 (''(HaveEL(EL3) && !(ELUsingAArch32(EL3)))'') \ + UsingAArch32 () ) \ (\ (w__2 :: bool) . + (((if w__2 then AArch32_ITAdvance () + else return () ) \ + SSAdvance () ) \ + (NextInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_MonitorCall \ (\ (exception :: ExceptionRecord) . + (let (tmp_2930 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2930 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2930 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2930 |))) in + AArch64_TakeException EL3 exception preferred_exception_return vect_offset)))))))))" + + +(*val AArch64_CallHypervisor : mword ty16 -> M unit*) + +definition AArch64_CallHypervisor :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_CallHypervisor immediate = ( + (assert_exp ((HaveEL EL2)) (''HaveEL(EL2)'') \ + UsingAArch32 () ) \ (\ (w__0 :: bool) . + (((if w__0 then AArch32_ITAdvance () + else return () ) \ + SSAdvance () ) \ + (NextInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_HypervisorCall \ (\ (exception :: ExceptionRecord) . + (let (tmp_2890 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_2890 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2890 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2890 |))) in + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + if ((((ProcState_EL w__1) = EL3))) then + AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))))" + + +(*val AArch64_BreakpointException : FaultRecord -> M unit*) + +definition AArch64_BreakpointException :: " FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_BreakpointException fault = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (assert_exp ((((ProcState_EL w__0) \ EL3))) (''((PSTATE).EL != EL3)'') \ + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (or_boolM + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + return ((((ProcState_EL w__3) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + return ((((ProcState_EL w__4) = EL1))))))) + (or_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))) \ (\ (route_to_el2 :: bool) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (vaddress :: 64 bits) . + AArch64_AbortSyndrome Exception_Breakpoint fault vaddress \ (\ (exception :: ExceptionRecord) . + or_boolM + (read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . return ((((ProcState_EL w__10) = EL2))))) + (return route_to_el2) \ (\ (w__11 :: bool) . + if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))" + + +(*val AArch64_Abort : mword ty64 -> FaultRecord -> M unit*) + +definition AArch64_Abort :: "(64)Word.word \ FaultRecord \((register_value),(unit),(exception))monad " where + " AArch64_Abort vaddress fault = ( + IsDebugException fault \ (\ (w__0 :: bool) . + if w__0 then + if ((((FaultRecord_acctype fault) = AccType_IFETCH))) then + and_boolM ((UsingAArch32 () )) + (return ((((FaultRecord_debugmoe fault) = DebugException_VectorCatch)))) \ (\ (w__2 :: + bool) . + if w__2 then AArch64_VectorCatchException fault + else AArch64_BreakpointException fault) + else AArch64_WatchpointException vaddress fault + else if ((((FaultRecord_acctype fault) = AccType_IFETCH))) then + AArch64_InstructionAbort vaddress fault + else AArch64_DataAbort vaddress fault))" + + +(*val AArch64_CheckAlignment : mword ty64 -> ii -> AccType -> bool -> M bool*) + +definition AArch64_CheckAlignment :: "(64)Word.word \ int \ AccType \ bool \((register_value),(bool),(exception))monad " where + " AArch64_CheckAlignment address alignment acctype iswrite = ( + (let (aligned :: bool) = (address = ((Align__1 address alignment :: 64 Word.word))) in + (let (atomic :: bool) = ((((acctype = AccType_ATOMIC))) \ (((acctype = AccType_ATOMICRW)))) in + (let (ordered :: bool) = + ((((acctype = AccType_ORDERED))) \ ((((((acctype = AccType_ORDEREDRW))) \ (((acctype = AccType_LIMITEDORDERED))))))) in + (let (vector_name :: bool) = (acctype = AccType_VEC) in + or_boolM (return (((atomic \ ordered)))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__0 (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (check' :: bool) . + undefined_bool () \ (\ (secondstage :: bool) . + (if (((check' \ ((\ aligned))))) then + (let secondstage = False in + AArch64_AlignmentFault acctype iswrite secondstage \ (\ (w__1 :: FaultRecord) . + AArch64_Abort address w__1)) + else return () ) \ + return aligned)))))))" + + +(*val AArch32_EnterMode : mword ty5 -> mword ty32 -> ii -> ii -> M unit*) + +definition AArch32_EnterMode :: "(5)Word.word \(32)Word.word \ int \ int \((register_value),(unit),(exception))monad " where + " AArch32_EnterMode target_mode preferred_exception_return lr_offset vect_offset = ( + (let (_ :: unit) = (SynchronizeContext () ) in + and_boolM ((ELUsingAArch32 EL1)) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) \ EL2))))) \ (\ (w__2 :: + bool) . + (assert_exp w__2 (''(ELUsingAArch32(EL1) && ((PSTATE).EL != EL2))'') \ + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \ (\ (spsr :: 32 bits) . + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (((((if ((((ProcState_M w__3) = M32_Monitor))) then + (read_reg SCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + write_reg + SCR_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + else return () ) \ + AArch32_WriteMode target_mode) \ + aset_SPSR spsr) \ + aset_R (( 14 :: int)::ii) ((add_vec_int preferred_exception_return lr_offset :: 32 Word.word))) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + (write_reg + PSTATE_ref + (w__5 (| ProcState_T := ((vec_of_bits [access_vec_dec w__6 (( 30 :: int)::ii)] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + ((write_reg PSTATE_ref (w__7 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + (if (((target_mode = M32_FIQ))) then + (let split_vec = ((vec_of_bits [B1,B1,B1] :: 3 Word.word)) in + (let (tup__0, tup__1, tup__2) = + ((subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_A := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_I := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + write_reg PSTATE_ref (w__10 (| ProcState_F := tup__2 |))))))) + else if ((((((target_mode = M32_Abort))) \ (((target_mode = M32_IRQ)))))) then + (let split_vec = ((vec_of_bits [B1,B1] :: 2 Word.word)) in + (let (tup__0, tup__1) = + ((subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_A := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + write_reg PSTATE_ref (w__12 (| ProcState_I := tup__1 |)))))) + else + read_reg PSTATE_ref \ (\ (w__13 :: ProcState) . + write_reg PSTATE_ref (w__13 (| ProcState_I := ((vec_of_bits [B1] :: 1 Word.word))|))))) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + (read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__15 :: 32 bits) . + (write_reg + PSTATE_ref + (w__14 (| ProcState_E := ((vec_of_bits [access_vec_dec w__15 (( 25 :: int)::ii)] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg + PSTATE_ref + (w__17 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \ + and_boolM (return ((HavePANExt () ))) + ((read_reg SCTLR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 23 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__19 :: bool) . + ((if w__19 then + read_reg PSTATE_ref \ (\ (w__20 :: ProcState) . + write_reg PSTATE_ref (w__20 (| ProcState_PAN := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + (ExcVectorBase () :: ( 32 Word.word) M)) \ (\ (w__21 :: 32 Word.word) . + BranchTo + ((concat_vec ((slice0 w__21 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) vect_offset (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word)) BranchType_UNKNOWN \ + EndOfInstruction () ))))))))))))))" + + +(*val AArch64_AdvSIMDFPAccessTrap : mword ty2 -> M unit*) + +definition AArch64_AdvSIMDFPAccessTrap :: "(2)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_AdvSIMDFPAccessTrap target_el = ( + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in + and_boolM + (and_boolM (return ((((((target_el = EL1))) \ ((HaveEL EL2)))))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (route_to_el2 :: bool) . + undefined_ExceptionRecord () \ (\ (exception :: ExceptionRecord) . + if route_to_el2 then + ExceptionSyndrome Exception_Uncategorized \ (\ (w__3 :: ExceptionRecord) . + (let exception = w__3 in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)) + else + ExceptionSyndrome Exception_AdvSIMDFPAccessTrap \ (\ (w__4 :: ExceptionRecord) . + (let exception = w__4 in + (let (tmp_2610 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (ConditionSyndrome () :: ( 5 Word.word) M) \ (\ (w__5 :: 5 Word.word) . + (let tmp_2610 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2610 (( 20 :: int)::ii) w__5 :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2610 |))) in + AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))))))" + + +(*val AArch64_CheckFPAdvSIMDTrap : unit -> M unit*) + +definition AArch64_CheckFPAdvSIMDTrap :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_CheckFPAdvSIMDTrap _ = ( + undefined_bool () \ (\ (disabled :: bool) . + and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: + bool) . + (if w__1 then + and_boolM (return ((HaveVirtHostExt () ))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__3 :: bool) . + if w__3 then + (read_reg CPTR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + (let p__607 = ((slice0 w__4 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let v__94 = p__607 in + (if (((((subrange_vec_dec v__94 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then + and_boolM + (read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + return ((((ProcState_EL w__5) = EL1))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__7 :: bool) . + (let (disabled :: bool) = (\ w__7) in + return disabled)) + else if (((v__94 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + and_boolM + (read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + return ((((ProcState_EL w__8) = EL0))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__9 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + else return False) \ (\ (disabled :: bool) . + if disabled then AArch64_AdvSIMDFPAccessTrap EL2 + else return () )))) + else + (read_reg CPTR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__11 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__11 (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + AArch64_AdvSIMDFPAccessTrap EL2 + else return () )) + else return () ) \ + (if ((HaveEL EL3)) then + (read_reg CPTR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__12 (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + AArch64_AdvSIMDFPAccessTrap EL3 + else return () ) + else return () ))))" + + +(*val AArch64_CheckFPAdvSIMDEnabled : unit -> M unit*) + +definition AArch64_CheckFPAdvSIMDEnabled :: " unit \((register_value),(unit),(exception))monad " where + " AArch64_CheckFPAdvSIMDEnabled _ = ( + undefined_bool () \ (\ (disabled :: bool) . + or_boolM + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) = EL1))))) \ (\ (w__2 :: + bool) . + (if w__2 then + (aget_CPACR () :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (let p__606 = ((slice0 w__3 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let v__96 = p__606 in + (if (((((subrange_vec_dec v__96 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then + return True + else if (((v__96 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + (let (disabled :: bool) = ((ProcState_EL w__4) = EL0) in + return disabled)) + else return False) \ (\ (disabled :: bool) . + if disabled then AArch64_AdvSIMDFPAccessTrap EL1 + else return () )))) + else return () ) \ + AArch64_CheckFPAdvSIMDTrap () )))" + + +(*val CheckFPAdvSIMDEnabled64 : unit -> M unit*) + +definition CheckFPAdvSIMDEnabled64 :: " unit \((register_value),(unit),(exception))monad " where + " CheckFPAdvSIMDEnabled64 _ = ( AArch64_CheckFPAdvSIMDEnabled () )" + + +(*val aarch64_float_move_fp_select : mword ty4 -> ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_float_move_fp_select :: "(4)Word.word \ int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_float_move_fp_select condition d l__133 m n = ( + if (((l__133 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + ConditionHolds condition) \ (\ (w__0 :: bool) . + (if w__0 then (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) + else (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + aset_V d result))) + else if (((l__133 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + ConditionHolds condition) \ (\ (w__3 :: bool) . + (if w__3 then (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) + else (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + aset_V d result))) + else if (((l__133 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + ConditionHolds condition) \ (\ (w__6 :: bool) . + (if w__6 then (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) + else (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + aset_V d result))) + else if (((l__133 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + ConditionHolds condition) \ (\ (w__9 :: bool) . + (if w__9 then (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) + else (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + aset_V d result))) + else if (((l__133 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + ConditionHolds condition) \ (\ (w__12 :: bool) . + (if w__12 then (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) + else (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + aset_V d result))) + else + (let dbytes = (ex_int ((l__133 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_move_fp_imm : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> M unit*) + +definition aarch64_float_move_fp_imm :: " int \('datasize::len)itself \('datasize::len)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_float_move_fp_imm d datasize imm = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ CheckFPAdvSIMDEnabled64 () ) \ aset_V d imm)))" + + +(*val aarch64_float_convert_int : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> itself 'intsize -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*) + +definition aarch64_float_convert_int :: " int \('fltsize::len)itself \('intsize::len)itself \ int \ FPConvOp \ int \ FPRounding \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_convert_int d fltsize intsize n op1 part rounding unsigned = ( + (let intsize = (size_itself_int intsize) in + (let fltsize = (size_itself_int fltsize) in + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \ (\ (fltval :: 'fltsize bits) . + (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \ (\ (intval :: 'intsize bits) . + (case op1 of + FPConvOp_CVT_FtoI => + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \ (\ (w__0 :: 'fltsize bits) . + (let fltval = w__0 in + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (FPToFixed intsize fltval (( 0 :: int)::ii) unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \ (\ (w__2 :: 'intsize + bits) . + (let intval = w__2 in + aset_X d intval))))) + | FPConvOp_CVT_ItoF => + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \ (\ (w__3 :: 'intsize bits) . + (let intval = w__3 in + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FixedToFP fltsize intval (( 0 :: int)::ii) unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \ (\ (w__5 :: 'fltsize + bits) . + (let fltval = w__5 in + aset_V d fltval))))) + | FPConvOp_MOV_FtoI => + (aget_Vpart fltsize n part :: (( 'fltsize::len)Word.word) M) \ (\ (w__6 :: 'fltsize bits) . + (let fltval = w__6 in + (ZeroExtend__0 fltval ((make_the_value intsize :: ( 'intsize::len)itself)) :: (( 'intsize::len)Word.word) M) \ (\ (w__7 :: 'intsize + bits) . + (let intval = w__7 in + aset_X d intval)))) + | FPConvOp_MOV_ItoF => + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \ (\ (w__8 :: 'intsize bits) . + (let intval = w__8 in + (let fltval = ((slice0 intval (( 0 :: int)::ii) fltsize :: ( 'fltsize::len)Word.word)) in + aset_Vpart d part fltval))) + | FPConvOp_CVT_FtoI_JS => + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \ (\ (w__9 :: 'fltsize bits) . + (let fltval = w__9 in + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + (FPToFixedJS intsize fltval w__10 True :: (( 'intsize::len)Word.word) M) \ (\ (w__11 :: 'intsize bits) . + (let intval = w__11 in + (ZeroExtend__0 ((slice0 intval (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__12 :: 64 Word.word) . + aset_X d w__12)))))) + ))))))" + + +(*val aarch64_float_convert_fp : forall 'dstsize 'srcsize . Size 'dstsize, Size 'srcsize => ii -> itself 'dstsize -> ii -> itself 'srcsize -> M unit*) + +definition aarch64_float_convert_fp :: " int \('dstsize::len)itself \ int \('srcsize::len)itself \((register_value),(unit),(exception))monad " where + " aarch64_float_convert_fp d dstsize n srcsize = ( + (let srcsize = (size_itself_int srcsize) in + (let dstsize = (size_itself_int dstsize) in + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector dstsize :: (( 'dstsize::len)Word.word) M)) \ (\ (result :: 'dstsize bits) . + (aget_V srcsize n :: (( 'srcsize::len)Word.word) M) \ (\ (operand :: 'srcsize bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPConvert__1 dstsize operand w__0 :: (( 'dstsize::len)Word.word) M) \ (\ (w__1 :: 'dstsize bits) . + (let result = w__1 in + aset_V d result))))))))" + + +(*val aarch64_float_convert_fix : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> ii -> itself 'intsize -> ii -> FPConvOp -> FPRounding -> bool -> M unit*) + +definition aarch64_float_convert_fix :: " int \('fltsize::len)itself \ int \('intsize::len)itself \ int \ FPConvOp \ FPRounding \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_convert_fix d fltsize fracbits intsize n op1 rounding unsigned = ( + (let intsize = (size_itself_int intsize) in + (let fltsize = (size_itself_int fltsize) in + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \ (\ (fltval :: 'fltsize bits) . + (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \ (\ (intval :: 'intsize bits) . + (case op1 of + FPConvOp_CVT_FtoI => + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \ (\ (w__0 :: 'fltsize bits) . + (let fltval = w__0 in + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (FPToFixed intsize fltval fracbits unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \ (\ (w__2 :: 'intsize + bits) . + (let intval = w__2 in + aset_X d intval))))) + | FPConvOp_CVT_ItoF => + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \ (\ (w__3 :: 'intsize bits) . + (let intval = w__3 in + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FixedToFP fltsize intval fracbits unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \ (\ (w__5 :: 'fltsize + bits) . + (let fltval = w__5 in + aset_V d fltval))))) + ))))))" + + +(*val aarch64_float_compare_uncond : bool -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_float_compare_uncond :: " bool \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_compare_uncond cmp_with_zero l__128 m n signal_all_nans = ( + if (((l__128 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (if cmp_with_zero then (FPZero (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 8 Word.word) M) + else (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M)) \ (\ (operand2 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__2 :: ( 4 Word.word) M) \ (\ split_vec . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + write_reg PSTATE_ref (w__6 (| ProcState_V := tup__3 |)))))))))))) + else if (((l__128 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (if cmp_with_zero then (FPZero (( 16 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 16 Word.word) M) + else (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M)) \ (\ (operand2 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__9 :: ( 4 Word.word) M) \ (\ split_vec . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + write_reg PSTATE_ref (w__13 (| ProcState_V := tup__3 |)))))))))))) + else if (((l__128 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (if cmp_with_zero then (FPZero (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 32 Word.word) M) + else (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M)) \ (\ (operand2 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__16 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__16 :: ( 4 Word.word) M) \ (\ split_vec . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + (write_reg PSTATE_ref (w__19 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__20 :: ProcState) . + write_reg PSTATE_ref (w__20 (| ProcState_V := tup__3 |)))))))))))) + else if (((l__128 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (if cmp_with_zero then (FPZero (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M) + else (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M)) \ (\ (operand2 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__23 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__23 :: ( 4 Word.word) M) \ (\ split_vec . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__24 :: ProcState) . + (write_reg PSTATE_ref (w__24 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__25 :: ProcState) . + (write_reg PSTATE_ref (w__25 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + write_reg PSTATE_ref (w__27 (| ProcState_V := tup__3 |)))))))))))) + else if (((l__128 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (if cmp_with_zero then (FPZero (( 128 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 128 Word.word) M) + else (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M)) \ (\ (operand2 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__30 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__30 :: ( 4 Word.word) M) \ (\ split_vec . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__31 :: ProcState) . + (write_reg PSTATE_ref (w__31 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__32 :: ProcState) . + (write_reg PSTATE_ref (w__32 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__33 :: ProcState) . + (write_reg PSTATE_ref (w__33 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__34 :: ProcState) . + write_reg PSTATE_ref (w__34 (| ProcState_V := tup__3 |)))))))))))) + else + (let dbytes = (ex_int ((l__128 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_compare_cond : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*) + +definition aarch64_float_compare_cond :: "(4)Word.word \ int \(4)Word.word \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_compare_cond condition l__123 flags__arg m n signal_all_nans = ( + if (((l__123 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (CheckFPAdvSIMDEnabled64 () \ + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + ConditionHolds condition \ (\ (w__0 :: bool) . + (if w__0 then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__1 :: ( 4 Word.word) M)) + else return flags) \ (\ (flags :: 4 Word.word) . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + write_reg PSTATE_ref (w__6 (| ProcState_V := tup__3 |)))))))))))))) + else if (((l__123 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (CheckFPAdvSIMDEnabled64 () \ + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + ConditionHolds condition \ (\ (w__7 :: bool) . + (if w__7 then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__8 :: ( 4 Word.word) M)) + else return flags) \ (\ (flags :: 4 Word.word) . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + write_reg PSTATE_ref (w__13 (| ProcState_V := tup__3 |)))))))))))))) + else if (((l__123 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (CheckFPAdvSIMDEnabled64 () \ + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + ConditionHolds condition \ (\ (w__14 :: bool) . + (if w__14 then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__15 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__15 :: ( 4 Word.word) M)) + else return flags) \ (\ (flags :: 4 Word.word) . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + (write_reg PSTATE_ref (w__17 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + (write_reg PSTATE_ref (w__19 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__20 :: ProcState) . + write_reg PSTATE_ref (w__20 (| ProcState_V := tup__3 |)))))))))))))) + else if (((l__123 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (CheckFPAdvSIMDEnabled64 () \ + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + ConditionHolds condition \ (\ (w__21 :: bool) . + (if w__21 then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__22 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__22 :: ( 4 Word.word) M)) + else return flags) \ (\ (flags :: 4 Word.word) . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__24 :: ProcState) . + (write_reg PSTATE_ref (w__24 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__25 :: ProcState) . + (write_reg PSTATE_ref (w__25 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + write_reg PSTATE_ref (w__27 (| ProcState_V := tup__3 |)))))))))))))) + else if (((l__123 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let flags = flags__arg in + (CheckFPAdvSIMDEnabled64 () \ + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + ConditionHolds condition \ (\ (w__28 :: bool) . + (if w__28 then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__29 :: 32 Word.word) . + (FPCompare operand1 operand2 signal_all_nans w__29 :: ( 4 Word.word) M)) + else return flags) \ (\ (flags :: 4 Word.word) . + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec flags (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__31 :: ProcState) . + (write_reg PSTATE_ref (w__31 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__32 :: ProcState) . + (write_reg PSTATE_ref (w__32 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__33 :: ProcState) . + (write_reg PSTATE_ref (w__33 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__34 :: ProcState) . + write_reg PSTATE_ref (w__34 (| ProcState_V := tup__3 |)))))))))))))) + else + (let dbytes = (ex_int ((l__123 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_unary : ii -> ii -> FPUnaryOp -> ii -> M unit*) + +definition aarch64_float_arithmetic_unary :: " int \ int \ FPUnaryOp \ int \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_unary d l__118 fpop n = ( + if (((l__118 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand :: 8 bits) . + (case fpop of + FPUnaryOp_MOV => return operand + | FPUnaryOp_ABS => (FPAbs operand :: ( 8 Word.word) M) + | FPUnaryOp_NEG => (FPNeg operand :: ( 8 Word.word) M) + | FPUnaryOp_SQRT => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPSqrt operand w__2 :: ( 8 Word.word) M)) + ) \ (\ (result :: 8 bits) . + aset_V d result)))) + else if (((l__118 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand :: 16 bits) . + (case fpop of + FPUnaryOp_MOV => return operand + | FPUnaryOp_ABS => (FPAbs operand :: ( 16 Word.word) M) + | FPUnaryOp_NEG => (FPNeg operand :: ( 16 Word.word) M) + | FPUnaryOp_SQRT => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPSqrt operand w__6 :: ( 16 Word.word) M)) + ) \ (\ (result :: 16 bits) . + aset_V d result)))) + else if (((l__118 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand :: 32 bits) . + (case fpop of + FPUnaryOp_MOV => return operand + | FPUnaryOp_ABS => (FPAbs operand :: ( 32 Word.word) M) + | FPUnaryOp_NEG => (FPNeg operand :: ( 32 Word.word) M) + | FPUnaryOp_SQRT => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + (FPSqrt operand w__10 :: ( 32 Word.word) M)) + ) \ (\ (result :: 32 bits) . + aset_V d result)))) + else if (((l__118 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand :: 64 bits) . + (case fpop of + FPUnaryOp_MOV => return operand + | FPUnaryOp_ABS => (FPAbs operand :: ( 64 Word.word) M) + | FPUnaryOp_NEG => (FPNeg operand :: ( 64 Word.word) M) + | FPUnaryOp_SQRT => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 Word.word) . + (FPSqrt operand w__14 :: ( 64 Word.word) M)) + ) \ (\ (result :: 64 bits) . + aset_V d result)))) + else if (((l__118 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand :: 128 bits) . + (case fpop of + FPUnaryOp_MOV => return operand + | FPUnaryOp_ABS => (FPAbs operand :: ( 128 Word.word) M) + | FPUnaryOp_NEG => (FPNeg operand :: ( 128 Word.word) M) + | FPUnaryOp_SQRT => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + (FPSqrt operand w__18 :: ( 128 Word.word) M)) + ) \ (\ (result :: 128 bits) . + aset_V d result)))) + else + (let dbytes = (ex_int ((l__118 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_round : ii -> ii -> bool -> ii -> FPRounding -> M unit*) + +definition aarch64_float_arithmetic_round :: " int \ int \ bool \ int \ FPRounding \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_round d l__113 exact n rounding = ( + if (((l__113 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPRoundInt operand w__0 rounding exact :: ( 8 Word.word) M) \ (\ (w__1 :: 8 bits) . + (let result = w__1 in + aset_V d result)))))) + else if (((l__113 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPRoundInt operand w__2 rounding exact :: ( 16 Word.word) M) \ (\ (w__3 :: 16 bits) . + (let result = w__3 in + aset_V d result)))))) + else if (((l__113 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FPRoundInt operand w__4 rounding exact :: ( 32 Word.word) M) \ (\ (w__5 :: 32 bits) . + (let result = w__5 in + aset_V d result)))))) + else if (((l__113 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPRoundInt operand w__6 rounding exact :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + (let result = w__7 in + aset_V d result)))))) + else if (((l__113 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (FPRoundInt operand w__8 rounding exact :: ( 128 Word.word) M) \ (\ (w__9 :: 128 bits) . + (let result = w__9 in + aset_V d result)))))) + else + (let dbytes = (ex_int ((l__113 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_mul_product : ii -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_float_arithmetic_mul_product :: " int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_mul_product d l__108 m n negated = ( + if (((l__108 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPMul operand1 operand2 w__0 :: ( 8 Word.word) M) \ (\ (w__1 :: 8 bits) . + (let result = w__1 in + (if negated then (FPNeg result :: ( 8 Word.word) M) + else return result) \ (\ (result :: 8 bits) . + aset_V d result)))))))) + else if (((l__108 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (FPMul operand1 operand2 w__3 :: ( 16 Word.word) M) \ (\ (w__4 :: 16 bits) . + (let result = w__4 in + (if negated then (FPNeg result :: ( 16 Word.word) M) + else return result) \ (\ (result :: 16 bits) . + aset_V d result)))))))) + else if (((l__108 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPMul operand1 operand2 w__6 :: ( 32 Word.word) M) \ (\ (w__7 :: 32 bits) . + (let result = w__7 in + (if negated then (FPNeg result :: ( 32 Word.word) M) + else return result) \ (\ (result :: 32 bits) . + aset_V d result)))))))) + else if (((l__108 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + (FPMul operand1 operand2 w__9 :: ( 64 Word.word) M) \ (\ (w__10 :: 64 bits) . + (let result = w__10 in + (if negated then (FPNeg result :: ( 64 Word.word) M) + else return result) \ (\ (result :: 64 bits) . + aset_V d result)))))))) + else if (((l__108 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + (FPMul operand1 operand2 w__12 :: ( 128 Word.word) M) \ (\ (w__13 :: 128 bits) . + (let result = w__13 in + (if negated then (FPNeg result :: ( 128 Word.word) M) + else return result) \ (\ (result :: 128 bits) . + aset_V d result)))))))) + else + (let dbytes = (ex_int ((l__108 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_mul_addsub : ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +definition aarch64_float_arithmetic_mul_addsub :: " int \ int \ int \ int \ int \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_mul_addsub a d l__103 m n op1_neg opa_neg = ( + if (((l__103 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) a :: ( 8 Word.word) M) \ (\ (operanda :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (if opa_neg then (FPNeg operanda :: ( 8 Word.word) M) + else return operanda) \ (\ (operanda :: 8 bits) . + (if op1_neg then (FPNeg operand1 :: ( 8 Word.word) M) + else return operand1) \ (\ (operand1 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPMulAdd operanda operand1 operand2 w__2 :: ( 8 Word.word) M) \ (\ (w__3 :: 8 bits) . + (let result = w__3 in + aset_V d result)))))))))) + else if (((l__103 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) a :: ( 16 Word.word) M) \ (\ (operanda :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (if opa_neg then (FPNeg operanda :: ( 16 Word.word) M) + else return operanda) \ (\ (operanda :: 16 bits) . + (if op1_neg then (FPNeg operand1 :: ( 16 Word.word) M) + else return operand1) \ (\ (operand1 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPMulAdd operanda operand1 operand2 w__6 :: ( 16 Word.word) M) \ (\ (w__7 :: 16 bits) . + (let result = w__7 in + aset_V d result)))))))))) + else if (((l__103 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) a :: ( 32 Word.word) M) \ (\ (operanda :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (if opa_neg then (FPNeg operanda :: ( 32 Word.word) M) + else return operanda) \ (\ (operanda :: 32 bits) . + (if op1_neg then (FPNeg operand1 :: ( 32 Word.word) M) + else return operand1) \ (\ (operand1 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + (FPMulAdd operanda operand1 operand2 w__10 :: ( 32 Word.word) M) \ (\ (w__11 :: 32 bits) . + (let result = w__11 in + aset_V d result)))))))))) + else if (((l__103 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) a :: ( 64 Word.word) M) \ (\ (operanda :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (if opa_neg then (FPNeg operanda :: ( 64 Word.word) M) + else return operanda) \ (\ (operanda :: 64 bits) . + (if op1_neg then (FPNeg operand1 :: ( 64 Word.word) M) + else return operand1) \ (\ (operand1 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 Word.word) . + (FPMulAdd operanda operand1 operand2 w__14 :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + (let result = w__15 in + aset_V d result)))))))))) + else if (((l__103 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) a :: ( 128 Word.word) M) \ (\ (operanda :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (if opa_neg then (FPNeg operanda :: ( 128 Word.word) M) + else return operanda) \ (\ (operanda :: 128 bits) . + (if op1_neg then (FPNeg operand1 :: ( 128 Word.word) M) + else return operand1) \ (\ (operand1 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + (FPMulAdd operanda operand1 operand2 w__18 :: ( 128 Word.word) M) \ (\ (w__19 :: 128 bits) . + (let result = w__19 in + aset_V d result)))))))))) + else + (let dbytes = (ex_int ((l__103 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_maxmin : ii -> ii -> ii -> ii -> FPMaxMinOp -> M unit*) + +definition aarch64_float_arithmetic_maxmin :: " int \ int \ int \ int \ FPMaxMinOp \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_maxmin d l__98 m n operation = ( + if (((l__98 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (case operation of + FPMaxMinOp_MAX => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPMax operand1 operand2 w__0 :: ( 8 Word.word) M)) + | FPMaxMinOp_MIN => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPMin operand1 operand2 w__2 :: ( 8 Word.word) M)) + | FPMaxMinOp_MAXNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FPMaxNum operand1 operand2 w__4 :: ( 8 Word.word) M)) + | FPMaxMinOp_MINNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPMinNum operand1 operand2 w__6 :: ( 8 Word.word) M)) + ) \ (\ (result :: 8 bits) . + aset_V d result))))) + else if (((l__98 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (case operation of + FPMaxMinOp_MAX => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (FPMax operand1 operand2 w__8 :: ( 16 Word.word) M)) + | FPMaxMinOp_MIN => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + (FPMin operand1 operand2 w__10 :: ( 16 Word.word) M)) + | FPMaxMinOp_MAXNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + (FPMaxNum operand1 operand2 w__12 :: ( 16 Word.word) M)) + | FPMaxMinOp_MINNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 Word.word) . + (FPMinNum operand1 operand2 w__14 :: ( 16 Word.word) M)) + ) \ (\ (result :: 16 bits) . + aset_V d result))))) + else if (((l__98 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (case operation of + FPMaxMinOp_MAX => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__16 :: 32 Word.word) . + (FPMax operand1 operand2 w__16 :: ( 32 Word.word) M)) + | FPMaxMinOp_MIN => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + (FPMin operand1 operand2 w__18 :: ( 32 Word.word) M)) + | FPMaxMinOp_MAXNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__20 :: 32 Word.word) . + (FPMaxNum operand1 operand2 w__20 :: ( 32 Word.word) M)) + | FPMaxMinOp_MINNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__22 :: 32 Word.word) . + (FPMinNum operand1 operand2 w__22 :: ( 32 Word.word) M)) + ) \ (\ (result :: 32 bits) . + aset_V d result))))) + else if (((l__98 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (case operation of + FPMaxMinOp_MAX => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__24 :: 32 Word.word) . + (FPMax operand1 operand2 w__24 :: ( 64 Word.word) M)) + | FPMaxMinOp_MIN => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__26 :: 32 Word.word) . + (FPMin operand1 operand2 w__26 :: ( 64 Word.word) M)) + | FPMaxMinOp_MAXNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__28 :: 32 Word.word) . + (FPMaxNum operand1 operand2 w__28 :: ( 64 Word.word) M)) + | FPMaxMinOp_MINNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__30 :: 32 Word.word) . + (FPMinNum operand1 operand2 w__30 :: ( 64 Word.word) M)) + ) \ (\ (result :: 64 bits) . + aset_V d result))))) + else if (((l__98 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (case operation of + FPMaxMinOp_MAX => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__32 :: 32 Word.word) . + (FPMax operand1 operand2 w__32 :: ( 128 Word.word) M)) + | FPMaxMinOp_MIN => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__34 :: 32 Word.word) . + (FPMin operand1 operand2 w__34 :: ( 128 Word.word) M)) + | FPMaxMinOp_MAXNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__36 :: 32 Word.word) . + (FPMaxNum operand1 operand2 w__36 :: ( 128 Word.word) M)) + | FPMaxMinOp_MINNUM => + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__38 :: 32 Word.word) . + (FPMinNum operand1 operand2 w__38 :: ( 128 Word.word) M)) + ) \ (\ (result :: 128 bits) . + aset_V d result))))) + else + (let dbytes = (ex_int ((l__98 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_div : ii -> ii -> ii -> ii -> M unit*) + +definition aarch64_float_arithmetic_div :: " int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_div d l__93 m n = ( + if (((l__93 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPDiv operand1 operand2 w__0 :: ( 8 Word.word) M) \ (\ (w__1 :: 8 bits) . + (let result = w__1 in + aset_V d result))))))) + else if (((l__93 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPDiv operand1 operand2 w__2 :: ( 16 Word.word) M) \ (\ (w__3 :: 16 bits) . + (let result = w__3 in + aset_V d result))))))) + else if (((l__93 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FPDiv operand1 operand2 w__4 :: ( 32 Word.word) M) \ (\ (w__5 :: 32 bits) . + (let result = w__5 in + aset_V d result))))))) + else if (((l__93 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPDiv operand1 operand2 w__6 :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + (let result = w__7 in + aset_V d result))))))) + else if (((l__93 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (FPDiv operand1 operand2 w__8 :: ( 128 Word.word) M) \ (\ (w__9 :: 128 bits) . + (let result = w__9 in + aset_V d result))))))) + else + (let dbytes = (ex_int ((l__93 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_float_arithmetic_addsub : ii -> ii -> ii -> ii -> bool -> M unit*) + +definition aarch64_float_arithmetic_addsub :: " int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_arithmetic_addsub d l__88 m n sub_op = ( + if (((l__88 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \ (\ (result :: 8 bits) . + (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \ (\ (operand1 :: 8 bits) . + (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (operand2 :: 8 bits) . + (if sub_op then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (FPSub operand1 operand2 w__0 :: ( 8 Word.word) M)) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (FPAdd operand1 operand2 w__2 :: ( 8 Word.word) M))) \ (\ (result :: 8 bits) . + aset_V d result))))) + else if (((l__88 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \ (\ (result :: 16 bits) . + (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \ (\ (operand1 :: 16 bits) . + (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (operand2 :: 16 bits) . + (if sub_op then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (FPSub operand1 operand2 w__4 :: ( 16 Word.word) M)) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (FPAdd operand1 operand2 w__6 :: ( 16 Word.word) M))) \ (\ (result :: 16 bits) . + aset_V d result))))) + else if (((l__88 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (result :: 32 bits) . + (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \ (\ (operand1 :: 32 bits) . + (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (operand2 :: 32 bits) . + (if sub_op then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (FPSub operand1 operand2 w__8 :: ( 32 Word.word) M)) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + (FPAdd operand1 operand2 w__10 :: ( 32 Word.word) M))) \ (\ (result :: 32 bits) . + aset_V d result))))) + else if (((l__88 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (result :: 64 bits) . + (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \ (\ (operand1 :: 64 bits) . + (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (operand2 :: 64 bits) . + (if sub_op then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + (FPSub operand1 operand2 w__12 :: ( 64 Word.word) M)) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 Word.word) . + (FPAdd operand1 operand2 w__14 :: ( 64 Word.word) M))) \ (\ (result :: 64 bits) . + aset_V d result))))) + else if (((l__88 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (result :: 128 bits) . + (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \ (\ (operand1 :: 128 bits) . + (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \ (\ (operand2 :: 128 bits) . + (if sub_op then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__16 :: 32 Word.word) . + (FPSub operand1 operand2 w__16 :: ( 128 Word.word) M)) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__18 :: 32 Word.word) . + (FPAdd operand1 operand2 w__18 :: ( 128 Word.word) M))) \ (\ (result :: 128 bits) . + aset_V d result))))) + else + (let dbytes = (ex_int ((l__88 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val AArch64_AccessIsPrivileged : AccType -> M bool*) + +definition AArch64_AccessIsPrivileged :: " AccType \((register_value),(bool),(exception))monad " where + " AArch64_AccessIsPrivileged acctype = ( + undefined_bool () \ (\ (ispriv :: bool) . + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + if ((((ProcState_EL w__0) = EL0))) then return False + else + read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . + if ((((ProcState_EL w__1) = EL3))) then return True + else + and_boolM + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL2))))) + (or_boolM (IsInHost () \ (\ (w__3 :: bool) . return ((\ w__3)))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__6 :: bool) . + if w__6 then return True + else + and_boolM (return ((HaveUAOExt () ))) + (read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + return ((((ProcState_UAO w__7) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__8 :: + bool) . + (let (ispriv :: bool) = (if w__8 then True else (acctype \ AccType_UNPRIV)) in + return ispriv)))))))" + + +(*val AArch64_CheckWatchpoint : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*) + +definition AArch64_CheckWatchpoint :: "(64)Word.word \ AccType \ bool \ int \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckWatchpoint vaddress acctype iswrite size1 = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + assert_exp ((\ w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \ + ((let (val_match :: bool) = False in + AArch64_AccessIsPrivileged acctype \ (\ (ispriv :: bool) . + (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) val_match + (\ i val_match . + or_boolM (return val_match) ((AArch64_WatchpointMatch i vaddress size1 ispriv iswrite)))) \ (\ (val_match :: + bool) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (reason :: 6 bits) . + and_boolM (return val_match) ((HaltOnBreakpointOrWatchpoint () )) \ (\ (w__6 :: bool) . + if w__6 then + (let reason = DebugHalt_Watchpoint in + Halt reason \ undefined_FaultRecord () ) + else + and_boolM + (and_boolM (return val_match) + ((read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 15 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) ((AArch64_GenerateDebugExceptions () )) \ (\ (w__11 :: + bool) . + if w__11 then AArch64_DebugFault acctype iswrite + else AArch64_NoFault () )))))))))))" + + +(*val AArch64_CheckDebug : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*) + +definition AArch64_CheckDebug :: "(64)Word.word \ AccType \ bool \ int \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckDebug vaddress acctype iswrite size1 = ( + AArch64_NoFault () \ (\ (fault :: FaultRecord) . + (let (d_side :: bool) = (acctype \ AccType_IFETCH) in + and_boolM ((AArch64_GenerateDebugExceptions () )) + ((read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 15 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (generate_exception :: bool) . + HaltOnBreakpointOrWatchpoint () \ (\ (halt :: bool) . + if (((generate_exception \ halt))) then + if d_side then AArch64_CheckWatchpoint vaddress acctype iswrite size1 + else AArch64_CheckBreakpoint vaddress size1 + else return fault)))))" + + +(*val AArch64_CheckPermission : Permissions -> mword ty64 -> ii -> mword ty1 -> AccType -> bool -> M FaultRecord*) + +definition AArch64_CheckPermission :: " Permissions \(64)Word.word \ int \(1)Word.word \ AccType \ bool \((register_value),(FaultRecord),(exception))monad " where + " AArch64_CheckPermission perms vaddress level NS acctype iswrite = ( + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__0 :: 2 Word.word) . + ELUsingAArch32 w__0 \ (\ (w__1 :: bool) . + (assert_exp ((\ w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \ + (aget_SCTLR__1 () :: ( 32 Word.word) M)) \ (\ (w__2 :: 32 Word.word) . + (let (wxn :: bool) = + ((vec_of_bits [access_vec_dec w__2 (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + undefined_bool () \ (\ (xn :: bool) . + undefined_bool () \ (\ (w :: bool) . + undefined_bool () \ (\ (r :: bool) . + undefined_bool () \ (\ (priv_xn :: bool) . + undefined_bool () \ (\ (user_xn :: bool) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (pan :: 1 bits) . + undefined_bool () \ (\ (ispriv :: bool) . + undefined_bool () \ (\ (user_w :: bool) . + undefined_bool () \ (\ (user_r :: bool) . + undefined_bool () \ (\ (priv_w :: bool) . + undefined_bool () \ (\ (priv_r :: bool) . + or_boolM + (or_boolM + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) = EL0))))) + (read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . return ((((ProcState_EL w__4) = EL1)))))) + ((IsInHost () )) \ (\ (w__7 :: bool) . + (if w__7 then + (let priv_r = True in + (let priv_w = + ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)) in + (let user_r = + ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let user_w = + (((slice0(Permissions_ap perms) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + AArch64_AccessIsPrivileged acctype \ (\ (w__8 :: bool) . + (let ispriv = w__8 in + (if ((HavePANExt () )) then + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . return(ProcState_PAN w__9)) + else return (vec_of_bits [B0] :: 1 Word.word)) \ (\ (w__10 :: 1 Word.word) . + (let pan = w__10 in + and_boolM + (and_boolM + (and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__13 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (IsSecure () \ (\ (w__15 :: bool) . return ((\ w__15))))) + (read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . return ((((ProcState_EL w__17) = EL1))))) \ (\ (w__18 :: + bool) . + (let (pan :: 1 bits) = (if w__18 then (vec_of_bits [B0] :: 1 Word.word) else pan) in + or_boolM + (return ((((((((((((pan = (vec_of_bits [B1] :: 1 Word.word)))) \ user_r))) \ ispriv))) \ ((\ ((((((acctype = AccType_DC))) \ ((((((acctype = AccType_AT))) \ (((acctype = AccType_IFETCH))))))))))))))) + (and_boolM (return (((acctype = AccType_AT)))) ((AArch64_ExecutingATS1xPInstr () ))) \ (\ (w__21 :: + bool) . + (let ((priv_r :: bool), (priv_w :: bool)) = + (if w__21 then + (let (priv_r :: bool) = False in + (let (priv_w :: bool) = False in + (priv_r, priv_w))) + else (priv_r, priv_w)) in + (let (user_xn :: bool) = + (((((Permissions_xn perms) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((user_w \ wxn)))) in + (let (priv_xn :: bool) = + ((((((((Permissions_pxn perms) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((priv_w \ wxn)))))) \ user_w) in + (let ((r :: bool), (w :: bool), (xn :: bool)) = + (if ispriv then + (let (tup__0, tup__1, tup__2) = (priv_r, priv_w, priv_xn) in + (let (r :: bool) = tup__0 in + (let (w :: bool) = tup__1 in + (let (xn :: bool) = tup__2 in + (r, w, xn))))) + else + (let (tup__0, tup__1, tup__2) = (user_r, user_w, user_xn) in + (let (r :: bool) = tup__0 in + (let (w :: bool) = tup__1 in + (let (xn :: bool) = tup__2 in + (r, w, xn)))))) in + return (r, w, xn)))))))))))))))) + else + (let (r :: bool) = True in + (let (w :: bool) = + ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)) in + (let (xn :: bool) = + (((((Permissions_xn perms) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((w \ wxn)))) in + return (r, w, xn))))) \ (\ varstup . (let ((r :: bool), (w :: bool), (xn :: bool)) = varstup in + and_boolM + (and_boolM (and_boolM (return ((HaveEL EL3))) ((IsSecure () ))) + (return (((NS = (vec_of_bits [B1] :: 1 Word.word)))))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__25 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__25 (( 9 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__26 :: bool) . + (let (xn :: bool) = (if w__26 then True else xn) in + undefined_bool () \ (\ (failedread :: bool) . + undefined_bool () \ (\ (fail1 :: bool) . + (let ((fail1 :: bool), (failedread :: bool)) = + (if (((acctype = AccType_IFETCH))) then + (let (fail1 :: bool) = xn in + (let (failedread :: bool) = True in + (fail1, failedread))) + else + (let ((fail1 :: bool), (failedread :: bool)) = + (if ((((((acctype = AccType_ATOMICRW))) \ (((acctype = AccType_ORDEREDRW)))))) then + (let (fail1 :: bool) = (((\ r)) \ ((\ w))) in + (let (failedread :: bool) = (\ r) in + (fail1, failedread))) + else + (let ((fail1 :: bool), (failedread :: bool)) = + (if iswrite then + (let (fail1 :: bool) = (\ w) in + (let (failedread :: bool) = False in + (fail1, failedread))) + else + (let (fail1 :: bool) = (\ r) in + (let (failedread :: bool) = True in + (fail1, failedread)))) in + (fail1, failedread))) in + (fail1, failedread))) in + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + undefined_bool () \ (\ (s2fs1walk :: bool) . + undefined_bool () \ (\ (secondstage :: bool) . + if fail1 then + (let secondstage = False in + (let s2fs1walk = False in + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (w__27 :: 52 bits) . + (let ipaddress = w__27 in + AArch64_PermissionFault ipaddress level acctype ((\ failedread)) secondstage s2fs1walk)))) + else AArch64_NoFault () )))))))))))))))))))))))))))" + + +(*val AArch64_FirstStageTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +definition AArch64_FirstStageTranslate :: "(64)Word.word \ AccType \ bool \ bool \ int \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size1 = ( + undefined_bool () \ (\ (s1_enabled :: bool) . + HasS2Translation () \ (\ (w__0 :: bool) . + (if w__0 then + and_boolM + (and_boolM + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__1 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 12 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + else + (aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (let (s1_enabled :: bool) = + ((vec_of_bits [access_vec_dec w__6 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + return s1_enabled))) \ (\ (s1_enabled :: bool) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \ (\ (ipaddress :: 52 bits) . + (let (secondstage :: bool) = False in + (let (s2fs1walk :: bool) = False in + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (nTLSMD :: 1 bits) . + undefined_bool () \ (\ (permissioncheck :: bool) . + undefined_TLBRecord () \ (\ (S1 :: TLBRecord) . + (if s1_enabled then + AArch64_TranslationTableWalk ipaddress vaddress acctype iswrite secondstage s2fs1walk size1 \ (\ (w__7 :: + TLBRecord) . + (let (S1 :: TLBRecord) = w__7 in + (let (permissioncheck :: bool) = True in + return (S1, permissioncheck)))) + else + AArch64_TranslateAddressS1Off vaddress acctype iswrite \ (\ (w__8 :: TLBRecord) . + (let S1 = w__8 in + (let permissioncheck = False in + and_boolM (and_boolM ((UsingAArch32 () )) (return ((HaveTrapLoadStoreMultipleDeviceExt () )))) + ((AArch32_ExecutingLSMInstr () )) \ (\ (w__12 :: bool) . + (if w__12 then + if (((((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S1))) = MemType_Device))) \ ((((MemoryAttributes_device (AddressDescriptor_memattrs (TLBRecord_addrdesc S1))) \ DeviceType_GRE)))))) then + (S1TranslationRegime__1 () :: ( 2 Word.word) M) \ (\ (w__13 :: 2 Word.word) . + (if (((w__13 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__14 (( 28 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__15 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__15 (( 28 :: int)::ii)] :: 1 Word.word))) \ (\ (w__16 :: + 1 Word.word) . + (let nTLSMD = w__16 in + if (((nTLSMD = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (tmp_2460 :: AddressDescriptor) = ((TLBRecord_addrdesc S1)) in + AArch64_AlignmentFault acctype iswrite secondstage \ (\ (w__17 :: FaultRecord) . + (let (tmp_2460 :: AddressDescriptor) = + ((tmp_2460 (| AddressDescriptor_fault := w__17 |))) in + (let (S1 :: TLBRecord) = ((S1 (| TLBRecord_addrdesc := tmp_2460 |))) in + return S1)))) + else return S1))) + else return S1 + else return S1) \ (\ (S1 :: TLBRecord) . + return (S1, permissioncheck))))))) \ (\ varstup . (let ((S1 :: TLBRecord), (permissioncheck :: + bool)) = varstup in + (if ((((((((((((((\ wasaligned)) \ (((acctype \ AccType_IFETCH)))))) \ (((acctype = AccType_DCZVA)))))) \ ((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S1))) = MemType_Device)))))) \ ((\ ((IsFault(TLBRecord_addrdesc S1)))))))) then + (let (tmp_2470 :: AddressDescriptor) = ((TLBRecord_addrdesc S1)) in + AArch64_AlignmentFault acctype iswrite secondstage \ (\ (w__18 :: FaultRecord) . + (let (tmp_2470 :: AddressDescriptor) = ((tmp_2470 (| AddressDescriptor_fault := w__18 |))) in + (let (S1 :: TLBRecord) = ((S1 (| TLBRecord_addrdesc := tmp_2470 |))) in + return S1)))) + else return S1) \ (\ (S1 :: TLBRecord) . + (if (((((\ ((IsFault(TLBRecord_addrdesc S1))))) \ permissioncheck))) then + (let (tmp_2480 :: AddressDescriptor) = ((TLBRecord_addrdesc S1)) in + AArch64_CheckPermission(TLBRecord_perms S1) vaddress(TLBRecord_level S1)(FullAddress_NS (AddressDescriptor_paddress (TLBRecord_addrdesc + S1))) acctype iswrite \ (\ (w__19 :: + FaultRecord) . + (let (tmp_2480 :: AddressDescriptor) = ((tmp_2480 (| AddressDescriptor_fault := w__19 |))) in + (let (S1 :: TLBRecord) = ((S1 (| TLBRecord_addrdesc := tmp_2480 |))) in + return S1)))) + else return S1) \ (\ (S1 :: TLBRecord) . + (if ((((((((\ ((IsFault(TLBRecord_addrdesc S1))))) \ ((((MemoryAttributes_typ (AddressDescriptor_memattrs (TLBRecord_addrdesc S1))) = MemType_Device)))))) \ (((acctype = AccType_IFETCH)))))) then + AArch64_InstructionDevice(TLBRecord_addrdesc S1) vaddress ipaddress(TLBRecord_level S1) acctype + iswrite secondstage s2fs1walk \ (\ (w__20 :: AddressDescriptor) . + (let (S1 :: TLBRecord) = ((S1 (| TLBRecord_addrdesc := w__20 |))) in + return S1)) + else return S1) \ (\ (S1 :: TLBRecord) . + (let (hwupdatewalk :: bool) = False in + (let s2fs1walk = False in + (let (tmp_2490 :: AddressDescriptor) = ((TLBRecord_addrdesc S1)) in + AArch64_CheckAndUpdateDescriptor(TLBRecord_descupdate S1)(AddressDescriptor_fault (TLBRecord_addrdesc + S1)) secondstage vaddress acctype iswrite s2fs1walk + hwupdatewalk \ (\ (w__21 :: FaultRecord) . + (let (tmp_2490 :: AddressDescriptor) = ((tmp_2490 (| AddressDescriptor_fault := w__21 |))) in + (let (S1 :: TLBRecord) = ((S1 (| TLBRecord_addrdesc := tmp_2490 |))) in + return(TLBRecord_addrdesc S1))))))))))))))))))))))" + + +(*val AArch64_FullTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +definition AArch64_FullTranslate :: "(64)Word.word \ AccType \ bool \ bool \ int \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_FullTranslate vaddress acctype iswrite wasaligned size1 = ( + AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size1 \ (\ (S1 :: + AddressDescriptor) . + undefined_AddressDescriptor () \ (\ (result :: AddressDescriptor) . + undefined_bool () \ (\ (hwupdatewalk :: bool) . + undefined_bool () \ (\ (s2fs1walk :: bool) . + and_boolM (return ((\ ((IsFault S1))))) ((HasS2Translation () )) \ (\ (w__1 :: bool) . + if w__1 then + (let s2fs1walk = False in + (let hwupdatewalk = False in + AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk)) + else return S1))))))" + + +(*val AArch64_TranslateAddress : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +definition AArch64_TranslateAddress :: "(64)Word.word \ AccType \ bool \ bool \ int \((register_value),(AddressDescriptor),(exception))monad " where + " AArch64_TranslateAddress vaddress acctype iswrite wasaligned size1 = ( + AArch64_FullTranslate vaddress acctype iswrite wasaligned size1 \ (\ (result :: + AddressDescriptor) . + (if (((((\ ((((((acctype = AccType_PTW))) \ ((((((acctype = AccType_IC))) \ (((acctype = AccType_AT))))))))))) \ ((\ ((IsFault result))))))) then + AArch64_CheckDebug vaddress acctype iswrite size1 \ (\ (w__0 :: FaultRecord) . + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_fault := w__0 |))) in + return result)) + else return result) \ (\ (result :: AddressDescriptor) . + (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_vaddress := w__1 |))) in + return result)))))" + + +(*val AArch64_aset_MemSingle : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> mword 'p8_times_size_ -> M unit*) + +definition AArch64_aset_MemSingle :: "(64)Word.word \ int \ AccType \ bool \('p8_times_size_::len)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_aset_MemSingle address size1 acctype wasaligned value_name = ( + ((assert_exp ((((((size1 = (( 1 :: int)::ii)))) \ ((((((size1 = (( 2 :: int)::ii)))) \ ((((((size1 = (( 4 :: int)::ii)))) \ ((((((size1 = (( 8 :: int)::ii)))) \ (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \ + assert_exp (((address = ((Align__1 address size1 :: 64 Word.word))))) (''(address == Align(address, size))'')) \ + undefined_AddressDescriptor () ) \ (\ (memaddrdesc :: AddressDescriptor) . + (let (iswrite :: bool) = True in + AArch64_TranslateAddress address acctype iswrite wasaligned size1 \ (\ (w__0 :: + AddressDescriptor) . + (let memaddrdesc = w__0 in + (if ((IsFault memaddrdesc)) then AArch64_Abort address(AddressDescriptor_fault memaddrdesc) + else return () ) \ + ((let (_ :: unit) = + (if(MemoryAttributes_shareable (AddressDescriptor_memattrs memaddrdesc)) then + ClearExclusiveByAddress(AddressDescriptor_paddress memaddrdesc) ((ProcessorID () )) size1 + else () ) in + CreateAccessDescriptor acctype \ (\ (accdesc :: AccessDescriptor) . + aset__Mem memaddrdesc size1 accdesc value_name))))))))" + + +(*val aset_Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> mword 'p8_times_size_ -> M unit*) + +definition aset_Mem :: "(64)Word.word \ int \ AccType \('p8_times_size_::len)Word.word \((register_value),(unit),(exception))monad " where + " aset_Mem address size1 acctype value_name__arg = ( + (let value_name = value_name__arg in + undefined_int () \ (\ (i :: ii) . + (let (iswrite :: bool) = True in + BigEndian () \ (\ (w__0 :: bool) . + (if w__0 then (BigEndianReverse value_name :: (( 'p8_times_size_::len)Word.word) M) + else return value_name) \ (\ value_name . + AArch64_CheckAlignment address size1 acctype iswrite \ (\ (aligned :: bool) . + undefined_bool () \ (\ (atomic :: bool) . + (let (atomic :: bool) = + (if ((((((size1 \ (( 16 :: int)::ii)))) \ ((\ ((((((acctype = AccType_VEC))) \ (((acctype = AccType_VECSTREAM))))))))))) then + aligned + else (address = ((Align__1 address (( 8 :: int)::ii) :: 64 Word.word)))) in + undefined_Constraint () \ (\ (c :: Constraint) . + if ((\ atomic)) then + ((assert_exp ((size1 > (( 1 :: int)::ii))) (''(size > 1)'') \ + AArch64_aset_MemSingle address (( 1 :: int)::ii) acctype aligned + ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) \ + (if ((\ aligned)) then + (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in + assert_exp ((((((c = Constraint_FAULT))) \ (((c = Constraint_NONE)))))) (''((c == Constraint_FAULT) || (c == Constraint_NONE))'') \ + ((let (aligned :: bool) = (if (((c = Constraint_NONE))) then True else aligned) in + return aligned))) + else return aligned)) \ (\ (aligned :: bool) . + (foreachM (index_list (( 1 :: int)::ii) ((size1 - (( 1 :: int)::ii))) (( 1 :: int)::ii)) () + (\ i unit_var . + AArch64_aset_MemSingle ((add_vec_int address i :: 64 Word.word)) (( 1 :: int)::ii) acctype aligned + ((slice0 value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii) :: 8 Word.word))))) + else if ((((((size1 = (( 16 :: int)::ii)))) \ ((((((acctype = AccType_VEC))) \ (((acctype = AccType_VECSTREAM))))))))) then + AArch64_aset_MemSingle address (( 8 :: int)::ii) acctype aligned + ((slice0 value_name (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \ + AArch64_aset_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned + ((slice0 value_name (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))))" + + +(*val AArch64_aget_MemSingle : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> M (mword 'p8_times_size_)*) + +definition AArch64_aget_MemSingle :: "(64)Word.word \ int \ AccType \ bool \((register_value),(('p8_times_size_::len)Word.word),(exception))monad " where + " AArch64_aget_MemSingle address size1 acctype wasaligned = ( + ((assert_exp ((((((size1 = (( 1 :: int)::ii)))) \ ((((((size1 = (( 2 :: int)::ii)))) \ ((((((size1 = (( 4 :: int)::ii)))) \ ((((((size1 = (( 8 :: int)::ii)))) \ (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \ + assert_exp (((address = ((Align__1 address size1 :: 64 Word.word))))) (''(address == Align(address, size))'')) \ + undefined_AddressDescriptor () ) \ (\ (memaddrdesc :: AddressDescriptor) . + (undefined_bitvector (((( 8 :: int)::ii) * size1)) :: (( 'p8_times_size_::len)Word.word) M) \ (\ value_name . + (let (iswrite :: bool) = False in + AArch64_TranslateAddress address acctype iswrite wasaligned size1 \ (\ (w__0 :: + AddressDescriptor) . + (let memaddrdesc = w__0 in + ((if ((IsFault memaddrdesc)) then AArch64_Abort address(AddressDescriptor_fault memaddrdesc) + else return () ) \ + CreateAccessDescriptor acctype) \ (\ (accdesc :: AccessDescriptor) . + (aget__Mem memaddrdesc size1 accdesc :: (( 'p8_times_size_::len)Word.word) M))))))))" + + +(*val aget_Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> M (mword 'p8_times_size_)*) + +definition aget_Mem :: "(64)Word.word \ int \ AccType \((register_value),(('p8_times_size_::len)Word.word),(exception))monad " where + " aget_Mem address size1 acctype = ( + (assert_exp ((((((size1 = (( 1 :: int)::ii)))) \ ((((((size1 = (( 2 :: int)::ii)))) \ ((((((size1 = (( 4 :: int)::ii)))) \ ((((((size1 = (( 8 :: int)::ii)))) \ (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \ + (undefined_bitvector (((( 8 :: int)::ii) * size1)) :: (( 'p8_times_size_::len)Word.word) M)) \ (\ value_name . + undefined_int () \ (\ (i :: ii) . + (let (iswrite :: bool) = False in + AArch64_CheckAlignment address size1 acctype iswrite \ (\ (aligned :: bool) . + undefined_bool () \ (\ (atomic :: bool) . + (let (atomic :: bool) = + (if ((((((size1 \ (( 16 :: int)::ii)))) \ ((\ ((((((acctype = AccType_VEC))) \ (((acctype = AccType_VECSTREAM))))))))))) then + aligned + else (address = ((Align__1 address (( 8 :: int)::ii) :: 64 Word.word)))) in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((\ atomic)) then + (assert_exp ((size1 > (( 1 :: int)::ii))) (''(size > 1)'') \ + (AArch64_aget_MemSingle address (( 1 :: int)::ii) acctype aligned :: ( 8 Word.word) M)) \ (\ (w__0 :: + 8 Word.word) . + (let value_name = + ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (( 0 :: int)::ii) w__0 + :: ( 'p8_times_size_::len)Word.word)) in + (if ((\ aligned)) then + (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in + assert_exp ((((((c = Constraint_FAULT))) \ (((c = Constraint_NONE)))))) (''((c == Constraint_FAULT) || (c == Constraint_NONE))'') \ + ((let (aligned :: bool) = (if (((c = Constraint_NONE))) then True else aligned) in + return aligned))) + else return aligned) \ (\ (aligned :: bool) . + (foreachM (index_list (( 1 :: int)::ii) ((size1 - (( 1 :: int)::ii))) (( 1 :: int)::ii)) value_name + (\ i value_name . + (AArch64_aget_MemSingle ((add_vec_int address i :: 64 Word.word)) (( 1 :: int)::ii) acctype aligned + :: ( 8 Word.word) M) \ (\ (w__1 :: 8 Word.word) . + (let value_name = + ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (((( 8 :: int)::ii) * i)) w__1 + :: ( 'p8_times_size_::len)Word.word)) in + return value_name))))))) + else if ((((((size1 = (( 16 :: int)::ii)))) \ ((((((acctype = AccType_VEC))) \ (((acctype = AccType_VECSTREAM))))))))) then + (AArch64_aget_MemSingle address (( 8 :: int)::ii) acctype aligned :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (let value_name = + ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2 + :: ( 'p8_times_size_::len)Word.word)) in + (AArch64_aget_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned + :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (let value_name = + ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3 + :: ( 'p8_times_size_::len)Word.word)) in + return value_name)))) + else (AArch64_aget_MemSingle address size1 acctype aligned :: (( 'p8_times_size_::len)Word.word) M)) \ (\ value_name . + BigEndian () \ (\ (w__5 :: bool) . + if w__5 then (BigEndianReverse value_name :: (( 'p8_times_size_::len)Word.word) M) + else return value_name))))))))))" + + +(*val aarch64_memory_vector_single_nowb : forall 'datasize 'esize . Size 'datasize, Size 'esize => itself 'datasize -> itself 'esize -> ii -> ii -> MemOp -> ii -> bool -> integer -> ii -> bool -> M unit*) + +definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \('esize::len)itself \ int \ int \ MemOp \ int \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_vector_single_nowb datasize esize index1 m memop n replicate1 selem t__arg wback = ( + (let esize = (size_itself_int esize) in + (let datasize = (size_itself_int datasize) in + assert_exp True ('''') \ + ((let (t :: ii) = t__arg in + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offs :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (rval :: 128 bits) . + (undefined_bitvector esize :: (( 'esize::len)Word.word) M) \ (\ (element :: 'esize bits) . + undefined_int () \ (\ (s :: ii) . + (let (ebytes :: int) = (ex_int ((esize div (( 8 :: int)::ii)))) in + (assert_exp True ('''') \ + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \ (\ (address :: 64 bits) . + (let offs = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in + (if replicate1 then + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs + (\ s offs . + (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \ (\ (w__2 :: 'esize + bits) . + (let element = w__2 in + (let (v :: int) = (ex_int ((datasize div esize))) in + (assert_exp True ('''') \ + aset_V t ((replicate_bits element v :: ( 'datasize::len)Word.word))) \ + ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in + (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in + return offs)))))))) + else + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs + (\ s offs . + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (w__3 :: 128 bits) . + (let rval = w__3 in + (if (((memop = MemOp_LOAD))) then + (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \ (\ (w__4 :: + ( 'esize::len)Word.word) . + (aset_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) w__4 + :: ( 128 Word.word) M) \ (\ (w__5 :: 128 bits) . + (let rval = w__5 in + aset_V t rval))) + else + (aget_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \ (\ w__6 . + aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__6)) \ + ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in + (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in + return offs)))))))) \ (\ (offs :: 64 bits) . + if wback then + (if (((m \ (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) + else return offs) \ (\ (offs :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP ((add_vec address offs :: 64 Word.word)) + else aset_X n ((add_vec address offs :: 64 Word.word))) + else return () ))))))))))))))" + + +(*val aarch64_memory_vector_multiple_nowb : forall 'datasize 'esize . Size 'datasize, Size 'esize => itself 'datasize -> integer -> itself 'esize -> ii -> MemOp -> ii -> integer -> integer -> ii -> bool -> M unit*) + +definition aarch64_memory_vector_multiple_nowb :: "('datasize::len)itself \ int \('esize::len)itself \ int \ MemOp \ int \ int \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_vector_multiple_nowb datasize elements esize m memop n rpt selem t wback = ( + (let esize = (size_itself_int esize) in + (let datasize = (size_itself_int datasize) in + ((assert_exp True (''datasize constraint'') \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offs :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (rval :: 'datasize bits) . + undefined_int () \ (\ (e :: ii) . + undefined_int () \ (\ (r :: ii) . + undefined_int () \ (\ (s :: ii) . + undefined_int () \ (\ (tt :: ii) . + (let ebytes = (ex_int ((esize div (( 8 :: int)::ii)))) in + (assert_exp True ('''') \ + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \ (\ (address :: 64 bits) . + (let offs = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) ((rpt - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs + (\ r offs . + (foreachM (index_list (( 0 :: int)::ii) ((elements - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs + (\ e offs . + (let tt = (((t + r)) mod (( 32 :: int)::ii)) in + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs + (\ s offs . + (aget_V datasize tt :: (( 'datasize::len)Word.word) M) \ (\ (w__2 :: 'datasize bits) . + (let rval = w__2 in + (if (((memop = MemOp_LOAD))) then + (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC + :: (( 'esize::len)Word.word) M) \ (\ (w__3 :: ( 'esize::len)Word.word) . + (aset_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) w__3 + :: (( 'datasize::len)Word.word) M) \ (\ (w__4 :: 'datasize bits) . + (let rval = w__4 in + aset_V tt rval))) + else + (aget_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \ (\ w__5 . + aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__5)) \ + ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in + (let (tt :: ii) = (((((ex_int tt)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in + return offs)))))))))))) \ (\ (offs :: 64 bits) . + if wback then + (if (((m \ (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) + else return offs) \ (\ (offs :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP ((add_vec address offs :: 64 Word.word)) + else aset_X n ((add_vec address offs :: 64 Word.word))) + else return () ))))))))))))))" + + +(*val aarch64_memory_single_simdfp_register : AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> ii -> ii -> bool -> M unit*) + +definition aarch64_memory_single_simdfp_register :: " AccType \ int \ ExtendType \ int \ MemOp \ int \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_simdfp_register acctype l__83 extend_type m memop n postindex shift t wback = ( + if (((l__83 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \ (\ (w__2 :: 8 bits) . + (let data = w__2 in + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__3 :: 8 + bits) . + (let data = w__3 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))) + else if (((l__83 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \ (\ (w__6 :: 16 bits) . + (let data = w__6 in + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__7 :: 16 + bits) . + (let data = w__7 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))) + else if (((l__83 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + (let data = w__10 in + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__11 :: 32 + bits) . + (let data = w__11 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))) + else if (((l__83 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + (let data = w__14 in + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__15 :: 64 + bits) . + (let data = w__15 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))) + else if (((l__83 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M)) \ (\ (offset :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (w__18 :: 128 bits) . + (let data = w__18 in + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__19 :: 128 + bits) . + (let data = w__19 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))) + else + (let dbytes = (ex_int ((l__83 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_memory_single_simdfp_immediate_signed_postidx : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_simdfp_immediate_signed_postidx acctype l__78 memop n offset postindex t wback = ( + if (((l__78 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \ (\ (w__2 :: 8 bits) . + (let data = w__2 in + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__3 :: 8 + bits) . + (let data = w__3 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__78 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \ (\ (w__6 :: 16 bits) . + (let data = w__6 in + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__7 :: 16 + bits) . + (let data = w__7 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__78 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + (let data = w__10 in + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__11 :: 32 + bits) . + (let data = w__11 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__78 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + (let data = w__14 in + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__15 :: 64 + bits) . + (let data = w__15 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__78 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (w__18 :: 128 bits) . + (let data = w__18 in + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__19 :: 128 + bits) . + (let data = w__19 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else + (let dbytes = (ex_int ((l__78 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_memory_single_simdfp_immediate_signed_offset_normal : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype l__73 memop n offset postindex t wback = ( + if (((l__73 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \ (\ (w__2 :: 8 bits) . + (let data = w__2 in + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__3 :: 8 + bits) . + (let data = w__3 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__73 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \ (\ (w__6 :: 16 bits) . + (let data = w__6 in + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__7 :: 16 + bits) . + (let data = w__7 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__73 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + (let data = w__10 in + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__11 :: 32 + bits) . + (let data = w__11 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__73 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + (let data = w__14 in + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__15 :: 64 + bits) . + (let data = w__15 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else if (((l__73 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (w__18 :: 128 bits) . + (let data = w__18 in + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__19 :: 128 + bits) . + (let data = w__19 in + aset_V t data)) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))) + else + (let dbytes = (ex_int ((l__73 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_memory_ordered : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> MemOp -> ii -> itself 'regsize -> ii -> M unit*) + +definition aarch64_memory_ordered :: " AccType \('datasize::len)itself \ MemOp \ int \('regsize::len)itself \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_ordered acctype datasize memop n regsize t = ( + (let regsize = (size_itself_int regsize) in + (let datasize = (size_itself_int datasize) in + (assert_exp True (''datasize constraint'') \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data :: 'datasize bits) . + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (assert_exp True ('''') \ + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \ (\ (address :: 64 bits) . + (case memop of + MemOp_STORE => + (aget_X ((int (size data))) t :: (( 'datasize::len)Word.word) M) \ (\ (w__2 :: 'datasize bits) . + (let data = w__2 in + aset_Mem address dbytes acctype data)) + | MemOp_LOAD => + (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__3 :: 'datasize bits) . + (let data = w__3 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__4 :: + ( 'regsize::len)Word.word) . + aset_X t w__4))) + ))))))))" + + +(*val memory_ordered_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_ordered_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_ordered_decode b__0 o2 L o1 Rs o0 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B0] :: 1 Word.word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 8 :: int)::ii) :: 8 itself)) memop n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B0] :: 1 Word.word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 16 :: int)::ii) :: 16 itself)) memop n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B0] :: 1 Word.word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 32 :: int)::ii) :: 32 itself)) memop n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))))) + else + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B0] :: 1 Word.word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 64 :: int)::ii) :: 64 itself)) memop n + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) t)))))))))))" + + +(*val aarch64_memory_orderedrcpc : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> ii -> itself 'regsize -> ii -> M unit*) + +definition aarch64_memory_orderedrcpc :: " AccType \('datasize::len)itself \ int \('regsize::len)itself \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_orderedrcpc acctype datasize n regsize t = ( + (let regsize = (size_itself_int regsize) in + (let datasize = (size_itself_int datasize) in + (assert_exp True (''datasize constraint'') \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data :: 'datasize bits) . + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (assert_exp True ('''') \ + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \ (\ (address :: 64 bits) . + (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__2 :: 'datasize bits) . + (let data = w__2 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__3 :: + ( 'regsize::len)Word.word) . + aset_X t w__3))))))))))" + + +(*val memory_orderedrcpc_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_orderedrcpc_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_orderedrcpc_decode b__0 V1 A R1 Rs o3 opc Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = AccType_ORDERED in + (let (elsize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 8 :: int)::ii) :: 8 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = AccType_ORDERED in + (let (elsize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 16 :: int)::ii) :: 16 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = AccType_ORDERED in + (let (elsize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))) + else + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = AccType_ORDERED in + (let (elsize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) t)))))))))" + + +(*val aarch64_memory_literal_simdfp : mword ty64 -> integer -> ii -> M unit*) + +definition aarch64_memory_literal_simdfp :: "(64)Word.word \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_literal_simdfp offset l__70 t = ( + if (((l__70 = (( 4 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp True ('''')) \ + (aget_PC () :: ( 64 Word.word) M)) \ (\ (w__0 :: 64 Word.word) . + (let (address :: 64 bits) = ((add_vec w__0 offset :: 64 Word.word)) in + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (aget_Mem address (( 4 :: int)::ii) AccType_VEC :: ( 32 Word.word) M)) \ (\ (w__1 :: 32 bits) . + (let data = w__1 in + aset_V t data))))) + else if (((l__70 = (( 8 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp True ('''')) \ + (aget_PC () :: ( 64 Word.word) M)) \ (\ (w__2 :: 64 Word.word) . + (let (address :: 64 bits) = ((add_vec w__2 offset :: 64 Word.word)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (aget_Mem address (( 8 :: int)::ii) AccType_VEC :: ( 64 Word.word) M)) \ (\ (w__3 :: 64 bits) . + (let data = w__3 in + aset_V t data))))) + else if (((l__70 = (( 16 :: int)::ii)))) then + ((assert_exp True ('''') \ + assert_exp True ('''')) \ + (aget_PC () :: ( 64 Word.word) M)) \ (\ (w__4 :: 64 Word.word) . + (let (address :: 64 bits) = ((add_vec w__4 offset :: 64 Word.word)) in + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (CheckFPAdvSIMDEnabled64 () \ + (aget_Mem address (( 16 :: int)::ii) AccType_VEC :: ( 128 Word.word) M)) \ (\ (w__5 :: 128 bits) . + (let data = w__5 in + aset_V t data))))) + else assert_exp True ('''') \ assert_exp True (''''))" + + +(*val aarch64_memory_literal_general : forall 'size. Size 'size => MemOp -> mword ty64 -> bool -> itself 'size -> ii -> M unit*) + +definition aarch64_memory_literal_general :: " MemOp \(64)Word.word \ bool \('size::len)itself \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_literal_general memop offset signed size1 t = ( + (let size1 = (size_itself_int size1) in + (aget_PC () :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (let (address :: 64 bits) = ((add_vec w__0 offset :: 64 Word.word)) in + (undefined_bitvector size1 :: (( 'size::len)Word.word) M) \ (\ (data :: 'size bits) . + (case memop of + MemOp_LOAD => + assert_exp True ('''') \ + ((let bytes = (size1 div (( 8 :: int)::ii)) in + (assert_exp True ('''') \ + (aget_Mem address bytes AccType_NORMAL :: (( 'size::len)Word.word) M)) \ (\ (w__1 :: 'size bits) . + (let data = w__1 in + if signed then + (SignExtend__0 data ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + aset_X t w__2) + else aset_X t data)))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ))))))" + + +(*val memory_literal_general_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +definition memory_literal_general_decode :: "(2)Word.word \(1)Word.word \(19)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_literal_general_decode b__0 V1 imm19 Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (memop :: MemOp) = MemOp_LOAD in + (let (signed :: bool) = False in + undefined_int () \ (\ (size1 :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let size1 = ((( 4 :: int)::ii)) in + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (let offset = w__0 in + aarch64_memory_literal_general MemOp_LOAD offset False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (memop :: MemOp) = MemOp_LOAD in + (let (signed :: bool) = False in + undefined_int () \ (\ (size1 :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let size1 = ((( 8 :: int)::ii)) in + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__1 :: 64 bits) . + (let offset = w__1 in + aarch64_memory_literal_general MemOp_LOAD offset False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) t))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (memop :: MemOp) = MemOp_LOAD in + (let (signed :: bool) = False in + undefined_int () \ (\ (size1 :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let size1 = ((( 4 :: int)::ii)) in + (let signed = True in + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + (let offset = w__2 in + aarch64_memory_literal_general MemOp_LOAD offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + t)))))))))) + else + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (memop :: MemOp) = MemOp_LOAD in + (let (signed :: bool) = False in + undefined_int () \ (\ (size1 :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let memop = MemOp_PREFETCH in + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__3 :: 64 bits) . + (let offset = w__3 in + aarch64_memory_literal_general MemOp_PREFETCH offset False + ((make_the_value (((( 8 :: int)::ii) * (( 32 :: int)::ii))) :: 256 itself)) t))))))))))" + + +(*val aarch64_memory_atomicops_swp : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +definition aarch64_memory_atomicops_swp :: " int \ AccType \ int \('regsize::len)itself \ int \ AccType \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_atomicops_swp l__65 ldacctype n regsize s stacctype t = ( + if (((l__65 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \ (\ (w__2 :: 8 + bits) . + (let data = w__2 in + (aget_X ((int (size data))) s :: ( 8 Word.word) M) \ (\ w__3 . + (aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__3 \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__4 :: + ( 'regsize::len)Word.word) . + aset_X t w__4)))))))))) + else if (((l__65 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \ (\ (w__7 :: 16 + bits) . + (let data = w__7 in + (aget_X ((int (size data))) s :: ( 16 Word.word) M) \ (\ w__8 . + (aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__8 \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__9 :: + ( 'regsize::len)Word.word) . + aset_X t w__9)))))))))) + else if (((l__65 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \ (\ (w__12 :: 32 + bits) . + (let data = w__12 in + (aget_X ((int (size data))) s :: ( 32 Word.word) M) \ (\ w__13 . + (aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__13 \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14)))))))))) + else if (((l__65 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \ (\ (w__17 :: 64 + bits) . + (let data = w__17 in + (aget_X ((int (size address))) s :: ( 64 Word.word) M) \ (\ w__18 . + (aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__18 \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__19 :: + ( 'regsize::len)Word.word) . + aset_X t w__19)))))))))) + else if (((l__65 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \ (\ (w__22 :: 128 + bits) . + (let data = w__22 in + (aget_X ((int (size data))) s :: ( 128 Word.word) M) \ (\ w__23 . + (aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__23 \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__24 :: + ( 'regsize::len)Word.word) . + aset_X t w__24)))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__65 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_atomicops_st : ii -> AccType -> ii -> MemAtomicOp -> ii -> AccType -> M unit*) + +definition aarch64_memory_atomicops_st :: " int \ AccType \ int \ MemAtomicOp \ int \ AccType \((register_value),(unit),(exception))monad " where + " aarch64_memory_atomicops_st l__60 ldacctype n op1 s stacctype = ( + if (((l__60 = (( 8 :: int)::ii)))) then + (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (value_name :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \ (\ (w__0 :: 8 bits) . + (let value_name = w__0 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \ (\ (w__3 :: 8 + bits) . + (let data = w__3 in + (let (result :: 8 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 8 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 8 Word.word)) :: 8 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 8 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 8 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype result))))))))))) + else if (((l__60 = (( 16 :: int)::ii)))) then + (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (value_name :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \ (\ (w__4 :: 16 bits) . + (let value_name = w__4 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \ (\ (w__7 :: 16 + bits) . + (let data = w__7 in + (let (result :: 16 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 16 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 16 Word.word)) :: 16 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 16 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 16 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype result))))))))))) + else if (((l__60 = (( 32 :: int)::ii)))) then + (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (value_name :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \ (\ (w__8 :: 32 bits) . + (let value_name = w__8 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \ (\ (w__11 :: 32 + bits) . + (let data = w__11 in + (let (result :: 32 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 32 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 32 Word.word)) :: 32 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 32 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 32 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype result))))))))))) + else if (((l__60 = (( 64 :: int)::ii)))) then + (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (value_name :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + (let value_name = w__12 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \ (\ (w__15 :: 64 + bits) . + (let data = w__15 in + (let (result :: 64 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 64 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 64 Word.word)) :: 64 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 64 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 64 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype result))))))))))) + else if (((l__60 = (( 128 :: int)::ii)))) then + (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (value_name :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \ (\ (w__16 :: 128 bits) . + (let value_name = w__16 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \ (\ (w__19 :: 128 + bits) . + (let data = w__19 in + (let (result :: 128 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 128 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 128 Word.word)) :: 128 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 128 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 128 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype result))))))))))) + else + (let dbytes = (ex_int ((l__60 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))" + + +(*val aarch64_memory_atomicops_ld : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> MemAtomicOp -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +definition aarch64_memory_atomicops_ld :: " int \ AccType \ int \ MemAtomicOp \('regsize::len)itself \ int \ AccType \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_atomicops_ld l__55 ldacctype n op1 regsize s stacctype t = ( + if (((l__55 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (value_name :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (result :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \ (\ (w__0 :: 8 bits) . + (let value_name = w__0 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \ (\ (w__3 :: 8 + bits) . + (let data = w__3 in + (let (result :: 8 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 8 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 8 Word.word)) :: 8 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 8 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 8 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + (aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__4 :: + ( 'regsize::len)Word.word) . + aset_X t w__4)))))))))))))) + else if (((l__55 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (value_name :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (result :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \ (\ (w__5 :: 16 bits) . + (let value_name = w__5 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \ (\ (w__8 :: 16 + bits) . + (let data = w__8 in + (let (result :: 16 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 16 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 16 Word.word)) :: 16 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 16 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 16 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + (aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__9 :: + ( 'regsize::len)Word.word) . + aset_X t w__9)))))))))))))) + else if (((l__55 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (value_name :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (result :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + (let value_name = w__10 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \ (\ (w__13 :: 32 + bits) . + (let data = w__13 in + (let (result :: 32 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 32 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 32 Word.word)) :: 32 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 32 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 32 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + (aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14)))))))))))))) + else if (((l__55 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (value_name :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (result :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \ (\ (w__15 :: 64 bits) . + (let value_name = w__15 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \ (\ (w__18 :: 64 + bits) . + (let data = w__18 in + (let (result :: 64 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 64 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 64 Word.word)) :: 64 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 64 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 64 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + (aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__19 :: + ( 'regsize::len)Word.word) . + aset_X t w__19)))))))))))))) + else if (((l__55 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (value_name :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (result :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \ (\ (w__20 :: 128 bits) . + (let value_name = w__20 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \ (\ (w__23 :: 128 + bits) . + (let data = w__23 in + (let (result :: 128 bits) = + ((case op1 of + MemAtomicOp_ADD => (add_vec data value_name :: 128 Word.word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name :: 128 Word.word)) :: 128 Word.word) + | MemAtomicOp_EOR => (xor_vec data value_name :: 128 Word.word) + | MemAtomicOp_ORR => (or_vec data value_name :: 128 Word.word) + | MemAtomicOp_SMAX => if ((((Word.sint data)) > ((Word.sint value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((Word.sint data)) > ((Word.sint value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((Word.uint data)) > ((Word.uint value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data + )) in + (aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__24 :: + ( 'regsize::len)Word.word) . + aset_X t w__24)))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__55 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_atomicops_cas_single : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +definition aarch64_memory_atomicops_cas_single :: " int \ AccType \ int \('regsize::len)itself \ int \ AccType \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_atomicops_cas_single l__50 ldacctype n regsize s stacctype t = ( + if (((l__50 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (comparevalue :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (newvalue :: 8 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \ (\ (w__0 :: 8 bits) . + (let comparevalue = w__0 in + (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M) \ (\ (w__1 :: 8 bits) . + (let newvalue = w__1 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X s w__5))))))))))))))) + else if (((l__50 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (comparevalue :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (newvalue :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \ (\ (w__6 :: 16 bits) . + (let comparevalue = w__6 in + (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M) \ (\ (w__7 :: 16 bits) . + (let newvalue = w__7 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \ (\ (w__10 :: 16 + bits) . + (let data = w__10 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__11 :: + ( 'regsize::len)Word.word) . + aset_X s w__11))))))))))))))) + else if (((l__50 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (comparevalue :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (newvalue :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \ (\ (w__12 :: 32 bits) . + (let comparevalue = w__12 in + (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M) \ (\ (w__13 :: 32 bits) . + (let newvalue = w__13 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \ (\ (w__16 :: 32 + bits) . + (let data = w__16 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__17 :: + ( 'regsize::len)Word.word) . + aset_X s w__17))))))))))))))) + else if (((l__50 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (comparevalue :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (newvalue :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \ (\ (w__18 :: 64 bits) . + (let comparevalue = w__18 in + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (w__19 :: 64 bits) . + (let newvalue = w__19 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \ (\ (w__22 :: 64 + bits) . + (let data = w__22 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__23 :: + ( 'regsize::len)Word.word) . + aset_X s w__23))))))))))))))) + else if (((l__50 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (comparevalue :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (newvalue :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \ (\ (w__24 :: 128 bits) . + (let comparevalue = w__24 in + (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (w__25 :: 128 bits) . + (let newvalue = w__25 in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \ (\ (w__28 :: 128 + bits) . + (let data = w__28 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X s w__29))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__50 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_atomicops_cas_pair : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +definition aarch64_memory_atomicops_cas_pair :: " int \ AccType \ int \('regsize::len)itself \ int \ AccType \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_atomicops_cas_pair l__45 ldacctype n regsize s stacctype t = ( + if (((l__45 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (comparevalue :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (newvalue :: 16 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \ (\ (s1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) ((s + (( 1 :: int)::ii))) :: ( 8 Word.word) M) \ (\ (s2 :: 8 bits) . + (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M) \ (\ (t1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) ((t + (( 1 :: int)::ii))) :: ( 8 Word.word) M) \ (\ (t2 :: 8 bits) . + BigEndian () \ (\ (w__0 :: bool) . + (let comparevalue = + (if w__0 then (concat_vec s1 s2 :: 16 Word.word) + else (concat_vec s2 s1 :: 16 Word.word)) in + BigEndian () \ (\ (w__1 :: bool) . + (let newvalue = + (if w__1 then (concat_vec t1 t2 :: 16 Word.word) + else (concat_vec t2 t1 :: 16 Word.word)) in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \ (\ (w__4 :: 16 + bits) . + (let data = w__4 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + BigEndian () ) \ (\ (w__5 :: bool) . + if w__5 then + (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: ( 'regsize::len)Word.word) . + (aset_X s w__6 \ + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__7 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__7)) + else + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__8 :: ( 'regsize::len)Word.word) . + (aset_X s w__8 \ + (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__9 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__9))))))))))))))))))))) + else if (((l__45 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (comparevalue :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (newvalue :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \ (\ (s1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) ((s + (( 1 :: int)::ii))) :: ( 16 Word.word) M) \ (\ (s2 :: 16 bits) . + (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M) \ (\ (t1 :: 16 bits) . + (aget_X (( 16 :: int)::ii) ((t + (( 1 :: int)::ii))) :: ( 16 Word.word) M) \ (\ (t2 :: 16 bits) . + BigEndian () \ (\ (w__10 :: bool) . + (let comparevalue = + (if w__10 then (concat_vec s1 s2 :: 32 Word.word) + else (concat_vec s2 s1 :: 32 Word.word)) in + BigEndian () \ (\ (w__11 :: bool) . + (let newvalue = + (if w__11 then (concat_vec t1 t2 :: 32 Word.word) + else (concat_vec t2 t1 :: 32 Word.word)) in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \ (\ (w__14 :: 32 + bits) . + (let data = w__14 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + BigEndian () ) \ (\ (w__15 :: bool) . + if w__15 then + (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__16 :: ( 'regsize::len)Word.word) . + (aset_X s w__16 \ + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__17 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__17)) + else + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__18 :: ( 'regsize::len)Word.word) . + (aset_X s w__18 \ + (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__19 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__19))))))))))))))))))))) + else if (((l__45 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (comparevalue :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (newvalue :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \ (\ (s1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) ((s + (( 1 :: int)::ii))) :: ( 32 Word.word) M) \ (\ (s2 :: 32 bits) . + (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M) \ (\ (t1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) ((t + (( 1 :: int)::ii))) :: ( 32 Word.word) M) \ (\ (t2 :: 32 bits) . + BigEndian () \ (\ (w__20 :: bool) . + (let comparevalue = + (if w__20 then (concat_vec s1 s2 :: 64 Word.word) + else (concat_vec s2 s1 :: 64 Word.word)) in + BigEndian () \ (\ (w__21 :: bool) . + (let newvalue = + (if w__21 then (concat_vec t1 t2 :: 64 Word.word) + else (concat_vec t2 t1 :: 64 Word.word)) in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \ (\ (w__24 :: 64 + bits) . + (let data = w__24 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + BigEndian () ) \ (\ (w__25 :: bool) . + if w__25 then + (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__26 :: ( 'regsize::len)Word.word) . + (aset_X s w__26 \ + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__27 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__27)) + else + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__28 :: ( 'regsize::len)Word.word) . + (aset_X s w__28 \ + (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__29 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__29))))))))))))))))))))) + else if (((l__45 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (comparevalue :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (newvalue :: 128 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \ (\ (s1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) ((s + (( 1 :: int)::ii))) :: ( 64 Word.word) M) \ (\ (s2 :: 64 bits) . + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \ (\ (t1 :: 64 bits) . + (aget_X (( 64 :: int)::ii) ((t + (( 1 :: int)::ii))) :: ( 64 Word.word) M) \ (\ (t2 :: 64 bits) . + BigEndian () \ (\ (w__30 :: bool) . + (let comparevalue = + (if w__30 then (concat_vec s1 s2 :: 128 Word.word) + else (concat_vec s2 s1 :: 128 Word.word)) in + BigEndian () \ (\ (w__31 :: bool) . + (let newvalue = + (if w__31 then (concat_vec t1 t2 :: 128 Word.word) + else (concat_vec t2 t1 :: 128 Word.word)) in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \ (\ (w__34 :: 128 + bits) . + (let data = w__34 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + BigEndian () ) \ (\ (w__35 :: bool) . + if w__35 then + (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__36 :: ( 'regsize::len)Word.word) . + (aset_X s w__36 \ + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__37 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__37)) + else + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: ( 'regsize::len)Word.word) . + (aset_X s w__38 \ + (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__39 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__39))))))))))))))))))))) + else if (((l__45 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 256 :: int)::ii) :: ( 256 Word.word) M) \ (\ (comparevalue :: 256 bits) . + (undefined_bitvector (( 256 :: int)::ii) :: ( 256 Word.word) M) \ (\ (newvalue :: 256 bits) . + (undefined_bitvector (( 256 :: int)::ii) :: ( 256 Word.word) M) \ (\ (data :: 256 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \ (\ (s1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) ((s + (( 1 :: int)::ii))) :: ( 128 Word.word) M) \ (\ (s2 :: 128 bits) . + (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M) \ (\ (t1 :: 128 bits) . + (aget_X (( 128 :: int)::ii) ((t + (( 1 :: int)::ii))) :: ( 128 Word.word) M) \ (\ (t2 :: 128 bits) . + BigEndian () \ (\ (w__40 :: bool) . + (let comparevalue = + (if w__40 then (concat_vec s1 s2 :: 256 Word.word) + else (concat_vec s2 s1 :: 256 Word.word)) in + BigEndian () \ (\ (w__41 :: bool) . + (let newvalue = + (if w__41 then (concat_vec t1 t2 :: 256 Word.word) + else (concat_vec t2 t1 :: 256 Word.word)) in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (aget_Mem address (((( 256 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 256 Word.word) M) \ (\ (w__44 :: 256 + bits) . + (let data = w__44 in + ((if (((data = comparevalue))) then + aset_Mem address (((( 256 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue + else return () ) \ + BigEndian () ) \ (\ (w__45 :: bool) . + if w__45 then + (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__46 :: ( 'regsize::len)Word.word) . + (aset_X s w__46 \ + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__47 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__47)) + else + (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M) \ (\ (w__48 :: ( 'regsize::len)Word.word) . + (aset_X s w__48 \ + (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + ((make_the_value regsize :: ( 'regsize::len)itself)) + :: (( 'regsize::len)Word.word) M)) \ (\ (w__49 :: ( 'regsize::len)Word.word) . + aset_X ((s + (( 1 :: int)::ii))) w__49))))))))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__45 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val AArch64_SetExclusiveMonitors : mword ty64 -> ii -> M unit*) + +definition AArch64_SetExclusiveMonitors :: "(64)Word.word \ int \((register_value),(unit),(exception))monad " where + " AArch64_SetExclusiveMonitors address size1 = ( + (let (acctype :: AccType) = AccType_ATOMIC in + (let (iswrite :: bool) = False in + (let (aligned :: bool) = (address \ ((Align__1 address size1 :: 64 Word.word))) in + AArch64_TranslateAddress address acctype iswrite aligned size1 \ (\ (memaddrdesc :: + AddressDescriptor) . + (let (_ :: unit) = (if ((IsFault memaddrdesc)) then () else () ) in + ((if(MemoryAttributes_shareable (AddressDescriptor_memattrs memaddrdesc)) then + MarkExclusiveGlobal(AddressDescriptor_paddress memaddrdesc) ((ProcessorID () )) size1 + else return () ) \ + MarkExclusiveLocal(AddressDescriptor_paddress memaddrdesc) ((ProcessorID () )) size1) \ + AArch64_MarkExclusiveVA address ((ProcessorID () )) size1))))))" + + +(*val AArch64_ExclusiveMonitorsPass : mword ty64 -> ii -> M bool*) + +definition AArch64_ExclusiveMonitorsPass :: "(64)Word.word \ int \((register_value),(bool),(exception))monad " where + " AArch64_ExclusiveMonitorsPass address size1 = ( + (let (acctype :: AccType) = AccType_ATOMIC in + (let (iswrite :: bool) = True in + (let (aligned :: bool) = (address = ((Align__1 address size1 :: 64 Word.word))) in + undefined_bool () \ (\ (secondstage :: bool) . + ((if ((\ aligned)) then + (let secondstage = False in + AArch64_AlignmentFault acctype iswrite secondstage \ (\ (w__0 :: FaultRecord) . + AArch64_Abort address w__0)) + else return () ) \ + AArch64_IsExclusiveVA address ((ProcessorID () )) size1) \ (\ (passed :: bool) . + if ((\ passed)) then return False + else + AArch64_TranslateAddress address acctype iswrite aligned size1 \ (\ (memaddrdesc :: + AddressDescriptor) . + ((if ((IsFault memaddrdesc)) then AArch64_Abort address(AddressDescriptor_fault memaddrdesc) + else return () ) \ + IsExclusiveLocal(AddressDescriptor_paddress memaddrdesc) ((ProcessorID () )) size1) \ (\ (w__1 :: + bool) . + (let passed = w__1 in + if passed then + ClearExclusiveLocal ((ProcessorID () )) \ + (if(MemoryAttributes_shareable (AddressDescriptor_memattrs memaddrdesc)) then + IsExclusiveGlobal(AddressDescriptor_paddress memaddrdesc) ((ProcessorID () )) size1 + else return passed) + else return passed)))))))))" + + +(*val AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled : unit -> M bool*) + +definition AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled :: " unit \((register_value),(bool),(exception))monad " where + " AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled _ = ( + and_boolM (return ((\ ((HaveEL EL3))))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: bool) . + if w__1 then return False + else + and_boolM (read_reg DBGEN_ref \ (\ (w__2 :: signal) . return (((w__2 = HIGH))))) + (read_reg SPIDEN_ref \ (\ (w__3 :: signal) . return (((w__3 = HIGH)))))))" + + +(*val AArch32_GenerateDebugExceptionsFrom : mword ty2 -> bool -> M bool*) + +definition AArch32_GenerateDebugExceptionsFrom :: "(2)Word.word \ bool \((register_value),(bool),(exception))monad " where + " AArch32_GenerateDebugExceptionsFrom from1 secure = ( + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (mask1 :: 1 bits) . + and_boolM (return (((from1 = EL0)))) + (ELStateUsingAArch32 EL1 secure \ (\ (w__0 :: bool) . return ((\ w__0)))) \ (\ (w__1 :: + bool) . + if w__1 then + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (w__2 :: 1 bits) . + (let mask1 = w__2 in + AArch64_GenerateDebugExceptionsFrom from1 secure mask1)) + else + or_boolM + (or_boolM + ((read_reg DBGOSLSR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) ((DoubleLockStatus () ))) ((Halted () )) \ (\ (w__8 :: + bool) . + if w__8 then return False + else + undefined_bool () \ (\ (enabled :: bool) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (spd :: 2 bits) . + if (((((HaveEL EL3)) \ secure))) then + ELUsingAArch32 EL3 \ (\ (w__9 :: bool) . + (if w__9 then + (read_reg SDCR_ref :: ( 32 Word.word) M) \ (\ (w__10 :: 32 bits) . + return ((slice0 w__10 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) + else + (read_reg MDCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__11 :: 32 bits) . + return ((slice0 w__11 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))) \ (\ (w__12 :: 2 Word.word) . + (let spd = w__12 in + (if ((((vec_of_bits [access_vec_dec spd (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + (let (enabled :: bool) = + ((vec_of_bits [access_vec_dec spd (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + return enabled) + else AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled () ) \ (\ (enabled :: bool) . + if (((from1 = EL0))) then + or_boolM (return enabled) + ((read_reg SDER_ref :: ( 32 Word.word) M) \ (\ (w__14 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) + else return enabled)))) + else + (let (enabled :: bool) = (from1 \ EL2) in + return enabled)))))))" + + +(*val AArch32_GenerateDebugExceptions : unit -> M bool*) + +definition AArch32_GenerateDebugExceptions :: " unit \((register_value),(bool),(exception))monad " where + " AArch32_GenerateDebugExceptions _ = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + IsSecure () \ (\ (w__1 :: bool) . AArch32_GenerateDebugExceptionsFrom(ProcState_EL w__0) w__1)))" + + +(*val DebugExceptionReturnSS : mword ty32 -> M (mword ty1)*) + +definition DebugExceptionReturnSS :: "(32)Word.word \((register_value),((1)Word.word),(exception))monad " where + " DebugExceptionReturnSS spsr = ( + or_boolM (or_boolM ((Halted () )) ((Restarting () ))) + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) \ EL0))))) \ (\ (w__4 :: + bool) . + assert_exp w__4 (''((Halted() || Restarting()) || ((PSTATE).EL != EL0))'') \ + ((let (SS_bit :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (ELd :: 2 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \ (\ (mask1 :: 1 bits) . + undefined_bool () \ (\ (enabled_at_dest :: bool) . + undefined_bool () \ (\ (secure :: bool) . + undefined_bool () \ (\ (valid_name :: bool) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (dest :: 2 bits) . + undefined_bool () \ (\ (enabled_at_source :: bool) . + (read_reg MDSCR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__5 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__5 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + Restarting () \ (\ (w__6 :: bool) . + (if w__6 then return False + else + UsingAArch32 () \ (\ (w__7 :: bool) . + if w__7 then AArch32_GenerateDebugExceptions () + else AArch64_GenerateDebugExceptions () )) \ (\ (enabled_at_source :: bool) . + IllegalExceptionReturn spsr \ (\ (w__10 :: bool) . + (if w__10 then + read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + (let (dest :: 2 bits) = ((ProcState_EL w__11)) in + return dest)) + else + (ELFromSPSR spsr :: ((bool * 2 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let valid_name = tup__0 in + (let dest = tup__1 in + assert_exp valid_name (''valid'') \ return dest))))) \ (\ (dest :: 2 bits) . + or_boolM ((IsSecureBelowEL3 () )) (return (((dest = EL3)))) \ (\ (w__13 :: bool) . + (let secure = w__13 in + ELUsingAArch32 dest \ (\ (w__14 :: bool) . + (if w__14 then AArch32_GenerateDebugExceptionsFrom dest secure + else + (let mask1 = ((vec_of_bits [access_vec_dec spsr (( 9 :: int)::ii)] :: 1 Word.word)) in + AArch64_GenerateDebugExceptionsFrom dest secure mask1)) \ (\ (enabled_at_dest :: bool) . + (DebugTargetFrom secure :: ( 2 Word.word) M) \ (\ (w__17 :: 2 bits) . + (let ELd = w__17 in + and_boolM + (and_boolM (ELUsingAArch32 ELd \ (\ (w__18 :: bool) . return ((\ w__18)))) + (return ((\ enabled_at_source)))) (return enabled_at_dest) \ (\ (w__20 :: bool) . + (let (SS_bit :: 1 bits) = + (if w__20 then (vec_of_bits [access_vec_dec spsr (( 21 :: int)::ii)] :: 1 Word.word) + else SS_bit) in + return SS_bit)))))))))))) + else return SS_bit))))))))))))" + + +(*val SetPSTATEFromPSR : mword ty32 -> M unit*) + +definition SetPSTATEFromPSR :: "(32)Word.word \((register_value),(unit),(exception))monad " where + " SetPSTATEFromPSR spsr__arg = ( + (let spsr = spsr__arg in + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + (DebugExceptionReturnSS spsr :: ( 1 Word.word) M) \ (\ (w__1 :: 1 bits) . + (write_reg PSTATE_ref (w__0 (| ProcState_SS := w__1 |)) \ + IllegalExceptionReturn spsr) \ (\ (w__2 :: bool) . + ((if w__2 then + read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . + write_reg PSTATE_ref (w__3 (| ProcState_IL := ((vec_of_bits [B1] :: 1 Word.word))|))) + else + read_reg PSTATE_ref \ (\ (w__4 :: ProcState) . + write_reg + PSTATE_ref + (w__4 (| ProcState_IL := ((vec_of_bits [access_vec_dec spsr (( 20 :: int)::ii)] :: 1 Word.word))|)) \ + (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + AArch32_WriteMode ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) + else + read_reg PSTATE_ref \ (\ (w__5 :: ProcState) . + (write_reg PSTATE_ref (w__5 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_EL := ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__7 :: ProcState) . + write_reg + PSTATE_ref + (w__7 (| ProcState_SP := ((vec_of_bits [access_vec_dec spsr (( 0 :: int)::ii)] :: 1 Word.word))|)))))))) \ + and_boolM + (read_reg PSTATE_ref \ (\ (w__8 :: ProcState) . + return ((((ProcState_IL w__8) = (vec_of_bits [B1] :: 1 Word.word)))))) + (read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + return ((((ProcState_nRW w__9) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (w__10 :: bool) . + (if w__10 then + ConstrainUnpredictableBool Unpredictable_ILZEROT \ (\ (w__11 :: bool) . + (let (spsr :: 32 Word.word) = + (if w__11 then + (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) spsr (( 5 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word) + else spsr) in + return spsr)) + else return spsr) \ (\ (spsr :: 32 Word.word) . + (let split_vec = ((slice0 spsr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + (write_reg PSTATE_ref (w__14 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + (write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__16 :: ProcState) . + ((if ((((ProcState_nRW w__16) = (vec_of_bits [B1] :: 1 Word.word)))) then + read_reg PSTATE_ref \ (\ (w__17 :: ProcState) . + (write_reg + PSTATE_ref + (w__17 (| ProcState_Q := ((vec_of_bits [access_vec_dec spsr (( 27 :: int)::ii)] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (RestoredITBits spsr :: ( 8 Word.word) M) \ (\ (w__19 :: 8 bits) . + (write_reg PSTATE_ref (w__18 (| ProcState_IT := w__19 |)) \ + read_reg PSTATE_ref) \ (\ (w__20 :: ProcState) . + (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice0 spsr (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__21 :: ProcState) . + write_reg + PSTATE_ref + (w__21 (| ProcState_E := ((vec_of_bits [access_vec_dec spsr (( 9 :: int)::ii)] :: 1 Word.word))|)) \ + ((let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (tup__0, tup__1, tup__2) = + ((subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_A := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg PSTATE_ref (w__23 (| ProcState_I := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + (write_reg PSTATE_ref (w__24 (| ProcState_F := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__25 :: ProcState) . + write_reg + PSTATE_ref + (w__25 (| ProcState_T := ((vec_of_bits [access_vec_dec spsr (( 5 :: int)::ii)] :: 1 Word.word))|)))))))))))))) + else + (let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_D := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + (write_reg PSTATE_ref (w__27 (| ProcState_A := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__28 :: ProcState) . + (write_reg PSTATE_ref (w__28 (| ProcState_I := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__29 :: ProcState) . + write_reg PSTATE_ref (w__29 (| ProcState_F := tup__3 |))))))))) \ + (if ((HavePANExt () )) then + read_reg PSTATE_ref \ (\ (w__30 :: ProcState) . + write_reg + PSTATE_ref + (w__30 (| ProcState_PAN := ((vec_of_bits [access_vec_dec spsr (( 22 :: int)::ii)] :: 1 Word.word))|))) + else return () )) \ + (if ((HaveUAOExt () )) then + read_reg PSTATE_ref \ (\ (w__31 :: ProcState) . + write_reg + PSTATE_ref + (w__31 (| ProcState_UAO := ((vec_of_bits [access_vec_dec spsr (( 23 :: int)::ii)] :: 1 Word.word))|))) + else return () )))))))))))))))" + + +(*val DRPSInstruction : unit -> M unit*) + +definition DRPSInstruction :: " unit \((register_value),(unit),(exception))monad " where + " DRPSInstruction _ = ( + (let (_ :: unit) = (SynchronizeContext () ) in + and_boolM + (and_boolM (return ((HaveRASExt () ))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__0 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((ConstrainUnpredictableBool Unpredictable_IESBinDebug)) \ (\ (w__3 :: bool) . + (let (_ :: unit) = + (if w__3 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All + else () ) in + (aget_SPSR () :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (SetPSTATEFromPSR w__4 \ + UsingAArch32 () ) \ (\ (w__5 :: bool) . + (if w__5 then + (undefined_bitvector (( 13 :: int)::ii) :: ( 13 Word.word) M) \ (\ (w__6 :: 13 bits) . + (let split_vec = w__6 in + (let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8, tup__9) = + ((subrange_vec_dec split_vec (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word), + (subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . + (write_reg PSTATE_ref (w__7 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__8 :: ProcState) . + (write_reg PSTATE_ref (w__8 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__9 :: ProcState) . + (write_reg PSTATE_ref (w__9 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__10 :: ProcState) . + (write_reg PSTATE_ref (w__10 (| ProcState_V := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__11 :: ProcState) . + (write_reg PSTATE_ref (w__11 (| ProcState_Q := tup__4 |)) \ + read_reg PSTATE_ref) \ (\ (w__12 :: ProcState) . + (write_reg PSTATE_ref (w__12 (| ProcState_GE := tup__5 |)) \ + read_reg PSTATE_ref) \ (\ (w__13 :: ProcState) . + (write_reg PSTATE_ref (w__13 (| ProcState_SS := tup__6 |)) \ + read_reg PSTATE_ref) \ (\ (w__14 :: ProcState) . + (write_reg PSTATE_ref (w__14 (| ProcState_A := tup__7 |)) \ + read_reg PSTATE_ref) \ (\ (w__15 :: ProcState) . + (write_reg PSTATE_ref (w__15 (| ProcState_I := tup__8 |)) \ + read_reg PSTATE_ref) \ (\ (w__16 :: ProcState) . + (write_reg PSTATE_ref (w__16 (| ProcState_F := tup__9 |)) \ + read_reg PSTATE_ref) \ (\ (w__17 :: ProcState) . + (write_reg + PSTATE_ref + (w__17 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_T := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__19 :: 32 bits) . + (write_reg DLR_ref w__19 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__20 :: 32 bits) . + write_reg DSPSR_ref w__20))))))))))))))))) + else + (undefined_bitvector (( 9 :: int)::ii) :: ( 9 Word.word) M) \ (\ (w__21 :: 9 bits) . + (let split_vec = w__21 in + (let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8) = + ((subrange_vec_dec split_vec (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), + (subrange_vec_dec split_vec (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + read_reg PSTATE_ref \ (\ (w__22 :: ProcState) . + (write_reg PSTATE_ref (w__22 (| ProcState_N := tup__0 |)) \ + read_reg PSTATE_ref) \ (\ (w__23 :: ProcState) . + (write_reg PSTATE_ref (w__23 (| ProcState_Z := tup__1 |)) \ + read_reg PSTATE_ref) \ (\ (w__24 :: ProcState) . + (write_reg PSTATE_ref (w__24 (| ProcState_C := tup__2 |)) \ + read_reg PSTATE_ref) \ (\ (w__25 :: ProcState) . + (write_reg PSTATE_ref (w__25 (| ProcState_V := tup__3 |)) \ + read_reg PSTATE_ref) \ (\ (w__26 :: ProcState) . + (write_reg PSTATE_ref (w__26 (| ProcState_SS := tup__4 |)) \ + read_reg PSTATE_ref) \ (\ (w__27 :: ProcState) . + (write_reg PSTATE_ref (w__27 (| ProcState_D := tup__5 |)) \ + read_reg PSTATE_ref) \ (\ (w__28 :: ProcState) . + (write_reg PSTATE_ref (w__28 (| ProcState_A := tup__6 |)) \ + read_reg PSTATE_ref) \ (\ (w__29 :: ProcState) . + (write_reg PSTATE_ref (w__29 (| ProcState_I := tup__7 |)) \ + read_reg PSTATE_ref) \ (\ (w__30 :: ProcState) . + (write_reg PSTATE_ref (w__30 (| ProcState_F := tup__8 |)) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__31 :: 64 bits) . + (write_reg DLR_EL0_ref w__31 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__32 :: 32 bits) . + write_reg DSPSR_EL0_ref w__32))))))))))))))) \ + UpdateEDSCRFields () ))))))" + + +(*val aarch64_branch_unconditional_dret : unit -> M unit*) + +definition aarch64_branch_unconditional_dret :: " unit \((register_value),(unit),(exception))monad " where + " aarch64_branch_unconditional_dret _ = ( DRPSInstruction () )" + + +(*val AArch64_ExceptionReturn : mword ty64 -> mword ty32 -> M unit*) + +definition AArch64_ExceptionReturn :: "(64)Word.word \(32)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_ExceptionReturn new_pc__arg spsr = ( + (let new_pc = new_pc__arg in + (let (_ :: unit) = (SynchronizeContext () ) in + undefined_bool () \ (\ (iesb_req :: bool) . + and_boolM (return ((HaveRASExt () ))) + ((aget_SCTLR__1 () :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__0 (( 21 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__1 :: bool) . + (((((if w__1 then + (let (_ :: unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in + (let iesb_req = True in + TakeUnmaskedPhysicalSErrorInterrupts iesb_req)) + else return () ) \ + SetPSTATEFromPSR spsr) \ + ClearExclusiveLocal ((ProcessorID () ))) \ + SendEventLocal () ) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (if ((((ProcState_IL w__2) = (vec_of_bits [B1] :: 1 Word.word)))) then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (let new_pc = ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) new_pc (( 32 :: int)::ii) w__3 :: 64 Word.word)) in + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (w__4 :: 2 Word.word) . + (let (new_pc :: 64 Word.word) = ((set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) w__4 :: 64 Word.word)) in + return new_pc)))) + else + UsingAArch32 () \ (\ (w__5 :: bool) . + if w__5 then + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + (let (new_pc :: 64 Word.word) = + (if ((((ProcState_T w__6) = (vec_of_bits [B0] :: 1 Word.word)))) then + (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word) + else + (set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) in + return new_pc)) + else (AArch64_BranchAddr new_pc :: ( 64 Word.word) M))) \ (\ (new_pc :: 64 Word.word) . + UsingAArch32 () \ (\ (w__8 :: bool) . + if w__8 then BranchTo ((slice0 new_pc (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) BranchType_UNKNOWN + else BranchToAddr new_pc BranchType_ERET))))))))" + + +(*val aarch64_branch_unconditional_eret : bool -> bool -> M unit*) + +definition aarch64_branch_unconditional_eret :: " bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_branch_unconditional_eret pac use_key_a = ( + (AArch64_CheckForERetTrap pac use_key_a \ + (aget_ELR__1 () :: ( 64 Word.word) M)) \ (\ (target :: 64 bits) . + (if pac then + if use_key_a then + (aget_ELR__1 () :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__1 :: 64 Word.word) . + (AuthIA w__0 w__1 :: ( 64 Word.word) M))) + else + (aget_ELR__1 () :: ( 64 Word.word) M) \ (\ (w__3 :: 64 Word.word) . + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthIB w__3 w__4 :: ( 64 Word.word) M))) + else return target) \ (\ (target :: 64 bits) . + (aget_SPSR () :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + AArch64_ExceptionReturn target w__6))))" + + +(*val AArch32_GeneralExceptionsToAArch64 : unit -> M bool*) + +definition AArch32_GeneralExceptionsToAArch64 :: " unit \((register_value),(bool),(exception))monad " where + " AArch32_GeneralExceptionsToAArch64 _ = ( + or_boolM + (and_boolM + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL0))))) + (ELUsingAArch32 EL1 \ (\ (w__1 :: bool) . return ((\ w__1))))) + (and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__3 :: bool) . return ((\ w__3))))) + (ELUsingAArch32 EL2 \ (\ (w__5 :: bool) . return ((\ w__5))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))))" + + +(*val AArch32_EnterHypMode : ExceptionRecord -> mword ty32 -> ii -> M unit*) + +definition AArch32_EnterHypMode :: " ExceptionRecord \(32)Word.word \ int \((register_value),(unit),(exception))monad " where + " AArch32_EnterHypMode exception preferred_exception_return vect_offset = ( + (let (_ :: unit) = (SynchronizeContext () ) in + and_boolM + (and_boolM (return ((HaveEL EL2))) (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + ((ELUsingAArch32 EL2)) \ (\ (w__3 :: bool) . + (assert_exp w__3 (''((HaveEL(EL2) && !(IsSecure())) && ELUsingAArch32(EL2))'') \ + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \ (\ (spsr :: 32 bits) . + (((((if ((\ (((((((ExceptionRecord_typ exception) = Exception_IRQ))) \ ((((ExceptionRecord_typ exception) = Exception_FIQ)))))))) then + AArch32_ReportHypEntry exception + else return () ) \ + AArch32_WriteMode M32_Hyp) \ + aset_SPSR spsr) \ + write_reg ELR_hyp_ref preferred_exception_return) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (read_reg HSCTLR_ref :: ( 32 Word.word) M) \ (\ (w__5 :: 32 bits) . + (write_reg + PSTATE_ref + (w__4 (| ProcState_T := ((vec_of_bits [access_vec_dec w__5 (( 30 :: int)::ii)] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__6 :: ProcState) . + (write_reg PSTATE_ref (w__6 (| ProcState_SS := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + or_boolM (return ((\ ((HaveEL EL3))))) + ((aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__7 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__7 (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__8 :: bool) . + ((if w__8 then + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + write_reg PSTATE_ref (w__9 (| ProcState_A := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + or_boolM (return ((\ ((HaveEL EL3))))) + ((aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__10 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__10 (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__11 :: bool) . + ((if w__11 then + read_reg PSTATE_ref \ (\ (w__12 :: ProcState) . + write_reg PSTATE_ref (w__12 (| ProcState_I := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + or_boolM (return ((\ ((HaveEL EL3))))) + ((aget_SCR_GEN () :: ( 32 Word.word) M) \ (\ (w__13 :: 32 Word.word) . + return ((((vec_of_bits [access_vec_dec w__13 (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__14 :: bool) . + ((if w__14 then + read_reg PSTATE_ref \ (\ (w__15 :: ProcState) . + write_reg PSTATE_ref (w__15 (| ProcState_F := ((vec_of_bits [B1] :: 1 Word.word))|))) + else return () ) \ + read_reg PSTATE_ref) \ (\ (w__16 :: ProcState) . + (read_reg HSCTLR_ref :: ( 32 Word.word) M) \ (\ (w__17 :: 32 bits) . + (write_reg + PSTATE_ref + (w__16 (| ProcState_E := ((vec_of_bits [access_vec_dec w__17 (( 25 :: int)::ii)] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__18 :: ProcState) . + (write_reg PSTATE_ref (w__18 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__19 :: ProcState) . + (write_reg + PSTATE_ref + (w__19 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \ + (read_reg HVBAR_ref :: ( 32 Word.word) M)) \ (\ (w__20 :: 32 bits) . + BranchTo + ((concat_vec ((slice0 w__20 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) vect_offset (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word)) BranchType_UNKNOWN \ + EndOfInstruction () )))))))))))))))" + + +(*val AArch32_TakeUndefInstrException__0 : unit -> M unit*) + +(*val AArch32_TakeUndefInstrException__1 : ExceptionRecord -> M unit*) + +definition AArch32_TakeUndefInstrException__1 :: " ExceptionRecord \((register_value),(unit),(exception))monad " where + " AArch32_TakeUndefInstrException__1 exception = ( + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL0)))))) + ((read_reg HCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (route_to_hyp :: bool) . + (ThisInstrAddr (( 32 :: int)::ii) () :: ( 32 Word.word) M) \ (\ (preferred_exception_return :: 32 bits) . + (let (vect_offset :: ii) = ((( 4 :: int)::ii)) in + CurrentInstrSet () \ (\ (w__5 :: InstrSet) . + (let (lr_offset :: ii) = (if (((w__5 = InstrSet_A32))) then (( 4 :: int)::ii) else (( 2 :: int)::ii)) in + read_reg PSTATE_ref \ (\ (w__6 :: ProcState) . + if ((((ProcState_EL w__6) = EL2))) then + AArch32_EnterHypMode exception preferred_exception_return vect_offset + else if route_to_hyp then AArch32_EnterHypMode exception preferred_exception_return (( 20 :: int)::ii) + else AArch32_EnterMode M32_Undef preferred_exception_return lr_offset vect_offset)))))))" + + +definition AArch32_TakeUndefInstrException__0 :: " unit \((register_value),(unit),(exception))monad " where + " AArch32_TakeUndefInstrException__0 _ = ( + ExceptionSyndrome Exception_Uncategorized \ (\ (exception :: ExceptionRecord) . + AArch32_TakeUndefInstrException__1 exception))" + + +(*val UnallocatedEncoding : unit -> M unit*) + +definition UnallocatedEncoding :: " unit \((register_value),(unit),(exception))monad " where + " UnallocatedEncoding _ = ( + and_boolM ((UsingAArch32 () )) ((AArch32_ExecutingCP10or11Instr () )) \ (\ (w__2 :: bool) . + ((if w__2 then + (read_reg FPEXC_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + write_reg + FPEXC_ref + ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + else return () ) \ + and_boolM ((UsingAArch32 () )) + (AArch32_GeneralExceptionsToAArch64 () \ (\ (w__5 :: bool) . return ((\ w__5))))) \ (\ (w__6 :: + bool) . + if w__6 then AArch32_TakeUndefInstrException__0 () + else AArch64_UndefinedFault () )))" + + +(*val aarch64_system_exceptions_runtime_hvc : mword ty16 -> M unit*) + +definition aarch64_system_exceptions_runtime_hvc :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_runtime_hvc imm = ( + or_boolM + (or_boolM (return ((\ ((HaveEL EL2))))) + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL0)))))) + (and_boolM + (read_reg PSTATE_ref \ (\ (w__2 :: ProcState) . return ((((ProcState_EL w__2) = EL1))))) + ((IsSecure () ))) \ (\ (w__5 :: bool) . + ((if w__5 then UnallocatedEncoding () + else return () ) \ + (if ((HaveEL EL3)) then + (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 8 :: int)::ii)] :: 1 Word.word)) + else + (read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((not_vec (vec_of_bits [access_vec_dec w__7 (( 29 :: int)::ii)] :: 1 Word.word) :: 1 Word.word))))) \ (\ (hvc_enable :: 1 + bits) . + if (((hvc_enable = (vec_of_bits [B0] :: 1 Word.word)))) then AArch64_UndefinedFault () + else AArch64_CallHypervisor imm)))" + + +(*val system_exceptions_runtime_hvc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_runtime_hvc_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_runtime_hvc_decode opc imm16 op2 LL = ( + write_reg unconditional_ref True \ + ((let (imm :: 16 bits) = imm16 in + aarch64_system_exceptions_runtime_hvc imm)))" + + +(*val aarch64_memory_single_general_register : forall 'regsize. Size 'regsize => AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> itself 'regsize -> ii -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_general_register :: " AccType \ int \ ExtendType \ int \ MemOp \ int \ bool \('regsize::len)itself \ int \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_register acctype l__40 extend_type m memop n postindex regsize shift signed t wback__arg = ( + if (((l__40 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X t w__5) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: + ( 'regsize::len)Word.word) . + aset_X t w__6))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))) + else if (((l__40 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__12 :: 16 + bits) . + (let data = w__12 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__13 :: + ( 'regsize::len)Word.word) . + aset_X t w__13) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))) + else if (((l__40 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__20 :: 32 + bits) . + (let data = w__20 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__21 :: + ( 'regsize::len)Word.word) . + aset_X t w__21) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__22 :: + ( 'regsize::len)Word.word) . + aset_X t w__22))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))) + else if (((l__40 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__28 :: 64 + bits) . + (let data = w__28 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__30 :: + ( 'regsize::len)Word.word) . + aset_X t w__30))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))) + else if (((l__40 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (ExtendReg (( 64 :: int)::ii) m extend_type shift :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__36 :: 128 + bits) . + (let data = w__36 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__37 :: + ( 'regsize::len)Word.word) . + aset_X t w__37) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: + ( 'regsize::len)Word.word) . + aset_X t w__38))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__40 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_single_general_immediate_unsigned : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_general_immediate_unsigned :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \('regsize::len)itself \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_immediate_unsigned acctype l__35 memop n offset postindex regsize signed t wback__arg = ( + if (((l__35 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X t w__5) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: + ( 'regsize::len)Word.word) . + aset_X t w__6))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__35 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__12 :: 16 + bits) . + (let data = w__12 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__13 :: + ( 'regsize::len)Word.word) . + aset_X t w__13) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__35 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__20 :: 32 + bits) . + (let data = w__20 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__21 :: + ( 'regsize::len)Word.word) . + aset_X t w__21) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__22 :: + ( 'regsize::len)Word.word) . + aset_X t w__22))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__35 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__28 :: 64 + bits) . + (let data = w__28 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__30 :: + ( 'regsize::len)Word.word) . + aset_X t w__30))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__35 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__36 :: 128 + bits) . + (let data = w__36 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__37 :: + ( 'regsize::len)Word.word) . + aset_X t w__37) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: + ( 'regsize::len)Word.word) . + aset_X t w__38))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__35 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_single_general_immediate_signed_postidx : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \('regsize::len)itself \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_immediate_signed_postidx acctype l__30 memop n offset postindex regsize signed t wback__arg = ( + if (((l__30 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X t w__5) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: + ( 'regsize::len)Word.word) . + aset_X t w__6))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__30 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__12 :: 16 + bits) . + (let data = w__12 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__13 :: + ( 'regsize::len)Word.word) . + aset_X t w__13) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__30 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__20 :: 32 + bits) . + (let data = w__20 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__21 :: + ( 'regsize::len)Word.word) . + aset_X t w__21) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__22 :: + ( 'regsize::len)Word.word) . + aset_X t w__22))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__30 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__28 :: 64 + bits) . + (let data = w__28 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__30 :: + ( 'regsize::len)Word.word) . + aset_X t w__30))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__30 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__36 :: 128 + bits) . + (let data = w__36 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__37 :: + ( 'regsize::len)Word.word) . + aset_X t w__37) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: + ( 'regsize::len)Word.word) . + aset_X t w__38))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__30 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_single_general_immediate_signed_pac : ii -> mword ty64 -> ii -> bool -> bool -> M unit*) + +definition aarch64_memory_single_general_immediate_signed_pac :: " int \(64)Word.word \ int \ bool \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_immediate_signed_pac n offset t use_key_a wback__arg = ( + (let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((wback \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in + assert_exp ((((((c = Constraint_WBSUPPRESS))) \ ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + (case c of + Constraint_WBSUPPRESS => + (let (wback :: bool) = False in + return (wb_unknown, wback)) + | Constraint_UNKNOWN => + (let (wb_unknown :: bool) = True in + return (wb_unknown, wback)) + | Constraint_UNDEF => UnallocatedEncoding () \ return (wb_unknown, wback) + | Constraint_NOP => EndOfInstruction () \ return (wb_unknown, wback) + )) + else return (wb_unknown, wback)) \ (\ varstup . (let ((wb_unknown :: bool), (wback :: bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (if use_key_a then + (aget_X (( 64 :: int)::ii) (( 31 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + (AuthDA address w__2 :: ( 64 Word.word) M)) + else + (aget_X (( 64 :: int)::ii) (( 31 :: int)::ii) :: ( 64 Word.word) M) \ (\ (w__4 :: 64 Word.word) . + (AuthDB address w__4 :: ( 64 Word.word) M))) \ (\ (address :: 64 bits) . + (let address = ((add_vec address offset :: 64 Word.word)) in + (aget_Mem address (( 8 :: int)::ii) AccType_NORMAL :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + (let data = w__6 in + aset_X t data \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else return address) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))" + + +(*val aarch64_memory_single_general_immediate_signed_offset_unpriv : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \('regsize::len)itself \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_immediate_signed_offset_unpriv acctype l__25 memop n offset postindex regsize signed t wback__arg = ( + if (((l__25 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X t w__5) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: + ( 'regsize::len)Word.word) . + aset_X t w__6))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__25 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__12 :: 16 + bits) . + (let data = w__12 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__13 :: + ( 'regsize::len)Word.word) . + aset_X t w__13) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__25 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__20 :: 32 + bits) . + (let data = w__20 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__21 :: + ( 'regsize::len)Word.word) . + aset_X t w__21) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__22 :: + ( 'regsize::len)Word.word) . + aset_X t w__22))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__25 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__28 :: 64 + bits) . + (let data = w__28 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__30 :: + ( 'regsize::len)Word.word) . + aset_X t w__30))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__25 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__36 :: 128 + bits) . + (let data = w__36 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__37 :: + ( 'regsize::len)Word.word) . + aset_X t w__37) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: + ( 'regsize::len)Word.word) . + aset_X t w__38))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__25 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_single_general_immediate_signed_offset_normal : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +definition aarch64_memory_single_general_immediate_signed_offset_normal :: " AccType \ int \ MemOp \ int \(64)Word.word \ bool \('regsize::len)itself \ bool \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_single_general_immediate_signed_offset_normal acctype l__20 memop n offset postindex regsize signed t wback__arg = ( + if (((l__20 = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \ (\ (w__4 :: 8 + bits) . + (let data = w__4 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__5 :: + ( 'regsize::len)Word.word) . + aset_X t w__5) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__6 :: + ( 'regsize::len)Word.word) . + aset_X t w__6))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__20 = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \ (\ (w__12 :: 16 + bits) . + (let data = w__12 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__13 :: + ( 'regsize::len)Word.word) . + aset_X t w__13) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__20 = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \ (\ (w__20 :: 32 + bits) . + (let data = w__20 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__21 :: + ( 'regsize::len)Word.word) . + aset_X t w__21) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__22 :: + ( 'regsize::len)Word.word) . + aset_X t w__22))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__20 = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \ (\ (w__28 :: 64 + bits) . + (let data = w__28 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__30 :: + ( 'regsize::len)Word.word) . + aset_X t w__30))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else if (((l__20 = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (wb_unknown :: bool) = False in + (let (rt_unknown :: bool) = False in + undefined_Constraint () \ (\ (c :: Constraint) . + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_WBSUPPRESS in + assert_exp ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return wback) \ (\ (wback :: bool) . + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ (((n = t)))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let c = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then + (if (((memop \ MemOp_PREFETCH))) then CheckSPAlignment () + else return () ) \ + (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) + | MemOp_LOAD => + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \ (\ (w__36 :: 128 + bits) . + (let data = w__36 in + if signed then + (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__37 :: + ( 'regsize::len)Word.word) . + aset_X t w__37) + else + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__38 :: + ( 'regsize::len)Word.word) . + aset_X t w__38))) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) t (( 0 :: int)::ii) :: 5 Word.word)) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () ))))))))))))))) + else + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((l__20 div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint'')))))" + + +(*val aarch64_memory_pair_simdfp_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +definition aarch64_memory_pair_simdfp_postidx :: " AccType \('datasize::len)itself \ MemOp \ int \(64)Word.word \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_pair_simdfp_postidx acctype datasize memop n offset postindex t t2 wback = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data1 :: 'datasize bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (data2 :: 'datasize bits) . + (let (rt_unknown :: bool) = False in + (if ((((((memop = MemOp_LOAD))) \ (((t = t2)))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in + assert_exp ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + (case c of + Constraint_UNKNOWN => return True + | Constraint_UNDEF => UnallocatedEncoding () \ return rt_unknown + | Constraint_NOP => EndOfInstruction () \ return rt_unknown + )) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \ (\ (w__2 :: 'datasize bits) . + (let data1 = w__2 in + (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \ (\ (w__3 :: 'datasize bits) . + (let data2 = w__3 in + aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \ + aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)))) + | MemOp_LOAD => + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__4 :: 'datasize + bits) . + (let data1 = w__4 in + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__5 :: 'datasize + bits) . + (let data2 = w__5 in + (if rt_unknown then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__6 :: 'datasize + bits) . + (let data1 = w__6 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__7 :: 'datasize + bits) . + (let (data2 :: 'datasize bits) = w__7 in + return (data1, data2))))) + else return (data1, data2)) \ (\ varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize + bits)) = varstup in + aset_V t data1 \ aset_V t2 data2)))))) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))" + + +(*val aarch64_memory_pair_simdfp_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +definition aarch64_memory_pair_simdfp_noalloc :: " AccType \('datasize::len)itself \ MemOp \ int \(64)Word.word \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_pair_simdfp_noalloc acctype datasize memop n offset postindex t t2 wback = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + CheckFPAdvSIMDEnabled64 () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data1 :: 'datasize bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (data2 :: 'datasize bits) . + (let (rt_unknown :: bool) = False in + (if ((((((memop = MemOp_LOAD))) \ (((t = t2)))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in + assert_exp ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + (case c of + Constraint_UNKNOWN => return True + | Constraint_UNDEF => UnallocatedEncoding () \ return rt_unknown + | Constraint_NOP => EndOfInstruction () \ return rt_unknown + )) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \ (\ (w__2 :: 'datasize bits) . + (let data1 = w__2 in + (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \ (\ (w__3 :: 'datasize bits) . + (let data2 = w__3 in + aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \ + aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)))) + | MemOp_LOAD => + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__4 :: 'datasize + bits) . + (let data1 = w__4 in + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__5 :: 'datasize + bits) . + (let data2 = w__5 in + (if rt_unknown then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__6 :: 'datasize + bits) . + (let data1 = w__6 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__7 :: 'datasize + bits) . + (let (data2 :: 'datasize bits) = w__7 in + return (data1, data2))))) + else return (data1, data2)) \ (\ varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize + bits)) = varstup in + aset_V t data1 \ aset_V t2 data2)))))) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))" + + +(*val aarch64_memory_pair_general_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> bool -> ii -> ii -> bool -> M unit*) + +definition aarch64_memory_pair_general_postidx :: " AccType \('datasize::len)itself \ MemOp \ int \(64)Word.word \ bool \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_pair_general_postidx acctype datasize memop n offset postindex signed t t2 wback__arg = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + (assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + ((let wback = wback__arg in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data1 :: 'datasize bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (data2 :: 'datasize bits) . + (let (rt_unknown :: bool) = False in + (let (wb_unknown :: bool) = False in + (if ((((((((((((memop = MemOp_LOAD))) \ wback))) \ ((((((t = n))) \ (((t2 = n))))))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in + assert_exp ((((((c = Constraint_WBSUPPRESS))) \ ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP)))))))))))) (''((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + (case c of + Constraint_WBSUPPRESS => + (let (wback :: bool) = False in + return (wb_unknown, wback)) + | Constraint_UNKNOWN => + (let (wb_unknown :: bool) = True in + return (wb_unknown, wback)) + | Constraint_UNDEF => UnallocatedEncoding () \ return (wb_unknown, wback) + | Constraint_NOP => EndOfInstruction () \ return (wb_unknown, wback) + )) + else return (wb_unknown, wback)) \ (\ varstup . (let ((wb_unknown :: bool), (wback :: bool)) = varstup in + (if ((((((((((((memop = MemOp_STORE))) \ wback))) \ ((((((t = n))) \ (((t2 = n))))))))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPST) in + assert_exp ((((((c = Constraint_NONE))) \ ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP)))))))))))) (''((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + (case c of + Constraint_NONE => return False + | Constraint_UNKNOWN => return True + | Constraint_UNDEF => UnallocatedEncoding () \ return rt_unknown + | Constraint_NOP => EndOfInstruction () \ return rt_unknown + )) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((memop = MemOp_LOAD))) \ (((t = t2)))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in + assert_exp ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + (case c of + Constraint_UNKNOWN => return True + | Constraint_UNDEF => UnallocatedEncoding () \ return rt_unknown + | Constraint_NOP => EndOfInstruction () \ return rt_unknown + )) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if (((rt_unknown \ (((t = n)))))) then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) + else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \ (\ (data1 :: 'datasize bits) . + (if (((rt_unknown \ (((t2 = n)))))) then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) + else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \ (\ (data2 :: 'datasize bits) . + aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \ + aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)) + | MemOp_LOAD => + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__6 :: 'datasize + bits) . + (let data1 = w__6 in + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__7 :: 'datasize + bits) . + (let data2 = w__7 in + (if rt_unknown then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__8 :: 'datasize + bits) . + (let data1 = w__8 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__9 :: 'datasize + bits) . + (let (data2 :: 'datasize bits) = w__9 in + return (data1, data2))))) + else return (data1, data2)) \ (\ varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize + bits)) = varstup in + if signed then + (SignExtend__0 data1 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__10 :: + 64 Word.word) . + (aset_X t w__10 \ + (SignExtend__0 data2 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M)) \ (\ (w__11 :: + 64 Word.word) . + aset_X t2 w__11)) + else aset_X t data1 \ aset_X t2 data2)))))) + ) \ + (if wback then + (if wb_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + return address)) \ (\ (address :: 64 bits) . + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))))))))" + + +(*val aarch64_memory_pair_general_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +definition aarch64_memory_pair_general_noalloc :: " AccType \('datasize::len)itself \ MemOp \ int \(64)Word.word \ bool \ int \ int \ bool \((register_value),(unit),(exception))monad " where + " aarch64_memory_pair_general_noalloc acctype datasize memop n offset postindex t t2 wback = ( + (let datasize = (size_itself_int datasize) in + (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \ (\ (data1 :: 'datasize bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (data2 :: 'datasize bits) . + (let (rt_unknown :: bool) = False in + (if ((((((memop = MemOp_LOAD))) \ (((t = t2)))))) then + (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in + assert_exp ((((((c = Constraint_UNKNOWN))) \ ((((((c = Constraint_UNDEF))) \ (((c = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + (case c of + Constraint_UNKNOWN => return True + | Constraint_UNDEF => UnallocatedEncoding () \ return rt_unknown + | Constraint_NOP => EndOfInstruction () \ return rt_unknown + )) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (let (address :: 64 bits) = + (if ((\ postindex)) then (add_vec address offset :: 64 Word.word) + else address) in + (case memop of + MemOp_STORE => + (if (((rt_unknown \ (((t = n)))))) then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) + else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \ (\ (data1 :: 'datasize bits) . + (if (((rt_unknown \ (((t2 = n)))))) then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) + else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \ (\ (data2 :: 'datasize bits) . + aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \ + aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)) + | MemOp_LOAD => + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__6 :: 'datasize + bits) . + (let data1 = w__6 in + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \ (\ (w__7 :: 'datasize + bits) . + (let data2 = w__7 in + (if rt_unknown then + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__8 :: 'datasize + bits) . + (let data1 = w__8 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \ (\ (w__9 :: 'datasize + bits) . + (let (data2 :: 'datasize bits) = w__9 in + return (data1, data2))))) + else return (data1, data2)) \ (\ varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize + bits)) = varstup in + aset_X t data1 \ aset_X t2 data2)))))) + ) \ + (if wback then + (let (address :: 64 bits) = + (if postindex then (add_vec address offset :: 64 Word.word) + else address) in + if (((n = (( 31 :: int)::ii)))) then aset_SP address + else aset_X n address) + else return () )))))))))))" + + +(*val aarch64_memory_exclusive_single : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*) + +definition aarch64_memory_exclusive_single :: " AccType \('datasize::len)itself \ int \ MemOp \ int \ bool \('regsize::len)itself \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_exclusive_single acctype p_1 elsize memop n pair regsize s t t2 = ( + if (((((size_itself_int p_1)) = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else if pair then + (let v = (ex_int (((( 8 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X ((int (size DebugException_VectorCatch))) t :: ( 4 Word.word) M)) \ (\ el1 . + (aget_X ((int (size DebugException_VectorCatch))) t2 :: ( 4 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__4 :: bool) . + (let (data :: 8 bits) = + (if w__4 then (concat_vec el1 el2 :: 8 Word.word) + else (concat_vec el2 el1 :: 8 Word.word)) in + return data))))) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__6 :: bool) . + (if w__6 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__8 :: + 32 Word.word) . + aset_X s w__8))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True ('''') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__9 :: 32 bits) . + aset_X t w__9) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__10 :: FaultRecord) . + AArch64_Abort address w__10))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__11 :: + 64 Word.word) . + (aset_X t w__11 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__12 :: + 64 Word.word) . + aset_X t2 w__12))) + else + (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \ (\ (w__13 :: 8 bits) . + (let data = w__13 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else if pair then + (let v = (ex_int (((( 16 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 8 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 8 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__19 :: bool) . + (let (data :: 16 bits) = + (if w__19 then (concat_vec el1 el2 :: 16 Word.word) + else (concat_vec el2 el1 :: 16 Word.word)) in + return data))))) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__21 :: bool) . + (if w__21 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__23 :: + 32 Word.word) . + aset_X s w__23))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True ('''') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__24 :: 32 bits) . + aset_X t w__24) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__25 :: FaultRecord) . + AArch64_Abort address w__25))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__26 :: + 64 Word.word) . + (aset_X t w__26 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__27 :: + 64 Word.word) . + aset_X t2 w__27))) + else + (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \ (\ (w__28 :: 16 bits) . + (let data = w__28 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else if pair then + (let v = (ex_int (((( 32 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 16 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 16 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__34 :: bool) . + (let (data :: 32 bits) = + (if w__34 then (concat_vec el1 el2 :: 32 Word.word) + else (concat_vec el2 el1 :: 32 Word.word)) in + return data))))) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__36 :: bool) . + (if w__36 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__38 :: + 32 Word.word) . + aset_X s w__38))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True ('''') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__39 :: 32 bits) . + aset_X t w__39) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__40 :: FaultRecord) . + AArch64_Abort address w__40))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__41 :: + 64 Word.word) . + (aset_X t w__41 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__42 :: + 64 Word.word) . + aset_X t2 w__42))) + else + (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \ (\ (w__43 :: 32 bits) . + (let data = w__43 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__44 :: + ( 'regsize::len)Word.word) . + aset_X t w__44)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if pair then + (let v = (ex_int (((( 64 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 32 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 32 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__49 :: bool) . + (let (data :: 64 bits) = + (if w__49 then (concat_vec el1 el2 :: 64 Word.word) + else (concat_vec el2 el1 :: 64 Word.word)) in + return data))))) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__51 :: bool) . + (if w__51 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__53 :: + 32 Word.word) . + aset_X s w__53))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True ('''') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__54 :: 32 bits) . + aset_X t w__54) + else if (((elsize = (( 32 :: int)::ii)))) then + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \ (\ (w__55 :: 64 bits) . + (let data = w__55 in + BigEndian () \ (\ (w__56 :: bool) . + if w__56 then + aset_X t + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \ + aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else + aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \ + aset_X t2 + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__57 :: FaultRecord) . + AArch64_Abort address w__57))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__58 :: + 64 Word.word) . + (aset_X t w__58 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__59 :: + 64 Word.word) . + aset_X t2 w__59))) + else + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \ (\ (w__60 :: 64 bits) . + (let data = w__60 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__61 :: + ( 'regsize::len)Word.word) . + aset_X t w__61)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else if pair then + (let v = (ex_int (((( 128 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X ((int (size address))) t :: ( 64 Word.word) M)) \ (\ el1 . + (aget_X ((int (size address))) t2 :: ( 64 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__66 :: bool) . + (let (data :: 128 bits) = + (if w__66 then (concat_vec el1 el2 :: 128 Word.word) + else (concat_vec el2 el1 :: 128 Word.word)) in + return data))))) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__68 :: bool) . + (if w__68 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__70 :: + 32 Word.word) . + aset_X s w__70))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True ('''') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__71 :: 32 bits) . + aset_X t w__71) + else if (((elsize = (( 32 :: int)::ii)))) then + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \ (\ (w__72 :: 128 bits) . + (let data = w__72 in + BigEndian () \ (\ (w__73 :: bool) . + if w__73 then + aset_X t + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \ + aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else + aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \ + aset_X t2 + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__74 :: FaultRecord) . + AArch64_Abort address w__74))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__75 :: + 64 Word.word) . + (aset_X t w__75 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__76 :: + 64 Word.word) . + aset_X t2 w__76))) + else + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \ (\ (w__77 :: 128 bits) . + (let data = w__77 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__78 :: + ( 'regsize::len)Word.word) . + aset_X t w__78)))) + ))))))))))))) + else + (let regsize = (size_itself_int regsize) in + (let datasize = (size_itself_int p_1) in + assert_exp True (''destsize constraint'') \ + ((let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))))))" + + +(*val memory_exclusive_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_exclusive_single_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_exclusive_single_decode b__0 o2 L o1 Rs o0 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 8 :: int)::ii) :: 8 itself)) (( 8 :: int)::ii) memop n + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s t t2))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 16 :: int)::ii) :: 16 itself)) (( 16 :: int)::ii) memop + n False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s t t2))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 32 :: int)::ii) :: 32 itself)) (( 32 :: int)::ii) memop + n False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s t t2))))))))))) + else + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 64 :: int)::ii) memop + n False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) s t t2))))))))))))" + + +(*val aarch64_memory_exclusive_pair : forall 'datasize 'regsize . Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*) + +definition aarch64_memory_exclusive_pair :: " AccType \('datasize::len)itself \ int \ MemOp \ int \ bool \('regsize::len)itself \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_memory_exclusive_pair acctype p_1 elsize memop n pair regsize s t t2 = ( + if (((((size_itself_int p_1)) = (( 8 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \ (\ (data :: 8 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) + else if pair then + (let v = (ex_int (((( 8 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X ((int (size DebugException_VectorCatch))) t :: ( 4 Word.word) M)) \ (\ el1 . + (aget_X ((int (size DebugException_VectorCatch))) t2 :: ( 4 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__4 :: bool) . + (let (data :: 8 bits) = + (if w__4 then (concat_vec el1 el2 :: 8 Word.word) + else (concat_vec el2 el1 :: 8 Word.word)) in + return data))))) + else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \ (\ (data :: 8 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__6 :: bool) . + (if w__6 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__8 :: + 32 Word.word) . + aset_X s w__8))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True (''datasize constraint'') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__9 :: 32 bits) . + aset_X t w__9) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__10 :: FaultRecord) . + AArch64_Abort address w__10))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__11 :: + 64 Word.word) . + (aset_X t w__11 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__12 :: + 64 Word.word) . + aset_X t2 w__12))) + else + (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \ (\ (w__13 :: 8 bits) . + (let data = w__13 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__14 :: + ( 'regsize::len)Word.word) . + aset_X t w__14)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 16 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \ (\ (data :: 16 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) + else if pair then + (let v = (ex_int (((( 16 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 8 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 8 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__19 :: bool) . + (let (data :: 16 bits) = + (if w__19 then (concat_vec el1 el2 :: 16 Word.word) + else (concat_vec el2 el1 :: 16 Word.word)) in + return data))))) + else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \ (\ (data :: 16 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__21 :: bool) . + (if w__21 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__23 :: + 32 Word.word) . + aset_X s w__23))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True (''datasize constraint'') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__24 :: 32 bits) . + aset_X t w__24) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__25 :: FaultRecord) . + AArch64_Abort address w__25))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__26 :: + 64 Word.word) . + (aset_X t w__26 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__27 :: + 64 Word.word) . + aset_X t2 w__27))) + else + (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \ (\ (w__28 :: 16 bits) . + (let data = w__28 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__29 :: + ( 'regsize::len)Word.word) . + aset_X t w__29)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 32 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (data :: 32 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) + else if pair then + (let v = (ex_int (((( 32 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 16 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 16 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__34 :: bool) . + (let (data :: 32 bits) = + (if w__34 then (concat_vec el1 el2 :: 32 Word.word) + else (concat_vec el2 el1 :: 32 Word.word)) in + return data))))) + else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \ (\ (data :: 32 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__36 :: bool) . + (if w__36 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__38 :: + 32 Word.word) . + aset_X s w__38))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True (''datasize constraint'') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__39 :: 32 bits) . + aset_X t w__39) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__40 :: FaultRecord) . + AArch64_Abort address w__40))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__41 :: + 64 Word.word) . + (aset_X t w__41 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__42 :: + 64 Word.word) . + aset_X t2 w__42))) + else + (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \ (\ (w__43 :: 32 bits) . + (let data = w__43 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__44 :: + ( 'regsize::len)Word.word) . + aset_X t w__44)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 64 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (data :: 64 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else if pair then + (let v = (ex_int (((( 64 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X v t :: ( 32 Word.word) M)) \ (\ el1 . + (aget_X ((int (size el1))) t2 :: ( 32 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__49 :: bool) . + (let (data :: 64 bits) = + (if w__49 then (concat_vec el1 el2 :: 64 Word.word) + else (concat_vec el2 el1 :: 64 Word.word)) in + return data))))) + else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \ (\ (data :: 64 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__51 :: bool) . + (if w__51 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__53 :: + 32 Word.word) . + aset_X s w__53))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True (''datasize constraint'') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__54 :: 32 bits) . + aset_X t w__54) + else if (((elsize = (( 32 :: int)::ii)))) then + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \ (\ (w__55 :: 64 bits) . + (let data = w__55 in + BigEndian () \ (\ (w__56 :: bool) . + if w__56 then + aset_X t + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \ + aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else + aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \ + aset_X t2 + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__57 :: FaultRecord) . + AArch64_Abort address w__57))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__58 :: + 64 Word.word) . + (aset_X t w__58 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__59 :: + 64 Word.word) . + aset_X t2 w__59))) + else + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \ (\ (w__60 :: 64 bits) . + (let data = w__60 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__61 :: + ( 'regsize::len)Word.word) . + aset_X t w__61)))) + ))))))))))))) + else if (((((size_itself_int p_1)) = (( 128 :: int)::ii)))) then + (let regsize = (size_itself_int regsize) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in + ((assert_exp True (''datasize constraint'') \ + assert_exp True (''dbytes constraint'')) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \ (\ (data :: 128 bits) . + (let (rt_unknown :: bool) = False in + (let (rn_unknown :: bool) = False in + ((if (((((((((memop = MemOp_LOAD))) \ pair))) \ (((t = t2)))))) then + (let (c :: Constraint) = Constraint_UNDEF in + assert_exp ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \ ((((((Constraint_UNDEF = Constraint_UNDEF))) \ (((Constraint_UNDEF = Constraint_NOP))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))'') \ + UnallocatedEncoding () ) + else return () ) \ + (if (((memop = MemOp_STORE))) then + (if ((((((s = t))) \ (((pair \ (((s = t2))))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rt_unknown) \ (\ (rt_unknown :: bool) . + (if ((((((s = n))) \ (((n \ (( 31 :: int)::ii))))))) then + (let (c :: Constraint) = Constraint_NONE in + assert_exp ((((((Constraint_NONE = Constraint_UNKNOWN))) \ ((((((Constraint_NONE = Constraint_NONE))) \ ((((((Constraint_NONE = Constraint_UNDEF))) \ (((Constraint_NONE = Constraint_NOP)))))))))))) (''((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))'') \ + return False) + else return rn_unknown) \ (\ (rn_unknown :: bool) . + return (rn_unknown, rt_unknown))) + else return (rn_unknown, rt_unknown))) \ (\ varstup . (let ((rn_unknown :: bool), (rt_unknown :: + bool)) = varstup in + (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \ (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) + else if rn_unknown then (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) + else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \ (\ (address :: 64 bits) . + undefined_bool () \ (\ (secondstage :: bool) . + undefined_bool () \ (\ (iswrite :: bool) . + (case memop of + MemOp_STORE => + (if rt_unknown then (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) + else if pair then + (let v = (ex_int (((( 128 :: int)::ii) div (( 2 :: int)::ii)))) in + (assert_exp True ('''') \ + (aget_X ((int (size address))) t :: ( 64 Word.word) M)) \ (\ el1 . + (aget_X ((int (size address))) t2 :: ( 64 Word.word) M) \ (\ el2 . + BigEndian () \ (\ (w__66 :: bool) . + (let (data :: 128 bits) = + (if w__66 then (concat_vec el1 el2 :: 128 Word.word) + else (concat_vec el2 el1 :: 128 Word.word)) in + return data))))) + else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \ (\ (data :: 128 bits) . + (let (status :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in + AArch64_ExclusiveMonitorsPass address dbytes \ (\ (w__68 :: bool) . + (if w__68 then + aset_Mem address dbytes acctype data \ (ExclusiveMonitorsStatus () :: ( 1 Word.word) M) + else return status) \ (\ (status :: 1 bits) . + (ZeroExtend__0 status ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) \ (\ (w__70 :: + 32 Word.word) . + aset_X s w__70))))) + | MemOp_LOAD => + AArch64_SetExclusiveMonitors address dbytes \ + (if pair then + assert_exp True (''datasize constraint'') \ + (if rt_unknown then + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (w__71 :: 32 bits) . + aset_X t w__71) + else if (((elsize = (( 32 :: int)::ii)))) then + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \ (\ (w__72 :: 128 bits) . + (let data = w__72 in + BigEndian () \ (\ (w__73 :: bool) . + if w__73 then + aset_X t + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \ + aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else + aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \ + aset_X t2 + ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) + else + ((if (((address \ ((Align__1 address dbytes :: 64 Word.word))))) then + (let iswrite = False in + (let secondstage = False in + AArch64_AlignmentFault acctype False False \ (\ (w__74 :: FaultRecord) . + AArch64_Abort address w__74))) + else return () ) \ + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__75 :: + 64 Word.word) . + (aset_X t w__75 \ + (aget_Mem ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype :: ( 64 Word.word) M)) \ (\ (w__76 :: + 64 Word.word) . + aset_X t2 w__76))) + else + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \ (\ (w__77 :: 128 bits) . + (let data = w__77 in + (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \ (\ (w__78 :: + ( 'regsize::len)Word.word) . + aset_X t w__78)))) + ))))))))))))) + else + (let regsize = (size_itself_int regsize) in + (let datasize = (size_itself_int p_1) in + assert_exp True (''regsize constraint'') \ + ((let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in + assert_exp True (''datasize constraint''))))))" + + +(*val memory_exclusive_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_exclusive_pair_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_exclusive_pair_decode b__0 o2 L o1 Rs o0 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_exclusive_pair acctype ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 32 :: int)::ii) memop n + True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s t t2))))))))))) + else + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (s :: ii) = (Word.uint Rs) in + (let (acctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDERED + else AccType_ATOMIC) in + (let (pair :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (elsize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (datasize :: ii) = ((( 128 :: int)::ii)) in + aarch64_memory_exclusive_pair acctype ((make_the_value (( 128 :: int)::ii) :: 128 itself)) (( 64 :: int)::ii) memop + n True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) s t t2))))))))))))" + + +(*val aarch64_integer_crc : bool -> ii -> ii -> ii -> integer -> M unit*) + +definition aarch64_integer_crc :: " bool \ int \ int \ int \ int \((register_value),(unit),(exception))monad " where + " aarch64_integer_crc crc32c d m n l__16 = ( + if (((l__16 = (( 8 :: int)::ii)))) then + ((assert_exp True ('''') \ + (if ((\ ((HaveCRCExt () )))) then UnallocatedEncoding () + else return () )) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (acc1 :: 32 bits) . + (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \ (\ (val_name :: 8 bits) . + (let (poly :: 32 bits) = + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + (if crc32c then (( 517762881 :: int)::ii) + else (( 79764919 :: int)::ii)) (( 0 :: int)::ii) + :: 32 Word.word)) in + (BitReverse acc1 :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (let (tempacc :: 40 bits) = + ((concat_vec w__0 ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) + :: 40 Word.word)) in + (BitReverse val_name :: ( 8 Word.word) M) \ (\ (w__1 :: 8 Word.word) . + (let (tempval :: 40 bits) = + ((concat_vec w__1 ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 40 Word.word)) in + (Poly32Mod2 ((xor_vec tempacc tempval :: 40 Word.word)) poly :: ( 32 Word.word) M) \ (\ (w__2 :: + 32 Word.word) . + (BitReverse w__2 :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . aset_X d w__3))))))))) + else if (((l__16 = (( 16 :: int)::ii)))) then + ((assert_exp True ('''') \ + (if ((\ ((HaveCRCExt () )))) then UnallocatedEncoding () + else return () )) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (acc1 :: 32 bits) . + (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \ (\ (val_name :: 16 bits) . + (let (poly :: 32 bits) = + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + (if crc32c then (( 517762881 :: int)::ii) + else (( 79764919 :: int)::ii)) (( 0 :: int)::ii) + :: 32 Word.word)) in + (BitReverse acc1 :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (let (tempacc :: 48 bits) = + ((concat_vec w__4 ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + :: 48 Word.word)) in + (BitReverse val_name :: ( 16 Word.word) M) \ (\ (w__5 :: 16 Word.word) . + (let (tempval :: 48 bits) = + ((concat_vec w__5 ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 48 Word.word)) in + (Poly32Mod2 ((xor_vec tempacc tempval :: 48 Word.word)) poly :: ( 32 Word.word) M) \ (\ (w__6 :: + 32 Word.word) . + (BitReverse w__6 :: ( 32 Word.word) M) \ (\ (w__7 :: 32 Word.word) . aset_X d w__7))))))))) + else if (((l__16 = (( 32 :: int)::ii)))) then + ((assert_exp True ('''') \ + (if ((\ ((HaveCRCExt () )))) then UnallocatedEncoding () + else return () )) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (acc1 :: 32 bits) . + (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \ (\ (val_name :: 32 bits) . + (let (poly :: 32 bits) = + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + (if crc32c then (( 517762881 :: int)::ii) + else (( 79764919 :: int)::ii)) (( 0 :: int)::ii) + :: 32 Word.word)) in + (BitReverse acc1 :: ( 32 Word.word) M) \ (\ (w__8 :: 32 Word.word) . + (let (tempacc :: 64 bits) = + ((concat_vec w__8 ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 64 Word.word)) in + (BitReverse val_name :: ( 32 Word.word) M) \ (\ (w__9 :: 32 Word.word) . + (let (tempval :: 64 bits) = + ((concat_vec w__9 ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 64 Word.word)) in + (Poly32Mod2 ((xor_vec tempacc tempval :: 64 Word.word)) poly :: ( 32 Word.word) M) \ (\ (w__10 :: + 32 Word.word) . + (BitReverse w__10 :: ( 32 Word.word) M) \ (\ (w__11 :: 32 Word.word) . aset_X d w__11))))))))) + else if (((l__16 = (( 64 :: int)::ii)))) then + ((assert_exp True ('''') \ + (if ((\ ((HaveCRCExt () )))) then UnallocatedEncoding () + else return () )) \ + (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \ (\ (acc1 :: 32 bits) . + (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \ (\ (val_name :: 64 bits) . + (let (poly :: 32 bits) = + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + (if crc32c then (( 517762881 :: int)::ii) + else (( 79764919 :: int)::ii)) (( 0 :: int)::ii) + :: 32 Word.word)) in + (BitReverse acc1 :: ( 32 Word.word) M) \ (\ (w__12 :: 32 Word.word) . + (let (tempacc :: 96 bits) = + ((concat_vec w__12 ((Zeros__0 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: 64 Word.word)) + :: 96 Word.word)) in + (BitReverse val_name :: ( 64 Word.word) M) \ (\ (w__13 :: 64 Word.word) . + (let (tempval :: 96 bits) = + ((concat_vec w__13 ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 96 Word.word)) in + (Poly32Mod2 ((xor_vec tempacc tempval :: 96 Word.word)) poly :: ( 32 Word.word) M) \ (\ (w__14 :: + 32 Word.word) . + (BitReverse w__14 :: ( 32 Word.word) M) \ (\ (w__15 :: 32 Word.word) . aset_X d w__15))))))))) + else assert_exp True (''''))" + + +(*val system_exceptions_debug_exception_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_debug_exception_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_debug_exception_decode opc imm16 op2 LL = ( + write_reg unconditional_ref True \ + ((let (target_level :: 2 bits) = LL in + ((if (((LL = (vec_of_bits [B0,B0] :: 2 Word.word)))) then UnallocatedEncoding () + else return () ) \ + Halted () ) \ (\ (w__0 :: bool) . + (if ((\ w__0)) then AArch64_UndefinedFault () + else return () ) \ + aarch64_system_exceptions_debug_exception target_level))))" + + +(*val system_barriers_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty2 -> mword ty5 -> M unit*) + +definition system_barriers_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(2)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_barriers_decode L op0 op1 CRn CRm opc Rt = ( + (write_reg unconditional_ref True \ + undefined_MemBarrierOp () ) \ (\ (op1 :: MemBarrierOp) . + undefined_MBReqDomain () \ (\ (domain1 :: MBReqDomain) . + undefined_MBReqTypes () \ (\ (types1 :: MBReqTypes) . + (let b__0 = opc in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return MemBarrierOp_DSB + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return MemBarrierOp_DMB + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return MemBarrierOp_ISB + else UnallocatedEncoding () \ return op1) \ (\ (op1 :: MemBarrierOp) . + (let b__3 = ((slice0 CRm (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (domain1 :: MBReqDomain) = + (if (((b__3 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then MBReqDomain_OuterShareable + else if (((b__3 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then MBReqDomain_Nonshareable + else if (((b__3 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then MBReqDomain_InnerShareable + else MBReqDomain_FullSystem) in + (let b__7 = ((slice0 CRm (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let ((domain1 :: MBReqDomain), (types1 :: MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (types1 :: MBReqTypes) = MBReqTypes_Reads in + (domain1, types1)) + else + (let ((domain1 :: MBReqDomain), (types1 :: MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (types1 :: MBReqTypes) = MBReqTypes_Writes in + (domain1, types1)) + else + (let ((domain1 :: MBReqDomain), (types1 :: MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then + (let (types1 :: MBReqTypes) = MBReqTypes_All in + (domain1, types1)) + else + (let (types1 :: MBReqTypes) = MBReqTypes_All in + (let (domain1 :: MBReqDomain) = MBReqDomain_FullSystem in + (domain1, types1)))) in + (domain1, types1))) in + (domain1, types1))) in + return ((aarch64_system_barriers domain1 op1 types1))))))))))))" + + +(*val memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(3)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode b__0 L R1 Rm b__1 S b__2 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__0 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__0 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__1 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__1 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__2 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__2 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__3 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__3 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__4 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__4 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__5 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__5 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__6 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__6 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__7 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__7 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True)))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 m memop n False ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) m memop n False ((ex_int selem)) t True)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__8 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__8 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__9 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__9 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__10 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__10 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__11 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__11 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__12 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__12 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__13 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__13 m memop n True ((ex_int selem)) t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__14 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__14 m memop n True ((ex_int selem)) t True))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__15 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__15 m memop n True ((ex_int selem)) t True))))))))))))))))" + + +(*val memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(3)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode b__0 L R1 b__1 S b__2 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__0 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__0 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__1 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__1 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__2 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__2 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__3 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__3 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__4 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__4 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__5 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__5 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__6 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__6 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__7 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__7 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__8 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__8 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__9 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__9 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__10 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__10 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__11 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__11 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__12 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__12 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__13 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__13 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__14 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__14 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__15 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__15 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__16 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__16 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__17 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) w__17 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__18 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__18 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__19 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) w__19 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__20 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__20 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__21 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) w__21 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__22 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__22 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 0 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__23 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 0 :: int)::ii) w__23 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__24 :: ii) . + undefined_int () \ (\ (w__25 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__24 w__25 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__26 :: ii) . + undefined_int () \ (\ (w__27 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__26 w__27 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__28 :: ii) . + undefined_int () \ (\ (w__29 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__28 w__29 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__30 :: ii) . + undefined_int () \ (\ (w__31 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__30 w__31 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__32 :: ii) . + undefined_int () \ (\ (w__33 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__32 w__33 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__34 :: ii) . + undefined_int () \ (\ (w__35 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__34 w__35 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__36 :: ii) . + undefined_int () \ (\ (w__37 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__36 w__37 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__38 :: ii) . + undefined_int () \ (\ (w__39 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__38 w__39 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__40 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__40 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__41 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__41 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__42 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__42 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__43 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__43 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__44 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__44 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__45 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__45 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__46 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__46 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 4 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__47 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) index1 w__47 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__48 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__48 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__49 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__49 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__50 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__50 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__51 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__51 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__52 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__52 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__53 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__53 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__54 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__54 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = + (Word.uint ((concat_vec ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word)) + (vec_of_bits [B1] :: 1 Word.word) + :: 3 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__55 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) index1 w__55 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__56 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__56 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__57 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) w__57 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__58 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__58 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__59 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) w__59 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__60 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__60 memop n False ((ex_int selem)) t False))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__61 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) w__61 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + UnallocatedEncoding () \ + ((let index1 = (Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) S :: 2 Word.word))) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__62 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) index1 w__62 memop n False ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (UnallocatedEncoding () \ + (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then UnallocatedEncoding () + else return () )) \ + ((let index1 = ((( 1 :: int)::ii)) in + (let scale = ((( 3 :: int)::ii)) in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__63 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) (( 1 :: int)::ii) w__63 memop n False ((ex_int selem)) t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__64 :: ii) . + undefined_int () \ (\ (w__65 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__64 w__65 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__66 :: ii) . + undefined_int () \ (\ (w__67 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__66 w__67 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__68 :: ii) . + undefined_int () \ (\ (w__69 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__68 w__69 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B0] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__70 :: ii) . + undefined_int () \ (\ (w__71 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__70 w__71 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 0 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + undefined_int () \ (\ (w__72 :: ii) . + undefined_int () \ (\ (w__73 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__72 w__73 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 1 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (w__74 :: ii) . + undefined_int () \ (\ (w__75 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__74 w__75 memop n True ((ex_int selem)) t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((b__1 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ (((b__2 = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 2 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (w__76 :: ii) . + undefined_int () \ (\ (w__77 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__76 w__77 memop n True ((ex_int selem)) t False)))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = + (((Word.uint ((concat_vec (vec_of_bits [B1] :: 1 Word.word) R1 :: 2 Word.word)))) + (( 1 :: int)::ii)) in + (let (replicate1 :: bool) = False in + undefined_int () \ (\ (index1 :: ii) . + (if ((((((L = (vec_of_bits [B0] :: 1 Word.word)))) \ (((S = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let scale = ((( 3 :: int)::ii)) in + (let replicate1 = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (w__78 :: ii) . + undefined_int () \ (\ (w__79 :: ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__78 w__79 memop n True ((ex_int selem)) t False)))))))))))))))))" + + +(*val memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(3)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode size1 V1 opc Rm option_name S Rn Rt = ( + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = + (Word.uint ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) size1 :: 3 Word.word))) in + ((if ((((ex_int scale)) > (( 4 :: int)::ii))) then UnallocatedEncoding () + else return () ) \ + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () )) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then scale else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + MemOp_LOAD + else MemOp_STORE) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + aarch64_memory_single_simdfp_register acctype datasize extend_type m memop n postindex shift t + wback))))))))))))))" + + +(*val memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode size1 V1 opc imm12 Rn Rt = ( + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = + (Word.uint ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) size1 :: 3 Word.word))) in + ((if ((((ex_int scale)) > (( 4 :: int)::ii))) then UnallocatedEncoding () + else return () ) \ + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M)) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 scale :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + MemOp_LOAD + else MemOp_STORE) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback))))))))))))" + + +(*val memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode size1 V1 opc imm9 Rn Rt = ( + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = + (Word.uint ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) size1 :: 3 Word.word))) in + ((if ((((ex_int scale)) > (( 4 :: int)::ii))) then UnallocatedEncoding () + else return () ) \ + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M)) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + MemOp_LOAD + else MemOp_STORE) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback)))))))))))" + + +(*val memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode size1 V1 opc imm9 Rn Rt = ( + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = + (Word.uint ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) size1 :: 3 Word.word))) in + ((if ((((ex_int scale)) > (( 4 :: int)::ii))) then UnallocatedEncoding () + else return () ) \ + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M)) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + MemOp_LOAD + else MemOp_STORE) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback)))))))))))" + + +(*val memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode size1 V1 opc imm9 Rn Rt = ( + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = + (Word.uint ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) size1 :: 3 Word.word))) in + ((if ((((ex_int scale)) > (( 4 :: int)::ii))) then UnallocatedEncoding () + else return () ) \ + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M)) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + MemOp_LOAD + else MemOp_STORE) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype datasize memop n offset + postindex t wback)))))))))))" + + +(*val memory_single_general_register_aarch64_memory_single_general_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_register_aarch64_memory_single_general_register__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(3)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_register_aarch64_memory_single_general_register__decode b__0 V1 b__1 Rm option_name S Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 0 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 :: int)::ii) extend_type m MemOp_STORE n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 0 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 0 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 0 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 1 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 :: int)::ii) extend_type m MemOp_STORE n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 1 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 1 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 1 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 2 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 :: int)::ii) extend_type m MemOp_STORE n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 2 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 2 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 2 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift True t False))))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 3 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 64 :: int)::ii) extend_type m MemOp_STORE n False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 3 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 64 :: int)::ii) extend_type m MemOp_LOAD n False + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) shift False t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 3 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__0 :: bool) . + aarch64_memory_single_general_register AccType_NORMAL (( 64 :: int)::ii) extend_type m MemOp_PREFETCH n + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift w__0 t False))))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (if ((((vec_of_bits [access_vec_dec option_name (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + ((let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (if (((S = (vec_of_bits [B1] :: 1 Word.word)))) then (( 3 :: int)::ii) else (( 0 :: int)::ii)) in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (m :: ii) = (Word.uint Rm) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__1 :: bool) . + aarch64_memory_single_general_register AccType_NORMAL (( 64 :: int)::ii) extend_type m MemOp_PREFETCH n + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) shift w__1 t False)))))))))))))))))))" + + +(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode b__0 V1 b__1 imm12 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 :: int)::ii) MemOp_STORE n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__4 :: + 64 Word.word) . + (LSL w__4 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 :: int)::ii) MemOp_STORE n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__5 :: + 64 Word.word) . + (LSL w__5 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__6 :: + 64 Word.word) . + (LSL w__6 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__7 :: + 64 Word.word) . + (LSL w__7 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__8 :: + 64 Word.word) . + (LSL w__8 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 :: int)::ii) MemOp_STORE n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__9 :: + 64 Word.word) . + (LSL w__9 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__10 :: + 64 Word.word) . + (LSL w__10 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__11 :: + 64 Word.word) . + (LSL w__11 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__12 :: + 64 Word.word) . + (LSL w__12 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 :: int)::ii) MemOp_STORE n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__13 :: + 64 Word.word) . + (LSL w__13 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__14 :: + 64 Word.word) . + (LSL w__14 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__15 :: bool) . + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 :: int)::ii) MemOp_PREFETCH n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__15 t False))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__16 :: + 64 Word.word) . + (LSL w__16 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__17 :: bool) . + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 :: int)::ii) MemOp_PREFETCH n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__17 t False)))))))))))))))))" + + +(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode b__0 V1 b__1 imm12 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 0 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__4 :: + 64 Word.word) . + (LSL w__4 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__5 :: + 64 Word.word) . + (LSL w__5 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__6 :: + 64 Word.word) . + (LSL w__6 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__7 :: + 64 Word.word) . + (LSL w__7 (( 1 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__8 :: + 64 Word.word) . + (LSL w__8 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__9 :: + 64 Word.word) . + (LSL w__9 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__10 :: + 64 Word.word) . + (LSL w__10 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__11 :: + 64 Word.word) . + (LSL w__11 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__12 :: + 64 Word.word) . + (LSL w__12 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__13 :: + 64 Word.word) . + (LSL w__13 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__14 :: + 64 Word.word) . + (LSL w__14 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__15 :: MemOp) . + undefined_bool () \ (\ (w__16 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__15 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__16 t False)))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__17 :: + 64 Word.word) . + (LSL w__17 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__18 :: MemOp) . + undefined_bool () \ (\ (w__19 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__18 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__19 t False)))))))))))))))))" + + +(*val memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode b__0 V1 b__1 imm9 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__0 :: MemOp) . + undefined_bool () \ (\ (w__1 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__0 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__1 t True))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__2 :: MemOp) . + undefined_bool () \ (\ (w__3 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__2 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__3 t True))))))))))))))))" + + +(*val memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode b__0 V1 b__1 imm9 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_STORE n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_STORE n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_STORE n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t True)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_STORE n + offset True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) MemOp_LOAD n + offset True ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t True))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__0 :: MemOp) . + undefined_bool () \ (\ (w__1 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__0 n offset + True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__1 t True))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__2 :: MemOp) . + undefined_bool () \ (\ (w__3 :: bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 :: int)::ii) w__2 n offset + True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__3 t True))))))))))))))))" + + +(*val memory_single_general_immediate_signed_pac_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty9 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_signed_pac_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(9)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_signed_pac_decode size1 V1 M S imm9 W Rn Rt = ( + (write_reg unconditional_ref True \ + (if (((((\ ((HavePACExt () )))) \ (((size1 \ (vec_of_bits [B1,B1] :: 2 Word.word))))))) + then + UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (wback :: bool) = (W = (vec_of_bits [B1] :: 1 Word.word)) in + (let (use_key_a :: bool) = (M = (vec_of_bits [B0] :: 1 Word.word)) in + (let (S10 :: 10 bits) = ((concat_vec S imm9 :: 10 Word.word)) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 S10 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 scale :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_single_general_immediate_signed_pac n offset t use_key_a wback))))))))))" + + +(*val memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode b__0 V1 b__1 imm9 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__0 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__3 :: bool) . + (let (acctype :: AccType) = (if w__3 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__6 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__6 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__7 :: bool) . + (let (acctype :: AccType) = (if w__7 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__10 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__10 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__11 :: bool) . + (let (acctype :: AccType) = (if w__11 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__12 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__12 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__14 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__14 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__15 :: bool) . + (let (acctype :: AccType) = (if w__15 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 :: int)::ii) MemOp_LOAD n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__16 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__16 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__19 :: bool) . + (let (acctype :: AccType) = (if w__19 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__20 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__22 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__22 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__23 :: bool) . + (let (acctype :: AccType) = (if w__23 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__24 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__24 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__26 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__26 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__27 :: bool) . + (let (acctype :: AccType) = (if w__27 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__28 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__28 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__30 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__30 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__31 :: bool) . + (let (acctype :: AccType) = (if w__31 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__32 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__32 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__34 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__34 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__35 :: bool) . + (let (acctype :: AccType) = (if w__35 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__36 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__36 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__38 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__38 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__39 :: bool) . + (let (acctype :: AccType) = (if w__39 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__40 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__40 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__42 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__42 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__43 :: bool) . + (let (acctype :: AccType) = (if w__43 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__44 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__44 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__46 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__46 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__47 :: bool) . + (let (acctype :: AccType) = (if w__47 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__48 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__48 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__50 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__50 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__51 :: bool) . + (let (acctype :: AccType) = (if w__51 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 :: int)::ii) MemOp_STORE n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__52 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__52 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__54 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__54 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__55 :: bool) . + (let (acctype :: AccType) = (if w__55 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False))))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__56 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__56 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__58 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__58 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__59 :: bool) . + (let (acctype :: AccType) = (if w__59 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__60 :: MemOp) . + undefined_bool () \ (\ (w__61 :: bool) . + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 :: int)::ii) w__60 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__61 t False))))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_UNPRIV in + and_boolM + (and_boolM (return (((((HaveNVExt () )) \ ((HaveEL EL2)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__62 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__62 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__64 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__64 (( 43 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__65 :: bool) . + (let (acctype :: AccType) = (if w__65 then AccType_NORMAL else acctype) in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_MemOp () \ (\ (w__66 :: MemOp) . + undefined_bool () \ (\ (w__67 :: bool) . + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 :: int)::ii) w__66 n offset + False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__67 t False))))))))))))))))))" + + +(*val memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode :: "(2)Word.word \(1)Word.word \(2)Word.word \(9)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode b__0 V1 b__1 imm9 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 :: int)::ii) MemOp_STORE + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 0 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 :: int)::ii) MemOp_LOAD n + offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 :: int)::ii) MemOp_STORE + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 1 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((False \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 :: int)::ii) MemOp_STORE + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 32 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ False))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 64 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (if (((True \ True))) then UnallocatedEncoding () + else return () ) \ + ((let regsize = ((( 32 :: int)::ii)) in + (let signed = True in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) True t False)))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_STORE in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 :: int)::ii) MemOp_STORE + n offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_LOAD in + (let regsize = ((( 64 :: int)::ii)) in + (let signed = False in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 :: int)::ii) MemOp_LOAD + n offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) False t False))))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__0 :: bool) . + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 :: int)::ii) + MemOp_PREFETCH n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__0 t False)))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (SignExtend__0 imm9 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (offset :: 64 + bits) . + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (acctype :: AccType) = AccType_NORMAL in + undefined_MemOp () \ (\ (memop :: MemOp) . + undefined_bool () \ (\ (signed :: bool) . + undefined_int () \ (\ (regsize :: ii) . + (let memop = MemOp_PREFETCH in + UnallocatedEncoding () \ + ((let (datasize :: ii) = ((( 64 :: int)::ii)) in + undefined_bool () \ (\ (w__1 :: bool) . + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 :: int)::ii) + MemOp_PREFETCH n offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__1 t False))))))))))))))))" + + +(*val memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 :: int)::ii) :: 32 itself)) memop + n offset False t t2 True)))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 :: int)::ii) :: 64 itself)) memop + n offset False t t2 True)))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 4 :: int)::ii)) in + (let (datasize :: ii) = ((( 128 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 4 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + memop n offset False t t2 True)))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 5 :: int)::ii)) in + (let (datasize :: ii) = ((( 256 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 5 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 :: int)::ii) :: 256 itself)) + memop n offset False t t2 True))))))))))))))" + + +(*val memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 :: int)::ii) :: 32 itself)) memop + n offset True t t2 True)))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 :: int)::ii) :: 64 itself)) memop + n offset True t t2 True)))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 4 :: int)::ii)) in + (let (datasize :: ii) = ((( 128 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 4 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + memop n offset True t t2 True)))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 5 :: int)::ii)) in + (let (datasize :: ii) = ((( 256 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 5 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 :: int)::ii) :: 256 itself)) + memop n offset True t t2 True))))))))))))))" + + +(*val memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 :: int)::ii) :: 32 itself)) memop + n offset False t t2 False)))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 :: int)::ii) :: 64 itself)) memop + n offset False t t2 False)))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 4 :: int)::ii)) in + (let (datasize :: ii) = ((( 128 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 4 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + memop n offset False t t2 False)))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VEC in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 5 :: int)::ii)) in + (let (datasize :: ii) = ((( 256 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 5 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 :: int)::ii) :: 256 itself)) + memop n offset False t t2 False))))))))))))))" + + +(*val memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VECSTREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False t t2 False)))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VECSTREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False t t2 False)))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VECSTREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 4 :: int)::ii)) in + (let (datasize :: ii) = ((( 128 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 4 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM + ((make_the_value (( 128 :: int)::ii) :: 128 itself)) memop n offset False t t2 False)))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_VECSTREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 5 :: int)::ii)) in + (let (datasize :: ii) = ((( 256 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 5 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM + ((make_the_value (( 256 :: int)::ii) :: 256 itself)) memop n offset False t t2 False))))))))))))))" + + +(*val memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False False t t2 True)))))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False True t t2 True)))))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False False t t2 True)))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ True))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False True t t2 True)))))))))))))))" + + +(*val memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset True False t t2 True)))))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset True True t t2 True)))))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset True False t t2 True)))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = True in + (let (postindex :: bool) = True in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ True))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset True True t t2 True)))))))))))))))" + + +(*val memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False False t t2 False)))))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False True t t2 False)))))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B0] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = False in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False False t t2 False)))))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_NORMAL in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (if ((((((((concat_vec L (vec_of_bits [B1] :: 1 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ True))) then + UnallocatedEncoding () + else return () ) \ + ((let (signed :: bool) = True in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False True t t2 False)))))))))))))))" + + +(*val memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(7)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode b__0 V1 L imm7 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_STREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__0 :: + 64 Word.word) . + (LSL w__0 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False t t2 False)))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_STREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 2 :: int)::ii)) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__1 :: + 64 Word.word) . + (LSL w__1 (( 2 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + memop n offset False t t2 False))))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_STREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__2 :: + 64 Word.word) . + (LSL w__2 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False t t2 False)))))))))))) + else + write_reg unconditional_ref True \ + ((let (wback :: bool) = False in + (let (postindex :: bool) = False in + (let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (t2 :: ii) = (Word.uint Rt2) in + (let (acctype :: AccType) = AccType_STREAM in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + UnallocatedEncoding () \ + ((let (scale :: ii) = ((( 3 :: int)::ii)) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (SignExtend__0 imm7 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \ (\ (w__3 :: + 64 Word.word) . + (LSL w__3 (( 3 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + memop n offset False t t2 False))))))))))))))" + + +(*val memory_literal_simdfp_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +definition memory_literal_simdfp_decode :: "(2)Word.word \(1)Word.word \(19)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_literal_simdfp_decode opc V1 imm19 Rt = ( + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + undefined_int () \ (\ (size1 :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (offset :: 64 bits) . + (let b__0 = opc in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 4 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 8 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return size1) \ (\ (size1 :: ii) . + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) \ (\ (w__0 :: 64 bits) . + (let offset = w__0 in + aarch64_memory_literal_simdfp offset ((ex_int size1)) t)))))))))" + + +(*val memory_atomicops_swp_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_atomicops_swp_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_atomicops_swp_decode b__0 V1 A R1 Rs o3 opc Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 8 :: int)::ii) ldacctype n ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t)))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 16 :: int)::ii) ldacctype n ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t)))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 32 :: int)::ii) ldacctype n ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t)))))))) + else + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 64 :: int)::ii) ldacctype n ((make_the_value (( 64 :: int)::ii) :: 64 itself)) s + stacctype t)))))))))" + + +(*val memory_atomicops_st_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_atomicops_st_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_atomicops_st_decode size1 V1 A R1 Rs o3 opc Rn Rt = ( + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) ((Word.uint size1))) in + (let (regsize :: ii) = (if (((((ex_int datasize)) = (( 64 :: int)::ii)))) then (( 64 :: int)::ii) else (( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = AccType_ATOMICRW in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + undefined_MemAtomicOp () \ (\ (op1 :: MemAtomicOp) . + (let b__0 = opc in + (let (op1 :: MemAtomicOp) = + (if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then MemAtomicOp_ADD + else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then MemAtomicOp_BIC + else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then MemAtomicOp_EOR + else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then MemAtomicOp_ORR + else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then MemAtomicOp_SMAX + else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then MemAtomicOp_SMIN + else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_st datasize ldacctype n op1 s stacctype)))))))))))" + + +(*val memory_atomicops_ld_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_atomicops_ld_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_atomicops_ld_decode b__0 V1 A R1 Rs o3 opc Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + undefined_MemAtomicOp () \ (\ (op1 :: MemAtomicOp) . + (let b__1 = opc in + (let (op1 :: MemAtomicOp) = + (if (((b__1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then MemAtomicOp_ADD + else if (((b__1 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then MemAtomicOp_BIC + else if (((b__1 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then MemAtomicOp_EOR + else if (((b__1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then MemAtomicOp_ORR + else if (((b__1 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then MemAtomicOp_SMAX + else if (((b__1 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then MemAtomicOp_SMIN + else if (((b__1 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 8 :: int)::ii) ldacctype n op1 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t))))))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + undefined_MemAtomicOp () \ (\ (op1 :: MemAtomicOp) . + (let b__10 = opc in + (let (op1 :: MemAtomicOp) = + (if (((b__10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then MemAtomicOp_ADD + else if (((b__10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then MemAtomicOp_BIC + else if (((b__10 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then MemAtomicOp_EOR + else if (((b__10 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then MemAtomicOp_ORR + else if (((b__10 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then MemAtomicOp_SMAX + else if (((b__10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then MemAtomicOp_SMIN + else if (((b__10 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 16 :: int)::ii) ldacctype n op1 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t))))))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + undefined_MemAtomicOp () \ (\ (op1 :: MemAtomicOp) . + (let b__19 = opc in + (let (op1 :: MemAtomicOp) = + (if (((b__19 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then MemAtomicOp_ADD + else if (((b__19 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then MemAtomicOp_BIC + else if (((b__19 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then MemAtomicOp_EOR + else if (((b__19 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then MemAtomicOp_ORR + else if (((b__19 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then MemAtomicOp_SMAX + else if (((b__19 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then MemAtomicOp_SMIN + else if (((b__19 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 32 :: int)::ii) ldacctype n op1 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s + stacctype t))))))))))) + else + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if ((((((A = (vec_of_bits [B1] :: 1 Word.word)))) \ (((Rt \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((R1 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + undefined_MemAtomicOp () \ (\ (op1 :: MemAtomicOp) . + (let b__28 = opc in + (let (op1 :: MemAtomicOp) = + (if (((b__28 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then MemAtomicOp_ADD + else if (((b__28 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then MemAtomicOp_BIC + else if (((b__28 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then MemAtomicOp_EOR + else if (((b__28 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then MemAtomicOp_ORR + else if (((b__28 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then MemAtomicOp_SMAX + else if (((b__28 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then MemAtomicOp_SMIN + else if (((b__28 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 64 :: int)::ii) ldacctype n op1 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) s + stacctype t))))))))))))" + + +(*val memory_atomicops_cas_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_atomicops_cas_single_decode :: "(2)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_atomicops_cas_single_decode b__0 o2 L o1 Rs o0 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 8 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 8 :: int)::ii) ldacctype n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s stacctype t)))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 16 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 16 :: int)::ii) ldacctype n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s stacctype t)))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 32 :: int)::ii) ldacctype n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) s stacctype t)))))))) + else + (write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 64 :: int)::ii) ldacctype n + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) s stacctype t)))))))))" + + +(*val memory_atomicops_cas_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_atomicops_cas_pair_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_atomicops_cas_pair_decode b__0 o2 L o1 Rs o0 Rt2 Rn Rt = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + (((write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + (if ((((vec_of_bits [access_vec_dec Rs (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () )) \ + (if ((((vec_of_bits [access_vec_dec Rt (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 32 :: int)::ii)) in + (let (regsize :: ii) = ((( 32 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_pair (( 32 :: int)::ii) ldacctype n ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + s stacctype t)))))))) + else + (((write_reg unconditional_ref True \ + (if ((\ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else return () )) \ + (if ((((vec_of_bits [access_vec_dec Rs (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () )) \ + (if ((((vec_of_bits [access_vec_dec Rt (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + UnallocatedEncoding () + else return () )) \ + ((let (n :: ii) = (Word.uint Rn) in + (let (t :: ii) = (Word.uint Rt) in + (let (s :: ii) = (Word.uint Rs) in + (let (datasize :: ii) = ((( 64 :: int)::ii)) in + (let (regsize :: ii) = ((( 64 :: int)::ii)) in + (let (ldacctype :: AccType) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + (let (stacctype :: AccType) = + (if (((o0 = (vec_of_bits [B1] :: 1 Word.word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_pair (( 64 :: int)::ii) ldacctype n ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + s stacctype t)))))))))" + + +(*val integer_pac_strip_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_strip_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_strip_dp_1src_decode sf S opcode2 D Rn Rd = ( + write_reg unconditional_ref True \ + ((let (data :: bool) = (D = (vec_of_bits [B1] :: 1 Word.word)) in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () )) \ + aarch64_integer_pac_strip_dp_1src d data)))))" + + +(*val integer_pac_pacib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_pacib_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacib_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_pacib_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_pacia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_pacia_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacia_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_pacia_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_pacga_dp_2src_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_pacga_dp_2src_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacga_dp_2src_decode sf op1 S Rm opcode2 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + ((let (source_is_sp :: bool) = (if (((((ex_int m)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + aarch64_integer_pac_pacga_dp_2src d m n source_is_sp))))))))" + + +(*val integer_pac_pacdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_pacdb_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacdb_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_pacdb_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_pacda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_pacda_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_pacda_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_pacda_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_autib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_autib_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autib_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_autib_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_autia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_autia_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autia_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_autia_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_autdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_autdb_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autdb_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_autdb_dp_1src d n source_is_sp))))))" + + +(*val integer_pac_autda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_pac_autda_dp_1src_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_pac_autda_dp_1src_decode sf S opcode2 Z Rn Rd = ( + write_reg unconditional_ref True \ + ((let (source_is_sp :: bool) = False in + (let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + ((if ((\ ((HavePACExt () )))) then UnallocatedEncoding () + else return () ) \ + (if (((Z = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (source_is_sp :: bool) = (if (((((ex_int n)) = (( 31 :: int)::ii)))) then True else source_is_sp) in + return source_is_sp) + else + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + return source_is_sp)) \ (\ (source_is_sp :: bool) . + aarch64_integer_pac_autda_dp_1src d n source_is_sp))))))" + + +(*val integer_insext_insert_movewide_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty16 -> mword ty5 -> M unit*) + +definition integer_insext_insert_movewide_decode :: "(1)Word.word \(2)Word.word \(2)Word.word \(16)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_insext_insert_movewide_decode sf opc hw imm16 Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (imm :: 16 bits) = imm16 in + undefined_int () \ (\ (pos :: ii) . + undefined_MoveWideOp () \ (\ (opcode :: MoveWideOp) . + (let b__0 = opc in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return MoveWideOp_N + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return MoveWideOp_Z + else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return MoveWideOp_K + else UnallocatedEncoding () \ return opcode) \ (\ (opcode :: MoveWideOp) . + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec hw (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let pos = (Word.uint ((concat_vec hw (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 6 Word.word))) in + aarch64_integer_insext_insert_movewide d datasize imm opcode pos)))))))))))" + + +(*val integer_crc_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_crc_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(3)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_crc_decode sf op1 S Rm opcode2 C b__0 Rn Rd = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + ((if ((((((sf = (vec_of_bits [B1] :: 1 Word.word)))) \ True))) then UnallocatedEncoding () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () )) \ + ((let (size1 :: ii) = ((( 8 :: int)::ii)) in + (let (crc32c :: bool) = (C = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_crc crc32c d m n (( 8 :: int)::ii)))))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + ((if ((((((sf = (vec_of_bits [B1] :: 1 Word.word)))) \ True))) then UnallocatedEncoding () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () )) \ + ((let (size1 :: ii) = ((( 16 :: int)::ii)) in + (let (crc32c :: bool) = (C = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_crc crc32c d m n (( 16 :: int)::ii)))))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + ((if ((((((sf = (vec_of_bits [B1] :: 1 Word.word)))) \ True))) then UnallocatedEncoding () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () )) \ + ((let (size1 :: ii) = ((( 32 :: int)::ii)) in + (let (crc32c :: bool) = (C = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_crc crc32c d m n (( 32 :: int)::ii)))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + ((if ((((((sf = (vec_of_bits [B1] :: 1 Word.word)))) \ False))) then + UnallocatedEncoding () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ True))) then UnallocatedEncoding () + else return () )) \ + ((let (size1 :: ii) = ((( 64 :: int)::ii)) in + (let (crc32c :: bool) = (C = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_crc crc32c d m n (( 64 :: int)::ii)))))))))" + + +(*val integer_arithmetic_rev_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_rev_decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_rev_decode sf S opcode2 opc Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + undefined_int () \ (\ (container_size :: ii) . + (let b__0 = opc in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + Unreachable () \ return container_size + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 16 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else + (if (((sf = (vec_of_bits [B0] :: 1 Word.word)))) then UnallocatedEncoding () + else return () ) \ + return (( 64 :: int)::ii)) \ (\ (container_size :: ii) . + aarch64_integer_arithmetic_rev container_size d datasize n))))))))" + + +(*val float_move_fp_select_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_move_fp_select_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(4)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_move_fp_select_decode M S typ1 Rm cond Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (condition :: 4 bits) = cond in + aarch64_float_move_fp_select condition d datasize m n)))))))))" + + +(*val float_move_fp_imm_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty8 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_move_fp_imm_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(8)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_move_fp_imm_decode M S b__0 imm8 imm5 Rd = ( + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + undefined_int () \ (\ (datasize :: ii) . + (let datasize = ((( 32 :: int)::ii)) in + (assert_exp True ('''') \ + (VFPExpandImm (( 32 :: int)::ii) imm8 :: ( 32 Word.word) M)) \ (\ (imm :: 32 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) imm))))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + undefined_int () \ (\ (datasize :: ii) . + (let datasize = ((( 64 :: int)::ii)) in + (assert_exp True ('''') \ + (VFPExpandImm (( 64 :: int)::ii) imm8 :: ( 64 Word.word) M)) \ (\ (imm :: 64 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) imm))))) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + undefined_int () \ (\ (datasize :: ii) . + ((UnallocatedEncoding () \ + assert_exp True ('''')) \ + (VFPExpandImm (( 32 :: int)::ii) imm8 :: ( 32 Word.word) M)) \ (\ (imm :: 32 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) imm)))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + undefined_int () \ (\ (datasize :: ii) . + (let datasize = ((( 16 :: int)::ii)) in + (assert_exp True ('''') \ + (VFPExpandImm (( 16 :: int)::ii) imm8 :: ( 16 Word.word) M)) \ (\ (imm :: 16 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) imm))))))" + + +(*val aarch64_float_convert_int_split : ii -> ii -> ii -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*) + +definition aarch64_float_convert_int_split :: " int \ int \ int \ int \ FPConvOp \ int \ FPRounding \ bool \((register_value),(unit),(exception))monad " where + " aarch64_float_convert_int_split d l__0 l__1 n op1 part rounding unsigned = ( + if ((((((l__0 = (( 16 :: int)::ii)))) \ (((l__1 = (( 32 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 16 :: int)::ii)))) \ (((l__1 = (( 64 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 32 :: int)::ii)))) \ (((l__1 = (( 32 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 32 :: int)::ii)))) \ (((l__1 = (( 64 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 64 :: int)::ii)))) \ (((l__1 = (( 32 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 64 :: int)::ii)))) \ (((l__1 = (( 64 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 part rounding unsigned + else if ((((((l__0 = (( 128 :: int)::ii)))) \ (((l__1 = (( 32 :: int)::ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 part rounding unsigned + else + aarch64_float_convert_int d ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 part rounding unsigned )" + + +(*val float_convert_int_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_convert_int_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(2)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_convert_int_decode sf S typ1 rmode opcode Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + undefined_int () \ (\ (part :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (if (((((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) \ (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then + UnallocatedEncoding () + else return () ) \ + return (( 128 :: int)::ii) + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return fltsize) \ (\ (fltsize :: ii) . + (let v__98 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((((subrange_vec_dec v__98 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (rounding :: FPRounding) = (FPDecodeRounding rmode) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (fltsize, op1, part, rounding, unsigned)))) + else if (((v__98 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__0) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (fltsize, op1, part, rounding, unsigned))))) + else if (((v__98 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_TIEAWAY in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (fltsize, op1, part, rounding, unsigned)))) + else if (((v__98 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then + (if ((((((((ex_int fltsize)) \ (( 16 :: int)::ii)))) \ (((((ex_int fltsize)) \ intsize)))))) then + UnallocatedEncoding () + else return () ) \ + ((let (op1 :: FPConvOp) = + (if ((((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + FPConvOp_MOV_ItoF + else FPConvOp_MOV_FtoI) in + (let (part :: ii) = ((( 0 :: int)::ii)) in + return (fltsize, op1, part, rounding, unsigned)))) + else if (((v__98 = (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then + (if ((((((((ex_int intsize)) \ (( 64 :: int)::ii)))) \ (((((ex_int fltsize)) \ (( 128 :: int)::ii))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (op1 :: FPConvOp) = + (if ((((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + FPConvOp_MOV_ItoF + else FPConvOp_MOV_FtoI) in + (let (part :: ii) = ((( 1 :: int)::ii)) in + (let (fltsize :: ii) = ((( 64 :: int)::ii)) in + return (fltsize, op1, part, rounding, unsigned))))) + else + (if (((v__98 = (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))) then + (if ((\ ((HaveFJCVTZSExt () )))) then UnallocatedEncoding () + else return () ) \ + ((let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI_JS in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + return (fltsize, op1, part, rounding, unsigned)))) \ (\ varstup . (let ((fltsize :: ii), (op1 :: + FPConvOp), (part :: ii), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + (let fltsize2 = (ex_int fltsize) in + assert_exp True ('''') \ + aarch64_float_convert_int_split d fltsize2 intsize n op1 part rounding unsigned))))))))))))))))" + + +(*val float_convert_fp_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_convert_fp_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_convert_fp_decode M S b__0 b__1 Rn Rd = ( + if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (srcsize :: ii) . + (let srcsize = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 32 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 64 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (UnallocatedEncoding () \ + assert_exp True ('''')) \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)))))))) + else if ((((((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 16 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 32 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 64 :: int)::ii) :: 64 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (srcsize :: ii) . + (let srcsize = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 64 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n + ((make_the_value (( 64 :: int)::ii) :: 64 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (UnallocatedEncoding () \ + assert_exp True ('''')) \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 64 :: int)::ii) :: 64 itself)))))))) + else if ((((((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 16 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) n + ((make_the_value (( 64 :: int)::ii) :: 64 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (dstsize :: ii) . + (let dstsize = ((( 32 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (dstsize :: ii) . + (let dstsize = ((( 64 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (srcsize :: ii) . + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (dstsize :: ii) . + (UnallocatedEncoding () \ + assert_exp True ('''')) \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself))))))) + else if ((((((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (dstsize :: ii) . + (let dstsize = ((( 16 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) n + ((make_the_value (( 32 :: int)::ii) :: 32 itself)))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 32 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 16 :: int)::ii) :: 16 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 64 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n + ((make_the_value (( 16 :: int)::ii) :: 16 itself))))))))) + else if ((((((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (srcsize :: ii) . + (let srcsize = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (UnallocatedEncoding () \ + assert_exp True ('''')) \ + aarch64_float_convert_fp d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n + ((make_the_value (( 16 :: int)::ii) :: 16 itself)))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (UnallocatedEncoding () \ + undefined_int () ) \ (\ (srcsize :: ii) . + (let srcsize = ((( 16 :: int)::ii)) in + undefined_int () \ (\ (dstsize :: ii) . + (let dstsize = ((( 16 :: int)::ii)) in + assert_exp True ('''') \ + aarch64_float_convert_fp d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) n + ((make_the_value (( 16 :: int)::ii) :: 16 itself))))))))))" + + +(*val float_convert_fix_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_convert_fix_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(2)Word.word \(3)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_convert_fix_decode b__0 S b__1 rmode opcode scale Rn Rd = ( + if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 32 :: int)::ii)) in + (if (((True \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__2 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__2 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__2 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__0) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) fracbits + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 rounding unsigned)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 64 :: int)::ii)) in + (if (((True \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__6 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__6 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__6 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__1) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) fracbits + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 rounding unsigned)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (UnallocatedEncoding () \ + (if (((True \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () )) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__10 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__10 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__10 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__2 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__2) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) fracbits + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 rounding unsigned))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 32 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 16 :: int)::ii)) in + (if (((True \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__14 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__14 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__14 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__3) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) fracbits + ((make_the_value (( 32 :: int)::ii) :: 32 itself)) n op1 rounding unsigned)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 32 :: int)::ii)) in + (if (((False \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__18 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__18 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__18 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__4 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__4) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) fracbits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 rounding unsigned)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 64 :: int)::ii)) in + (if (((False \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__22 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__22 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__22 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__5 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__5) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) fracbits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 rounding unsigned)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (UnallocatedEncoding () \ + (if (((False \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () )) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__26 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__26 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__26 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__6 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__6) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) fracbits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 rounding unsigned))))))))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (intsize :: ii) = ((( 64 :: int)::ii)) in + undefined_int () \ (\ (fltsize :: ii) . + undefined_FPConvOp () \ (\ (op1 :: FPConvOp) . + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + undefined_bool () \ (\ (unsigned :: bool) . + (let fltsize = ((( 16 :: int)::ii)) in + (if (((False \ ((((vec_of_bits [access_vec_dec scale (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then + UnallocatedEncoding () + else return () ) \ + ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in + (let b__30 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (if (((b__30 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_ZERO in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in + return (op1, rounding, unsigned)))) + else if (((b__30 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__7 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__7) in + (let (unsigned :: bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1 :: FPConvOp) = FPConvOp_CVT_ItoF in + return (op1, rounding, unsigned))))) + else UnallocatedEncoding () \ return (op1, rounding, unsigned)) \ (\ varstup . (let ((op1 :: + FPConvOp), (rounding :: FPRounding), (unsigned :: bool)) = varstup in + assert_exp True ('''') \ + aarch64_float_convert_fix d ((make_the_value (( 16 :: int)::ii) :: 16 itself)) fracbits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) n op1 rounding unsigned)))))))))))))))" + + +(*val float_compare_uncond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty2 -> M unit*) + +definition float_compare_uncond_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(2)Word.word \(5)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " float_compare_uncond_decode M S typ1 Rm op1 Rn opc = ( + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (signal_all_nans :: bool) = + ((vec_of_bits [access_vec_dec opc (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + (let (cmp_with_zero :: bool) = + ((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_float_compare_uncond cmp_with_zero datasize m n signal_all_nans)))))))))" + + +(*val float_compare_cond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +definition float_compare_cond_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(4)Word.word \(5)Word.word \(1)Word.word \(4)Word.word \((register_value),(unit),(exception))monad " where + " float_compare_cond_decode M S typ1 Rm cond Rn op1 nzcv = ( + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (signal_all_nans :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (condition :: 4 bits) = cond in + (let (flags :: 4 bits) = nzcv in + aarch64_float_compare_cond condition datasize flags m n signal_all_nans))))))))))" + + +(*val float_arithmetic_unary_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_unary_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_unary_decode M S typ1 opc Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + undefined_FPUnaryOp () \ (\ (fpop :: FPUnaryOp) . + (let b__4 = opc in + (let (fpop :: FPUnaryOp) = + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then FPUnaryOp_MOV + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then FPUnaryOp_ABS + else if (((b__4 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then FPUnaryOp_NEG + else FPUnaryOp_SQRT) in + aarch64_float_arithmetic_unary d datasize fpop n))))))))))" + + +(*val float_arithmetic_round_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_round_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_round_decode M S typ1 rmode Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (exact :: bool) = False in + undefined_FPRounding () \ (\ (rounding :: FPRounding) . + (let v__101 = rmode in + (if (((((subrange_vec_dec v__101 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then + (let (rounding :: FPRounding) = (FPDecodeRounding ((slice0 rmode (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + return (exact, rounding)) + else if (((v__101 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (let (rounding :: FPRounding) = FPRounding_TIEAWAY in + return (exact, rounding)) + else if (((v__101 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + UnallocatedEncoding () \ return (exact, rounding) + else if (((v__101 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__0 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__0) in + (let (exact :: bool) = True in + return (exact, rounding)))) + else + (read_reg FPCR_ref :: ( 32 Word.word) M) \ (\ (w__1 :: 32 Word.word) . + (let (rounding :: FPRounding) = (FPRoundingMode w__1) in + return (exact, rounding)))) \ (\ varstup . (let ((exact :: bool), (rounding :: FPRounding)) = varstup in + aarch64_float_arithmetic_round d datasize exact n rounding))))))))))))" + + +(*val float_arithmetic_mul_product_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_mul_product_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_mul_product_decode M S typ1 Rm op1 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (negated :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_float_arithmetic_mul_product d datasize m n negated)))))))))" + + +(*val float_arithmetic_mul_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_mul_addsub_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(1)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_mul_addsub_decode M S typ1 o1 Rm o0 Ra Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (a :: ii) = (Word.uint Ra) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (opa_neg :: bool) = (o1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (op1_neg :: bool) = (o0 \ o1) in + aarch64_float_arithmetic_mul_addsub a d datasize m n op1_neg opa_neg)))))))))))" + + +(*val float_arithmetic_maxmin_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_maxmin_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_maxmin_decode M S typ1 Rm op1 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + undefined_FPMaxMinOp () \ (\ (operation :: FPMaxMinOp) . + (let b__4 = op1 in + (let (operation :: FPMaxMinOp) = + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then FPMaxMinOp_MAX + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then FPMaxMinOp_MIN + else if (((b__4 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then FPMaxMinOp_MAXNUM + else FPMaxMinOp_MINNUM) in + aarch64_float_arithmetic_maxmin d datasize m n operation)))))))))))" + + +(*val float_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_div_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_div_decode M S typ1 Rm Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + aarch64_float_arithmetic_div d datasize m n))))))))" + + +(*val float_arithmetic_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition float_arithmetic_addsub_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " float_arithmetic_addsub_decode M S typ1 Rm op1 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + undefined_int () \ (\ (datasize :: ii) . + (let b__0 = typ1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + UnallocatedEncoding () \ return datasize + else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) + else UnallocatedEncoding () \ return datasize) \ (\ (datasize :: ii) . + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_float_arithmetic_addsub d datasize m n sub_op)))))))))" + + +(*val branch_unconditional_register_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition branch_unconditional_register_decode :: "(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " branch_unconditional_register_decode Z opc op1 op2 op3 A M Rn Rm = ( + write_reg unconditional_ref True \ + ((let (n :: ii) = (Word.uint Rn) in + undefined_BranchType () \ (\ (branch_type :: BranchType) . + (let (m :: ii) = (Word.uint Rm) in + (let (pac :: bool) = (A = (vec_of_bits [B1] :: 1 Word.word)) in + (let (use_key_a :: bool) = (M = (vec_of_bits [B0] :: 1 Word.word)) in + (let (source_is_sp :: bool) = + ((((Z = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((ex_int m)) = (( 31 :: int)::ii))))) in + (if (((((\ pac)) \ (((((ex_int m)) \ (( 0 :: int)::ii))))))) then UnallocatedEncoding () + else if (((pac \ ((\ ((HavePACExt () ))))))) then UnallocatedEncoding () + else return () ) \ + ((let b__0 = op1 in + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return BranchType_JMP + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return BranchType_CALL + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return BranchType_RET + else UnallocatedEncoding () \ return branch_type) \ (\ (branch_type :: BranchType) . + (if pac then + (if ((((((Z = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((ex_int m)) \ (( 31 :: int)::ii))))))) + then + UnallocatedEncoding () + else return () ) \ + (if (((branch_type = BranchType_RET))) then + (if (((((ex_int n)) \ (( 31 :: int)::ii)))) then UnallocatedEncoding () + else return () ) \ + ((let (n :: ii) = ((( 30 :: int)::ii)) in + (let (source_is_sp :: bool) = True in + return (n, source_is_sp)))) + else return (n, source_is_sp)) + else return (n, source_is_sp)) \ (\ varstup . (let ((n :: ii), (source_is_sp :: bool)) = varstup in + aarch64_branch_unconditional_register branch_type m n pac source_is_sp use_key_a)))))))))))))" + + +(*val branch_unconditional_eret_decode : mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +definition branch_unconditional_eret_decode :: "(4)Word.word \(5)Word.word \(4)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " branch_unconditional_eret_decode opc op2 op3 A M Rn op4 = ( + (write_reg unconditional_ref True \ + read_reg PSTATE_ref) \ (\ (w__0 :: ProcState) . + (if ((((ProcState_EL w__0) = EL0))) then UnallocatedEncoding () + else return () ) \ + ((let (pac :: bool) = (A = (vec_of_bits [B1] :: 1 Word.word)) in + (let (use_key_a :: bool) = (M = (vec_of_bits [B0] :: 1 Word.word)) in + ((if (((((\ pac)) \ (((op4 \ (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + UnallocatedEncoding () + else if (((pac \ (((((\ ((HavePACExt () )))) \ (((op4 \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))))))) then + UnallocatedEncoding () + else return () ) \ + (if (((Rn \ (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))) then UnallocatedEncoding () + else return () )) \ + aarch64_branch_unconditional_eret pac use_key_a)))))" + + +(*val branch_unconditional_dret_decode : mword ty4 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition branch_unconditional_dret_decode :: "(4)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " branch_unconditional_dret_decode opc op2 op3 Rt op4 = ( + (write_reg unconditional_ref True \ + or_boolM (Halted () \ (\ (w__0 :: bool) . return ((\ w__0)))) + (read_reg PSTATE_ref \ (\ (w__1 :: ProcState) . return ((((ProcState_EL w__1) = EL0)))))) \ (\ (w__2 :: + bool) . + (if w__2 then UnallocatedEncoding () else return () ) \ aarch64_branch_unconditional_dret () ))" + + +(*val AArch64_CheckSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> mword ty1 -> M unit*) + +definition AArch64_CheckSystemAccess :: "(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \(1)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_CheckSystemAccess op0 op1 crn crm op2 rt read = ( + (let (unallocated :: bool) = False in + (let (need_secure :: bool) = False in + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \ (\ (min_EL :: 2 bits) . + undefined_bool () \ (\ (rcs_el0_trap :: bool) . + and_boolM + (and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__0 :: bool) . return ((\ w__0))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 20 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + (return (((((and_vec op0 (vec_of_bits [B0,B1] :: 2 Word.word) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))) + (return (((((and_vec crn (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) :: 4 Word.word)) = (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word))))) \ (\ (w__5 :: bool) . + (if w__5 then + undefined_bool () \ (\ (w__6 :: bool) . + (let rcs_el0_trap = w__6 in + and_boolM + (read_reg PSTATE_ref \ (\ (w__7 :: ProcState) . return ((((ProcState_EL w__7) = EL0))))) + (return rcs_el0_trap) \ (\ (w__8 :: bool) . + if w__8 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else + read_reg PSTATE_ref \ (\ (w__9 :: ProcState) . + if ((((ProcState_EL w__9) = EL1))) then + AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else return () )))) + else return () ) \ + ((let v__103 = op1 in + (if (((((subrange_vec_dec v__103 (( 2 :: int)::ii) (( 1 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (min_EL :: 2 bits) = EL1 in + return (min_EL, need_secure)) + else if (((v__103 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (let (min_EL :: 2 bits) = EL1 in + return (min_EL, need_secure)) + else if (((v__103 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (let (min_EL :: 2 bits) = EL0 in + return (min_EL, need_secure)) + else if (((v__103 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (let (min_EL :: 2 bits) = EL2 in + return (min_EL, need_secure)) + else if (((v__103 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (if ((\ ((HaveVirtHostExt () )))) then UnallocatedEncoding () + else return () ) \ + ((let (min_EL :: 2 bits) = EL2 in + return (min_EL, need_secure))) + else + (let ((min_EL :: 2 bits), (need_secure :: bool)) = + (if (((v__103 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (let (min_EL :: 2 bits) = EL3 in + (min_EL, need_secure)) + else + (let (min_EL :: 2 bits) = EL1 in + (let (need_secure :: bool) = True in + (min_EL, need_secure)))) in + return (min_EL, need_secure))) \ (\ varstup . (let ((min_EL :: 2 bits), (need_secure :: bool)) = varstup in + read_reg PSTATE_ref \ (\ (w__10 :: ProcState) . + ((if ((((Word.uint(ProcState_EL w__10))) < ((Word.uint min_EL)))) then + and_boolM + (and_boolM + (and_boolM + (and_boolM + (and_boolM + (read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + return ((((ProcState_EL w__11) = EL1))))) (return (((min_EL = EL2))))) + (return ((HaveNVExt () )))) + (IsSecure () \ (\ (w__14 :: bool) . return ((\ w__14))))) (return ((HaveEL EL2)))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__17 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__17 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__18 :: bool) . + if w__18 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else UnallocatedEncoding () ) + else + and_boolM (return need_secure) (IsSecure () \ (\ (w__19 :: bool) . return ((\ w__19)))) \ (\ (w__20 :: + bool) . + if w__20 then UnallocatedEncoding () + else + AArch64_CheckUnallocatedSystemAccess op0 op1 crn crm op2 read \ (\ (w__21 :: bool) . + if w__21 then UnallocatedEncoding () + else return () ))) \ + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M)) \ (\ (target_el :: 2 bits) . + undefined_bool () \ (\ (take_trap :: bool) . + (AArch64_CheckAdvSIMDFPSystemRegisterTraps op0 op1 crn crm op2 read :: ((bool * 2 Word.word)) M) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let take_trap = tup__0 in + (let target_el = tup__1 in + ((if take_trap then AArch64_AdvSIMDFPAccessTrap target_el + else return () ) \ + (AArch64_CheckSystemRegisterTraps op0 op1 crn crm op2 read :: ((bool * 2 Word.word)) M)) \ (\ varstup . (let (tup__0, tup__1) = varstup in + (let take_trap = tup__0 in + (let target_el = tup__1 in + if take_trap then AArch64_SystemRegisterTrap target_el op0 op2 op1 crn rt crm read + else return () )))))))))))))))))))))" + + +(*val system_sysops_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition system_sysops_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_sysops_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + AArch64_CheckSystemAccess (vec_of_bits [B0,B1] :: 2 Word.word) op1 CRn CRm op2 Rt L) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (sys_op0 :: ii) = ((( 1 :: int)::ii)) in + (let (sys_op1 :: ii) = (Word.uint op1) in + (let (sys_op2 :: ii) = (Word.uint op2) in + (let (sys_crn :: ii) = (Word.uint CRn) in + (let (sys_crm :: ii) = (Word.uint CRm) in + (let (has_result :: bool) = (L = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))))))))" + + +(*val system_register_system_decode : mword ty1 -> mword ty1 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition system_register_system_decode :: "(1)Word.word \(1)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_register_system_decode L o0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + AArch64_CheckSystemAccess ((concat_vec (vec_of_bits [B1] :: 1 Word.word) o0 :: 2 Word.word)) op1 CRn + CRm op2 Rt L) \ + ((let (t :: ii) = (Word.uint Rt) in + (let (sys_op0 :: ii) = ((( 2 :: int)::ii) + ((Word.uint o0))) in + (let (sys_op1 :: ii) = (Word.uint op1) in + (let (sys_op2 :: ii) = (Word.uint op2) in + (let (sys_crn :: ii) = (Word.uint CRn) in + (let (sys_crm :: ii) = (Word.uint CRm) in + (let (read :: bool) = (L = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))))))))" + + +(*val system_register_cpsr_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +definition system_register_cpsr_decode :: "(1)Word.word \(2)Word.word \(3)Word.word \(4)Word.word \(4)Word.word \(3)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " system_register_cpsr_decode L op0 op1 CRn CRm op2 Rt = ( + (write_reg unconditional_ref True \ + AArch64_CheckSystemAccess (vec_of_bits [B0,B0] :: 2 Word.word) op1 + (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) CRm op2 (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) + (vec_of_bits [B0] :: 1 Word.word)) \ + ((let (operand :: 4 bits) = CRm in + undefined_PSTATEField () \ (\ (field' :: PSTATEField) . + (let b__0 = ((concat_vec op1 op2 :: 6 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (if ((\ ((HaveUAOExt () )))) then UnallocatedEncoding () + else return () ) \ + return PSTATEField_UAO + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (if ((\ ((HavePANExt () )))) then UnallocatedEncoding () + else return () ) \ + return PSTATEField_PAN + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + return PSTATEField_SP + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0] :: 6 Word.word)))) then + return PSTATEField_DAIFSet + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B1] :: 6 Word.word)))) then + return PSTATEField_DAIFClr + else UnallocatedEncoding () \ return field') \ (\ (field' :: PSTATEField) . + and_boolM + (and_boolM (return (((op1 = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))) + (read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . return ((((ProcState_EL w__0) = EL0)))))) + (or_boolM ((IsInHost () )) + ((read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \ (\ (w__3 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 9 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \ (\ (w__5 :: bool) . + (if w__5 then + AArch64_SystemRegisterTrap EL1 (vec_of_bits [B0,B0] :: 2 Word.word) op2 op1 + (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) CRm + (vec_of_bits [B0] :: 1 Word.word) + else return () ) \ + aarch64_system_register_cpsr field' operand)))))))" + + +(*val AArch64_CheckForSMCUndefOrTrap : mword ty16 -> M unit*) + +definition AArch64_CheckForSMCUndefOrTrap :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " AArch64_CheckForSMCUndefOrTrap imm = ( + read_reg PSTATE_ref \ (\ (w__0 :: ProcState) . + ((if ((((ProcState_EL w__0) = EL0))) then UnallocatedEncoding () + else return () ) \ + undefined_bool () ) \ (\ (route_to_el2 :: bool) . + (if ((\ ((HaveEL EL3)))) then + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__1 :: bool) . return ((\ w__1))))) + (read_reg PSTATE_ref \ (\ (w__3 :: ProcState) . return ((((ProcState_EL w__3) = EL1))))) \ (\ (w__4 :: + bool) . + if w__4 then + and_boolM + (and_boolM (return ((HaveNVExt () ))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 42 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \ (\ (w__8 :: bool) . + if w__8 then return True + else UnallocatedEncoding () \ return route_to_el2) + else UnallocatedEncoding () \ return route_to_el2) + else + and_boolM + (and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \ (\ (w__9 :: bool) . return ((\ w__9))))) + (read_reg PSTATE_ref \ (\ (w__11 :: ProcState) . + return ((((ProcState_EL w__11) = EL1)))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \ (\ (w__13 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) \ (\ (route_to_el2 :: bool) . + undefined_ExceptionRecord () \ (\ (exception :: ExceptionRecord) . + undefined_int () \ (\ (vect_offset :: ii) . + if route_to_el2 then + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \ (\ (preferred_exception_return :: 64 bits) . + (let vect_offset = ((( 0 :: int)::ii)) in + ExceptionSyndrome Exception_MonitorCall \ (\ (w__15 :: ExceptionRecord) . + (let exception = w__15 in + (let (tmp_40 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in + (let tmp_40 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_40 (( 0 :: int)::ii) imm :: 25 Word.word)) in + (let exception = ((exception (| ExceptionRecord_syndrome := tmp_40 |))) in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))))) + else return () ))))))" + + +(*val aarch64_system_exceptions_runtime_smc : mword ty16 -> M unit*) + +definition aarch64_system_exceptions_runtime_smc :: "(16)Word.word \((register_value),(unit),(exception))monad " where + " aarch64_system_exceptions_runtime_smc imm = ( + (AArch64_CheckForSMCUndefOrTrap imm \ + (read_reg SCR_EL3_ref :: ( 32 Word.word) M)) \ (\ (w__0 :: 32 bits) . + if ((((vec_of_bits [access_vec_dec w__0 (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then + AArch64_UndefinedFault () + else AArch64_CallSecureMonitor imm))" + + +(*val system_exceptions_runtime_smc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +definition system_exceptions_runtime_smc_decode :: "(3)Word.word \(16)Word.word \(3)Word.word \(2)Word.word \((register_value),(unit),(exception))monad " where + " system_exceptions_runtime_smc_decode opc imm16 op2 LL = ( + write_reg unconditional_ref True \ + ((let (imm :: 16 bits) = imm16 in + aarch64_system_exceptions_runtime_smc imm)))" + + +(*val ReservedValue : unit -> M unit*) + +definition ReservedValue :: " unit \((register_value),(unit),(exception))monad " where + " ReservedValue _ = ( + and_boolM ((UsingAArch32 () )) + (AArch32_GeneralExceptionsToAArch64 () \ (\ (w__1 :: bool) . return ((\ w__1)))) \ (\ (w__2 :: + bool) . + if w__2 then AArch32_TakeUndefInstrException__0 () + else AArch64_UndefinedFault () ))" + + +(*val memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode :: "(1)Word.word \(1)Word.word \(5)Word.word \(4)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode b__0 L Rm opcode b__1 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 8 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__2 = opcode in + (if (((b__2 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 8 :: int)::ii) :: 8 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 16 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__11 = opcode in + (if (((b__11 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 16 :: int)::ii) :: 16 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 32 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__20 = opcode in + (if (((b__20 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 64 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__29 = opcode in + (if (((b__29 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((True \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 8 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__38 = opcode in + (if (((b__38 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 8 :: int)::ii) :: 8 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 16 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__47 = opcode in + (if (((b__47 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 16 :: int)::ii) :: 16 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 32 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__56 = opcode in + (if (((b__56 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))) + else + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (wback :: bool) = True in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 64 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__65 = opcode in + (if (((b__65 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + (if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t True))))))))))))))" + + +(*val memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +definition memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode :: "(1)Word.word \(1)Word.word \(4)Word.word \(2)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode b__0 L opcode b__1 Rn Rt = ( + if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 8 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__2 = opcode in + (if (((b__2 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__2 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__0 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__0 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 16 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__11 = opcode in + (if (((b__11 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__11 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__1 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__1 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 32 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__20 = opcode in + (if (((b__20 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__20 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__2 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__2 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + (let (elements :: ii) = ((( 64 :: int)::ii) div (( 64 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__29 = opcode in + (if (((b__29 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__29 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((True \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__3 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((ex_int elements)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__3 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 8 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 8 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__38 = opcode in + (if (((b__38 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__38 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__4 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 8 :: int)::ii) :: 8 itself)) w__4 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 16 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 16 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__47 = opcode in + (if (((b__47 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__47 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__5 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 16 :: int)::ii) :: 16 itself)) w__5 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else if ((((((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) \ (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 32 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 32 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__56 = opcode in + (if (((b__56 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__56 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__6 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) w__6 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))) + else + write_reg unconditional_ref True \ + ((let (t :: ii) = (Word.uint Rt) in + (let (n :: ii) = (Word.uint Rn) in + undefined_int () \ (\ (m :: ii) . + (let (wback :: bool) = False in + (let (memop :: MemOp) = + (if (((L = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD + else MemOp_STORE) in + (let (esize :: ii) = ((( 64 :: int)::ii)) in + (let (elements :: ii) = ((( 128 :: int)::ii) div (( 64 :: int)::ii)) in + undefined_int () \ (\ (rpt :: ii) . + undefined_int () \ (\ (selem :: ii) . + (let b__65 = opcode in + (if (((b__65 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 4 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 4 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 3 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 3 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 1 :: int)::ii)) in + (let (selem :: ii) = ((( 2 :: int)::ii)) in + return (rpt, selem))) + else if (((b__65 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then + (let (rpt :: ii) = ((( 2 :: int)::ii)) in + (let (selem :: ii) = ((( 1 :: int)::ii)) in + return (rpt, selem))) + else UnallocatedEncoding () \ return (rpt, selem)) \ (\ varstup . (let ((rpt :: ii), (selem :: + ii)) = varstup in + ((if (((False \ (((((ex_int selem)) \ (( 1 :: int)::ii))))))) then ReservedValue () + else return () ) \ + undefined_int () ) \ (\ (w__7 :: ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 :: int)::ii) :: 128 itself)) + ((ex_int elements)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) w__7 memop n ((ex_int rpt)) + ((ex_int selem)) t False)))))))))))))))" + + +(*val integer_logical_shiftedreg_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_logical_shiftedreg_decode :: "(1)Word.word \(2)Word.word \(2)Word.word \(1)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_logical_shiftedreg_decode sf opc shift N Rm imm6 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + undefined_bool () \ (\ (setflags :: bool) . + undefined_LogicalOp () \ (\ (op1 :: LogicalOp) . + (let b__0 = opc in + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_ORR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_EOR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = True in + (op1, setflags)))) in + (op1, setflags))) in + (op1, setflags))) in + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec imm6 (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + ReservedValue () + else return () ) \ + ((let (shift_type :: ShiftType) = (DecodeShift shift) in + (let (shift_amount :: ii) = (Word.uint imm6) in + (let (invert :: bool) = (N = (vec_of_bits [B1] :: 1 Word.word)) in + aarch64_integer_logical_shiftedreg d datasize invert m n op1 setflags shift_amount shift_type))))))))))))))" + + +(*val integer_insext_extract_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_insext_extract_immediate_decode :: "(1)Word.word \(2)Word.word \(1)Word.word \(1)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_insext_extract_immediate_decode sf op21 N o0 Rm imms Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + undefined_int () \ (\ (lsb1 :: ii) . + ((if (((N \ sf))) then UnallocatedEncoding () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec imms (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + ReservedValue () + else return () )) \ + ((let lsb1 = (Word.uint imms) in + aarch64_integer_insext_extract_immediate d datasize lsb1 m n)))))))))" + + +(*val integer_arithmetic_addsub_shiftedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_addsub_shiftedreg_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_addsub_shiftedreg_decode sf op1 S shift Rm imm6 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (setflags :: bool) = (S = (vec_of_bits [B1] :: 1 Word.word)) in + ((if (((shift = (vec_of_bits [B1,B1] :: 2 Word.word)))) then ReservedValue () + else return () ) \ + (if ((((((sf = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec imm6 (( 5 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then + ReservedValue () + else return () )) \ + ((let (shift_type :: ShiftType) = (DecodeShift shift) in + (let (shift_amount :: ii) = (Word.uint imm6) in + aarch64_integer_arithmetic_addsub_shiftedreg d datasize m n setflags shift_amount shift_type + sub_op)))))))))))" + + +(*val integer_arithmetic_addsub_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_addsub_immediate_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(2)Word.word \(12)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_addsub_immediate_decode b__0 op1 S shift imm12 Rn Rd = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (setflags :: bool) = (S = (vec_of_bits [B1] :: 1 Word.word)) in + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (imm :: 32 bits) . + (let b__1 = shift in + (if (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (ZeroExtend__0 imm12 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: ( 32 Word.word) M) + else if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (ZeroExtend__0 + ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 :: int)::ii) :: 12 itself)) :: 12 Word.word)) + :: 24 Word.word)) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + :: ( 32 Word.word) M) + else ReservedValue () \ return imm) \ (\ (imm :: 32 bits) . + aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) imm n + setflags sub_op)))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (setflags :: bool) = (S = (vec_of_bits [B1] :: 1 Word.word)) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (imm :: 64 bits) . + (let b__4 = shift in + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (ZeroExtend__0 imm12 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (ZeroExtend__0 + ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 :: int)::ii) :: 12 itself)) :: 12 Word.word)) + :: 24 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M) + else ReservedValue () \ return imm) \ (\ (imm :: 64 bits) . + aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) imm n + setflags sub_op)))))))))" + + +(*val integer_arithmetic_addsub_extendedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_arithmetic_addsub_extendedreg_decode :: "(1)Word.word \(1)Word.word \(1)Word.word \(2)Word.word \(5)Word.word \(3)Word.word \(3)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_arithmetic_addsub_extendedreg_decode sf op1 S opt Rm option_name imm3 Rn Rd = ( + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + (let (m :: ii) = (Word.uint Rm) in + (let (datasize :: int) = + (if (((sf = (vec_of_bits [B1] :: 1 Word.word)))) then (( 64 :: int)::ii) + else (( 32 :: int)::ii)) in + (let (sub_op :: bool) = (op1 = (vec_of_bits [B1] :: 1 Word.word)) in + (let (setflags :: bool) = (S = (vec_of_bits [B1] :: 1 Word.word)) in + (let (extend_type :: ExtendType) = (DecodeRegExtend option_name) in + (let (shift :: ii) = (Word.uint imm3) in + (if ((((ex_int shift)) > (( 4 :: int)::ii))) then ReservedValue () + else return () ) \ + aarch64_integer_arithmetic_addsub_extendedreg d datasize extend_type m n setflags shift sub_op))))))))))" + + +(*val DecodeBitMasks : forall 'M . Size 'M => integer -> mword ty1 -> mword ty6 -> mword ty6 -> bool -> M (mword 'M * mword 'M)*) + +definition DecodeBitMasks :: " int \(1)Word.word \(6)Word.word \(6)Word.word \ bool \((register_value),(('M::len)Word.word*('M::len)Word.word),(exception))monad " where + " DecodeBitMasks (M__tv :: int) immN imms immr immediate = ( + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (tmask :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (wmask :: 64 bits) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (tmask_and :: 6 bits) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (wmask_and :: 6 bits) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (tmask_or :: 6 bits) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (wmask_or :: 6 bits) . + (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \ (\ (levels :: 6 bits) . + HighestSetBit ((concat_vec immN ((not_vec imms :: 6 Word.word)) :: 7 Word.word)) \ (\ len . + ((assert_exp ((len \ (( 0 :: int)::ii))) ('''') \ + (if ((len < (( 1 :: int)::ii))) then ReservedValue () + else return () )) \ + assert_exp ((M__tv \ ((ex_int ((shl_int0 (( 1 :: int)::ii) len)))))) (''(M >= (1 << len))'')) \ + ((let levels = ((zext_ones (( 6 :: int)::ii) len :: 6 Word.word)) in + (if (((immediate \ (((((and_vec imms levels :: 6 Word.word)) = levels)))))) then + ReservedValue () + else return () ) \ + ((let (S :: ii) = (Word.uint ((and_vec imms levels :: 6 Word.word))) in + (let (R1 :: ii) = (Word.uint ((and_vec immr levels :: 6 Word.word))) in + (let (diff :: ii) = (((ex_int S)) - ((ex_int R1))) in + (let (tmask_and :: 6 bits) = + ((or_vec ((GetSlice_int ((make_the_value (( 6 :: int)::ii) :: 6 itself)) diff (( 0 :: int)::ii) :: 6 Word.word)) + ((not_vec levels :: 6 Word.word)) + :: 6 Word.word)) in + (let (tmask_or :: 6 bits) = + ((and_vec ((GetSlice_int ((make_the_value (( 6 :: int)::ii) :: 6 itself)) diff (( 0 :: int)::ii) :: 6 Word.word)) + levels + :: 6 Word.word)) in + (let (tmask :: 64 bits) = ((Ones__0 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 0 :: int)::ii)] :: 1 Word.word) + (( 1 :: int)::ii) + :: 1 Word.word)) + ((Ones__0 ((make_the_value (( 1 :: int)::ii) :: 1 itself)) :: 1 Word.word)) + :: 2 Word.word)) (( 32 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 1 :: int)::ii) :: 1 itself)) :: 1 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 0 :: int)::ii)] :: 1 Word.word) (( 1 :: int)::ii) + :: 1 Word.word)) + :: 2 Word.word)) (( 32 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 1 :: int)::ii)] :: 1 Word.word) + (( 2 :: int)::ii) + :: 2 Word.word)) + ((Ones__0 ((make_the_value (( 2 :: int)::ii) :: 2 itself)) :: 2 Word.word)) + :: 4 Word.word)) (( 16 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 2 :: int)::ii) :: 2 itself)) :: 2 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 1 :: int)::ii)] :: 1 Word.word) (( 2 :: int)::ii) + :: 2 Word.word)) + :: 4 Word.word)) (( 16 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 2 :: int)::ii)] :: 1 Word.word) + (( 4 :: int)::ii) + :: 4 Word.word)) + ((Ones__0 ((make_the_value (( 4 :: int)::ii) :: 4 itself)) :: 4 Word.word)) + :: 8 Word.word)) (( 8 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 4 :: int)::ii) :: 4 itself)) :: 4 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 2 :: int)::ii)] :: 1 Word.word) (( 4 :: int)::ii) + :: 4 Word.word)) + :: 8 Word.word)) (( 8 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 3 :: int)::ii)] :: 1 Word.word) + (( 8 :: int)::ii) + :: 8 Word.word)) + ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) + :: 16 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 3 :: int)::ii)] :: 1 Word.word) (( 8 :: int)::ii) + :: 8 Word.word)) + :: 16 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 4 :: int)::ii)] :: 1 Word.word) + (( 16 :: int)::ii) + :: 16 Word.word)) + ((Ones__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + :: 32 Word.word)) (( 2 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 4 :: int)::ii)] :: 1 Word.word) (( 16 :: int)::ii) + :: 16 Word.word)) + :: 32 Word.word)) (( 2 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (tmask :: 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 5 :: int)::ii)] :: 1 Word.word) + (( 32 :: int)::ii) + :: 32 Word.word)) + ((Ones__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 64 Word.word)) (( 1 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 5 :: int)::ii)] :: 1 Word.word) (( 32 :: int)::ii) + :: 32 Word.word)) + :: 64 Word.word)) (( 1 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask_and :: 6 bits) = ((or_vec immr ((not_vec levels :: 6 Word.word)) :: 6 Word.word)) in + (let (wmask_or :: 6 bits) = ((and_vec immr levels :: 6 Word.word)) in + (let (wmask :: 64 bits) = ((Zeros__0 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 1 :: int)::ii) :: 1 itself)) :: 1 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 0 :: int)::ii)] :: 1 Word.word) + (( 1 :: int)::ii) + :: 1 Word.word)) + :: 2 Word.word)) (( 32 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 0 :: int)::ii)] :: 1 Word.word) (( 1 :: int)::ii) + :: 1 Word.word)) ((Zeros__0 ((make_the_value (( 1 :: int)::ii) :: 1 itself)) :: 1 Word.word)) + :: 2 Word.word)) (( 32 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 2 :: int)::ii) :: 2 itself)) :: 2 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 1 :: int)::ii)] :: 1 Word.word) + (( 2 :: int)::ii) + :: 2 Word.word)) + :: 4 Word.word)) (( 16 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 1 :: int)::ii)] :: 1 Word.word) (( 2 :: int)::ii) + :: 2 Word.word)) ((Zeros__0 ((make_the_value (( 2 :: int)::ii) :: 2 itself)) :: 2 Word.word)) + :: 4 Word.word)) (( 16 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 4 :: int)::ii) :: 4 itself)) :: 4 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 2 :: int)::ii)] :: 1 Word.word) + (( 4 :: int)::ii) + :: 4 Word.word)) + :: 8 Word.word)) (( 8 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 2 :: int)::ii)] :: 1 Word.word) (( 4 :: int)::ii) + :: 4 Word.word)) ((Zeros__0 ((make_the_value (( 4 :: int)::ii) :: 4 itself)) :: 4 Word.word)) + :: 8 Word.word)) (( 8 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 3 :: int)::ii)] :: 1 Word.word) + (( 8 :: int)::ii) + :: 8 Word.word)) + :: 16 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 3 :: int)::ii)] :: 1 Word.word) (( 8 :: int)::ii) + :: 8 Word.word)) ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) + :: 16 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 4 :: int)::ii)] :: 1 Word.word) + (( 16 :: int)::ii) + :: 16 Word.word)) + :: 32 Word.word)) (( 2 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 4 :: int)::ii)] :: 1 Word.word) (( 16 :: int)::ii) + :: 16 Word.word)) + ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) + :: 32 Word.word)) (( 2 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 5 :: int)::ii)] :: 1 Word.word) + (( 32 :: int)::ii) + :: 32 Word.word)) + :: 64 Word.word)) (( 1 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 5 :: int)::ii)] :: 1 Word.word) (( 32 :: int)::ii) + :: 32 Word.word)) + ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) + :: 64 Word.word)) (( 1 :: int)::ii) + :: 64 Word.word)) + :: 64 Word.word)) in + (let (wmask :: 64 bits) = + (if (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) diff (( 6 :: int)::ii) :: 1 Word.word)) \ (vec_of_bits [B0] :: 1 Word.word)))) then + (and_vec wmask tmask :: 64 Word.word) + else (or_vec wmask tmask :: 64 Word.word)) in + return ((slice0 wmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word), (slice0 tmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word))))))))))))))))))))))))))))))))))))" + + +(*val integer_logical_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_logical_immediate_decode :: "(1)Word.word \(2)Word.word \(1)Word.word \(6)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_logical_immediate_decode b__0 opc N immr imms Rn Rd = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_bool () \ (\ (setflags :: bool) . + undefined_LogicalOp () \ (\ (op1 :: LogicalOp) . + (let b__1 = opc in + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_ORR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_EOR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = True in + (op1, setflags)))) in + (op1, setflags))) in + (op1, setflags))) in + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (imm :: 32 bits) . + ((if (((True \ (((N \ (vec_of_bits [B0] :: 1 Word.word))))))) then ReservedValue () + else return () ) \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (anon10 :: 32 bits) . + (DecodeBitMasks (( 32 :: int)::ii) N imms immr True :: (( 32 Word.word * 32 Word.word)) M) \ (\ (w__0 :: + ( 32 bits * 32 bits)) . + (let (tup__0, tup__1) = w__0 in + (let imm = tup__0 in + (let anon10 = tup__1 in + aarch64_integer_logical_immediate d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) imm n op1 setflags))))))))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_bool () \ (\ (setflags :: bool) . + undefined_LogicalOp () \ (\ (op1 :: LogicalOp) . + (let b__6 = opc in + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__6 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__6 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_ORR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let ((op1 :: LogicalOp), (setflags :: bool)) = + (if (((b__6 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (op1 :: LogicalOp) = LogicalOp_EOR in + (let (setflags :: bool) = False in + (op1, setflags))) + else + (let (op1 :: LogicalOp) = LogicalOp_AND in + (let (setflags :: bool) = True in + (op1, setflags)))) in + (op1, setflags))) in + (op1, setflags))) in + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (imm :: 64 bits) . + ((if (((False \ (((N \ (vec_of_bits [B0] :: 1 Word.word))))))) then ReservedValue () + else return () ) \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (anon10 :: 64 bits) . + (DecodeBitMasks (( 64 :: int)::ii) N imms immr True :: (( 64 Word.word * 64 Word.word)) M) \ (\ (w__1 :: + ( 64 bits * 64 bits)) . + (let (tup__0, tup__1) = w__1 in + (let imm = tup__0 in + (let anon10 = tup__1 in + aarch64_integer_logical_immediate d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) imm n op1 setflags))))))))))))))" + + +(*val integer_bitfield_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +definition integer_bitfield_decode :: "(1)Word.word \(2)Word.word \(1)Word.word \(6)Word.word \(6)Word.word \(5)Word.word \(5)Word.word \((register_value),(unit),(exception))monad " where + " integer_bitfield_decode b__0 opc N immr imms Rn Rd = ( + if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_bool () \ (\ (inzero :: bool) . + undefined_bool () \ (\ (extend1 :: bool) . + undefined_int () \ (\ (R1 :: ii) . + undefined_int () \ (\ (S :: ii) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (wmask :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \ (\ (tmask :: 32 bits) . + (let b__1 = opc in + (if (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (inzero :: bool) = True in + (let (extend1 :: bool) = True in + return (extend1, inzero))) + else if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (inzero :: bool) = False in + (let (extend1 :: bool) = False in + return (extend1, inzero))) + else if (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (inzero :: bool) = True in + (let (extend1 :: bool) = False in + return (extend1, inzero))) + else UnallocatedEncoding () \ return (extend1, inzero)) \ (\ varstup . (let ((extend1 :: bool), (inzero :: + bool)) = varstup in + ((if (((False \ (((N \ (vec_of_bits [B1] :: 1 Word.word))))))) then ReservedValue () + else return () ) \ + (if (((True \ (((((((((N \ (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec immr (( 5 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word))))))) \ ((((vec_of_bits [access_vec_dec imms (( 5 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)))))))))) then + ReservedValue () + else return () )) \ + ((let R1 = (Word.uint immr) in + (let S = (Word.uint imms) in + (DecodeBitMasks (( 32 :: int)::ii) N imms immr False :: (( 32 Word.word * 32 Word.word)) M) \ (\ (w__0 :: + ( 32 bits * 32 bits)) . + (let (tup__0, tup__1) = w__0 in + (let wmask = tup__0 in + (let tmask = tup__1 in + aarch64_integer_bitfield R1 S d ((make_the_value (( 32 :: int)::ii) :: 32 itself)) extend1 inzero n tmask + wmask))))))))))))))))))) + else + write_reg unconditional_ref True \ + ((let (d :: ii) = (Word.uint Rd) in + (let (n :: ii) = (Word.uint Rn) in + undefined_bool () \ (\ (inzero :: bool) . + undefined_bool () \ (\ (extend1 :: bool) . + undefined_int () \ (\ (R1 :: ii) . + undefined_int () \ (\ (S :: ii) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (wmask :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \ (\ (tmask :: 64 bits) . + (let b__6 = opc in + (if (((b__6 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (let (inzero :: bool) = True in + (let (extend1 :: bool) = True in + return (extend1, inzero))) + else if (((b__6 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (let (inzero :: bool) = False in + (let (extend1 :: bool) = False in + return (extend1, inzero))) + else if (((b__6 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (let (inzero :: bool) = True in + (let (extend1 :: bool) = False in + return (extend1, inzero))) + else UnallocatedEncoding () \ return (extend1, inzero)) \ (\ varstup . (let ((extend1 :: bool), (inzero :: + bool)) = varstup in + ((if (((True \ (((N \ (vec_of_bits [B1] :: 1 Word.word))))))) then ReservedValue () + else return () ) \ + (if (((False \ (((((((((N \ (vec_of_bits [B0] :: 1 Word.word)))) \ ((((vec_of_bits [access_vec_dec immr (( 5 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word))))))) \ ((((vec_of_bits [access_vec_dec imms (( 5 :: int)::ii)] :: 1 Word.word) \ (vec_of_bits [B0] :: 1 Word.word)))))))))) then + ReservedValue () + else return () )) \ + ((let R1 = (Word.uint immr) in + (let S = (Word.uint imms) in + (DecodeBitMasks (( 64 :: int)::ii) N imms immr False :: (( 64 Word.word * 64 Word.word)) M) \ (\ (w__1 :: + ( 64 bits * 64 bits)) . + (let (tup__0, tup__1) = w__1 in + (let wmask = tup__0 in + (let tmask = tup__1 in + aarch64_integer_bitfield R1 S d ((make_the_value (( 64 :: int)::ii) :: 64 itself)) extend1 inzero n tmask + wmask))))))))))))))))))))" + + +(*val decode : mword ty32 -> M unit*) + +definition decode :: "(32)Word.word \((register_value),(unit),(exception))monad " where + " decode op_code = ( + if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0,B1,B1] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 22 :: int)::ii) (( 21 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op54 :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (U :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Ra :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_mul_widening_64128hi_decode sf op54 U Rm o0 Ra Rn Rd)))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B0,B1] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B1,B0] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (option_name :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode size1 V1 opc Rm + option_name S Rn Rt)))))))) + else if (((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1] :: 8 Word.word)))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Ra :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_mul_addsub_decode M S typ1 o1 Rm o0 Ra Rn Rd))))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_atomicops_ld_decode size1 V1 A R1 Rs o3 opc Rn Rt))))))))) + else if (((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0] + :: 21 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (D :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_strip_dp_1src_decode sf S opcode2 D Rn Rd)))))) + else if (((op_code = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0,B0,B0,B0,B0, + B1,B1,B1,B1,B1,B1,B1,B1] + :: 32 Word.word)))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_strip_hint_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacda_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B1] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1,B1] :: 8 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_monitors_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode + size1 V1 opc imm9 Rn Rt)))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B0,B0] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_mul_product_decode M S typ1 Rm op1 Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0,B1,B0,B1,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode2 :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacga_dp_2src_decode sf op1 S Rm opcode2 Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_atomicops_cas_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 19 :: int)::ii) :: 13 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0] :: 13 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_register_cpsr_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1,B0,B0] :: 8 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 :: int)::ii)] :: 1 Word.word)) in + (let (imm19 :: 19 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 5 :: int)::ii) :: 19 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 :: int)::ii)] :: 1 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in + branch_conditional_cond_decode o1 imm19 o0 cond)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_runtime_hvc_decode opc imm16 op2 LL)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (let (sz :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_exclusive_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autdb_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 10 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_rbit_decode sf S opcode2 Rn Rd))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm12 :: 12 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 10 :: int)::ii) :: 12 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode + size1 V1 opc imm12 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autia_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autia_hint_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_runtime_svc_decode opc imm16 op2 LL)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B1] :: 7 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0,B0,B0,B0] :: 9 Word.word)))))))))) then + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 2 bits) = ((subrange_vec_dec op_code (( 22 :: int)::ii) (( 21 :: int)::ii) :: 2 Word.word)) in + (let (op2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op3 :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 :: int)::ii)] :: 1 Word.word)) in + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + branch_unconditional_register_decode Z opc op1 op2 op3 A M Rn Rm))))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 5 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm8 :: 8 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 13 :: int)::ii) :: 8 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_move_fp_imm_decode M S typ1 imm8 imm5 Rd)))))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (b5 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 :: int)::ii)] :: 1 Word.word)) in + (let (b40 :: 5 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 19 :: int)::ii) :: 5 Word.word)) in + (let (imm14 :: 14 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 5 :: int)::ii) :: 14 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + branch_conditional_test_decode b5 op1 b40 imm14 Rt))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt)))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm12 :: 12 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 10 :: int)::ii) :: 12 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm12 Rn Rt)))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (imm19 :: 19 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 5 :: int)::ii) :: 19 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_literal_general_decode opc V1 imm19 Rt)))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B0,B1] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1,B0] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 :: int)::ii)] :: 1 Word.word)) in + (let (imm19 :: 19 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 5 :: int)::ii) :: 19 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + branch_conditional_compare_decode sf op1 imm19 Rt)))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode + size1 V1 opc imm9 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacib_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacib_hint_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt)))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm12 :: 12 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 10 :: int)::ii) :: 12 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm12 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 16 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (Q :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (opcode :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode Q L opcode size1 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0,B1] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (let (Q :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode Q L Rm opcode size1 + Rn Rt))))))) + else if (((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B1,B0,B1,B0,B0,B1,B1,B1,B1,B1,B0,B0,B0,B0] + :: 20 Word.word)))) then + (let (opc :: 4 bits) = ((subrange_vec_dec op_code (( 24 :: int)::ii) (( 21 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op3 :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 :: int)::ii)] :: 1 Word.word)) in + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (op4 :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + branch_unconditional_eret_decode opc op2 op3 A M Rn op4))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 14 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 2 bits) = ((subrange_vec_dec op_code (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_maxmin_decode M S typ1 Rm op1 Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 17 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \ (((((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_unary_decode M S typ1 opc Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_runtime_smc_decode opc imm16 op2 LL)))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0,B1] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_ordered_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (option_name :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_register_aarch64_memory_single_general_register__decode size1 V1 opc Rm + option_name S Rn Rt)))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0] :: 7 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm7 :: 7 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 15 :: int)::ii) :: 7 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode opc V1 L imm7 Rt2 Rn Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B0,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_debug_breakpoint_decode opc imm16 op2 LL)))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 21 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1,B0,B0,B0] :: 10 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op54 :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (op31 :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Ra :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_mul_uniform_addsub_decode sf op54 op31 Rm o0 Ra Rn Rd)))))))) + else if (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (imm19 :: 19 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 5 :: int)::ii) :: 19 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_literal_simdfp_decode opc V1 imm19 Rt)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 22 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0] :: 10 Word.word)))) \ (((((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_sysops_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 24 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (shift :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm6 :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_addsub_shiftedreg_decode sf op1 S shift Rm imm6 Rn Rd)))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 23 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (N :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (immr :: 6 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 16 :: int)::ii) :: 6 Word.word)) in + (let (imms :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_logical_immediate_decode sf opc N immr imms Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 21 :: int)::ii) :: 9 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0,B1,B0] :: 9 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 :: int)::ii)] :: 1 Word.word)) in + (let (nzcv :: 4 bits) = ((subrange_vec_dec op_code (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in + integer_conditional_compare_register_decode sf op1 S Rm cond o2 Rn o3 nzcv))))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 23 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (N :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (immr :: 6 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 16 :: int)::ii) :: 6 Word.word)) in + (let (imms :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_bitfield_decode sf opc N immr imms Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 22 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0] :: 10 Word.word)))) \ (((((subrange_vec_dec op_code (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 19 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_register_system_decode L o0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 21 :: int)::ii) :: 9 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0,B1,B0] :: 9 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 :: int)::ii)] :: 1 Word.word)) in + (let (nzcv :: 4 bits) = ((subrange_vec_dec op_code (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in + integer_conditional_compare_immediate_decode sf op1 S imm5 cond o2 Rn o3 nzcv))))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_div_decode M S typ1 Rm Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_atomicops_swp_decode size1 V1 A R1 Rs o3 opc Rn Rt))))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 24 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (shift :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm12 :: 12 bits) = ((subrange_vec_dec op_code (( 21 :: int)::ii) (( 10 :: int)::ii) :: 12 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_addsub_immediate_decode sf op1 S shift imm12 Rn Rd))))))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 26 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) then + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (imm26 :: 26 bits) = ((subrange_vec_dec op_code (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + branch_unconditional_immediate_decode op1 imm26)) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autda_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 11 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] + :: 20 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_cnt_decode sf S opcode2 op1 Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 27 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 25 :: int)::ii) (( 24 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))))))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_atomicops_st_decode size1 V1 A R1 Rs o3 opc Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B1] + :: 20 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_barriers_decode L op0 op1 CRn CRm opc Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (let (sz :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_atomicops_cas_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt))))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 23 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (hw :: 2 bits) = ((subrange_vec_dec op_code (( 22 :: int)::ii) (( 21 :: int)::ii) :: 2 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_insext_insert_movewide_decode sf opc hw imm16 Rd))))) + else if (((op_code = (vec_of_bits [B1,B1,B0,B1,B0,B1,B1,B0,B1,B0,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1, + B1,B1,B1,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + (let (opc :: 4 bits) = ((subrange_vec_dec op_code (( 24 :: int)::ii) (( 21 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op3 :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (op4 :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + branch_unconditional_dret_decode opc op2 op3 Rt op4))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_move_fp_select_decode M S typ1 Rm cond Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B1,B0,B1] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_debug_exception_decode opc imm16 op2 LL)))) + else if (((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 12 :: int)::ii) :: 19 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 19 Word.word)))) + then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_rev_decode sf S opcode2 opc Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 17 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))) \ (((((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_convert_fp_decode M S typ1 opc Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacia_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacia_hint_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 24 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0] :: 7 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (rmode :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (opcode :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_convert_int_decode sf S typ1 rmode opcode Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 21 :: int)::ii) :: 9 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0,B1,B0,B0] :: 9 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_conditional_select_decode sf op1 S Rm cond o2 Rn Rd)))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 21 :: int)::ii) :: 9 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0,B1,B0,B1] :: 9 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (A :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o3 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_orderedrcpc_decode size1 V1 A R1 Rs o3 opc Rn Rt))))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 21 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0,B0,B1] :: 8 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opt :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (option_name :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (imm3 :: 3 bits) = ((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_addsub_extendedreg_decode sf op1 S opt Rm option_name imm3 Rn Rd))))))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 24 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) then + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (immlo :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (immhi :: 19 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 5 :: int)::ii) :: 19 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_address_pcrel_decode op1 immlo immhi Rd)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))))))) then + (let (Q :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (opcode :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode Q L R1 opcode S size1 Rn Rt)))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))) then + (let (Q :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (R1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode Q L R1 Rm opcode S size1 + Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (W :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_signed_pac_decode size1 V1 M S imm9 W Rn Rt)))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autib_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_autib_hint_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cond :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 :: int)::ii)] :: 1 Word.word)) in + (let (nzcv :: 4 bits) = ((subrange_vec_dec op_code (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in + float_compare_cond_decode M S typ1 Rm cond Rn op1 nzcv)))))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 23 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (o2 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rs :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Rt2 :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_exclusive_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt))))))))) + else if ((((((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 24 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0] :: 7 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (rmode :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (opcode :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (scale :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_convert_fix_decode sf S typ1 rmode opcode scale Rn Rd)))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 18 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \ (((((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (rmode :: 3 bits) = ((subrange_vec_dec op_code (( 17 :: int)::ii) (( 15 :: int)::ii) :: 3 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_round_decode M S typ1 rmode Rn Rd)))))) + else if (((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 24 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (shift :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (N :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm6 :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_logical_shiftedreg_decode sf opc shift N Rm imm6 Rn Rd)))))))) + else if ((((((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 21 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B1,B1,B0] :: 10 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode2 :: 3 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) in + (let (C :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (sz :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_crc_decode sf op1 S Rm opcode2 C sz Rn Rd))))))))) + else if ((((((((subrange_vec_dec op_code (( 28 :: int)::ii) (( 21 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0,B0,B0] :: 8 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode2 :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_addsub_carry_decode sf op1 S Rm opcode2 Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))) \ (((((subrange_vec_dec op_code (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 2 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 14 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + float_compare_uncond_decode M S typ1 Rm op1 Rn opc))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1,B0] + :: 20 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))))))) then + (let (L :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (op0 :: 2 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 19 :: int)::ii) :: 2 Word.word)) in + (let (op1 :: 3 bits) = ((subrange_vec_dec op_code (( 18 :: int)::ii) (( 16 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 7 :: int)::ii) (( 5 :: int)::ii) :: 3 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + system_hints_decode L op0 op1 CRn CRm op2 Rt))))))) + else if ((((((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 21 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B1,B1,B0] :: 10 Word.word)))) \ (((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode2 :: 4 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 2 bits) = ((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_shift_variable_decode sf op1 S Rm opcode2 op2 Rn Rd)))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 14 :: int)::ii) :: 18 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0,B1,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] + :: 18 Word.word)))) \ (((((subrange_vec_dec op_code (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (Z :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_pac_pacdb_dp_1src_decode sf S opcode2 Z Rn Rd)))))) + else if ((((((((subrange_vec_dec op_code (( 29 :: int)::ii) (( 24 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then + (let (size1 :: 2 bits) = ((subrange_vec_dec op_code (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word)) in + (let (V1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 :: int)::ii)] :: 1 Word.word)) in + (let (opc :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (imm9 :: 9 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 12 :: int)::ii) :: 9 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rt :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode + size1 V1 opc imm9 Rn Rt)))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B0] :: 8 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) \ ((((((((subrange_vec_dec op_code (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \ (((((subrange_vec_dec op_code (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))))))))) then + (let (M :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (typ1 :: 2 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 22 :: int)::ii) :: 2 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + float_arithmetic_addsub_decode M S typ1 Rm op1 Rn Rd))))))) + else if ((((((((subrange_vec_dec op_code (( 30 :: int)::ii) (( 23 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1,B1] :: 8 Word.word)))) \ (((((subrange_vec_dec op_code (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op21 :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (N :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 :: int)::ii)] :: 1 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imms :: 6 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_insext_extract_immediate_decode sf op21 N o0 Rm imms Rn Rd)))))))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B0,B0,B1,B0] :: 11 Word.word)))) \ (((((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (opc :: 3 bits) = ((subrange_vec_dec op_code (( 23 :: int)::ii) (( 21 :: int)::ii) :: 3 Word.word)) in + (let (imm16 :: 16 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 5 :: int)::ii) :: 16 Word.word)) in + (let (op2 :: 3 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (LL :: 2 bits) = ((subrange_vec_dec op_code (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + system_exceptions_debug_halt_decode opc imm16 op2 LL)))) + else if ((((((((subrange_vec_dec op_code (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0,B1,B1] :: 8 Word.word)))) \ (((((subrange_vec_dec op_code (( 22 :: int)::ii) (( 21 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op54 :: 2 bits) = ((subrange_vec_dec op_code (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) in + (let (U :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (o0 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 :: int)::ii)] :: 1 Word.word)) in + (let (Ra :: 5 bits) = ((subrange_vec_dec op_code (( 14 :: int)::ii) (( 10 :: int)::ii) :: 5 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_mul_widening_3264_decode sf op54 U Rm o0 Ra Rn Rd)))))))) + else + (let (sf :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (op1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (S :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 :: int)::ii)] :: 1 Word.word)) in + (let (Rm :: 5 bits) = ((subrange_vec_dec op_code (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (opcode2 :: 5 bits) = ((subrange_vec_dec op_code (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (o1 :: 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 :: int)::ii)] :: 1 Word.word)) in + (let (Rn :: 5 bits) = ((subrange_vec_dec op_code (( 9 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (Rd :: 5 bits) = ((subrange_vec_dec op_code (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + integer_arithmetic_div_decode sf op1 S Rm opcode2 o1 Rn Rd)))))))))" + + +(*val fetch_and_execute : unit -> M unit*) + +definition fetch_and_execute :: " unit \((register_value),(unit),(exception))monad " where + " fetch_and_execute _ = ( + (whileM () + (\ unit_var . return True) + (\ unit_var . + (try_catch ((read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__0 :: 64 Word.word) . + (aget_Mem w__0 (( 4 :: int)::ii) AccType_IFETCH :: ( 32 Word.word) M) \ (\ instr . + decode instr))) (\x . + (case x of + Error_Undefined _ => exit0 () + | Error_See s => + if(s = (''HINT'')) then (return () ) else (exit0 () ) + | Error_Implementation_Defined _ => exit0 () + | Error_ReservedEncoding _ => exit0 () + | Error_ExceptionTaken _ => exit0 () + )) \ + read_reg BranchTaken_ref) \ (\ (w__1 :: bool) . + if w__1 then write_reg BranchTaken_ref False + else + (read_reg PC_ref :: ( 64 Word.word) M) \ (\ (w__2 :: 64 Word.word) . + write_reg PC_ref ((add_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)))))))" + + +(*val main : unit -> M unit*) + +definition main :: " unit \((register_value),(unit),(exception))monad " where + " main _ = ( + (write_reg + PC_ref + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) (( 0 :: int)::ii) + :: 64 Word.word)) \ + (ZeroExtend__0 (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M)) \ (\ (w__0 :: 64 bits) . + (write_reg SP_EL0_ref w__0 \ + read_reg PSTATE_ref) \ (\ (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_D := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_A := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_I := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + read_reg PSTATE_ref) \ (\ (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_F := ((vec_of_bits [B1] :: 1 Word.word))|)) \ + (ZeroExtend__0 (vec_of_bits [B1,B0] :: 2 Word.word) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + :: ( 32 Word.word) M)) \ (\ (w__5 :: 32 bits) . + (write_reg OSLSR_EL1_ref w__5 \ write_reg BranchTaken_ref False) \ fetch_and_execute () )))))))" + + +(*val initialize_registers : unit -> M unit*) + +definition initialize_registers :: " unit \((register_value),(unit),(exception))monad " where + " initialize_registers _ = ( + undefined_bool () \ (\ (w__0 :: bool) . + (write_reg unconditional_ref w__0 \ + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \ (\ (w__1 :: 4 bits) . + (write_reg currentCond_ref w__1 \ + undefined___InstrEnc () ) \ (\ (w__2 :: InstrEnc) . + (write_reg ThisInstrEnc_ref w__2 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__3 :: 32 bits) . + (write_reg ThisInstr_ref w__3 \ + undefined_bool () ) \ (\ (w__4 :: bool) . + (write_reg Sleeping_ref w__4 \ + undefined_bool () ) \ (\ (w__5 :: bool) . + (write_reg PendingPhysicalSError_ref w__5 \ + undefined_bool () ) \ (\ (w__6 :: bool) . + (write_reg PendingInterrupt_ref w__6 \ + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \ (\ (w__7 :: 52 bits) . + (write_reg Memory_ref w__7 \ + undefined_bool () ) \ (\ (w__8 :: bool) . + (write_reg ExclusiveLocal_ref w__8 \ + undefined_bool () ) \ (\ (w__9 :: bool) . + (write_reg BranchTaken_ref w__9 \ + (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \ (\ (w__10 :: 128 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__10 :: ( ( 128 Word.word)list) M) \ (\ (w__11 :: ( 128 bits) list) . + (write_reg V_ref w__11 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__12 :: 64 Word.word) . + (undefined_vector (( 31 :: int)::ii) w__12 :: ( ( 64 Word.word)list) M) \ (\ (w__13 :: ( 64 bits) list) . + (write_reg R_ref w__13 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__14 :: 64 bits) . + (write_reg PC_ref w__14 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__15 :: 64 bits) . + (write_reg VTTBR_EL2_ref w__15 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__16 :: 32 bits) . + (write_reg VTCR_EL2_ref w__16 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__17 :: 32 bits) . + (write_reg VSESR_EL2_ref w__17 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__18 :: 32 bits) . + (write_reg VDFSR_ref w__18 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__19 :: 64 bits) . + (write_reg VBAR_EL3_ref w__19 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__20 :: 64 bits) . + (write_reg VBAR_EL2_ref w__20 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__21 :: 64 bits) . + (write_reg VBAR_EL1_ref w__21 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__22 :: 32 bits) . + (write_reg VBAR_ref w__22 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__23 :: 64 bits) . + (write_reg TTBR1_EL2_ref w__23 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__24 :: 64 bits) . + (write_reg TTBR1_EL1_ref w__24 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__25 :: 64 bits) . + (write_reg TTBR0_EL3_ref w__25 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__26 :: 64 bits) . + (write_reg TTBR0_EL2_ref w__26 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__27 :: 64 bits) . + (write_reg TTBR0_EL1_ref w__27 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__28 :: 32 bits) . + (write_reg TTBCR_ref w__28 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__29 :: 32 bits) . + (write_reg TCR_EL3_ref w__29 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__30 :: 64 bits) . + (write_reg TCR_EL2_ref w__30 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__31 :: 64 bits) . + (write_reg TCR_EL1_ref w__31 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__32 :: 32 bits) . + (write_reg SP_mon_ref w__32 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__33 :: 64 bits) . + (write_reg SP_EL3_ref w__33 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__34 :: 64 bits) . + (write_reg SP_EL2_ref w__34 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__35 :: 64 bits) . + (write_reg SP_EL1_ref w__35 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__36 :: 64 bits) . + (write_reg SP_EL0_ref w__36 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__37 :: 32 bits) . + (write_reg SPSR_und_ref w__37 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__38 :: 32 bits) . + (write_reg SPSR_svc_ref w__38 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__39 :: 32 bits) . + (write_reg SPSR_mon_ref w__39 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__40 :: 32 bits) . + (write_reg SPSR_irq_ref w__40 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__41 :: 32 bits) . + (write_reg SPSR_hyp_ref w__41 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__42 :: 32 bits) . + (write_reg SPSR_fiq_ref w__42 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__43 :: 32 bits) . + (write_reg SPSR_abt_ref w__43 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__44 :: 32 bits) . + (write_reg SPSR_EL3_ref w__44 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__45 :: 32 bits) . + (write_reg SPSR_EL2_ref w__45 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__46 :: 32 bits) . + (write_reg SPSR_EL1_ref w__46 \ + undefined_signal () ) \ (\ (w__47 :: signal) . + (write_reg SPIDEN_ref w__47 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__48 :: 32 bits) . + (write_reg SDER_ref w__48 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__49 :: 32 bits) . + (write_reg SDCR_ref w__49 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__50 :: 32 bits) . + (write_reg SCTLR_EL3_ref w__50 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__51 :: 32 bits) . + (write_reg SCTLR_EL2_ref w__51 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__52 :: 32 bits) . + (write_reg SCTLR_EL1_ref w__52 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__53 :: 32 bits) . + (write_reg SCTLR_ref w__53 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__54 :: 32 bits) . + (write_reg SCR_EL3_ref w__54 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__55 :: 32 bits) . + (write_reg SCR_ref w__55 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__56 :: 64 bits) . + (write_reg RVBAR_EL3_ref w__56 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__57 :: 64 bits) . + (write_reg RVBAR_EL2_ref w__57 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__58 :: 64 bits) . + (write_reg RVBAR_EL1_ref w__58 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__59 :: 64 Word.word) . + (undefined_vector (( 5 :: int)::ii) w__59 :: ( ( 64 Word.word)list) M) \ (\ (w__60 :: ( 64 bits) list) . + (write_reg RC_ref w__60 \ + undefined_ProcState () ) \ (\ (w__61 :: ProcState) . + (write_reg PSTATE_ref w__61 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__62 :: 32 bits) . + (write_reg OSLSR_EL1_ref w__62 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__63 :: 32 bits) . + (write_reg OSDLR_EL1_ref w__63 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__64 :: 32 bits) . + (write_reg MDSCR_EL1_ref w__64 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__65 :: 32 bits) . + (write_reg MDCR_EL3_ref w__65 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__66 :: 32 bits) . + (write_reg MDCR_EL2_ref w__66 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__67 :: 64 bits) . + (write_reg MAIR_EL3_ref w__67 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__68 :: 64 bits) . + (write_reg MAIR_EL2_ref w__68 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__69 :: 64 bits) . + (write_reg MAIR_EL1_ref w__69 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__70 :: 32 bits) . + (write_reg LR_mon_ref w__70 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__71 :: 64 bits) . + (write_reg ID_AA64DFR0_EL1_ref w__71 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__72 :: 32 bits) . + (write_reg HVBAR_ref w__72 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__73 :: 32 bits) . + (write_reg HSR_ref w__73 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__74 :: 32 bits) . + (write_reg HSCTLR_ref w__74 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__75 :: 64 bits) . + (write_reg HPFAR_EL2_ref w__75 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__76 :: 32 bits) . + (write_reg HPFAR_ref w__76 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__77 :: 32 bits) . + (write_reg HIFAR_ref w__77 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__78 :: 32 bits) . + (write_reg HDFAR_ref w__78 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__79 :: 32 bits) . + (write_reg HDCR_ref w__79 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__80 :: 64 bits) . + (write_reg HCR_EL2_ref w__80 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__81 :: 32 bits) . + (write_reg HCR2_ref w__81 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__82 :: 32 bits) . + (write_reg HCR_ref w__82 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__83 :: 32 bits) . + (write_reg FPSR_ref w__83 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__84 :: 32 bits) . + (write_reg FPSCR_ref w__84 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__85 :: 32 bits) . + (write_reg FPEXC_ref w__85 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__86 :: 32 bits) . + (write_reg FPCR_ref w__86 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__87 :: 64 bits) . + (write_reg FAR_EL3_ref w__87 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__88 :: 64 bits) . + (write_reg FAR_EL2_ref w__88 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__89 :: 64 bits) . + (write_reg FAR_EL1_ref w__89 \ + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \ (\ (w__90 :: 1 bits) . + (write_reg EventRegister_ref w__90 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__91 :: 32 bits) . + (write_reg ESR_EL3_ref w__91 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__92 :: 32 bits) . + (write_reg ESR_EL2_ref w__92 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__93 :: 32 bits) . + (write_reg ESR_EL1_ref w__93 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__94 :: 32 bits) . + (write_reg ELR_hyp_ref w__94 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__95 :: 64 bits) . + (write_reg ELR_EL3_ref w__95 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__96 :: 64 bits) . + (write_reg ELR_EL2_ref w__96 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__97 :: 64 bits) . + (write_reg ELR_EL1_ref w__97 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__98 :: 32 bits) . + (write_reg EDSCR_ref w__98 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__99 :: 32 bits) . + (write_reg DSPSR_EL0_ref w__99 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__100 :: 32 bits) . + (write_reg DSPSR_ref w__100 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__101 :: 64 bits) . + (write_reg DLR_EL0_ref w__101 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__102 :: 32 bits) . + (write_reg DLR_ref w__102 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__103 :: 64 Word.word) . + (undefined_vector (( 16 :: int)::ii) w__103 :: ( ( 64 Word.word)list) M) \ (\ (w__104 :: ( 64 bits) list) . + (write_reg DBGWVR_EL1_ref w__104 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__105 :: 32 Word.word) . + (undefined_vector (( 16 :: int)::ii) w__105 :: ( ( 32 Word.word)list) M) \ (\ (w__106 :: ( 32 bits) list) . + (write_reg DBGWCR_EL1_ref w__106 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__107 :: 32 bits) . + (write_reg DBGPRCR_EL1_ref w__107 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__108 :: 32 bits) . + (write_reg DBGPRCR_ref w__108 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__109 :: 32 bits) . + (write_reg DBGOSLSR_ref w__109 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__110 :: 32 bits) . + (write_reg DBGOSDLR_ref w__110 \ + undefined_signal () ) \ (\ (w__111 :: signal) . + (write_reg DBGEN_ref w__111 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__112 :: 64 Word.word) . + (undefined_vector (( 16 :: int)::ii) w__112 :: ( ( 64 Word.word)list) M) \ (\ (w__113 :: ( 64 bits) list) . + (write_reg DBGBVR_EL1_ref w__113 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__114 :: 32 Word.word) . + (undefined_vector (( 16 :: int)::ii) w__114 :: ( ( 32 Word.word)list) M) \ (\ (w__115 :: ( 32 bits) list) . + (write_reg DBGBCR_EL1_ref w__115 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__116 :: 32 bits) . + (write_reg CPTR_EL3_ref w__116 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__117 :: 32 bits) . + (write_reg CPTR_EL2_ref w__117 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__118 :: 32 bits) . + (write_reg CPACR_EL1_ref w__118 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__119 :: 32 bits) . + (write_reg CONTEXTIDR_EL2_ref w__119 \ + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \ (\ (w__120 :: 32 bits) . + (write_reg CONTEXTIDR_EL1_ref w__120 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__121 :: 64 bits) . + (write_reg APIBKeyLo_EL1_ref w__121 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__122 :: 64 bits) . + (write_reg APIBKeyHi_EL1_ref w__122 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__123 :: 64 bits) . + (write_reg APIAKeyLo_EL1_ref w__123 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__124 :: 64 bits) . + (write_reg APIAKeyHi_EL1_ref w__124 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__125 :: 64 bits) . + (write_reg APGAKeyLo_EL1_ref w__125 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__126 :: 64 bits) . + (write_reg APGAKeyHi_EL1_ref w__126 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__127 :: 64 bits) . + (write_reg APDBKeyLo_EL1_ref w__127 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__128 :: 64 bits) . + (write_reg APDBKeyHi_EL1_ref w__128 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__129 :: 64 bits) . + (write_reg APDAKeyLo_EL1_ref w__129 \ + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \ (\ (w__130 :: 64 bits) . + write_reg APDAKeyHi_EL1_ref w__130))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| APDAKeyHi_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APDAKeyLo_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APDBKeyHi_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APDBKeyLo_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APGAKeyHi_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APGAKeyLo_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APIAKeyHi_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APIAKeyLo_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APIBKeyHi_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + APIBKeyLo_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CONTEXTIDR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CONTEXTIDR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CPACR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CPTR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CPTR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DBGBCR_EL1 = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)]), + DBGBVR_EL1 = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + DBGEN = LOW, + DBGOSDLR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DBGOSLSR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DBGPRCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DBGPRCR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DBGWCR_EL1 = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)]), + DBGWVR_EL1 = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + DLR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DLR_EL0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + DSPSR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + DSPSR_EL0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + EDSCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ELR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + ELR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + ELR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + ELR_hyp = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ESR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ESR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ESR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + EventRegister = ((vec_of_bits [B0] :: 1 Word.word)), + FAR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + FAR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + FAR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + FPCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + FPEXC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + FPSCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + FPSR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HCR2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HCR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + HDCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HDFAR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HIFAR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HPFAR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HPFAR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + HSCTLR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HSR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + HVBAR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ID_AA64DFR0_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + LR_mon = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + MAIR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + MAIR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + MAIR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + MDCR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + MDCR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + MDSCR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + OSDLR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + OSLSR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + PSTATE = + ((| ProcState_N = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_Z = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_C = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_V = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_D = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_A = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_I = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_F = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_PAN = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_UAO = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_SS = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_IL = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_EL = ((vec_of_bits [B0,B0] :: 2 Word.word)), + ProcState_nRW = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_SP = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_Q = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_GE = ((vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)), + ProcState_IT = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + ProcState_J = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_T = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_E = ((vec_of_bits [B0] :: 1 Word.word)), + ProcState_M = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) |)), + RC = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + RVBAR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + RVBAR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + RVBAR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + SCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SCR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SCTLR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SCTLR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SCTLR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SCTLR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SDCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SDER = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPIDEN = LOW, + SPSR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_abt = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_fiq = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_hyp = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_irq = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_mon = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_svc = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SPSR_und = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + SP_EL0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + SP_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + SP_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + SP_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + SP_mon = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TCR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TCR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TCR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TTBCR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TTBR0_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TTBR0_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TTBR0_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TTBR1_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + TTBR1_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + VBAR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + VBAR_EL1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + VBAR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + VBAR_EL3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + VDFSR = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + VSESR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + VTCR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + VTTBR_EL2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + R = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + V = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 128 Word.word)]), + BranchTaken = False, + ExclusiveLocal = False, + Memory = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 52 Word.word)), + PendingInterrupt = False, + PendingPhysicalSError = False, + Sleeping = False, + ThisInstr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + ThisInstrEnc = A64, + currentCond = ((vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)), + unconditional = False |) )" + + + +end diff --git a/snapshots/isabelle/aarch64/Aarch64_extras.thy b/snapshots/isabelle/aarch64/Aarch64_extras.thy new file mode 100644 index 00000000..be3afd72 --- /dev/null +++ b/snapshots/isabelle/aarch64/Aarch64_extras.thy @@ -0,0 +1,194 @@ +chapter \Generated by Lem from ../aarch64_extras.lem.\ + +theory "Aarch64_extras" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(*type ty512*) +(*type ty1024*) +(*type ty2048*) + +(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition slice0 :: "('a::len)Word.word \ int \ int \('b::len)Word.word " where + " slice0 v lo len = ( + subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )" + + +(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*) +definition set_slice0 :: " int \ int \('a::len)Word.word \ int \('b::len)Word.word \('a::len)Word.word " where + " set_slice0 (out_len::ii) (slice_len::ii) out (n::ii) v = ( + update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )" + + +definition get_slice_int_bl :: " int \ int \ int \(bool)list " where + " get_slice_int_bl len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + subrange_list False bs hi lo)))" + + +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) +definition get_slice_int0 :: " int \ int \ int \('a::len)Word.word " where + " get_slice_int0 len n lo = ( Word.of_bl (get_slice_int_bl len n lo))" + + +(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) +definition set_slice_int0 :: " int \ int \ int \('a::len)Word.word \ int " where + " set_slice_int0 len n lo v = ( + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + (*let len_n = max (hi + 1) (integerFromNat (List.length bs)) in + let ext_bs = exts_bools len_n bs in*) + signed_of_bools (update_subrange_list False bs hi lo (Word.to_bl v)))))" + + +(*let ext_slice signed v i j = + let len = length v in + let bits = get_bits false (bits_of v) i j in + of_bits (if signed then exts_bits len bits else extz_bits len bits) +val exts_slice : list bitU -> integer -> integer -> list bitU +let exts_slice v i j = ext_slice true v i j +val extz_slice : list bitU -> integer -> integer -> list bitU +let extz_slice v i j = ext_slice false v i j*) + +(*val shr_int : ii -> ii -> ii*) +function (sequential,domintros) shr_int0 :: " int \ int \ int " where + " shr_int0 x s = ( if s >( 0 :: int) then shr_int0 (x div( 2 :: int)) (s -( 1 :: int)) else x )" +by pat_completeness auto + + +(*val shl_int : integer -> integer -> integer*) +function (sequential,domintros) shl_int0 :: " int \ int \ int " where + " shl_int0 i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int0 i (shift -( 1 :: int)) else i )" +by pat_completeness auto + + +definition hexchar_to_bool_list :: " char \((bool)list)option " where + " hexchar_to_bool_list c = ( + if c = (CHR ''0'') then Some ([False,False,False,False]) + else if c = (CHR ''1'') then Some ([False,False,False,True ]) + else if c = (CHR ''2'') then Some ([False,False,True, False]) + else if c = (CHR ''3'') then Some ([False,False,True, True ]) + else if c = (CHR ''4'') then Some ([False,True, False,False]) + else if c = (CHR ''5'') then Some ([False,True, False,True ]) + else if c = (CHR ''6'') then Some ([False,True, True, False]) + else if c = (CHR ''7'') then Some ([False,True, True, True ]) + else if c = (CHR ''8'') then Some ([True, False,False,False]) + else if c = (CHR ''9'') then Some ([True, False,False,True ]) + else if c = (CHR ''A'') then Some ([True, False,True, False]) + else if c = (CHR ''a'') then Some ([True, False,True, False]) + else if c = (CHR ''B'') then Some ([True, False,True, True ]) + else if c = (CHR ''b'') then Some ([True, False,True, True ]) + else if c = (CHR ''C'') then Some ([True, True, False,False]) + else if c = (CHR ''c'') then Some ([True, True, False,False]) + else if c = (CHR ''D'') then Some ([True, True, False,True ]) + else if c = (CHR ''d'') then Some ([True, True, False,True ]) + else if c = (CHR ''E'') then Some ([True, True, True, False]) + else if c = (CHR ''e'') then Some ([True, True, True, False]) + else if c = (CHR ''F'') then Some ([True, True, True, True ]) + else if c = (CHR ''f'') then Some ([True, True, True, True ]) + else None )" + + +definition hexstring_to_bools :: " string \((bool)list)option " where + " hexstring_to_bools s = ( + (case ( s) of + z # x # hs => + (let str = (if ((z = (CHR ''0'')) \ (x = (CHR ''x''))) then hs else z # (x # hs)) in + map_option List.concat (just_list (List.map hexchar_to_bool_list str))) + | _ => None + ))" + + +(*val hex_slice : forall 'rv 'n 'e. Size 'n => string -> integer -> integer -> monad 'rv (mword 'n) 'e*) +definition hex_slice :: " string \ int \ int \('rv,(('n::len)Word.word),'e)monad " where + " hex_slice v len lo = ( + (case hexstring_to_bools v of + Some bs => + (let hi = ((len + lo) -( 1 :: int)) in + (let bs = (ext_list False (len + lo) bs) in + return (Word.of_bl (subrange_list False bs hi lo)))) + | None => Fail (''hex_slice'') + ))" + + +definition internal_pick :: " 'a list \('c,'a,'b)monad " where + " internal_pick vs = ( return (List.hd vs))" + + +(* Use constants for undefined values for now *) +definition undefined_string :: " unit \('b,(string),'a)monad " where + " undefined_string _ = ( return (''''))" + +definition undefined_unit :: " unit \('b,(unit),'a)monad " where + " undefined_unit _ = ( return () )" + +definition undefined_int :: " unit \('b,(int),'a)monad " where + " undefined_int _ = ( return (( 0 :: int)::ii))" + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +definition undefined_vector :: " int \ 'a \('rv,('a list),'e)monad " where + " undefined_vector len u = ( return (repeat [u] len))" + +(*val undefined_bitvector : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*) +definition undefined_bitvector :: " int \('rv,(('a::len)Word.word),'e)monad " where + " undefined_bitvector len = ( return (Word.of_bl (repeat [False] len)))" + +(*val undefined_bits : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*) +definition undefined_bits :: " int \('rv,(('a::len)Word.word),'e)monad " where + " undefined_bits = ( undefined_bitvector )" + +definition undefined_bit :: " unit \('b,(bitU),'a)monad " where + " undefined_bit _ = ( return B0 )" + +definition undefined_real :: " unit \('b,(real),'a)monad " where + " undefined_real _ = ( return (realFromFrac(( 0 :: int))(( 1 :: int))))" + +definition undefined_range :: " 'a \ 'd \('c,'a,'b)monad " where + " undefined_range i j = ( return i )" + +definition undefined_atom :: " 'a \('c,'a,'b)monad " where + " undefined_atom i = ( return i )" + +definition undefined_nat :: " unit \('b,(int),'a)monad " where + " undefined_nat _ = ( return (( 0 :: int)::ii))" + + +(*val write_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c => + integer -> integer -> mword 'a -> mword 'b -> mword 'c -> monad 'rv unit 'e*) +definition write_ram :: " int \ int \('a::len)Word.word \('b::len)Word.word \('c::len)Word.word \('rv,(unit),'e)monad " where + " write_ram addrsize size1 hexRAM address value1 = ( + (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \ + write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \ (\x . (case x of _ => return () )) )" + + +(*val read_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c => + integer -> integer -> mword 'a -> mword 'b -> monad 'rv (mword 'c) 'e*) +definition read_ram :: " int \ int \('a::len)Word.word \('b::len)Word.word \('rv,(('c::len)Word.word),'e)monad " where + " read_ram addrsize size1 hexRAM address = ( + (*let _ = prerr_endline (Reading ^ (stringFromInteger size) ^ bytes from address ^ (stringFromInteger (unsigned address))) in*) + read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )" + + +(*val elf_entry : unit -> integer*) +definition elf_entry :: " unit \ int " where + " elf_entry _ = (( 0 :: int))" + +end diff --git a/snapshots/isabelle/aarch64/Aarch64_lemmas.thy b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy new file mode 100644 index 00000000..5a06d97e --- /dev/null +++ b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy @@ -0,0 +1,1075 @@ +theory Aarch64_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Aarch64 +begin + +abbreviation "liftS \ liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def APDAKeyHi_EL1_ref_def APDAKeyLo_EL1_ref_def + APDBKeyHi_EL1_ref_def APDBKeyLo_EL1_ref_def APGAKeyHi_EL1_ref_def APGAKeyLo_EL1_ref_def + APIAKeyHi_EL1_ref_def APIAKeyLo_EL1_ref_def APIBKeyHi_EL1_ref_def APIBKeyLo_EL1_ref_def + CONTEXTIDR_EL1_ref_def CONTEXTIDR_EL2_ref_def CPACR_EL1_ref_def CPTR_EL2_ref_def CPTR_EL3_ref_def + DBGBCR_EL1_ref_def DBGBVR_EL1_ref_def DBGEN_ref_def DBGOSDLR_ref_def DBGOSLSR_ref_def + DBGPRCR_ref_def DBGPRCR_EL1_ref_def DBGWCR_EL1_ref_def DBGWVR_EL1_ref_def DLR_ref_def + DLR_EL0_ref_def DSPSR_ref_def DSPSR_EL0_ref_def EDSCR_ref_def ELR_EL1_ref_def ELR_EL2_ref_def + ELR_EL3_ref_def ELR_hyp_ref_def ESR_EL1_ref_def ESR_EL2_ref_def ESR_EL3_ref_def + EventRegister_ref_def FAR_EL1_ref_def FAR_EL2_ref_def FAR_EL3_ref_def FPCR_ref_def FPEXC_ref_def + FPSCR_ref_def FPSR_ref_def HCR_ref_def HCR2_ref_def HCR_EL2_ref_def HDCR_ref_def HDFAR_ref_def + HIFAR_ref_def HPFAR_ref_def HPFAR_EL2_ref_def HSCTLR_ref_def HSR_ref_def HVBAR_ref_def + ID_AA64DFR0_EL1_ref_def LR_mon_ref_def MAIR_EL1_ref_def MAIR_EL2_ref_def MAIR_EL3_ref_def + MDCR_EL2_ref_def MDCR_EL3_ref_def MDSCR_EL1_ref_def OSDLR_EL1_ref_def OSLSR_EL1_ref_def + PSTATE_ref_def RC_ref_def RVBAR_EL1_ref_def RVBAR_EL2_ref_def RVBAR_EL3_ref_def SCR_ref_def + SCR_EL3_ref_def SCTLR_ref_def SCTLR_EL1_ref_def SCTLR_EL2_ref_def SCTLR_EL3_ref_def SDCR_ref_def + SDER_ref_def SPIDEN_ref_def SPSR_EL1_ref_def SPSR_EL2_ref_def SPSR_EL3_ref_def SPSR_abt_ref_def + SPSR_fiq_ref_def SPSR_hyp_ref_def SPSR_irq_ref_def SPSR_mon_ref_def SPSR_svc_ref_def + SPSR_und_ref_def SP_EL0_ref_def SP_EL1_ref_def SP_EL2_ref_def SP_EL3_ref_def SP_mon_ref_def + TCR_EL1_ref_def TCR_EL2_ref_def TCR_EL3_ref_def TTBCR_ref_def TTBR0_EL1_ref_def TTBR0_EL2_ref_def + TTBR0_EL3_ref_def TTBR1_EL1_ref_def TTBR1_EL2_ref_def VBAR_ref_def VBAR_EL1_ref_def + VBAR_EL2_ref_def VBAR_EL3_ref_def VDFSR_ref_def VSESR_EL2_ref_def VTCR_EL2_ref_def + VTTBR_EL2_ref_def PC_ref_def R_ref_def V_ref_def BranchTaken_ref_def ExclusiveLocal_ref_def + Memory_ref_def PendingInterrupt_ref_def PendingPhysicalSError_ref_def Sleeping_ref_def + ThisInstr_ref_def ThisInstrEnc_ref_def currentCond_ref_def unconditional_ref_def + +lemma regval_ProcState[simp]: + "ProcState_of_regval (regval_of_ProcState v) = Some v" + by (auto simp: regval_of_ProcState_def) + +lemma regval___InstrEnc[simp]: + "InstrEnc_of_regval (regval_of___InstrEnc v) = Some v" + by (auto simp: regval_of___InstrEnc_def) + +lemma regval_bool[simp]: + "bool_of_regval (regval_of_bool v) = Some v" + by (auto simp: regval_of_bool_def) + +lemma regval_signal[simp]: + "signal_of_regval (regval_of_signal v) = Some v" + by (auto simp: regval_of_signal_def) + +lemma regval_vector_128_dec_bit[simp]: + "vector_128_dec_bit_of_regval (regval_of_vector_128_dec_bit v) = Some v" + by (auto simp: regval_of_vector_128_dec_bit_def) + +lemma regval_vector_1_dec_bit[simp]: + "vector_1_dec_bit_of_regval (regval_of_vector_1_dec_bit v) = Some v" + by (auto simp: regval_of_vector_1_dec_bit_def) + +lemma regval_vector_32_dec_bit[simp]: + "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v" + by (auto simp: regval_of_vector_32_dec_bit_def) + +lemma regval_vector_4_dec_bit[simp]: + "vector_4_dec_bit_of_regval (regval_of_vector_4_dec_bit v) = Some v" + by (auto simp: regval_of_vector_4_dec_bit_def) + +lemma regval_vector_52_dec_bit[simp]: + "vector_52_dec_bit_of_regval (regval_of_vector_52_dec_bit v) = Some v" + by (auto simp: regval_of_vector_52_dec_bit_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \ rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_APDAKeyHi_EL1[simp]: + "liftS (read_reg APDAKeyHi_EL1_ref) = readS (APDAKeyHi_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APDAKeyHi_EL1[simp]: + "liftS (write_reg APDAKeyHi_EL1_ref v) = updateS (regstate_update (APDAKeyHi_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APDAKeyLo_EL1[simp]: + "liftS (read_reg APDAKeyLo_EL1_ref) = readS (APDAKeyLo_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APDAKeyLo_EL1[simp]: + "liftS (write_reg APDAKeyLo_EL1_ref v) = updateS (regstate_update (APDAKeyLo_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APDBKeyHi_EL1[simp]: + "liftS (read_reg APDBKeyHi_EL1_ref) = readS (APDBKeyHi_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APDBKeyHi_EL1[simp]: + "liftS (write_reg APDBKeyHi_EL1_ref v) = updateS (regstate_update (APDBKeyHi_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APDBKeyLo_EL1[simp]: + "liftS (read_reg APDBKeyLo_EL1_ref) = readS (APDBKeyLo_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APDBKeyLo_EL1[simp]: + "liftS (write_reg APDBKeyLo_EL1_ref v) = updateS (regstate_update (APDBKeyLo_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APGAKeyHi_EL1[simp]: + "liftS (read_reg APGAKeyHi_EL1_ref) = readS (APGAKeyHi_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APGAKeyHi_EL1[simp]: + "liftS (write_reg APGAKeyHi_EL1_ref v) = updateS (regstate_update (APGAKeyHi_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APGAKeyLo_EL1[simp]: + "liftS (read_reg APGAKeyLo_EL1_ref) = readS (APGAKeyLo_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APGAKeyLo_EL1[simp]: + "liftS (write_reg APGAKeyLo_EL1_ref v) = updateS (regstate_update (APGAKeyLo_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APIAKeyHi_EL1[simp]: + "liftS (read_reg APIAKeyHi_EL1_ref) = readS (APIAKeyHi_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APIAKeyHi_EL1[simp]: + "liftS (write_reg APIAKeyHi_EL1_ref v) = updateS (regstate_update (APIAKeyHi_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APIAKeyLo_EL1[simp]: + "liftS (read_reg APIAKeyLo_EL1_ref) = readS (APIAKeyLo_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APIAKeyLo_EL1[simp]: + "liftS (write_reg APIAKeyLo_EL1_ref v) = updateS (regstate_update (APIAKeyLo_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APIBKeyHi_EL1[simp]: + "liftS (read_reg APIBKeyHi_EL1_ref) = readS (APIBKeyHi_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APIBKeyHi_EL1[simp]: + "liftS (write_reg APIBKeyHi_EL1_ref v) = updateS (regstate_update (APIBKeyHi_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_APIBKeyLo_EL1[simp]: + "liftS (read_reg APIBKeyLo_EL1_ref) = readS (APIBKeyLo_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_APIBKeyLo_EL1[simp]: + "liftS (write_reg APIBKeyLo_EL1_ref v) = updateS (regstate_update (APIBKeyLo_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CONTEXTIDR_EL1[simp]: + "liftS (read_reg CONTEXTIDR_EL1_ref) = readS (CONTEXTIDR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CONTEXTIDR_EL1[simp]: + "liftS (write_reg CONTEXTIDR_EL1_ref v) = updateS (regstate_update (CONTEXTIDR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CONTEXTIDR_EL2[simp]: + "liftS (read_reg CONTEXTIDR_EL2_ref) = readS (CONTEXTIDR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CONTEXTIDR_EL2[simp]: + "liftS (write_reg CONTEXTIDR_EL2_ref v) = updateS (regstate_update (CONTEXTIDR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CPACR_EL1[simp]: + "liftS (read_reg CPACR_EL1_ref) = readS (CPACR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CPACR_EL1[simp]: + "liftS (write_reg CPACR_EL1_ref v) = updateS (regstate_update (CPACR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CPTR_EL2[simp]: + "liftS (read_reg CPTR_EL2_ref) = readS (CPTR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CPTR_EL2[simp]: + "liftS (write_reg CPTR_EL2_ref v) = updateS (regstate_update (CPTR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CPTR_EL3[simp]: + "liftS (read_reg CPTR_EL3_ref) = readS (CPTR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CPTR_EL3[simp]: + "liftS (write_reg CPTR_EL3_ref v) = updateS (regstate_update (CPTR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGBCR_EL1[simp]: + "liftS (read_reg DBGBCR_EL1_ref) = readS (DBGBCR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGBCR_EL1[simp]: + "liftS (write_reg DBGBCR_EL1_ref v) = updateS (regstate_update (DBGBCR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGBVR_EL1[simp]: + "liftS (read_reg DBGBVR_EL1_ref) = readS (DBGBVR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGBVR_EL1[simp]: + "liftS (write_reg DBGBVR_EL1_ref v) = updateS (regstate_update (DBGBVR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGEN[simp]: + "liftS (read_reg DBGEN_ref) = readS (DBGEN \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGEN[simp]: + "liftS (write_reg DBGEN_ref v) = updateS (regstate_update (DBGEN_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGOSDLR[simp]: + "liftS (read_reg DBGOSDLR_ref) = readS (DBGOSDLR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGOSDLR[simp]: + "liftS (write_reg DBGOSDLR_ref v) = updateS (regstate_update (DBGOSDLR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGOSLSR[simp]: + "liftS (read_reg DBGOSLSR_ref) = readS (DBGOSLSR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGOSLSR[simp]: + "liftS (write_reg DBGOSLSR_ref v) = updateS (regstate_update (DBGOSLSR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGPRCR[simp]: + "liftS (read_reg DBGPRCR_ref) = readS (DBGPRCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGPRCR[simp]: + "liftS (write_reg DBGPRCR_ref v) = updateS (regstate_update (DBGPRCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGPRCR_EL1[simp]: + "liftS (read_reg DBGPRCR_EL1_ref) = readS (DBGPRCR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGPRCR_EL1[simp]: + "liftS (write_reg DBGPRCR_EL1_ref v) = updateS (regstate_update (DBGPRCR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGWCR_EL1[simp]: + "liftS (read_reg DBGWCR_EL1_ref) = readS (DBGWCR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGWCR_EL1[simp]: + "liftS (write_reg DBGWCR_EL1_ref v) = updateS (regstate_update (DBGWCR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DBGWVR_EL1[simp]: + "liftS (read_reg DBGWVR_EL1_ref) = readS (DBGWVR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DBGWVR_EL1[simp]: + "liftS (write_reg DBGWVR_EL1_ref v) = updateS (regstate_update (DBGWVR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DLR[simp]: + "liftS (read_reg DLR_ref) = readS (DLR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DLR[simp]: + "liftS (write_reg DLR_ref v) = updateS (regstate_update (DLR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DLR_EL0[simp]: + "liftS (read_reg DLR_EL0_ref) = readS (DLR_EL0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DLR_EL0[simp]: + "liftS (write_reg DLR_EL0_ref v) = updateS (regstate_update (DLR_EL0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DSPSR[simp]: + "liftS (read_reg DSPSR_ref) = readS (DSPSR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DSPSR[simp]: + "liftS (write_reg DSPSR_ref v) = updateS (regstate_update (DSPSR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_DSPSR_EL0[simp]: + "liftS (read_reg DSPSR_EL0_ref) = readS (DSPSR_EL0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_DSPSR_EL0[simp]: + "liftS (write_reg DSPSR_EL0_ref v) = updateS (regstate_update (DSPSR_EL0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_EDSCR[simp]: + "liftS (read_reg EDSCR_ref) = readS (EDSCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_EDSCR[simp]: + "liftS (write_reg EDSCR_ref v) = updateS (regstate_update (EDSCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ELR_EL1[simp]: + "liftS (read_reg ELR_EL1_ref) = readS (ELR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ELR_EL1[simp]: + "liftS (write_reg ELR_EL1_ref v) = updateS (regstate_update (ELR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ELR_EL2[simp]: + "liftS (read_reg ELR_EL2_ref) = readS (ELR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ELR_EL2[simp]: + "liftS (write_reg ELR_EL2_ref v) = updateS (regstate_update (ELR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ELR_EL3[simp]: + "liftS (read_reg ELR_EL3_ref) = readS (ELR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ELR_EL3[simp]: + "liftS (write_reg ELR_EL3_ref v) = updateS (regstate_update (ELR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ELR_hyp[simp]: + "liftS (read_reg ELR_hyp_ref) = readS (ELR_hyp \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ELR_hyp[simp]: + "liftS (write_reg ELR_hyp_ref v) = updateS (regstate_update (ELR_hyp_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ESR_EL1[simp]: + "liftS (read_reg ESR_EL1_ref) = readS (ESR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ESR_EL1[simp]: + "liftS (write_reg ESR_EL1_ref v) = updateS (regstate_update (ESR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ESR_EL2[simp]: + "liftS (read_reg ESR_EL2_ref) = readS (ESR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ESR_EL2[simp]: + "liftS (write_reg ESR_EL2_ref v) = updateS (regstate_update (ESR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ESR_EL3[simp]: + "liftS (read_reg ESR_EL3_ref) = readS (ESR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ESR_EL3[simp]: + "liftS (write_reg ESR_EL3_ref v) = updateS (regstate_update (ESR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_EventRegister[simp]: + "liftS (read_reg EventRegister_ref) = readS (EventRegister \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_EventRegister[simp]: + "liftS (write_reg EventRegister_ref v) = updateS (regstate_update (EventRegister_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FAR_EL1[simp]: + "liftS (read_reg FAR_EL1_ref) = readS (FAR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FAR_EL1[simp]: + "liftS (write_reg FAR_EL1_ref v) = updateS (regstate_update (FAR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FAR_EL2[simp]: + "liftS (read_reg FAR_EL2_ref) = readS (FAR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FAR_EL2[simp]: + "liftS (write_reg FAR_EL2_ref v) = updateS (regstate_update (FAR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FAR_EL3[simp]: + "liftS (read_reg FAR_EL3_ref) = readS (FAR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FAR_EL3[simp]: + "liftS (write_reg FAR_EL3_ref v) = updateS (regstate_update (FAR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FPCR[simp]: + "liftS (read_reg FPCR_ref) = readS (FPCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FPCR[simp]: + "liftS (write_reg FPCR_ref v) = updateS (regstate_update (FPCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FPEXC[simp]: + "liftS (read_reg FPEXC_ref) = readS (FPEXC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FPEXC[simp]: + "liftS (write_reg FPEXC_ref v) = updateS (regstate_update (FPEXC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FPSCR[simp]: + "liftS (read_reg FPSCR_ref) = readS (FPSCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FPSCR[simp]: + "liftS (write_reg FPSCR_ref v) = updateS (regstate_update (FPSCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_FPSR[simp]: + "liftS (read_reg FPSR_ref) = readS (FPSR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_FPSR[simp]: + "liftS (write_reg FPSR_ref v) = updateS (regstate_update (FPSR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HCR[simp]: + "liftS (read_reg HCR_ref) = readS (HCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HCR[simp]: + "liftS (write_reg HCR_ref v) = updateS (regstate_update (HCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HCR2[simp]: + "liftS (read_reg HCR2_ref) = readS (HCR2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HCR2[simp]: + "liftS (write_reg HCR2_ref v) = updateS (regstate_update (HCR2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HCR_EL2[simp]: + "liftS (read_reg HCR_EL2_ref) = readS (HCR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HCR_EL2[simp]: + "liftS (write_reg HCR_EL2_ref v) = updateS (regstate_update (HCR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HDCR[simp]: + "liftS (read_reg HDCR_ref) = readS (HDCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HDCR[simp]: + "liftS (write_reg HDCR_ref v) = updateS (regstate_update (HDCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HDFAR[simp]: + "liftS (read_reg HDFAR_ref) = readS (HDFAR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HDFAR[simp]: + "liftS (write_reg HDFAR_ref v) = updateS (regstate_update (HDFAR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HIFAR[simp]: + "liftS (read_reg HIFAR_ref) = readS (HIFAR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HIFAR[simp]: + "liftS (write_reg HIFAR_ref v) = updateS (regstate_update (HIFAR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HPFAR[simp]: + "liftS (read_reg HPFAR_ref) = readS (HPFAR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HPFAR[simp]: + "liftS (write_reg HPFAR_ref v) = updateS (regstate_update (HPFAR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HPFAR_EL2[simp]: + "liftS (read_reg HPFAR_EL2_ref) = readS (HPFAR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HPFAR_EL2[simp]: + "liftS (write_reg HPFAR_EL2_ref v) = updateS (regstate_update (HPFAR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HSCTLR[simp]: + "liftS (read_reg HSCTLR_ref) = readS (HSCTLR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HSCTLR[simp]: + "liftS (write_reg HSCTLR_ref v) = updateS (regstate_update (HSCTLR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HSR[simp]: + "liftS (read_reg HSR_ref) = readS (HSR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HSR[simp]: + "liftS (write_reg HSR_ref v) = updateS (regstate_update (HSR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HVBAR[simp]: + "liftS (read_reg HVBAR_ref) = readS (HVBAR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HVBAR[simp]: + "liftS (write_reg HVBAR_ref v) = updateS (regstate_update (HVBAR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ID_AA64DFR0_EL1[simp]: + "liftS (read_reg ID_AA64DFR0_EL1_ref) = readS (ID_AA64DFR0_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ID_AA64DFR0_EL1[simp]: + "liftS (write_reg ID_AA64DFR0_EL1_ref v) = updateS (regstate_update (ID_AA64DFR0_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_LR_mon[simp]: + "liftS (read_reg LR_mon_ref) = readS (LR_mon \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_LR_mon[simp]: + "liftS (write_reg LR_mon_ref v) = updateS (regstate_update (LR_mon_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MAIR_EL1[simp]: + "liftS (read_reg MAIR_EL1_ref) = readS (MAIR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MAIR_EL1[simp]: + "liftS (write_reg MAIR_EL1_ref v) = updateS (regstate_update (MAIR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MAIR_EL2[simp]: + "liftS (read_reg MAIR_EL2_ref) = readS (MAIR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MAIR_EL2[simp]: + "liftS (write_reg MAIR_EL2_ref v) = updateS (regstate_update (MAIR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MAIR_EL3[simp]: + "liftS (read_reg MAIR_EL3_ref) = readS (MAIR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MAIR_EL3[simp]: + "liftS (write_reg MAIR_EL3_ref v) = updateS (regstate_update (MAIR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MDCR_EL2[simp]: + "liftS (read_reg MDCR_EL2_ref) = readS (MDCR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MDCR_EL2[simp]: + "liftS (write_reg MDCR_EL2_ref v) = updateS (regstate_update (MDCR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MDCR_EL3[simp]: + "liftS (read_reg MDCR_EL3_ref) = readS (MDCR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MDCR_EL3[simp]: + "liftS (write_reg MDCR_EL3_ref v) = updateS (regstate_update (MDCR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_MDSCR_EL1[simp]: + "liftS (read_reg MDSCR_EL1_ref) = readS (MDSCR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_MDSCR_EL1[simp]: + "liftS (write_reg MDSCR_EL1_ref v) = updateS (regstate_update (MDSCR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_OSDLR_EL1[simp]: + "liftS (read_reg OSDLR_EL1_ref) = readS (OSDLR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_OSDLR_EL1[simp]: + "liftS (write_reg OSDLR_EL1_ref v) = updateS (regstate_update (OSDLR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_OSLSR_EL1[simp]: + "liftS (read_reg OSLSR_EL1_ref) = readS (OSLSR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_OSLSR_EL1[simp]: + "liftS (write_reg OSLSR_EL1_ref v) = updateS (regstate_update (OSLSR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PSTATE[simp]: + "liftS (read_reg PSTATE_ref) = readS (PSTATE \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PSTATE[simp]: + "liftS (write_reg PSTATE_ref v) = updateS (regstate_update (PSTATE_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_RC[simp]: + "liftS (read_reg RC_ref) = readS (RC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_RC[simp]: + "liftS (write_reg RC_ref v) = updateS (regstate_update (RC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_RVBAR_EL1[simp]: + "liftS (read_reg RVBAR_EL1_ref) = readS (RVBAR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_RVBAR_EL1[simp]: + "liftS (write_reg RVBAR_EL1_ref v) = updateS (regstate_update (RVBAR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_RVBAR_EL2[simp]: + "liftS (read_reg RVBAR_EL2_ref) = readS (RVBAR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_RVBAR_EL2[simp]: + "liftS (write_reg RVBAR_EL2_ref v) = updateS (regstate_update (RVBAR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_RVBAR_EL3[simp]: + "liftS (read_reg RVBAR_EL3_ref) = readS (RVBAR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_RVBAR_EL3[simp]: + "liftS (write_reg RVBAR_EL3_ref v) = updateS (regstate_update (RVBAR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCR[simp]: + "liftS (read_reg SCR_ref) = readS (SCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCR[simp]: + "liftS (write_reg SCR_ref v) = updateS (regstate_update (SCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCR_EL3[simp]: + "liftS (read_reg SCR_EL3_ref) = readS (SCR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCR_EL3[simp]: + "liftS (write_reg SCR_EL3_ref v) = updateS (regstate_update (SCR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCTLR[simp]: + "liftS (read_reg SCTLR_ref) = readS (SCTLR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCTLR[simp]: + "liftS (write_reg SCTLR_ref v) = updateS (regstate_update (SCTLR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCTLR_EL1[simp]: + "liftS (read_reg SCTLR_EL1_ref) = readS (SCTLR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCTLR_EL1[simp]: + "liftS (write_reg SCTLR_EL1_ref v) = updateS (regstate_update (SCTLR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCTLR_EL2[simp]: + "liftS (read_reg SCTLR_EL2_ref) = readS (SCTLR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCTLR_EL2[simp]: + "liftS (write_reg SCTLR_EL2_ref v) = updateS (regstate_update (SCTLR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SCTLR_EL3[simp]: + "liftS (read_reg SCTLR_EL3_ref) = readS (SCTLR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SCTLR_EL3[simp]: + "liftS (write_reg SCTLR_EL3_ref v) = updateS (regstate_update (SCTLR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SDCR[simp]: + "liftS (read_reg SDCR_ref) = readS (SDCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SDCR[simp]: + "liftS (write_reg SDCR_ref v) = updateS (regstate_update (SDCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SDER[simp]: + "liftS (read_reg SDER_ref) = readS (SDER \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SDER[simp]: + "liftS (write_reg SDER_ref v) = updateS (regstate_update (SDER_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPIDEN[simp]: + "liftS (read_reg SPIDEN_ref) = readS (SPIDEN \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPIDEN[simp]: + "liftS (write_reg SPIDEN_ref v) = updateS (regstate_update (SPIDEN_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_EL1[simp]: + "liftS (read_reg SPSR_EL1_ref) = readS (SPSR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_EL1[simp]: + "liftS (write_reg SPSR_EL1_ref v) = updateS (regstate_update (SPSR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_EL2[simp]: + "liftS (read_reg SPSR_EL2_ref) = readS (SPSR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_EL2[simp]: + "liftS (write_reg SPSR_EL2_ref v) = updateS (regstate_update (SPSR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_EL3[simp]: + "liftS (read_reg SPSR_EL3_ref) = readS (SPSR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_EL3[simp]: + "liftS (write_reg SPSR_EL3_ref v) = updateS (regstate_update (SPSR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_abt[simp]: + "liftS (read_reg SPSR_abt_ref) = readS (SPSR_abt \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_abt[simp]: + "liftS (write_reg SPSR_abt_ref v) = updateS (regstate_update (SPSR_abt_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_fiq[simp]: + "liftS (read_reg SPSR_fiq_ref) = readS (SPSR_fiq \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_fiq[simp]: + "liftS (write_reg SPSR_fiq_ref v) = updateS (regstate_update (SPSR_fiq_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_hyp[simp]: + "liftS (read_reg SPSR_hyp_ref) = readS (SPSR_hyp \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_hyp[simp]: + "liftS (write_reg SPSR_hyp_ref v) = updateS (regstate_update (SPSR_hyp_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_irq[simp]: + "liftS (read_reg SPSR_irq_ref) = readS (SPSR_irq \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_irq[simp]: + "liftS (write_reg SPSR_irq_ref v) = updateS (regstate_update (SPSR_irq_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_mon[simp]: + "liftS (read_reg SPSR_mon_ref) = readS (SPSR_mon \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_mon[simp]: + "liftS (write_reg SPSR_mon_ref v) = updateS (regstate_update (SPSR_mon_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_svc[simp]: + "liftS (read_reg SPSR_svc_ref) = readS (SPSR_svc \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_svc[simp]: + "liftS (write_reg SPSR_svc_ref v) = updateS (regstate_update (SPSR_svc_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SPSR_und[simp]: + "liftS (read_reg SPSR_und_ref) = readS (SPSR_und \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SPSR_und[simp]: + "liftS (write_reg SPSR_und_ref v) = updateS (regstate_update (SPSR_und_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SP_EL0[simp]: + "liftS (read_reg SP_EL0_ref) = readS (SP_EL0 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SP_EL0[simp]: + "liftS (write_reg SP_EL0_ref v) = updateS (regstate_update (SP_EL0_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SP_EL1[simp]: + "liftS (read_reg SP_EL1_ref) = readS (SP_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SP_EL1[simp]: + "liftS (write_reg SP_EL1_ref v) = updateS (regstate_update (SP_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SP_EL2[simp]: + "liftS (read_reg SP_EL2_ref) = readS (SP_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SP_EL2[simp]: + "liftS (write_reg SP_EL2_ref v) = updateS (regstate_update (SP_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SP_EL3[simp]: + "liftS (read_reg SP_EL3_ref) = readS (SP_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SP_EL3[simp]: + "liftS (write_reg SP_EL3_ref v) = updateS (regstate_update (SP_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_SP_mon[simp]: + "liftS (read_reg SP_mon_ref) = readS (SP_mon \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_SP_mon[simp]: + "liftS (write_reg SP_mon_ref v) = updateS (regstate_update (SP_mon_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TCR_EL1[simp]: + "liftS (read_reg TCR_EL1_ref) = readS (TCR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TCR_EL1[simp]: + "liftS (write_reg TCR_EL1_ref v) = updateS (regstate_update (TCR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TCR_EL2[simp]: + "liftS (read_reg TCR_EL2_ref) = readS (TCR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TCR_EL2[simp]: + "liftS (write_reg TCR_EL2_ref v) = updateS (regstate_update (TCR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TCR_EL3[simp]: + "liftS (read_reg TCR_EL3_ref) = readS (TCR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TCR_EL3[simp]: + "liftS (write_reg TCR_EL3_ref v) = updateS (regstate_update (TCR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBCR[simp]: + "liftS (read_reg TTBCR_ref) = readS (TTBCR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBCR[simp]: + "liftS (write_reg TTBCR_ref v) = updateS (regstate_update (TTBCR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBR0_EL1[simp]: + "liftS (read_reg TTBR0_EL1_ref) = readS (TTBR0_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBR0_EL1[simp]: + "liftS (write_reg TTBR0_EL1_ref v) = updateS (regstate_update (TTBR0_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBR0_EL2[simp]: + "liftS (read_reg TTBR0_EL2_ref) = readS (TTBR0_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBR0_EL2[simp]: + "liftS (write_reg TTBR0_EL2_ref v) = updateS (regstate_update (TTBR0_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBR0_EL3[simp]: + "liftS (read_reg TTBR0_EL3_ref) = readS (TTBR0_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBR0_EL3[simp]: + "liftS (write_reg TTBR0_EL3_ref v) = updateS (regstate_update (TTBR0_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBR1_EL1[simp]: + "liftS (read_reg TTBR1_EL1_ref) = readS (TTBR1_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBR1_EL1[simp]: + "liftS (write_reg TTBR1_EL1_ref v) = updateS (regstate_update (TTBR1_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TTBR1_EL2[simp]: + "liftS (read_reg TTBR1_EL2_ref) = readS (TTBR1_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TTBR1_EL2[simp]: + "liftS (write_reg TTBR1_EL2_ref v) = updateS (regstate_update (TTBR1_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VBAR[simp]: + "liftS (read_reg VBAR_ref) = readS (VBAR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VBAR[simp]: + "liftS (write_reg VBAR_ref v) = updateS (regstate_update (VBAR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VBAR_EL1[simp]: + "liftS (read_reg VBAR_EL1_ref) = readS (VBAR_EL1 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VBAR_EL1[simp]: + "liftS (write_reg VBAR_EL1_ref v) = updateS (regstate_update (VBAR_EL1_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VBAR_EL2[simp]: + "liftS (read_reg VBAR_EL2_ref) = readS (VBAR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VBAR_EL2[simp]: + "liftS (write_reg VBAR_EL2_ref v) = updateS (regstate_update (VBAR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VBAR_EL3[simp]: + "liftS (read_reg VBAR_EL3_ref) = readS (VBAR_EL3 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VBAR_EL3[simp]: + "liftS (write_reg VBAR_EL3_ref v) = updateS (regstate_update (VBAR_EL3_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VDFSR[simp]: + "liftS (read_reg VDFSR_ref) = readS (VDFSR \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VDFSR[simp]: + "liftS (write_reg VDFSR_ref v) = updateS (regstate_update (VDFSR_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VSESR_EL2[simp]: + "liftS (read_reg VSESR_EL2_ref) = readS (VSESR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VSESR_EL2[simp]: + "liftS (write_reg VSESR_EL2_ref v) = updateS (regstate_update (VSESR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VTCR_EL2[simp]: + "liftS (read_reg VTCR_EL2_ref) = readS (VTCR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VTCR_EL2[simp]: + "liftS (write_reg VTCR_EL2_ref v) = updateS (regstate_update (VTCR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_VTTBR_EL2[simp]: + "liftS (read_reg VTTBR_EL2_ref) = readS (VTTBR_EL2 \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_VTTBR_EL2[simp]: + "liftS (write_reg VTTBR_EL2_ref v) = updateS (regstate_update (VTTBR_EL2_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_R[simp]: + "liftS (read_reg R_ref) = readS (R \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_R[simp]: + "liftS (write_reg R_ref v) = updateS (regstate_update (R_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_V[simp]: + "liftS (read_reg V_ref) = readS (V \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_V[simp]: + "liftS (write_reg V_ref v) = updateS (regstate_update (V_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_BranchTaken[simp]: + "liftS (read_reg BranchTaken_ref) = readS (BranchTaken \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_BranchTaken[simp]: + "liftS (write_reg BranchTaken_ref v) = updateS (regstate_update (BranchTaken_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ExclusiveLocal[simp]: + "liftS (read_reg ExclusiveLocal_ref) = readS (ExclusiveLocal \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ExclusiveLocal[simp]: + "liftS (write_reg ExclusiveLocal_ref v) = updateS (regstate_update (ExclusiveLocal_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_Memory[simp]: + "liftS (read_reg Memory_ref) = readS (Memory \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Memory[simp]: + "liftS (write_reg Memory_ref v) = updateS (regstate_update (Memory_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PendingInterrupt[simp]: + "liftS (read_reg PendingInterrupt_ref) = readS (PendingInterrupt \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PendingInterrupt[simp]: + "liftS (write_reg PendingInterrupt_ref v) = updateS (regstate_update (PendingInterrupt_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PendingPhysicalSError[simp]: + "liftS (read_reg PendingPhysicalSError_ref) = readS (PendingPhysicalSError \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PendingPhysicalSError[simp]: + "liftS (write_reg PendingPhysicalSError_ref v) = updateS (regstate_update (PendingPhysicalSError_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_Sleeping[simp]: + "liftS (read_reg Sleeping_ref) = readS (Sleeping \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Sleeping[simp]: + "liftS (write_reg Sleeping_ref v) = updateS (regstate_update (Sleeping_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ThisInstr[simp]: + "liftS (read_reg ThisInstr_ref) = readS (ThisInstr \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ThisInstr[simp]: + "liftS (write_reg ThisInstr_ref v) = updateS (regstate_update (ThisInstr_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_ThisInstrEnc[simp]: + "liftS (read_reg ThisInstrEnc_ref) = readS (ThisInstrEnc \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_ThisInstrEnc[simp]: + "liftS (write_reg ThisInstrEnc_ref v) = updateS (regstate_update (ThisInstrEnc_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_currentCond[simp]: + "liftS (read_reg currentCond_ref) = readS (currentCond \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_currentCond[simp]: + "liftS (write_reg currentCond_ref v) = updateS (regstate_update (currentCond_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_unconditional[simp]: + "liftS (read_reg unconditional_ref) = readS (unconditional \ regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_unconditional[simp]: + "liftS (write_reg unconditional_ref v) = updateS (regstate_update (unconditional_update (\_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/aarch64/Aarch64_types.thy b/snapshots/isabelle/aarch64/Aarch64_types.thy new file mode 100644 index 00000000..b2379614 --- /dev/null +++ b/snapshots/isabelle/aarch64/Aarch64_types.thy @@ -0,0 +1,2511 @@ +chapter \Generated by Lem from aarch64_types.lem.\ + +theory "Aarch64_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from aarch64.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + +datatype exception = + Error_Undefined " (unit)" + | Error_See " (string)" + | Error_Implementation_Defined " (string)" + | Error_ReservedEncoding " (unit)" + | Error_ExceptionTaken " (unit)" + + + +datatype boolean = FALSE | TRUE + + + +datatype signal = LOW | HIGH + + + +datatype RetCode = + RC_OK + | RC_UNDEFINED + | RC_UNPREDICTABLE + | RC_SEE + | RC_IMPLEMENTATION_DEFINED + | RC_SUBARCHITECTURE_DEFINED + | RC_EXCEPTION_TAKEN + | RC_ASSERT_FAILED + | RC_UNMATCHED_CASE + + + +type_synonym CPACRType =" 32 bits " + +type_synonym CNTKCTLType =" 32 bits " + +type_synonym ESRType =" 32 bits " + +type_synonym FPCRType =" 32 bits " + +type_synonym MAIRType =" 64 bits " + +type_synonym SCRType =" 32 bits " + +type_synonym SCTLRType =" 32 bits " + +datatype FPConvOp = + FPConvOp_CVT_FtoI + | FPConvOp_CVT_ItoF + | FPConvOp_MOV_FtoI + | FPConvOp_MOV_ItoF + | FPConvOp_CVT_FtoI_JS + + + +datatype Exception = + Exception_Uncategorized + | Exception_WFxTrap + | Exception_CP15RTTrap + | Exception_CP15RRTTrap + | Exception_CP14RTTrap + | Exception_CP14DTTrap + | Exception_AdvSIMDFPAccessTrap + | Exception_FPIDTrap + | Exception_PACTrap + | Exception_CP14RRTTrap + | Exception_IllegalState + | Exception_SupervisorCall + | Exception_HypervisorCall + | Exception_MonitorCall + | Exception_SystemRegisterTrap + | Exception_ERetTrap + | Exception_InstructionAbort + | Exception_PCAlignment + | Exception_DataAbort + | Exception_SPAlignment + | Exception_FPTrappedException + | Exception_SError + | Exception_Breakpoint + | Exception_SoftwareStep + | Exception_Watchpoint + | Exception_SoftwareBreakpoint + | Exception_VectorCatch + | Exception_IRQ + | Exception_FIQ + + + +datatype ArchVersion = ARMv8p0 | ARMv8p1 | ARMv8p2 | ARMv8p3 + + + +datatype Unpredictable = + Unpredictable_WBOVERLAPLD + | Unpredictable_WBOVERLAPST + | Unpredictable_LDPOVERLAP + | Unpredictable_BASEOVERLAP + | Unpredictable_DATAOVERLAP + | Unpredictable_DEVPAGE2 + | Unpredictable_INSTRDEVICE + | Unpredictable_RESCPACR + | Unpredictable_RESMAIR + | Unpredictable_RESTEXCB + | Unpredictable_RESPRRR + | Unpredictable_RESDACR + | Unpredictable_RESVTCRS + | Unpredictable_RESTnSZ + | Unpredictable_OORTnSZ + | Unpredictable_LARGEIPA + | Unpredictable_ESRCONDPASS + | Unpredictable_ILZEROIT + | Unpredictable_ILZEROT + | Unpredictable_BPVECTORCATCHPRI + | Unpredictable_VCMATCHHALF + | Unpredictable_VCMATCHDAPA + | Unpredictable_WPMASKANDBAS + | Unpredictable_WPBASCONTIGUOUS + | Unpredictable_RESWPMASK + | Unpredictable_WPMASKEDBITS + | Unpredictable_RESBPWPCTRL + | Unpredictable_BPNOTIMPL + | Unpredictable_RESBPTYPE + | Unpredictable_BPNOTCTXCMP + | Unpredictable_BPMATCHHALF + | Unpredictable_BPMISMATCHHALF + | Unpredictable_RESTARTALIGNPC + | Unpredictable_RESTARTZEROUPPERPC + | Unpredictable_ZEROUPPER + | Unpredictable_ERETZEROUPPERPC + | Unpredictable_A32FORCEALIGNPC + | Unpredictable_SMD + | Unpredictable_AFUPDATE + | Unpredictable_IESBinDebug + | Unpredictable_ZEROPMSEVFR + | Unpredictable_NOOPTYPES + | Unpredictable_ZEROMINLATENCY + | Unpredictable_CLEARERRITEZERO + | Unpredictable_TBD + + + +datatype Constraint = + Constraint_NONE + | Constraint_UNKNOWN + | Constraint_UNDEF + | Constraint_UNDEFEL0 + | Constraint_NOP + | Constraint_TRUE + | Constraint_FALSE + | Constraint_DISABLED + | Constraint_UNCOND + | Constraint_COND + | Constraint_ADDITIONAL_DECODE + | Constraint_WBSUPPRESS + | Constraint_FAULT + | Constraint_FORCE + | Constraint_FORCENOSLCHECK + + + +datatype InstrSet = InstrSet_A64 | InstrSet_A32 | InstrSet_T32 + + + +record ProcState = + + ProcState_N ::" 1 bits " + + ProcState_Z ::" 1 bits " + + ProcState_C ::" 1 bits " + + ProcState_V ::" 1 bits " + + ProcState_D ::" 1 bits " + + ProcState_A ::" 1 bits " + + ProcState_I ::" 1 bits " + + ProcState_F ::" 1 bits " + + ProcState_PAN ::" 1 bits " + + ProcState_UAO ::" 1 bits " + + ProcState_SS ::" 1 bits " + + ProcState_IL ::" 1 bits " + + ProcState_EL ::" 2 bits " + + ProcState_nRW ::" 1 bits " + + ProcState_SP ::" 1 bits " + + ProcState_Q ::" 1 bits " + + ProcState_GE ::" 4 bits " + + ProcState_IT ::" 8 bits " + + ProcState_J ::" 1 bits " + + ProcState_T ::" 1 bits " + + ProcState_E ::" 1 bits " + + ProcState_M ::" 5 bits " + + + +datatype BranchType = + BranchType_CALL + | BranchType_ERET + | BranchType_DBGEXIT + | BranchType_RET + | BranchType_JMP + | BranchType_EXCEPTION + | BranchType_UNKNOWN + + + +record ExceptionRecord = + + ExceptionRecord_typ ::" Exception " + + ExceptionRecord_syndrome ::" 25 bits " + + ExceptionRecord_vaddress ::" 64 bits " + + ExceptionRecord_ipavalid ::" bool " + + ExceptionRecord_ipaddress ::" 52 bits " + + + +datatype Fault = + Fault_None + | Fault_AccessFlag + | Fault_Alignment + | Fault_Background + | Fault_Domain + | Fault_Permission + | Fault_Translation + | Fault_AddressSize + | Fault_SyncExternal + | Fault_SyncExternalOnWalk + | Fault_SyncParity + | Fault_SyncParityOnWalk + | Fault_AsyncParity + | Fault_AsyncExternal + | Fault_Debug + | Fault_TLBConflict + | Fault_Lockdown + | Fault_Exclusive + | Fault_ICacheMaint + + + +datatype AccType = + AccType_NORMAL + | AccType_VEC + | AccType_STREAM + | AccType_VECSTREAM + | AccType_ATOMIC + | AccType_ATOMICRW + | AccType_ORDERED + | AccType_ORDEREDRW + | AccType_LIMITEDORDERED + | AccType_UNPRIV + | AccType_IFETCH + | AccType_PTW + | AccType_DC + | AccType_IC + | AccType_DCZVA + | AccType_AT + + + +record FaultRecord = + + FaultRecord_typ ::" Fault " + + FaultRecord_acctype ::" AccType " + + FaultRecord_ipaddress ::" 52 bits " + + FaultRecord_s2fs1walk ::" bool " + + FaultRecord_write ::" bool " + + FaultRecord_level ::" ii " + + FaultRecord_extflag ::" 1 bits " + + FaultRecord_secondstage ::" bool " + + FaultRecord_domain ::" 4 bits " + + FaultRecord_errortype ::" 2 bits " + + FaultRecord_debugmoe ::" 4 bits " + + + +datatype MBReqDomain = + MBReqDomain_Nonshareable + | MBReqDomain_InnerShareable + | MBReqDomain_OuterShareable + | MBReqDomain_FullSystem + + + +datatype MBReqTypes = MBReqTypes_Reads | MBReqTypes_Writes | MBReqTypes_All + + + +datatype MemType = MemType_Normal | MemType_Device + + + +datatype DeviceType = DeviceType_GRE | DeviceType_nGRE | DeviceType_nGnRE | DeviceType_nGnRnE + + + +record MemAttrHints = + + MemAttrHints_attrs ::" 2 bits " + MemAttrHints_hints ::" 2 bits " + MemAttrHints_transient ::" bool " + + + +record MemoryAttributes = + + MemoryAttributes_typ ::" MemType " + + MemoryAttributes_device ::" DeviceType " + + MemoryAttributes_inner ::" MemAttrHints " + + MemoryAttributes_outer ::" MemAttrHints " + + MemoryAttributes_shareable ::" bool " + + MemoryAttributes_outershareable ::" bool " + + + +record FullAddress = + FullAddress_physicaladdress ::" 52 bits " + FullAddress_NS ::" 1 bits " + + + +record AddressDescriptor = + + AddressDescriptor_fault ::" FaultRecord " + + AddressDescriptor_memattrs ::" MemoryAttributes " + + AddressDescriptor_paddress ::" FullAddress " + + AddressDescriptor_vaddress ::" 64 bits " + + + +record DescriptorUpdate = + + DescriptorUpdate_AF ::" bool " + + DescriptorUpdate_AP ::" bool " + + DescriptorUpdate_descaddr ::" AddressDescriptor " + + + +datatype MemAtomicOp = + MemAtomicOp_ADD + | MemAtomicOp_BIC + | MemAtomicOp_EOR + | MemAtomicOp_ORR + | MemAtomicOp_SMAX + | MemAtomicOp_SMIN + | MemAtomicOp_UMAX + | MemAtomicOp_UMIN + | MemAtomicOp_SWP + + + +datatype FPType = FPType_Nonzero | FPType_Zero | FPType_Infinity | FPType_QNaN | FPType_SNaN + + + +datatype FPExc = + FPExc_InvalidOp + | FPExc_DivideByZero + | FPExc_Overflow + | FPExc_Underflow + | FPExc_Inexact + | FPExc_InputDenorm + + + +datatype FPRounding = + FPRounding_TIEEVEN + | FPRounding_POSINF + | FPRounding_NEGINF + | FPRounding_ZERO + | FPRounding_TIEAWAY + | FPRounding_ODD + + + +datatype SysRegAccess = + SysRegAccess_OK + | SysRegAccess_UNDEFINED + | SysRegAccess_TrapToEL1 + | SysRegAccess_TrapToEL2 + | SysRegAccess_TrapToEL3 + + + +datatype SRType = SRType_LSL | SRType_LSR | SRType_ASR | SRType_ROR | SRType_RRX + + + +datatype ShiftType = ShiftType_LSL | ShiftType_LSR | ShiftType_ASR | ShiftType_ROR + + + +datatype PrefetchHint = Prefetch_READ | Prefetch_WRITE | Prefetch_EXEC + + + +datatype InterruptID = + InterruptID_PMUIRQ + | InterruptID_COMMIRQ + | InterruptID_CTIIRQ + | InterruptID_COMMRX + | InterruptID_COMMTX + + + +datatype CrossTriggerOut = + CrossTriggerOut_DebugRequest + | CrossTriggerOut_RestartRequest + | CrossTriggerOut_IRQ + | CrossTriggerOut_RSVD3 + | CrossTriggerOut_TraceExtIn0 + | CrossTriggerOut_TraceExtIn1 + | CrossTriggerOut_TraceExtIn2 + | CrossTriggerOut_TraceExtIn3 + + + +datatype CrossTriggerIn = + CrossTriggerIn_CrossHalt + | CrossTriggerIn_PMUOverflow + | CrossTriggerIn_RSVD2 + | CrossTriggerIn_RSVD3 + | CrossTriggerIn_TraceExtOut0 + | CrossTriggerIn_TraceExtOut1 + | CrossTriggerIn_TraceExtOut2 + | CrossTriggerIn_TraceExtOut3 + + + +datatype MemBarrierOp = MemBarrierOp_DSB | MemBarrierOp_DMB | MemBarrierOp_ISB + + + +record AccessDescriptor = + + AccessDescriptor_acctype ::" AccType " + + AccessDescriptor_page_table_walk ::" bool " + + AccessDescriptor_secondstage ::" bool " + + AccessDescriptor_s2fs1walk ::" bool " + + AccessDescriptor_level ::" ii " + + + +record Permissions = + + Permissions_ap ::" 3 bits " + + Permissions_xn ::" 1 bits " + + Permissions_xxn ::" 1 bits " + + Permissions_pxn ::" 1 bits " + + + +record TLBRecord = + + TLBRecord_perms ::" Permissions " + + TLBRecord_nG ::" 1 bits " + + TLBRecord_domain ::" 4 bits " + + TLBRecord_contiguous ::" bool " + + TLBRecord_level ::" ii " + + TLBRecord_blocksize ::" ii " + + TLBRecord_descupdate ::" DescriptorUpdate " + + TLBRecord_CnP ::" 1 bits " + + TLBRecord_addrdesc ::" AddressDescriptor " + + + +datatype ImmediateOp = ImmediateOp_MOVI | ImmediateOp_MVNI | ImmediateOp_ORR | ImmediateOp_BIC + + + +datatype MoveWideOp = MoveWideOp_N | MoveWideOp_Z | MoveWideOp_K + + + +datatype SystemAccessType = SystemAccessType_RT | SystemAccessType_RRT | SystemAccessType_DT + + + +datatype VBitOp = VBitOp_VBIF | VBitOp_VBIT | VBitOp_VBSL | VBitOp_VEOR + + + +datatype TimeStamp = TimeStamp_None | TimeStamp_Virtual | TimeStamp_Physical + + + +datatype PrivilegeLevel = PL3 | PL2 | PL1 | PL0 + + + +record AArch32_SErrorSyndrome = + + AArch32_SErrorSyndrome_AET ::" 2 bits " + AArch32_SErrorSyndrome_ExT ::" 1 bits " + + + +datatype SystemOp = Sys_AT | Sys_DC | Sys_IC | Sys_TLBI | Sys_SYS + + + +record PCSample = + + PCSample_valid_name ::" bool " + + PCSample_pc ::" 64 bits " + + PCSample_el ::" 2 bits " + + PCSample_rw ::" 1 bits " + + PCSample_ns ::" 1 bits " + + PCSample_contextidr ::" 32 bits " + + PCSample_contextidr_el2 ::" 32 bits " + + PCSample_vmid ::" 16 bits " + + + +datatype ReduceOp = + ReduceOp_FMINNUM | ReduceOp_FMAXNUM | ReduceOp_FMIN | ReduceOp_FMAX | ReduceOp_FADD | ReduceOp_ADD + + + +datatype LogicalOp = LogicalOp_AND | LogicalOp_EOR | LogicalOp_ORR + + + +datatype ExtendType = + ExtendType_SXTB + | ExtendType_SXTH + | ExtendType_SXTW + | ExtendType_SXTX + | ExtendType_UXTB + | ExtendType_UXTH + | ExtendType_UXTW + | ExtendType_UXTX + + + +datatype SystemHintOp = + SystemHintOp_NOP + | SystemHintOp_YIELD + | SystemHintOp_WFE + | SystemHintOp_WFI + | SystemHintOp_SEV + | SystemHintOp_SEVL + | SystemHintOp_ESB + | SystemHintOp_PSB + + + +datatype MemOp = MemOp_LOAD | MemOp_STORE | MemOp_PREFETCH + + + +datatype OpType = OpType_Load | OpType_Store | OpType_LoadAtomic | OpType_Branch | OpType_Other + + + +datatype FPUnaryOp = FPUnaryOp_ABS | FPUnaryOp_MOV | FPUnaryOp_NEG | FPUnaryOp_SQRT + + + +datatype CompareOp = CompareOp_GT | CompareOp_GE | CompareOp_EQ | CompareOp_LE | CompareOp_LT + + + +datatype PSTATEField = + PSTATEField_DAIFSet | PSTATEField_DAIFClr | PSTATEField_PAN | PSTATEField_UAO | PSTATEField_SP + + + +datatype FPMaxMinOp = FPMaxMinOp_MAX | FPMaxMinOp_MIN | FPMaxMinOp_MAXNUM | FPMaxMinOp_MINNUM + + + +datatype CountOp = CountOp_CLZ | CountOp_CLS | CountOp_CNT + + + +datatype VFPNegMul = VFPNegMul_VNMLA | VFPNegMul_VNMLS | VFPNegMul_VNMUL + + + +datatype VBitOps = VBitOps_VBIF | VBitOps_VBIT | VBitOps_VBSL + + + +datatype VCGEtype = VCGEtype_signed | VCGEtype_unsigned | VCGEtype_fp + + + +datatype VCGTtype = VCGTtype_signed | VCGTtype_unsigned | VCGTtype_fp + + + +datatype InstrEnc = A64 | A32 | T16 | T32 + + + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_ProcState " (ProcState)" + | Regval___InstrEnc " (InstrEnc)" + | Regval_bool " (bool)" + | Regval_signal " (signal)" + | Regval_vector_128_dec_bit " ( 128 Word.word)" + | Regval_vector_1_dec_bit " ( 1 Word.word)" + | Regval_vector_32_dec_bit " ( 32 Word.word)" + | Regval_vector_4_dec_bit " ( 4 Word.word)" + | Regval_vector_52_dec_bit " ( 52 Word.word)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + + + +record regstate = + + APDAKeyHi_EL1 ::" 64 Word.word " + + APDAKeyLo_EL1 ::" 64 Word.word " + + APDBKeyHi_EL1 ::" 64 Word.word " + + APDBKeyLo_EL1 ::" 64 Word.word " + + APGAKeyHi_EL1 ::" 64 Word.word " + + APGAKeyLo_EL1 ::" 64 Word.word " + + APIAKeyHi_EL1 ::" 64 Word.word " + + APIAKeyLo_EL1 ::" 64 Word.word " + + APIBKeyHi_EL1 ::" 64 Word.word " + + APIBKeyLo_EL1 ::" 64 Word.word " + + CONTEXTIDR_EL1 ::" 32 Word.word " + + CONTEXTIDR_EL2 ::" 32 Word.word " + + CPACR_EL1 ::" 32 Word.word " + + CPTR_EL2 ::" 32 Word.word " + + CPTR_EL3 ::" 32 Word.word " + + DBGBCR_EL1 ::" ( 32 Word.word) list " + + DBGBVR_EL1 ::" ( 64 Word.word) list " + + DBGEN ::" signal " + + DBGOSDLR ::" 32 Word.word " + + DBGOSLSR ::" 32 Word.word " + + DBGPRCR ::" 32 Word.word " + + DBGPRCR_EL1 ::" 32 Word.word " + + DBGWCR_EL1 ::" ( 32 Word.word) list " + + DBGWVR_EL1 ::" ( 64 Word.word) list " + + DLR ::" 32 Word.word " + + DLR_EL0 ::" 64 Word.word " + + DSPSR ::" 32 Word.word " + + DSPSR_EL0 ::" 32 Word.word " + + EDSCR ::" 32 Word.word " + + ELR_EL1 ::" 64 Word.word " + + ELR_EL2 ::" 64 Word.word " + + ELR_EL3 ::" 64 Word.word " + + ELR_hyp ::" 32 Word.word " + + ESR_EL1 ::" 32 Word.word " + + ESR_EL2 ::" 32 Word.word " + + ESR_EL3 ::" 32 Word.word " + + EventRegister ::" 1 Word.word " + + FAR_EL1 ::" 64 Word.word " + + FAR_EL2 ::" 64 Word.word " + + FAR_EL3 ::" 64 Word.word " + + FPCR ::" 32 Word.word " + + FPEXC ::" 32 Word.word " + + FPSCR ::" 32 Word.word " + + FPSR ::" 32 Word.word " + + HCR ::" 32 Word.word " + + HCR2 ::" 32 Word.word " + + HCR_EL2 ::" 64 Word.word " + + HDCR ::" 32 Word.word " + + HDFAR ::" 32 Word.word " + + HIFAR ::" 32 Word.word " + + HPFAR ::" 32 Word.word " + + HPFAR_EL2 ::" 64 Word.word " + + HSCTLR ::" 32 Word.word " + + HSR ::" 32 Word.word " + + HVBAR ::" 32 Word.word " + + ID_AA64DFR0_EL1 ::" 64 Word.word " + + LR_mon ::" 32 Word.word " + + MAIR_EL1 ::" 64 Word.word " + + MAIR_EL2 ::" 64 Word.word " + + MAIR_EL3 ::" 64 Word.word " + + MDCR_EL2 ::" 32 Word.word " + + MDCR_EL3 ::" 32 Word.word " + + MDSCR_EL1 ::" 32 Word.word " + + OSDLR_EL1 ::" 32 Word.word " + + OSLSR_EL1 ::" 32 Word.word " + + PSTATE ::" ProcState " + + RC ::" ( 64 Word.word) list " + + RVBAR_EL1 ::" 64 Word.word " + + RVBAR_EL2 ::" 64 Word.word " + + RVBAR_EL3 ::" 64 Word.word " + + SCR ::" 32 Word.word " + + SCR_EL3 ::" 32 Word.word " + + SCTLR ::" 32 Word.word " + + SCTLR_EL1 ::" 32 Word.word " + + SCTLR_EL2 ::" 32 Word.word " + + SCTLR_EL3 ::" 32 Word.word " + + SDCR ::" 32 Word.word " + + SDER ::" 32 Word.word " + + SPIDEN ::" signal " + + SPSR_EL1 ::" 32 Word.word " + + SPSR_EL2 ::" 32 Word.word " + + SPSR_EL3 ::" 32 Word.word " + + SPSR_abt ::" 32 Word.word " + + SPSR_fiq ::" 32 Word.word " + + SPSR_hyp ::" 32 Word.word " + + SPSR_irq ::" 32 Word.word " + + SPSR_mon ::" 32 Word.word " + + SPSR_svc ::" 32 Word.word " + + SPSR_und ::" 32 Word.word " + + SP_EL0 ::" 64 Word.word " + + SP_EL1 ::" 64 Word.word " + + SP_EL2 ::" 64 Word.word " + + SP_EL3 ::" 64 Word.word " + + SP_mon ::" 32 Word.word " + + TCR_EL1 ::" 64 Word.word " + + TCR_EL2 ::" 64 Word.word " + + TCR_EL3 ::" 32 Word.word " + + TTBCR ::" 32 Word.word " + + TTBR0_EL1 ::" 64 Word.word " + + TTBR0_EL2 ::" 64 Word.word " + + TTBR0_EL3 ::" 64 Word.word " + + TTBR1_EL1 ::" 64 Word.word " + + TTBR1_EL2 ::" 64 Word.word " + + VBAR ::" 32 Word.word " + + VBAR_EL1 ::" 64 Word.word " + + VBAR_EL2 ::" 64 Word.word " + + VBAR_EL3 ::" 64 Word.word " + + VDFSR ::" 32 Word.word " + + VSESR_EL2 ::" 32 Word.word " + + VTCR_EL2 ::" 32 Word.word " + + VTTBR_EL2 ::" 64 Word.word " + + PC ::" 64 Word.word " + + R ::" ( 64 Word.word) list " + + V ::" ( 128 Word.word) list " + + BranchTaken ::" bool " + + ExclusiveLocal ::" bool " + + Memory ::" 52 Word.word " + + PendingInterrupt ::" bool " + + PendingPhysicalSError ::" bool " + + Sleeping ::" bool " + + ThisInstr ::" 32 Word.word " + + ThisInstrEnc ::" InstrEnc " + + currentCond ::" 4 Word.word " + + unconditional ::" bool " + + + + + +(*val ProcState_of_regval : register_value -> maybe ProcState*) + +fun ProcState_of_regval :: " register_value \(ProcState)option " where + " ProcState_of_regval (Regval_ProcState (v)) = ( Some v )" +|" ProcState_of_regval g__605 = ( None )" + + +(*val regval_of_ProcState : ProcState -> register_value*) + +definition regval_of_ProcState :: " ProcState \ register_value " where + " regval_of_ProcState v = ( Regval_ProcState v )" + + +(*val __InstrEnc_of_regval : register_value -> maybe __InstrEnc*) + +fun InstrEnc_of_regval :: " register_value \(InstrEnc)option " where + " InstrEnc_of_regval (Regval___InstrEnc (v)) = ( Some v )" +|" InstrEnc_of_regval g__604 = ( None )" + + +(*val regval_of___InstrEnc : __InstrEnc -> register_value*) + +definition regval_of___InstrEnc :: " InstrEnc \ register_value " where + " regval_of___InstrEnc v = ( Regval___InstrEnc v )" + + +(*val bool_of_regval : register_value -> maybe bool*) + +fun bool_of_regval :: " register_value \(bool)option " where + " bool_of_regval (Regval_bool (v)) = ( Some v )" +|" bool_of_regval g__603 = ( None )" + + +(*val regval_of_bool : bool -> register_value*) + +definition regval_of_bool :: " bool \ register_value " where + " regval_of_bool v = ( Regval_bool v )" + + +(*val signal_of_regval : register_value -> maybe signal*) + +fun signal_of_regval :: " register_value \(signal)option " where + " signal_of_regval (Regval_signal (v)) = ( Some v )" +|" signal_of_regval g__602 = ( None )" + + +(*val regval_of_signal : signal -> register_value*) + +definition regval_of_signal :: " signal \ register_value " where + " regval_of_signal v = ( Regval_signal v )" + + +(*val vector_128_dec_bit_of_regval : register_value -> maybe (mword ty128)*) + +fun vector_128_dec_bit_of_regval :: " register_value \((128)Word.word)option " where + " vector_128_dec_bit_of_regval (Regval_vector_128_dec_bit (v)) = ( Some v )" +|" vector_128_dec_bit_of_regval g__601 = ( None )" + + +(*val regval_of_vector_128_dec_bit : mword ty128 -> register_value*) + +definition regval_of_vector_128_dec_bit :: "(128)Word.word \ register_value " where + " regval_of_vector_128_dec_bit v = ( Regval_vector_128_dec_bit v )" + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +fun vector_1_dec_bit_of_regval :: " register_value \((1)Word.word)option " where + " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" +|" vector_1_dec_bit_of_regval g__600 = ( None )" + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +definition regval_of_vector_1_dec_bit :: "(1)Word.word \ register_value " where + " regval_of_vector_1_dec_bit v = ( Regval_vector_1_dec_bit v )" + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +fun vector_32_dec_bit_of_regval :: " register_value \((32)Word.word)option " where + " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" +|" vector_32_dec_bit_of_regval g__599 = ( None )" + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +definition regval_of_vector_32_dec_bit :: "(32)Word.word \ register_value " where + " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )" + + +(*val vector_4_dec_bit_of_regval : register_value -> maybe (mword ty4)*) + +fun vector_4_dec_bit_of_regval :: " register_value \((4)Word.word)option " where + " vector_4_dec_bit_of_regval (Regval_vector_4_dec_bit (v)) = ( Some v )" +|" vector_4_dec_bit_of_regval g__598 = ( None )" + + +(*val regval_of_vector_4_dec_bit : mword ty4 -> register_value*) + +definition regval_of_vector_4_dec_bit :: "(4)Word.word \ register_value " where + " regval_of_vector_4_dec_bit v = ( Regval_vector_4_dec_bit v )" + + +(*val vector_52_dec_bit_of_regval : register_value -> maybe (mword ty52)*) + +fun vector_52_dec_bit_of_regval :: " register_value \((52)Word.word)option " where + " vector_52_dec_bit_of_regval (Regval_vector_52_dec_bit (v)) = ( Some v )" +|" vector_52_dec_bit_of_regval g__597 = ( None )" + + +(*val regval_of_vector_52_dec_bit : mword ty52 -> register_value*) + +definition regval_of_vector_52_dec_bit :: "(52)Word.word \ register_value " where + " regval_of_vector_52_dec_bit v = ( Regval_vector_52_dec_bit v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__596 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \ register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " vector_of_regval of_regval1 = ( \x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \ register_value)\ int \ bool \ 'a list \ register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \ 'a option)\ register_value \('a list)option " where + " list_of_regval of_regval1 = ( \x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \ register_value)\ 'a list \ register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \ 'a option)\ register_value \('a option)option " where + " option_of_regval of_regval1 = ( \x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \ register_value)\ 'a option \ register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition APDAKeyHi_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APDAKeyHi_EL1_ref = ( (| + name = (''APDAKeyHi_EL1''), + read_from = (\ s . (APDAKeyHi_EL1 s)), + write_to = (\ v s . (( s (| APDAKeyHi_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APDAKeyLo_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APDAKeyLo_EL1_ref = ( (| + name = (''APDAKeyLo_EL1''), + read_from = (\ s . (APDAKeyLo_EL1 s)), + write_to = (\ v s . (( s (| APDAKeyLo_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APDBKeyHi_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APDBKeyHi_EL1_ref = ( (| + name = (''APDBKeyHi_EL1''), + read_from = (\ s . (APDBKeyHi_EL1 s)), + write_to = (\ v s . (( s (| APDBKeyHi_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APDBKeyLo_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APDBKeyLo_EL1_ref = ( (| + name = (''APDBKeyLo_EL1''), + read_from = (\ s . (APDBKeyLo_EL1 s)), + write_to = (\ v s . (( s (| APDBKeyLo_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APGAKeyHi_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APGAKeyHi_EL1_ref = ( (| + name = (''APGAKeyHi_EL1''), + read_from = (\ s . (APGAKeyHi_EL1 s)), + write_to = (\ v s . (( s (| APGAKeyHi_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APGAKeyLo_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APGAKeyLo_EL1_ref = ( (| + name = (''APGAKeyLo_EL1''), + read_from = (\ s . (APGAKeyLo_EL1 s)), + write_to = (\ v s . (( s (| APGAKeyLo_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APIAKeyHi_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APIAKeyHi_EL1_ref = ( (| + name = (''APIAKeyHi_EL1''), + read_from = (\ s . (APIAKeyHi_EL1 s)), + write_to = (\ v s . (( s (| APIAKeyHi_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APIAKeyLo_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APIAKeyLo_EL1_ref = ( (| + name = (''APIAKeyLo_EL1''), + read_from = (\ s . (APIAKeyLo_EL1 s)), + write_to = (\ v s . (( s (| APIAKeyLo_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APIBKeyHi_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APIBKeyHi_EL1_ref = ( (| + name = (''APIBKeyHi_EL1''), + read_from = (\ s . (APIBKeyHi_EL1 s)), + write_to = (\ v s . (( s (| APIBKeyHi_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition APIBKeyLo_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " APIBKeyLo_EL1_ref = ( (| + name = (''APIBKeyLo_EL1''), + read_from = (\ s . (APIBKeyLo_EL1 s)), + write_to = (\ v s . (( s (| APIBKeyLo_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition CONTEXTIDR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CONTEXTIDR_EL1_ref = ( (| + name = (''CONTEXTIDR_EL1''), + read_from = (\ s . (CONTEXTIDR_EL1 s)), + write_to = (\ v s . (( s (| CONTEXTIDR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CONTEXTIDR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CONTEXTIDR_EL2_ref = ( (| + name = (''CONTEXTIDR_EL2''), + read_from = (\ s . (CONTEXTIDR_EL2 s)), + write_to = (\ v s . (( s (| CONTEXTIDR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CPACR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CPACR_EL1_ref = ( (| + name = (''CPACR_EL1''), + read_from = (\ s . (CPACR_EL1 s)), + write_to = (\ v s . (( s (| CPACR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CPTR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CPTR_EL2_ref = ( (| + name = (''CPTR_EL2''), + read_from = (\ s . (CPTR_EL2 s)), + write_to = (\ v s . (( s (| CPTR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition CPTR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CPTR_EL3_ref = ( (| + name = (''CPTR_EL3''), + read_from = (\ s . (CPTR_EL3 s)), + write_to = (\ v s . (( s (| CPTR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DBGBCR_EL1_ref :: "((regstate),(register_value),(((32)Word.word)list))register_ref " where + " DBGBCR_EL1_ref = ( (| + name = (''DBGBCR_EL1''), + read_from = (\ s . (DBGBCR_EL1 s)), + write_to = (\ v s . (( s (| DBGBCR_EL1 := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_32_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_32_dec_bit v)(( 16 :: int)) False v) |) )" + + +definition DBGBVR_EL1_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " DBGBVR_EL1_ref = ( (| + name = (''DBGBVR_EL1''), + read_from = (\ s . (DBGBVR_EL1 s)), + write_to = (\ v s . (( s (| DBGBVR_EL1 := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 16 :: int)) False v) |) )" + + +definition DBGEN_ref :: "((regstate),(register_value),(signal))register_ref " where + " DBGEN_ref = ( (| + name = (''DBGEN''), + read_from = (\ s . (DBGEN s)), + write_to = (\ v s . (( s (| DBGEN := v |)))), + of_regval = (\ v . signal_of_regval v), + regval_of = (\ v . regval_of_signal v) |) )" + + +definition DBGOSDLR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DBGOSDLR_ref = ( (| + name = (''DBGOSDLR''), + read_from = (\ s . (DBGOSDLR s)), + write_to = (\ v s . (( s (| DBGOSDLR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DBGOSLSR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DBGOSLSR_ref = ( (| + name = (''DBGOSLSR''), + read_from = (\ s . (DBGOSLSR s)), + write_to = (\ v s . (( s (| DBGOSLSR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DBGPRCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DBGPRCR_ref = ( (| + name = (''DBGPRCR''), + read_from = (\ s . (DBGPRCR s)), + write_to = (\ v s . (( s (| DBGPRCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DBGPRCR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DBGPRCR_EL1_ref = ( (| + name = (''DBGPRCR_EL1''), + read_from = (\ s . (DBGPRCR_EL1 s)), + write_to = (\ v s . (( s (| DBGPRCR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DBGWCR_EL1_ref :: "((regstate),(register_value),(((32)Word.word)list))register_ref " where + " DBGWCR_EL1_ref = ( (| + name = (''DBGWCR_EL1''), + read_from = (\ s . (DBGWCR_EL1 s)), + write_to = (\ v s . (( s (| DBGWCR_EL1 := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_32_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_32_dec_bit v)(( 16 :: int)) False v) |) )" + + +definition DBGWVR_EL1_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " DBGWVR_EL1_ref = ( (| + name = (''DBGWVR_EL1''), + read_from = (\ s . (DBGWVR_EL1 s)), + write_to = (\ v s . (( s (| DBGWVR_EL1 := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 16 :: int)) False v) |) )" + + +definition DLR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DLR_ref = ( (| + name = (''DLR''), + read_from = (\ s . (DLR s)), + write_to = (\ v s . (( s (| DLR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DLR_EL0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " DLR_EL0_ref = ( (| + name = (''DLR_EL0''), + read_from = (\ s . (DLR_EL0 s)), + write_to = (\ v s . (( s (| DLR_EL0 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition DSPSR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DSPSR_ref = ( (| + name = (''DSPSR''), + read_from = (\ s . (DSPSR s)), + write_to = (\ v s . (( s (| DSPSR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition DSPSR_EL0_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " DSPSR_EL0_ref = ( (| + name = (''DSPSR_EL0''), + read_from = (\ s . (DSPSR_EL0 s)), + write_to = (\ v s . (( s (| DSPSR_EL0 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition EDSCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " EDSCR_ref = ( (| + name = (''EDSCR''), + read_from = (\ s . (EDSCR s)), + write_to = (\ v s . (( s (| EDSCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ELR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " ELR_EL1_ref = ( (| + name = (''ELR_EL1''), + read_from = (\ s . (ELR_EL1 s)), + write_to = (\ v s . (( s (| ELR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition ELR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " ELR_EL2_ref = ( (| + name = (''ELR_EL2''), + read_from = (\ s . (ELR_EL2 s)), + write_to = (\ v s . (( s (| ELR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition ELR_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " ELR_EL3_ref = ( (| + name = (''ELR_EL3''), + read_from = (\ s . (ELR_EL3 s)), + write_to = (\ v s . (( s (| ELR_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition ELR_hyp_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " ELR_hyp_ref = ( (| + name = (''ELR_hyp''), + read_from = (\ s . (ELR_hyp s)), + write_to = (\ v s . (( s (| ELR_hyp := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ESR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " ESR_EL1_ref = ( (| + name = (''ESR_EL1''), + read_from = (\ s . (ESR_EL1 s)), + write_to = (\ v s . (( s (| ESR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ESR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " ESR_EL2_ref = ( (| + name = (''ESR_EL2''), + read_from = (\ s . (ESR_EL2 s)), + write_to = (\ v s . (( s (| ESR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ESR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " ESR_EL3_ref = ( (| + name = (''ESR_EL3''), + read_from = (\ s . (ESR_EL3 s)), + write_to = (\ v s . (( s (| ESR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition EventRegister_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " EventRegister_ref = ( (| + name = (''EventRegister''), + read_from = (\ s . (EventRegister s)), + write_to = (\ v s . (( s (| EventRegister := v |)))), + of_regval = (\ v . vector_1_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_1_dec_bit v) |) )" + + +definition FAR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " FAR_EL1_ref = ( (| + name = (''FAR_EL1''), + read_from = (\ s . (FAR_EL1 s)), + write_to = (\ v s . (( s (| FAR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition FAR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " FAR_EL2_ref = ( (| + name = (''FAR_EL2''), + read_from = (\ s . (FAR_EL2 s)), + write_to = (\ v s . (( s (| FAR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition FAR_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " FAR_EL3_ref = ( (| + name = (''FAR_EL3''), + read_from = (\ s . (FAR_EL3 s)), + write_to = (\ v s . (( s (| FAR_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition FPCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " FPCR_ref = ( (| + name = (''FPCR''), + read_from = (\ s . (FPCR s)), + write_to = (\ v s . (( s (| FPCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition FPEXC_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " FPEXC_ref = ( (| + name = (''FPEXC''), + read_from = (\ s . (FPEXC s)), + write_to = (\ v s . (( s (| FPEXC := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition FPSCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " FPSCR_ref = ( (| + name = (''FPSCR''), + read_from = (\ s . (FPSCR s)), + write_to = (\ v s . (( s (| FPSCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition FPSR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " FPSR_ref = ( (| + name = (''FPSR''), + read_from = (\ s . (FPSR s)), + write_to = (\ v s . (( s (| FPSR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HCR_ref = ( (| + name = (''HCR''), + read_from = (\ s . (HCR s)), + write_to = (\ v s . (( s (| HCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HCR2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HCR2_ref = ( (| + name = (''HCR2''), + read_from = (\ s . (HCR2 s)), + write_to = (\ v s . (( s (| HCR2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HCR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " HCR_EL2_ref = ( (| + name = (''HCR_EL2''), + read_from = (\ s . (HCR_EL2 s)), + write_to = (\ v s . (( s (| HCR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition HDCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HDCR_ref = ( (| + name = (''HDCR''), + read_from = (\ s . (HDCR s)), + write_to = (\ v s . (( s (| HDCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HDFAR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HDFAR_ref = ( (| + name = (''HDFAR''), + read_from = (\ s . (HDFAR s)), + write_to = (\ v s . (( s (| HDFAR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HIFAR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HIFAR_ref = ( (| + name = (''HIFAR''), + read_from = (\ s . (HIFAR s)), + write_to = (\ v s . (( s (| HIFAR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HPFAR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HPFAR_ref = ( (| + name = (''HPFAR''), + read_from = (\ s . (HPFAR s)), + write_to = (\ v s . (( s (| HPFAR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HPFAR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " HPFAR_EL2_ref = ( (| + name = (''HPFAR_EL2''), + read_from = (\ s . (HPFAR_EL2 s)), + write_to = (\ v s . (( s (| HPFAR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition HSCTLR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HSCTLR_ref = ( (| + name = (''HSCTLR''), + read_from = (\ s . (HSCTLR s)), + write_to = (\ v s . (( s (| HSCTLR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HSR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HSR_ref = ( (| + name = (''HSR''), + read_from = (\ s . (HSR s)), + write_to = (\ v s . (( s (| HSR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition HVBAR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " HVBAR_ref = ( (| + name = (''HVBAR''), + read_from = (\ s . (HVBAR s)), + write_to = (\ v s . (( s (| HVBAR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ID_AA64DFR0_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " ID_AA64DFR0_EL1_ref = ( (| + name = (''ID_AA64DFR0_EL1''), + read_from = (\ s . (ID_AA64DFR0_EL1 s)), + write_to = (\ v s . (( s (| ID_AA64DFR0_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition LR_mon_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " LR_mon_ref = ( (| + name = (''LR_mon''), + read_from = (\ s . (LR_mon s)), + write_to = (\ v s . (( s (| LR_mon := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition MAIR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " MAIR_EL1_ref = ( (| + name = (''MAIR_EL1''), + read_from = (\ s . (MAIR_EL1 s)), + write_to = (\ v s . (( s (| MAIR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition MAIR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " MAIR_EL2_ref = ( (| + name = (''MAIR_EL2''), + read_from = (\ s . (MAIR_EL2 s)), + write_to = (\ v s . (( s (| MAIR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition MAIR_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " MAIR_EL3_ref = ( (| + name = (''MAIR_EL3''), + read_from = (\ s . (MAIR_EL3 s)), + write_to = (\ v s . (( s (| MAIR_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition MDCR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " MDCR_EL2_ref = ( (| + name = (''MDCR_EL2''), + read_from = (\ s . (MDCR_EL2 s)), + write_to = (\ v s . (( s (| MDCR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition MDCR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " MDCR_EL3_ref = ( (| + name = (''MDCR_EL3''), + read_from = (\ s . (MDCR_EL3 s)), + write_to = (\ v s . (( s (| MDCR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition MDSCR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " MDSCR_EL1_ref = ( (| + name = (''MDSCR_EL1''), + read_from = (\ s . (MDSCR_EL1 s)), + write_to = (\ v s . (( s (| MDSCR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition OSDLR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " OSDLR_EL1_ref = ( (| + name = (''OSDLR_EL1''), + read_from = (\ s . (OSDLR_EL1 s)), + write_to = (\ v s . (( s (| OSDLR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition OSLSR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " OSLSR_EL1_ref = ( (| + name = (''OSLSR_EL1''), + read_from = (\ s . (OSLSR_EL1 s)), + write_to = (\ v s . (( s (| OSLSR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition PSTATE_ref :: "((regstate),(register_value),(ProcState))register_ref " where + " PSTATE_ref = ( (| + name = (''PSTATE''), + read_from = (\ s . (PSTATE s)), + write_to = (\ v s . (( s (| PSTATE := v |)))), + of_regval = (\ v . ProcState_of_regval v), + regval_of = (\ v . regval_of_ProcState v) |) )" + + +definition RC_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " RC_ref = ( (| + name = (''RC''), + read_from = (\ s . (RC s)), + write_to = (\ v s . (( s (| RC := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 5 :: int)) False v) |) )" + + +definition RVBAR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " RVBAR_EL1_ref = ( (| + name = (''RVBAR_EL1''), + read_from = (\ s . (RVBAR_EL1 s)), + write_to = (\ v s . (( s (| RVBAR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition RVBAR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " RVBAR_EL2_ref = ( (| + name = (''RVBAR_EL2''), + read_from = (\ s . (RVBAR_EL2 s)), + write_to = (\ v s . (( s (| RVBAR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition RVBAR_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " RVBAR_EL3_ref = ( (| + name = (''RVBAR_EL3''), + read_from = (\ s . (RVBAR_EL3 s)), + write_to = (\ v s . (( s (| RVBAR_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition SCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCR_ref = ( (| + name = (''SCR''), + read_from = (\ s . (SCR s)), + write_to = (\ v s . (( s (| SCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SCR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCR_EL3_ref = ( (| + name = (''SCR_EL3''), + read_from = (\ s . (SCR_EL3 s)), + write_to = (\ v s . (( s (| SCR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SCTLR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCTLR_ref = ( (| + name = (''SCTLR''), + read_from = (\ s . (SCTLR s)), + write_to = (\ v s . (( s (| SCTLR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SCTLR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCTLR_EL1_ref = ( (| + name = (''SCTLR_EL1''), + read_from = (\ s . (SCTLR_EL1 s)), + write_to = (\ v s . (( s (| SCTLR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SCTLR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCTLR_EL2_ref = ( (| + name = (''SCTLR_EL2''), + read_from = (\ s . (SCTLR_EL2 s)), + write_to = (\ v s . (( s (| SCTLR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SCTLR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SCTLR_EL3_ref = ( (| + name = (''SCTLR_EL3''), + read_from = (\ s . (SCTLR_EL3 s)), + write_to = (\ v s . (( s (| SCTLR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SDCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SDCR_ref = ( (| + name = (''SDCR''), + read_from = (\ s . (SDCR s)), + write_to = (\ v s . (( s (| SDCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SDER_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SDER_ref = ( (| + name = (''SDER''), + read_from = (\ s . (SDER s)), + write_to = (\ v s . (( s (| SDER := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPIDEN_ref :: "((regstate),(register_value),(signal))register_ref " where + " SPIDEN_ref = ( (| + name = (''SPIDEN''), + read_from = (\ s . (SPIDEN s)), + write_to = (\ v s . (( s (| SPIDEN := v |)))), + of_regval = (\ v . signal_of_regval v), + regval_of = (\ v . regval_of_signal v) |) )" + + +definition SPSR_EL1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_EL1_ref = ( (| + name = (''SPSR_EL1''), + read_from = (\ s . (SPSR_EL1 s)), + write_to = (\ v s . (( s (| SPSR_EL1 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_EL2_ref = ( (| + name = (''SPSR_EL2''), + read_from = (\ s . (SPSR_EL2 s)), + write_to = (\ v s . (( s (| SPSR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_EL3_ref = ( (| + name = (''SPSR_EL3''), + read_from = (\ s . (SPSR_EL3 s)), + write_to = (\ v s . (( s (| SPSR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_abt_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_abt_ref = ( (| + name = (''SPSR_abt''), + read_from = (\ s . (SPSR_abt s)), + write_to = (\ v s . (( s (| SPSR_abt := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_fiq_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_fiq_ref = ( (| + name = (''SPSR_fiq''), + read_from = (\ s . (SPSR_fiq s)), + write_to = (\ v s . (( s (| SPSR_fiq := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_hyp_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_hyp_ref = ( (| + name = (''SPSR_hyp''), + read_from = (\ s . (SPSR_hyp s)), + write_to = (\ v s . (( s (| SPSR_hyp := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_irq_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_irq_ref = ( (| + name = (''SPSR_irq''), + read_from = (\ s . (SPSR_irq s)), + write_to = (\ v s . (( s (| SPSR_irq := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_mon_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_mon_ref = ( (| + name = (''SPSR_mon''), + read_from = (\ s . (SPSR_mon s)), + write_to = (\ v s . (( s (| SPSR_mon := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_svc_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_svc_ref = ( (| + name = (''SPSR_svc''), + read_from = (\ s . (SPSR_svc s)), + write_to = (\ v s . (( s (| SPSR_svc := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SPSR_und_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SPSR_und_ref = ( (| + name = (''SPSR_und''), + read_from = (\ s . (SPSR_und s)), + write_to = (\ v s . (( s (| SPSR_und := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition SP_EL0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " SP_EL0_ref = ( (| + name = (''SP_EL0''), + read_from = (\ s . (SP_EL0 s)), + write_to = (\ v s . (( s (| SP_EL0 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition SP_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " SP_EL1_ref = ( (| + name = (''SP_EL1''), + read_from = (\ s . (SP_EL1 s)), + write_to = (\ v s . (( s (| SP_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition SP_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " SP_EL2_ref = ( (| + name = (''SP_EL2''), + read_from = (\ s . (SP_EL2 s)), + write_to = (\ v s . (( s (| SP_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition SP_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " SP_EL3_ref = ( (| + name = (''SP_EL3''), + read_from = (\ s . (SP_EL3 s)), + write_to = (\ v s . (( s (| SP_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition SP_mon_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " SP_mon_ref = ( (| + name = (''SP_mon''), + read_from = (\ s . (SP_mon s)), + write_to = (\ v s . (( s (| SP_mon := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition TCR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TCR_EL1_ref = ( (| + name = (''TCR_EL1''), + read_from = (\ s . (TCR_EL1 s)), + write_to = (\ v s . (( s (| TCR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TCR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TCR_EL2_ref = ( (| + name = (''TCR_EL2''), + read_from = (\ s . (TCR_EL2 s)), + write_to = (\ v s . (( s (| TCR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TCR_EL3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " TCR_EL3_ref = ( (| + name = (''TCR_EL3''), + read_from = (\ s . (TCR_EL3 s)), + write_to = (\ v s . (( s (| TCR_EL3 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition TTBCR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " TTBCR_ref = ( (| + name = (''TTBCR''), + read_from = (\ s . (TTBCR s)), + write_to = (\ v s . (( s (| TTBCR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition TTBR0_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TTBR0_EL1_ref = ( (| + name = (''TTBR0_EL1''), + read_from = (\ s . (TTBR0_EL1 s)), + write_to = (\ v s . (( s (| TTBR0_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TTBR0_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TTBR0_EL2_ref = ( (| + name = (''TTBR0_EL2''), + read_from = (\ s . (TTBR0_EL2 s)), + write_to = (\ v s . (( s (| TTBR0_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TTBR0_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TTBR0_EL3_ref = ( (| + name = (''TTBR0_EL3''), + read_from = (\ s . (TTBR0_EL3 s)), + write_to = (\ v s . (( s (| TTBR0_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TTBR1_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TTBR1_EL1_ref = ( (| + name = (''TTBR1_EL1''), + read_from = (\ s . (TTBR1_EL1 s)), + write_to = (\ v s . (( s (| TTBR1_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition TTBR1_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " TTBR1_EL2_ref = ( (| + name = (''TTBR1_EL2''), + read_from = (\ s . (TTBR1_EL2 s)), + write_to = (\ v s . (( s (| TTBR1_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition VBAR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " VBAR_ref = ( (| + name = (''VBAR''), + read_from = (\ s . (VBAR s)), + write_to = (\ v s . (( s (| VBAR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition VBAR_EL1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " VBAR_EL1_ref = ( (| + name = (''VBAR_EL1''), + read_from = (\ s . (VBAR_EL1 s)), + write_to = (\ v s . (( s (| VBAR_EL1 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition VBAR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " VBAR_EL2_ref = ( (| + name = (''VBAR_EL2''), + read_from = (\ s . (VBAR_EL2 s)), + write_to = (\ v s . (( s (| VBAR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition VBAR_EL3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " VBAR_EL3_ref = ( (| + name = (''VBAR_EL3''), + read_from = (\ s . (VBAR_EL3 s)), + write_to = (\ v s . (( s (| VBAR_EL3 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition VDFSR_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " VDFSR_ref = ( (| + name = (''VDFSR''), + read_from = (\ s . (VDFSR s)), + write_to = (\ v s . (( s (| VDFSR := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition VSESR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " VSESR_EL2_ref = ( (| + name = (''VSESR_EL2''), + read_from = (\ s . (VSESR_EL2 s)), + write_to = (\ v s . (( s (| VSESR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition VTCR_EL2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " VTCR_EL2_ref = ( (| + name = (''VTCR_EL2''), + read_from = (\ s . (VTCR_EL2 s)), + write_to = (\ v s . (( s (| VTCR_EL2 := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition VTTBR_EL2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " VTTBR_EL2_ref = ( (| + name = (''VTTBR_EL2''), + read_from = (\ s . (VTTBR_EL2 s)), + write_to = (\ v s . (( s (| VTTBR_EL2 := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''_PC''), + read_from = (\ s . (PC s)), + write_to = (\ v s . (( s (| PC := v |)))), + of_regval = (\ v . vector_64_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_64_dec_bit v) |) )" + + +definition R_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " R_ref = ( (| + name = (''_R''), + read_from = (\ s . (R s)), + write_to = (\ v s . (( s (| R := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 31 :: int)) False v) |) )" + + +definition V_ref :: "((regstate),(register_value),(((128)Word.word)list))register_ref " where + " V_ref = ( (| + name = (''_V''), + read_from = (\ s . (V s)), + write_to = (\ v s . (( s (| V := v |)))), + of_regval = (\ v . vector_of_regval (\ v . vector_128_dec_bit_of_regval v) v), + regval_of = (\ v . regval_of_vector (\ v . regval_of_vector_128_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition BranchTaken_ref :: "((regstate),(register_value),(bool))register_ref " where + " BranchTaken_ref = ( (| + name = (''__BranchTaken''), + read_from = (\ s . (BranchTaken s)), + write_to = (\ v s . (( s (| BranchTaken := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +definition ExclusiveLocal_ref :: "((regstate),(register_value),(bool))register_ref " where + " ExclusiveLocal_ref = ( (| + name = (''__ExclusiveLocal''), + read_from = (\ s . (ExclusiveLocal s)), + write_to = (\ v s . (( s (| ExclusiveLocal := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +definition Memory_ref :: "((regstate),(register_value),((52)Word.word))register_ref " where + " Memory_ref = ( (| + name = (''__Memory''), + read_from = (\ s . (Memory s)), + write_to = (\ v s . (( s (| Memory := v |)))), + of_regval = (\ v . vector_52_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_52_dec_bit v) |) )" + + +definition PendingInterrupt_ref :: "((regstate),(register_value),(bool))register_ref " where + " PendingInterrupt_ref = ( (| + name = (''__PendingInterrupt''), + read_from = (\ s . (PendingInterrupt s)), + write_to = (\ v s . (( s (| PendingInterrupt := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +definition PendingPhysicalSError_ref :: "((regstate),(register_value),(bool))register_ref " where + " PendingPhysicalSError_ref = ( (| + name = (''__PendingPhysicalSError''), + read_from = (\ s . (PendingPhysicalSError s)), + write_to = (\ v s . (( s (| PendingPhysicalSError := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +definition Sleeping_ref :: "((regstate),(register_value),(bool))register_ref " where + " Sleeping_ref = ( (| + name = (''__Sleeping''), + read_from = (\ s . (Sleeping s)), + write_to = (\ v s . (( s (| Sleeping := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +definition ThisInstr_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " ThisInstr_ref = ( (| + name = (''__ThisInstr''), + read_from = (\ s . (ThisInstr s)), + write_to = (\ v s . (( s (| ThisInstr := v |)))), + of_regval = (\ v . vector_32_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_32_dec_bit v) |) )" + + +definition ThisInstrEnc_ref :: "((regstate),(register_value),(InstrEnc))register_ref " where + " ThisInstrEnc_ref = ( (| + name = (''__ThisInstrEnc''), + read_from = (\ s . (ThisInstrEnc s)), + write_to = (\ v s . (( s (| ThisInstrEnc := v |)))), + of_regval = (\ v . InstrEnc_of_regval v), + regval_of = (\ v . regval_of___InstrEnc v) |) )" + + +definition currentCond_ref :: "((regstate),(register_value),((4)Word.word))register_ref " where + " currentCond_ref = ( (| + name = (''__currentCond''), + read_from = (\ s . (currentCond s)), + write_to = (\ v s . (( s (| currentCond := v |)))), + of_regval = (\ v . vector_4_dec_bit_of_regval v), + regval_of = (\ v . regval_of_vector_4_dec_bit v) |) )" + + +definition unconditional_ref :: "((regstate),(register_value),(bool))register_ref " where + " unconditional_ref = ( (| + name = (''__unconditional''), + read_from = (\ s . (unconditional s)), + write_to = (\ v s . (( s (| unconditional := v |)))), + of_regval = (\ v . bool_of_regval v), + regval_of = (\ v . regval_of_bool v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \ regstate \(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''APDAKeyHi_EL1'') then Some ((regval_of APDAKeyHi_EL1_ref) ((read_from APDAKeyHi_EL1_ref) s)) else + if reg_name = (''APDAKeyLo_EL1'') then Some ((regval_of APDAKeyLo_EL1_ref) ((read_from APDAKeyLo_EL1_ref) s)) else + if reg_name = (''APDBKeyHi_EL1'') then Some ((regval_of APDBKeyHi_EL1_ref) ((read_from APDBKeyHi_EL1_ref) s)) else + if reg_name = (''APDBKeyLo_EL1'') then Some ((regval_of APDBKeyLo_EL1_ref) ((read_from APDBKeyLo_EL1_ref) s)) else + if reg_name = (''APGAKeyHi_EL1'') then Some ((regval_of APGAKeyHi_EL1_ref) ((read_from APGAKeyHi_EL1_ref) s)) else + if reg_name = (''APGAKeyLo_EL1'') then Some ((regval_of APGAKeyLo_EL1_ref) ((read_from APGAKeyLo_EL1_ref) s)) else + if reg_name = (''APIAKeyHi_EL1'') then Some ((regval_of APIAKeyHi_EL1_ref) ((read_from APIAKeyHi_EL1_ref) s)) else + if reg_name = (''APIAKeyLo_EL1'') then Some ((regval_of APIAKeyLo_EL1_ref) ((read_from APIAKeyLo_EL1_ref) s)) else + if reg_name = (''APIBKeyHi_EL1'') then Some ((regval_of APIBKeyHi_EL1_ref) ((read_from APIBKeyHi_EL1_ref) s)) else + if reg_name = (''APIBKeyLo_EL1'') then Some ((regval_of APIBKeyLo_EL1_ref) ((read_from APIBKeyLo_EL1_ref) s)) else + if reg_name = (''CONTEXTIDR_EL1'') then Some ((regval_of CONTEXTIDR_EL1_ref) ((read_from CONTEXTIDR_EL1_ref) s)) else + if reg_name = (''CONTEXTIDR_EL2'') then Some ((regval_of CONTEXTIDR_EL2_ref) ((read_from CONTEXTIDR_EL2_ref) s)) else + if reg_name = (''CPACR_EL1'') then Some ((regval_of CPACR_EL1_ref) ((read_from CPACR_EL1_ref) s)) else + if reg_name = (''CPTR_EL2'') then Some ((regval_of CPTR_EL2_ref) ((read_from CPTR_EL2_ref) s)) else + if reg_name = (''CPTR_EL3'') then Some ((regval_of CPTR_EL3_ref) ((read_from CPTR_EL3_ref) s)) else + if reg_name = (''DBGBCR_EL1'') then Some ((regval_of DBGBCR_EL1_ref) ((read_from DBGBCR_EL1_ref) s)) else + if reg_name = (''DBGBVR_EL1'') then Some ((regval_of DBGBVR_EL1_ref) ((read_from DBGBVR_EL1_ref) s)) else + if reg_name = (''DBGEN'') then Some ((regval_of DBGEN_ref) ((read_from DBGEN_ref) s)) else + if reg_name = (''DBGOSDLR'') then Some ((regval_of DBGOSDLR_ref) ((read_from DBGOSDLR_ref) s)) else + if reg_name = (''DBGOSLSR'') then Some ((regval_of DBGOSLSR_ref) ((read_from DBGOSLSR_ref) s)) else + if reg_name = (''DBGPRCR'') then Some ((regval_of DBGPRCR_ref) ((read_from DBGPRCR_ref) s)) else + if reg_name = (''DBGPRCR_EL1'') then Some ((regval_of DBGPRCR_EL1_ref) ((read_from DBGPRCR_EL1_ref) s)) else + if reg_name = (''DBGWCR_EL1'') then Some ((regval_of DBGWCR_EL1_ref) ((read_from DBGWCR_EL1_ref) s)) else + if reg_name = (''DBGWVR_EL1'') then Some ((regval_of DBGWVR_EL1_ref) ((read_from DBGWVR_EL1_ref) s)) else + if reg_name = (''DLR'') then Some ((regval_of DLR_ref) ((read_from DLR_ref) s)) else + if reg_name = (''DLR_EL0'') then Some ((regval_of DLR_EL0_ref) ((read_from DLR_EL0_ref) s)) else + if reg_name = (''DSPSR'') then Some ((regval_of DSPSR_ref) ((read_from DSPSR_ref) s)) else + if reg_name = (''DSPSR_EL0'') then Some ((regval_of DSPSR_EL0_ref) ((read_from DSPSR_EL0_ref) s)) else + if reg_name = (''EDSCR'') then Some ((regval_of EDSCR_ref) ((read_from EDSCR_ref) s)) else + if reg_name = (''ELR_EL1'') then Some ((regval_of ELR_EL1_ref) ((read_from ELR_EL1_ref) s)) else + if reg_name = (''ELR_EL2'') then Some ((regval_of ELR_EL2_ref) ((read_from ELR_EL2_ref) s)) else + if reg_name = (''ELR_EL3'') then Some ((regval_of ELR_EL3_ref) ((read_from ELR_EL3_ref) s)) else + if reg_name = (''ELR_hyp'') then Some ((regval_of ELR_hyp_ref) ((read_from ELR_hyp_ref) s)) else + if reg_name = (''ESR_EL1'') then Some ((regval_of ESR_EL1_ref) ((read_from ESR_EL1_ref) s)) else + if reg_name = (''ESR_EL2'') then Some ((regval_of ESR_EL2_ref) ((read_from ESR_EL2_ref) s)) else + if reg_name = (''ESR_EL3'') then Some ((regval_of ESR_EL3_ref) ((read_from ESR_EL3_ref) s)) else + if reg_name = (''EventRegister'') then Some ((regval_of EventRegister_ref) ((read_from EventRegister_ref) s)) else + if reg_name = (''FAR_EL1'') then Some ((regval_of FAR_EL1_ref) ((read_from FAR_EL1_ref) s)) else + if reg_name = (''FAR_EL2'') then Some ((regval_of FAR_EL2_ref) ((read_from FAR_EL2_ref) s)) else + if reg_name = (''FAR_EL3'') then Some ((regval_of FAR_EL3_ref) ((read_from FAR_EL3_ref) s)) else + if reg_name = (''FPCR'') then Some ((regval_of FPCR_ref) ((read_from FPCR_ref) s)) else + if reg_name = (''FPEXC'') then Some ((regval_of FPEXC_ref) ((read_from FPEXC_ref) s)) else + if reg_name = (''FPSCR'') then Some ((regval_of FPSCR_ref) ((read_from FPSCR_ref) s)) else + if reg_name = (''FPSR'') then Some ((regval_of FPSR_ref) ((read_from FPSR_ref) s)) else + if reg_name = (''HCR'') then Some ((regval_of HCR_ref) ((read_from HCR_ref) s)) else + if reg_name = (''HCR2'') then Some ((regval_of HCR2_ref) ((read_from HCR2_ref) s)) else + if reg_name = (''HCR_EL2'') then Some ((regval_of HCR_EL2_ref) ((read_from HCR_EL2_ref) s)) else + if reg_name = (''HDCR'') then Some ((regval_of HDCR_ref) ((read_from HDCR_ref) s)) else + if reg_name = (''HDFAR'') then Some ((regval_of HDFAR_ref) ((read_from HDFAR_ref) s)) else + if reg_name = (''HIFAR'') then Some ((regval_of HIFAR_ref) ((read_from HIFAR_ref) s)) else + if reg_name = (''HPFAR'') then Some ((regval_of HPFAR_ref) ((read_from HPFAR_ref) s)) else + if reg_name = (''HPFAR_EL2'') then Some ((regval_of HPFAR_EL2_ref) ((read_from HPFAR_EL2_ref) s)) else + if reg_name = (''HSCTLR'') then Some ((regval_of HSCTLR_ref) ((read_from HSCTLR_ref) s)) else + if reg_name = (''HSR'') then Some ((regval_of HSR_ref) ((read_from HSR_ref) s)) else + if reg_name = (''HVBAR'') then Some ((regval_of HVBAR_ref) ((read_from HVBAR_ref) s)) else + if reg_name = (''ID_AA64DFR0_EL1'') then Some ((regval_of ID_AA64DFR0_EL1_ref) ((read_from ID_AA64DFR0_EL1_ref) s)) else + if reg_name = (''LR_mon'') then Some ((regval_of LR_mon_ref) ((read_from LR_mon_ref) s)) else + if reg_name = (''MAIR_EL1'') then Some ((regval_of MAIR_EL1_ref) ((read_from MAIR_EL1_ref) s)) else + if reg_name = (''MAIR_EL2'') then Some ((regval_of MAIR_EL2_ref) ((read_from MAIR_EL2_ref) s)) else + if reg_name = (''MAIR_EL3'') then Some ((regval_of MAIR_EL3_ref) ((read_from MAIR_EL3_ref) s)) else + if reg_name = (''MDCR_EL2'') then Some ((regval_of MDCR_EL2_ref) ((read_from MDCR_EL2_ref) s)) else + if reg_name = (''MDCR_EL3'') then Some ((regval_of MDCR_EL3_ref) ((read_from MDCR_EL3_ref) s)) else + if reg_name = (''MDSCR_EL1'') then Some ((regval_of MDSCR_EL1_ref) ((read_from MDSCR_EL1_ref) s)) else + if reg_name = (''OSDLR_EL1'') then Some ((regval_of OSDLR_EL1_ref) ((read_from OSDLR_EL1_ref) s)) else + if reg_name = (''OSLSR_EL1'') then Some ((regval_of OSLSR_EL1_ref) ((read_from OSLSR_EL1_ref) s)) else + if reg_name = (''PSTATE'') then Some ((regval_of PSTATE_ref) ((read_from PSTATE_ref) s)) else + if reg_name = (''RC'') then Some ((regval_of RC_ref) ((read_from RC_ref) s)) else + if reg_name = (''RVBAR_EL1'') then Some ((regval_of RVBAR_EL1_ref) ((read_from RVBAR_EL1_ref) s)) else + if reg_name = (''RVBAR_EL2'') then Some ((regval_of RVBAR_EL2_ref) ((read_from RVBAR_EL2_ref) s)) else + if reg_name = (''RVBAR_EL3'') then Some ((regval_of RVBAR_EL3_ref) ((read_from RVBAR_EL3_ref) s)) else + if reg_name = (''SCR'') then Some ((regval_of SCR_ref) ((read_from SCR_ref) s)) else + if reg_name = (''SCR_EL3'') then Some ((regval_of SCR_EL3_ref) ((read_from SCR_EL3_ref) s)) else + if reg_name = (''SCTLR'') then Some ((regval_of SCTLR_ref) ((read_from SCTLR_ref) s)) else + if reg_name = (''SCTLR_EL1'') then Some ((regval_of SCTLR_EL1_ref) ((read_from SCTLR_EL1_ref) s)) else + if reg_name = (''SCTLR_EL2'') then Some ((regval_of SCTLR_EL2_ref) ((read_from SCTLR_EL2_ref) s)) else + if reg_name = (''SCTLR_EL3'') then Some ((regval_of SCTLR_EL3_ref) ((read_from SCTLR_EL3_ref) s)) else + if reg_name = (''SDCR'') then Some ((regval_of SDCR_ref) ((read_from SDCR_ref) s)) else + if reg_name = (''SDER'') then Some ((regval_of SDER_ref) ((read_from SDER_ref) s)) else + if reg_name = (''SPIDEN'') then Some ((regval_of SPIDEN_ref) ((read_from SPIDEN_ref) s)) else + if reg_name = (''SPSR_EL1'') then Some ((regval_of SPSR_EL1_ref) ((read_from SPSR_EL1_ref) s)) else + if reg_name = (''SPSR_EL2'') then Some ((regval_of SPSR_EL2_ref) ((read_from SPSR_EL2_ref) s)) else + if reg_name = (''SPSR_EL3'') then Some ((regval_of SPSR_EL3_ref) ((read_from SPSR_EL3_ref) s)) else + if reg_name = (''SPSR_abt'') then Some ((regval_of SPSR_abt_ref) ((read_from SPSR_abt_ref) s)) else + if reg_name = (''SPSR_fiq'') then Some ((regval_of SPSR_fiq_ref) ((read_from SPSR_fiq_ref) s)) else + if reg_name = (''SPSR_hyp'') then Some ((regval_of SPSR_hyp_ref) ((read_from SPSR_hyp_ref) s)) else + if reg_name = (''SPSR_irq'') then Some ((regval_of SPSR_irq_ref) ((read_from SPSR_irq_ref) s)) else + if reg_name = (''SPSR_mon'') then Some ((regval_of SPSR_mon_ref) ((read_from SPSR_mon_ref) s)) else + if reg_name = (''SPSR_svc'') then Some ((regval_of SPSR_svc_ref) ((read_from SPSR_svc_ref) s)) else + if reg_name = (''SPSR_und'') then Some ((regval_of SPSR_und_ref) ((read_from SPSR_und_ref) s)) else + if reg_name = (''SP_EL0'') then Some ((regval_of SP_EL0_ref) ((read_from SP_EL0_ref) s)) else + if reg_name = (''SP_EL1'') then Some ((regval_of SP_EL1_ref) ((read_from SP_EL1_ref) s)) else + if reg_name = (''SP_EL2'') then Some ((regval_of SP_EL2_ref) ((read_from SP_EL2_ref) s)) else + if reg_name = (''SP_EL3'') then Some ((regval_of SP_EL3_ref) ((read_from SP_EL3_ref) s)) else + if reg_name = (''SP_mon'') then Some ((regval_of SP_mon_ref) ((read_from SP_mon_ref) s)) else + if reg_name = (''TCR_EL1'') then Some ((regval_of TCR_EL1_ref) ((read_from TCR_EL1_ref) s)) else + if reg_name = (''TCR_EL2'') then Some ((regval_of TCR_EL2_ref) ((read_from TCR_EL2_ref) s)) else + if reg_name = (''TCR_EL3'') then Some ((regval_of TCR_EL3_ref) ((read_from TCR_EL3_ref) s)) else + if reg_name = (''TTBCR'') then Some ((regval_of TTBCR_ref) ((read_from TTBCR_ref) s)) else + if reg_name = (''TTBR0_EL1'') then Some ((regval_of TTBR0_EL1_ref) ((read_from TTBR0_EL1_ref) s)) else + if reg_name = (''TTBR0_EL2'') then Some ((regval_of TTBR0_EL2_ref) ((read_from TTBR0_EL2_ref) s)) else + if reg_name = (''TTBR0_EL3'') then Some ((regval_of TTBR0_EL3_ref) ((read_from TTBR0_EL3_ref) s)) else + if reg_name = (''TTBR1_EL1'') then Some ((regval_of TTBR1_EL1_ref) ((read_from TTBR1_EL1_ref) s)) else + if reg_name = (''TTBR1_EL2'') then Some ((regval_of TTBR1_EL2_ref) ((read_from TTBR1_EL2_ref) s)) else + if reg_name = (''VBAR'') then Some ((regval_of VBAR_ref) ((read_from VBAR_ref) s)) else + if reg_name = (''VBAR_EL1'') then Some ((regval_of VBAR_EL1_ref) ((read_from VBAR_EL1_ref) s)) else + if reg_name = (''VBAR_EL2'') then Some ((regval_of VBAR_EL2_ref) ((read_from VBAR_EL2_ref) s)) else + if reg_name = (''VBAR_EL3'') then Some ((regval_of VBAR_EL3_ref) ((read_from VBAR_EL3_ref) s)) else + if reg_name = (''VDFSR'') then Some ((regval_of VDFSR_ref) ((read_from VDFSR_ref) s)) else + if reg_name = (''VSESR_EL2'') then Some ((regval_of VSESR_EL2_ref) ((read_from VSESR_EL2_ref) s)) else + if reg_name = (''VTCR_EL2'') then Some ((regval_of VTCR_EL2_ref) ((read_from VTCR_EL2_ref) s)) else + if reg_name = (''VTTBR_EL2'') then Some ((regval_of VTTBR_EL2_ref) ((read_from VTTBR_EL2_ref) s)) else + if reg_name = (''_PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + if reg_name = (''_R'') then Some ((regval_of R_ref) ((read_from R_ref) s)) else + if reg_name = (''_V'') then Some ((regval_of V_ref) ((read_from V_ref) s)) else + if reg_name = (''__BranchTaken'') then Some ((regval_of BranchTaken_ref) ((read_from BranchTaken_ref) s)) else + if reg_name = (''__ExclusiveLocal'') then Some ((regval_of ExclusiveLocal_ref) ((read_from ExclusiveLocal_ref) s)) else + if reg_name = (''__Memory'') then Some ((regval_of Memory_ref) ((read_from Memory_ref) s)) else + if reg_name = (''__PendingInterrupt'') then Some ((regval_of PendingInterrupt_ref) ((read_from PendingInterrupt_ref) s)) else + if reg_name = (''__PendingPhysicalSError'') then Some ((regval_of PendingPhysicalSError_ref) ((read_from PendingPhysicalSError_ref) s)) else + if reg_name = (''__Sleeping'') then Some ((regval_of Sleeping_ref) ((read_from Sleeping_ref) s)) else + if reg_name = (''__ThisInstr'') then Some ((regval_of ThisInstr_ref) ((read_from ThisInstr_ref) s)) else + if reg_name = (''__ThisInstrEnc'') then Some ((regval_of ThisInstrEnc_ref) ((read_from ThisInstrEnc_ref) s)) else + if reg_name = (''__currentCond'') then Some ((regval_of currentCond_ref) ((read_from currentCond_ref) s)) else + if reg_name = (''__unconditional'') then Some ((regval_of unconditional_ref) ((read_from unconditional_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \ register_value \ regstate \(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''APDAKeyHi_EL1'') then map_option (\ v . (write_to APDAKeyHi_EL1_ref) v s) ((of_regval APDAKeyHi_EL1_ref) v) else + if reg_name = (''APDAKeyLo_EL1'') then map_option (\ v . (write_to APDAKeyLo_EL1_ref) v s) ((of_regval APDAKeyLo_EL1_ref) v) else + if reg_name = (''APDBKeyHi_EL1'') then map_option (\ v . (write_to APDBKeyHi_EL1_ref) v s) ((of_regval APDBKeyHi_EL1_ref) v) else + if reg_name = (''APDBKeyLo_EL1'') then map_option (\ v . (write_to APDBKeyLo_EL1_ref) v s) ((of_regval APDBKeyLo_EL1_ref) v) else + if reg_name = (''APGAKeyHi_EL1'') then map_option (\ v . (write_to APGAKeyHi_EL1_ref) v s) ((of_regval APGAKeyHi_EL1_ref) v) else + if reg_name = (''APGAKeyLo_EL1'') then map_option (\ v . (write_to APGAKeyLo_EL1_ref) v s) ((of_regval APGAKeyLo_EL1_ref) v) else + if reg_name = (''APIAKeyHi_EL1'') then map_option (\ v . (write_to APIAKeyHi_EL1_ref) v s) ((of_regval APIAKeyHi_EL1_ref) v) else + if reg_name = (''APIAKeyLo_EL1'') then map_option (\ v . (write_to APIAKeyLo_EL1_ref) v s) ((of_regval APIAKeyLo_EL1_ref) v) else + if reg_name = (''APIBKeyHi_EL1'') then map_option (\ v . (write_to APIBKeyHi_EL1_ref) v s) ((of_regval APIBKeyHi_EL1_ref) v) else + if reg_name = (''APIBKeyLo_EL1'') then map_option (\ v . (write_to APIBKeyLo_EL1_ref) v s) ((of_regval APIBKeyLo_EL1_ref) v) else + if reg_name = (''CONTEXTIDR_EL1'') then map_option (\ v . (write_to CONTEXTIDR_EL1_ref) v s) ((of_regval CONTEXTIDR_EL1_ref) v) else + if reg_name = (''CONTEXTIDR_EL2'') then map_option (\ v . (write_to CONTEXTIDR_EL2_ref) v s) ((of_regval CONTEXTIDR_EL2_ref) v) else + if reg_name = (''CPACR_EL1'') then map_option (\ v . (write_to CPACR_EL1_ref) v s) ((of_regval CPACR_EL1_ref) v) else + if reg_name = (''CPTR_EL2'') then map_option (\ v . (write_to CPTR_EL2_ref) v s) ((of_regval CPTR_EL2_ref) v) else + if reg_name = (''CPTR_EL3'') then map_option (\ v . (write_to CPTR_EL3_ref) v s) ((of_regval CPTR_EL3_ref) v) else + if reg_name = (''DBGBCR_EL1'') then map_option (\ v . (write_to DBGBCR_EL1_ref) v s) ((of_regval DBGBCR_EL1_ref) v) else + if reg_name = (''DBGBVR_EL1'') then map_option (\ v . (write_to DBGBVR_EL1_ref) v s) ((of_regval DBGBVR_EL1_ref) v) else + if reg_name = (''DBGEN'') then map_option (\ v . (write_to DBGEN_ref) v s) ((of_regval DBGEN_ref) v) else + if reg_name = (''DBGOSDLR'') then map_option (\ v . (write_to DBGOSDLR_ref) v s) ((of_regval DBGOSDLR_ref) v) else + if reg_name = (''DBGOSLSR'') then map_option (\ v . (write_to DBGOSLSR_ref) v s) ((of_regval DBGOSLSR_ref) v) else + if reg_name = (''DBGPRCR'') then map_option (\ v . (write_to DBGPRCR_ref) v s) ((of_regval DBGPRCR_ref) v) else + if reg_name = (''DBGPRCR_EL1'') then map_option (\ v . (write_to DBGPRCR_EL1_ref) v s) ((of_regval DBGPRCR_EL1_ref) v) else + if reg_name = (''DBGWCR_EL1'') then map_option (\ v . (write_to DBGWCR_EL1_ref) v s) ((of_regval DBGWCR_EL1_ref) v) else + if reg_name = (''DBGWVR_EL1'') then map_option (\ v . (write_to DBGWVR_EL1_ref) v s) ((of_regval DBGWVR_EL1_ref) v) else + if reg_name = (''DLR'') then map_option (\ v . (write_to DLR_ref) v s) ((of_regval DLR_ref) v) else + if reg_name = (''DLR_EL0'') then map_option (\ v . (write_to DLR_EL0_ref) v s) ((of_regval DLR_EL0_ref) v) else + if reg_name = (''DSPSR'') then map_option (\ v . (write_to DSPSR_ref) v s) ((of_regval DSPSR_ref) v) else + if reg_name = (''DSPSR_EL0'') then map_option (\ v . (write_to DSPSR_EL0_ref) v s) ((of_regval DSPSR_EL0_ref) v) else + if reg_name = (''EDSCR'') then map_option (\ v . (write_to EDSCR_ref) v s) ((of_regval EDSCR_ref) v) else + if reg_name = (''ELR_EL1'') then map_option (\ v . (write_to ELR_EL1_ref) v s) ((of_regval ELR_EL1_ref) v) else + if reg_name = (''ELR_EL2'') then map_option (\ v . (write_to ELR_EL2_ref) v s) ((of_regval ELR_EL2_ref) v) else + if reg_name = (''ELR_EL3'') then map_option (\ v . (write_to ELR_EL3_ref) v s) ((of_regval ELR_EL3_ref) v) else + if reg_name = (''ELR_hyp'') then map_option (\ v . (write_to ELR_hyp_ref) v s) ((of_regval ELR_hyp_ref) v) else + if reg_name = (''ESR_EL1'') then map_option (\ v . (write_to ESR_EL1_ref) v s) ((of_regval ESR_EL1_ref) v) else + if reg_name = (''ESR_EL2'') then map_option (\ v . (write_to ESR_EL2_ref) v s) ((of_regval ESR_EL2_ref) v) else + if reg_name = (''ESR_EL3'') then map_option (\ v . (write_to ESR_EL3_ref) v s) ((of_regval ESR_EL3_ref) v) else + if reg_name = (''EventRegister'') then map_option (\ v . (write_to EventRegister_ref) v s) ((of_regval EventRegister_ref) v) else + if reg_name = (''FAR_EL1'') then map_option (\ v . (write_to FAR_EL1_ref) v s) ((of_regval FAR_EL1_ref) v) else + if reg_name = (''FAR_EL2'') then map_option (\ v . (write_to FAR_EL2_ref) v s) ((of_regval FAR_EL2_ref) v) else + if reg_name = (''FAR_EL3'') then map_option (\ v . (write_to FAR_EL3_ref) v s) ((of_regval FAR_EL3_ref) v) else + if reg_name = (''FPCR'') then map_option (\ v . (write_to FPCR_ref) v s) ((of_regval FPCR_ref) v) else + if reg_name = (''FPEXC'') then map_option (\ v . (write_to FPEXC_ref) v s) ((of_regval FPEXC_ref) v) else + if reg_name = (''FPSCR'') then map_option (\ v . (write_to FPSCR_ref) v s) ((of_regval FPSCR_ref) v) else + if reg_name = (''FPSR'') then map_option (\ v . (write_to FPSR_ref) v s) ((of_regval FPSR_ref) v) else + if reg_name = (''HCR'') then map_option (\ v . (write_to HCR_ref) v s) ((of_regval HCR_ref) v) else + if reg_name = (''HCR2'') then map_option (\ v . (write_to HCR2_ref) v s) ((of_regval HCR2_ref) v) else + if reg_name = (''HCR_EL2'') then map_option (\ v . (write_to HCR_EL2_ref) v s) ((of_regval HCR_EL2_ref) v) else + if reg_name = (''HDCR'') then map_option (\ v . (write_to HDCR_ref) v s) ((of_regval HDCR_ref) v) else + if reg_name = (''HDFAR'') then map_option (\ v . (write_to HDFAR_ref) v s) ((of_regval HDFAR_ref) v) else + if reg_name = (''HIFAR'') then map_option (\ v . (write_to HIFAR_ref) v s) ((of_regval HIFAR_ref) v) else + if reg_name = (''HPFAR'') then map_option (\ v . (write_to HPFAR_ref) v s) ((of_regval HPFAR_ref) v) else + if reg_name = (''HPFAR_EL2'') then map_option (\ v . (write_to HPFAR_EL2_ref) v s) ((of_regval HPFAR_EL2_ref) v) else + if reg_name = (''HSCTLR'') then map_option (\ v . (write_to HSCTLR_ref) v s) ((of_regval HSCTLR_ref) v) else + if reg_name = (''HSR'') then map_option (\ v . (write_to HSR_ref) v s) ((of_regval HSR_ref) v) else + if reg_name = (''HVBAR'') then map_option (\ v . (write_to HVBAR_ref) v s) ((of_regval HVBAR_ref) v) else + if reg_name = (''ID_AA64DFR0_EL1'') then map_option (\ v . (write_to ID_AA64DFR0_EL1_ref) v s) ((of_regval ID_AA64DFR0_EL1_ref) v) else + if reg_name = (''LR_mon'') then map_option (\ v . (write_to LR_mon_ref) v s) ((of_regval LR_mon_ref) v) else + if reg_name = (''MAIR_EL1'') then map_option (\ v . (write_to MAIR_EL1_ref) v s) ((of_regval MAIR_EL1_ref) v) else + if reg_name = (''MAIR_EL2'') then map_option (\ v . (write_to MAIR_EL2_ref) v s) ((of_regval MAIR_EL2_ref) v) else + if reg_name = (''MAIR_EL3'') then map_option (\ v . (write_to MAIR_EL3_ref) v s) ((of_regval MAIR_EL3_ref) v) else + if reg_name = (''MDCR_EL2'') then map_option (\ v . (write_to MDCR_EL2_ref) v s) ((of_regval MDCR_EL2_ref) v) else + if reg_name = (''MDCR_EL3'') then map_option (\ v . (write_to MDCR_EL3_ref) v s) ((of_regval MDCR_EL3_ref) v) else + if reg_name = (''MDSCR_EL1'') then map_option (\ v . (write_to MDSCR_EL1_ref) v s) ((of_regval MDSCR_EL1_ref) v) else + if reg_name = (''OSDLR_EL1'') then map_option (\ v . (write_to OSDLR_EL1_ref) v s) ((of_regval OSDLR_EL1_ref) v) else + if reg_name = (''OSLSR_EL1'') then map_option (\ v . (write_to OSLSR_EL1_ref) v s) ((of_regval OSLSR_EL1_ref) v) else + if reg_name = (''PSTATE'') then map_option (\ v . (write_to PSTATE_ref) v s) ((of_regval PSTATE_ref) v) else + if reg_name = (''RC'') then map_option (\ v . (write_to RC_ref) v s) ((of_regval RC_ref) v) else + if reg_name = (''RVBAR_EL1'') then map_option (\ v . (write_to RVBAR_EL1_ref) v s) ((of_regval RVBAR_EL1_ref) v) else + if reg_name = (''RVBAR_EL2'') then map_option (\ v . (write_to RVBAR_EL2_ref) v s) ((of_regval RVBAR_EL2_ref) v) else + if reg_name = (''RVBAR_EL3'') then map_option (\ v . (write_to RVBAR_EL3_ref) v s) ((of_regval RVBAR_EL3_ref) v) else + if reg_name = (''SCR'') then map_option (\ v . (write_to SCR_ref) v s) ((of_regval SCR_ref) v) else + if reg_name = (''SCR_EL3'') then map_option (\ v . (write_to SCR_EL3_ref) v s) ((of_regval SCR_EL3_ref) v) else + if reg_name = (''SCTLR'') then map_option (\ v . (write_to SCTLR_ref) v s) ((of_regval SCTLR_ref) v) else + if reg_name = (''SCTLR_EL1'') then map_option (\ v . (write_to SCTLR_EL1_ref) v s) ((of_regval SCTLR_EL1_ref) v) else + if reg_name = (''SCTLR_EL2'') then map_option (\ v . (write_to SCTLR_EL2_ref) v s) ((of_regval SCTLR_EL2_ref) v) else + if reg_name = (''SCTLR_EL3'') then map_option (\ v . (write_to SCTLR_EL3_ref) v s) ((of_regval SCTLR_EL3_ref) v) else + if reg_name = (''SDCR'') then map_option (\ v . (write_to SDCR_ref) v s) ((of_regval SDCR_ref) v) else + if reg_name = (''SDER'') then map_option (\ v . (write_to SDER_ref) v s) ((of_regval SDER_ref) v) else + if reg_name = (''SPIDEN'') then map_option (\ v . (write_to SPIDEN_ref) v s) ((of_regval SPIDEN_ref) v) else + if reg_name = (''SPSR_EL1'') then map_option (\ v . (write_to SPSR_EL1_ref) v s) ((of_regval SPSR_EL1_ref) v) else + if reg_name = (''SPSR_EL2'') then map_option (\ v . (write_to SPSR_EL2_ref) v s) ((of_regval SPSR_EL2_ref) v) else + if reg_name = (''SPSR_EL3'') then map_option (\ v . (write_to SPSR_EL3_ref) v s) ((of_regval SPSR_EL3_ref) v) else + if reg_name = (''SPSR_abt'') then map_option (\ v . (write_to SPSR_abt_ref) v s) ((of_regval SPSR_abt_ref) v) else + if reg_name = (''SPSR_fiq'') then map_option (\ v . (write_to SPSR_fiq_ref) v s) ((of_regval SPSR_fiq_ref) v) else + if reg_name = (''SPSR_hyp'') then map_option (\ v . (write_to SPSR_hyp_ref) v s) ((of_regval SPSR_hyp_ref) v) else + if reg_name = (''SPSR_irq'') then map_option (\ v . (write_to SPSR_irq_ref) v s) ((of_regval SPSR_irq_ref) v) else + if reg_name = (''SPSR_mon'') then map_option (\ v . (write_to SPSR_mon_ref) v s) ((of_regval SPSR_mon_ref) v) else + if reg_name = (''SPSR_svc'') then map_option (\ v . (write_to SPSR_svc_ref) v s) ((of_regval SPSR_svc_ref) v) else + if reg_name = (''SPSR_und'') then map_option (\ v . (write_to SPSR_und_ref) v s) ((of_regval SPSR_und_ref) v) else + if reg_name = (''SP_EL0'') then map_option (\ v . (write_to SP_EL0_ref) v s) ((of_regval SP_EL0_ref) v) else + if reg_name = (''SP_EL1'') then map_option (\ v . (write_to SP_EL1_ref) v s) ((of_regval SP_EL1_ref) v) else + if reg_name = (''SP_EL2'') then map_option (\ v . (write_to SP_EL2_ref) v s) ((of_regval SP_EL2_ref) v) else + if reg_name = (''SP_EL3'') then map_option (\ v . (write_to SP_EL3_ref) v s) ((of_regval SP_EL3_ref) v) else + if reg_name = (''SP_mon'') then map_option (\ v . (write_to SP_mon_ref) v s) ((of_regval SP_mon_ref) v) else + if reg_name = (''TCR_EL1'') then map_option (\ v . (write_to TCR_EL1_ref) v s) ((of_regval TCR_EL1_ref) v) else + if reg_name = (''TCR_EL2'') then map_option (\ v . (write_to TCR_EL2_ref) v s) ((of_regval TCR_EL2_ref) v) else + if reg_name = (''TCR_EL3'') then map_option (\ v . (write_to TCR_EL3_ref) v s) ((of_regval TCR_EL3_ref) v) else + if reg_name = (''TTBCR'') then map_option (\ v . (write_to TTBCR_ref) v s) ((of_regval TTBCR_ref) v) else + if reg_name = (''TTBR0_EL1'') then map_option (\ v . (write_to TTBR0_EL1_ref) v s) ((of_regval TTBR0_EL1_ref) v) else + if reg_name = (''TTBR0_EL2'') then map_option (\ v . (write_to TTBR0_EL2_ref) v s) ((of_regval TTBR0_EL2_ref) v) else + if reg_name = (''TTBR0_EL3'') then map_option (\ v . (write_to TTBR0_EL3_ref) v s) ((of_regval TTBR0_EL3_ref) v) else + if reg_name = (''TTBR1_EL1'') then map_option (\ v . (write_to TTBR1_EL1_ref) v s) ((of_regval TTBR1_EL1_ref) v) else + if reg_name = (''TTBR1_EL2'') then map_option (\ v . (write_to TTBR1_EL2_ref) v s) ((of_regval TTBR1_EL2_ref) v) else + if reg_name = (''VBAR'') then map_option (\ v . (write_to VBAR_ref) v s) ((of_regval VBAR_ref) v) else + if reg_name = (''VBAR_EL1'') then map_option (\ v . (write_to VBAR_EL1_ref) v s) ((of_regval VBAR_EL1_ref) v) else + if reg_name = (''VBAR_EL2'') then map_option (\ v . (write_to VBAR_EL2_ref) v s) ((of_regval VBAR_EL2_ref) v) else + if reg_name = (''VBAR_EL3'') then map_option (\ v . (write_to VBAR_EL3_ref) v s) ((of_regval VBAR_EL3_ref) v) else + if reg_name = (''VDFSR'') then map_option (\ v . (write_to VDFSR_ref) v s) ((of_regval VDFSR_ref) v) else + if reg_name = (''VSESR_EL2'') then map_option (\ v . (write_to VSESR_EL2_ref) v s) ((of_regval VSESR_EL2_ref) v) else + if reg_name = (''VTCR_EL2'') then map_option (\ v . (write_to VTCR_EL2_ref) v s) ((of_regval VTCR_EL2_ref) v) else + if reg_name = (''VTTBR_EL2'') then map_option (\ v . (write_to VTTBR_EL2_ref) v s) ((of_regval VTTBR_EL2_ref) v) else + if reg_name = (''_PC'') then map_option (\ v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + if reg_name = (''_R'') then map_option (\ v . (write_to R_ref) v s) ((of_regval R_ref) v) else + if reg_name = (''_V'') then map_option (\ v . (write_to V_ref) v s) ((of_regval V_ref) v) else + if reg_name = (''__BranchTaken'') then map_option (\ v . (write_to BranchTaken_ref) v s) ((of_regval BranchTaken_ref) v) else + if reg_name = (''__ExclusiveLocal'') then map_option (\ v . (write_to ExclusiveLocal_ref) v s) ((of_regval ExclusiveLocal_ref) v) else + if reg_name = (''__Memory'') then map_option (\ v . (write_to Memory_ref) v s) ((of_regval Memory_ref) v) else + if reg_name = (''__PendingInterrupt'') then map_option (\ v . (write_to PendingInterrupt_ref) v s) ((of_regval PendingInterrupt_ref) v) else + if reg_name = (''__PendingPhysicalSError'') then map_option (\ v . (write_to PendingPhysicalSError_ref) v s) ((of_regval PendingPhysicalSError_ref) v) else + if reg_name = (''__Sleeping'') then map_option (\ v . (write_to Sleeping_ref) v s) ((of_regval Sleeping_ref) v) else + if reg_name = (''__ThisInstr'') then map_option (\ v . (write_to ThisInstr_ref) v s) ((of_regval ThisInstr_ref) v) else + if reg_name = (''__ThisInstrEnc'') then map_option (\ v . (write_to ThisInstrEnc_ref) v s) ((of_regval ThisInstrEnc_ref) v) else + if reg_name = (''__currentCond'') then map_option (\ v . (write_to currentCond_ref) v s) ((of_regval currentCond_ref) v) else + if reg_name = (''__unconditional'') then map_option (\ v . (write_to unconditional_ref) v s) ((of_regval unconditional_ref) v) else + None )" + + +definition register_accessors :: "(string \ regstate \(register_value)option)*(string \ register_value \ regstate \(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end -- cgit v1.2.3 From 7bda99ec25b8866ebd56487f49bce66a37c69a8d Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Fri, 11 May 2018 19:02:51 +0100 Subject: Add links in Isabelle snapshot README --- snapshots/isabelle/README.md | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/snapshots/isabelle/README.md b/snapshots/isabelle/README.md index b1d9db23..975b7dee 100644 --- a/snapshots/isabelle/README.md +++ b/snapshots/isabelle/README.md @@ -1,15 +1,16 @@ # Isabelle Snapshots of Sail Specifications This directory contains snapshots of the Isabelle theories generated by Sail -for the CHERI-MIPS, RISC-V, and ARM v8.3 specifications, together with -snapshots of the Sail and Lem libraries. These snapshots are provided for -convenience, and are not guaranteed to be up-to-date. +for the [CHERI-MIPS](cheri/), [RISC-V](riscv/), and [ARM v8.3](aarch64/) +specifications, together with snapshots of the Sail and Lem libraries. These +snapshots are provided for convenience, and are not guaranteed to be +up-to-date. In order to open a theory of one of the specifications in Isabelle, use the `-l Sail` command-line flag to load the session containing the Sail library. -Snapshots of the Sail and Lem libraries are in the `lib/sail` and `lib/lem` -directories, respectively. You can tell Isabelle where to find them using the -`-d` flag, as in +Snapshots of the Sail and Lem libraries are in the [lib/sail](lib/sail/) and +[lib/lem](lib/lem/) directories, respectively. You can tell Isabelle where to +find them using the `-d` flag, as in ``` isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy @@ -17,7 +18,8 @@ isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy This will open the RISC-V specification. -The file `Manual.thy` (and its PDF rendering in `Manual.pdf`) contains an +The file [Manual.thy](Manual.thy) (and its PDF rendering in +[Manual.pdf](Manual.pdf)) contains an introduction on how to use the Sail specifications in Isabelle. The Lem library files in `lib/lem` have been generated from the -- cgit v1.2.3 From 6368f7fea326340ffd1c2b6e3ff3bcdccdeb9cec Mon Sep 17 00:00:00 2001 From: Peter Sewell Date: Sat, 12 May 2018 08:54:12 +0100 Subject: add -A --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 9de94d32..5144d13c 100644 --- a/README.md +++ b/README.md @@ -23,7 +23,7 @@ some Sail specifications and related tools. * A Sail specification of the CHERI MIPS ISA (in [cheri/](cheri/)) -* A Sail specification of ARMv8.3 generated from ARM's publically +* A Sail specification of ARMv8.3-A generated from ARM's publically released ASL specification (in [aarch64/](aarch64/)) * Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle](snapshots/isabelle) @@ -36,16 +36,10 @@ some Sail specifications and related tools. * A test suite for Sail (in [test/](test/)) We also have versions of IBM POWER, a fragment of x86, and a -hand-written fragment of ARM, but these are currently not up-to-date +hand-written fragment of ARMv8-A, but these are currently not up-to-date with the latest version of Sail, which is the (default) sail2 branch on Github. -Building -======== - -See [INSTALL.md](INSTALL.md) for full details of how to build Sail from source -with all the required dependencies. - OPAM Installation ================= @@ -53,6 +47,12 @@ See the following Sail [wiki page](https://github.com/rems-project/sail/wiki/OPAMInstall) for how to get pre-built binaries of Sail using OPAM. +Building +======== + +See [INSTALL.md](INSTALL.md) for full details of how to build Sail from source +with all the required dependencies. + Emacs Mode ========== -- cgit v1.2.3 From 526b71d5fed2f6a79c41fe482a578a8634a0345a Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Sat, 12 May 2018 11:16:27 +0100 Subject: Fix bug in handling of registers with option type Also add test cases and Isabelle lemmas --- src/state.ml | 15 ++++++++++++++- test/typecheck/pass/reg_list.sail | 7 +++++++ test/typecheck/pass/reg_option.sail | 16 ++++++++++++++++ 3 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 test/typecheck/pass/reg_list.sail create mode 100644 test/typecheck/pass/reg_option.sail diff --git a/src/state.ml b/src/state.ml index 5a360456..ab63747c 100644 --- a/src/state.ml +++ b/src/state.ml @@ -286,7 +286,7 @@ let register_refs_lem mwords registers = ""; "val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)"; "let option_of_regval of_regval = function"; - " | Regval_option v -> Maybe.map of_regval v"; + " | Regval_option v -> Just (Maybe.bind v of_regval)"; " | _ -> Nothing"; "end"; ""; @@ -388,6 +388,19 @@ let generate_isa_lemmas mwords (Defs defs : tannot defs) = "proof -"; " from assms have \"of_rv \\ rv_of = Some\" by auto"; " then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)"; + "qed"; + ""; + "lemma option_of_rv_rv_of_option[simp]:"; + " assumes \"\\v. of_rv (rv_of v) = Some v\""; + " shows \"option_of_regval of_rv (regval_of_option rv_of v) = Some v\""; + " using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def)"; + ""; + "lemma list_of_rv_rv_of_list[simp]:"; + " assumes \"\\v. of_rv (rv_of v) = Some v\""; + " shows \"list_of_regval of_rv (regval_of_list rv_of v) = Some v\""; + "proof -"; + " from assms have \"of_rv \\ rv_of = Some\" by auto"; + " with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)"; "qed"] ^^ hardline ^^ hardline ^^ separate_map (hardline ^^ hardline) register_lemmas registers diff --git a/test/typecheck/pass/reg_list.sail b/test/typecheck/pass/reg_list.sail new file mode 100644 index 00000000..bf776942 --- /dev/null +++ b/test/typecheck/pass/reg_list.sail @@ -0,0 +1,7 @@ +register X : list(bool) + +val init_X : unit -> unit effect {wreg} +function init_X () = { + X = [||]; +} + diff --git a/test/typecheck/pass/reg_option.sail b/test/typecheck/pass/reg_option.sail new file mode 100644 index 00000000..55317d1f --- /dev/null +++ b/test/typecheck/pass/reg_option.sail @@ -0,0 +1,16 @@ +$include +$include +$include + +register X : option(int) + +val inc_X : unit -> int effect {rreg, wreg} +function inc_X () = { + let x : int = match X { + Some(x) => x + 1, + None() => 0 + }; + X = Some(x); + return x; +} + -- cgit v1.2.3 From bd2d1c51ce4128394c6752de9781ddb397254689 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Sat, 12 May 2018 11:17:29 +0100 Subject: Update RISC-V snapshot --- snapshots/isabelle/riscv/Riscv_lemmas.thy | 13 +++++++++++++ snapshots/isabelle/riscv/Riscv_types.thy | 5 ++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/snapshots/isabelle/riscv/Riscv_lemmas.thy b/snapshots/isabelle/riscv/Riscv_lemmas.thy index b2f4e80d..108208ca 100644 --- a/snapshots/isabelle/riscv/Riscv_lemmas.thy +++ b/snapshots/isabelle/riscv/Riscv_lemmas.thy @@ -67,6 +67,19 @@ proof - then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) qed +lemma option_of_rv_rv_of_option[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v" + using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def) + +lemma list_of_rv_rv_of_list[simp]: + assumes "\v. of_rv (rv_of v) = Some v" + shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v" +proof - + from assms have "of_rv \ rv_of = Some" by auto + with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def) +qed + lemma liftS_read_reg_tlb39[simp]: "liftS (read_reg tlb39_ref) = readS (tlb39 \ regstate)" by (auto simp: liftState_read_reg_readS register_defs) diff --git a/snapshots/isabelle/riscv/Riscv_types.thy b/snapshots/isabelle/riscv/Riscv_types.thy index b4fc7f6c..71dce180 100644 --- a/snapshots/isabelle/riscv/Riscv_types.thy +++ b/snapshots/isabelle/riscv/Riscv_types.thy @@ -636,7 +636,10 @@ definition regval_of_list :: "('a \ register_value)\ 'a (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) definition option_of_regval :: "(register_value \ 'a option)\ register_value \('a option)option " where " option_of_regval of_regval1 = ( \x . - (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + (case x of + Regval_option v => Some (Option.bind v of_regval1) + | _ => None + ) )" (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) -- cgit v1.2.3 From 01ef8f770c22f4a0fd030746f4afddcb37733a54 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Sat, 12 May 2018 11:19:30 +0100 Subject: Add link to README.md --- snapshots/isabelle/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/snapshots/isabelle/README.md b/snapshots/isabelle/README.md index 975b7dee..cabf4fc0 100644 --- a/snapshots/isabelle/README.md +++ b/snapshots/isabelle/README.md @@ -19,9 +19,9 @@ isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy This will open the RISC-V specification. The file [Manual.thy](Manual.thy) (and its PDF rendering in -[Manual.pdf](Manual.pdf)) contains an -introduction on how to use the Sail specifications in Isabelle. +[Manual.pdf](Manual.pdf)) contains an introduction on how to use the Sail +specifications in Isabelle. The Lem library files in `lib/lem` have been generated from the [Lem](https://github.com/rems-project/lem) sources. The Lem license can be -found in `lib/lem/LICENSE`. +found in [lib/lem/LICENSE](lib/lem/LICENSE). -- cgit v1.2.3 From 809adfffc12021f2af195de78e9b6f138ed7956b Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Sat, 12 May 2018 12:26:29 +0100 Subject: Add ROOT files --- riscv/ROOT | 4 ++++ snapshots/isabelle/aarch64/ROOT | 4 ++++ snapshots/isabelle/cheri/ROOT | 4 ++++ snapshots/isabelle/riscv/ROOT | 4 ++++ 4 files changed, 16 insertions(+) create mode 100644 riscv/ROOT create mode 100644 snapshots/isabelle/aarch64/ROOT create mode 100644 snapshots/isabelle/cheri/ROOT create mode 100644 snapshots/isabelle/riscv/ROOT diff --git a/riscv/ROOT b/riscv/ROOT new file mode 100644 index 00000000..cfc7f5bd --- /dev/null +++ b/riscv/ROOT @@ -0,0 +1,4 @@ +session "Sail-RISC-V" = "Sail" + + options [document = false] + theories + Riscv_lemmas diff --git a/snapshots/isabelle/aarch64/ROOT b/snapshots/isabelle/aarch64/ROOT new file mode 100644 index 00000000..113e8e70 --- /dev/null +++ b/snapshots/isabelle/aarch64/ROOT @@ -0,0 +1,4 @@ +session "Sail-AArch64" = "Sail" + + options [document = false] + theories + Aarch64_lemmas diff --git a/snapshots/isabelle/cheri/ROOT b/snapshots/isabelle/cheri/ROOT new file mode 100644 index 00000000..244413d5 --- /dev/null +++ b/snapshots/isabelle/cheri/ROOT @@ -0,0 +1,4 @@ +session "Sail-CHERI" = "Sail" + + options [document = false] + theories + Cheri_lemmas diff --git a/snapshots/isabelle/riscv/ROOT b/snapshots/isabelle/riscv/ROOT new file mode 100644 index 00000000..cfc7f5bd --- /dev/null +++ b/snapshots/isabelle/riscv/ROOT @@ -0,0 +1,4 @@ +session "Sail-RISC-V" = "Sail" + + options [document = false] + theories + Riscv_lemmas -- cgit v1.2.3 From f80784d0aaba88c1f5bd078b1d7bbe60e05424b0 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Mon, 14 May 2018 13:29:15 +0100 Subject: Add missing HOL4 files (and disable overzealous cleaning) --- snapshots/hol4/sail/lib/hol/Holmakefile | 2 +- snapshots/hol4/sail/lib/hol/promptScript.sml | 15 + snapshots/hol4/sail/lib/hol/prompt_monadScript.sml | 24 + .../hol4/sail/lib/hol/sail_instr_kindsScript.sml | 473 ++++++++ .../hol4/sail/lib/hol/sail_operatorsScript.sml | 367 ++++++ .../sail/lib/hol/sail_operators_bitlistsScript.sml | 792 +++++++++++++ .../sail/lib/hol/sail_operators_mwordsScript.sml | 612 ++++++++++ snapshots/hol4/sail/lib/hol/sail_valuesScript.sml | 1238 ++++++++++++++++++++ snapshots/hol4/sail/lib/hol/stateScript.sml | 119 ++ snapshots/hol4/sail/lib/hol/state_monadScript.sml | 348 ++++++ 10 files changed, 3989 insertions(+), 1 deletion(-) create mode 100644 snapshots/hol4/sail/lib/hol/promptScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/prompt_monadScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/sail_valuesScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/stateScript.sml create mode 100644 snapshots/hol4/sail/lib/hol/state_monadScript.sml diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile index 45ed41ff..d7df9bcb 100644 --- a/snapshots/hol4/sail/lib/hol/Holmakefile +++ b/snapshots/hol4/sail/lib/hol/Holmakefile @@ -2,7 +2,7 @@ SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript. sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \ state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml -EXTRA_CLEANS = $(SCRIPTS) +#EXTRA_CLEANS = $(SCRIPTS) THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS)) diff --git a/snapshots/hol4/sail/lib/hol/promptScript.sml b/snapshots/hol4/sail/lib/hol/promptScript.sml new file mode 100644 index 00000000..95d6e752 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/promptScript.sml @@ -0,0 +1,15 @@ +(*Generated by Lem from prompt.lem.*) +open HolKernel Parse boolLib bossLib; +open prompt_monadTheory state_monadTheory stateTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "prompt" + +(*open import Prompt_monad*) +(*open import State_monad*) +(*open import State*) +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml b/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml new file mode 100644 index 00000000..627620ff --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml @@ -0,0 +1,24 @@ +(*Generated by Lem from prompt_monad.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory state_monadTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "prompt_monad" + +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import State_monad*) + +(* Fake interface of the prompt monad by redirecting to the state monad, since + the former is not currently supported by HOL4 *) + +val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) state_monad$monadS``); +val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) state_monad$monadRS``); +val _ = Define ` + ((barrier:'c -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) _= (returnS () ))`; +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml b/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml new file mode 100644 index 00000000..cfe0ac60 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml @@ -0,0 +1,473 @@ +(*Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail_instr_kinds" + +(*========================================================================*) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(*open import Pervasives_extra*) + + +val _ = Hol_datatype ` +(* 'a *) EnumerationType_class= <| + toNat_method : 'a -> num +|>`; + + + +(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> Basic_classes.ordering*) +val _ = Define ` + ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> lem_basic_classes$ordering)dict_Sail_instr_kinds_EnumerationType_a e1 e2= +(genericCompare (<) (=) ( + dict_Sail_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail_instr_kinds_EnumerationType_a.toNat_method e2)))`; + + + +val _ = Define ` +((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a lem_basic_classes$Ord_class)dict_Sail_instr_kinds_EnumerationType_a= (<| + + compare_method := + (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a); + + isLess_method := (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT); + + isLessEqual_method := (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> GT); + + isGreater_method := (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT); + + isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> LT)|>))`; + + + +(* Data structures for building up instructions *) + +(* careful: changes in the read/write/barrier kinds have to be + reflected in deep_shallow_convert *) +val _ = Hol_datatype ` + read_kind = + (* common reads *) + Read_plain + (* Power reads *) + | Read_reserve + (* AArch64 reads *) + | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream + (* RISC-V reads *) + | Read_RISCV_acquire | Read_RISCV_strong_acquire + | Read_RISCV_reserved | Read_RISCV_reserved_acquire + | Read_RISCV_reserved_strong_acquire + (* x86 reads *) + | Read_X86_locked`; + (* the read part of a lock'd instruction (rmw) *) + +val _ = Define ` +((instance_Show_Show_Sail_instr_kinds_read_kind_dict:(read_kind)lem_show$Show_class)= (<| + + show_method := (\x . + (case x of + Read_plain => "Read_plain" + | Read_reserve => "Read_reserve" + | Read_acquire => "Read_acquire" + | Read_exclusive => "Read_exclusive" + | Read_exclusive_acquire => "Read_exclusive_acquire" + | Read_stream => "Read_stream" + | Read_RISCV_acquire => "Read_RISCV_acquire" + | Read_RISCV_strong_acquire => "Read_RISCV_strong_acquire" + | Read_RISCV_reserved => "Read_RISCV_reserved" + | Read_RISCV_reserved_acquire => "Read_RISCV_reserved_acquire" + | Read_RISCV_reserved_strong_acquire => "Read_RISCV_reserved_strong_acquire" + | Read_X86_locked => "Read_X86_locked" + ))|>))`; + + +val _ = Hol_datatype ` + write_kind = + (* common writes *) + Write_plain + (* Power writes *) + | Write_conditional + (* AArch64 writes *) + | Write_release | Write_exclusive | Write_exclusive_release + (* RISC-V *) + | Write_RISCV_release | Write_RISCV_strong_release + | Write_RISCV_conditional | Write_RISCV_conditional_release + | Write_RISCV_conditional_strong_release + (* x86 writes *) + | Write_X86_locked`; + (* the write part of a lock'd instruction (rmw) *) + +val _ = Define ` +((instance_Show_Show_Sail_instr_kinds_write_kind_dict:(write_kind)lem_show$Show_class)= (<| + + show_method := (\x . + (case x of + Write_plain => "Write_plain" + | Write_conditional => "Write_conditional" + | Write_release => "Write_release" + | Write_exclusive => "Write_exclusive" + | Write_exclusive_release => "Write_exclusive_release" + | Write_RISCV_release => "Write_RISCV_release" + | Write_RISCV_strong_release => "Write_RISCV_strong_release" + | Write_RISCV_conditional => "Write_RISCV_conditional" + | Write_RISCV_conditional_release => "Write_RISCV_conditional_release" + | Write_RISCV_conditional_strong_release => "Write_RISCV_conditional_strong_release" + | Write_X86_locked => "Write_X86_locked" + ))|>))`; + + +val _ = Hol_datatype ` + barrier_kind = + (* Power barriers *) + Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync + (* AArch64 barriers *) + | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB + | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB + | Barrier_TM_COMMIT + (* MIPS barriers *) + | Barrier_MIPS_SYNC + (* RISC-V barriers *) + | Barrier_RISCV_rw_rw + | Barrier_RISCV_r_rw + | Barrier_RISCV_r_r + | Barrier_RISCV_rw_w + | Barrier_RISCV_w_w + | Barrier_RISCV_i + (* X86 *) + | Barrier_x86_MFENCE`; + + + +val _ = Define ` +((instance_Show_Show_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)lem_show$Show_class)= (<| + + show_method := (\x . + (case x of + Barrier_Sync => "Barrier_Sync" + | Barrier_LwSync => "Barrier_LwSync" + | Barrier_Eieio => "Barrier_Eieio" + | Barrier_Isync => "Barrier_Isync" + | Barrier_DMB => "Barrier_DMB" + | Barrier_DMB_ST => "Barrier_DMB_ST" + | Barrier_DMB_LD => "Barrier_DMB_LD" + | Barrier_DSB => "Barrier_DSB" + | Barrier_DSB_ST => "Barrier_DSB_ST" + | Barrier_DSB_LD => "Barrier_DSB_LD" + | Barrier_ISB => "Barrier_ISB" + | Barrier_TM_COMMIT => "Barrier_TM_COMMIT" + | Barrier_MIPS_SYNC => "Barrier_MIPS_SYNC" + | Barrier_RISCV_rw_rw => "Barrier_RISCV_rw_rw" + | Barrier_RISCV_r_rw => "Barrier_RISCV_r_rw" + | Barrier_RISCV_r_r => "Barrier_RISCV_r_r" + | Barrier_RISCV_rw_w => "Barrier_RISCV_rw_w" + | Barrier_RISCV_w_w => "Barrier_RISCV_w_w" + | Barrier_RISCV_i => "Barrier_RISCV_i" + | Barrier_x86_MFENCE => "Barrier_x86_MFENCE" + ))|>))`; + + +val _ = Hol_datatype ` + trans_kind = + (* AArch64 *) + Transaction_start | Transaction_commit | Transaction_abort`; + + +val _ = Define ` +((instance_Show_Show_Sail_instr_kinds_trans_kind_dict:(trans_kind)lem_show$Show_class)= (<| + + show_method := (\x . + (case x of + Transaction_start => "Transaction_start" + | Transaction_commit => "Transaction_commit" + | Transaction_abort => "Transaction_abort" + ))|>))`; + + +val _ = Hol_datatype ` + instruction_kind = + IK_barrier of barrier_kind + | IK_mem_read of read_kind + | IK_mem_write of write_kind + | IK_mem_rmw of (read_kind # write_kind) + | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + indirect/computed-branch (single nia of kind NIA_indirect_address) + and branch/jump (single nia of kind NIA_concrete_address) *) + | IK_trans of trans_kind + | IK_simple`; + + + +val _ = Define ` +((instance_Show_Show_Sail_instr_kinds_instruction_kind_dict:(instruction_kind)lem_show$Show_class)= (<| + + show_method := (\x . + (case x of + IK_barrier barrier_kind => STRCAT "IK_barrier " + (((\x . (case x of + Barrier_Sync => "Barrier_Sync" + | Barrier_LwSync => "Barrier_LwSync" + | Barrier_Eieio => "Barrier_Eieio" + | Barrier_Isync => "Barrier_Isync" + | Barrier_DMB => "Barrier_DMB" + | Barrier_DMB_ST => "Barrier_DMB_ST" + | Barrier_DMB_LD => "Barrier_DMB_LD" + | Barrier_DSB => "Barrier_DSB" + | Barrier_DSB_ST => "Barrier_DSB_ST" + | Barrier_DSB_LD => "Barrier_DSB_LD" + | Barrier_ISB => "Barrier_ISB" + | Barrier_TM_COMMIT => + "Barrier_TM_COMMIT" + | Barrier_MIPS_SYNC => + "Barrier_MIPS_SYNC" + | Barrier_RISCV_rw_rw => + "Barrier_RISCV_rw_rw" + | Barrier_RISCV_r_rw => + "Barrier_RISCV_r_rw" + | Barrier_RISCV_r_r => + "Barrier_RISCV_r_r" + | Barrier_RISCV_rw_w => + "Barrier_RISCV_rw_w" + | Barrier_RISCV_w_w => + "Barrier_RISCV_w_w" + | Barrier_RISCV_i => + "Barrier_RISCV_i" + | Barrier_x86_MFENCE => + "Barrier_x86_MFENCE" + )) barrier_kind)) + | IK_mem_read read_kind => STRCAT "IK_mem_read " + (((\x . (case x of + Read_plain => "Read_plain" + | Read_reserve => "Read_reserve" + | Read_acquire => "Read_acquire" + | Read_exclusive => "Read_exclusive" + | Read_exclusive_acquire => + "Read_exclusive_acquire" + | Read_stream => "Read_stream" + | Read_RISCV_acquire => "Read_RISCV_acquire" + | Read_RISCV_strong_acquire => + "Read_RISCV_strong_acquire" + | Read_RISCV_reserved => + "Read_RISCV_reserved" + | Read_RISCV_reserved_acquire => + "Read_RISCV_reserved_acquire" + | Read_RISCV_reserved_strong_acquire => + "Read_RISCV_reserved_strong_acquire" + | Read_X86_locked => "Read_X86_locked" + )) read_kind)) + | IK_mem_write write_kind => STRCAT "IK_mem_write " + (((\x . (case x of + Write_plain => "Write_plain" + | Write_conditional => + "Write_conditional" + | Write_release => "Write_release" + | Write_exclusive => "Write_exclusive" + | Write_exclusive_release => + "Write_exclusive_release" + | Write_RISCV_release => + "Write_RISCV_release" + | Write_RISCV_strong_release => + "Write_RISCV_strong_release" + | Write_RISCV_conditional => + "Write_RISCV_conditional" + | Write_RISCV_conditional_release => + "Write_RISCV_conditional_release" + | Write_RISCV_conditional_strong_release => + "Write_RISCV_conditional_strong_release" + | Write_X86_locked => "Write_X86_locked" + )) write_kind)) + | IK_mem_rmw (r, w) => STRCAT "IK_mem_rmw " + (STRCAT + (((\x . (case x of + Read_plain => "Read_plain" + | Read_reserve => "Read_reserve" + | Read_acquire => "Read_acquire" + | Read_exclusive => "Read_exclusive" + | Read_exclusive_acquire => + "Read_exclusive_acquire" + | Read_stream => "Read_stream" + | Read_RISCV_acquire => "Read_RISCV_acquire" + | Read_RISCV_strong_acquire => + "Read_RISCV_strong_acquire" + | Read_RISCV_reserved => "Read_RISCV_reserved" + | Read_RISCV_reserved_acquire => + "Read_RISCV_reserved_acquire" + | Read_RISCV_reserved_strong_acquire => + "Read_RISCV_reserved_strong_acquire" + | Read_X86_locked => "Read_X86_locked" + )) r)) + (STRCAT " " + (((\x . (case x of + Write_plain => "Write_plain" + | Write_conditional => + "Write_conditional" + | Write_release => "Write_release" + | Write_exclusive => "Write_exclusive" + | Write_exclusive_release => + "Write_exclusive_release" + | Write_RISCV_release => + "Write_RISCV_release" + | Write_RISCV_strong_release => + "Write_RISCV_strong_release" + | Write_RISCV_conditional => + "Write_RISCV_conditional" + | Write_RISCV_conditional_release => + "Write_RISCV_conditional_release" + | Write_RISCV_conditional_strong_release => + "Write_RISCV_conditional_strong_release" + | Write_X86_locked => "Write_X86_locked" + )) w)))) + | IK_branch => "IK_branch" + | IK_trans trans_kind => STRCAT "IK_trans " + (((\x . (case x of + Transaction_start => "Transaction_start" + | Transaction_commit => "Transaction_commit" + | Transaction_abort => "Transaction_abort" + )) trans_kind)) + | IK_simple => "IK_simple" + ))|>))`; + + + +val _ = Define ` + ((read_is_exclusive:read_kind -> bool)= + (\x . (case x of + Read_plain => F + | Read_reserve => T + | Read_acquire => F + | Read_exclusive => T + | Read_exclusive_acquire => T + | Read_stream => F + | Read_RISCV_acquire => F + | Read_RISCV_strong_acquire => F + | Read_RISCV_reserved => T + | Read_RISCV_reserved_acquire => T + | Read_RISCV_reserved_strong_acquire => T + | Read_X86_locked => T + )))`; + + + + +val _ = Define ` +((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<| + + toNat_method := (\x . + (case x of + Read_plain =>( 0 : num) + | Read_reserve =>( 1 : num) + | Read_acquire =>( 2 : num) + | Read_exclusive =>( 3 : num) + | Read_exclusive_acquire =>( 4 : num) + | Read_stream =>( 5 : num) + | Read_RISCV_acquire =>( 6 : num) + | Read_RISCV_strong_acquire =>( 7 : num) + | Read_RISCV_reserved =>( 8 : num) + | Read_RISCV_reserved_acquire =>( 9 : num) + | Read_RISCV_reserved_strong_acquire =>( 10 : num) + | Read_X86_locked =>( 11 : num) + ))|>))`; + + +val _ = Define ` +((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<| + + toNat_method := (\x . + (case x of + Write_plain =>( 0 : num) + | Write_conditional =>( 1 : num) + | Write_release =>( 2 : num) + | Write_exclusive =>( 3 : num) + | Write_exclusive_release =>( 4 : num) + | Write_RISCV_release =>( 5 : num) + | Write_RISCV_strong_release =>( 6 : num) + | Write_RISCV_conditional =>( 7 : num) + | Write_RISCV_conditional_release =>( 8 : num) + | Write_RISCV_conditional_strong_release =>( 9 : num) + | Write_X86_locked =>( 10 : num) + ))|>))`; + + +val _ = Define ` +((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<| + + toNat_method := (\x . + (case x of + Barrier_Sync =>( 0 : num) + | Barrier_LwSync =>( 1 : num) + | Barrier_Eieio =>( 2 : num) + | Barrier_Isync =>( 3 : num) + | Barrier_DMB =>( 4 : num) + | Barrier_DMB_ST =>( 5 : num) + | Barrier_DMB_LD =>( 6 : num) + | Barrier_DSB =>( 7 : num) + | Barrier_DSB_ST =>( 8 : num) + | Barrier_DSB_LD =>( 9 : num) + | Barrier_ISB =>( 10 : num) + | Barrier_TM_COMMIT =>( 11 : num) + | Barrier_MIPS_SYNC =>( 12 : num) + | Barrier_RISCV_rw_rw =>( 13 : num) + | Barrier_RISCV_r_rw =>( 14 : num) + | Barrier_RISCV_r_r =>( 15 : num) + | Barrier_RISCV_rw_w =>( 16 : num) + | Barrier_RISCV_w_w =>( 17 : num) + | Barrier_RISCV_i =>( 18 : num) + | Barrier_x86_MFENCE =>( 19 : num) + ))|>))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml new file mode 100644 index 00000000..f1f0c8d4 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml @@ -0,0 +1,367 @@ +(*Generated by Lem from ../../src/gen_lib/sail_operators.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail_operators" + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) + +(*** Bit vector operations *) + +(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list Sail_values.bitU*) +val _ = Define ` + ((concat_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> 'b ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r= ( + dict_Sail_values_Bitvector_a.bits_of_method l ++ dict_Sail_values_Bitvector_b.bits_of_method r))`; + + +(*val cons_bv : forall 'a. Bitvector 'a => Sail_values.bitU -> 'a -> list Sail_values.bitU*) +val _ = Define ` + ((cons_bv:'a sail_values$Bitvector_class -> sail_values$bitU -> 'a ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a b v= (b :: + dict_Sail_values_Bitvector_a.bits_of_method v))`; + + +(*val cast_unit_bv : Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((cast_unit_bv:sail_values$bitU ->(sail_values$bitU)list) b= ([b]))`; + + +(*val bv_of_bit : Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((bv_of_bit:int -> sail_values$bitU ->(sail_values$bitU)list) len b= (extz_bits len [b]))`; + + +val _ = Define ` + ((most_significant:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU)dict_Sail_values_Bitvector_a v= ((case + dict_Sail_values_Bitvector_a.bits_of_method v of + b :: _ => b + | _ => B0 (* Treat empty bitvector as all zeros *) + )))`; + + +val _ = Define ` + ((get_max_representable_in:bool -> int -> int) sign (n : int) : int= + (if (n =( 64 : int)) then (case sign of T => max_64 | F => max_64u ) + else if (n=( 32 : int)) then (case sign of T => max_32 | F => max_32u ) + else if (n=( 8 : int)) then max_8 + else if (n=( 5 : int)) then max_5 + else (case sign of T => (( 2 : int))** ((Num (ABS (I n))) -( 1 : num)) + | F => (( 2 : int))** (Num (ABS (I n))) + )))`; + + +val _ = Define ` + ((get_min_representable_in:'a -> int -> int) _ (n : int) : int= + (if n =( 64 : int) then min_64 + else if n =( 32 : int) then min_32 + else if n =( 8 : int) then min_8 + else if n =( 5 : int) then min_5 + else( 0 : int) - ((( 2 : int))** (Num (ABS (I n))))))`; + + +(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => + (Num.integer -> Num.integer -> Num.integer) -> bool -> 'a -> Num.integer -> 'a*) +val _ = Define ` + ((arith_op_bv_int:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail_values_Bitvector_a op sign l r= + (let r' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l r'))`; + + +(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => + (Num.integer -> Num.integer -> Num.integer) -> bool -> Num.integer -> 'a -> 'a*) +val _ = Define ` + ((arith_op_int_bv:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail_values_Bitvector_a op sign l r= + (let l' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method r) l) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l' r))`; + + +val _ = Define ` + ((arith_op_bv_bool:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a op sign l r= (arith_op_bv_int + dict_Sail_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`; + +val _ = Define ` + ((arith_op_bv_bit:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool + dict_Sail_values_Bitvector_a op sign l) (bool_of_bitU r)))`; + + +(* TODO (or just omit and define it per spec if needed) +val arith_op_overflow_bv : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU) +let arith_op_overflow_bv op sign size l r = + let len = length l in + let act_size = len * size in + match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with + | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) -> + let n = op l_sign r_sign in + let n_unsign = op l_unsign r_unsign in + let correct_size = of_int act_size n in + let one_more_size_u = bits_of_int (act_size + 1) n_unsign in + let overflow = + if n <= get_max_representable_in sign len && + n >= get_min_representable_in sign len + then B0 else B1 in + let c_out = most_significant one_more_size_u in + (correct_size,overflow,c_out) + | (_, _, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv = arith_op_overflow_bv integerAdd false 1 +let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1 +let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1 +let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1 +let mult_overflow_bv = arith_op_overflow_bv integerMult false 2 +let mults_overflow_bv = arith_op_overflow_bv integerMult true 2 + +val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU) +let arith_op_overflow_bv_bit op sign size l r_bit = + let act_size = length l * size in + match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with + | (Just l', Just l_u, false) -> + let (n, nu, changed) = match r_bit with + | B1 -> (op l' 1, op l_u 1, true) + | B0 -> (l', l_u, false) + | BU -> (* unreachable due to check above *) + failwith "arith_op_overflow_bv_bit applied to undefined bit" + end in + let correct_size = of_int act_size n in + let one_larger = bits_of_int (act_size + 1) nu in + let overflow = + if changed + then + if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size + then B0 else B1 + else B0 in + (correct_size, overflow, most_significant one_larger) + | (_, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1 +let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1 +let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1 +let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*) + +val _ = Hol_datatype ` + shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot`; + + +val _ = Define ` + ((invert_shift:shift -> shift)= + (\x . (case x of + LL_shift => RR_shift + | RR_shift => LL_shift + | RR_shift_arith => LL_shift + | LL_rot => RR_rot + | RR_rot => LL_rot + )))`; + + +(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((shift_op_bv:'a sail_values$Bitvector_class -> shift -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a op v n= + (let v = (dict_Sail_values_Bitvector_a.bits_of_method v) in + if n =( 0 : int) then v else + let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in + (case op of + LL_shift => + subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ repeat [B0] n + | RR_shift => + repeat [B0] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int)) + | RR_shift_arith => + repeat [most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int)) + | LL_rot => + subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ subrange_list T v(( 0 : int)) (n -( 1 : int)) + | RR_rot => + subrange_list F v(( 0 : int)) (n -( 1 : int)) ++ subrange_list F v n (int_of_num (LENGTH v) -( 1 : int)) + )))`; + + +val _ = Define ` + ((shiftl_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + dict_Sail_values_Bitvector_a LL_shift))`; + (*"<<"*) +val _ = Define ` + ((shiftr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + dict_Sail_values_Bitvector_a RR_shift))`; + (*">>"*) +val _ = Define ` + ((arith_shiftr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + dict_Sail_values_Bitvector_a RR_shift_arith))`; + +val _ = Define ` + ((rotl_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + dict_Sail_values_Bitvector_a LL_rot))`; + (*"<<<"*) +val _ = Define ` + ((rotr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + dict_Sail_values_Bitvector_a LL_rot))`; + (*">>>"*) + +val _ = Define ` + ((shiftl_mword:'a words$word -> int -> 'a words$word) w n= (words$word_lsl w (nat_of_int n)))`; + +val _ = Define ` + ((shiftr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_lsr w (nat_of_int n)))`; + +val _ = Define ` + ((arith_shiftr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_asr w (nat_of_int n)))`; + +val _ = Define ` + ((rotl_mword:'a words$word -> int -> 'a words$word) w n= (words$word_rol w (nat_of_int n)))`; + +val _ = Define ` + ((rotr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_ror w (nat_of_int n)))`; + + + val _ = Define ` + ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r= + (if r =( 0 : int) + then NONE + else SOME (op l r)))`; + + +(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => + (Num.integer -> Num.integer -> Num.integer) -> bool -> Num.integer -> 'a -> 'a -> Maybe.maybe 'b*) +val _ = Define ` + ((arith_op_bv_no0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= + (OPTION_BIND (int_of_bv + dict_Sail_values_Bitvector_a sign l) (\ l' . + OPTION_BIND (int_of_bv + dict_Sail_values_Bitvector_a sign r) (\ r' . + if r' =( 0 : int) then NONE else SOME ( + dict_Sail_values_Bitvector_b.of_int_method (dict_Sail_values_Bitvector_a.length_method l * size1) (op l' r'))))))`; + + +val _ = Define ` + ((mod_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; + +val _ = Define ` + ((quot_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; + +val _ = Define ` + ((quots_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot T(( 1 : int))))`; + + +val _ = Define ` + ((mod_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_mod)`; + +val _ = Define ` + ((quot_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_div)`; + +val _ = Define ` + ((quots_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_quot)`; + + +val _ = Define ` + ((arith_op_bv_int_no0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= + (arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r)))`; + + +val _ = Define ` + ((quot_bv_int:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; + +val _ = Define ` + ((mod_bv_int:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; + + +val _ = Define ` + ((mod_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_mod l (integer_word$i2w r)))`; + +val _ = Define ` + ((quot_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_div l (integer_word$i2w r)))`; + +val _ = Define ` + ((quots_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_quot l (integer_word$i2w r)))`; + + +val _ = Define ` + ((replicate_bits_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a v count1= (repeat ( + dict_Sail_values_Bitvector_a.bits_of_method v) count1))`; + +val _ = Define ` + ((duplicate_bit_bv:'a sail_values$BitU_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_BitU_a bit len= (replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len))`; + + +(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +val _ = Define ` + ((eq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ( + dict_Sail_values_Bitvector_a.bits_of_method l = dict_Sail_values_Bitvector_a.bits_of_method r))`; + + +(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +val _ = Define ` + ((neq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (eq_bv + dict_Sail_values_Bitvector_a l r)))`; + + +(*val ult_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +val _ = Define ` + ((ult_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (lexicographic_less (\ l r. (compare_bitU l r) = LT) (\ l r. (compare_bitU l r) <> GT) (REVERSE ( + dict_Sail_values_Bitvector_a.bits_of_method l)) (REVERSE (dict_Sail_values_Bitvector_a.bits_of_method r))))`; + +val _ = Define ` + ((ulteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv + dict_Sail_values_Bitvector_a l r) \/ (ult_bv dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((ugt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (ulteq_bv + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((ugteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv + dict_Sail_values_Bitvector_a l r) \/ (ugt_bv dict_Sail_values_Bitvector_a l r)))`; + + +(*val slt_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +val _ = Define ` + ((slt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= + ((case (most_significant + dict_Sail_values_Bitvector_a l, most_significant dict_Sail_values_Bitvector_a r) of + (B0, B0) => ult_bv + dict_Sail_values_Bitvector_a l r + | (B0, B1) => F + | (B1, B0) => T + | (B1, B1) => + let l' = (add_one_bit_ignore_overflow ( + dict_Sail_values_Bitvector_a.bits_of_method l)) in + let r' = (add_one_bit_ignore_overflow ( + dict_Sail_values_Bitvector_a.bits_of_method r)) in + ugt_bv (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l' r' + | (BU, BU) => ult_bv + dict_Sail_values_Bitvector_a l r + | (BU, _) => T + | (_, BU) => F + )))`; + +val _ = Define ` + ((slteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv + dict_Sail_values_Bitvector_a l r) \/ (slt_bv dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((sgt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (slteq_bv + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((sgteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv + dict_Sail_values_Bitvector_a l r) \/ (sgt_bv dict_Sail_values_Bitvector_a l r)))`; + + +(*val ucmp_mword : forall 'a. Size 'a => (Num.integer -> Num.integer -> bool) -> Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) + +(*val scmp_mword : forall 'a. Size 'a => (Num.integer -> Num.integer -> bool) -> Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml new file mode 100644 index 00000000..5d2978bb --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml @@ -0,0 +1,792 @@ +(*Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail_operators_bitlists" + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(* Specialisation of operators to bit lists *) + +(*val uint_maybe : list Sail_values.bitU -> Maybe.maybe Num.integer*) +val _ = Define ` + ((uint_maybe0:(sail_values$bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`; + +val _ = Define ` + ((uint_fail0:'a sail_values$Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "uint" ( + dict_Sail_values_Bitvector_a.unsigned_method v)))`; + +val _ = Define ` + ((uint_oracle0:(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS +(state$bools_of_bits_oracleS v) (\ bs . + state_monad$returnS (int_of_bools F bs))))`; + +val _ = Define ` + ((uint:(sail_values$bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`; + + +(*val sint_maybe : list Sail_values.bitU -> Maybe.maybe Num.integer*) +val _ = Define ` + ((sint_maybe0:(sail_values$bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`; + +val _ = Define ` + ((sint_fail0:'a sail_values$Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "sint" ( + dict_Sail_values_Bitvector_a.signed_method v)))`; + +val _ = Define ` + ((sint_oracle0:(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS +(state$bools_of_bits_oracleS v) (\ bs . + state_monad$returnS (int_of_bools T bs))))`; + +val _ = Define ` + ((sint:(sail_values$bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`; + + +(*val extz_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((extz_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val exts_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((exts_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (exts_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val zero_extend : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((zero_extend0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bits len= (extz_bits len bits))`; + + +(*val sign_extend : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((sign_extend0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bits len= (exts_bits len bits))`; + + +(*val vector_truncate : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((vector_truncate0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bs len= (extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) len bs))`; + + +(*val vec_of_bits_maybe : list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) +(*val vec_of_bits_fail : forall 'rv 'e. list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'e. list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val vec_of_bits_failwith : list Sail_values.bitU -> list Sail_values.bitU*) +(*val vec_of_bits : list Sail_values.bitU -> list Sail_values.bitU*) + +(*val access_vec_inc : list Sail_values.bitU -> Num.integer -> Sail_values.bitU*) +val _ = Define ` + ((access_vec_inc0:(sail_values$bitU)list -> int -> sail_values$bitU)= + (access_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val access_vec_dec : list Sail_values.bitU -> Num.integer -> Sail_values.bitU*) +val _ = Define ` + ((access_vec_dec0:(sail_values$bitU)list -> int -> sail_values$bitU)= + (access_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val update_vec_inc : list Sail_values.bitU -> Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((update_vec_inc0:(sail_values$bitU)list -> int -> sail_values$bitU ->(sail_values$bitU)list)= + (update_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((update_vec_inc_maybe0:(sail_values$bitU)list -> int -> sail_values$bitU ->((sail_values$bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`; + +val _ = Define ` + ((update_vec_inc_fail0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; + +val _ = Define ` + ((update_vec_inc_oracle0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; + + +(*val update_vec_dec : list Sail_values.bitU -> Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((update_vec_dec0:(sail_values$bitU)list -> int -> sail_values$bitU ->(sail_values$bitU)list)= + (update_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((update_vec_dec_maybe0:(sail_values$bitU)list -> int -> sail_values$bitU ->((sail_values$bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`; + +val _ = Define ` + ((update_vec_dec_fail0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; + +val _ = Define ` + ((update_vec_dec_oracle0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; + + +(*val subrange_vec_inc : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((subrange_vec_inc0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list)= + (subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val subrange_vec_dec : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((subrange_vec_dec0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list)= + (subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val update_subrange_vec_inc : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((update_subrange_vec_inc0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (update_subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val update_subrange_vec_dec : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((update_subrange_vec_dec0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (update_subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val concat_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((concat_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (concat_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val cons_vec : Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((cons_vec0:sail_values$bitU ->(sail_values$bitU)list ->(sail_values$bitU)list)= + (cons_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((cons_vec_maybe0:sail_values$bitU ->(sail_values$bitU)list ->((sail_values$bitU)list)option) b v= (SOME (cons_vec0 b v)))`; + +val _ = Define ` + ((cons_vec_fail0:sail_values$bitU ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; + +val _ = Define ` + ((cons_vec_oracle0:sail_values$bitU ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; + + +(*val cast_unit_vec : Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((cast_unit_vec0:sail_values$bitU ->(sail_values$bitU)list)= cast_unit_bv)`; + +val _ = Define ` + ((cast_unit_vec_maybe0:sail_values$bitU ->((sail_values$bitU)list)option) b= (SOME (cast_unit_vec0 b)))`; + +val _ = Define ` + ((cast_unit_vec_fail0:sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; + +val _ = Define ` + ((cast_unit_vec_oracle0:sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; + + +(*val vec_of_bit : Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((vec_of_bit0:int -> sail_values$bitU ->(sail_values$bitU)list)= bv_of_bit)`; + +val _ = Define ` + ((vec_of_bit_maybe0:int -> sail_values$bitU ->((sail_values$bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`; + +val _ = Define ` + ((vec_of_bit_fail0:int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; + +val _ = Define ` + ((vec_of_bit_oracle0:int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; + + +(*val msb : list Sail_values.bitU -> Sail_values.bitU*) +val _ = Define ` + ((msb0:(sail_values$bitU)list -> sail_values$bitU)= + (most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val int_of_vec_maybe : bool -> list Sail_values.bitU -> Maybe.maybe Num.integer*) +val _ = Define ` + ((int_of_vec_maybe0:bool ->(sail_values$bitU)list ->(int)option)= + (int_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((int_of_vec_fail0:bool ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`; + +val _ = Define ` + ((int_of_vec_oracle:bool ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$bindS (state$bools_of_bits_oracleS v) (\ v . state_monad$returnS (int_of_bools sign v))))`; + +val _ = Define ` + ((int_of_vec0:bool ->(sail_values$bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`; + + +(*val string_of_vec : list Sail_values.bitU -> string*) +val _ = Define ` + ((string_of_vec0:(sail_values$bitU)list -> string)= + (string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val and_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val or_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val xor_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val not_vec : list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((and_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list and_bit))`; + +val _ = Define ` + ((or_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list or_bit))`; + +val _ = Define ` + ((xor_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list xor_bit))`; + +val _ = Define ` + ((not_vec0:(sail_values$bitU)list ->(sail_values$bitU)list)= (MAP not_bit))`; + + +(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => + (Num.integer -> Num.integer -> Num.integer) -> bool -> 'a -> 'a -> list Sail_values.bitU*) +val _ = Define ` + ((arith_op_double_bl:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a op sign l r= + (let len =(( 2 : int) * + dict_Sail_values_Bitvector_a.length_method l) in + let l' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in + let r' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in + MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`; + + +(*val add_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val adds_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val sub_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val subs_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val mult_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val mults_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((add_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((adds_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((sub_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((subs_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((mult_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F))`; + +val _ = Define ` + ((mults_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T))`; + + +(*val add_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val adds_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val sub_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val subs_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val mult_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val mults_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((add_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; + +val _ = Define ` + ((adds_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; + +val _ = Define ` + ((sub_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; + +val _ = Define ` + ((subs_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; + +val _ = Define ` + ((mult_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; + +val _ = Define ` + ((mults_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; + + +(*val add_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val adds_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val sub_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val subs_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val mult_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val mults_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((add_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; + +val _ = Define ` + ((adds_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; + +val _ = Define ` + ((sub_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; + +val _ = Define ` + ((subs_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; + +val _ = Define ` + ((mult_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; + +val _ = Define ` + ((mults_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; + + +(*val add_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) +(*val adds_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) +(*val sub_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) +(*val subs_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) + +val _ = Define ` + ((add_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail_values_Bitvector_a (+) F l r))`; + +val _ = Define ` + ((add_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail_values_Bitvector_a (+) F l r))`; + +val _ = Define ` + ((add_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((add_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool0 + dict_Sail_values_Bitvector_a l r))))`; + +val _ = Define ` + ((add_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (add_vec_bit_maybe0 + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((adds_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail_values_Bitvector_a (+) T l r))`; + +val _ = Define ` + ((adds_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail_values_Bitvector_a (+) T l r))`; + +val _ = Define ` + ((adds_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((adds_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool0 + dict_Sail_values_Bitvector_a l r))))`; + +val _ = Define ` + ((adds_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (adds_vec_bit_maybe0 + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((sub_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail_values_Bitvector_a (-) F l r))`; + +val _ = Define ` + ((sub_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail_values_Bitvector_a (-) F l r))`; + +val _ = Define ` + ((sub_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((sub_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool0 + dict_Sail_values_Bitvector_a l r))))`; + +val _ = Define ` + ((sub_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (sub_vec_bit_maybe0 + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((subs_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail_values_Bitvector_a (-) T l r))`; + +val _ = Define ` + ((subs_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail_values_Bitvector_a (-) T l r))`; + +val _ = Define ` + ((subs_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 + dict_Sail_values_Bitvector_a l r)))`; + +val _ = Define ` + ((subs_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool0 + dict_Sail_values_Bitvector_a l r))))`; + +val _ = Define ` + ((subs_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (subs_vec_bit_maybe0 + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val shiftr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val arith_shiftr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val rotl : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val rotr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((shiftl0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (shiftl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((shiftr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((arith_shiftr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (arith_shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((rotl0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (rotl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((rotr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (rotr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val mod_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val mod_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) +(*val mod_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val mod_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +val _ = Define ` + ((mod_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((mod_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; + +val _ = Define ` + ((mod_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; + +val _ = Define ` + ((mod_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec0 l r)))`; + + +(*val quot_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val quot_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) +(*val quot_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quot_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +val _ = Define ` + ((quot_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quot_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; + +val _ = Define ` + ((quot_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quot_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec0 l r)))`; + + +(*val quots_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val quots_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) +(*val quots_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quots_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +val _ = Define ` + ((quots_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quots_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; + +val _ = Define ` + ((quots_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quots_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec0 l r)))`; + + +(*val mod_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val mod_vec_int_maybe : list Sail_values.bitU -> Num.integer -> Maybe.maybe (list Sail_values.bitU)*) +(*val mod_vec_int_fail : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +val _ = Define ` + ((mod_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (option_CASE (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((mod_vec_int_maybe0:(sail_values$bitU)list -> int ->((sail_values$bitU)list)option) l r= (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; + +val _ = Define ` + ((mod_vec_int_fail0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; + +val _ = Define ` + ((mod_vec_int_oracle0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int0 l r)))`; + + +(*val quot_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val quot_vec_int_maybe : list Sail_values.bitU -> Num.integer -> Maybe.maybe (list Sail_values.bitU)*) +(*val quot_vec_int_fail : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +val _ = Define ` + ((quot_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (option_CASE (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quot_vec_int_maybe0:(sail_values$bitU)list -> int ->((sail_values$bitU)list)option) l r= (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; + +val _ = Define ` + ((quot_vec_int_fail0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quot_vec_int_oracle0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int0 l r)))`; + + +(*val replicate_bits : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((replicate_bits0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + (replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + + +(*val duplicate : Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +val _ = Define ` + ((duplicate0:sail_values$bitU -> int ->(sail_values$bitU)list)= + (duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict))`; + +val _ = Define ` + ((duplicate_maybe0:sail_values$bitU -> int ->((sail_values$bitU)list)option) b n= (SOME (duplicate0 b n)))`; + +val _ = Define ` + ((duplicate_fail0:sail_values$bitU -> int -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$returnS (duplicate0 b n)))`; + +val _ = Define ` + ((duplicate_oracle0:sail_values$bitU -> int -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$bindS +(state$bool_of_bitU_oracleS b) (\ b . + state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`; + + +(*val reverse_endianness : list Sail_values.bitU -> list Sail_values.bitU*) +val _ = Define ` + ((reverse_endianness0:(sail_values$bitU)list ->(sail_values$bitU)list) v= (reverse_endianness_list v))`; + + +(*val eq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val neq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val ult_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val slt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val ugt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val sgt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val ulteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val slteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val ugteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val sgteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +val _ = Define ` + ((eq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (eq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((neq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (neq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((ult_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (ult_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((slt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (slt_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((ugt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (ugt_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((sgt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (sgt_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((ulteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (ulteq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((slteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (slteq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((ugteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (ugteq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = Define ` + ((sgteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= + (sgteq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml new file mode 100644 index 00000000..bd0a68ef --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml @@ -0,0 +1,612 @@ +(*Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail_operators_mwords" + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) +val _ = Define ` + ((uint_maybe:'a words$word ->(int)option) v= (SOME (lem$w2ui v)))`; + +val _ = Define ` + ((uint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (lem$w2ui v)))`; + +val _ = Define ` + ((uint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (lem$w2ui v)))`; + +val _ = Define ` + ((sint_maybe:'a words$word ->(int)option) v= (SOME (integer_word$w2i v)))`; + +val _ = Define ` + ((sint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (integer_word$w2i v)))`; + +val _ = Define ` + ((sint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (integer_word$w2i v)))`; + + +(*val vec_of_bits_maybe : forall 'a. Size 'a => list Sail_values.bitU -> Maybe.maybe (Machine_word.mword 'a)*) +(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list Sail_values.bitU -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list Sail_values.bitU -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val vec_of_bits_failwith : forall 'a. Size 'a => list Sail_values.bitU -> Machine_word.mword 'a*) +(*val vec_of_bits : forall 'a. Size 'a => list Sail_values.bitU -> Machine_word.mword 'a*) +val _ = Define ` + ((vec_of_bits_maybe:(sail_values$bitU)list ->('a words$word)option) bits= (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`; + +val _ = Define ` + ((vec_of_bits_fail:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_failS + instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + +val _ = Define ` + ((vec_of_bits_oracle:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_oracleS + instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + +val _ = Define ` + ((vec_of_bits_failwith:(sail_values$bitU)list -> 'a words$word) bits= (of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + +val _ = Define ` + ((vec_of_bits:(sail_values$bitU)list -> 'a words$word) bits= (of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + + +(*val access_vec_inc : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Sail_values.bitU*) +val _ = Define ` + ((access_vec_inc:'a words$word -> int -> sail_values$bitU)= + (access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +(*val access_vec_dec : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Sail_values.bitU*) +val _ = Define ` + ((access_vec_dec:'a words$word -> int -> sail_values$bitU)= + (access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +val _ = Define ` + ((update_vec_dec_maybe:'a words$word -> int -> sail_values$bitU ->('a words$word)option) w i b= (update_mword_dec w i b))`; + +val _ = Define ` + ((update_vec_dec_fail:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS +(state$bool_of_bitU_fail b) (\ b . + state_monad$returnS (update_mword_bool_dec w i b))))`; + +val _ = Define ` + ((update_vec_dec_oracle:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS +(state$bool_of_bitU_oracleS b) (\ b . + state_monad$returnS (update_mword_bool_dec w i b))))`; + +val _ = Define ` + ((update_vec_dec:'a words$word -> int -> sail_values$bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_dec_maybe w i b)))`; + + +val _ = Define ` + ((update_vec_inc_maybe:'a words$word -> int -> sail_values$bitU ->('a words$word)option) w i b= (update_mword_inc w i b))`; + +val _ = Define ` + ((update_vec_inc_fail:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS +(state$bool_of_bitU_fail b) (\ b . + state_monad$returnS (update_mword_bool_inc w i b))))`; + +val _ = Define ` + ((update_vec_inc_oracle:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS +(state$bool_of_bitU_oracleS b) (\ b . + state_monad$returnS (update_mword_bool_inc w i b))))`; + +val _ = Define ` + ((update_vec_inc:'a words$word -> int -> sail_values$bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_inc_maybe w i b)))`; + + +(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((subrange_vec_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int i) (nat_of_int j) w))`; + + +(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((subrange_vec_inc:'a words$word -> int -> int -> 'b words$word) w i j= (subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j)))`; + + +(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +val _ = Define ` + ((update_subrange_vec_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int i) (nat_of_int j) w' w))`; + + +(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +val _ = Define ` + ((update_subrange_vec_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (update_subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j) w'))`; + + +(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +val _ = Define ` + ((extz_vec:int -> 'a words$word -> 'b words$word) _ w= (words$w2w w))`; + + +(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +val _ = Define ` + ((exts_vec:int -> 'a words$word -> 'b words$word) _ w= (words$sw2sw w))`; + + +(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((zero_extend:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`; + + +(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((sign_extend:'a words$word -> int -> 'b words$word) w _= (words$sw2sw w))`; + + +(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((vector_truncate:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`; + + +(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => Machine_word.mword 'a -> Machine_word.mword 'b -> Machine_word.mword 'c*) +val _ = Define ` + ((concat_vec:'a words$word -> 'b words$word -> 'c words$word)= words$word_concat)`; + + +(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> Machine_word.mword 'a -> Machine_word.mword 'b*) +val _ = Define ` + ((cons_vec_bool:bool -> 'a words$word -> 'b words$word) b w= (bitstring$v2w (b :: bitstring$w2v w)))`; + +val _ = Define ` + ((cons_vec_maybe:sail_values$bitU -> 'c words$word ->('b words$word)option) b w= (OPTION_MAP (\ b . cons_vec_bool b w) (bool_of_bitU b)))`; + +val _ = Define ` + ((cons_vec_fail:sail_values$bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + +val _ = Define ` + ((cons_vec_oracle:sail_values$bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + +val _ = Define ` + ((cons_vec:sail_values$bitU -> 'a words$word -> 'b words$word) b w= (maybe_failwith (cons_vec_maybe b w)))`; + + +(*val vec_of_bool : forall 'a. Size 'a => Num.integer -> bool -> Machine_word.mword 'a*) +val _ = Define ` + ((vec_of_bool:int -> bool -> 'a words$word) _ b= (bitstring$v2w [b]))`; + +val _ = Define ` + ((vec_of_bit_maybe:int -> sail_values$bitU ->('a words$word)option) len b= (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`; + +val _ = Define ` + ((vec_of_bit_fail:int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + +val _ = Define ` + ((vec_of_bit_oracle:int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + +val _ = Define ` + ((vec_of_bit:int -> sail_values$bitU -> 'a words$word) len b= (maybe_failwith (vec_of_bit_maybe len b)))`; + + +(*val cast_bool_vec : bool -> Machine_word.mword Machine_word.ty1*) +val _ = Define ` + ((cast_bool_vec:bool ->(1)words$word) b= (vec_of_bool(( 1 : int)) b))`; + +val _ = Define ` + ((cast_unit_vec_maybe:sail_values$bitU ->('a words$word)option) b= (vec_of_bit_maybe(( 1 : int)) b))`; + +val _ = Define ` + ((cast_unit_vec_fail:sail_values$bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + +val _ = Define ` + ((cast_unit_vec_oracle:sail_values$bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + +val _ = Define ` + ((cast_unit_vec:sail_values$bitU -> 'a words$word) b= (maybe_failwith (cast_unit_vec_maybe b)))`; + + +(*val msb : forall 'a. Size 'a => Machine_word.mword 'a -> Sail_values.bitU*) +val _ = Define ` + ((msb:'a words$word -> sail_values$bitU)= + (most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +(*val int_of_vec : forall 'a. Size 'a => bool -> Machine_word.mword 'a -> Num.integer*) +val _ = Define ` + ((int_of_vec:bool -> 'a words$word -> int) sign w= + (if sign + then integer_word$w2i w + else lem$w2ui w))`; + +val _ = Define ` + ((int_of_vec_maybe:bool -> 'a words$word ->(int)option) sign w= (SOME (int_of_vec sign w)))`; + +val _ = Define ` + ((int_of_vec_fail:bool -> 'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) sign w= (state_monad$returnS (int_of_vec sign w)))`; + + +(*val string_of_vec : forall 'a. Size 'a => Machine_word.mword 'a -> string*) +val _ = Define ` + ((string_of_vec:'a words$word -> string)= + (string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +(*val and_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val or_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val xor_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val not_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a*) +val _ = Define ` + ((and_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_and)`; + +val _ = Define ` + ((or_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_or)`; + +val _ = Define ` + ((xor_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_xor)`; + +val _ = Define ` + ((not_vec:'a words$word -> 'a words$word)= words$word_1comp)`; + + +(*val add_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val adds_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val sub_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val subs_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'b*) +val _ = Define ` + ((add_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword F l) + (int_of_mword F r))))`; + +val _ = Define ` + ((adds_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword T l) + (int_of_mword T r))))`; + +val _ = Define ` + ((sub_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword F l) - (int_of_mword F r))))`; + +val _ = Define ` + ((subs_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword T l) - (int_of_mword T r))))`; + +val _ = Define ` + ((mult_vec:'a words$word -> 'a words$word -> 'b words$word) l r= (integer_word$i2w ((int_of_mword F (words$w2w l : 'b words$word)) * (int_of_mword F (words$w2w r : 'b words$word)))))`; + +val _ = Define ` + ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r= (integer_word$i2w ((int_of_mword T (words$sw2sw l : 'b words$word)) * (int_of_mword T (words$sw2sw r : 'b words$word)))))`; + + +(*val add_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val adds_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val sub_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val subs_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((add_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + +val _ = Define ` + ((adds_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + +val _ = Define ` + ((sub_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + +val _ = Define ` + ((subs_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + +val _ = Define ` + ((mult_vec_int:'a words$word -> int -> 'b words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) F (words$w2w l : 'b words$word) r))`; + +val _ = Define ` + ((mults_vec_int:'a words$word -> int -> 'b words$word) l r= (arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T (words$sw2sw l : 'b words$word) r))`; + + +(*val add_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val adds_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val sub_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val subs_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +val _ = Define ` + ((add_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + +val _ = Define ` + ((adds_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + +val _ = Define ` + ((sub_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + +val _ = Define ` + ((subs_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + +val _ = Define ` + ((mult_int_vec:int -> 'a words$word -> 'b words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) F l (words$w2w r : 'b words$word)))`; + +val _ = Define ` + ((mults_int_vec:int -> 'a words$word -> 'b words$word) l r= (arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T l (words$sw2sw r : 'b words$word)))`; + + +(*val add_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) +(*val adds_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) +(*val sub_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) +(*val subs_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) + +val _ = Define ` + ((add_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + +val _ = Define ` + ((add_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`; + +val _ = Define ` + ((add_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + +val _ = Define ` + ((add_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + +val _ = Define ` + ((add_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (add_vec_bit_maybe l r)))`; + + +val _ = Define ` + ((adds_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + +val _ = Define ` + ((adds_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`; + +val _ = Define ` + ((adds_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + +val _ = Define ` + ((adds_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + +val _ = Define ` + ((adds_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (adds_vec_bit_maybe l r)))`; + + +val _ = Define ` + ((sub_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + +val _ = Define ` + ((sub_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`; + +val _ = Define ` + ((sub_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + +val _ = Define ` + ((sub_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + +val _ = Define ` + ((sub_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (sub_vec_bit_maybe l r)))`; + + +val _ = Define ` + ((subs_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + +val _ = Define ` + ((subs_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`; + +val _ = Define ` + ((subs_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + +val _ = Define ` + ((subs_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + +val _ = Define ` + ((subs_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (subs_vec_bit_maybe l r)))`; + + +(* TODO +val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU) +let maybe_mword_of_bits_overflow (bits, overflow, carry) = + Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits) + +val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val adds_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val subs_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +let add_overflow_vec l r = maybe_mword_of_bits_overflow (add_overflow_bv l r) +let adds_overflow_vec l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r) +let sub_overflow_vec l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r) +let subs_overflow_vec l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r) +let mult_overflow_vec l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r) +let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r) + +val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val shiftr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val arith_shiftr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val rotl : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val rotr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +val _ = Define ` + ((shiftl:'a words$word -> int -> 'a words$word)= shiftl_mword)`; + +val _ = Define ` + ((shiftr:'a words$word -> int -> 'a words$word)= shiftr_mword)`; + +val _ = Define ` + ((arith_shiftr:'a words$word -> int -> 'a words$word)= arith_shiftr_mword)`; + +val _ = Define ` + ((rotl:'a words$word -> int -> 'a words$word)= rotl_mword)`; + +val _ = Define ` + ((rotr:'a words$word -> int -> 'a words$word)= rotr_mword)`; + + +(*val mod_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val mod_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) +(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((mod_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (mod_mword l r))`; + +val _ = Define ` + ((mod_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + +val _ = Define ` + ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + +val _ = Define ` + ((mod_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => state_monad$returnS w + | NONE => state$mword_oracleS () + )))`; + + +(*val quot_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val quot_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) +(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((quot_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quot_mword l r))`; + +val _ = Define ` + ((quot_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + +val _ = Define ` + ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + +val _ = Define ` + ((quot_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => state_monad$returnS w + | NONE => state$mword_oracleS () + )))`; + + +(*val quots_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val quots_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) +(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((quots_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quots_mword l r))`; + +val _ = Define ` + ((quots_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + +val _ = Define ` + ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + +val _ = Define ` + ((quots_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => state_monad$returnS w + | NONE => state$mword_oracleS () + )))`; + + +(*val mod_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val mod_vec_int_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Maybe.maybe (Machine_word.mword 'a)*) +(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((mod_vec_int:'a words$word -> int -> 'a words$word) l r= (mod_mword_int l r))`; + +val _ = Define ` + ((mod_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + +val _ = Define ` + ((mod_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + +val _ = Define ` + ((mod_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => state_monad$returnS w + | NONE => state$mword_oracleS () + )))`; + + +(*val quot_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val quot_vec_int_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Maybe.maybe (Machine_word.mword 'a)*) +(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((quot_vec_int:'a words$word -> int -> 'a words$word) l r= (quot_mword_int l r))`; + +val _ = Define ` + ((quot_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + +val _ = Define ` + ((quot_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + +val _ = Define ` + ((quot_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quot_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => state_monad$returnS w + | NONE => state$mword_oracleS () + )))`; + + +(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((replicate_bits:'a words$word -> int -> 'b words$word) v count1= (bitstring$v2w (repeat (bitstring$w2v v) count1)))`; + + +(*val duplicate_bool : forall 'a. Size 'a => bool -> Num.integer -> Machine_word.mword 'a*) +val _ = Define ` + ((duplicate_bool:bool -> int -> 'a words$word) b n= (bitstring$v2w (repeat [b] n)))`; + +val _ = Define ` + ((duplicate_maybe:sail_values$bitU -> int ->('a words$word)option) b n= (OPTION_MAP (\ b . duplicate_bool b n) (bool_of_bitU b)))`; + +val _ = Define ` + ((duplicate_fail:sail_values$bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + +val _ = Define ` + ((duplicate_oracle:sail_values$bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + +val _ = Define ` + ((duplicate:sail_values$bitU -> int -> 'a words$word) b n= (maybe_failwith (duplicate_maybe b n)))`; + + +(*val reverse_endianness : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a*) +val _ = Define ` + ((reverse_endianness:'a words$word -> 'a words$word) v= (bitstring$v2w (reverse_endianness_list (bitstring$w2v v))))`; + + +(*val eq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val neq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val ult_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val slt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val ugt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val sgt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val ulteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val slteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val ugteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val sgteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml b/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml new file mode 100644 index 00000000..2d6c019a --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml @@ -0,0 +1,1238 @@ +(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail_values" + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_impl_base*) + + +val _ = type_abbrev( "ii" , ``: int``); +val _ = type_abbrev( "nn" , ``: num``); + +(*val nat_of_int : Num.integer -> nat*) +val _ = Define ` + ((nat_of_int:int -> num) i= (if i <( 0 : int) then( 0 : num) else Num (ABS (I i))))`; + + +(*val pow : Num.integer -> Num.integer -> Num.integer*) +val _ = Define ` + ((pow0:int -> int -> int) m n= (m ** (nat_of_int n)))`; + + +val _ = Define ` + ((pow2:int -> int) n= (pow0(( 2 : int)) n))`; + + +(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*let add_int l r = integerAdd l r +let add_signed l r = integerAdd l r +let sub_int l r = integerMinus l r +let mult_int l r = integerMult l r +let div_int l r = integerDiv l r +let div_nat l r = natDiv l r +let power_int_nat l r = integerPow l r +let power_int_int l r = integerPow l (nat_of_int r) +let negate_int i = integerNegate i +let min_int l r = integerMin l r +let max_int l r = integerMax l r + +let add_real l r = realAdd l r +let sub_real l r = realMinus l r +let mult_real l r = realMult l r +let div_real l r = realDiv l r +let negate_real r = realNegate r +let abs_real r = realAbs r +let power_real b e = realPowInteger b e*) + +(*val prerr_endline : string -> unit*) +val _ = Define ` + ((prerr_endline:string -> unit) _= () )`; + + +(*val print_int : string -> Num.integer -> unit*) +val _ = Define ` + ((print_int:string -> int -> unit) msg i= (prerr_endline ( STRCAT msg (stringFromInteger i))))`; + + +(*val putchar : Num.integer -> unit*) +val _ = Define ` + ((putchar:int -> unit) _= () )`; + + +(*val shr_int : ii -> ii -> ii*) + val shr_int_defn = Hol_defn "shr_int" ` + ((shr_int:int -> int -> int) x s= (if s >( 0 : int) then shr_int (x /( 2 : int)) (s -( 1 : int)) else x))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shr_int_defn; + +(*val shl_int : Num.integer -> Num.integer -> Num.integer*) + val shl_int_defn = Hol_defn "shl_int" ` + ((shl_int:int -> int -> int) i shift= (if shift >( 0 : int) then( 2 : int) * shl_int i (shift -( 1 : int)) else i))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shl_int_defn; +val _ = Define ` + ((take_list:int -> 'a list -> 'a list) n xs= (TAKE (nat_of_int n) xs))`; + +val _ = Define ` + ((drop_list:int -> 'a list -> 'a list) n xs= (DROP (nat_of_int n) xs))`; + + +(*val repeat : forall 'a. list 'a -> Num.integer -> list 'a*) + val repeat_defn = Hol_defn "repeat" ` + ((repeat:'a list -> int -> 'a list) xs n= + (if n <=( 0 : int) then [] + else xs ++ repeat xs (n -( 1 : int))))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn repeat_defn; + +val _ = Define ` + ((duplicate_to_list:'a -> int -> 'a list) bit length= (repeat [bit] length))`; + + + val replace_defn = Hol_defn "replace" ` + ((replace:'a list -> int -> 'a -> 'a list) bs (n : int) b'= ((case bs of + [] => [] + | b :: bs => + if n =( 0 : int) then b' :: bs + else b :: replace bs (n -( 1 : int)) b' + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn replace_defn; + +val _ = Define ` + ((upper:'a -> 'a) n= n)`; + + +(* Modulus operation corresponding to quot below -- result + has sign of dividend. *) +val _ = Define ` + ((hardware_mod:int -> int -> int) (a: int) (b:int) : int= + (let m = ((ABS a) % (ABS b)) in + if a <( 0 : int) then ~ m else m))`; + + +(* There are different possible answers for integer divide regarding +rounding behaviour on negative operands. Positive operands always +round down so derive the one we want (trucation towards zero) from +that *) +val _ = Define ` + ((hardware_quot:int -> int -> int) (a:int) (b:int) : int= + (let q = ((ABS a) / (ABS b)) in + if ((a<( 0 : int)) <=> (b<( 0 : int))) then + q (* same sign -- result positive *) + else + ~ q))`; + (* different sign -- result negative *) + +val _ = Define ` + ((max_64u:int)= (((( 2 : int))**(( 64 : num))) -( 1 : int)))`; + +val _ = Define ` + ((max_64:int)= (((( 2 : int))**(( 63 : num))) -( 1 : int)))`; + +val _ = Define ` + ((min_64:int)= (( 0 : int) - ((( 2 : int))**(( 63 : num)))))`; + +val _ = Define ` + ((max_32u:int)= ((( 4294967295 : int) : int)))`; + +val _ = Define ` + ((max_32:int)= ((( 2147483647 : int) : int)))`; + +val _ = Define ` + ((min_32:int)= ((( 0 : int) -( 2147483648 : int) : int)))`; + +val _ = Define ` + ((max_8:int)= ((( 127 : int) : int)))`; + +val _ = Define ` + ((min_8:int)= ((( 0 : int) -( 128 : int) : int)))`; + +val _ = Define ` + ((max_5:int)= ((( 31 : int) : int)))`; + +val _ = Define ` + ((min_5:int)= ((( 0 : int) -( 32 : int) : int)))`; + + +(* just_list takes a list of maybes and returns Just xs if all elements have + a value, and Nothing if one of the elements is Nothing. *) +(*val just_list : forall 'a. list (Maybe.maybe 'a) -> Maybe.maybe (list 'a)*) + val just_list_defn = Hol_defn "just_list" ` + ((just_list:('a option)list ->('a list)option) l= ((case l of + [] => SOME [] + | (x :: xs) => + (case (x, just_list xs) of + (SOME x, SOME xs) => SOME (x :: xs) + | (_, _) => NONE + ) + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn just_list_defn; + +(*val maybe_failwith : forall 'a. Maybe.maybe 'a -> 'a*) +val _ = Define ` + ((maybe_failwith:'a option -> 'a)= + (\x . (case x of SOME a => a | NONE => failwith "maybe_failwith" )))`; + + +(*** Bits *) +val _ = Hol_datatype ` + bitU = B0 | B1 | BU`; + + +val _ = Define ` + ((showBitU:bitU -> string)= + (\x . (case x of B0 => "O" | B1 => "I" | BU => "U" )))`; + + +val _ = Define ` + ((bitU_char:bitU -> char)= + (\x . (case x of B0 => #"0" | B1 => #"1" | BU => #"?" )))`; + + +val _ = Define ` +((instance_Show_Show_Sail_values_bitU_dict:(bitU)lem_show$Show_class)= (<| + + show_method := showBitU|>))`; + + +(*val compare_bitU : bitU -> bitU -> Basic_classes.ordering*) +val _ = Define ` + ((compare_bitU:bitU -> bitU -> lem_basic_classes$ordering) l r= ((case (l, r) of + (BU, BU) => EQ + | (B0, B0) => EQ + | (B1, B1) => EQ + | (BU, _) => LT + | (_, BU) => GT + | (B0, _) => LT + | (_, _) => GT +)))`; + + +val _ = Define ` +((instance_Basic_classes_Ord_Sail_values_bitU_dict:(bitU)lem_basic_classes$Ord_class)= (<| + + compare_method := compare_bitU; + + isLess_method := (\ l r. (compare_bitU l r) = LT); + + isLessEqual_method := (\ l r. (compare_bitU l r) <> GT); + + isGreater_method := (\ l r. (compare_bitU l r) = GT); + + isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LT)|>))`; + + +val _ = Hol_datatype ` +(* 'a *) BitU_class= <| + to_bitU_method : 'a -> bitU; + of_bitU_method : bitU -> 'a +|>`; + + +val _ = Define ` +((instance_Sail_values_BitU_Sail_values_bitU_dict:(bitU)BitU_class)= (<| + + to_bitU_method := (\ b. b); + + of_bitU_method := (\ b. b)|>))`; + + +val _ = Define ` + ((bool_of_bitU:bitU ->(bool)option)= + (\x . (case x of B0 => SOME F | B1 => SOME T | BU => NONE )))`; + + +val _ = Define ` + ((bitU_of_bool:bool -> bitU) b= (if b then B1 else B0))`; + + +(*instance (BitU bool) + let to_bitU = bitU_of_bool + let of_bitU = bool_of_bitU +end*) + +val _ = Define ` + ((cast_bit_bool:bitU ->(bool)option)= bool_of_bitU)`; + + +val _ = Define ` + ((not_bit:bitU -> bitU)= + (\x . (case x of B1 => B0 | B0 => B1 | BU => BU )))`; + + +(*val is_one : Num.integer -> bitU*) +val _ = Define ` + ((is_one:int -> bitU) i= + (if i =( 1 : int) then B1 else B0))`; + + +(*val and_bit : bitU -> bitU -> bitU*) +val _ = Define ` + ((and_bit:bitU -> bitU -> bitU) x y= + ((case (x, y) of + (B0, _) => B0 + | (_, B0) => B0 + | (B1, B1) => B1 + | (_, _) => BU + )))`; + + +(*val or_bit : bitU -> bitU -> bitU*) +val _ = Define ` + ((or_bit:bitU -> bitU -> bitU) x y= + ((case (x, y) of + (B1, _) => B1 + | (_, B1) => B1 + | (B0, B0) => B0 + | (_, _) => BU + )))`; + + +(*val xor_bit : bitU -> bitU -> bitU*) +val _ = Define ` + ((xor_bit:bitU -> bitU -> bitU) x y= +((case (x, y) of + (B0, B0) => B0 + | (B0, B1) => B1 + | (B1, B0) => B1 + | (B1, B1) => B0 + | (_, _) => BU + )))`; + + +(*val &. : bitU -> bitU -> bitU*) + +(*val |. : bitU -> bitU -> bitU*) + +(*val +. : bitU -> bitU -> bitU*) + + +(*** Bool lists ***) + +(*val bools_of_nat_aux : Num.integer -> Num.natural -> list bool -> list bool*) + val bools_of_nat_aux_defn = Hol_defn "bools_of_nat_aux" ` + ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc= + (if len <=( 0 : int) then acc + else bools_of_nat_aux (len -( 1 : int)) (x DIV( 2:num)) ((if (x MOD( 2:num)) =( 1:num) then T else F) :: acc)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn bools_of_nat_aux_defn; +val _ = Define ` + ((bools_of_nat:int -> num ->(bool)list) len n= (bools_of_nat_aux len n []))`; + (*List.reverse (bools_of_nat_aux n)*) + +(*val nat_of_bools_aux : Num.natural -> list bool -> Num.natural*) + val nat_of_bools_aux_defn = Hol_defn "nat_of_bools_aux" ` + ((nat_of_bools_aux:num ->(bool)list -> num) acc bs= ((case bs of + [] => acc + | T :: bs => nat_of_bools_aux ((( 2:num) * acc) +( 1:num)) bs + | F :: bs => nat_of_bools_aux (( 2:num) * acc) bs +)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn nat_of_bools_aux_defn; +val _ = Define ` + ((nat_of_bools:(bool)list -> num) bs= (nat_of_bools_aux(( 0:num)) bs))`; + + +(*val unsigned_of_bools : list bool -> Num.integer*) +val _ = Define ` + ((unsigned_of_bools:(bool)list -> int) bs= (int_of_num (nat_of_bools bs)))`; + + +(*val signed_of_bools : list bool -> Num.integer*) +val _ = Define ` + ((signed_of_bools:(bool)list -> int) bs= + ((case bs of + T :: _ =>( 0 : int) - (( 1 : int) + (unsigned_of_bools (MAP (\ x. ~ x) bs))) + | F :: _ => unsigned_of_bools bs + | [] =>( 0 : int) (* Treat empty list as all zeros *) + )))`; + + +(*val int_of_bools : bool -> list bool -> Num.integer*) +val _ = Define ` + ((int_of_bools:bool ->(bool)list -> int) sign bs= (if sign then signed_of_bools bs else unsigned_of_bools bs))`; + + +(*val pad_list : forall 'a. 'a -> list 'a -> Num.integer -> list 'a*) + val pad_list_defn = Hol_defn "pad_list" ` + ((pad_list:'a -> 'a list -> int -> 'a list) x xs n= + (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn pad_list_defn; + +val _ = Define ` + ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs= + (let longer = (len - (int_of_num (LENGTH xs))) in + if longer <( 0 : int) then DROP (nat_of_int (ABS (longer))) xs + else pad_list pad xs longer))`; + + +val _ = Define ` + ((extz_bools:int ->(bool)list ->(bool)list) len bs= (ext_list F len bs))`; + +val _ = Define ` + ((exts_bools:int ->(bool)list ->(bool)list) len bs= + ((case bs of + T :: _ => ext_list T len bs + | _ => ext_list F len bs + )))`; + + + val add_one_bool_ignore_overflow_aux_defn = Hol_defn "add_one_bool_ignore_overflow_aux" ` + ((add_one_bool_ignore_overflow_aux:(bool)list ->(bool)list) bits= ((case bits of + [] => [] + | F :: bits => T :: bits + | T :: bits => F :: add_one_bool_ignore_overflow_aux bits +)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn add_one_bool_ignore_overflow_aux_defn; + +val _ = Define ` + ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits= + (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`; + + +(*let bool_list_of_int n = + let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in + if n >= (0 : integer) then bs_abs + else add_one_bool_ignore_overflow (List.map not bs_abs) +let bools_of_int len n = exts_bools len (bool_list_of_int n)*) +val _ = Define ` + ((bools_of_int:int -> int ->(bool)list) len n= + (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in + if n >= (( 0 : int) : int) then bs_abs + else add_one_bool_ignore_overflow (MAP (\ x. ~ x) bs_abs)))`; + + +(*** Bit lists ***) + +(*val has_undefined_bits : list bitU -> bool*) +val _ = Define ` + ((has_undefined_bits:(bitU)list -> bool) bs= (EXISTS (\x . + (case x of BU => T | _ => F )) bs))`; + + +val _ = Define ` + ((bits_of_nat:int -> num ->(bitU)list) len n= (MAP bitU_of_bool (bools_of_nat len n)))`; + + +val _ = Define ` + ((nat_of_bits:(bitU)list ->(num)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of + SOME bs => SOME (nat_of_bools bs) + | NONE => NONE + )))`; + + +val _ = Define ` + ((not_bits:(bitU)list ->(bitU)list)= (MAP not_bit))`; + + +(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*) +val _ = Define ` + ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys= + (FOLDR (\ (x, y) acc . op x y :: acc) [] (list_combine xs ys)))`; + + +val _ = Define ` + ((unsigned_of_bits:(bitU)list ->(int)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of + SOME bs => SOME (unsigned_of_bools bs) + | NONE => NONE + )))`; + + +val _ = Define ` + ((signed_of_bits:(bitU)list ->(int)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of + SOME bs => SOME (signed_of_bools bs) + | NONE => NONE + )))`; + + +(*val int_of_bits : bool -> list bitU -> Maybe.maybe Num.integer*) +val _ = Define ` + ((int_of_bits:bool ->(bitU)list ->(int)option) sign bs= (if sign then signed_of_bits bs else unsigned_of_bits bs))`; + + +val _ = Define ` + ((extz_bits:int ->(bitU)list ->(bitU)list) len bits= (ext_list B0 len bits))`; + +val _ = Define ` + ((exts_bits:int ->(bitU)list ->(bitU)list) len bits= + ((case bits of + BU :: _ => ext_list BU len bits + | B1 :: _ => ext_list B1 len bits + | _ => ext_list B0 len bits + )))`; + + + val add_one_bit_ignore_overflow_aux_defn = Hol_defn "add_one_bit_ignore_overflow_aux" ` + ((add_one_bit_ignore_overflow_aux:(bitU)list ->(bitU)list) bits= ((case bits of + [] => [] + | B0 :: bits => B1 :: bits + | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits + | BU :: bits => BU :: MAP (\b . + (case (b ) of ( _ ) => BU )) bits +)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn add_one_bit_ignore_overflow_aux_defn; + +val _ = Define ` + ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits= + (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`; + + +(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n) +let bits_of_int len n = exts_bits len (bit_list_of_int n)*) +val _ = Define ` + ((bits_of_int:int -> int ->(bitU)list) len n= (MAP bitU_of_bool (bools_of_int len n)))`; + + +(*val arith_op_bits : + (Num.integer -> Num.integer -> Num.integer) -> bool -> list bitU -> list bitU -> list bitU*) +val _ = Define ` + ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r= + ((case (int_of_bits sign l, int_of_bits sign r) of + (SOME li, SOME ri) => bits_of_int (int_of_num (LENGTH l)) (op li ri) + | (_, _) => repeat [BU] (int_of_num (LENGTH l)) + )))`; + + +val _ = Define ` + ((char_of_nibble:bitU#bitU#bitU#bitU ->(char)option)= + (\x . (case x of + (B0, B0, B0, B0) => SOME #"0" + | (B0, B0, B0, B1) => SOME #"1" + | (B0, B0, B1, B0) => SOME #"2" + | (B0, B0, B1, B1) => SOME #"3" + | (B0, B1, B0, B0) => SOME #"4" + | (B0, B1, B0, B1) => SOME #"5" + | (B0, B1, B1, B0) => SOME #"6" + | (B0, B1, B1, B1) => SOME #"7" + | (B1, B0, B0, B0) => SOME #"8" + | (B1, B0, B0, B1) => SOME #"9" + | (B1, B0, B1, B0) => SOME #"A" + | (B1, B0, B1, B1) => SOME #"B" + | (B1, B1, B0, B0) => SOME #"C" + | (B1, B1, B0, B1) => SOME #"D" + | (B1, B1, B1, B0) => SOME #"E" + | (B1, B1, B1, B1) => SOME #"F" + | _ => NONE + )))`; + + + val hexstring_of_bits_defn = Hol_defn "hexstring_of_bits" ` + ((hexstring_of_bits:(bitU)list ->((char)list)option) bs= ((case bs of + b1 :: b2 :: b3 :: b4 :: bs => + let n = (char_of_nibble (b1, b2, b3, b4)) in + let s = (hexstring_of_bits bs) in + (case (n, s) of + (SOME n, SOME s) => SOME (n :: s) + | _ => NONE + ) + | _ => NONE + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn hexstring_of_bits_defn; + +val _ = Define ` + ((show_bitlist:(bitU)list -> string) bs= + ((case hexstring_of_bits bs of + SOME s => IMPLODE (#"0" :: (#"x" :: s)) + | NONE => IMPLODE (#"0" :: (#"b" :: MAP bitU_char bs)) + )))`; + + +(*val subrange_list_inc : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a*) +val _ = Define ` + ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j= + (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in + let (prefix0,fromItoJ) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in + fromItoJ))`; + + +(*val subrange_list_dec : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a*) +val _ = Define ` + ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + subrange_list_inc xs (top - i) (top - j)))`; + + +(*val subrange_list : forall 'a. bool -> list 'a -> Num.integer -> Num.integer -> list 'a*) +val _ = Define ` + ((subrange_list:bool -> 'a list -> int -> int -> 'a list) is_inc xs i j= (if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j))`; + + +(*val update_subrange_list_inc : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +val _ = Define ` + ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= + (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in + let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in +(prefix ++ xs') ++ suffix))`; + + +(*val update_subrange_list_dec : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +val _ = Define ` + ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + update_subrange_list_inc xs (top - i) (top - j) xs'))`; + + +(*val update_subrange_list : forall 'a. bool -> list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +val _ = Define ` + ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'= + (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`; + + +(*val access_list_inc : forall 'a. list 'a -> Num.integer -> 'a*) +val _ = Define ` + ((access_list_inc:'a list -> int -> 'a) xs n= (EL (nat_of_int n) xs))`; + + +(*val access_list_dec : forall 'a. list 'a -> Num.integer -> 'a*) +val _ = Define ` + ((access_list_dec:'a list -> int -> 'a) xs n= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + access_list_inc xs (top - n)))`; + + +(*val access_list : forall 'a. bool -> list 'a -> Num.integer -> 'a*) +val _ = Define ` + ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n= + (if is_inc then access_list_inc xs n else access_list_dec xs n))`; + + +(*val update_list_inc : forall 'a. list 'a -> Num.integer -> 'a -> list 'a*) +val _ = Define ` + ((update_list_inc:'a list -> int -> 'a -> 'a list) xs n x= (LUPDATE x (nat_of_int n) xs))`; + + +(*val update_list_dec : forall 'a. list 'a -> Num.integer -> 'a -> list 'a*) +val _ = Define ` + ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + update_list_inc xs (top - n) x))`; + + +(*val update_list : forall 'a. bool -> list 'a -> Num.integer -> 'a -> list 'a*) +val _ = Define ` + ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x= + (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`; + + +val _ = Define ` + ((extract_only_bit:(bitU)list -> bitU)= + (\x . (case x of [] => BU | [e] => e | _ => BU )))`; + + +(*** Machine words *) + +(*val length_mword : forall 'a. Machine_word.mword 'a -> Num.integer*) + +(*val slice_mword_dec : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((slice_mword_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int j) (nat_of_int i) w))`; + + +(*val slice_mword_inc : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + slice_mword_dec w (top - i) (top - j)))`; + + +(*val slice_mword : forall 'a 'b. bool -> Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +val _ = Define ` + ((slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word) is_inc w i j= (if is_inc then slice_mword_inc w i j else slice_mword_dec w i j))`; + + +(*val update_slice_mword_dec : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +val _ = Define ` + ((update_slice_mword_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int j) (nat_of_int i) w' w))`; + + +(*val update_slice_mword_inc : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +val _ = Define ` + ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + update_slice_mword_dec w (top - i) (top - j) w'))`; + + +(*val update_slice_mword : forall 'a 'b. bool -> Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +val _ = Define ` + ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'= + (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`; + + +(*val access_mword_dec : forall 'a. Machine_word.mword 'a -> Num.integer -> bitU*) +val _ = Define ` + ((access_mword_dec:'a words$word -> int -> bitU) w n= (bitU_of_bool (words$word_bit (nat_of_int n) w)))`; + + +(*val access_mword_inc : forall 'a. Machine_word.mword 'a -> Num.integer -> bitU*) +val _ = Define ` + ((access_mword_inc:'a words$word -> int -> bitU) w n= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + access_mword_dec w (top - n)))`; + + +(*val access_mword : forall 'a. bool -> Machine_word.mword 'a -> Num.integer -> bitU*) +val _ = Define ` + ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n= + (if is_inc then access_mword_inc w n else access_mword_dec w n))`; + + +(*val update_mword_bool_dec : forall 'a. Machine_word.mword 'a -> Num.integer -> bool -> Machine_word.mword 'a*) +val _ = Define ` + ((update_mword_bool_dec:'a words$word -> int -> bool -> 'a words$word) w n b= ($:+ (nat_of_int n) b w))`; + +val _ = Define ` + ((update_mword_dec:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_dec w n) (bool_of_bitU b)))`; + + +(*val update_mword_bool_inc : forall 'a. Machine_word.mword 'a -> Num.integer -> bool -> Machine_word.mword 'a*) +val _ = Define ` + ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + update_mword_bool_dec w (top - n) b))`; + +val _ = Define ` + ((update_mword_inc:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_inc w n) (bool_of_bitU b)))`; + + +(*val int_of_mword : forall 'a. bool -> Machine_word.mword 'a -> Num.integer*) +val _ = Define ` + ((int_of_mword:bool -> 'a words$word -> int) sign w= + (if sign then integer_word$w2i w else lem$w2ui w))`; + + +(* Translating between a type level number (itself 'n) and an integer *) + +val _ = Define ` + ((size_itself_int:'a itself -> int) x= (int_of_num (size_itself x)))`; + + +(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), + the actual integer is ignored. *) + +(*val make_the_value : forall 'n. Num.integer -> Machine_word.itself 'n*) +val _ = Define ` + ((make_the_value:int -> 'n itself) _= the_value)`; + + +(*** Bitvectors *) + +val _ = Hol_datatype ` +(* 'a *) Bitvector_class= <| + bits_of_method : 'a -> bitU list; + (* We allow of_bits to be partial, as not all bitvector representations + support undefined bits *) + of_bits_method : bitU list -> 'a option; + of_bools_method : bool list -> 'a; + length_method : 'a -> int; + (* of_int: the first parameter specifies the desired length of the bitvector *) + of_int_method : int -> int -> 'a; + (* Conversion to integers is undefined if any bit is undefined *) + unsigned_method : 'a -> int option; + signed_method : 'a -> int option; + (* Lifting of integer operations to bitvectors: The boolean flag indicates + whether to treat the bitvectors as signed (true) or not (false). *) + arith_op_bv_method : (int -> int -> int) -> bool -> 'a -> 'a -> 'a +|>`; + + +(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*) +val _ = Define ` + ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail_values_Bitvector_a bits= (maybe_failwith ( + dict_Sail_values_Bitvector_a.of_bits_method bits)))`; + + +val _ = Define ` + ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail_values_Bitvector_a sign= (if sign then + dict_Sail_values_Bitvector_a.signed_method else dict_Sail_values_Bitvector_a.unsigned_method))`; + + +val _ = Define ` +((instance_Sail_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail_values_BitU_a= (<| + + bits_of_method := (\ v. MAP + dict_Sail_values_BitU_a.to_bitU_method v); + + of_bits_method := (\ v. SOME (MAP + dict_Sail_values_BitU_a.of_bitU_method v)); + + of_bools_method := (\ v. MAP + dict_Sail_values_BitU_a.of_bitU_method (MAP bitU_of_bool v)); + + length_method := (\ xs. int_of_num (LENGTH xs)); + + of_int_method := (\ len n. MAP + dict_Sail_values_BitU_a.of_bitU_method (bits_of_int len n)); + + unsigned_method := (\ v. unsigned_of_bits (MAP + dict_Sail_values_BitU_a.to_bitU_method v)); + + signed_method := (\ v. signed_of_bits (MAP + dict_Sail_values_BitU_a.to_bitU_method v)); + + arith_op_bv_method := (\ op sign l r. MAP + dict_Sail_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP + dict_Sail_values_BitU_a.to_bitU_method l) (MAP dict_Sail_values_BitU_a.to_bitU_method r)))|>))`; + + +val _ = Define ` +((instance_Sail_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<| + + bits_of_method := (\ v. MAP bitU_of_bool (bitstring$w2v v)); + + of_bits_method := (\ v. OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU v))); + + of_bools_method := (\ v. bitstring$v2w v); + + length_method := (\ v. int_of_num (words$word_len v)); + + of_int_method := (\i n . + (case (i ,n ) of ( _ , n ) => integer_word$i2w n )); + + unsigned_method := (\ v. SOME (lem$w2ui v)); + + signed_method := (\ v. SOME (integer_word$w2i v)); + + arith_op_bv_method := (\ op sign l r. integer_word$i2w (op (int_of_mword sign l) (int_of_mword sign r)))|>))`; + + +val _ = Define ` + ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n= (access_list T ( + dict_Sail_values_Bitvector_a.bits_of_method v) n))`; + +val _ = Define ` + ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n= (access_list F ( + dict_Sail_values_Bitvector_a.bits_of_method v) n))`; + + +val _ = Define ` + ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b= (update_list T ( + dict_Sail_values_Bitvector_a.bits_of_method v) n b))`; + +val _ = Define ` + ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b= (update_list F ( + dict_Sail_values_Bitvector_a.bits_of_method v) n b))`; + + +val _ = Define ` + ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j= (subrange_list T ( + dict_Sail_values_Bitvector_a.bits_of_method v) i j))`; + +val _ = Define ` + ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j= (subrange_list F ( + dict_Sail_values_Bitvector_a.bits_of_method v) i j))`; + + +val _ = Define ` + ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'= (update_subrange_list T ( + dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`; + +val _ = Define ` + ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'= (update_subrange_list F ( + dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`; + + +(*val extz_bv : forall 'a. Bitvector 'a => Num.integer -> 'a -> list bitU*) +val _ = Define ` + ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (extz_bits n ( + dict_Sail_values_Bitvector_a.bits_of_method v)))`; + + +(*val exts_bv : forall 'a. Bitvector 'a => Num.integer -> 'a -> list bitU*) +val _ = Define ` + ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (exts_bits n ( + dict_Sail_values_Bitvector_a.bits_of_method v)))`; + + +(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*) +val _ = Define ` + ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a v= (show_bitlist ( + dict_Sail_values_Bitvector_a.bits_of_method v)))`; + + +(*** Bytes and addresses *) + +val _ = type_abbrev( "memory_byte" , ``: bitU list``); + +(*val byte_chunks : forall 'a. list 'a -> Maybe.maybe (list (list 'a))*) + val byte_chunks_defn = Hol_defn "byte_chunks" ` + ((byte_chunks:'a list ->(('a list)list)option) bs= ((case bs of + [] => SOME [] + | a::b::c::d::e::f::g::h::rest => + OPTION_BIND (byte_chunks rest) (\ rest . SOME ([a;b;c;d;e;f;g;h] :: rest)) + | _ => NONE +)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn byte_chunks_defn; + +(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> Maybe.maybe (list memory_byte)*) +val _ = Define ` + ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail_values_Bitvector_a bs= (byte_chunks ( + dict_Sail_values_Bitvector_a.bits_of_method bs)))`; + + +(*val bits_of_bytes : list memory_byte -> list bitU*) +val _ = Define ` + ((bits_of_bytes:((bitU)list)list ->(bitU)list) bs= (FLAT (MAP (\ v. MAP (\ b. b) v) bs)))`; + + +val _ = Define ` + ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail_values_Bitvector_a bs= (OPTION_MAP REVERSE (bytes_of_bits + dict_Sail_values_Bitvector_a bs)))`; + +val _ = Define ` + ((bits_of_mem_bytes:((bitU)list)list ->(bitU)list) bs= (bits_of_bytes (REVERSE bs)))`; + + +(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU +let bitv_of_byte_lifteds v = + foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v + +val bitv_of_bytes : list Sail_impl_base.byte -> list bitU +let bitv_of_bytes v = + foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v + +val byte_lifteds_of_bitv : list bitU -> list byte_lifted +let byte_lifteds_of_bitv bits = + let bits = List.map bit_lifted_of_bitU bits in + byte_lifteds_of_bit_lifteds bits + +val bytes_of_bitv : list bitU -> list byte +let bytes_of_bitv bits = + let bits = List.map bit_of_bitU bits in + bytes_of_bits bits + +val bit_lifteds_of_bitUs : list bitU -> list bit_lifted +let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits + +val bit_lifteds_of_bitv : list bitU -> list bit_lifted +let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v + + +val address_lifted_of_bitv : list bitU -> address_lifted +let address_lifted_of_bitv v = + let byte_lifteds = byte_lifteds_of_bitv v in + let maybe_address_integer = + match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with + | Just bs -> Just (integer_of_byte_list bs) + | _ -> Nothing + end in + Address_lifted byte_lifteds maybe_address_integer + +val bitv_of_address_lifted : address_lifted -> list bitU +let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs + +val address_of_bitv : list bitU -> address +let address_of_bitv v = + let bytes = bytes_of_bitv v in + address_of_byte_list bytes*) + + val reverse_endianness_list_defn = Hol_defn "reverse_endianness_list" ` + ((reverse_endianness_list:'a list -> 'a list) bits= + (if LENGTH bits <=( 8 : num) then bits else + reverse_endianness_list (drop_list(( 8 : int)) bits) ++ take_list(( 8 : int)) bits))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn reverse_endianness_list_defn; + + +(*** Registers *) + +(*type register_field = string +type register_field_index = string * (integer * integer) (* name, start and end *) + +type register = + | Register of string * (* name *) + integer * (* length *) + integer * (* start index *) + bool * (* is increasing *) + list register_field_index + | UndefinedRegister of integer (* length *) + | RegisterPair of register * register*) + +val _ = Hol_datatype ` +(* ( 'a_regstate, 'b_regval, 'c_a) *) register_ref = + <| name : string; + (*is_inc : bool;*) + read_from :'a_regstate -> 'c_a; + write_to :'c_a -> 'a_regstate -> 'a_regstate; + of_regval :'b_regval -> 'c_a option; + regval_of :'c_a -> 'b_regval |>`; + + +(* Register accessors: pair of functions for reading and writing register values *) +val _ = type_abbrev((* ( 'regstate, 'regval) *) "register_accessors" , ``: + ((string -> 'regstate -> 'regval option) # + (string -> 'regval -> 'regstate -> 'regstate option))``); + +val _ = Hol_datatype ` +(* ( 'a_regtype, 'b_a) *) field_ref = + <| field_name : string; + field_start : int; + field_is_inc : bool; + get_field :'a_regtype -> 'b_a; + set_field :'a_regtype -> 'b_a -> 'a_regtype |>`; + + +(*let name_of_reg = function + | Register name _ _ _ _ -> name + | UndefinedRegister _ -> failwith "name_of_reg UndefinedRegister" + | RegisterPair _ _ -> failwith "name_of_reg RegisterPair" +end + +let size_of_reg = function + | Register _ size _ _ _ -> size + | UndefinedRegister size -> size + | RegisterPair _ _ -> failwith "size_of_reg RegisterPair" +end + +let start_of_reg = function + | Register _ _ start _ _ -> start + | UndefinedRegister _ -> failwith "start_of_reg UndefinedRegister" + | RegisterPair _ _ -> failwith "start_of_reg RegisterPair" +end + +let is_inc_of_reg = function + | Register _ _ _ is_inc _ -> is_inc + | UndefinedRegister _ -> failwith "is_inc_of_reg UndefinedRegister" + | RegisterPair _ _ -> failwith "in_inc_of_reg RegisterPair" +end + +let dir_of_reg = function + | Register _ _ _ is_inc _ -> dir_of_bool is_inc + | UndefinedRegister _ -> failwith "dir_of_reg UndefinedRegister" + | RegisterPair _ _ -> failwith "dir_of_reg RegisterPair" +end + +let size_of_reg_nat reg = natFromInteger (size_of_reg reg) +let start_of_reg_nat reg = natFromInteger (start_of_reg reg) + +val register_field_indices_aux : register -> register_field -> maybe (integer * integer) +let rec register_field_indices_aux register rfield = + match register with + | Register _ _ _ _ rfields -> List.lookup rfield rfields + | RegisterPair r1 r2 -> + let m_indices = register_field_indices_aux r1 rfield in + if isJust m_indices then m_indices else register_field_indices_aux r2 rfield + | UndefinedRegister _ -> Nothing + end + +val register_field_indices : register -> register_field -> integer * integer +let register_field_indices register rfield = + match register_field_indices_aux register rfield with + | Just indices -> indices + | Nothing -> failwith "Invalid register/register-field combination" + end + +let register_field_indices_nat reg regfield= + let (i,j) = register_field_indices reg regfield in + (natFromInteger i,natFromInteger j)*) + +(*let rec external_reg_value reg_name v = + let (internal_start, external_start, direction) = + match reg_name with + | Reg _ start size dir -> + (start, (if dir = D_increasing then start else (start - (size +1))), dir) + | Reg_slice _ reg_start dir (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_field _ reg_start dir _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_f_slice _ reg_start dir _ _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + end in + let bits = bit_lifteds_of_bitv v in + <| rv_bits = bits; + rv_dir = direction; + rv_start = external_start; + rv_start_internal = internal_start |> + +val internal_reg_value : register_value -> list bitU +let internal_reg_value v = + List.map bitU_of_bit_lifted v.rv_bits + (*(integerFromNat v.rv_start_internal) + (v.rv_dir = D_increasing)*) + + +let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) = + match d with + (*This is the case the thread/concurrecny model expects, so no change needed*) + | D_increasing -> (i,j) + | D_decreasing -> let slice_i = start - i in + let slice_j = (i - j) + slice_i in + (slice_i,slice_j) + end *) + +(* TODO +let external_reg_whole r = + Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc) + +let external_reg_slice r (i,j) = + let start = natFromInteger r.start in + let dir = dir_of_bool r.is_inc in + Reg_slice (r.name) start dir (external_slice dir start (i,j)) + +let external_reg_field_whole reg rfield = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n)) + +let external_reg_field_slice reg rfield (i,j) = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_f_slice (name_of_reg reg) start dir rfield + (external_slice dir start (m,n)) + (external_slice dir start (i,j))*) + +(*val external_mem_value : list bitU -> memory_value +let external_mem_value v = + byte_lifteds_of_bitv v $> List.reverse + +val internal_mem_value : memory_value -> list bitU +let internal_mem_value bytes = + List.reverse bytes $> bitv_of_byte_lifteds*) + + +(*val foreach : forall 'a 'vars. + (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*) + val foreach_defn = Hol_defn "foreach" ` + ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body= + ((case l of + [] => vars + | (x :: xs) => foreach xs (body x vars) body + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreach_defn; + +(*val index_list : Num.integer -> Num.integer -> Num.integer -> list Num.integer*) + val index_list_defn = Hol_defn "index_list" ` + ((index_list:int -> int -> int ->(int)list) from to step= + (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then + from :: index_list (from + step) to step + else []))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn index_list_defn; + +(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) + val while_defn = Hol_defn "while" ` + ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= + (if cond vars then while (body vars) cond body else vars))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn while_defn; + +(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) + val until_defn = Hol_defn "until" ` + ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= + (let vars = (body vars) in + if cond vars then vars else until (body vars) cond body))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn until_defn; + + +(* convert numbers unsafely to naturals *) + +val _ = Hol_datatype ` +(* 'a *) ToNatural_class= <| toNatural_method : 'a -> num |>`; + +(* eta-expanded for Isabelle output, otherwise it breaks *) +val _ = Define ` +((instance_Sail_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<| + + toNatural_method := (\ n . Num (ABS n))|>))`; + +val _ = Define ` +((instance_Sail_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<| + + toNatural_method := (\ n . ((Num (ABS n)):num))|>))`; + +val _ = Define ` +((instance_Sail_values_ToNatural_nat_dict:(num)ToNatural_class)= (<| + + toNatural_method := (\ n . ( n:num))|>))`; + +val _ = Define ` +((instance_Sail_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<| + + toNatural_method := (\ n . n)|>))`; + + +val _ = Define ` + ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5)= + (dict_Sail_values_ToNatural_d.toNatural_method n1, dict_Sail_values_ToNatural_c.toNatural_method n2, dict_Sail_values_ToNatural_b.toNatural_method n3, dict_Sail_values_ToNatural_a.toNatural_method n4, dict_Sail_values_ToNatural_e.toNatural_method n5))`; + + +(* Let the following types be generated by Sail per spec, using either bitlists + or machine words as bitvector representation *) +(*type regfp = + | RFull of (string) + | RSlice of (string * integer * integer) + | RSliceBit of (string * integer) + | RField of (string * string) + +type niafp = + | NIAFP_successor + | NIAFP_concrete_address of vector bitU + | NIAFP_indirect_address + +(* only for MIPS *) +type diafp = + | DIAFP_none + | DIAFP_concrete of vector bitU + | DIAFP_reg of regfp + +let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function + | RFull name -> + let (start,length,direction,_) = reg_info name Nothing in + Reg name start length direction + | RSlice (name,i,j) -> + let i = natFromInteger i in + let j = natFromInteger j in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,j) in + Reg_slice name start direction slice + | RSliceBit (name,i) -> + let i = natFromInteger i in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,i) in + Reg_slice name start direction slice + | RField (name,field_name) -> + let (start,length,direction,span) = reg_info name (Just field_name) in + let slice = external_slice direction start span in + Reg_field name start direction field_name slice +end + +let niafp_to_nia reginfo = function + | NIAFP_successor -> NIA_successor + | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v) + | NIAFP_indirect_address -> NIA_indirect_address +end + +let diafp_to_dia reginfo = function + | DIAFP_none -> DIA_none + | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v) + | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r) +end +*) +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/stateScript.sml b/snapshots/hol4/sail/lib/hol/stateScript.sml new file mode 100644 index 00000000..0eb048a0 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/stateScript.sml @@ -0,0 +1,119 @@ +(*Generated by Lem from ../../src/gen_lib/state.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "state" + +(*open import Pervasives_extra*) +(*open import Sail_values*) +(*open import State_monad*) +(*open import {isabelle} `State_monad_lemmas`*) + +(*val iterS_aux : forall 'rv 'a 'e. Num.integer -> (Num.integer -> 'a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) + val iterS_aux_defn = Hol_defn "iterS_aux" ` + ((iterS_aux:int ->(int -> 'a -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) i f xs= ((case xs of + x :: xs => seqS (f i x) (iterS_aux (i +( 1 : int)) f xs) + | [] => returnS () + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn iterS_aux_defn; + +(*val iteriS : forall 'rv 'a 'e. (Num.integer -> 'a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) +val _ = Define ` + ((iteriS:(int -> 'a ->('rv,(unit),'e)state_monad$monadS) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) f xs= (iterS_aux(( 0 : int)) f xs))`; + + +(*val iterS : forall 'rv 'a 'e. ('a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) +val _ = Define ` + ((iterS:('a -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) f xs= (iteriS (\i x . + (case (i ,x ) of ( _ , x ) => f x )) xs))`; + + +(*val foreachS : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) + val foreachS_defn = Hol_defn "foreachS" ` + ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) xs vars body= ((case xs of + [] => returnS vars + | x :: xs => bindS +(body x vars) (\ vars . + foreachS xs vars body) +)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreachS_defn; + +(*val bool_of_bitU_fail : forall 'rv 'e. Sail_values.bitU -> State_monad.monadS 'rv bool 'e*) +val _ = Define ` + ((bool_of_bitU_fail:sail_values$bitU -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set)= + (\x . (case x of + B0 => returnS F + | B1 => returnS T + | BU => failS "bool_of_bitU" + )))`; + + +(*val bool_of_bitU_oracleS : forall 'rv 'e. Sail_values.bitU -> State_monad.monadS 'rv bool 'e*) +val _ = Define ` + ((bool_of_bitU_oracleS:sail_values$bitU -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set)= + (\x . (case x of + B0 => returnS F + | B1 => returnS T + | BU => undefined_boolS () + )))`; + + +(*val bools_of_bits_oracleS : forall 'rv 'e. list Sail_values.bitU -> State_monad.monadS 'rv (list bool) 'e*) +val _ = Define ` + ((bools_of_bits_oracleS:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((bool)list),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= + (foreachS bits [] + (\ b bools . bindS +(bool_of_bitU_oracleS b) (\ b . + returnS (bools ++ [b])))))`; + + +(*val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list Sail_values.bitU -> State_monad.monadS 'rv 'a 'e*) +val _ = Define ` + ((of_bits_oracleS:'a sail_values$Bitvector_class ->(sail_values$bitU)list ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a bits= (bindS +(bools_of_bits_oracleS bits) (\ bs . + returnS (dict_Sail_values_Bitvector_a.of_bools_method bs))))`; + + +(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list Sail_values.bitU -> State_monad.monadS 'rv 'a 'e*) +val _ = Define ` + ((of_bits_failS:'a sail_values$Bitvector_class ->(sail_values$bitU)list ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a bits= (maybe_failS "of_bits" ( + dict_Sail_values_Bitvector_a.of_bits_method bits)))`; + + +(*val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> State_monad.monadS 'rv (Machine_word.mword 'a) 'e*) +val _ = Define ` + ((mword_oracleS:unit -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) () = (bindS +(bools_of_bits_oracleS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . + returnS (bitstring$v2w bs))))`; + + + +(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> State_monad.monadS 'rv bool 'e) -> + ('vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) + val whileS_defn = Hol_defn "whileS" ` + ((whileS:'vars ->('vars -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set) ->('vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) vars cond body s= + (( bindS(cond vars) (\ cond_val s' . + if cond_val then + ( bindS(body vars) (\ vars s'' . whileS vars cond body s'')) s' + else returnS vars s')) s))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn whileS_defn; + +(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> State_monad.monadS 'rv bool 'e) -> + ('vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) + val untilS_defn = Hol_defn "untilS" ` + ((untilS:'vars ->('vars -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set) ->('vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) vars cond body s= + (( bindS(body vars) (\ vars s' . + ( bindS(cond vars) (\ cond_val s'' . + if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn untilS_defn; +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/state_monadScript.sml b/snapshots/hol4/sail/lib/hol/state_monadScript.sml new file mode 100644 index 00000000..cf4764c0 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/state_monadScript.sml @@ -0,0 +1,348 @@ +(*Generated by Lem from ../../src/gen_lib/state_monad.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "state_monad" + +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) + +(* 'a is result type *) + +val _ = type_abbrev( "memstate" , ``: (int, sail_values$memory_byte) fmap``); +val _ = type_abbrev( "tagstate" , ``: (int, sail_values$bitU) fmap``); +(* type regstate = map string (vector bitU) *) + +val _ = Hol_datatype ` +(* 'regs *) sequential_state = + <| regstate : 'regs; + memstate : memstate; + tagstate : tagstate; + write_ea : (sail_instr_kinds$write_kind # int # int)option; + last_exclusive_operation_was_load : bool; + (* Random bool generator for use as an undefined bit oracle *) + next_bool : num -> (bool # num); + seed : num |>`; + + +(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) +val _ = Define ` + ((init_state:'regs ->(num -> bool#num) -> num -> 'regs sequential_state) regs o1 s= + (<| regstate := regs; + memstate := FEMPTY; + tagstate := FEMPTY; + write_ea := NONE; + last_exclusive_operation_was_load := F; + next_bool := o1; + seed := s |>))`; + + +val _ = Hol_datatype ` + ex = + Failure of string + | Throw of 'e`; + + +val _ = Hol_datatype ` + result = + Value of 'a + | Ex of ( 'e ex)`; + + +(* State, nondeterminism and exception monad with result value type 'a + and exception type 'e. *) +val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_e) *) "monadS" , ``:'a_regs sequential_state -> (('b_a,'c_e)result #'a_regs sequential_state) set``); + +(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*) +val _ = Define ` + ((returnS:'a -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) a s= ({(Value a,s)}))`; + + +(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*) +val _ = Define ` + ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)= + (BIGUNION (IMAGE (\x . + (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s))))`; + + +(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*) +val _ = Define ` + ((seqS:('regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) ->('regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m n= (bindS m (\u . + (case (u ) of ( (_ : unit) ) => n ))))`; + + +(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*) +val _ = Define ` + ((chooseS:'a set -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) xs s= (IMAGE (\ x . (Value x, s)) xs))`; + + +(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*) +val _ = Define ` + ((readS:('regs sequential_state -> 'a) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) f= (\ s . returnS (f s) s))`; + + +(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*) +val _ = Define ` + ((updateS:('regs sequential_state -> 'regs sequential_state) -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) f= (\ s . returnS () (f s)))`; + + +(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*) +val _ = Define ` + ((failS:string -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg s= ({(Ex (Failure msg), s)}))`; + + +(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) +val _ = Define ` + ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS +(readS (\ s . s.next_bool (s.seed))) (\ (b, seed) . seqS +(updateS (\ s . ( s with<| seed := seed |>))) +(returnS b))))`; + + +(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) +val _ = Define ` + ((exitS:unit -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) () = (failS "exit"))`; + + +(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*) +val _ = Define ` + ((throwS:'e -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) e s= ({(Ex (Throw e), s)}))`; + + +(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*) +val _ = Define ` + ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s= + (BIGUNION (IMAGE (\x . + (case x of + (Value a, s') => returnS a s' + | (Ex (Throw e), s') => h e s' + | (Ex (Failure msg), s') => {(Ex (Failure msg), s')} + )) (m s))))`; + + +(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*) +val _ = Define ` + ((assert_expS:bool -> string -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) exp msg= (if exp then returnS () else failS msg))`; + + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is "either 'r 'e", where "Right e" + represents a proper exception and "Left r" an early return of value "r". *) +val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_r, 'd_e) *) "monadRS" , ``:('a_regs,'b_a, (('c_r,'d_e)sum)) monadS``); + +(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*) +val _ = Define ` + ((early_returnS:'r -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) r= (throwS (INL r)))`; + + +(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) +val _ = Define ` + ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m= + (try_catchS m + (\x . (case x of INL a => returnS a | INR e => throwS e ))))`; + + +(* Lift to monad with early return by wrapping exceptions *) +(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*) +val _ = Define ` + ((liftRS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) m= (try_catchS m (\ e . throwS (INR e))))`; + + +(* Catch exceptions in the presence of early returns *) +(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2*) +val _ = Define ` + ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h= + (try_catchS m + (\x . (case x of INL r => throwS (INL r) | INR e => h e ))))`; + + +(*val maybe_failS : forall 'regs 'a 'e. string -> Maybe.maybe 'a -> monadS 'regs 'a 'e*) +val _ = Define ` + ((maybe_failS:string -> 'a option -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg= + (\x . (case x of SOME a => returnS a | NONE => failS msg )))`; + + +(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs Sail_values.bitU 'e*) +val _ = Define ` + ((read_tagS:'a sail_values$Bitvector_class -> 'a ->('regs,(sail_values$bitU),'e)monadS)dict_Sail_values_Bitvector_a addr= (bindS +(maybe_failS "unsigned" ( + dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + readS (\ s . option_CASE (FLOOKUP s.tagstate addr) B0 I))))`; + + +(* Read bytes from memory and return in little endian order *) +(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => Sail_instr_kinds.read_kind -> 'a -> nat -> monadS 'regs (list Sail_values.memory_byte) 'e*) +val _ = Define ` + ((read_mem_bytesS:'a sail_values$Bitvector_class -> sail_instr_kinds$read_kind -> 'a -> num ->('regs,((sail_values$memory_byte)list),'e)monadS)dict_Sail_values_Bitvector_a read_kind addr sz= (bindS +(maybe_failS "unsigned" ( + dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + let sz = (int_of_num sz) in + let addrs = (index_list addr ((addr+sz)-( 1 : int))(( 1 : int))) in + let read_byte = (\ s addr . FLOOKUP s.memstate addr) in + bindS (readS (\ s . just_list (MAP (read_byte s) addrs))) + (\x . (case x of + SOME mem_val => seqS + (updateS + (\ s . + if read_is_exclusive read_kind then + ( s with<| last_exclusive_operation_was_load := T |>) + else s)) (returnS mem_val) + | NONE => failS "read_memS" + )))))`; + + +(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => Sail_instr_kinds.read_kind -> 'a -> Num.integer -> monadS 'regs 'b 'e*) +val _ = Define ` + ((read_memS:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> sail_instr_kinds$read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz= (bindS +(read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . + maybe_failS "bits_of_mem_bytes" ( + dict_Sail_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`; + + +(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) +val _ = Define ` + ((excl_resultS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS +(readS (\ s . s.last_exclusive_operation_was_load)) (\ excl_load . seqS +(updateS (\ s . ( s with<| last_exclusive_operation_was_load := F |>))) +(chooseS (if excl_load then {F; T} else {F})))))`; + + +(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => Sail_instr_kinds.write_kind -> 'a -> nat -> monadS 'regs unit 'e*) +val _ = Define ` + ((write_mem_eaS:'a sail_values$Bitvector_class -> sail_instr_kinds$write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail_values_Bitvector_a write_kind addr sz= (bindS +(maybe_failS "unsigned" ( + dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + let sz = (int_of_num sz) in + updateS (\ s . ( s with<| write_ea := (SOME (write_kind, addr, sz)) |>)))))`; + + +(* Write little-endian list of bytes to previously announced address *) +(*val write_mem_bytesS : forall 'regs 'e. list Sail_values.memory_byte -> monadS 'regs bool 'e*) +val _ = Define ` + ((write_mem_bytesS:((sail_values$bitU)list)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) v= (bindS +(readS (\ s . s.write_ea)) (\x . + (case x of + NONE => failS "write ea has not been announced yet" + | SOME (_, addr, sz) => + let addrs = (index_list addr ((addr + sz) - ( 1 : int)) (( 1 : int))) in + (*let v = external_mem_value (bits_of v) in*) + let a_v = (lem_list$list_combine addrs v) in + let write_byte = (\mem p . (case (mem ,p ) of + ( mem , (addr, v) ) => mem |+ ( addr , + v ) + )) in + seqS + (updateS + (\ s . ( s with<| memstate := (FOLDL write_byte s.memstate a_v) |>))) + (returnS T) + ))))`; + + +(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) +val _ = Define ` + ((write_mem_valS:'a sail_values$Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a v= ((case mem_bytes_of_bits + dict_Sail_values_Bitvector_a v of + SOME v => write_mem_bytesS v + | NONE => failS "write_mem_val" +)))`; + + +(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> Sail_values.bitU -> monadS 'regs bool 'e*) +val _ = Define ` + ((write_tagS:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a addr t= (bindS +(maybe_failS "unsigned" ( + dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . seqS +(updateS (\ s . ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>))) +(returnS T))))`; + + +(*val read_regS : forall 'regs 'rv 'a 'e. Sail_values.register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*) +val _ = Define ` + ((read_regS:('regs,'rv,'a)sail_values$register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg= (readS (\ s . reg.read_from s.regstate)))`; + + +(* TODO +let read_reg_range reg i j state = + let v = slice (get_reg state (name_of_reg reg)) i j in + [(Value (vec_to_bvec v),state)] +let read_reg_bit reg i state = + let v = access (get_reg state (name_of_reg reg)) i in + [(Value v,state)] +let read_reg_field reg regfield = + let (i,j) = register_field_indices reg regfield in + read_reg_range reg i j +let read_reg_bitfield reg regfield = + let (i,_) = register_field_indices reg regfield in + read_reg_bit reg i *) + +(*val read_regvalS : forall 'regs 'rv 'e. + Sail_values.register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*) +val _ = Define ` + ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg= (bindS +(readS (\ s . read reg s.regstate)) (\x . + (case x of + SOME v => returnS v + | NONE => failS ( STRCAT "read_regvalS " reg) + ))))`; + + +(*val write_regvalS : forall 'regs 'rv 'e. + Sail_values.register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*) +val _ = Define ` + ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v= (bindS +(readS (\ s . write reg v s.regstate)) (\x . + (case x of + SOME rs' => updateS (\ s . ( s with<| regstate := rs' |>)) + | NONE => failS ( STRCAT "write_regvalS " reg) + ))))`; + + +(*val write_regS : forall 'regs 'rv 'a 'e. Sail_values.register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*) +val _ = Define ` + ((write_regS:('regs,'rv,'a)sail_values$register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v= + (updateS (\ s . ( s with<| regstate := (reg.write_to v s.regstate) |>))))`; + + +(* TODO +val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e +let update_reg reg f v state = + let current_value = get_reg state reg in + let new_value = f current_value v in + [(Value (), set_reg state reg new_value)] + +let write_reg_field reg regfield = update_reg reg regfield.set_field + +val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a +let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val) +let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) + +let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x +let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) + +let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit) +let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) + +let update_reg_field_range regfield i j reg_val new_val = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in + regfield.set_field reg_val new_field_value +let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) + +let update_reg_field_pos regfield i reg_val x = + let current_field_value = regfield.get_field reg_val in + let new_field_value = update_list regfield.field_is_inc current_field_value i x in + regfield.set_field reg_val new_field_value +let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) + +let update_reg_field_bit regfield i reg_val bit = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in + regfield.set_field reg_val new_field_value +let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*) +val _ = export_theory() + -- cgit v1.2.3 From 14bc7fd8d631196e7f0e9ab882d30c88c764336a Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Mon, 14 May 2018 13:31:34 +0100 Subject: Ignore built files in HOL4 snapshot --- snapshots/hol4/.gitignore | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 snapshots/hol4/.gitignore diff --git a/snapshots/hol4/.gitignore b/snapshots/hol4/.gitignore new file mode 100644 index 00000000..462135be --- /dev/null +++ b/snapshots/hol4/.gitignore @@ -0,0 +1,9 @@ +*.uo +*.ui +*.dat +*Theory.sml +*Theory.sig +.HOLMK +.hollogs +lem/hol-lib/lemheap +sail/lib/hol/sail-heap -- cgit v1.2.3 From 1af099d46188cacd115639ec6d465ca8163ae07f Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 14 May 2018 15:38:02 +0100 Subject: import new build of riscv tests including some new ones that are expected to pass. --- test/riscv/tests/README | 2 +- test/riscv/tests/disabled/rv64mi-p-sbreak.dump | 130 + test/riscv/tests/disabled/rv64si-p-sbreak.dump | 128 + test/riscv/tests/disabled/rv64ua-p-lrsc.elf | Bin 13576 -> 14632 bytes test/riscv/tests/rv64mi-p-access.dump | 142 + test/riscv/tests/rv64mi-p-breakpoint.dump | 207 + test/riscv/tests/rv64mi-p-breakpoint.elf | Bin 0 -> 13488 bytes test/riscv/tests/rv64mi-p-csr.dump | 287 ++ test/riscv/tests/rv64mi-p-csr.elf | Bin 0 -> 13936 bytes test/riscv/tests/rv64mi-p-illegal.dump | 383 ++ test/riscv/tests/rv64mi-p-illegal.elf | Bin 0 -> 9648 bytes test/riscv/tests/rv64mi-p-ma_addr.dump | 563 ++ test/riscv/tests/rv64mi-p-ma_addr.elf | Bin 0 -> 13712 bytes test/riscv/tests/rv64mi-p-ma_fetch.dump | 219 + test/riscv/tests/rv64mi-p-ma_fetch.elf | Bin 0 -> 9296 bytes test/riscv/tests/rv64mi-p-mcsr.dump | 126 + test/riscv/tests/rv64mi-p-mcsr.elf | Bin 0 -> 9320 bytes test/riscv/tests/rv64mi-p-scall.dump | 147 + test/riscv/tests/rv64mi-p-scall.elf | Bin 0 -> 9328 bytes test/riscv/tests/rv64si-p-csr.dump | 222 + test/riscv/tests/rv64si-p-csr.elf | Bin 0 -> 13840 bytes test/riscv/tests/rv64si-p-dirty.dump | 202 + test/riscv/tests/rv64si-p-dirty.elf | Bin 0 -> 13552 bytes test/riscv/tests/rv64si-p-ma_fetch.dump | 175 + test/riscv/tests/rv64si-p-ma_fetch.elf | Bin 0 -> 9296 bytes test/riscv/tests/rv64si-p-scall.dump | 121 + test/riscv/tests/rv64si-p-scall.elf | Bin 0 -> 9328 bytes test/riscv/tests/rv64si-p-wfi.dump | 128 + test/riscv/tests/rv64si-p-wfi.elf | Bin 0 -> 9256 bytes test/riscv/tests/rv64ua-p-amoadd_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoadd_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoand_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoand_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomax_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomax_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomaxu_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomaxu_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomin_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amomin_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amominu_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amominu_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoor_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoor_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoswap_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoswap_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoxor_d.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-amoxor_w.elf | Bin 9504 -> 9504 bytes test/riscv/tests/rv64ua-p-lrsc.dump | 691 +++ test/riscv/tests/rv64ua-v-amoadd_d.dump | 874 ++++ test/riscv/tests/rv64ua-v-amoadd_d.elf | Bin 0 -> 17912 bytes test/riscv/tests/rv64ua-v-amoadd_w.dump | 871 ++++ test/riscv/tests/rv64ua-v-amoadd_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amoand_d.dump | 871 ++++ test/riscv/tests/rv64ua-v-amoand_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amoand_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amoand_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomax_d.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomax_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomax_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomax_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomaxu_d.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomaxu_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomaxu_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomaxu_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomin_d.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomin_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amomin_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amomin_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amominu_d.dump | 870 ++++ test/riscv/tests/rv64ua-v-amominu_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amominu_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amominu_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amoor_d.dump | 869 ++++ test/riscv/tests/rv64ua-v-amoor_d.elf | Bin 0 -> 17888 bytes test/riscv/tests/rv64ua-v-amoor_w.dump | 869 ++++ test/riscv/tests/rv64ua-v-amoor_w.elf | Bin 0 -> 17888 bytes test/riscv/tests/rv64ua-v-amoswap_d.dump | 871 ++++ test/riscv/tests/rv64ua-v-amoswap_d.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amoswap_w.dump | 870 ++++ test/riscv/tests/rv64ua-v-amoswap_w.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ua-v-amoxor_d.dump | 872 ++++ test/riscv/tests/rv64ua-v-amoxor_d.elf | Bin 0 -> 17904 bytes test/riscv/tests/rv64ua-v-amoxor_w.dump | 874 ++++ test/riscv/tests/rv64ua-v-amoxor_w.elf | Bin 0 -> 17912 bytes test/riscv/tests/rv64ua-v-lrsc.dump | 1426 ++++++ test/riscv/tests/rv64uc-p-rvc.elf | Bin 18392 -> 18392 bytes test/riscv/tests/rv64uc-v-rvc.dump | 6518 ++++++++++++++++++++++++ test/riscv/tests/rv64uc-v-rvc.elf | Bin 0 -> 32128 bytes test/riscv/tests/rv64ui-p-add.elf | Bin 10432 -> 10432 bytes test/riscv/tests/rv64ui-p-addi.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-addiw.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-addw.elf | Bin 10432 -> 10432 bytes test/riscv/tests/rv64ui-p-and.elf | Bin 10080 -> 10080 bytes test/riscv/tests/rv64ui-p-andi.elf | Bin 9664 -> 9664 bytes test/riscv/tests/rv64ui-p-auipc.elf | Bin 9320 -> 9320 bytes test/riscv/tests/rv64ui-p-beq.elf | Bin 9888 -> 9888 bytes test/riscv/tests/rv64ui-p-bge.elf | Bin 9984 -> 9984 bytes test/riscv/tests/rv64ui-p-bgeu.elf | Bin 9984 -> 9984 bytes test/riscv/tests/rv64ui-p-blt.elf | Bin 9888 -> 9888 bytes test/riscv/tests/rv64ui-p-bltu.elf | Bin 9888 -> 9888 bytes test/riscv/tests/rv64ui-p-bne.elf | Bin 9888 -> 9888 bytes test/riscv/tests/rv64ui-p-fence_i.elf | Bin 13480 -> 13480 bytes test/riscv/tests/rv64ui-p-jal.elf | Bin 9384 -> 9384 bytes test/riscv/tests/rv64ui-p-jalr.elf | Bin 9480 -> 9480 bytes test/riscv/tests/rv64ui-p-lb.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-lbu.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-ld.elf | Bin 14120 -> 14120 bytes test/riscv/tests/rv64ui-p-lh.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-lhu.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-lui.elf | Bin 9408 -> 9408 bytes test/riscv/tests/rv64ui-p-lw.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-lwu.elf | Bin 14104 -> 14104 bytes test/riscv/tests/rv64ui-p-or.elf | Bin 10080 -> 10080 bytes test/riscv/tests/rv64ui-p-ori.elf | Bin 9664 -> 9664 bytes test/riscv/tests/rv64ui-p-sb.elf | Bin 14416 -> 14416 bytes test/riscv/tests/rv64ui-p-sd.elf | Bin 14480 -> 14480 bytes test/riscv/tests/rv64ui-p-sh.elf | Bin 14432 -> 14432 bytes test/riscv/tests/rv64ui-p-simple.elf | Bin 9200 -> 9200 bytes test/riscv/tests/rv64ui-p-sll.elf | Bin 10688 -> 10688 bytes test/riscv/tests/rv64ui-p-slli.dump | 305 +- test/riscv/tests/rv64ui-p-slli.elf | Bin 10112 -> 10112 bytes test/riscv/tests/rv64ui-p-slliw.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-sllw.elf | Bin 10592 -> 10592 bytes test/riscv/tests/rv64ui-p-slt.elf | Bin 10432 -> 10432 bytes test/riscv/tests/rv64ui-p-slti.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-sltiu.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-sltu.elf | Bin 10432 -> 10432 bytes test/riscv/tests/rv64ui-p-sra.elf | Bin 10592 -> 10592 bytes test/riscv/tests/rv64ui-p-srai.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-sraiw.elf | Bin 10080 -> 10080 bytes test/riscv/tests/rv64ui-p-sraw.elf | Bin 10592 -> 10592 bytes test/riscv/tests/rv64ui-p-srl.elf | Bin 10592 -> 10592 bytes test/riscv/tests/rv64ui-p-srli.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-srliw.elf | Bin 10016 -> 10016 bytes test/riscv/tests/rv64ui-p-srlw.elf | Bin 10592 -> 10592 bytes test/riscv/tests/rv64ui-p-sub.elf | Bin 10400 -> 10400 bytes test/riscv/tests/rv64ui-p-subw.elf | Bin 10400 -> 10400 bytes test/riscv/tests/rv64ui-p-sw.elf | Bin 14448 -> 14448 bytes test/riscv/tests/rv64ui-p-xor.elf | Bin 10080 -> 10080 bytes test/riscv/tests/rv64ui-p-xori.elf | Bin 9664 -> 9664 bytes test/riscv/tests/rv64ui-v-add.dump | 1229 +++++ test/riscv/tests/rv64ui-v-add.elf | Bin 0 -> 20080 bytes test/riscv/tests/rv64ui-v-addi.dump | 1051 ++++ test/riscv/tests/rv64ui-v-addi.elf | Bin 0 -> 19056 bytes test/riscv/tests/rv64ui-v-addiw.dump | 1048 ++++ test/riscv/tests/rv64ui-v-addiw.elf | Bin 0 -> 19048 bytes test/riscv/tests/rv64ui-v-addw.dump | 1224 +++++ test/riscv/tests/rv64ui-v-addw.elf | Bin 0 -> 20064 bytes test/riscv/tests/rv64ui-v-and.dump | 1232 +++++ test/riscv/tests/rv64ui-v-and.elf | Bin 0 -> 19832 bytes test/riscv/tests/rv64ui-v-andi.dump | 990 ++++ test/riscv/tests/rv64ui-v-andi.elf | Bin 0 -> 18552 bytes test/riscv/tests/rv64ui-v-auipc.dump | 859 ++++ test/riscv/tests/rv64ui-v-auipc.elf | Bin 0 -> 17768 bytes test/riscv/tests/rv64ui-v-beq.dump | 1054 ++++ test/riscv/tests/rv64ui-v-beq.elf | Bin 0 -> 18976 bytes test/riscv/tests/rv64ui-v-bge.dump | 1084 ++++ test/riscv/tests/rv64ui-v-bge.elf | Bin 0 -> 19168 bytes test/riscv/tests/rv64ui-v-bgeu.dump | 1138 +++++ test/riscv/tests/rv64ui-v-bgeu.elf | Bin 0 -> 19384 bytes test/riscv/tests/rv64ui-v-blt.dump | 1054 ++++ test/riscv/tests/rv64ui-v-blt.elf | Bin 0 -> 18976 bytes test/riscv/tests/rv64ui-v-bltu.dump | 1104 ++++ test/riscv/tests/rv64ui-v-bltu.elf | Bin 0 -> 19176 bytes test/riscv/tests/rv64ui-v-bne.dump | 1055 ++++ test/riscv/tests/rv64ui-v-bne.elf | Bin 0 -> 18976 bytes test/riscv/tests/rv64ui-v-fence_i.dump | 959 ++++ test/riscv/tests/rv64ui-v-fence_i.elf | Bin 0 -> 18656 bytes test/riscv/tests/rv64ui-v-jal.dump | 867 ++++ test/riscv/tests/rv64ui-v-jal.elf | Bin 0 -> 17856 bytes test/riscv/tests/rv64ui-v-jalr.dump | 905 ++++ test/riscv/tests/rv64ui-v-jalr.elf | Bin 0 -> 18072 bytes test/riscv/tests/rv64ui-v-lb.dump | 1037 ++++ test/riscv/tests/rv64ui-v-lb.elf | Bin 0 -> 19280 bytes test/riscv/tests/rv64ui-v-lbu.dump | 1037 ++++ test/riscv/tests/rv64ui-v-lbu.elf | Bin 0 -> 19280 bytes test/riscv/tests/rv64ui-v-ld.dump | 1141 +++++ test/riscv/tests/rv64ui-v-ld.elf | Bin 0 -> 23408 bytes test/riscv/tests/rv64ui-v-lh.dump | 1043 ++++ test/riscv/tests/rv64ui-v-lh.elf | Bin 0 -> 19288 bytes test/riscv/tests/rv64ui-v-lhu.dump | 1048 ++++ test/riscv/tests/rv64ui-v-lhu.elf | Bin 0 -> 19288 bytes test/riscv/tests/rv64ui-v-lui.dump | 872 ++++ test/riscv/tests/rv64ui-v-lui.elf | Bin 0 -> 17896 bytes test/riscv/tests/rv64ui-v-lw.dump | 1054 ++++ test/riscv/tests/rv64ui-v-lw.elf | Bin 0 -> 19296 bytes test/riscv/tests/rv64ui-v-lwu.dump | 1072 ++++ test/riscv/tests/rv64ui-v-lwu.elf | Bin 0 -> 19296 bytes test/riscv/tests/rv64ui-v-or.dump | 1265 +++++ test/riscv/tests/rv64ui-v-or.elf | Bin 0 -> 19960 bytes test/riscv/tests/rv64ui-v-ori.dump | 987 ++++ test/riscv/tests/rv64ui-v-ori.elf | Bin 0 -> 18536 bytes test/riscv/tests/rv64ui-v-sb.dump | 1169 +++++ test/riscv/tests/rv64ui-v-sb.elf | Bin 0 -> 23688 bytes test/riscv/tests/rv64ui-v-sd.dump | 1325 +++++ test/riscv/tests/rv64ui-v-sd.elf | Bin 0 -> 23760 bytes test/riscv/tests/rv64ui-v-sh.dump | 1200 +++++ test/riscv/tests/rv64ui-v-sh.elf | Bin 0 -> 23696 bytes test/riscv/tests/rv64ui-v-simple.dump | 832 +++ test/riscv/tests/rv64ui-v-simple.elf | Bin 0 -> 17528 bytes test/riscv/tests/rv64ui-v-sll.dump | 1315 +++++ test/riscv/tests/rv64ui-v-sll.elf | Bin 0 -> 20616 bytes test/riscv/tests/rv64ui-v-slli.dump | 1082 ++++ test/riscv/tests/rv64ui-v-slli.elf | Bin 0 -> 19256 bytes test/riscv/tests/rv64ui-v-slliw.dump | 1047 ++++ test/riscv/tests/rv64ui-v-slliw.elf | Bin 0 -> 19040 bytes test/riscv/tests/rv64ui-v-sllw.dump | 1269 +++++ test/riscv/tests/rv64ui-v-sllw.elf | Bin 0 -> 20360 bytes test/riscv/tests/rv64ui-v-slt.dump | 1218 +++++ test/riscv/tests/rv64ui-v-slt.elf | Bin 0 -> 20040 bytes test/riscv/tests/rv64ui-v-slti.dump | 1043 ++++ test/riscv/tests/rv64ui-v-slti.elf | Bin 0 -> 19024 bytes test/riscv/tests/rv64ui-v-sltiu.dump | 1043 ++++ test/riscv/tests/rv64ui-v-sltiu.elf | Bin 0 -> 19024 bytes test/riscv/tests/rv64ui-v-sltu.dump | 1235 +++++ test/riscv/tests/rv64ui-v-sltu.elf | Bin 0 -> 20104 bytes test/riscv/tests/rv64ui-v-sra.dump | 1281 +++++ test/riscv/tests/rv64ui-v-sra.elf | Bin 0 -> 20408 bytes test/riscv/tests/rv64ui-v-srai.dump | 1062 ++++ test/riscv/tests/rv64ui-v-srai.elf | Bin 0 -> 19104 bytes test/riscv/tests/rv64ui-v-sraiw.dump | 1076 ++++ test/riscv/tests/rv64ui-v-sraiw.elf | Bin 0 -> 19208 bytes test/riscv/tests/rv64ui-v-sraw.dump | 1281 +++++ test/riscv/tests/rv64ui-v-sraw.elf | Bin 0 -> 20408 bytes test/riscv/tests/rv64ui-v-srl.dump | 1308 +++++ test/riscv/tests/rv64ui-v-srl.elf | Bin 0 -> 20520 bytes test/riscv/tests/rv64ui-v-srli.dump | 1077 ++++ test/riscv/tests/rv64ui-v-srli.elf | Bin 0 -> 19160 bytes test/riscv/tests/rv64ui-v-srliw.dump | 1054 ++++ test/riscv/tests/rv64ui-v-srliw.elf | Bin 0 -> 19072 bytes test/riscv/tests/rv64ui-v-srlw.dump | 1275 +++++ test/riscv/tests/rv64ui-v-srlw.elf | Bin 0 -> 20384 bytes test/riscv/tests/rv64ui-v-sub.dump | 1218 +++++ test/riscv/tests/rv64ui-v-sub.elf | Bin 0 -> 20016 bytes test/riscv/tests/rv64ui-v-subw.dump | 1214 +++++ test/riscv/tests/rv64ui-v-subw.elf | Bin 0 -> 20000 bytes test/riscv/tests/rv64ui-v-sw.dump | 1203 +++++ test/riscv/tests/rv64ui-v-sw.elf | Bin 0 -> 23720 bytes test/riscv/tests/rv64ui-v-xor.dump | 1260 +++++ test/riscv/tests/rv64ui-v-xor.elf | Bin 0 -> 19944 bytes test/riscv/tests/rv64ui-v-xori.dump | 985 ++++ test/riscv/tests/rv64ui-v-xori.elf | Bin 0 -> 18528 bytes test/riscv/tests/rv64um-p-div.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-divu.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-divuw.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-divw.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-mul.elf | Bin 10272 -> 10272 bytes test/riscv/tests/rv64um-p-mulh.elf | Bin 10144 -> 10144 bytes test/riscv/tests/rv64um-p-mulhsu.elf | Bin 10144 -> 10144 bytes test/riscv/tests/rv64um-p-mulhu.elf | Bin 10208 -> 10208 bytes test/riscv/tests/rv64um-p-mulw.elf | Bin 10144 -> 10144 bytes test/riscv/tests/rv64um-p-rem.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-remu.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-remuw.elf | Bin 9536 -> 9536 bytes test/riscv/tests/rv64um-p-remw.elf | Bin 9568 -> 9568 bytes test/riscv/tests/rv64um-v-div.dump | 916 ++++ test/riscv/tests/rv64um-v-div.elf | Bin 0 -> 18160 bytes test/riscv/tests/rv64um-v-divu.dump | 922 ++++ test/riscv/tests/rv64um-v-divu.elf | Bin 0 -> 18184 bytes test/riscv/tests/rv64um-v-divuw.dump | 914 ++++ test/riscv/tests/rv64um-v-divuw.elf | Bin 0 -> 18152 bytes test/riscv/tests/rv64um-v-divw.dump | 911 ++++ test/riscv/tests/rv64um-v-divw.elf | Bin 0 -> 18136 bytes test/riscv/tests/rv64um-v-mul.dump | 1209 +++++ test/riscv/tests/rv64um-v-mul.elf | Bin 0 -> 19880 bytes test/riscv/tests/rv64um-v-mulh.dump | 1179 +++++ test/riscv/tests/rv64um-v-mulh.elf | Bin 0 -> 19664 bytes test/riscv/tests/rv64um-v-mulhsu.dump | 1179 +++++ test/riscv/tests/rv64um-v-mulhsu.elf | Bin 0 -> 19664 bytes test/riscv/tests/rv64um-v-mulhu.dump | 1215 +++++ test/riscv/tests/rv64um-v-mulhu.elf | Bin 0 -> 19856 bytes test/riscv/tests/rv64um-v-mulw.dump | 1140 +++++ test/riscv/tests/rv64um-v-mulw.elf | Bin 0 -> 19512 bytes test/riscv/tests/rv64um-v-rem.dump | 915 ++++ test/riscv/tests/rv64um-v-rem.elf | Bin 0 -> 18152 bytes test/riscv/tests/rv64um-v-remu.dump | 916 ++++ test/riscv/tests/rv64um-v-remu.elf | Bin 0 -> 18160 bytes test/riscv/tests/rv64um-v-remuw.dump | 911 ++++ test/riscv/tests/rv64um-v-remuw.elf | Bin 0 -> 18136 bytes test/riscv/tests/rv64um-v-remw.dump | 919 ++++ test/riscv/tests/rv64um-v-remw.elf | Bin 0 -> 18192 bytes 281 files changed, 97368 insertions(+), 152 deletions(-) create mode 100644 test/riscv/tests/disabled/rv64mi-p-sbreak.dump create mode 100644 test/riscv/tests/disabled/rv64si-p-sbreak.dump mode change 100755 => 100644 test/riscv/tests/disabled/rv64ua-p-lrsc.elf create mode 100644 test/riscv/tests/rv64mi-p-access.dump create mode 100644 test/riscv/tests/rv64mi-p-breakpoint.dump create mode 100644 test/riscv/tests/rv64mi-p-breakpoint.elf create mode 100644 test/riscv/tests/rv64mi-p-csr.dump create mode 100644 test/riscv/tests/rv64mi-p-csr.elf create mode 100644 test/riscv/tests/rv64mi-p-illegal.dump create mode 100644 test/riscv/tests/rv64mi-p-illegal.elf create mode 100644 test/riscv/tests/rv64mi-p-ma_addr.dump create mode 100644 test/riscv/tests/rv64mi-p-ma_addr.elf create mode 100644 test/riscv/tests/rv64mi-p-ma_fetch.dump create mode 100644 test/riscv/tests/rv64mi-p-ma_fetch.elf create mode 100644 test/riscv/tests/rv64mi-p-mcsr.dump create mode 100644 test/riscv/tests/rv64mi-p-mcsr.elf create mode 100644 test/riscv/tests/rv64mi-p-scall.dump create mode 100644 test/riscv/tests/rv64mi-p-scall.elf create mode 100644 test/riscv/tests/rv64si-p-csr.dump create mode 100644 test/riscv/tests/rv64si-p-csr.elf create mode 100644 test/riscv/tests/rv64si-p-dirty.dump create mode 100644 test/riscv/tests/rv64si-p-dirty.elf create mode 100644 test/riscv/tests/rv64si-p-ma_fetch.dump create mode 100644 test/riscv/tests/rv64si-p-ma_fetch.elf create mode 100644 test/riscv/tests/rv64si-p-scall.dump create mode 100644 test/riscv/tests/rv64si-p-scall.elf create mode 100644 test/riscv/tests/rv64si-p-wfi.dump create mode 100644 test/riscv/tests/rv64si-p-wfi.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoadd_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoadd_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoand_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoand_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomax_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomax_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomaxu_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomaxu_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomin_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amomin_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amominu_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amominu_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoor_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoor_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoswap_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoswap_w.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoxor_d.elf mode change 100755 => 100644 test/riscv/tests/rv64ua-p-amoxor_w.elf create mode 100644 test/riscv/tests/rv64ua-p-lrsc.dump create mode 100644 test/riscv/tests/rv64ua-v-amoadd_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amoadd_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amoadd_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amoadd_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amoand_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amoand_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amoand_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amoand_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amomax_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amomax_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amomax_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amomax_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amomaxu_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amomaxu_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amomaxu_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amomaxu_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amomin_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amomin_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amomin_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amomin_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amominu_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amominu_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amominu_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amominu_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amoor_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amoor_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amoor_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amoor_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amoswap_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amoswap_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amoswap_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amoswap_w.elf create mode 100644 test/riscv/tests/rv64ua-v-amoxor_d.dump create mode 100644 test/riscv/tests/rv64ua-v-amoxor_d.elf create mode 100644 test/riscv/tests/rv64ua-v-amoxor_w.dump create mode 100644 test/riscv/tests/rv64ua-v-amoxor_w.elf create mode 100644 test/riscv/tests/rv64ua-v-lrsc.dump mode change 100755 => 100644 test/riscv/tests/rv64uc-p-rvc.elf create mode 100644 test/riscv/tests/rv64uc-v-rvc.dump create mode 100644 test/riscv/tests/rv64uc-v-rvc.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-add.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-addi.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-addiw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-addw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-and.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-andi.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-auipc.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-beq.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-bge.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-bgeu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-blt.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-bltu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-bne.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-fence_i.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-jal.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-jalr.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lb.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lbu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-ld.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lh.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lhu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lui.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-lwu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-or.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-ori.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sb.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sd.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sh.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-simple.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sll.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-slli.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-slliw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sllw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-slt.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-slti.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sltiu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sltu.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sra.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-srai.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sraiw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sraw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-srl.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-srli.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-srliw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-srlw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sub.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-subw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-sw.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-xor.elf mode change 100755 => 100644 test/riscv/tests/rv64ui-p-xori.elf create mode 100644 test/riscv/tests/rv64ui-v-add.dump create mode 100644 test/riscv/tests/rv64ui-v-add.elf create mode 100644 test/riscv/tests/rv64ui-v-addi.dump create mode 100644 test/riscv/tests/rv64ui-v-addi.elf create mode 100644 test/riscv/tests/rv64ui-v-addiw.dump create mode 100644 test/riscv/tests/rv64ui-v-addiw.elf create mode 100644 test/riscv/tests/rv64ui-v-addw.dump create mode 100644 test/riscv/tests/rv64ui-v-addw.elf create mode 100644 test/riscv/tests/rv64ui-v-and.dump create mode 100644 test/riscv/tests/rv64ui-v-and.elf create mode 100644 test/riscv/tests/rv64ui-v-andi.dump create mode 100644 test/riscv/tests/rv64ui-v-andi.elf create mode 100644 test/riscv/tests/rv64ui-v-auipc.dump create mode 100644 test/riscv/tests/rv64ui-v-auipc.elf create mode 100644 test/riscv/tests/rv64ui-v-beq.dump create mode 100644 test/riscv/tests/rv64ui-v-beq.elf create mode 100644 test/riscv/tests/rv64ui-v-bge.dump create mode 100644 test/riscv/tests/rv64ui-v-bge.elf create mode 100644 test/riscv/tests/rv64ui-v-bgeu.dump create mode 100644 test/riscv/tests/rv64ui-v-bgeu.elf create mode 100644 test/riscv/tests/rv64ui-v-blt.dump create mode 100644 test/riscv/tests/rv64ui-v-blt.elf create mode 100644 test/riscv/tests/rv64ui-v-bltu.dump create mode 100644 test/riscv/tests/rv64ui-v-bltu.elf create mode 100644 test/riscv/tests/rv64ui-v-bne.dump create mode 100644 test/riscv/tests/rv64ui-v-bne.elf create mode 100644 test/riscv/tests/rv64ui-v-fence_i.dump create mode 100644 test/riscv/tests/rv64ui-v-fence_i.elf create mode 100644 test/riscv/tests/rv64ui-v-jal.dump create mode 100644 test/riscv/tests/rv64ui-v-jal.elf create mode 100644 test/riscv/tests/rv64ui-v-jalr.dump create mode 100644 test/riscv/tests/rv64ui-v-jalr.elf create mode 100644 test/riscv/tests/rv64ui-v-lb.dump create mode 100644 test/riscv/tests/rv64ui-v-lb.elf create mode 100644 test/riscv/tests/rv64ui-v-lbu.dump create mode 100644 test/riscv/tests/rv64ui-v-lbu.elf create mode 100644 test/riscv/tests/rv64ui-v-ld.dump create mode 100644 test/riscv/tests/rv64ui-v-ld.elf create mode 100644 test/riscv/tests/rv64ui-v-lh.dump create mode 100644 test/riscv/tests/rv64ui-v-lh.elf create mode 100644 test/riscv/tests/rv64ui-v-lhu.dump create mode 100644 test/riscv/tests/rv64ui-v-lhu.elf create mode 100644 test/riscv/tests/rv64ui-v-lui.dump create mode 100644 test/riscv/tests/rv64ui-v-lui.elf create mode 100644 test/riscv/tests/rv64ui-v-lw.dump create mode 100644 test/riscv/tests/rv64ui-v-lw.elf create mode 100644 test/riscv/tests/rv64ui-v-lwu.dump create mode 100644 test/riscv/tests/rv64ui-v-lwu.elf create mode 100644 test/riscv/tests/rv64ui-v-or.dump create mode 100644 test/riscv/tests/rv64ui-v-or.elf create mode 100644 test/riscv/tests/rv64ui-v-ori.dump create mode 100644 test/riscv/tests/rv64ui-v-ori.elf create mode 100644 test/riscv/tests/rv64ui-v-sb.dump create mode 100644 test/riscv/tests/rv64ui-v-sb.elf create mode 100644 test/riscv/tests/rv64ui-v-sd.dump create mode 100644 test/riscv/tests/rv64ui-v-sd.elf create mode 100644 test/riscv/tests/rv64ui-v-sh.dump create mode 100644 test/riscv/tests/rv64ui-v-sh.elf create mode 100644 test/riscv/tests/rv64ui-v-simple.dump create mode 100644 test/riscv/tests/rv64ui-v-simple.elf create mode 100644 test/riscv/tests/rv64ui-v-sll.dump create mode 100644 test/riscv/tests/rv64ui-v-sll.elf create mode 100644 test/riscv/tests/rv64ui-v-slli.dump create mode 100644 test/riscv/tests/rv64ui-v-slli.elf create mode 100644 test/riscv/tests/rv64ui-v-slliw.dump create mode 100644 test/riscv/tests/rv64ui-v-slliw.elf create mode 100644 test/riscv/tests/rv64ui-v-sllw.dump create mode 100644 test/riscv/tests/rv64ui-v-sllw.elf create mode 100644 test/riscv/tests/rv64ui-v-slt.dump create mode 100644 test/riscv/tests/rv64ui-v-slt.elf create mode 100644 test/riscv/tests/rv64ui-v-slti.dump create mode 100644 test/riscv/tests/rv64ui-v-slti.elf create mode 100644 test/riscv/tests/rv64ui-v-sltiu.dump create mode 100644 test/riscv/tests/rv64ui-v-sltiu.elf create mode 100644 test/riscv/tests/rv64ui-v-sltu.dump create mode 100644 test/riscv/tests/rv64ui-v-sltu.elf create mode 100644 test/riscv/tests/rv64ui-v-sra.dump create mode 100644 test/riscv/tests/rv64ui-v-sra.elf create mode 100644 test/riscv/tests/rv64ui-v-srai.dump create mode 100644 test/riscv/tests/rv64ui-v-srai.elf create mode 100644 test/riscv/tests/rv64ui-v-sraiw.dump create mode 100644 test/riscv/tests/rv64ui-v-sraiw.elf create mode 100644 test/riscv/tests/rv64ui-v-sraw.dump create mode 100644 test/riscv/tests/rv64ui-v-sraw.elf create mode 100644 test/riscv/tests/rv64ui-v-srl.dump create mode 100644 test/riscv/tests/rv64ui-v-srl.elf create mode 100644 test/riscv/tests/rv64ui-v-srli.dump create mode 100644 test/riscv/tests/rv64ui-v-srli.elf create mode 100644 test/riscv/tests/rv64ui-v-srliw.dump create mode 100644 test/riscv/tests/rv64ui-v-srliw.elf create mode 100644 test/riscv/tests/rv64ui-v-srlw.dump create mode 100644 test/riscv/tests/rv64ui-v-srlw.elf create mode 100644 test/riscv/tests/rv64ui-v-sub.dump create mode 100644 test/riscv/tests/rv64ui-v-sub.elf create mode 100644 test/riscv/tests/rv64ui-v-subw.dump create mode 100644 test/riscv/tests/rv64ui-v-subw.elf create mode 100644 test/riscv/tests/rv64ui-v-sw.dump create mode 100644 test/riscv/tests/rv64ui-v-sw.elf create mode 100644 test/riscv/tests/rv64ui-v-xor.dump create mode 100644 test/riscv/tests/rv64ui-v-xor.elf create mode 100644 test/riscv/tests/rv64ui-v-xori.dump create mode 100644 test/riscv/tests/rv64ui-v-xori.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-div.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-divu.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-divuw.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-divw.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-mul.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-mulh.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-mulhsu.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-mulhu.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-mulw.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-rem.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-remu.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-remuw.elf mode change 100755 => 100644 test/riscv/tests/rv64um-p-remw.elf create mode 100644 test/riscv/tests/rv64um-v-div.dump create mode 100644 test/riscv/tests/rv64um-v-div.elf create mode 100644 test/riscv/tests/rv64um-v-divu.dump create mode 100644 test/riscv/tests/rv64um-v-divu.elf create mode 100644 test/riscv/tests/rv64um-v-divuw.dump create mode 100644 test/riscv/tests/rv64um-v-divuw.elf create mode 100644 test/riscv/tests/rv64um-v-divw.dump create mode 100644 test/riscv/tests/rv64um-v-divw.elf create mode 100644 test/riscv/tests/rv64um-v-mul.dump create mode 100644 test/riscv/tests/rv64um-v-mul.elf create mode 100644 test/riscv/tests/rv64um-v-mulh.dump create mode 100644 test/riscv/tests/rv64um-v-mulh.elf create mode 100644 test/riscv/tests/rv64um-v-mulhsu.dump create mode 100644 test/riscv/tests/rv64um-v-mulhsu.elf create mode 100644 test/riscv/tests/rv64um-v-mulhu.dump create mode 100644 test/riscv/tests/rv64um-v-mulhu.elf create mode 100644 test/riscv/tests/rv64um-v-mulw.dump create mode 100644 test/riscv/tests/rv64um-v-mulw.elf create mode 100644 test/riscv/tests/rv64um-v-rem.dump create mode 100644 test/riscv/tests/rv64um-v-rem.elf create mode 100644 test/riscv/tests/rv64um-v-remu.dump create mode 100644 test/riscv/tests/rv64um-v-remu.elf create mode 100644 test/riscv/tests/rv64um-v-remuw.dump create mode 100644 test/riscv/tests/rv64um-v-remuw.elf create mode 100644 test/riscv/tests/rv64um-v-remw.dump create mode 100644 test/riscv/tests/rv64um-v-remw.elf diff --git a/test/riscv/tests/README b/test/riscv/tests/README index 4dcfeb11..cb1e5105 100644 --- a/test/riscv/tests/README +++ b/test/riscv/tests/README @@ -24,4 +24,4 @@ HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. The tests in this directory were built from -https://github.com/riscv/riscv-tools commit 98682995dc4a1ab8777ff45ba673cf2658e54ae2 . +https://github.com/riscv/riscv-tools commit 84e9d5bf515908d15215cd8ee5b5beb6f7519491 . diff --git a/test/riscv/tests/disabled/rv64mi-p-sbreak.dump b/test/riscv/tests/disabled/rv64mi-p-sbreak.dump new file mode 100644 index 00000000..8e03511c --- /dev/null +++ b/test/riscv/tests/disabled/rv64mi-p-sbreak.dump @@ -0,0 +1,130 @@ + +rv64mi-p-sbreak: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 118f0f13 addi t5,t5,280 # 80000138 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + +000000008000010c : + 8000010c: 00100073 ebreak + 80000110: 0080006f j 80000118 + 80000114: 00301c63 bne zero,gp,8000012c + +0000000080000118 : + 80000118: 0ff0000f fence + 8000011c: 00018063 beqz gp,8000011c + 80000120: 00119193 slli gp,gp,0x1 + 80000124: 0011e193 ori gp,gp,1 + 80000128: 00000073 ecall + +000000008000012c : + 8000012c: 0ff0000f fence + 80000130: 00100193 li gp,1 + 80000134: 00000073 ecall + +0000000080000138 : + 80000138: 00300313 li t1,3 + 8000013c: 342022f3 csrr t0,mcause + 80000140: fc629ce3 bne t0,t1,80000118 + 80000144: 00000317 auipc t1,0x0 + 80000148: fc830313 addi t1,t1,-56 # 8000010c + 8000014c: 341022f3 csrr t0,mepc + 80000150: fc6294e3 bne t0,t1,80000118 + 80000154: fd9ff06f j 8000012c + 80000158: c0001073 unimp + 8000015c: 0000 unimp + 8000015e: 0000 unimp + 80000160: 0000 unimp + 80000162: 0000 unimp + 80000164: 0000 unimp + 80000166: 0000 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/disabled/rv64si-p-sbreak.dump b/test/riscv/tests/disabled/rv64si-p-sbreak.dump new file mode 100644 index 00000000..e981c549 --- /dev/null +++ b/test/riscv/tests/disabled/rv64si-p-sbreak.dump @@ -0,0 +1,128 @@ + +rv64si-p-sbreak: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 00000297 auipc t0,0x0 + 800000c4: 08028293 addi t0,t0,128 # 80000140 + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + 80000110: 00200193 li gp,2 + +0000000080000114 : + 80000114: 00100073 ebreak + 80000118: 0080006f j 80000120 + 8000011c: 00301c63 bne zero,gp,80000134 + +0000000080000120 : + 80000120: 0ff0000f fence + 80000124: 00018063 beqz gp,80000124 + 80000128: 00119193 slli gp,gp,0x1 + 8000012c: 0011e193 ori gp,gp,1 + 80000130: 00000073 ecall + +0000000080000134 : + 80000134: 0ff0000f fence + 80000138: 00100193 li gp,1 + 8000013c: 00000073 ecall + +0000000080000140 : + 80000140: 00300313 li t1,3 + 80000144: 142022f3 csrr t0,scause + 80000148: fc629ce3 bne t0,t1,80000120 + 8000014c: 00000317 auipc t1,0x0 + 80000150: fc830313 addi t1,t1,-56 # 80000114 + 80000154: 141022f3 csrr t0,sepc + 80000158: fc6294e3 bne t0,t1,80000120 + 8000015c: fd9ff06f j 80000134 + 80000160: c0001073 unimp + 80000164: 0000 unimp + 80000166: 0000 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/disabled/rv64ua-p-lrsc.elf b/test/riscv/tests/disabled/rv64ua-p-lrsc.elf old mode 100755 new mode 100644 index f9b7fc2e..bff66644 Binary files a/test/riscv/tests/disabled/rv64ua-p-lrsc.elf and b/test/riscv/tests/disabled/rv64ua-p-lrsc.elf differ diff --git a/test/riscv/tests/rv64mi-p-access.dump b/test/riscv/tests/rv64mi-p-access.dump new file mode 100644 index 00000000..5b35e596 --- /dev/null +++ b/test/riscv/tests/rv64mi-p-access.dump @@ -0,0 +1,142 @@ + +rv64mi-p-access: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 158f0f13 addi t5,t5,344 # 80000178 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00000397 auipc t2,0x0 + 8000010c: 05038393 addi t2,t2,80 # 80000158 + 80000110: fff0029b addiw t0,zero,-1 + 80000114: 03f29293 slli t0,t0,0x3f + 80000118: 0072c2b3 xor t0,t0,t2 + 8000011c: 00200193 li gp,2 + 80000120: 00100313 li t1,1 + 80000124: 00000e17 auipc t3,0x0 + 80000128: 010e0e13 addi t3,t3,16 # 80000134 + 8000012c: 00000393 li t2,0 + 80000130: 000283e7 jalr t2,t0 + 80000134: 00300193 li gp,3 + 80000138: 00500313 li t1,5 + 8000013c: 00000e17 auipc t3,0x0 + 80000140: 014e0e13 addi t3,t3,20 # 80000150 + 80000144: 000e0393 mv t2,t3 + 80000148: 00028383 lb t2,0(t0) + 8000014c: 00c0006f j 80000158 + 80000150: 01c0006f j 8000016c + 80000154: 00301c63 bne zero,gp,8000016c + +0000000080000158 : + 80000158: 0ff0000f fence + 8000015c: 00018063 beqz gp,8000015c + 80000160: 00119193 slli gp,gp,0x1 + 80000164: 0011e193 ori gp,gp,1 + 80000168: 00000073 ecall + +000000008000016c : + 8000016c: 0ff0000f fence + 80000170: 00100193 li gp,1 + 80000174: 00000073 ecall + +0000000080000178 : + 80000178: 00200513 li a0,2 + 8000017c: 00a18863 beq gp,a0,8000018c + 80000180: 00300513 li a0,3 + 80000184: 00a18463 beq gp,a0,8000018c + 80000188: fd1ff06f j 80000158 + 8000018c: fdc396e3 bne t2,t3,80000158 + 80000190: 342023f3 csrr t2,mcause + 80000194: fc6392e3 bne t2,t1,80000158 + 80000198: 341e1073 csrw mepc,t3 + 8000019c: 30200073 mret + 800001a0: c0001073 unimp + 800001a4: 0000 unimp + 800001a6: 0000 unimp + 800001a8: 0000 unimp + 800001aa: 0000 unimp + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0000 unimp + 800001b2: 0000 unimp + 800001b4: 0000 unimp + 800001b6: 0000 unimp + 800001b8: 0000 unimp + 800001ba: 0000 unimp + 800001bc: 0000 unimp + 800001be: 0000 unimp + 800001c0: 0000 unimp + 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-breakpoint.dump b/test/riscv/tests/rv64mi-p-breakpoint.dump new file mode 100644 index 00000000..d882b10a --- /dev/null +++ b/test/riscv/tests/rv64mi-p-breakpoint.dump @@ -0,0 +1,207 @@ + +rv64mi-p-breakpoint: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 210f0f13 addi t5,t5,528 # 80000230 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + 8000010c: 7a001073 csrw tselect,zero + 80000110: 7a0025f3 csrr a1,tselect + 80000114: 10b01863 bne zero,a1,80000224 + 80000118: 7a102573 csrr a0,tdata1 + 8000011c: 03c55513 srli a0,a0,0x3c + 80000120: 00200593 li a1,2 + 80000124: 10b51063 bne a0,a1,80000224 + 80000128: 00000617 auipc a2,0x0 + 8000012c: 02060613 addi a2,a2,32 # 80000148 + 80000130: 7a261073 csrw tdata2,a2 + 80000134: 04400513 li a0,68 + 80000138: 7a151073 csrw tdata1,a0 + 8000013c: 7a1025f3 csrr a1,tdata1 + 80000140: 7ff5f593 andi a1,a1,2047 + 80000144: 00b51863 bne a0,a1,80000154 + 80000148: 0c000463 beqz zero,80000210 + 8000014c: 00300193 li gp,3 + 80000150: 00062503 lw a0,0(a2) + 80000154: 00400193 li gp,4 + 80000158: 04100513 li a0,65 + 8000015c: 7a151073 csrw tdata1,a0 + 80000160: 7a1025f3 csrr a1,tdata1 + 80000164: 7ff5f593 andi a1,a1,2047 + 80000168: 02b51063 bne a0,a1,80000188 + 8000016c: 00002617 auipc a2,0x2 + 80000170: e9460613 addi a2,a2,-364 # 80002000 + 80000174: 7a261073 csrw tdata2,a2 + 80000178: 00062603 lw a2,0(a2) + 8000017c: 08060a63 beqz a2,80000210 + 80000180: 00500193 li gp,5 + 80000184: 00062023 sw zero,0(a2) + 80000188: 00600193 li gp,6 + 8000018c: 04200513 li a0,66 + 80000190: 7a151073 csrw tdata1,a0 + 80000194: 7a1025f3 csrr a1,tdata1 + 80000198: 7ff5f593 andi a1,a1,2047 + 8000019c: 06b51863 bne a0,a1,8000020c + 800001a0: 00c62023 sw a2,0(a2) + 800001a4: 00700193 li gp,7 + 800001a8: 00062603 lw a2,0(a2) + 800001ac: 06061263 bnez a2,80000210 + 800001b0: 00100513 li a0,1 + 800001b4: 7a051073 csrw tselect,a0 + 800001b8: 7a0025f3 csrr a1,tselect + 800001bc: 06b51463 bne a0,a1,80000224 + 800001c0: 7a102573 csrr a0,tdata1 + 800001c4: 03c55513 srli a0,a0,0x3c + 800001c8: 00200593 li a1,2 + 800001cc: 04b51c63 bne a0,a1,80000224 + 800001d0: 04100513 li a0,65 + 800001d4: 7a151073 csrw tdata1,a0 + 800001d8: 00002697 auipc a3,0x2 + 800001dc: e2c68693 addi a3,a3,-468 # 80002004 + 800001e0: 7a269073 csrw tdata2,a3 + 800001e4: 00800193 li gp,8 + 800001e8: 0006a683 lw a3,0(a3) + 800001ec: 02068263 beqz a3,80000210 + 800001f0: 00a00193 li gp,10 + 800001f4: 00002617 auipc a2,0x2 + 800001f8: e0c60613 addi a2,a2,-500 # 80002000 + 800001fc: 00c62023 sw a2,0(a2) + 80000200: 00b00193 li gp,11 + 80000204: 00062603 lw a2,0(a2) + 80000208: 00061463 bnez a2,80000210 + 8000020c: 00301c63 bne zero,gp,80000224 + +0000000080000210 : + 80000210: 0ff0000f fence + 80000214: 00018063 beqz gp,80000214 + 80000218: 00119193 slli gp,gp,0x1 + 8000021c: 0011e193 ori gp,gp,1 + 80000220: 00000073 ecall + +0000000080000224 : + 80000224: 0ff0000f fence + 80000228: 00100193 li gp,1 + 8000022c: 00000073 ecall + +0000000080000230 : + 80000230: 0011f293 andi t0,gp,1 + 80000234: fc029ee3 bnez t0,80000210 + 80000238: 00300293 li t0,3 + 8000023c: 34202373 csrr t1,mcause + 80000240: fc6298e3 bne t0,t1,80000210 + 80000244: 341022f3 csrr t0,mepc + 80000248: 00428293 addi t0,t0,4 + 8000024c: 34129073 csrw mepc,t0 + 80000250: 30200073 mret + 80000254: c0001073 unimp + 80000258: 0000 unimp + 8000025a: 0000 unimp + 8000025c: 0000 unimp + 8000025e: 0000 unimp + 80000260: 0000 unimp + 80000262: 0000 unimp + 80000264: 0000 unimp + 80000266: 0000 unimp + 80000268: 0000 unimp + 8000026a: 0000 unimp + 8000026c: 0000 unimp + 8000026e: 0000 unimp + 80000270: 0000 unimp + 80000272: 0000 unimp + 80000274: 0000 unimp + 80000276: 0000 unimp + 80000278: 0000 unimp + 8000027a: 0000 unimp + 8000027c: 0000 unimp + 8000027e: 0000 unimp + 80000280: 0000 unimp + 80000282: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: 0000 unimp + 80002002: 0000 unimp + +0000000080002004 : + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-breakpoint.elf b/test/riscv/tests/rv64mi-p-breakpoint.elf new file mode 100644 index 00000000..04af6b26 Binary files /dev/null and b/test/riscv/tests/rv64mi-p-breakpoint.elf differ diff --git a/test/riscv/tests/rv64mi-p-csr.dump b/test/riscv/tests/rv64mi-p-csr.dump new file mode 100644 index 00000000..e2ccda2f --- /dev/null +++ b/test/riscv/tests/rv64mi-p-csr.dump @@ -0,0 +1,287 @@ + +rv64mi-p-csr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 2a0f0f13 addi t5,t5,672 # 800002c0 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 000022b7 lui t0,0x2 + 8000010c: 8002829b addiw t0,t0,-2048 + 80000110: 3002b073 csrc mstatus,t0 + 80000114: 30002373 csrr t1,mstatus + 80000118: 0062f2b3 and t0,t0,t1 + 8000011c: 02029463 bnez t0,80000144 + +0000000080000120 : + 80000120: 30002573 csrr a0,mstatus + 80000124: 0030059b addiw a1,zero,3 + 80000128: 02059593 slli a1,a1,0x20 + 8000012c: 00b57533 and a0,a0,a1 + 80000130: 00100e9b addiw t4,zero,1 + 80000134: 021e9e93 slli t4,t4,0x21 + 80000138: 00d00193 li gp,13 + 8000013c: 17d51263 bne a0,t4,800002a0 + 80000140: 0200006f j 80000160 + +0000000080000144 : + 80000144: 30002573 csrr a0,mstatus + 80000148: 0030059b addiw a1,zero,3 + 8000014c: 02059593 slli a1,a1,0x20 + 80000150: 00b57533 and a0,a0,a1 + 80000154: 00000e93 li t4,0 + 80000158: 00e00193 li gp,14 + 8000015c: 15d51263 bne a0,t4,800002a0 + 80000160: 3401d073 csrwi mscratch,3 + +0000000080000164 : + 80000164: 34002573 csrr a0,mscratch + 80000168: 00300e93 li t4,3 + 8000016c: 00200193 li gp,2 + 80000170: 13d51863 bne a0,t4,800002a0 + +0000000080000174 : + 80000174: 3400f5f3 csrrci a1,mscratch,1 + 80000178: 00300e93 li t4,3 + 8000017c: 00300193 li gp,3 + 80000180: 13d59063 bne a1,t4,800002a0 + +0000000080000184 : + 80000184: 34026673 csrrsi a2,mscratch,4 + 80000188: 00200e93 li t4,2 + 8000018c: 00400193 li gp,4 + 80000190: 11d61863 bne a2,t4,800002a0 + +0000000080000194 : + 80000194: 340156f3 csrrwi a3,mscratch,2 + 80000198: 00600e93 li t4,6 + 8000019c: 00500193 li gp,5 + 800001a0: 11d69063 bne a3,t4,800002a0 + +00000000800001a4 : + 800001a4: 0bad2537 lui a0,0xbad2 + 800001a8: dea5051b addiw a0,a0,-534 + 800001ac: 340515f3 csrrw a1,mscratch,a0 + 800001b0: 00200e93 li t4,2 + 800001b4: 00600193 li gp,6 + 800001b8: 0fd59463 bne a1,t4,800002a0 + +00000000800001bc : + 800001bc: 00002537 lui a0,0x2 + 800001c0: dea5051b addiw a0,a0,-534 + 800001c4: 34053573 csrrc a0,mscratch,a0 + 800001c8: 0bad2eb7 lui t4,0xbad2 + 800001cc: deae8e9b addiw t4,t4,-534 + 800001d0: 00700193 li gp,7 + 800001d4: 0dd51663 bne a0,t4,800002a0 + +00000000800001d8 : + 800001d8: 0000c537 lui a0,0xc + 800001dc: eef5051b addiw a0,a0,-273 + 800001e0: 34052573 csrrs a0,mscratch,a0 + 800001e4: 0bad0eb7 lui t4,0xbad0 + 800001e8: 00800193 li gp,8 + 800001ec: 0bd51a63 bne a0,t4,800002a0 + +00000000800001f0 : + 800001f0: 34002573 csrr a0,mscratch + 800001f4: 0badceb7 lui t4,0xbadc + 800001f8: eefe8e9b addiw t4,t4,-273 + 800001fc: 00900193 li gp,9 + 80000200: 0bd51063 bne a0,t4,800002a0 + 80000204: 30102573 csrr a0,misa + 80000208: 02057513 andi a0,a0,32 + 8000020c: 02050863 beqz a0,8000023c + 80000210: 000065b7 lui a1,0x6 + 80000214: 3005a073 csrs mstatus,a1 + 80000218: f0000053 fmv.w.x ft0,zero + 8000021c: 3005b073 csrc mstatus,a1 + 80000220: 00002597 auipc a1,0x2 + 80000224: de058593 addi a1,a1,-544 # 80002000 + +0000000080000228 : + 80000228: 0005a027 fsw ft0,0(a1) + 8000022c: 0005a503 lw a0,0(a1) + 80000230: 00100e93 li t4,1 + 80000234: 00a00193 li gp,10 + 80000238: 07d51463 bne a0,t4,800002a0 + 8000023c: 30102573 csrr a0,misa + 80000240: 01455513 srli a0,a0,0x14 + 80000244: 00157513 andi a0,a0,1 + 80000248: 04050463 beqz a0,80000290 + 8000024c: 000022b7 lui t0,0x2 + 80000250: 8002829b addiw t0,t0,-2048 + 80000254: 3002b073 csrc mstatus,t0 + 80000258: 00000297 auipc t0,0x0 + 8000025c: 01028293 addi t0,t0,16 # 80000268 + 80000260: 34129073 csrw mepc,t0 + 80000264: 30200073 mret + +0000000080000268 : + 80000268: 0ff00513 li a0,255 + 8000026c: c0001573 csrrw a0,cycle,zero + 80000270: 0ff00e93 li t4,255 + 80000274: 00b00193 li gp,11 + 80000278: 03d51463 bne a0,t4,800002a0 + +000000008000027c : + 8000027c: 0ff00513 li a0,255 + 80000280: 30002573 csrr a0,mstatus + 80000284: 0ff00e93 li t4,255 + 80000288: 00c00193 li gp,12 + 8000028c: 01d51a63 bne a0,t4,800002a0 + +0000000080000290 : + 80000290: 0ff0000f fence + 80000294: 00100193 li gp,1 + 80000298: 00000073 ecall + 8000029c: 00301c63 bne zero,gp,800002b4 + +00000000800002a0 : + 800002a0: 0ff0000f fence + 800002a4: 00018063 beqz gp,800002a4 + 800002a8: 00119193 slli gp,gp,0x1 + 800002ac: 0011e193 ori gp,gp,1 + 800002b0: 00000073 ecall + +00000000800002b4 : + 800002b4: 0ff0000f fence + 800002b8: 00100193 li gp,1 + 800002bc: 00000073 ecall + +00000000800002c0 : + 800002c0: 00900293 li t0,9 + 800002c4: 0051e663 bltu gp,t0,800002d0 + 800002c8: 00b00293 li t0,11 + 800002cc: 0032fe63 bleu gp,t0,800002e8 + 800002d0: 342022f3 csrr t0,mcause + 800002d4: 00800313 li t1,8 + 800002d8: fc6294e3 bne t0,t1,800002a0 + 800002dc: 0ff0000f fence + 800002e0: 00100193 li gp,1 + 800002e4: 00000073 ecall + +00000000800002e8 : + 800002e8: 342022f3 csrr t0,mcause + 800002ec: 00200313 li t1,2 + 800002f0: fa6298e3 bne t0,t1,800002a0 + 800002f4: 341022f3 csrr t0,mepc + 800002f8: 00428293 addi t0,t0,4 + 800002fc: 34129073 csrw mepc,t0 + 80000300: 30200073 mret + 80000304: c0001073 unimp + 80000308: 0000 unimp + 8000030a: 0000 unimp + 8000030c: 0000 unimp + 8000030e: 0000 unimp + 80000310: 0000 unimp + 80000312: 0000 unimp + 80000314: 0000 unimp + 80000316: 0000 unimp + 80000318: 0000 unimp + 8000031a: 0000 unimp + 8000031c: 0000 unimp + 8000031e: 0000 unimp + 80000320: 0000 unimp + 80000322: 0000 unimp + 80000324: 0000 unimp + 80000326: 0000 unimp + 80000328: 0000 unimp + 8000032a: 0000 unimp + 8000032c: 0000 unimp + 8000032e: 0000 unimp + 80000330: 0000 unimp + 80000332: 0000 unimp + 80000334: 0000 unimp + 80000336: 0000 unimp + 80000338: 0000 unimp + 8000033a: 0000 unimp + 8000033c: 0000 unimp + 8000033e: 0000 unimp + 80000340: 0000 unimp + 80000342: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: 0001 nop + 80002002: 0000 unimp + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-csr.elf b/test/riscv/tests/rv64mi-p-csr.elf new file mode 100644 index 00000000..d7c74bc2 Binary files /dev/null and b/test/riscv/tests/rv64mi-p-csr.elf differ diff --git a/test/riscv/tests/rv64mi-p-illegal.dump b/test/riscv/tests/rv64mi-p-illegal.dump new file mode 100644 index 00000000..56485c4a --- /dev/null +++ b/test/riscv/tests/rv64mi-p-illegal.dump @@ -0,0 +1,383 @@ + +rv64mi-p-illegal: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 2e0f0f13 addi t5,t5,736 # 80000300 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + +000000008000010c : + 8000010c: 0000 unimp + 8000010e: 0000 unimp + 80000110: 0f40006f j 80000204 + 80000114: 000022b7 lui t0,0x2 + 80000118: 8002829b addiw t0,t0,-2048 + 8000011c: 3002b073 csrc mstatus,t0 + 80000120: 00001337 lui t1,0x1 + 80000124: 8003031b addiw t1,t1,-2048 + 80000128: 30032073 csrs mstatus,t1 + 8000012c: 300023f3 csrr t2,mstatus + 80000130: 0053f3b3 and t2,t2,t0 + 80000134: 0e731263 bne t1,t2,80000218 + +0000000080000138 : + 80000138: 34415073 csrwi mip,2 + 8000013c: 30415073 csrwi mie,2 + 80000140: 00000297 auipc t0,0x0 + 80000144: 1c128293 addi t0,t0,449 # 80000301 + 80000148: 30529473 csrrw s0,mtvec,t0 + 8000014c: 305022f3 csrr t0,mtvec + 80000150: 0012f293 andi t0,t0,1 + 80000154: 00028663 beqz t0,80000160 + 80000158: 30046073 csrsi mstatus,8 + 8000015c: 0000006f j 8000015c + +0000000080000160 : + 80000160: 30541073 csrw mtvec,s0 + 80000164: 30315073 csrwi mideleg,2 + 80000168: 00000297 auipc t0,0x0 + 8000016c: 02828293 addi t0,t0,40 # 80000190 + 80000170: 34129073 csrw mepc,t0 + 80000174: 000022b7 lui t0,0x2 + 80000178: 8002829b addiw t0,t0,-2048 + 8000017c: 3002b073 csrc mstatus,t0 + 80000180: 00001337 lui t1,0x1 + 80000184: 8003031b addiw t1,t1,-2048 + 80000188: 30032073 csrs mstatus,t1 + 8000018c: 30200073 mret + 80000190: 10500073 wfi + +0000000080000194 : + 80000194: 0000 unimp + 80000196: 0000 unimp + 80000198: 06c0006f j 80000204 + +000000008000019c : + 8000019c: 10500073 wfi + 800001a0: 0640006f j 80000204 + 800001a4: 12000073 sfence.vma + 800001a8: 180022f3 csrr t0,satp + +00000000800001ac : + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0540006f j 80000204 + +00000000800001b4 : + 800001b4: 12000073 sfence.vma + 800001b8: 04c0006f j 80000204 + +00000000800001bc : + 800001bc: 180022f3 csrr t0,satp + 800001c0: 0440006f j 80000204 + 800001c4: 00000297 auipc t0,0x0 + 800001c8: 02028293 addi t0,t0,32 # 800001e4 + 800001cc: 14129073 csrw sepc,t0 + 800001d0: 10000293 li t0,256 + 800001d4: 1002a073 csrs sstatus,t0 + 800001d8: 02000293 li t0,32 + 800001dc: 1002b073 csrc sstatus,t0 + 800001e0: 10200073 sret + +00000000800001e4 : + 800001e4: 0000 unimp + 800001e6: 0000 unimp + 800001e8: 01c0006f j 80000204 + 800001ec: 00000297 auipc t0,0x0 + 800001f0: 01028293 addi t0,t0,16 # 800001fc + 800001f4: 14129073 csrw sepc,t0 + +00000000800001f8 : + 800001f8: 10200073 sret + 800001fc: 0080006f j 80000204 + 80000200: 00301c63 bne zero,gp,80000218 + +0000000080000204 : + 80000204: 0ff0000f fence + 80000208: 00018063 beqz gp,80000208 + 8000020c: 00119193 slli gp,gp,0x1 + 80000210: 0011e193 ori gp,gp,1 + 80000214: 00000073 ecall + +0000000080000218 : + 80000218: 0ff0000f fence + 8000021c: 00100193 li gp,1 + 80000220: 00000073 ecall + 80000224: 00000013 nop + 80000228: 00000013 nop + 8000022c: 00000013 nop + 80000230: 00000013 nop + 80000234: 00000013 nop + 80000238: 00000013 nop + 8000023c: 00000013 nop + 80000240: 00000013 nop + 80000244: 00000013 nop + 80000248: 00000013 nop + 8000024c: 00000013 nop + 80000250: 00000013 nop + 80000254: 00000013 nop + 80000258: 00000013 nop + 8000025c: 00000013 nop + 80000260: 00000013 nop + 80000264: 00000013 nop + 80000268: 00000013 nop + 8000026c: 00000013 nop + 80000270: 00000013 nop + 80000274: 00000013 nop + 80000278: 00000013 nop + 8000027c: 00000013 nop + 80000280: 00000013 nop + 80000284: 00000013 nop + 80000288: 00000013 nop + 8000028c: 00000013 nop + 80000290: 00000013 nop + 80000294: 00000013 nop + 80000298: 00000013 nop + 8000029c: 00000013 nop + 800002a0: 00000013 nop + 800002a4: 00000013 nop + 800002a8: 00000013 nop + 800002ac: 00000013 nop + 800002b0: 00000013 nop + 800002b4: 00000013 nop + 800002b8: 00000013 nop + 800002bc: 00000013 nop + 800002c0: 00000013 nop + 800002c4: 00000013 nop + 800002c8: 00000013 nop + 800002cc: 00000013 nop + 800002d0: 00000013 nop + 800002d4: 00000013 nop + 800002d8: 00000013 nop + 800002dc: 00000013 nop + 800002e0: 00000013 nop + 800002e4: 00000013 nop + 800002e8: 00000013 nop + 800002ec: 00000013 nop + 800002f0: 00000013 nop + 800002f4: 00000013 nop + 800002f8: 00000013 nop + 800002fc: 00000013 nop + +0000000080000300 : + 80000300: 0400006f j 80000340 + 80000304: e5dff06f j 80000160 + 80000308: efdff06f j 80000204 + 8000030c: ef9ff06f j 80000204 + 80000310: ef5ff06f j 80000204 + 80000314: ef1ff06f j 80000204 + 80000318: eedff06f j 80000204 + 8000031c: ee9ff06f j 80000204 + 80000320: ee5ff06f j 80000204 + 80000324: ee1ff06f j 80000204 + 80000328: eddff06f j 80000204 + 8000032c: ed9ff06f j 80000204 + 80000330: ed5ff06f j 80000204 + 80000334: ed1ff06f j 80000204 + 80000338: ecdff06f j 80000204 + 8000033c: ec9ff06f j 80000204 + +0000000080000340 : + 80000340: 00200313 li t1,2 + 80000344: 342022f3 csrr t0,mcause + 80000348: ea629ee3 bne t0,t1,80000204 + 8000034c: 341022f3 csrr t0,mepc + 80000350: 343023f3 csrr t2,mbadaddr + 80000354: 00038c63 beqz t2,8000036c + 80000358: 0002de03 lhu t3,0(t0) + 8000035c: 0022de83 lhu t4,2(t0) + 80000360: 010e9e93 slli t4,t4,0x10 + 80000364: 01de6e33 or t3,t3,t4 + 80000368: e9c39ee3 bne t2,t3,80000204 + 8000036c: 00000317 auipc t1,0x0 + 80000370: da030313 addi t1,t1,-608 # 8000010c + 80000374: 04628e63 beq t0,t1,800003d0 + 80000378: 00000317 auipc t1,0x0 + 8000037c: e1c30313 addi t1,t1,-484 # 80000194 + 80000380: 04628e63 beq t0,t1,800003dc + 80000384: 00000317 auipc t1,0x0 + 80000388: e1830313 addi t1,t1,-488 # 8000019c + 8000038c: 04628263 beq t0,t1,800003d0 + 80000390: 00000317 auipc t1,0x0 + 80000394: e1c30313 addi t1,t1,-484 # 800001ac + 80000398: 04628863 beq t0,t1,800003e8 + 8000039c: 00000317 auipc t1,0x0 + 800003a0: e1830313 addi t1,t1,-488 # 800001b4 + 800003a4: 02628663 beq t0,t1,800003d0 + 800003a8: 00000317 auipc t1,0x0 + 800003ac: e1430313 addi t1,t1,-492 # 800001bc + 800003b0: 02628063 beq t0,t1,800003d0 + 800003b4: 00000317 auipc t1,0x0 + 800003b8: e3030313 addi t1,t1,-464 # 800001e4 + 800003bc: 02628c63 beq t0,t1,800003f4 + 800003c0: 00000317 auipc t1,0x0 + 800003c4: e3830313 addi t1,t1,-456 # 800001f8 + 800003c8: 02628c63 beq t0,t1,80000400 + 800003cc: e39ff06f j 80000204 + 800003d0: 00828293 addi t0,t0,8 + 800003d4: 34129073 csrw mepc,t0 + 800003d8: 30200073 mret + 800003dc: 00200337 lui t1,0x200 + 800003e0: 30032073 csrs mstatus,t1 + 800003e4: fedff06f j 800003d0 + 800003e8: 00100337 lui t1,0x100 + 800003ec: 30032073 csrs mstatus,t1 + 800003f0: fe1ff06f j 800003d0 + 800003f4: 00400337 lui t1,0x400 + 800003f8: 30032073 csrs mstatus,t1 + 800003fc: fd5ff06f j 800003d0 + 80000400: fd1ff06f j 800003d0 + 80000404: c0001073 unimp + 80000408: 0000 unimp + 8000040a: 0000 unimp + 8000040c: 0000 unimp + 8000040e: 0000 unimp + 80000410: 0000 unimp + 80000412: 0000 unimp + 80000414: 0000 unimp + 80000416: 0000 unimp + 80000418: 0000 unimp + 8000041a: 0000 unimp + 8000041c: 0000 unimp + 8000041e: 0000 unimp + 80000420: 0000 unimp + 80000422: 0000 unimp + 80000424: 0000 unimp + 80000426: 0000 unimp + 80000428: 0000 unimp + 8000042a: 0000 unimp + 8000042c: 0000 unimp + 8000042e: 0000 unimp + 80000430: 0000 unimp + 80000432: 0000 unimp + 80000434: 0000 unimp + 80000436: 0000 unimp + 80000438: 0000 unimp + 8000043a: 0000 unimp + 8000043c: 0000 unimp + 8000043e: 0000 unimp + 80000440: 0000 unimp + 80000442: 0000 unimp + 80000444: 0000 unimp + 80000446: 0000 unimp + 80000448: 0000 unimp + 8000044a: 0000 unimp + 8000044c: 0000 unimp + 8000044e: 0000 unimp + 80000450: 0000 unimp + 80000452: 0000 unimp + 80000454: 0000 unimp + 80000456: 0000 unimp + 80000458: 0000 unimp + 8000045a: 0000 unimp + 8000045c: 0000 unimp + 8000045e: 0000 unimp + 80000460: 0000 unimp + 80000462: 0000 unimp + 80000464: 0000 unimp + 80000466: 0000 unimp + 80000468: 0000 unimp + 8000046a: 0000 unimp + 8000046c: 0000 unimp + 8000046e: 0000 unimp + 80000470: 0000 unimp + 80000472: 0000 unimp + 80000474: 0000 unimp + 80000476: 0000 unimp + 80000478: 0000 unimp + 8000047a: 0000 unimp + 8000047c: 0000 unimp + 8000047e: 0000 unimp + 80000480: 0000 unimp + 80000482: 0000 unimp + 80000484: 0000 unimp + 80000486: 0000 unimp + 80000488: 0000 unimp + 8000048a: 0000 unimp + 8000048c: 0000 unimp + 8000048e: 0000 unimp + 80000490: 0000 unimp + 80000492: 0000 unimp + 80000494: 0000 unimp + 80000496: 0000 unimp + 80000498: 0000 unimp + 8000049a: 0000 unimp + 8000049c: 0000 unimp + 8000049e: 0000 unimp + 800004a0: 0000 unimp + 800004a2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-illegal.elf b/test/riscv/tests/rv64mi-p-illegal.elf new file mode 100644 index 00000000..7441498d Binary files /dev/null and b/test/riscv/tests/rv64mi-p-illegal.elf differ diff --git a/test/riscv/tests/rv64mi-p-ma_addr.dump b/test/riscv/tests/rv64mi-p-ma_addr.dump new file mode 100644 index 00000000..b5595679 --- /dev/null +++ b/test/riscv/tests/rv64mi-p-ma_addr.dump @@ -0,0 +1,563 @@ + +rv64mi-p-ma_addr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 5e8f0f13 addi t5,t5,1512 # 80000608 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00002417 auipc s0,0x2 + 8000010c: ef840413 addi s0,s0,-264 # 80002000 + 80000110: 00400493 li s1,4 + 80000114: 00200193 li gp,2 + 80000118: 00000397 auipc t2,0x0 + 8000011c: 01c38393 addi t2,t2,28 # 80000134 + 80000120: 00140313 addi t1,s0,1 + 80000124: 00141303 lh t1,1(s0) + 80000128: ffffc3b7 lui t2,0xffffc + 8000012c: bcc3839b addiw t2,t2,-1076 + 80000130: 4a731c63 bne t1,t2,800005e8 + 80000134: 00300193 li gp,3 + 80000138: 00000397 auipc t2,0x0 + 8000013c: 01c38393 addi t2,t2,28 # 80000154 + 80000140: 00140313 addi t1,s0,1 + 80000144: 00145303 lhu t1,1(s0) + 80000148: 0000c3b7 lui t2,0xc + 8000014c: bcc3839b addiw t2,t2,-1076 + 80000150: 48731c63 bne t1,t2,800005e8 + 80000154: 00400193 li gp,4 + 80000158: 00000397 auipc t2,0x0 + 8000015c: 01c38393 addi t2,t2,28 # 80000174 + 80000160: 00140313 addi t1,s0,1 + 80000164: 00142303 lw t1,1(s0) + 80000168: 99aac3b7 lui t2,0x99aac + 8000016c: bcc3839b addiw t2,t2,-1076 + 80000170: 46731c63 bne t1,t2,800005e8 + 80000174: 00500193 li gp,5 + 80000178: 00000397 auipc t2,0x0 + 8000017c: 01c38393 addi t2,t2,28 # 80000194 + 80000180: 00240313 addi t1,s0,2 + 80000184: 00242303 lw t1,2(s0) + 80000188: 8899b3b7 lui t2,0x8899b + 8000018c: abb3839b addiw t2,t2,-1349 + 80000190: 44731c63 bne t1,t2,800005e8 + 80000194: 00600193 li gp,6 + 80000198: 00000397 auipc t2,0x0 + 8000019c: 01c38393 addi t2,t2,28 # 800001b4 + 800001a0: 00340313 addi t1,s0,3 + 800001a4: 00342303 lw t1,3(s0) + 800001a8: 7788a3b7 lui t2,0x7788a + 800001ac: 9aa3839b addiw t2,t2,-1622 + 800001b0: 42731c63 bne t1,t2,800005e8 + 800001b4: 00700193 li gp,7 + 800001b8: 00000397 auipc t2,0x0 + 800001bc: 02438393 addi t2,t2,36 # 800001dc + 800001c0: 00140313 addi t1,s0,1 + 800001c4: 00146303 lwu t1,1(s0) + 800001c8: 000263b7 lui t2,0x26 + 800001cc: 6ab3839b addiw t2,t2,1707 + 800001d0: 00e39393 slli t2,t2,0xe + 800001d4: bcc38393 addi t2,t2,-1076 # 25bcc <_start-0x7ffda434> + 800001d8: 40731863 bne t1,t2,800005e8 + 800001dc: 00800193 li gp,8 + 800001e0: 00000397 auipc t2,0x0 + 800001e4: 02438393 addi t2,t2,36 # 80000204 + 800001e8: 00240313 addi t1,s0,2 + 800001ec: 00246303 lwu t1,2(s0) + 800001f0: 000893b7 lui t2,0x89 + 800001f4: 99b3839b addiw t2,t2,-1637 + 800001f8: 00c39393 slli t2,t2,0xc + 800001fc: abb38393 addi t2,t2,-1349 # 88abb <_start-0x7ff77545> + 80000200: 3e731463 bne t1,t2,800005e8 + 80000204: 00900193 li gp,9 + 80000208: 00000397 auipc t2,0x0 + 8000020c: 01c38393 addi t2,t2,28 # 80000224 + 80000210: 00340313 addi t1,s0,3 + 80000214: 00346303 lwu t1,3(s0) + 80000218: 7788a3b7 lui t2,0x7788a + 8000021c: 9aa3839b addiw t2,t2,-1622 + 80000220: 3c731463 bne t1,t2,800005e8 + 80000224: 00a00193 li gp,10 + 80000228: 00000397 auipc t2,0x0 + 8000022c: 03438393 addi t2,t2,52 # 8000025c + 80000230: 00140313 addi t1,s0,1 + 80000234: 00143303 ld t1,1(s0) + 80000238: 00aad3b7 lui t2,0xaad + 8000023c: cef3839b addiw t2,t2,-785 + 80000240: 00c39393 slli t2,t2,0xc + 80000244: 11338393 addi t2,t2,275 # aad113 <_start-0x7f552eed> + 80000248: 00d39393 slli t2,t2,0xd + 8000024c: 6ab38393 addi t2,t2,1707 + 80000250: 00e39393 slli t2,t2,0xe + 80000254: bcc38393 addi t2,t2,-1076 + 80000258: 38731863 bne t1,t2,800005e8 + 8000025c: 00b00193 li gp,11 + 80000260: 00000397 auipc t2,0x0 + 80000264: 03438393 addi t2,t2,52 # 80000294 + 80000268: 00240313 addi t1,s0,2 + 8000026c: 00243303 ld t1,2(s0) + 80000270: 044553b7 lui t2,0x4455 + 80000274: 6673839b addiw t2,t2,1639 + 80000278: 00c39393 slli t2,t2,0xc + 8000027c: 78938393 addi t2,t2,1929 # 4455789 <_start-0x7bbaa877> + 80000280: 00c39393 slli t2,t2,0xc + 80000284: 99b38393 addi t2,t2,-1637 + 80000288: 00c39393 slli t2,t2,0xc + 8000028c: abb38393 addi t2,t2,-1349 + 80000290: 34731c63 bne t1,t2,800005e8 + 80000294: 00c00193 li gp,12 + 80000298: 00000397 auipc t2,0x0 + 8000029c: 03438393 addi t2,t2,52 # 800002cc + 800002a0: 00340313 addi t1,s0,3 + 800002a4: 00343303 ld t1,3(s0) + 800002a8: 006693b7 lui t2,0x669 + 800002ac: 8ab3839b addiw t2,t2,-1877 + 800002b0: 00c39393 slli t2,t2,0xc + 800002b4: ccf38393 addi t2,t2,-817 # 668ccf <_start-0x7f997331> + 800002b8: 00e39393 slli t2,t2,0xe + 800002bc: c4538393 addi t2,t2,-955 + 800002c0: 00d39393 slli t2,t2,0xd + 800002c4: 9aa38393 addi t2,t2,-1622 + 800002c8: 32731063 bne t1,t2,800005e8 + 800002cc: 00d00193 li gp,13 + 800002d0: 00000397 auipc t2,0x0 + 800002d4: 03438393 addi t2,t2,52 # 80000304 + 800002d8: 00440313 addi t1,s0,4 + 800002dc: 00443303 ld t1,4(s0) + 800002e0: 0111a3b7 lui t2,0x111a + 800002e4: a233839b addiw t2,t2,-1501 + 800002e8: 00c39393 slli t2,t2,0xc + 800002ec: ab338393 addi t2,t2,-1357 # 1119ab3 <_start-0x7eee654d> + 800002f0: 00d39393 slli t2,t2,0xd + 800002f4: 77938393 addi t2,t2,1913 + 800002f8: 00c39393 slli t2,t2,0xc + 800002fc: 89938393 addi t2,t2,-1895 + 80000300: 2e731463 bne t1,t2,800005e8 + 80000304: 00e00193 li gp,14 + 80000308: 00000397 auipc t2,0x0 + 8000030c: 03438393 addi t2,t2,52 # 8000033c + 80000310: 00540313 addi t1,s0,5 + 80000314: 00543303 ld t1,5(s0) + 80000318: 004493b7 lui t2,0x449 + 8000031c: 8cd3839b addiw t2,t2,-1843 + 80000320: 00e39393 slli t2,t2,0xe + 80000324: 45538393 addi t2,t2,1109 # 449455 <_start-0x7fbb6bab> + 80000328: 00c39393 slli t2,t2,0xc + 8000032c: 66738393 addi t2,t2,1639 + 80000330: 00c39393 slli t2,t2,0xc + 80000334: 78838393 addi t2,t2,1928 + 80000338: 2a731863 bne t1,t2,800005e8 + 8000033c: 00f00193 li gp,15 + 80000340: 00000397 auipc t2,0x0 + 80000344: 03438393 addi t2,t2,52 # 80000374 + 80000348: 00640313 addi t1,s0,6 + 8000034c: 00643303 ld t1,6(s0) + 80000350: ffb843b7 lui t2,0xffb84 + 80000354: 4893839b addiw t2,t2,1161 + 80000358: 00c39393 slli t2,t2,0xc + 8000035c: cd138393 addi t2,t2,-815 # ffffffffffb83cd1 <_end+0xffffffff7fb81bc1> + 80000360: 00d39393 slli t2,t2,0xd + 80000364: 2ab38393 addi t2,t2,683 + 80000368: 00d39393 slli t2,t2,0xd + 8000036c: 67738393 addi t2,t2,1655 + 80000370: 26731c63 bne t1,t2,800005e8 + 80000374: 01000193 li gp,16 + 80000378: 00000397 auipc t2,0x0 + 8000037c: 02c38393 addi t2,t2,44 # 800003a4 + 80000380: 00740313 addi t1,s0,7 + 80000384: 00743303 ld t1,7(s0) + 80000388: ee1123b7 lui t2,0xee112 + 8000038c: 2333839b addiw t2,t2,563 + 80000390: 00c39393 slli t2,t2,0xc + 80000394: 44538393 addi t2,t2,1093 # ffffffffee112445 <_end+0xffffffff6e110335> + 80000398: 00c39393 slli t2,t2,0xc + 8000039c: 56638393 addi t2,t2,1382 + 800003a0: 24731463 bne t1,t2,800005e8 + 800003a4: 00600493 li s1,6 + 800003a8: 01600193 li gp,22 + 800003ac: 00000397 auipc t2,0x0 + 800003b0: 03038393 addi t2,t2,48 # 800003dc + 800003b4: 00140313 addi t1,s0,1 + 800003b8: 000410a3 sh zero,1(s0) + 800003bc: 00040303 lb t1,0(s0) + 800003c0: 22030463 beqz t1,800005e8 + 800003c4: 00340303 lb t1,3(s0) + 800003c8: 22030063 beqz t1,800005e8 + 800003cc: 00140303 lb t1,1(s0) + 800003d0: 20031c63 bnez t1,800005e8 + 800003d4: 00240303 lb t1,2(s0) + 800003d8: 20031863 bnez t1,800005e8 + 800003dc: 01700193 li gp,23 + 800003e0: 00000397 auipc t2,0x0 + 800003e4: 03038393 addi t2,t2,48 # 80000410 + 800003e8: 00540313 addi t1,s0,5 + 800003ec: 000422a3 sw zero,5(s0) + 800003f0: 00440303 lb t1,4(s0) + 800003f4: 1e030a63 beqz t1,800005e8 + 800003f8: 00940303 lb t1,9(s0) + 800003fc: 1e030663 beqz t1,800005e8 + 80000400: 00540303 lb t1,5(s0) + 80000404: 1e031263 bnez t1,800005e8 + 80000408: 00840303 lb t1,8(s0) + 8000040c: 1c031e63 bnez t1,800005e8 + 80000410: 01800193 li gp,24 + 80000414: 00000397 auipc t2,0x0 + 80000418: 03038393 addi t2,t2,48 # 80000444 + 8000041c: 00a40313 addi t1,s0,10 + 80000420: 00042523 sw zero,10(s0) + 80000424: 00940303 lb t1,9(s0) + 80000428: 1c030063 beqz t1,800005e8 + 8000042c: 00e40303 lb t1,14(s0) + 80000430: 1a030c63 beqz t1,800005e8 + 80000434: 00a40303 lb t1,10(s0) + 80000438: 1a031863 bnez t1,800005e8 + 8000043c: 00d40303 lb t1,13(s0) + 80000440: 1a031463 bnez t1,800005e8 + 80000444: 01900193 li gp,25 + 80000448: 00000397 auipc t2,0x0 + 8000044c: 03038393 addi t2,t2,48 # 80000478 + 80000450: 00f40313 addi t1,s0,15 + 80000454: 000427a3 sw zero,15(s0) + 80000458: 00e40303 lb t1,14(s0) + 8000045c: 18030663 beqz t1,800005e8 + 80000460: 01340303 lb t1,19(s0) + 80000464: 18030263 beqz t1,800005e8 + 80000468: 00f40303 lb t1,15(s0) + 8000046c: 16031e63 bnez t1,800005e8 + 80000470: 01240303 lb t1,18(s0) + 80000474: 16031a63 bnez t1,800005e8 + 80000478: 01a00193 li gp,26 + 8000047c: 00000397 auipc t2,0x0 + 80000480: 03038393 addi t2,t2,48 # 800004ac + 80000484: 01940313 addi t1,s0,25 + 80000488: 00043ca3 sd zero,25(s0) + 8000048c: 01840303 lb t1,24(s0) + 80000490: 14030c63 beqz t1,800005e8 + 80000494: 02140303 lb t1,33(s0) + 80000498: 14030863 beqz t1,800005e8 + 8000049c: 01940303 lb t1,25(s0) + 800004a0: 14031463 bnez t1,800005e8 + 800004a4: 02040303 lb t1,32(s0) + 800004a8: 14031063 bnez t1,800005e8 + 800004ac: 01b00193 li gp,27 + 800004b0: 00000397 auipc t2,0x0 + 800004b4: 03038393 addi t2,t2,48 # 800004e0 + 800004b8: 02240313 addi t1,s0,34 + 800004bc: 02043123 sd zero,34(s0) + 800004c0: 02140303 lb t1,33(s0) + 800004c4: 12030263 beqz t1,800005e8 + 800004c8: 02a40303 lb t1,42(s0) + 800004cc: 10030e63 beqz t1,800005e8 + 800004d0: 02240303 lb t1,34(s0) + 800004d4: 10031a63 bnez t1,800005e8 + 800004d8: 02940303 lb t1,41(s0) + 800004dc: 10031663 bnez t1,800005e8 + 800004e0: 01c00193 li gp,28 + 800004e4: 00000397 auipc t2,0x0 + 800004e8: 03038393 addi t2,t2,48 # 80000514 + 800004ec: 02b40313 addi t1,s0,43 + 800004f0: 020435a3 sd zero,43(s0) + 800004f4: 02a40303 lb t1,42(s0) + 800004f8: 0e030863 beqz t1,800005e8 + 800004fc: 03340303 lb t1,51(s0) + 80000500: 0e030463 beqz t1,800005e8 + 80000504: 02b40303 lb t1,43(s0) + 80000508: 0e031063 bnez t1,800005e8 + 8000050c: 03240303 lb t1,50(s0) + 80000510: 0c031c63 bnez t1,800005e8 + 80000514: 01d00193 li gp,29 + 80000518: 00000397 auipc t2,0x0 + 8000051c: 03038393 addi t2,t2,48 # 80000548 + 80000520: 03440313 addi t1,s0,52 + 80000524: 02043a23 sd zero,52(s0) + 80000528: 03340303 lb t1,51(s0) + 8000052c: 0a030e63 beqz t1,800005e8 + 80000530: 03c40303 lb t1,60(s0) + 80000534: 0a030a63 beqz t1,800005e8 + 80000538: 03440303 lb t1,52(s0) + 8000053c: 0a031663 bnez t1,800005e8 + 80000540: 03b40303 lb t1,59(s0) + 80000544: 0a031263 bnez t1,800005e8 + 80000548: 01e00193 li gp,30 + 8000054c: 00000397 auipc t2,0x0 + 80000550: 03038393 addi t2,t2,48 # 8000057c + 80000554: 03d40313 addi t1,s0,61 + 80000558: 02043ea3 sd zero,61(s0) + 8000055c: 03c40303 lb t1,60(s0) + 80000560: 08030463 beqz t1,800005e8 + 80000564: 04540303 lb t1,69(s0) + 80000568: 08030063 beqz t1,800005e8 + 8000056c: 03d40303 lb t1,61(s0) + 80000570: 06031c63 bnez t1,800005e8 + 80000574: 04440303 lb t1,68(s0) + 80000578: 06031863 bnez t1,800005e8 + 8000057c: 01f00193 li gp,31 + 80000580: 00000397 auipc t2,0x0 + 80000584: 03038393 addi t2,t2,48 # 800005b0 + 80000588: 04640313 addi t1,s0,70 + 8000058c: 04043323 sd zero,70(s0) + 80000590: 04540303 lb t1,69(s0) + 80000594: 04030a63 beqz t1,800005e8 + 80000598: 04e40303 lb t1,78(s0) + 8000059c: 04030663 beqz t1,800005e8 + 800005a0: 04640303 lb t1,70(s0) + 800005a4: 04031263 bnez t1,800005e8 + 800005a8: 04d40303 lb t1,77(s0) + 800005ac: 02031e63 bnez t1,800005e8 + 800005b0: 02000193 li gp,32 + 800005b4: 00000397 auipc t2,0x0 + 800005b8: 03038393 addi t2,t2,48 # 800005e4 + 800005bc: 04f40313 addi t1,s0,79 + 800005c0: 040437a3 sd zero,79(s0) + 800005c4: 04e40303 lb t1,78(s0) + 800005c8: 02030063 beqz t1,800005e8 + 800005cc: 05740303 lb t1,87(s0) + 800005d0: 00030c63 beqz t1,800005e8 + 800005d4: 04f40303 lb t1,79(s0) + 800005d8: 00031863 bnez t1,800005e8 + 800005dc: 05640303 lb t1,86(s0) + 800005e0: 00031463 bnez t1,800005e8 + 800005e4: 00301c63 bne zero,gp,800005fc + +00000000800005e8 : + 800005e8: 0ff0000f fence + 800005ec: 00018063 beqz gp,800005ec + 800005f0: 00119193 slli gp,gp,0x1 + 800005f4: 0011e193 ori gp,gp,1 + 800005f8: 00000073 ecall + +00000000800005fc : + 800005fc: 0ff0000f fence + 80000600: 00100193 li gp,1 + 80000604: 00000073 ecall + +0000000080000608 : + 80000608: 342022f3 csrr t0,mcause + 8000060c: fc929ee3 bne t0,s1,800005e8 + 80000610: 343022f3 csrr t0,mbadaddr + 80000614: fc629ae3 bne t0,t1,800005e8 + 80000618: 00028283 lb t0,0(t0) + 8000061c: fc0286e3 beqz t0,800005e8 + 80000620: 34139073 csrw mepc,t2 + 80000624: 30200073 mret + 80000628: c0001073 unimp + 8000062c: 0000 unimp + 8000062e: 0000 unimp + 80000630: 0000 unimp + 80000632: 0000 unimp + 80000634: 0000 unimp + 80000636: 0000 unimp + 80000638: 0000 unimp + 8000063a: 0000 unimp + 8000063c: 0000 unimp + 8000063e: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: ccdd beqz s1,800020be + 80002002: 8899aabb 0x8899aabb + 80002006: 44556677 0x44556677 + 8000200a: ee112233 0xee112233 + 8000200e: eeff 0xeeff + 80002010: 5050 lw a2,36(s0) + 80002012: 5050 lw a2,36(s0) + 80002014: 5050 lw a2,36(s0) + 80002016: 5050 lw a2,36(s0) + 80002018: 5050 lw a2,36(s0) + 8000201a: 5050 lw a2,36(s0) + 8000201c: 5050 lw a2,36(s0) + 8000201e: 5050 lw a2,36(s0) + 80002020: 5050 lw a2,36(s0) + 80002022: 5050 lw a2,36(s0) + 80002024: 5050 lw a2,36(s0) + 80002026: 5050 lw a2,36(s0) + 80002028: 5050 lw a2,36(s0) + 8000202a: 5050 lw a2,36(s0) + 8000202c: 5050 lw a2,36(s0) + 8000202e: 5050 lw a2,36(s0) + 80002030: 5050 lw a2,36(s0) + 80002032: 5050 lw a2,36(s0) + 80002034: 5050 lw a2,36(s0) + 80002036: 5050 lw a2,36(s0) + 80002038: 5050 lw a2,36(s0) + 8000203a: 5050 lw a2,36(s0) + 8000203c: 5050 lw a2,36(s0) + 8000203e: 5050 lw a2,36(s0) + 80002040: 5050 lw a2,36(s0) + 80002042: 5050 lw a2,36(s0) + 80002044: 5050 lw a2,36(s0) + 80002046: 5050 lw a2,36(s0) + 80002048: 5050 lw a2,36(s0) + 8000204a: 5050 lw a2,36(s0) + 8000204c: 5050 lw a2,36(s0) + 8000204e: 5050 lw a2,36(s0) + 80002050: 5050 lw a2,36(s0) + 80002052: 5050 lw a2,36(s0) + 80002054: 5050 lw a2,36(s0) + 80002056: 5050 lw a2,36(s0) + 80002058: 5050 lw a2,36(s0) + 8000205a: 5050 lw a2,36(s0) + 8000205c: 5050 lw a2,36(s0) + 8000205e: 5050 lw a2,36(s0) + 80002060: 5050 lw a2,36(s0) + 80002062: 5050 lw a2,36(s0) + 80002064: 5050 lw a2,36(s0) + 80002066: 5050 lw a2,36(s0) + 80002068: 5050 lw a2,36(s0) + 8000206a: 5050 lw a2,36(s0) + 8000206c: 5050 lw a2,36(s0) + 8000206e: 5050 lw a2,36(s0) + 80002070: 5050 lw a2,36(s0) + 80002072: 5050 lw a2,36(s0) + 80002074: 5050 lw a2,36(s0) + 80002076: 5050 lw a2,36(s0) + 80002078: 5050 lw a2,36(s0) + 8000207a: 5050 lw a2,36(s0) + 8000207c: 5050 lw a2,36(s0) + 8000207e: 5050 lw a2,36(s0) + 80002080: 5050 lw a2,36(s0) + 80002082: 5050 lw a2,36(s0) + 80002084: 5050 lw a2,36(s0) + 80002086: 5050 lw a2,36(s0) + 80002088: 5050 lw a2,36(s0) + 8000208a: 5050 lw a2,36(s0) + 8000208c: 5050 lw a2,36(s0) + 8000208e: 5050 lw a2,36(s0) + 80002090: 5050 lw a2,36(s0) + 80002092: 5050 lw a2,36(s0) + 80002094: 5050 lw a2,36(s0) + 80002096: 5050 lw a2,36(s0) + 80002098: 5050 lw a2,36(s0) + 8000209a: 5050 lw a2,36(s0) + 8000209c: 5050 lw a2,36(s0) + 8000209e: 5050 lw a2,36(s0) + 800020a0: 5050 lw a2,36(s0) + 800020a2: 5050 lw a2,36(s0) + 800020a4: 5050 lw a2,36(s0) + 800020a6: 5050 lw a2,36(s0) + 800020a8: 5050 lw a2,36(s0) + 800020aa: 5050 lw a2,36(s0) + 800020ac: 5050 lw a2,36(s0) + 800020ae: 5050 lw a2,36(s0) + 800020b0: 5050 lw a2,36(s0) + 800020b2: 5050 lw a2,36(s0) + 800020b4: 5050 lw a2,36(s0) + 800020b6: 5050 lw a2,36(s0) + 800020b8: 5050 lw a2,36(s0) + 800020ba: 5050 lw a2,36(s0) + 800020bc: 5050 lw a2,36(s0) + 800020be: 5050 lw a2,36(s0) + 800020c0: 5050 lw a2,36(s0) + 800020c2: 5050 lw a2,36(s0) + 800020c4: 5050 lw a2,36(s0) + 800020c6: 5050 lw a2,36(s0) + 800020c8: 5050 lw a2,36(s0) + 800020ca: 5050 lw a2,36(s0) + 800020cc: 5050 lw a2,36(s0) + 800020ce: 5050 lw a2,36(s0) + 800020d0: 5050 lw a2,36(s0) + 800020d2: 5050 lw a2,36(s0) + 800020d4: 5050 lw a2,36(s0) + 800020d6: 5050 lw a2,36(s0) + 800020d8: 5050 lw a2,36(s0) + 800020da: 5050 lw a2,36(s0) + 800020dc: 5050 lw a2,36(s0) + 800020de: 5050 lw a2,36(s0) + 800020e0: 5050 lw a2,36(s0) + 800020e2: 5050 lw a2,36(s0) + 800020e4: 5050 lw a2,36(s0) + 800020e6: 5050 lw a2,36(s0) + 800020e8: 5050 lw a2,36(s0) + 800020ea: 5050 lw a2,36(s0) + 800020ec: 5050 lw a2,36(s0) + 800020ee: 5050 lw a2,36(s0) + 800020f0: 5050 lw a2,36(s0) + 800020f2: 5050 lw a2,36(s0) + 800020f4: 5050 lw a2,36(s0) + 800020f6: 5050 lw a2,36(s0) + 800020f8: 5050 lw a2,36(s0) + 800020fa: 5050 lw a2,36(s0) + 800020fc: 5050 lw a2,36(s0) + 800020fe: 5050 lw a2,36(s0) + 80002100: 5050 lw a2,36(s0) + 80002102: 5050 lw a2,36(s0) + 80002104: 5050 lw a2,36(s0) + 80002106: 5050 lw a2,36(s0) + 80002108: 5050 lw a2,36(s0) + 8000210a: 5050 lw a2,36(s0) + 8000210c: 5050 lw a2,36(s0) + 8000210e: 0050 addi a2,sp,4 diff --git a/test/riscv/tests/rv64mi-p-ma_addr.elf b/test/riscv/tests/rv64mi-p-ma_addr.elf new file mode 100644 index 00000000..fc326628 Binary files /dev/null and b/test/riscv/tests/rv64mi-p-ma_addr.elf differ diff --git a/test/riscv/tests/rv64mi-p-ma_fetch.dump b/test/riscv/tests/rv64mi-p-ma_fetch.dump new file mode 100644 index 00000000..6a5285a6 --- /dev/null +++ b/test/riscv/tests/rv64mi-p-ma_fetch.dump @@ -0,0 +1,219 @@ + +rv64mi-p-ma_fetch: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 208f0f13 addi t5,t5,520 # 80000228 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + 8000010c: 00000313 li t1,0 + 80000110: 00000297 auipc t0,0x0 + 80000114: 00c28293 addi t0,t0,12 # 8000011c + 80000118: 00228367 jalr t1,2(t0) + 8000011c: a011 j 80000120 + 8000011e: a019 j 80000124 + 80000120: 0e80006f j 80000208 + 80000124: 00300193 li gp,3 + 80000128: 00000297 auipc t0,0x0 + 8000012c: 00c28293 addi t0,t0,12 # 80000134 + 80000130: 00128367 jalr t1,1(t0) + 80000134: 0080006f j 8000013c + 80000138: 0d00006f j 80000208 + 8000013c: 00400193 li gp,4 + 80000140: 00000313 li t1,0 + 80000144: 00000297 auipc t0,0x0 + 80000148: 00c28293 addi t0,t0,12 # 80000150 + 8000014c: 00328367 jalr t1,3(t0) + 80000150: a011 j 80000154 + 80000152: a019 j 80000158 + 80000154: 0b40006f j 80000208 + 80000158: 00500193 li gp,5 + 8000015c: 00000313 li t1,0 + 80000160: 00000297 auipc t0,0x0 + 80000164: 00c28293 addi t0,t0,12 # 8000016c + 80000168: 0060036f jal t1,8000016e + 8000016c: a011 j 80000170 + 8000016e: a019 j 80000174 + 80000170: 0980006f j 80000208 + 80000174: 00600193 li gp,6 + 80000178: 00000313 li t1,0 + 8000017c: 00000297 auipc t0,0x0 + 80000180: 00c28293 addi t0,t0,12 # 80000188 + 80000184: 00000363 beqz zero,8000018a + 80000188: a011 j 8000018c + 8000018a: a019 j 80000190 + 8000018c: 07c0006f j 80000208 + 80000190: 00700193 li gp,7 + 80000194: 00001563 bnez zero,8000019e + 80000198: 00c0006f j 800001a4 + 8000019c: a009 j 8000019e + 8000019e: a009 j 800001a0 + 800001a0: 0680006f j 80000208 + 800001a4: 00800193 li gp,8 + 800001a8: 301023f3 csrr t2,misa + 800001ac: 0043f393 andi t2,t2,4 + 800001b0: 04038863 beqz t2,80000200 + 800001b4: 0001 nop + 800001b6: 30127073 csrci misa,4 + 800001ba: 0001 nop + 800001bc: 301023f3 csrr t2,misa + 800001c0: 0043f393 andi t2,t2,4 + 800001c4: 04038263 beqz t2,80000208 + 800001c8: 00000297 auipc t0,0x0 + 800001cc: 03428293 addi t0,t0,52 # 800001fc + 800001d0: ffe28293 addi t0,t0,-2 + 800001d4: 34129073 csrw mepc,t0 + 800001d8: 30127073 csrci misa,4 + 800001dc: 301023f3 csrr t2,misa + 800001e0: 0043f393 andi t2,t2,4 + 800001e4: 00039e63 bnez t2,80000200 + 800001e8: 000023b7 lui t2,0x2 + 800001ec: 8003839b addiw t2,t2,-2048 + 800001f0: 3003a073 csrs mstatus,t2 + 800001f4: 30200073 mret + 800001f8: 00000263 beqz zero,800001fc + 800001fc: 30126073 csrsi misa,4 + 80000200: 01c0006f j 8000021c + 80000204: 00301c63 bne zero,gp,8000021c + +0000000080000208 : + 80000208: 0ff0000f fence + 8000020c: 00018063 beqz gp,8000020c + 80000210: 00119193 slli gp,gp,0x1 + 80000214: 0011e193 ori gp,gp,1 + 80000218: 00000073 ecall + +000000008000021c : + 8000021c: 0ff0000f fence + 80000220: 00100193 li gp,1 + 80000224: 00000073 ecall + +0000000080000228 : + 80000228: 00200513 li a0,2 + 8000022c: 02a18063 beq gp,a0,8000024c + 80000230: 00400513 li a0,4 + 80000234: 00a18c63 beq gp,a0,8000024c + 80000238: 00500513 li a0,5 + 8000023c: 00a18863 beq gp,a0,8000024c + 80000240: 00600513 li a0,6 + 80000244: 00a18463 beq gp,a0,8000024c + 80000248: fc1ff06f j 80000208 + 8000024c: fa031ee3 bnez t1,80000208 + 80000250: 00000593 li a1,0 + 80000254: 34202573 csrr a0,mcause + 80000258: fab518e3 bne a0,a1,80000208 + 8000025c: 341025f3 csrr a1,mepc + 80000260: 00458593 addi a1,a1,4 + 80000264: fab292e3 bne t0,a1,80000208 + 80000268: 34302573 csrr a0,mbadaddr + 8000026c: 00050663 beqz a0,80000278 + 80000270: ffe50513 addi a0,a0,-2 # 1ffe <_start-0x7fffe002> + 80000274: f8551ae3 bne a0,t0,80000208 + 80000278: 00c58593 addi a1,a1,12 + 8000027c: 34159073 csrw mepc,a1 + 80000280: 30200073 mret + 80000284: c0001073 unimp + 80000288: 0000 unimp + 8000028a: 0000 unimp + 8000028c: 0000 unimp + 8000028e: 0000 unimp + 80000290: 0000 unimp + 80000292: 0000 unimp + 80000294: 0000 unimp + 80000296: 0000 unimp + 80000298: 0000 unimp + 8000029a: 0000 unimp + 8000029c: 0000 unimp + 8000029e: 0000 unimp + 800002a0: 0000 unimp + 800002a2: 0000 unimp + 800002a4: 0000 unimp + 800002a6: 0000 unimp + 800002a8: 0000 unimp + 800002aa: 0000 unimp + 800002ac: 0000 unimp + 800002ae: 0000 unimp + 800002b0: 0000 unimp + 800002b2: 0000 unimp + 800002b4: 0000 unimp + 800002b6: 0000 unimp + 800002b8: 0000 unimp + 800002ba: 0000 unimp + 800002bc: 0000 unimp + 800002be: 0000 unimp + 800002c0: 0000 unimp + 800002c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-ma_fetch.elf b/test/riscv/tests/rv64mi-p-ma_fetch.elf new file mode 100644 index 00000000..40ffdf38 Binary files /dev/null and b/test/riscv/tests/rv64mi-p-ma_fetch.elf differ diff --git a/test/riscv/tests/rv64mi-p-mcsr.dump b/test/riscv/tests/rv64mi-p-mcsr.dump new file mode 100644 index 00000000..befb1931 --- /dev/null +++ b/test/riscv/tests/rv64mi-p-mcsr.dump @@ -0,0 +1,126 @@ + +rv64mi-p-mcsr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + +0000000080000108 : + 80000108: 30102573 csrr a0,misa + 8000010c: 03e55513 srli a0,a0,0x3e + 80000110: 00200e93 li t4,2 + 80000114: 00200193 li gp,2 + 80000118: 03d51863 bne a0,t4,80000148 + +000000008000011c : + 8000011c: f1402573 csrr a0,mhartid + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 03d51063 bne a0,t4,80000148 + 8000012c: f1302573 csrr a0,mimpid + 80000130: f1202573 csrr a0,marchid + 80000134: f1102573 csrr a0,mvendorid + 80000138: 00000293 li t0,0 + 8000013c: 3052a073 csrs mtvec,t0 + 80000140: 3412a073 csrs mepc,t0 + 80000144: 00301c63 bne zero,gp,8000015c + +0000000080000148 : + 80000148: 0ff0000f fence + 8000014c: 00018063 beqz gp,8000014c + 80000150: 00119193 slli gp,gp,0x1 + 80000154: 0011e193 ori gp,gp,1 + 80000158: 00000073 ecall + +000000008000015c : + 8000015c: 0ff0000f fence + 80000160: 00100193 li gp,1 + 80000164: 00000073 ecall + 80000168: c0001073 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-mcsr.elf b/test/riscv/tests/rv64mi-p-mcsr.elf new file mode 100644 index 00000000..4ce3d35f Binary files /dev/null and b/test/riscv/tests/rv64mi-p-mcsr.elf differ diff --git a/test/riscv/tests/rv64mi-p-scall.dump b/test/riscv/tests/rv64mi-p-scall.dump new file mode 100644 index 00000000..940db038 --- /dev/null +++ b/test/riscv/tests/rv64mi-p-scall.dump @@ -0,0 +1,147 @@ + +rv64mi-p-scall: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 158f0f13 addi t5,t5,344 # 80000178 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + 8000010c: 00800313 li t1,8 + 80000110: 000022b7 lui t0,0x2 + 80000114: 8002829b addiw t0,t0,-2048 + 80000118: 3002b073 csrc mstatus,t0 + 8000011c: 30002373 csrr t1,mstatus + 80000120: 0062f2b3 and t0,t0,t1 + 80000124: 00028463 beqz t0,8000012c + 80000128: 00b00313 li t1,11 + 8000012c: 000022b7 lui t0,0x2 + 80000130: 8002829b addiw t0,t0,-2048 + 80000134: 3002b073 csrc mstatus,t0 + 80000138: 00000297 auipc t0,0x0 + 8000013c: 01028293 addi t0,t0,16 # 80000148 + 80000140: 34129073 csrw mepc,t0 + 80000144: 30200073 mret + 80000148: 00100193 li gp,1 + +000000008000014c : + 8000014c: 00000073 ecall + 80000150: 0080006f j 80000158 + 80000154: 00301c63 bne zero,gp,8000016c + +0000000080000158 : + 80000158: 0ff0000f fence + 8000015c: 00018063 beqz gp,8000015c + 80000160: 00119193 slli gp,gp,0x1 + 80000164: 0011e193 ori gp,gp,1 + 80000168: 00000073 ecall + +000000008000016c : + 8000016c: 0ff0000f fence + 80000170: 00100193 li gp,1 + 80000174: 00000073 ecall + +0000000080000178 : + 80000178: 342022f3 csrr t0,mcause + 8000017c: fc629ee3 bne t0,t1,80000158 + 80000180: 00000397 auipc t2,0x0 + 80000184: fcc38393 addi t2,t2,-52 # 8000014c + 80000188: 341022f3 csrr t0,mepc + 8000018c: fc7296e3 bne t0,t2,80000158 + 80000190: fddff06f j 8000016c + 80000194: c0001073 unimp + 80000198: 0000 unimp + 8000019a: 0000 unimp + 8000019c: 0000 unimp + 8000019e: 0000 unimp + 800001a0: 0000 unimp + 800001a2: 0000 unimp + 800001a4: 0000 unimp + 800001a6: 0000 unimp + 800001a8: 0000 unimp + 800001aa: 0000 unimp + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0000 unimp + 800001b2: 0000 unimp + 800001b4: 0000 unimp + 800001b6: 0000 unimp + 800001b8: 0000 unimp + 800001ba: 0000 unimp + 800001bc: 0000 unimp + 800001be: 0000 unimp + 800001c0: 0000 unimp + 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-scall.elf b/test/riscv/tests/rv64mi-p-scall.elf new file mode 100644 index 00000000..bbb1526b Binary files /dev/null and b/test/riscv/tests/rv64mi-p-scall.elf differ diff --git a/test/riscv/tests/rv64si-p-csr.dump b/test/riscv/tests/rv64si-p-csr.dump new file mode 100644 index 00000000..e4e92ac7 --- /dev/null +++ b/test/riscv/tests/rv64si-p-csr.dump @@ -0,0 +1,222 @@ + +rv64si-p-csr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 00000297 auipc t0,0x0 + 800000c4: 16c28293 addi t0,t0,364 # 8000022c + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + +0000000080000110 : + 80000110: 10002573 csrr a0,sstatus + 80000114: 0030059b addiw a1,zero,3 + 80000118: 02059593 slli a1,a1,0x20 + 8000011c: 00b57533 and a0,a0,a1 + 80000120: 00100e9b addiw t4,zero,1 + 80000124: 021e9e93 slli t4,t4,0x21 + 80000128: 00d00193 li gp,13 + 8000012c: 0fd51063 bne a0,t4,8000020c + 80000130: 1401d073 csrwi sscratch,3 + +0000000080000134 : + 80000134: 14002573 csrr a0,sscratch + 80000138: 00300e93 li t4,3 + 8000013c: 00200193 li gp,2 + 80000140: 0dd51663 bne a0,t4,8000020c + +0000000080000144 : + 80000144: 1400f5f3 csrrci a1,sscratch,1 + 80000148: 00300e93 li t4,3 + 8000014c: 00300193 li gp,3 + 80000150: 0bd59e63 bne a1,t4,8000020c + +0000000080000154 : + 80000154: 14026673 csrrsi a2,sscratch,4 + 80000158: 00200e93 li t4,2 + 8000015c: 00400193 li gp,4 + 80000160: 0bd61663 bne a2,t4,8000020c + +0000000080000164 : + 80000164: 140156f3 csrrwi a3,sscratch,2 + 80000168: 00600e93 li t4,6 + 8000016c: 00500193 li gp,5 + 80000170: 09d69e63 bne a3,t4,8000020c + +0000000080000174 : + 80000174: 0bad2537 lui a0,0xbad2 + 80000178: dea5051b addiw a0,a0,-534 + 8000017c: 140515f3 csrrw a1,sscratch,a0 + 80000180: 00200e93 li t4,2 + 80000184: 00600193 li gp,6 + 80000188: 09d59263 bne a1,t4,8000020c + +000000008000018c : + 8000018c: 00002537 lui a0,0x2 + 80000190: dea5051b addiw a0,a0,-534 + 80000194: 14053573 csrrc a0,sscratch,a0 + 80000198: 0bad2eb7 lui t4,0xbad2 + 8000019c: deae8e9b addiw t4,t4,-534 + 800001a0: 00700193 li gp,7 + 800001a4: 07d51463 bne a0,t4,8000020c + +00000000800001a8 : + 800001a8: 0000c537 lui a0,0xc + 800001ac: eef5051b addiw a0,a0,-273 + 800001b0: 14052573 csrrs a0,sscratch,a0 + 800001b4: 0bad0eb7 lui t4,0xbad0 + 800001b8: 00800193 li gp,8 + 800001bc: 05d51863 bne a0,t4,8000020c + +00000000800001c0 : + 800001c0: 14002573 csrr a0,sscratch + 800001c4: 0badceb7 lui t4,0xbadc + 800001c8: eefe8e9b addiw t4,t4,-273 + 800001cc: 00900193 li gp,9 + 800001d0: 03d51e63 bne a0,t4,8000020c + 800001d4: 10000293 li t0,256 + 800001d8: 1002b073 csrc sstatus,t0 + 800001dc: 00000297 auipc t0,0x0 + 800001e0: 01028293 addi t0,t0,16 # 800001ec + 800001e4: 14129073 csrw sepc,t0 + 800001e8: 10200073 sret + +00000000800001ec : + 800001ec: 00000013 nop + 800001f0: 00000e93 li t4,0 + 800001f4: 00c00193 li gp,12 + 800001f8: 01d01a63 bne zero,t4,8000020c + +00000000800001fc : + 800001fc: 0ff0000f fence + 80000200: 00100193 li gp,1 + 80000204: 00000073 ecall + 80000208: 00301c63 bne zero,gp,80000220 + +000000008000020c : + 8000020c: 0ff0000f fence + 80000210: 00018063 beqz gp,80000210 + 80000214: 00119193 slli gp,gp,0x1 + 80000218: 0011e193 ori gp,gp,1 + 8000021c: 00000073 ecall + +0000000080000220 : + 80000220: 0ff0000f fence + 80000224: 00100193 li gp,1 + 80000228: 00000073 ecall + +000000008000022c : + 8000022c: 00900293 li t0,9 + 80000230: 0051e663 bltu gp,t0,8000023c + 80000234: 00b00293 li t0,11 + 80000238: 0032fe63 bleu gp,t0,80000254 + 8000023c: 142022f3 csrr t0,scause + 80000240: 00800313 li t1,8 + 80000244: fc6294e3 bne t0,t1,8000020c + 80000248: 0ff0000f fence + 8000024c: 00100193 li gp,1 + 80000250: 00000073 ecall + +0000000080000254 : + 80000254: 142022f3 csrr t0,scause + 80000258: 00200313 li t1,2 + 8000025c: fa6298e3 bne t0,t1,8000020c + 80000260: 141022f3 csrr t0,sepc + 80000264: 00428293 addi t0,t0,4 + 80000268: 14129073 csrw sepc,t0 + 8000026c: 10200073 sret + 80000270: c0001073 unimp + 80000274: 0000 unimp + 80000276: 0000 unimp + 80000278: 0000 unimp + 8000027a: 0000 unimp + 8000027c: 0000 unimp + 8000027e: 0000 unimp + 80000280: 0000 unimp + 80000282: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: 0001 nop + 80002002: 0000 unimp + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-csr.elf b/test/riscv/tests/rv64si-p-csr.elf new file mode 100644 index 00000000..3f0921cb Binary files /dev/null and b/test/riscv/tests/rv64si-p-csr.elf differ diff --git a/test/riscv/tests/rv64si-p-dirty.dump b/test/riscv/tests/rv64si-p-dirty.dump new file mode 100644 index 00000000..a92c70da --- /dev/null +++ b/test/riscv/tests/rv64si-p-dirty.dump @@ -0,0 +1,202 @@ + +rv64si-p-dirty: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 00000f17 auipc t5,0x0 + 80000024: 1d0f0f13 addi t5,t5,464 # 800001f0 + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: fff0051b addiw a0,zero,-1 + 8000010c: 03f51513 slli a0,a0,0x3f + 80000110: 00002597 auipc a1,0x2 + 80000114: ef058593 addi a1,a1,-272 # 80002000 + 80000118: 00c5d593 srli a1,a1,0xc + 8000011c: 00a5e5b3 or a1,a1,a0 + 80000120: 18059073 csrw satp,a1 + 80000124: 12000073 sfence.vma + 80000128: 000215b7 lui a1,0x21 + 8000012c: 8005859b addiw a1,a1,-2048 + 80000130: 3005a073 csrs mstatus,a1 + 80000134: 00200193 li gp,2 + 80000138: 00100393 li t2,1 + 8000013c: 80002517 auipc a0,0x80002 + 80000140: ec752623 sw t2,-308(a0) # 2008 <_start-0x7fffdff8> + 80000144: 00300193 li gp,3 + 80000148: 000415b7 lui a1,0x41 + 8000014c: 8005859b addiw a1,a1,-2048 + 80000150: 3005a073 csrs mstatus,a1 + 80000154: 80002297 auipc t0,0x80002 + 80000158: eb42a283 lw t0,-332(t0) # 2008 <_start-0x7fffdff8> + 8000015c: 10029063 bnez t0,8000025c + 80000160: 80002517 auipc a0,0x80002 + 80000164: ea752423 sw t2,-344(a0) # 2008 <_start-0x7fffdff8> + 80000168: 80002297 auipc t0,0x80002 + 8000016c: ea02a283 lw t0,-352(t0) # 2008 <_start-0x7fffdff8> + 80000170: 0e729663 bne t0,t2,8000025c + 80000174: 000202b7 lui t0,0x20 + 80000178: 3002b073 csrc mstatus,t0 + 8000017c: 00002297 auipc t0,0x2 + 80000180: e842a283 lw t0,-380(t0) # 80002000 + 80000184: 0c000513 li a0,192 + 80000188: 00a2f2b3 and t0,t0,a0 + 8000018c: 0ca29863 bne t0,a0,8000025c + 80000190: 000202b7 lui t0,0x20 + 80000194: 3002a073 csrs mstatus,t0 + 80000198: 00400193 li gp,4 + 8000019c: 80002517 auipc a0,0x80002 + 800001a0: e6452503 lw a0,-412(a0) # 2000 <_start-0x7fffe000> + 800001a4: 40056513 ori a0,a0,1024 + 800001a8: 80002297 auipc t0,0x80002 + 800001ac: e4a2ac23 sw a0,-424(t0) # 2000 <_start-0x7fffe000> + 800001b0: 12000073 sfence.vma + 800001b4: 80002297 auipc t0,0x80002 + 800001b8: e4a2a623 sw a0,-436(t0) # 2000 <_start-0x7fffe000> + 800001bc: 0a00006f j 8000025c + 800001c0: 0ff0000f fence + 800001c4: 00100193 li gp,1 + 800001c8: 00000073 ecall + 800001cc: 00301c63 bne zero,gp,800001e4 + +00000000800001d0 : + 800001d0: 0ff0000f fence + 800001d4: 00018063 beqz gp,800001d4 + 800001d8: 00119193 slli gp,gp,0x1 + 800001dc: 0011e193 ori gp,gp,1 + 800001e0: 00000073 ecall + +00000000800001e4 : + 800001e4: 0ff0000f fence + 800001e8: 00100193 li gp,1 + 800001ec: 00000073 ecall + +00000000800001f0 : + 800001f0: 342022f3 csrr t0,mcause + 800001f4: ff128293 addi t0,t0,-15 + 800001f8: 06029263 bnez t0,8000025c + 800001fc: 00200313 li t1,2 + 80000200: 02619263 bne gp,t1,80000224 + 80000204: 00002297 auipc t0,0x2 + 80000208: dfc2a283 lw t0,-516(t0) # 80002000 + 8000020c: 0802f313 andi t1,t0,128 + 80000210: 04031663 bnez t1,8000025c + +0000000080000214 : + 80000214: 341022f3 csrr t0,mepc + 80000218: 00428293 addi t0,t0,4 + 8000021c: 34129073 csrw mepc,t0 + 80000220: 30200073 mret + 80000224: 00300313 li t1,3 + 80000228: 02619463 bne gp,t1,80000250 + 8000022c: 00002297 auipc t0,0x2 + 80000230: dd42a283 lw t0,-556(t0) # 80002000 + 80000234: 0802f313 andi t1,t0,128 + 80000238: 02031263 bnez t1,8000025c + 8000023c: 0802e293 ori t0,t0,128 + 80000240: 00002317 auipc t1,0x2 + 80000244: dc532023 sw t0,-576(t1) # 80002000 + 80000248: 12000073 sfence.vma + 8000024c: 30200073 mret + 80000250: 00400313 li t1,4 + 80000254: 00619463 bne gp,t1,8000025c + 80000258: f8dff06f j 800001e4 + +000000008000025c : + 8000025c: 0ff0000f fence + 80000260: 00018063 beqz gp,80000260 + 80000264: 00119193 slli gp,gp,0x1 + 80000268: 0011e193 ori gp,gp,1 + 8000026c: 00000073 ecall + 80000270: c0001073 unimp + 80000274: 0000 unimp + 80000276: 0000 unimp + 80000278: 0000 unimp + 8000027a: 0000 unimp + 8000027c: 0000 unimp + 8000027e: 0000 unimp + 80000280: 0000 unimp + 80000282: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: 005f 2000 0000 0x2000005f + 80002006: 0000 unimp + +0000000080002008 : + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-dirty.elf b/test/riscv/tests/rv64si-p-dirty.elf new file mode 100644 index 00000000..7ff11e51 Binary files /dev/null and b/test/riscv/tests/rv64si-p-dirty.elf differ diff --git a/test/riscv/tests/rv64si-p-ma_fetch.dump b/test/riscv/tests/rv64si-p-ma_fetch.dump new file mode 100644 index 00000000..bd8178ba --- /dev/null +++ b/test/riscv/tests/rv64si-p-ma_fetch.dump @@ -0,0 +1,175 @@ + +rv64si-p-ma_fetch: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 00000297 auipc t0,0x0 + 800000c4: 11428293 addi t0,t0,276 # 800001d4 + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + 80000110: 00200193 li gp,2 + 80000114: 00000313 li t1,0 + 80000118: 00000297 auipc t0,0x0 + 8000011c: 00c28293 addi t0,t0,12 # 80000124 + 80000120: 00228367 jalr t1,2(t0) + 80000124: a011 j 80000128 + 80000126: a019 j 8000012c + 80000128: 08c0006f j 800001b4 + 8000012c: 00300193 li gp,3 + 80000130: 00000297 auipc t0,0x0 + 80000134: 00c28293 addi t0,t0,12 # 8000013c + 80000138: 00128367 jalr t1,1(t0) + 8000013c: 0080006f j 80000144 + 80000140: 0740006f j 800001b4 + 80000144: 00400193 li gp,4 + 80000148: 00000313 li t1,0 + 8000014c: 00000297 auipc t0,0x0 + 80000150: 00c28293 addi t0,t0,12 # 80000158 + 80000154: 00328367 jalr t1,3(t0) + 80000158: a011 j 8000015c + 8000015a: a019 j 80000160 + 8000015c: 0580006f j 800001b4 + 80000160: 00500193 li gp,5 + 80000164: 00000313 li t1,0 + 80000168: 00000297 auipc t0,0x0 + 8000016c: 00c28293 addi t0,t0,12 # 80000174 + 80000170: 0060036f jal t1,80000176 + 80000174: a011 j 80000178 + 80000176: a019 j 8000017c + 80000178: 03c0006f j 800001b4 + 8000017c: 00600193 li gp,6 + 80000180: 00000313 li t1,0 + 80000184: 00000297 auipc t0,0x0 + 80000188: 00c28293 addi t0,t0,12 # 80000190 + 8000018c: 00000363 beqz zero,80000192 + 80000190: a011 j 80000194 + 80000192: a019 j 80000198 + 80000194: 0200006f j 800001b4 + 80000198: 00700193 li gp,7 + 8000019c: 00001563 bnez zero,800001a6 + 800001a0: 00c0006f j 800001ac + 800001a4: a009 j 800001a6 + 800001a6: a009 j 800001a8 + 800001a8: 00c0006f j 800001b4 + 800001ac: 01c0006f j 800001c8 + 800001b0: 00301c63 bne zero,gp,800001c8 + +00000000800001b4 : + 800001b4: 0ff0000f fence + 800001b8: 00018063 beqz gp,800001b8 + 800001bc: 00119193 slli gp,gp,0x1 + 800001c0: 0011e193 ori gp,gp,1 + 800001c4: 00000073 ecall + +00000000800001c8 : + 800001c8: 0ff0000f fence + 800001cc: 00100193 li gp,1 + 800001d0: 00000073 ecall + +00000000800001d4 : + 800001d4: 00200513 li a0,2 + 800001d8: 02a18063 beq gp,a0,800001f8 + 800001dc: 00400513 li a0,4 + 800001e0: 00a18c63 beq gp,a0,800001f8 + 800001e4: 00500513 li a0,5 + 800001e8: 00a18863 beq gp,a0,800001f8 + 800001ec: 00600513 li a0,6 + 800001f0: 00a18463 beq gp,a0,800001f8 + 800001f4: fc1ff06f j 800001b4 + 800001f8: fa031ee3 bnez t1,800001b4 + 800001fc: 00000593 li a1,0 + 80000200: 14202573 csrr a0,scause + 80000204: fab518e3 bne a0,a1,800001b4 + 80000208: 141025f3 csrr a1,sepc + 8000020c: 00458593 addi a1,a1,4 + 80000210: fab292e3 bne t0,a1,800001b4 + 80000214: 14302573 csrr a0,sbadaddr + 80000218: 00050663 beqz a0,80000224 + 8000021c: ffe50513 addi a0,a0,-2 # ffe <_start-0x7ffff002> + 80000220: f8551ae3 bne a0,t0,800001b4 + 80000224: 00c58593 addi a1,a1,12 + 80000228: 14159073 csrw sepc,a1 + 8000022c: 10200073 sret + 80000230: c0001073 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-ma_fetch.elf b/test/riscv/tests/rv64si-p-ma_fetch.elf new file mode 100644 index 00000000..23977add Binary files /dev/null and b/test/riscv/tests/rv64si-p-ma_fetch.elf differ diff --git a/test/riscv/tests/rv64si-p-scall.dump b/test/riscv/tests/rv64si-p-scall.dump new file mode 100644 index 00000000..99674507 --- /dev/null +++ b/test/riscv/tests/rv64si-p-scall.dump @@ -0,0 +1,121 @@ + +rv64si-p-scall: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 00000297 auipc t0,0x0 + 800000c4: 0a028293 addi t0,t0,160 # 80000160 + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + 80000110: 00200193 li gp,2 + 80000114: 00800313 li t1,8 + 80000118: 10000293 li t0,256 + 8000011c: 1002b073 csrc sstatus,t0 + 80000120: 00000297 auipc t0,0x0 + 80000124: 01028293 addi t0,t0,16 # 80000130 + 80000128: 14129073 csrw sepc,t0 + 8000012c: 10200073 sret + 80000130: 00100193 li gp,1 + +0000000080000134 : + 80000134: 00000073 ecall + 80000138: 0080006f j 80000140 + 8000013c: 00301c63 bne zero,gp,80000154 + +0000000080000140 : + 80000140: 0ff0000f fence + 80000144: 00018063 beqz gp,80000144 + 80000148: 00119193 slli gp,gp,0x1 + 8000014c: 0011e193 ori gp,gp,1 + 80000150: 00000073 ecall + +0000000080000154 : + 80000154: 0ff0000f fence + 80000158: 00100193 li gp,1 + 8000015c: 00000073 ecall + +0000000080000160 : + 80000160: 142022f3 csrr t0,scause + 80000164: fc629ee3 bne t0,t1,80000140 + 80000168: 00000397 auipc t2,0x0 + 8000016c: fcc38393 addi t2,t2,-52 # 80000134 + 80000170: 141022f3 csrr t0,sepc + 80000174: fc7296e3 bne t0,t2,80000140 + 80000178: fddff06f j 80000154 + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-scall.elf b/test/riscv/tests/rv64si-p-scall.elf new file mode 100644 index 00000000..4d7dc278 Binary files /dev/null and b/test/riscv/tests/rv64si-p-scall.elf differ diff --git a/test/riscv/tests/rv64si-p-wfi.dump b/test/riscv/tests/rv64si-p-wfi.dump new file mode 100644 index 00000000..2cd7bf86 --- /dev/null +++ b/test/riscv/tests/rv64si-p-wfi.dump @@ -0,0 +1,128 @@ + +rv64si-p-wfi: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + 80000110: 10017073 csrci sstatus,2 + 80000114: 10416073 csrsi sie,2 + 80000118: 14416073 csrsi sip,2 + 8000011c: 10500073 wfi + 80000120: 0ff0000f fence + 80000124: 00100193 li gp,1 + 80000128: 00000073 ecall + 8000012c: 00301c63 bne zero,gp,80000144 + +0000000080000130 : + 80000130: 0ff0000f fence + 80000134: 00018063 beqz gp,80000134 + 80000138: 00119193 slli gp,gp,0x1 + 8000013c: 0011e193 ori gp,gp,1 + 80000140: 00000073 ecall + +0000000080000144 : + 80000144: 0ff0000f fence + 80000148: 00100193 li gp,1 + 8000014c: 00000073 ecall + 80000150: c0001073 unimp + 80000154: 0000 unimp + 80000156: 0000 unimp + 80000158: 0000 unimp + 8000015a: 0000 unimp + 8000015c: 0000 unimp + 8000015e: 0000 unimp + 80000160: 0000 unimp + 80000162: 0000 unimp + 80000164: 0000 unimp + 80000166: 0000 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-wfi.elf b/test/riscv/tests/rv64si-p-wfi.elf new file mode 100644 index 00000000..23d0c0cc Binary files /dev/null and b/test/riscv/tests/rv64si-p-wfi.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoadd_d.elf b/test/riscv/tests/rv64ua-p-amoadd_d.elf old mode 100755 new mode 100644 index f4fac374..e20d2903 Binary files a/test/riscv/tests/rv64ua-p-amoadd_d.elf and b/test/riscv/tests/rv64ua-p-amoadd_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoadd_w.elf b/test/riscv/tests/rv64ua-p-amoadd_w.elf old mode 100755 new mode 100644 index 4b3457d8..f8c15af6 Binary files a/test/riscv/tests/rv64ua-p-amoadd_w.elf and b/test/riscv/tests/rv64ua-p-amoadd_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoand_d.elf b/test/riscv/tests/rv64ua-p-amoand_d.elf old mode 100755 new mode 100644 index 47e8b321..6f9ec5cf Binary files a/test/riscv/tests/rv64ua-p-amoand_d.elf and b/test/riscv/tests/rv64ua-p-amoand_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoand_w.elf b/test/riscv/tests/rv64ua-p-amoand_w.elf old mode 100755 new mode 100644 index 06c29f8b..fefc4fc0 Binary files a/test/riscv/tests/rv64ua-p-amoand_w.elf and b/test/riscv/tests/rv64ua-p-amoand_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomax_d.elf b/test/riscv/tests/rv64ua-p-amomax_d.elf old mode 100755 new mode 100644 index 4828a226..051cf481 Binary files a/test/riscv/tests/rv64ua-p-amomax_d.elf and b/test/riscv/tests/rv64ua-p-amomax_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomax_w.elf b/test/riscv/tests/rv64ua-p-amomax_w.elf old mode 100755 new mode 100644 index 1336c9c7..59d12a1f Binary files a/test/riscv/tests/rv64ua-p-amomax_w.elf and b/test/riscv/tests/rv64ua-p-amomax_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomaxu_d.elf b/test/riscv/tests/rv64ua-p-amomaxu_d.elf old mode 100755 new mode 100644 index 04a36aad..4c13c12c Binary files a/test/riscv/tests/rv64ua-p-amomaxu_d.elf and b/test/riscv/tests/rv64ua-p-amomaxu_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomaxu_w.elf b/test/riscv/tests/rv64ua-p-amomaxu_w.elf old mode 100755 new mode 100644 index 37b392f4..0c97a3a9 Binary files a/test/riscv/tests/rv64ua-p-amomaxu_w.elf and b/test/riscv/tests/rv64ua-p-amomaxu_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomin_d.elf b/test/riscv/tests/rv64ua-p-amomin_d.elf old mode 100755 new mode 100644 index 87a28983..791c78fe Binary files a/test/riscv/tests/rv64ua-p-amomin_d.elf and b/test/riscv/tests/rv64ua-p-amomin_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amomin_w.elf b/test/riscv/tests/rv64ua-p-amomin_w.elf old mode 100755 new mode 100644 index 201e7deb..7bf86a36 Binary files a/test/riscv/tests/rv64ua-p-amomin_w.elf and b/test/riscv/tests/rv64ua-p-amomin_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amominu_d.elf b/test/riscv/tests/rv64ua-p-amominu_d.elf old mode 100755 new mode 100644 index a5cee277..1c6d6adb Binary files a/test/riscv/tests/rv64ua-p-amominu_d.elf and b/test/riscv/tests/rv64ua-p-amominu_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amominu_w.elf b/test/riscv/tests/rv64ua-p-amominu_w.elf old mode 100755 new mode 100644 index a2b0bfdd..af14db97 Binary files a/test/riscv/tests/rv64ua-p-amominu_w.elf and b/test/riscv/tests/rv64ua-p-amominu_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoor_d.elf b/test/riscv/tests/rv64ua-p-amoor_d.elf old mode 100755 new mode 100644 index 3549d35f..a00b97c5 Binary files a/test/riscv/tests/rv64ua-p-amoor_d.elf and b/test/riscv/tests/rv64ua-p-amoor_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoor_w.elf b/test/riscv/tests/rv64ua-p-amoor_w.elf old mode 100755 new mode 100644 index 4e408f28..e35c29f2 Binary files a/test/riscv/tests/rv64ua-p-amoor_w.elf and b/test/riscv/tests/rv64ua-p-amoor_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoswap_d.elf b/test/riscv/tests/rv64ua-p-amoswap_d.elf old mode 100755 new mode 100644 index 642c648d..63d01a74 Binary files a/test/riscv/tests/rv64ua-p-amoswap_d.elf and b/test/riscv/tests/rv64ua-p-amoswap_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoswap_w.elf b/test/riscv/tests/rv64ua-p-amoswap_w.elf old mode 100755 new mode 100644 index e0b9e58e..011d5e2f Binary files a/test/riscv/tests/rv64ua-p-amoswap_w.elf and b/test/riscv/tests/rv64ua-p-amoswap_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoxor_d.elf b/test/riscv/tests/rv64ua-p-amoxor_d.elf old mode 100755 new mode 100644 index a04e1f1c..4bec6cca Binary files a/test/riscv/tests/rv64ua-p-amoxor_d.elf and b/test/riscv/tests/rv64ua-p-amoxor_d.elf differ diff --git a/test/riscv/tests/rv64ua-p-amoxor_w.elf b/test/riscv/tests/rv64ua-p-amoxor_w.elf old mode 100755 new mode 100644 index fc27683f..22e8ba98 Binary files a/test/riscv/tests/rv64ua-p-amoxor_w.elf and b/test/riscv/tests/rv64ua-p-amoxor_w.elf differ diff --git a/test/riscv/tests/rv64ua-p-lrsc.dump b/test/riscv/tests/rv64ua-p-lrsc.dump new file mode 100644 index 00000000..bcca392e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-lrsc.dump @@ -0,0 +1,691 @@ + +rv64ua-p-lrsc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 00002517 auipc a0,0x2 + 80000100: f0450513 addi a0,a0,-252 # 80002000 + 80000104: 00100593 li a1,1 + 80000108: 00b5262f amoadd.w a2,a1,(a0) + 8000010c: 00100693 li a3,1 + 80000110: fed67ee3 bleu a3,a2,8000010c + 80000114: 00052583 lw a1,0(a0) + 80000118: fed5eee3 bltu a1,a3,80000114 + +000000008000011c : + 8000011c: 00002517 auipc a0,0x2 + 80000120: eec50513 addi a0,a0,-276 # 80002008 + 80000124: 1805272f sc.w a4,zero,(a0) + 80000128: 00100e93 li t4,1 + 8000012c: 00200193 li gp,2 + 80000130: 09d71a63 bne a4,t4,800001c4 + +0000000080000134 : + 80000134: 00002517 auipc a0,0x2 + 80000138: ed450513 addi a0,a0,-300 # 80002008 + 8000013c: 00002597 auipc a1,0x2 + 80000140: 2d058593 addi a1,a1,720 # 8000240c + 80000144: 1005a5af lr.w a1,(a1) + 80000148: 18b5272f sc.w a4,a1,(a0) + 8000014c: 00100e93 li t4,1 + 80000150: 00300193 li gp,3 + 80000154: 07d71863 bne a4,t4,800001c4 + 80000158: 00002517 auipc a0,0x2 + 8000015c: eb050513 addi a0,a0,-336 # 80002008 + 80000160: 40000593 li a1,1024 + 80000164: 00160613 addi a2,a2,1 + 80000168: 1005272f lr.w a4,(a0) + 8000016c: 00c70733 add a4,a4,a2 + 80000170: 18e5272f sc.w a4,a4,(a0) + 80000174: fe071ae3 bnez a4,80000168 + 80000178: fff58593 addi a1,a1,-1 + 8000017c: fe0596e3 bnez a1,80000168 + 80000180: 00002517 auipc a0,0x2 + 80000184: e8450513 addi a0,a0,-380 # 80002004 + 80000188: 00100593 li a1,1 + 8000018c: 00b5202f amoadd.w zero,a1,(a0) + 80000190: 00052583 lw a1,0(a0) + 80000194: fed5cee3 blt a1,a3,80000190 + 80000198: 0ff0000f fence + +000000008000019c : + 8000019c: 00002517 auipc a0,0x2 + 800001a0: e6c52503 lw a0,-404(a0) # 80002008 + 800001a4: 00969593 slli a1,a3,0x9 + 800001a8: 40b50533 sub a0,a0,a1 + 800001ac: fff68693 addi a3,a3,-1 + 800001b0: fe06dce3 bgez a3,800001a8 + 800001b4: 00000e93 li t4,0 + 800001b8: 00400193 li gp,4 + 800001bc: 01d51463 bne a0,t4,800001c4 + 800001c0: 00301c63 bne zero,gp,800001d8 + +00000000800001c4 : + 800001c4: 0ff0000f fence + 800001c8: 00018063 beqz gp,800001c8 + 800001cc: 00119193 slli gp,gp,0x1 + 800001d0: 0011e193 ori gp,gp,1 + 800001d4: 00000073 ecall + +00000000800001d8 : + 800001d8: 0ff0000f fence + 800001dc: 00100193 li gp,1 + 800001e0: 00000073 ecall + 800001e4: c0001073 unimp + 800001e8: 0000 unimp + 800001ea: 0000 unimp + 800001ec: 0000 unimp + 800001ee: 0000 unimp + 800001f0: 0000 unimp + 800001f2: 0000 unimp + 800001f4: 0000 unimp + 800001f6: 0000 unimp + 800001f8: 0000 unimp + 800001fa: 0000 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp + +Disassembly of section .data: + +0000000080002000 : + 80002000: 0000 unimp + 80002002: 0000 unimp + +0000000080002004 : + 80002004: 0000 unimp + 80002006: 0000 unimp + +0000000080002008 : + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp + 80002010: 0000 unimp + 80002012: 0000 unimp + 80002014: 0000 unimp + 80002016: 0000 unimp + 80002018: 0000 unimp + 8000201a: 0000 unimp + 8000201c: 0000 unimp + 8000201e: 0000 unimp + 80002020: 0000 unimp + 80002022: 0000 unimp + 80002024: 0000 unimp + 80002026: 0000 unimp + 80002028: 0000 unimp + 8000202a: 0000 unimp + 8000202c: 0000 unimp + 8000202e: 0000 unimp + 80002030: 0000 unimp + 80002032: 0000 unimp + 80002034: 0000 unimp + 80002036: 0000 unimp + 80002038: 0000 unimp + 8000203a: 0000 unimp + 8000203c: 0000 unimp + 8000203e: 0000 unimp + 80002040: 0000 unimp + 80002042: 0000 unimp + 80002044: 0000 unimp + 80002046: 0000 unimp + 80002048: 0000 unimp + 8000204a: 0000 unimp + 8000204c: 0000 unimp + 8000204e: 0000 unimp + 80002050: 0000 unimp + 80002052: 0000 unimp + 80002054: 0000 unimp + 80002056: 0000 unimp + 80002058: 0000 unimp + 8000205a: 0000 unimp + 8000205c: 0000 unimp + 8000205e: 0000 unimp + 80002060: 0000 unimp + 80002062: 0000 unimp + 80002064: 0000 unimp + 80002066: 0000 unimp + 80002068: 0000 unimp + 8000206a: 0000 unimp + 8000206c: 0000 unimp + 8000206e: 0000 unimp + 80002070: 0000 unimp + 80002072: 0000 unimp + 80002074: 0000 unimp + 80002076: 0000 unimp + 80002078: 0000 unimp + 8000207a: 0000 unimp + 8000207c: 0000 unimp + 8000207e: 0000 unimp + 80002080: 0000 unimp + 80002082: 0000 unimp + 80002084: 0000 unimp + 80002086: 0000 unimp + 80002088: 0000 unimp + 8000208a: 0000 unimp + 8000208c: 0000 unimp + 8000208e: 0000 unimp + 80002090: 0000 unimp + 80002092: 0000 unimp + 80002094: 0000 unimp + 80002096: 0000 unimp + 80002098: 0000 unimp + 8000209a: 0000 unimp + 8000209c: 0000 unimp + 8000209e: 0000 unimp + 800020a0: 0000 unimp + 800020a2: 0000 unimp + 800020a4: 0000 unimp + 800020a6: 0000 unimp + 800020a8: 0000 unimp + 800020aa: 0000 unimp + 800020ac: 0000 unimp + 800020ae: 0000 unimp + 800020b0: 0000 unimp + 800020b2: 0000 unimp + 800020b4: 0000 unimp + 800020b6: 0000 unimp + 800020b8: 0000 unimp + 800020ba: 0000 unimp + 800020bc: 0000 unimp + 800020be: 0000 unimp + 800020c0: 0000 unimp + 800020c2: 0000 unimp + 800020c4: 0000 unimp + 800020c6: 0000 unimp + 800020c8: 0000 unimp + 800020ca: 0000 unimp + 800020cc: 0000 unimp + 800020ce: 0000 unimp + 800020d0: 0000 unimp + 800020d2: 0000 unimp + 800020d4: 0000 unimp + 800020d6: 0000 unimp + 800020d8: 0000 unimp + 800020da: 0000 unimp + 800020dc: 0000 unimp + 800020de: 0000 unimp + 800020e0: 0000 unimp + 800020e2: 0000 unimp + 800020e4: 0000 unimp + 800020e6: 0000 unimp + 800020e8: 0000 unimp + 800020ea: 0000 unimp + 800020ec: 0000 unimp + 800020ee: 0000 unimp + 800020f0: 0000 unimp + 800020f2: 0000 unimp + 800020f4: 0000 unimp + 800020f6: 0000 unimp + 800020f8: 0000 unimp + 800020fa: 0000 unimp + 800020fc: 0000 unimp + 800020fe: 0000 unimp + 80002100: 0000 unimp + 80002102: 0000 unimp + 80002104: 0000 unimp + 80002106: 0000 unimp + 80002108: 0000 unimp + 8000210a: 0000 unimp + 8000210c: 0000 unimp + 8000210e: 0000 unimp + 80002110: 0000 unimp + 80002112: 0000 unimp + 80002114: 0000 unimp + 80002116: 0000 unimp + 80002118: 0000 unimp + 8000211a: 0000 unimp + 8000211c: 0000 unimp + 8000211e: 0000 unimp + 80002120: 0000 unimp + 80002122: 0000 unimp + 80002124: 0000 unimp + 80002126: 0000 unimp + 80002128: 0000 unimp + 8000212a: 0000 unimp + 8000212c: 0000 unimp + 8000212e: 0000 unimp + 80002130: 0000 unimp + 80002132: 0000 unimp + 80002134: 0000 unimp + 80002136: 0000 unimp + 80002138: 0000 unimp + 8000213a: 0000 unimp + 8000213c: 0000 unimp + 8000213e: 0000 unimp + 80002140: 0000 unimp + 80002142: 0000 unimp + 80002144: 0000 unimp + 80002146: 0000 unimp + 80002148: 0000 unimp + 8000214a: 0000 unimp + 8000214c: 0000 unimp + 8000214e: 0000 unimp + 80002150: 0000 unimp + 80002152: 0000 unimp + 80002154: 0000 unimp + 80002156: 0000 unimp + 80002158: 0000 unimp + 8000215a: 0000 unimp + 8000215c: 0000 unimp + 8000215e: 0000 unimp + 80002160: 0000 unimp + 80002162: 0000 unimp + 80002164: 0000 unimp + 80002166: 0000 unimp + 80002168: 0000 unimp + 8000216a: 0000 unimp + 8000216c: 0000 unimp + 8000216e: 0000 unimp + 80002170: 0000 unimp + 80002172: 0000 unimp + 80002174: 0000 unimp + 80002176: 0000 unimp + 80002178: 0000 unimp + 8000217a: 0000 unimp + 8000217c: 0000 unimp + 8000217e: 0000 unimp + 80002180: 0000 unimp + 80002182: 0000 unimp + 80002184: 0000 unimp + 80002186: 0000 unimp + 80002188: 0000 unimp + 8000218a: 0000 unimp + 8000218c: 0000 unimp + 8000218e: 0000 unimp + 80002190: 0000 unimp + 80002192: 0000 unimp + 80002194: 0000 unimp + 80002196: 0000 unimp + 80002198: 0000 unimp + 8000219a: 0000 unimp + 8000219c: 0000 unimp + 8000219e: 0000 unimp + 800021a0: 0000 unimp + 800021a2: 0000 unimp + 800021a4: 0000 unimp + 800021a6: 0000 unimp + 800021a8: 0000 unimp + 800021aa: 0000 unimp + 800021ac: 0000 unimp + 800021ae: 0000 unimp + 800021b0: 0000 unimp + 800021b2: 0000 unimp + 800021b4: 0000 unimp + 800021b6: 0000 unimp + 800021b8: 0000 unimp + 800021ba: 0000 unimp + 800021bc: 0000 unimp + 800021be: 0000 unimp + 800021c0: 0000 unimp + 800021c2: 0000 unimp + 800021c4: 0000 unimp + 800021c6: 0000 unimp + 800021c8: 0000 unimp + 800021ca: 0000 unimp + 800021cc: 0000 unimp + 800021ce: 0000 unimp + 800021d0: 0000 unimp + 800021d2: 0000 unimp + 800021d4: 0000 unimp + 800021d6: 0000 unimp + 800021d8: 0000 unimp + 800021da: 0000 unimp + 800021dc: 0000 unimp + 800021de: 0000 unimp + 800021e0: 0000 unimp + 800021e2: 0000 unimp + 800021e4: 0000 unimp + 800021e6: 0000 unimp + 800021e8: 0000 unimp + 800021ea: 0000 unimp + 800021ec: 0000 unimp + 800021ee: 0000 unimp + 800021f0: 0000 unimp + 800021f2: 0000 unimp + 800021f4: 0000 unimp + 800021f6: 0000 unimp + 800021f8: 0000 unimp + 800021fa: 0000 unimp + 800021fc: 0000 unimp + 800021fe: 0000 unimp + 80002200: 0000 unimp + 80002202: 0000 unimp + 80002204: 0000 unimp + 80002206: 0000 unimp + 80002208: 0000 unimp + 8000220a: 0000 unimp + 8000220c: 0000 unimp + 8000220e: 0000 unimp + 80002210: 0000 unimp + 80002212: 0000 unimp + 80002214: 0000 unimp + 80002216: 0000 unimp + 80002218: 0000 unimp + 8000221a: 0000 unimp + 8000221c: 0000 unimp + 8000221e: 0000 unimp + 80002220: 0000 unimp + 80002222: 0000 unimp + 80002224: 0000 unimp + 80002226: 0000 unimp + 80002228: 0000 unimp + 8000222a: 0000 unimp + 8000222c: 0000 unimp + 8000222e: 0000 unimp + 80002230: 0000 unimp + 80002232: 0000 unimp + 80002234: 0000 unimp + 80002236: 0000 unimp + 80002238: 0000 unimp + 8000223a: 0000 unimp + 8000223c: 0000 unimp + 8000223e: 0000 unimp + 80002240: 0000 unimp + 80002242: 0000 unimp + 80002244: 0000 unimp + 80002246: 0000 unimp + 80002248: 0000 unimp + 8000224a: 0000 unimp + 8000224c: 0000 unimp + 8000224e: 0000 unimp + 80002250: 0000 unimp + 80002252: 0000 unimp + 80002254: 0000 unimp + 80002256: 0000 unimp + 80002258: 0000 unimp + 8000225a: 0000 unimp + 8000225c: 0000 unimp + 8000225e: 0000 unimp + 80002260: 0000 unimp + 80002262: 0000 unimp + 80002264: 0000 unimp + 80002266: 0000 unimp + 80002268: 0000 unimp + 8000226a: 0000 unimp + 8000226c: 0000 unimp + 8000226e: 0000 unimp + 80002270: 0000 unimp + 80002272: 0000 unimp + 80002274: 0000 unimp + 80002276: 0000 unimp + 80002278: 0000 unimp + 8000227a: 0000 unimp + 8000227c: 0000 unimp + 8000227e: 0000 unimp + 80002280: 0000 unimp + 80002282: 0000 unimp + 80002284: 0000 unimp + 80002286: 0000 unimp + 80002288: 0000 unimp + 8000228a: 0000 unimp + 8000228c: 0000 unimp + 8000228e: 0000 unimp + 80002290: 0000 unimp + 80002292: 0000 unimp + 80002294: 0000 unimp + 80002296: 0000 unimp + 80002298: 0000 unimp + 8000229a: 0000 unimp + 8000229c: 0000 unimp + 8000229e: 0000 unimp + 800022a0: 0000 unimp + 800022a2: 0000 unimp + 800022a4: 0000 unimp + 800022a6: 0000 unimp + 800022a8: 0000 unimp + 800022aa: 0000 unimp + 800022ac: 0000 unimp + 800022ae: 0000 unimp + 800022b0: 0000 unimp + 800022b2: 0000 unimp + 800022b4: 0000 unimp + 800022b6: 0000 unimp + 800022b8: 0000 unimp + 800022ba: 0000 unimp + 800022bc: 0000 unimp + 800022be: 0000 unimp + 800022c0: 0000 unimp + 800022c2: 0000 unimp + 800022c4: 0000 unimp + 800022c6: 0000 unimp + 800022c8: 0000 unimp + 800022ca: 0000 unimp + 800022cc: 0000 unimp + 800022ce: 0000 unimp + 800022d0: 0000 unimp + 800022d2: 0000 unimp + 800022d4: 0000 unimp + 800022d6: 0000 unimp + 800022d8: 0000 unimp + 800022da: 0000 unimp + 800022dc: 0000 unimp + 800022de: 0000 unimp + 800022e0: 0000 unimp + 800022e2: 0000 unimp + 800022e4: 0000 unimp + 800022e6: 0000 unimp + 800022e8: 0000 unimp + 800022ea: 0000 unimp + 800022ec: 0000 unimp + 800022ee: 0000 unimp + 800022f0: 0000 unimp + 800022f2: 0000 unimp + 800022f4: 0000 unimp + 800022f6: 0000 unimp + 800022f8: 0000 unimp + 800022fa: 0000 unimp + 800022fc: 0000 unimp + 800022fe: 0000 unimp + 80002300: 0000 unimp + 80002302: 0000 unimp + 80002304: 0000 unimp + 80002306: 0000 unimp + 80002308: 0000 unimp + 8000230a: 0000 unimp + 8000230c: 0000 unimp + 8000230e: 0000 unimp + 80002310: 0000 unimp + 80002312: 0000 unimp + 80002314: 0000 unimp + 80002316: 0000 unimp + 80002318: 0000 unimp + 8000231a: 0000 unimp + 8000231c: 0000 unimp + 8000231e: 0000 unimp + 80002320: 0000 unimp + 80002322: 0000 unimp + 80002324: 0000 unimp + 80002326: 0000 unimp + 80002328: 0000 unimp + 8000232a: 0000 unimp + 8000232c: 0000 unimp + 8000232e: 0000 unimp + 80002330: 0000 unimp + 80002332: 0000 unimp + 80002334: 0000 unimp + 80002336: 0000 unimp + 80002338: 0000 unimp + 8000233a: 0000 unimp + 8000233c: 0000 unimp + 8000233e: 0000 unimp + 80002340: 0000 unimp + 80002342: 0000 unimp + 80002344: 0000 unimp + 80002346: 0000 unimp + 80002348: 0000 unimp + 8000234a: 0000 unimp + 8000234c: 0000 unimp + 8000234e: 0000 unimp + 80002350: 0000 unimp + 80002352: 0000 unimp + 80002354: 0000 unimp + 80002356: 0000 unimp + 80002358: 0000 unimp + 8000235a: 0000 unimp + 8000235c: 0000 unimp + 8000235e: 0000 unimp + 80002360: 0000 unimp + 80002362: 0000 unimp + 80002364: 0000 unimp + 80002366: 0000 unimp + 80002368: 0000 unimp + 8000236a: 0000 unimp + 8000236c: 0000 unimp + 8000236e: 0000 unimp + 80002370: 0000 unimp + 80002372: 0000 unimp + 80002374: 0000 unimp + 80002376: 0000 unimp + 80002378: 0000 unimp + 8000237a: 0000 unimp + 8000237c: 0000 unimp + 8000237e: 0000 unimp + 80002380: 0000 unimp + 80002382: 0000 unimp + 80002384: 0000 unimp + 80002386: 0000 unimp + 80002388: 0000 unimp + 8000238a: 0000 unimp + 8000238c: 0000 unimp + 8000238e: 0000 unimp + 80002390: 0000 unimp + 80002392: 0000 unimp + 80002394: 0000 unimp + 80002396: 0000 unimp + 80002398: 0000 unimp + 8000239a: 0000 unimp + 8000239c: 0000 unimp + 8000239e: 0000 unimp + 800023a0: 0000 unimp + 800023a2: 0000 unimp + 800023a4: 0000 unimp + 800023a6: 0000 unimp + 800023a8: 0000 unimp + 800023aa: 0000 unimp + 800023ac: 0000 unimp + 800023ae: 0000 unimp + 800023b0: 0000 unimp + 800023b2: 0000 unimp + 800023b4: 0000 unimp + 800023b6: 0000 unimp + 800023b8: 0000 unimp + 800023ba: 0000 unimp + 800023bc: 0000 unimp + 800023be: 0000 unimp + 800023c0: 0000 unimp + 800023c2: 0000 unimp + 800023c4: 0000 unimp + 800023c6: 0000 unimp + 800023c8: 0000 unimp + 800023ca: 0000 unimp + 800023cc: 0000 unimp + 800023ce: 0000 unimp + 800023d0: 0000 unimp + 800023d2: 0000 unimp + 800023d4: 0000 unimp + 800023d6: 0000 unimp + 800023d8: 0000 unimp + 800023da: 0000 unimp + 800023dc: 0000 unimp + 800023de: 0000 unimp + 800023e0: 0000 unimp + 800023e2: 0000 unimp + 800023e4: 0000 unimp + 800023e6: 0000 unimp + 800023e8: 0000 unimp + 800023ea: 0000 unimp + 800023ec: 0000 unimp + 800023ee: 0000 unimp + 800023f0: 0000 unimp + 800023f2: 0000 unimp + 800023f4: 0000 unimp + 800023f6: 0000 unimp + 800023f8: 0000 unimp + 800023fa: 0000 unimp + 800023fc: 0000 unimp + 800023fe: 0000 unimp + 80002400: 0000 unimp + 80002402: 0000 unimp + 80002404: 0000 unimp + 80002406: 0000 unimp + 80002408: 0000 unimp + 8000240a: 0000 unimp + +000000008000240c : + 8000240c: 0000 unimp + 8000240e: 0000 unimp diff --git a/test/riscv/tests/rv64ua-v-amoadd_d.dump b/test/riscv/tests/rv64ua-v-amoadd_d.dump new file mode 100644 index 00000000..6e2c6142 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoadd_d.dump @@ -0,0 +1,874 @@ + +rv64ua-v-amoadd_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 70068693 addi a3,a3,1792 # 80002b58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 73460613 addi a2,a2,1844 # 80002be8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6fc60613 addi a2,a2,1788 # 80002c00 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 64c68693 addi a3,a3,1612 # 80002ba0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 66868693 addi a3,a3,1640 # 80002cd8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5e860613 addi a2,a2,1512 # 80002cb0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 51c68693 addi a3,a3,1308 # 80002d08 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 43c68693 addi a3,a3,1084 # 80002c78 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3cc68693 addi a3,a3,972 # 80002c40 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03e00793 li a5,62 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0f6267b7 lui a5,0xf626 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 79178793 addi a5,a5,1937 # f626791 <_start-0x709d986f> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 00b6b72f amoadd.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71863 bne a4,t4,80002b38 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: fff00e9b addiw t4,zero,-1 + 80002af4: 01fe9e93 slli t4,t4,0x1f + 80002af8: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff7010> + 80002afc: 00300193 li gp,3 + 80002b00: 03d79c63 bne a5,t4,80002b38 + +0000000080002b04 : + 80002b04: 00b6b72f amoadd.d a4,a1,(a3) + 80002b08: fff00e9b addiw t4,zero,-1 + 80002b0c: 01fe9e93 slli t4,t4,0x1f + 80002b10: 800e8e93 addi t4,t4,-2048 + 80002b14: 00400193 li gp,4 + 80002b18: 03d71063 bne a4,t4,80002b38 + +0000000080002b1c : + 80002b1c: 0006b783 ld a5,0(a3) + 80002b20: fff80eb7 lui t4,0xfff80 + 80002b24: fffe8e9b addiw t4,t4,-1 + 80002b28: 00ce9e93 slli t4,t4,0xc + 80002b2c: 00500193 li gp,5 + 80002b30: 01d79463 bne a5,t4,80002b38 + 80002b34: 00301a63 bne zero,gp,80002b48 + +0000000080002b38 : + 80002b38: 00119513 slli a0,gp,0x1 + 80002b3c: 00050063 beqz a0,80002b3c + 80002b40: 00156513 ori a0,a0,1 + 80002b44: 00000073 ecall + +0000000080002b48 : + 80002b48: 00100513 li a0,1 + 80002b4c: 00000073 ecall + 80002b50: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoadd_d.elf b/test/riscv/tests/rv64ua-v-amoadd_d.elf new file mode 100644 index 00000000..655f27c6 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoadd_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoadd_w.dump b/test/riscv/tests/rv64ua-v-amoadd_w.dump new file mode 100644 index 00000000..b8ca9c8d --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoadd_w.dump @@ -0,0 +1,871 @@ + +rv64ua-v-amoadd_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00100793 li a5,1 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0806d7b7 lui a5,0x806d + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 4f578793 addi a5,a5,1269 # 806d4f5 <_start-0x77f92b0b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 00b6a72f amoadd.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71263 bne a4,t4,80002b2c + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 800e8e9b addiw t4,t4,-2048 + 80002af8: 00300193 li gp,3 + 80002afc: 03d79863 bne a5,t4,80002b2c + +0000000080002b00 : + 80002b00: 800005b7 lui a1,0x80000 + 80002b04: 00b6a72f amoadd.w a4,a1,(a3) + 80002b08: 80000eb7 lui t4,0x80000 + 80002b0c: 800e8e9b addiw t4,t4,-2048 + 80002b10: 00400193 li gp,4 + 80002b14: 01d71c63 bne a4,t4,80002b2c + +0000000080002b18 : + 80002b18: 0006a783 lw a5,0(a3) + 80002b1c: 80000e93 li t4,-2048 + 80002b20: 00500193 li gp,5 + 80002b24: 01d79463 bne a5,t4,80002b2c + 80002b28: 00301a63 bne zero,gp,80002b3c + +0000000080002b2c : + 80002b2c: 00119513 slli a0,gp,0x1 + 80002b30: 00050063 beqz a0,80002b30 + 80002b34: 00156513 ori a0,a0,1 + 80002b38: 00000073 ecall + +0000000080002b3c : + 80002b3c: 00100513 li a0,1 + 80002b40: 00000073 ecall + 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoadd_w.elf b/test/riscv/tests/rv64ua-v-amoadd_w.elf new file mode 100644 index 00000000..32d6c1a9 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoadd_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoand_d.dump b/test/riscv/tests/rv64ua-v-amoand_d.dump new file mode 100644 index 00000000..89e47221 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoand_d.dump @@ -0,0 +1,871 @@ + +rv64ua-v-amoand_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02800793 li a5,40 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 02f8b7b7 lui a5,0x2f8b + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 4c878793 addi a5,a5,1224 # 2f8b4c8 <_start-0x7d074b38> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 60b6b72f amoand.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71263 bne a4,t4,80002b2c + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79a63 bne a5,t4,80002b2c + +0000000080002afc : + 80002afc: 0010059b addiw a1,zero,1 + 80002b00: 01f59593 slli a1,a1,0x1f + 80002b04: 60b6b72f amoand.d a4,a1,(a3) + 80002b08: 80000eb7 lui t4,0x80000 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71e63 bne a4,t4,80002b2c + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: 00100e9b addiw t4,zero,1 + 80002b1c: 01fe9e93 slli t4,t4,0x1f + 80002b20: 00500193 li gp,5 + 80002b24: 01d79463 bne a5,t4,80002b2c + 80002b28: 00301a63 bne zero,gp,80002b3c + +0000000080002b2c : + 80002b2c: 00119513 slli a0,gp,0x1 + 80002b30: 00050063 beqz a0,80002b30 + 80002b34: 00156513 ori a0,a0,1 + 80002b38: 00000073 ecall + +0000000080002b3c : + 80002b3c: 00100513 li a0,1 + 80002b40: 00000073 ecall + 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoand_d.elf b/test/riscv/tests/rv64ua-v-amoand_d.elf new file mode 100644 index 00000000..ae0fa7c0 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoand_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoand_w.dump b/test/riscv/tests/rv64ua-v-amoand_w.dump new file mode 100644 index 00000000..0fdbc133 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoand_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amoand_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00900793 li a5,9 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 068a27b7 lui a5,0x68a2 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: d4878793 addi a5,a5,-696 # 68a1d48 <_start-0x7975e2b8> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 60b6a72f amoand.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: 0010059b addiw a1,zero,1 + 80002b00: 01f59593 slli a1,a1,0x1f + 80002b04: 60b6a72f amoand.w a4,a1,(a3) + 80002b08: 80000eb7 lui t4,0x80000 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: 80000eb7 lui t4,0x80000 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoand_w.elf b/test/riscv/tests/rv64ua-v-amoand_w.elf new file mode 100644 index 00000000..97e45f4f Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoand_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomax_d.dump b/test/riscv/tests/rv64ua-v-amomax_d.dump new file mode 100644 index 00000000..d69d15d2 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomax_d.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomax_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03c00793 li a5,60 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 09d2d7b7 lui a5,0x9d2d + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 6b578793 addi a5,a5,1717 # 9d2d6b5 <_start-0x762d294b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: a0b6b72f amomax.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: 00100593 li a1,1 + 80002b00: 0006b023 sd zero,0(a3) + 80002b04: a0b6b72f amomax.d a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: 00100e93 li t4,1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomax_d.elf b/test/riscv/tests/rv64ua-v-amomax_d.elf new file mode 100644 index 00000000..04dfdae4 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomax_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomax_w.dump b/test/riscv/tests/rv64ua-v-amomax_w.dump new file mode 100644 index 00000000..eb204ee5 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomax_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomax_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02700793 li a5,39 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 06a237b7 lui a5,0x6a23 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 87378793 addi a5,a5,-1933 # 6a22873 <_start-0x795dd78d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: a0b6a72f amomax.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: 00100593 li a1,1 + 80002b00: 0006a023 sw zero,0(a3) + 80002b04: a0b6a72f amomax.w a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: 00100e93 li t4,1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomax_w.elf b/test/riscv/tests/rv64ua-v-amomax_w.elf new file mode 100644 index 00000000..49521793 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomax_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomaxu_d.dump b/test/riscv/tests/rv64ua-v-amomaxu_d.dump new file mode 100644 index 00000000..271a03c5 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomaxu_d.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomaxu_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03700793 li a5,55 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 00b117b7 lui a5,0xb11 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: cc678793 addi a5,a5,-826 # b10cc6 <_start-0x7f4ef33a> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: e0b6b72f amomaxu.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006b023 sd zero,0(a3) + 80002b04: e0b6b72f amomaxu.d a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: fff00e93 li t4,-1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomaxu_d.elf b/test/riscv/tests/rv64ua-v-amomaxu_d.elf new file mode 100644 index 00000000..0b9930fe Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomaxu_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomaxu_w.dump b/test/riscv/tests/rv64ua-v-amomaxu_w.dump new file mode 100644 index 00000000..d6f336eb --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomaxu_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomaxu_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00700793 li a5,7 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0d8487b7 lui a5,0xd848 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: c5e78793 addi a5,a5,-930 # d847c5e <_start-0x727b83a2> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: e0b6a72f amomaxu.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006a023 sw zero,0(a3) + 80002b04: e0b6a72f amomaxu.w a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: fff00e93 li t4,-1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomaxu_w.elf b/test/riscv/tests/rv64ua-v-amomaxu_w.elf new file mode 100644 index 00000000..989ad0c5 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomaxu_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomin_d.dump b/test/riscv/tests/rv64ua-v-amomin_d.dump new file mode 100644 index 00000000..a97febdb --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomin_d.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomin_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00500793 li a5,5 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0353d7b7 lui a5,0x353d + 80002a70: 000805b7 lui a1,0x80 + 80002a74: a0778793 addi a5,a5,-1529 # 353ca07 <_start-0x7cac35f9> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 80b6b72f amomin.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006b023 sd zero,0(a3) + 80002b04: 80b6b72f amomin.d a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: fff00e93 li t4,-1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomin_d.elf b/test/riscv/tests/rv64ua-v-amomin_d.elf new file mode 100644 index 00000000..c1364087 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomin_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amomin_w.dump b/test/riscv/tests/rv64ua-v-amomin_w.dump new file mode 100644 index 00000000..a436c950 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amomin_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amomin_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03800793 li a5,56 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0ccca7b7 lui a5,0xccca + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 0ea78793 addi a5,a5,234 # ccca0ea <_start-0x73335f16> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 80b6a72f amomin.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006a023 sw zero,0(a3) + 80002b04: 80b6a72f amomin.w a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: fff00e93 li t4,-1 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomin_w.elf b/test/riscv/tests/rv64ua-v-amomin_w.elf new file mode 100644 index 00000000..46fa3ac6 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amomin_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amominu_d.dump b/test/riscv/tests/rv64ua-v-amominu_d.dump new file mode 100644 index 00000000..693d6a66 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amominu_d.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amominu_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02800793 li a5,40 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 08b4f7b7 lui a5,0x8b4f + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 5cb78793 addi a5,a5,1483 # 8b4f5cb <_start-0x774b0a35> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: c0b6b72f amominu.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006b023 sd zero,0(a3) + 80002b04: c0b6b72f amominu.d a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: 00000e93 li t4,0 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amominu_d.elf b/test/riscv/tests/rv64ua-v-amominu_d.elf new file mode 100644 index 00000000..1c7e7db1 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amominu_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amominu_w.dump b/test/riscv/tests/rv64ua-v-amominu_w.dump new file mode 100644 index 00000000..ac8240d7 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amominu_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amominu_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 01500793 li a5,21 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 083c07b7 lui a5,0x83c0 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 36f78793 addi a5,a5,879 # 83c036f <_start-0x77c3fc91> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: c0b6a72f amominu.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: fff00593 li a1,-1 + 80002b00: 0006a023 sw zero,0(a3) + 80002b04: c0b6a72f amominu.w a4,a1,(a3) + 80002b08: 00000e93 li t4,0 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: 00000e93 li t4,0 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amominu_w.elf b/test/riscv/tests/rv64ua-v-amominu_w.elf new file mode 100644 index 00000000..b2556893 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amominu_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoor_d.dump b/test/riscv/tests/rv64ua-v-amoor_d.dump new file mode 100644 index 00000000..6bf5fa12 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoor_d.dump @@ -0,0 +1,869 @@ + +rv64ua-v-amoor_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6e868693 addi a3,a3,1768 # 80002b40 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 71c60613 addi a2,a2,1820 # 80002bd0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6e460613 addi a2,a2,1764 # 80002be8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63468693 addi a3,a3,1588 # 80002b88 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65068693 addi a3,a3,1616 # 80002cc0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d060613 addi a2,a2,1488 # 80002c98 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50468693 addi a3,a3,1284 # 80002cf0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42468693 addi a3,a3,1060 # 80002c60 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3b468693 addi a3,a3,948 # 80002c28 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02d00793 li a5,45 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 006937b7 lui a5,0x693 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b1378793 addi a5,a5,-1261 # 692b13 <_start-0x7f96d4ed> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 40b6b72f amoor.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 03d71e63 bne a4,t4,80002b24 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79663 bne a5,t4,80002b24 + +0000000080002afc : + 80002afc: 00100593 li a1,1 + 80002b00: 40b6b72f amoor.d a4,a1,(a3) + 80002b04: 80000e93 li t4,-2048 + 80002b08: 00400193 li gp,4 + 80002b0c: 01d71c63 bne a4,t4,80002b24 + +0000000080002b10 : + 80002b10: 0006b783 ld a5,0(a3) + 80002b14: 80100e93 li t4,-2047 + 80002b18: 00500193 li gp,5 + 80002b1c: 01d79463 bne a5,t4,80002b24 + 80002b20: 00301a63 bne zero,gp,80002b34 + +0000000080002b24 : + 80002b24: 00119513 slli a0,gp,0x1 + 80002b28: 00050063 beqz a0,80002b28 + 80002b2c: 00156513 ori a0,a0,1 + 80002b30: 00000073 ecall + +0000000080002b34 : + 80002b34: 00100513 li a0,1 + 80002b38: 00000073 ecall + 80002b3c: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoor_d.elf b/test/riscv/tests/rv64ua-v-amoor_d.elf new file mode 100644 index 00000000..ce15b22d Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoor_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoor_w.dump b/test/riscv/tests/rv64ua-v-amoor_w.dump new file mode 100644 index 00000000..71a4ebee --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoor_w.dump @@ -0,0 +1,869 @@ + +rv64ua-v-amoor_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6e868693 addi a3,a3,1768 # 80002b40 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 71c60613 addi a2,a2,1820 # 80002bd0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6e460613 addi a2,a2,1764 # 80002be8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63468693 addi a3,a3,1588 # 80002b88 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65068693 addi a3,a3,1616 # 80002cc0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d060613 addi a2,a2,1488 # 80002c98 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50468693 addi a3,a3,1284 # 80002cf0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42468693 addi a3,a3,1060 # 80002c60 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3b468693 addi a3,a3,948 # 80002c28 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00f00793 li a5,15 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 092c77b7 lui a5,0x92c7 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: f3678793 addi a5,a5,-202 # 92c6f36 <_start-0x76d390ca> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 40b6a72f amoor.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 03d71e63 bne a4,t4,80002b24 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79663 bne a5,t4,80002b24 + +0000000080002afc : + 80002afc: 00100593 li a1,1 + 80002b00: 40b6a72f amoor.w a4,a1,(a3) + 80002b04: 80000e93 li t4,-2048 + 80002b08: 00400193 li gp,4 + 80002b0c: 01d71c63 bne a4,t4,80002b24 + +0000000080002b10 : + 80002b10: 0006a783 lw a5,0(a3) + 80002b14: 80100e93 li t4,-2047 + 80002b18: 00500193 li gp,5 + 80002b1c: 01d79463 bne a5,t4,80002b24 + 80002b20: 00301a63 bne zero,gp,80002b34 + +0000000080002b24 : + 80002b24: 00119513 slli a0,gp,0x1 + 80002b28: 00050063 beqz a0,80002b28 + 80002b2c: 00156513 ori a0,a0,1 + 80002b30: 00000073 ecall + +0000000080002b34 : + 80002b34: 00100513 li a0,1 + 80002b38: 00000073 ecall + 80002b3c: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoor_w.elf b/test/riscv/tests/rv64ua-v-amoor_w.elf new file mode 100644 index 00000000..44f0a915 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoor_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoswap_d.dump b/test/riscv/tests/rv64ua-v-amoswap_d.dump new file mode 100644 index 00000000..bcb607be --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoswap_d.dump @@ -0,0 +1,871 @@ + +rv64ua-v-amoswap_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03700793 li a5,55 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 039c87b7 lui a5,0x39c8 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: e8a78793 addi a5,a5,-374 # 39c7e8a <_start-0x7c638176> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 08b6b72f amoswap.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71263 bne a4,t4,80002b2c + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79a63 bne a5,t4,80002b2c + +0000000080002afc : + 80002afc: 0010059b addiw a1,zero,1 + 80002b00: 01f59593 slli a1,a1,0x1f + 80002b04: 08b6b72f amoswap.d a4,a1,(a3) + 80002b08: 80000e93 li t4,-2048 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71e63 bne a4,t4,80002b2c + +0000000080002b14 : + 80002b14: 0006b783 ld a5,0(a3) + 80002b18: 00100e9b addiw t4,zero,1 + 80002b1c: 01fe9e93 slli t4,t4,0x1f + 80002b20: 00500193 li gp,5 + 80002b24: 01d79463 bne a5,t4,80002b2c + 80002b28: 00301a63 bne zero,gp,80002b3c + +0000000080002b2c : + 80002b2c: 00119513 slli a0,gp,0x1 + 80002b30: 00050063 beqz a0,80002b30 + 80002b34: 00156513 ori a0,a0,1 + 80002b38: 00000073 ecall + +0000000080002b3c : + 80002b3c: 00100513 li a0,1 + 80002b40: 00000073 ecall + 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoswap_d.elf b/test/riscv/tests/rv64ua-v-amoswap_d.elf new file mode 100644 index 00000000..6f8a8173 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoswap_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoswap_w.dump b/test/riscv/tests/rv64ua-v-amoswap_w.dump new file mode 100644 index 00000000..2369b0d6 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoswap_w.dump @@ -0,0 +1,870 @@ + +rv64ua-v-amoswap_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00d00793 li a5,13 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0788e7b7 lui a5,0x788e + 80002a70: 000805b7 lui a1,0x80 + 80002a74: c2478793 addi a5,a5,-988 # 788dc24 <_start-0x787723dc> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 08b6a72f amoswap.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71063 bne a4,t4,80002b28 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000e93 li t4,-2048 + 80002af4: 00300193 li gp,3 + 80002af8: 03d79863 bne a5,t4,80002b28 + +0000000080002afc : + 80002afc: 0010059b addiw a1,zero,1 + 80002b00: 01f59593 slli a1,a1,0x1f + 80002b04: 08b6a72f amoswap.w a4,a1,(a3) + 80002b08: 80000e93 li t4,-2048 + 80002b0c: 00400193 li gp,4 + 80002b10: 01d71c63 bne a4,t4,80002b28 + +0000000080002b14 : + 80002b14: 0006a783 lw a5,0(a3) + 80002b18: 80000eb7 lui t4,0x80000 + 80002b1c: 00500193 li gp,5 + 80002b20: 01d79463 bne a5,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoswap_w.elf b/test/riscv/tests/rv64ua-v-amoswap_w.elf new file mode 100644 index 00000000..58a23d37 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoswap_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoxor_d.dump b/test/riscv/tests/rv64ua-v-amoxor_d.dump new file mode 100644 index 00000000..6fa564d8 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoxor_d.dump @@ -0,0 +1,872 @@ + +rv64ua-v-amoxor_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f868693 addi a3,a3,1784 # 80002b50 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72c60613 addi a2,a2,1836 # 80002be0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6f460613 addi a2,a2,1780 # 80002bf8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 64468693 addi a3,a3,1604 # 80002b98 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 66068693 addi a3,a3,1632 # 80002cd0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5e060613 addi a2,a2,1504 # 80002ca8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 51468693 addi a3,a3,1300 # 80002d00 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 43468693 addi a3,a3,1076 # 80002c70 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3c468693 addi a3,a3,964 # 80002c38 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02e00793 li a5,46 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a9e67b7 lui a5,0xa9e6 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 11178793 addi a5,a5,273 # a9e6111 <_start-0x75619eef> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6b023 sd a0,0(a3) + 80002adc: 20b6b72f amoxor.d a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71463 bne a4,t4,80002b30 + +0000000080002aec : + 80002aec: 0006b783 ld a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 800e8e9b addiw t4,t4,-2048 + 80002af8: 00300193 li gp,3 + 80002afc: 03d79a63 bne a5,t4,80002b30 + +0000000080002b00 : + 80002b00: 00100593 li a1,1 + 80002b04: 20b6b72f amoxor.d a4,a1,(a3) + 80002b08: 80000eb7 lui t4,0x80000 + 80002b0c: 800e8e9b addiw t4,t4,-2048 + 80002b10: 00400193 li gp,4 + 80002b14: 01d71e63 bne a4,t4,80002b30 + +0000000080002b18 : + 80002b18: 0006b783 ld a5,0(a3) + 80002b1c: 80000eb7 lui t4,0x80000 + 80002b20: 801e8e9b addiw t4,t4,-2047 + 80002b24: 00500193 li gp,5 + 80002b28: 01d79463 bne a5,t4,80002b30 + 80002b2c: 00301a63 bne zero,gp,80002b40 + +0000000080002b30 : + 80002b30: 00119513 slli a0,gp,0x1 + 80002b34: 00050063 beqz a0,80002b34 + 80002b38: 00156513 ori a0,a0,1 + 80002b3c: 00000073 ecall + +0000000080002b40 : + 80002b40: 00100513 li a0,1 + 80002b44: 00000073 ecall + 80002b48: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoxor_d.elf b/test/riscv/tests/rv64ua-v-amoxor_d.elf new file mode 100644 index 00000000..963af595 Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoxor_d.elf differ diff --git a/test/riscv/tests/rv64ua-v-amoxor_w.dump b/test/riscv/tests/rv64ua-v-amoxor_w.dump new file mode 100644 index 00000000..6ced7407 --- /dev/null +++ b/test/riscv/tests/rv64ua-v-amoxor_w.dump @@ -0,0 +1,874 @@ + +rv64ua-v-amoxor_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 70068693 addi a3,a3,1792 # 80002b58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 73460613 addi a2,a2,1844 # 80002be8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6fc60613 addi a2,a2,1788 # 80002c00 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 64c68693 addi a3,a3,1612 # 80002ba0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 66868693 addi a3,a3,1640 # 80002cd8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5e860613 addi a2,a2,1512 # 80002cb0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 51c68693 addi a3,a3,1308 # 80002d08 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 43c68693 addi a3,a3,1084 # 80002c78 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3cc68693 addi a3,a3,972 # 80002c40 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00600793 li a5,6 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 078757b7 lui a5,0x7875 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 2db78793 addi a5,a5,731 # 78752db <_start-0x7878ad25> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 80000537 lui a0,0x80000 + 80002acc: 80000593 li a1,-2048 + 80002ad0: 00000697 auipc a3,0x0 + 80002ad4: 53068693 addi a3,a3,1328 # 80003000 + 80002ad8: 00a6a023 sw a0,0(a3) + 80002adc: 20b6a72f amoxor.w a4,a1,(a3) + 80002ae0: 80000eb7 lui t4,0x80000 + 80002ae4: 00200193 li gp,2 + 80002ae8: 05d71863 bne a4,t4,80002b38 + +0000000080002aec : + 80002aec: 0006a783 lw a5,0(a3) + 80002af0: 80000eb7 lui t4,0x80000 + 80002af4: 800e8e9b addiw t4,t4,-2048 + 80002af8: 00300193 li gp,3 + 80002afc: 03d79e63 bne a5,t4,80002b38 + +0000000080002b00 : + 80002b00: 0030059b addiw a1,zero,3 + 80002b04: 01e59593 slli a1,a1,0x1e + 80002b08: 00158593 addi a1,a1,1 + 80002b0c: 20b6a72f amoxor.w a4,a1,(a3) + 80002b10: 80000eb7 lui t4,0x80000 + 80002b14: 800e8e9b addiw t4,t4,-2048 + 80002b18: 00400193 li gp,4 + 80002b1c: 01d71e63 bne a4,t4,80002b38 + +0000000080002b20 : + 80002b20: 0006a783 lw a5,0(a3) + 80002b24: c0000eb7 lui t4,0xc0000 + 80002b28: 801e8e9b addiw t4,t4,-2047 + 80002b2c: 00500193 li gp,5 + 80002b30: 01d79463 bne a5,t4,80002b38 + 80002b34: 00301a63 bne zero,gp,80002b48 + +0000000080002b38 : + 80002b38: 00119513 slli a0,gp,0x1 + 80002b3c: 00050063 beqz a0,80002b3c + 80002b40: 00156513 ori a0,a0,1 + 80002b44: 00000073 ecall + +0000000080002b48 : + 80002b48: 00100513 li a0,1 + 80002b4c: 00000073 ecall + 80002b50: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoxor_w.elf b/test/riscv/tests/rv64ua-v-amoxor_w.elf new file mode 100644 index 00000000..3b91cc1e Binary files /dev/null and b/test/riscv/tests/rv64ua-v-amoxor_w.elf differ diff --git a/test/riscv/tests/rv64ua-v-lrsc.dump b/test/riscv/tests/rv64ua-v-lrsc.dump new file mode 100644 index 00000000..5678673c --- /dev/null +++ b/test/riscv/tests/rv64ua-v-lrsc.dump @@ -0,0 +1,1426 @@ + +rv64ua-v-lrsc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 75868693 addi a3,a3,1880 # 80002bb0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 78c60613 addi a2,a2,1932 # 80002c40 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 75460613 addi a2,a2,1876 # 80002c58 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6a468693 addi a3,a3,1700 # 80002bf8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6c068693 addi a3,a3,1728 # 80002d30 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 64060613 addi a2,a2,1600 # 80002d08 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 57468693 addi a3,a3,1396 # 80002d60 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 49468693 addi a3,a3,1172 # 80002cd0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 42468693 addi a3,a3,1060 # 80002c98 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02c00793 li a5,44 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0b4d77b7 lui a5,0xb4d7 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 59f78793 addi a5,a5,1439 # b4d759f <_start-0x74b28a61> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000517 auipc a0,0x0 + 80002acc: 53850513 addi a0,a0,1336 # 80003000 + 80002ad0: 00100593 li a1,1 + 80002ad4: 00b5262f amoadd.w a2,a1,(a0) + 80002ad8: 00100693 li a3,1 + 80002adc: fed67ee3 bleu a3,a2,80002ad8 + 80002ae0: 00052583 lw a1,0(a0) + 80002ae4: fed5eee3 bltu a1,a3,80002ae0 + +0000000080002ae8 : + 80002ae8: 00000517 auipc a0,0x0 + 80002aec: 52050513 addi a0,a0,1312 # 80003008 + 80002af0: 1805272f sc.w a4,zero,(a0) + 80002af4: 00100e93 li t4,1 + 80002af8: 00200193 li gp,2 + 80002afc: 09d71a63 bne a4,t4,80002b90 + +0000000080002b00 : + 80002b00: 00000517 auipc a0,0x0 + 80002b04: 50850513 addi a0,a0,1288 # 80003008 + 80002b08: 00001597 auipc a1,0x1 + 80002b0c: 90458593 addi a1,a1,-1788 # 8000340c + 80002b10: 1005a5af lr.w a1,(a1) + 80002b14: 18b5272f sc.w a4,a1,(a0) + 80002b18: 00100e93 li t4,1 + 80002b1c: 00300193 li gp,3 + 80002b20: 07d71863 bne a4,t4,80002b90 + 80002b24: 00000517 auipc a0,0x0 + 80002b28: 4e450513 addi a0,a0,1252 # 80003008 + 80002b2c: 40000593 li a1,1024 + 80002b30: 00160613 addi a2,a2,1 + 80002b34: 1005272f lr.w a4,(a0) + 80002b38: 00c70733 add a4,a4,a2 + 80002b3c: 18e5272f sc.w a4,a4,(a0) + 80002b40: fe071ae3 bnez a4,80002b34 + 80002b44: fff58593 addi a1,a1,-1 + 80002b48: fe0596e3 bnez a1,80002b34 + 80002b4c: 00000517 auipc a0,0x0 + 80002b50: 4b850513 addi a0,a0,1208 # 80003004 + 80002b54: 00100593 li a1,1 + 80002b58: 00b5202f amoadd.w zero,a1,(a0) + 80002b5c: 00052583 lw a1,0(a0) + 80002b60: fed5cee3 blt a1,a3,80002b5c + 80002b64: 0ff0000f fence + +0000000080002b68 : + 80002b68: 00000517 auipc a0,0x0 + 80002b6c: 4a052503 lw a0,1184(a0) # 80003008 + 80002b70: 00969593 slli a1,a3,0x9 + 80002b74: 40b50533 sub a0,a0,a1 + 80002b78: fff68693 addi a3,a3,-1 + 80002b7c: fe06dce3 bgez a3,80002b74 + 80002b80: 00000e93 li t4,0 + 80002b84: 00400193 li gp,4 + 80002b88: 01d51463 bne a0,t4,80002b90 + 80002b8c: 00301a63 bne zero,gp,80002ba0 + +0000000080002b90 : + 80002b90: 00119513 slli a0,gp,0x1 + 80002b94: 00050063 beqz a0,80002b94 + 80002b98: 00156513 ori a0,a0,1 + 80002b9c: 00000073 ecall + +0000000080002ba0 : + 80002ba0: 00100513 li a0,1 + 80002ba4: 00000073 ecall + 80002ba8: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 0000 unimp + 80003002: 0000 unimp + +0000000080003004 : + 80003004: 0000 unimp + 80003006: 0000 unimp + +0000000080003008 : + 80003008: 0000 unimp + 8000300a: 0000 unimp + 8000300c: 0000 unimp + 8000300e: 0000 unimp + 80003010: 0000 unimp + 80003012: 0000 unimp + 80003014: 0000 unimp + 80003016: 0000 unimp + 80003018: 0000 unimp + 8000301a: 0000 unimp + 8000301c: 0000 unimp + 8000301e: 0000 unimp + 80003020: 0000 unimp + 80003022: 0000 unimp + 80003024: 0000 unimp + 80003026: 0000 unimp + 80003028: 0000 unimp + 8000302a: 0000 unimp + 8000302c: 0000 unimp + 8000302e: 0000 unimp + 80003030: 0000 unimp + 80003032: 0000 unimp + 80003034: 0000 unimp + 80003036: 0000 unimp + 80003038: 0000 unimp + 8000303a: 0000 unimp + 8000303c: 0000 unimp + 8000303e: 0000 unimp + 80003040: 0000 unimp + 80003042: 0000 unimp + 80003044: 0000 unimp + 80003046: 0000 unimp + 80003048: 0000 unimp + 8000304a: 0000 unimp + 8000304c: 0000 unimp + 8000304e: 0000 unimp + 80003050: 0000 unimp + 80003052: 0000 unimp + 80003054: 0000 unimp + 80003056: 0000 unimp + 80003058: 0000 unimp + 8000305a: 0000 unimp + 8000305c: 0000 unimp + 8000305e: 0000 unimp + 80003060: 0000 unimp + 80003062: 0000 unimp + 80003064: 0000 unimp + 80003066: 0000 unimp + 80003068: 0000 unimp + 8000306a: 0000 unimp + 8000306c: 0000 unimp + 8000306e: 0000 unimp + 80003070: 0000 unimp + 80003072: 0000 unimp + 80003074: 0000 unimp + 80003076: 0000 unimp + 80003078: 0000 unimp + 8000307a: 0000 unimp + 8000307c: 0000 unimp + 8000307e: 0000 unimp + 80003080: 0000 unimp + 80003082: 0000 unimp + 80003084: 0000 unimp + 80003086: 0000 unimp + 80003088: 0000 unimp + 8000308a: 0000 unimp + 8000308c: 0000 unimp + 8000308e: 0000 unimp + 80003090: 0000 unimp + 80003092: 0000 unimp + 80003094: 0000 unimp + 80003096: 0000 unimp + 80003098: 0000 unimp + 8000309a: 0000 unimp + 8000309c: 0000 unimp + 8000309e: 0000 unimp + 800030a0: 0000 unimp + 800030a2: 0000 unimp + 800030a4: 0000 unimp + 800030a6: 0000 unimp + 800030a8: 0000 unimp + 800030aa: 0000 unimp + 800030ac: 0000 unimp + 800030ae: 0000 unimp + 800030b0: 0000 unimp + 800030b2: 0000 unimp + 800030b4: 0000 unimp + 800030b6: 0000 unimp + 800030b8: 0000 unimp + 800030ba: 0000 unimp + 800030bc: 0000 unimp + 800030be: 0000 unimp + 800030c0: 0000 unimp + 800030c2: 0000 unimp + 800030c4: 0000 unimp + 800030c6: 0000 unimp + 800030c8: 0000 unimp + 800030ca: 0000 unimp + 800030cc: 0000 unimp + 800030ce: 0000 unimp + 800030d0: 0000 unimp + 800030d2: 0000 unimp + 800030d4: 0000 unimp + 800030d6: 0000 unimp + 800030d8: 0000 unimp + 800030da: 0000 unimp + 800030dc: 0000 unimp + 800030de: 0000 unimp + 800030e0: 0000 unimp + 800030e2: 0000 unimp + 800030e4: 0000 unimp + 800030e6: 0000 unimp + 800030e8: 0000 unimp + 800030ea: 0000 unimp + 800030ec: 0000 unimp + 800030ee: 0000 unimp + 800030f0: 0000 unimp + 800030f2: 0000 unimp + 800030f4: 0000 unimp + 800030f6: 0000 unimp + 800030f8: 0000 unimp + 800030fa: 0000 unimp + 800030fc: 0000 unimp + 800030fe: 0000 unimp + 80003100: 0000 unimp + 80003102: 0000 unimp + 80003104: 0000 unimp + 80003106: 0000 unimp + 80003108: 0000 unimp + 8000310a: 0000 unimp + 8000310c: 0000 unimp + 8000310e: 0000 unimp + 80003110: 0000 unimp + 80003112: 0000 unimp + 80003114: 0000 unimp + 80003116: 0000 unimp + 80003118: 0000 unimp + 8000311a: 0000 unimp + 8000311c: 0000 unimp + 8000311e: 0000 unimp + 80003120: 0000 unimp + 80003122: 0000 unimp + 80003124: 0000 unimp + 80003126: 0000 unimp + 80003128: 0000 unimp + 8000312a: 0000 unimp + 8000312c: 0000 unimp + 8000312e: 0000 unimp + 80003130: 0000 unimp + 80003132: 0000 unimp + 80003134: 0000 unimp + 80003136: 0000 unimp + 80003138: 0000 unimp + 8000313a: 0000 unimp + 8000313c: 0000 unimp + 8000313e: 0000 unimp + 80003140: 0000 unimp + 80003142: 0000 unimp + 80003144: 0000 unimp + 80003146: 0000 unimp + 80003148: 0000 unimp + 8000314a: 0000 unimp + 8000314c: 0000 unimp + 8000314e: 0000 unimp + 80003150: 0000 unimp + 80003152: 0000 unimp + 80003154: 0000 unimp + 80003156: 0000 unimp + 80003158: 0000 unimp + 8000315a: 0000 unimp + 8000315c: 0000 unimp + 8000315e: 0000 unimp + 80003160: 0000 unimp + 80003162: 0000 unimp + 80003164: 0000 unimp + 80003166: 0000 unimp + 80003168: 0000 unimp + 8000316a: 0000 unimp + 8000316c: 0000 unimp + 8000316e: 0000 unimp + 80003170: 0000 unimp + 80003172: 0000 unimp + 80003174: 0000 unimp + 80003176: 0000 unimp + 80003178: 0000 unimp + 8000317a: 0000 unimp + 8000317c: 0000 unimp + 8000317e: 0000 unimp + 80003180: 0000 unimp + 80003182: 0000 unimp + 80003184: 0000 unimp + 80003186: 0000 unimp + 80003188: 0000 unimp + 8000318a: 0000 unimp + 8000318c: 0000 unimp + 8000318e: 0000 unimp + 80003190: 0000 unimp + 80003192: 0000 unimp + 80003194: 0000 unimp + 80003196: 0000 unimp + 80003198: 0000 unimp + 8000319a: 0000 unimp + 8000319c: 0000 unimp + 8000319e: 0000 unimp + 800031a0: 0000 unimp + 800031a2: 0000 unimp + 800031a4: 0000 unimp + 800031a6: 0000 unimp + 800031a8: 0000 unimp + 800031aa: 0000 unimp + 800031ac: 0000 unimp + 800031ae: 0000 unimp + 800031b0: 0000 unimp + 800031b2: 0000 unimp + 800031b4: 0000 unimp + 800031b6: 0000 unimp + 800031b8: 0000 unimp + 800031ba: 0000 unimp + 800031bc: 0000 unimp + 800031be: 0000 unimp + 800031c0: 0000 unimp + 800031c2: 0000 unimp + 800031c4: 0000 unimp + 800031c6: 0000 unimp + 800031c8: 0000 unimp + 800031ca: 0000 unimp + 800031cc: 0000 unimp + 800031ce: 0000 unimp + 800031d0: 0000 unimp + 800031d2: 0000 unimp + 800031d4: 0000 unimp + 800031d6: 0000 unimp + 800031d8: 0000 unimp + 800031da: 0000 unimp + 800031dc: 0000 unimp + 800031de: 0000 unimp + 800031e0: 0000 unimp + 800031e2: 0000 unimp + 800031e4: 0000 unimp + 800031e6: 0000 unimp + 800031e8: 0000 unimp + 800031ea: 0000 unimp + 800031ec: 0000 unimp + 800031ee: 0000 unimp + 800031f0: 0000 unimp + 800031f2: 0000 unimp + 800031f4: 0000 unimp + 800031f6: 0000 unimp + 800031f8: 0000 unimp + 800031fa: 0000 unimp + 800031fc: 0000 unimp + 800031fe: 0000 unimp + 80003200: 0000 unimp + 80003202: 0000 unimp + 80003204: 0000 unimp + 80003206: 0000 unimp + 80003208: 0000 unimp + 8000320a: 0000 unimp + 8000320c: 0000 unimp + 8000320e: 0000 unimp + 80003210: 0000 unimp + 80003212: 0000 unimp + 80003214: 0000 unimp + 80003216: 0000 unimp + 80003218: 0000 unimp + 8000321a: 0000 unimp + 8000321c: 0000 unimp + 8000321e: 0000 unimp + 80003220: 0000 unimp + 80003222: 0000 unimp + 80003224: 0000 unimp + 80003226: 0000 unimp + 80003228: 0000 unimp + 8000322a: 0000 unimp + 8000322c: 0000 unimp + 8000322e: 0000 unimp + 80003230: 0000 unimp + 80003232: 0000 unimp + 80003234: 0000 unimp + 80003236: 0000 unimp + 80003238: 0000 unimp + 8000323a: 0000 unimp + 8000323c: 0000 unimp + 8000323e: 0000 unimp + 80003240: 0000 unimp + 80003242: 0000 unimp + 80003244: 0000 unimp + 80003246: 0000 unimp + 80003248: 0000 unimp + 8000324a: 0000 unimp + 8000324c: 0000 unimp + 8000324e: 0000 unimp + 80003250: 0000 unimp + 80003252: 0000 unimp + 80003254: 0000 unimp + 80003256: 0000 unimp + 80003258: 0000 unimp + 8000325a: 0000 unimp + 8000325c: 0000 unimp + 8000325e: 0000 unimp + 80003260: 0000 unimp + 80003262: 0000 unimp + 80003264: 0000 unimp + 80003266: 0000 unimp + 80003268: 0000 unimp + 8000326a: 0000 unimp + 8000326c: 0000 unimp + 8000326e: 0000 unimp + 80003270: 0000 unimp + 80003272: 0000 unimp + 80003274: 0000 unimp + 80003276: 0000 unimp + 80003278: 0000 unimp + 8000327a: 0000 unimp + 8000327c: 0000 unimp + 8000327e: 0000 unimp + 80003280: 0000 unimp + 80003282: 0000 unimp + 80003284: 0000 unimp + 80003286: 0000 unimp + 80003288: 0000 unimp + 8000328a: 0000 unimp + 8000328c: 0000 unimp + 8000328e: 0000 unimp + 80003290: 0000 unimp + 80003292: 0000 unimp + 80003294: 0000 unimp + 80003296: 0000 unimp + 80003298: 0000 unimp + 8000329a: 0000 unimp + 8000329c: 0000 unimp + 8000329e: 0000 unimp + 800032a0: 0000 unimp + 800032a2: 0000 unimp + 800032a4: 0000 unimp + 800032a6: 0000 unimp + 800032a8: 0000 unimp + 800032aa: 0000 unimp + 800032ac: 0000 unimp + 800032ae: 0000 unimp + 800032b0: 0000 unimp + 800032b2: 0000 unimp + 800032b4: 0000 unimp + 800032b6: 0000 unimp + 800032b8: 0000 unimp + 800032ba: 0000 unimp + 800032bc: 0000 unimp + 800032be: 0000 unimp + 800032c0: 0000 unimp + 800032c2: 0000 unimp + 800032c4: 0000 unimp + 800032c6: 0000 unimp + 800032c8: 0000 unimp + 800032ca: 0000 unimp + 800032cc: 0000 unimp + 800032ce: 0000 unimp + 800032d0: 0000 unimp + 800032d2: 0000 unimp + 800032d4: 0000 unimp + 800032d6: 0000 unimp + 800032d8: 0000 unimp + 800032da: 0000 unimp + 800032dc: 0000 unimp + 800032de: 0000 unimp + 800032e0: 0000 unimp + 800032e2: 0000 unimp + 800032e4: 0000 unimp + 800032e6: 0000 unimp + 800032e8: 0000 unimp + 800032ea: 0000 unimp + 800032ec: 0000 unimp + 800032ee: 0000 unimp + 800032f0: 0000 unimp + 800032f2: 0000 unimp + 800032f4: 0000 unimp + 800032f6: 0000 unimp + 800032f8: 0000 unimp + 800032fa: 0000 unimp + 800032fc: 0000 unimp + 800032fe: 0000 unimp + 80003300: 0000 unimp + 80003302: 0000 unimp + 80003304: 0000 unimp + 80003306: 0000 unimp + 80003308: 0000 unimp + 8000330a: 0000 unimp + 8000330c: 0000 unimp + 8000330e: 0000 unimp + 80003310: 0000 unimp + 80003312: 0000 unimp + 80003314: 0000 unimp + 80003316: 0000 unimp + 80003318: 0000 unimp + 8000331a: 0000 unimp + 8000331c: 0000 unimp + 8000331e: 0000 unimp + 80003320: 0000 unimp + 80003322: 0000 unimp + 80003324: 0000 unimp + 80003326: 0000 unimp + 80003328: 0000 unimp + 8000332a: 0000 unimp + 8000332c: 0000 unimp + 8000332e: 0000 unimp + 80003330: 0000 unimp + 80003332: 0000 unimp + 80003334: 0000 unimp + 80003336: 0000 unimp + 80003338: 0000 unimp + 8000333a: 0000 unimp + 8000333c: 0000 unimp + 8000333e: 0000 unimp + 80003340: 0000 unimp + 80003342: 0000 unimp + 80003344: 0000 unimp + 80003346: 0000 unimp + 80003348: 0000 unimp + 8000334a: 0000 unimp + 8000334c: 0000 unimp + 8000334e: 0000 unimp + 80003350: 0000 unimp + 80003352: 0000 unimp + 80003354: 0000 unimp + 80003356: 0000 unimp + 80003358: 0000 unimp + 8000335a: 0000 unimp + 8000335c: 0000 unimp + 8000335e: 0000 unimp + 80003360: 0000 unimp + 80003362: 0000 unimp + 80003364: 0000 unimp + 80003366: 0000 unimp + 80003368: 0000 unimp + 8000336a: 0000 unimp + 8000336c: 0000 unimp + 8000336e: 0000 unimp + 80003370: 0000 unimp + 80003372: 0000 unimp + 80003374: 0000 unimp + 80003376: 0000 unimp + 80003378: 0000 unimp + 8000337a: 0000 unimp + 8000337c: 0000 unimp + 8000337e: 0000 unimp + 80003380: 0000 unimp + 80003382: 0000 unimp + 80003384: 0000 unimp + 80003386: 0000 unimp + 80003388: 0000 unimp + 8000338a: 0000 unimp + 8000338c: 0000 unimp + 8000338e: 0000 unimp + 80003390: 0000 unimp + 80003392: 0000 unimp + 80003394: 0000 unimp + 80003396: 0000 unimp + 80003398: 0000 unimp + 8000339a: 0000 unimp + 8000339c: 0000 unimp + 8000339e: 0000 unimp + 800033a0: 0000 unimp + 800033a2: 0000 unimp + 800033a4: 0000 unimp + 800033a6: 0000 unimp + 800033a8: 0000 unimp + 800033aa: 0000 unimp + 800033ac: 0000 unimp + 800033ae: 0000 unimp + 800033b0: 0000 unimp + 800033b2: 0000 unimp + 800033b4: 0000 unimp + 800033b6: 0000 unimp + 800033b8: 0000 unimp + 800033ba: 0000 unimp + 800033bc: 0000 unimp + 800033be: 0000 unimp + 800033c0: 0000 unimp + 800033c2: 0000 unimp + 800033c4: 0000 unimp + 800033c6: 0000 unimp + 800033c8: 0000 unimp + 800033ca: 0000 unimp + 800033cc: 0000 unimp + 800033ce: 0000 unimp + 800033d0: 0000 unimp + 800033d2: 0000 unimp + 800033d4: 0000 unimp + 800033d6: 0000 unimp + 800033d8: 0000 unimp + 800033da: 0000 unimp + 800033dc: 0000 unimp + 800033de: 0000 unimp + 800033e0: 0000 unimp + 800033e2: 0000 unimp + 800033e4: 0000 unimp + 800033e6: 0000 unimp + 800033e8: 0000 unimp + 800033ea: 0000 unimp + 800033ec: 0000 unimp + 800033ee: 0000 unimp + 800033f0: 0000 unimp + 800033f2: 0000 unimp + 800033f4: 0000 unimp + 800033f6: 0000 unimp + 800033f8: 0000 unimp + 800033fa: 0000 unimp + 800033fc: 0000 unimp + 800033fe: 0000 unimp + 80003400: 0000 unimp + 80003402: 0000 unimp + 80003404: 0000 unimp + 80003406: 0000 unimp + 80003408: 0000 unimp + 8000340a: 0000 unimp + +000000008000340c : + 8000340c: 0000 unimp + 8000340e: 0000 unimp diff --git a/test/riscv/tests/rv64uc-p-rvc.elf b/test/riscv/tests/rv64uc-p-rvc.elf old mode 100755 new mode 100644 index dbfdfcc3..3421d31b Binary files a/test/riscv/tests/rv64uc-p-rvc.elf and b/test/riscv/tests/rv64uc-p-rvc.elf differ diff --git a/test/riscv/tests/rv64uc-v-rvc.dump b/test/riscv/tests/rv64uc-v-rvc.dump new file mode 100644 index 00000000..696b038d --- /dev/null +++ b/test/riscv/tests/rv64uc-v-rvc.dump @@ -0,0 +1,6518 @@ + +rv64uc-v-rvc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000c117 auipc sp,0xc + 8000001c: 6b810113 addi sp,sp,1720 # 8000c6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: fd050513 addi a0,a0,-48 # 80003000 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00005617 auipc a2,0x5 + 80002318: cec60613 addi a2,a2,-788 # 80007000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00009797 auipc a5,0x9 + 80002334: 4b878793 addi a5,a5,1208 # 8000b7e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00009717 auipc a4,0x9 + 80002348: 49c70713 addi a4,a4,1180 # 8000b7e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00009897 auipc a7,0x9 + 80002354: 48f8bc23 sd a5,1176(a7) # 8000b7e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00009797 auipc a5,0x9 + 80002384: 07078793 addi a5,a5,112 # 8000b3f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf4810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00009797 auipc a5,0x9 + 80002448: 3807be23 sd zero,924(a5) # 8000b7e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00004697 auipc a3,0x4 + 8000245c: b7068693 addi a3,a3,-1168 # 80005fc8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00004617 auipc a2,0x4 + 800024b8: ba460613 addi a2,a2,-1116 # 80006058 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00004617 auipc a2,0x4 + 80002508: b6c60613 addi a2,a2,-1172 # 80006070 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00004697 auipc a3,0x4 + 80002558: abc68693 addi a3,a3,-1348 # 80006010 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00004697 auipc a3,0x4 + 80002674: ad868693 addi a3,a3,-1320 # 80006148 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00004617 auipc a2,0x4 + 800026cc: a5860613 addi a2,a2,-1448 # 80006120 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00009d17 auipc s10,0x9 + 80002720: cd4d0d13 addi s10,s10,-812 # 8000b3f0 + 80002724: 00005b97 auipc s7,0x5 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80007000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00009a17 auipc s4,0x9 + 80002738: 0aca0a13 addi s4,s4,172 # 8000b7e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00009717 auipc a4,0x9 + 8000274c: 08f73c23 sd a5,152(a4) # 8000b7e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00009717 auipc a4,0x9 + 800027d4: 00f73823 sd a5,16(a4) # 8000b7e0 + 800027d8: 00009717 auipc a4,0x9 + 800027dc: 00f73823 sd a5,16(a4) # 8000b7e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00004697 auipc a3,0x4 + 800027f0: 98c68693 addi a3,a3,-1652 # 80006178 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00004697 auipc a3,0x4 + 80002840: 8ac68693 addi a3,a3,-1876 # 800060e8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00004697 auipc a3,0x4 + 80002878: 83c68693 addi a3,a3,-1988 # 800060b0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00005697 auipc a3,0x5 + 800028e0: 72468693 addi a3,a3,1828 # 80008000 + 800028e4: 00006717 auipc a4,0x6 + 800028e8: 71c70713 addi a4,a4,1820 # 80009000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00007797 auipc a5,0x7 + 800028f8: 70c78793 addi a5,a5,1804 # 8000a000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00004897 auipc a7,0x4 + 80002914: 6ed8b823 sd a3,1776(a7) # 80007000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00005697 auipc a3,0x5 + 80002920: 6ce6be23 sd a4,1756(a3) # 80007ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00004617 auipc a2,0x4 + 80002938: 6cc60613 addi a2,a2,1740 # 80007000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00007697 auipc a3,0x7 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80009ff8 + 8000294c: 00005717 auipc a4,0x5 + 80002950: 6af73a23 sd a5,1716(a4) # 80008000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00008697 auipc a3,0x8 + 800029c0: 64468693 addi a3,a3,1604 # 8000b000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00009617 auipc a2,0x9 + 800029d0: e0f63e23 sd a5,-484(a2) # 8000b7e8 + 800029d4: 00009797 auipc a5,0x9 + 800029d8: e0e7b623 sd a4,-500(a5) # 8000b7e0 + 800029dc: 00009317 auipc t1,0x9 + 800029e0: a1430313 addi t1,t1,-1516 # 8000b3f0 + 800029e4: 03000793 li a5,48 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00009797 auipc a5,0x9 + 80002a40: 9a07b623 sd zero,-1620(a5) # 8000b3e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0db157b7 lui a5,0xdb15 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 50c78793 addi a5,a5,1292 # db1550c <_start-0x724eaaf4> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + 80002ac8: 0000 unimp + 80002aca: 0000 unimp + 80002acc: 0000 unimp + 80002ace: 0000 unimp + 80002ad0: 0000 unimp + 80002ad2: 0000 unimp + 80002ad4: 0000 unimp + 80002ad6: 0000 unimp + 80002ad8: 0000 unimp + 80002ada: 0000 unimp + 80002adc: 0000 unimp + 80002ade: 0000 unimp + 80002ae0: 0000 unimp + 80002ae2: 0000 unimp + 80002ae4: 0000 unimp + 80002ae6: 0000 unimp + 80002ae8: 0000 unimp + 80002aea: 0000 unimp + 80002aec: 0000 unimp + 80002aee: 0000 unimp + 80002af0: 0000 unimp + 80002af2: 0000 unimp + 80002af4: 0000 unimp + 80002af6: 0000 unimp + 80002af8: 0000 unimp + 80002afa: 0000 unimp + 80002afc: 0000 unimp + 80002afe: 0000 unimp + 80002b00: 0000 unimp + 80002b02: 0000 unimp + 80002b04: 0000 unimp + 80002b06: 0000 unimp + 80002b08: 0000 unimp + 80002b0a: 0000 unimp + 80002b0c: 0000 unimp + 80002b0e: 0000 unimp + 80002b10: 0000 unimp + 80002b12: 0000 unimp + 80002b14: 0000 unimp + 80002b16: 0000 unimp + 80002b18: 0000 unimp + 80002b1a: 0000 unimp + 80002b1c: 0000 unimp + 80002b1e: 0000 unimp + 80002b20: 0000 unimp + 80002b22: 0000 unimp + 80002b24: 0000 unimp + 80002b26: 0000 unimp + 80002b28: 0000 unimp + 80002b2a: 0000 unimp + 80002b2c: 0000 unimp + 80002b2e: 0000 unimp + 80002b30: 0000 unimp + 80002b32: 0000 unimp + 80002b34: 0000 unimp + 80002b36: 0000 unimp + 80002b38: 0000 unimp + 80002b3a: 0000 unimp + 80002b3c: 0000 unimp + 80002b3e: 0000 unimp + 80002b40: 0000 unimp + 80002b42: 0000 unimp + 80002b44: 0000 unimp + 80002b46: 0000 unimp + 80002b48: 0000 unimp + 80002b4a: 0000 unimp + 80002b4c: 0000 unimp + 80002b4e: 0000 unimp + 80002b50: 0000 unimp + 80002b52: 0000 unimp + 80002b54: 0000 unimp + 80002b56: 0000 unimp + 80002b58: 0000 unimp + 80002b5a: 0000 unimp + 80002b5c: 0000 unimp + 80002b5e: 0000 unimp + 80002b60: 0000 unimp + 80002b62: 0000 unimp + 80002b64: 0000 unimp + 80002b66: 0000 unimp + 80002b68: 0000 unimp + 80002b6a: 0000 unimp + 80002b6c: 0000 unimp + 80002b6e: 0000 unimp + 80002b70: 0000 unimp + 80002b72: 0000 unimp + 80002b74: 0000 unimp + 80002b76: 0000 unimp + 80002b78: 0000 unimp + 80002b7a: 0000 unimp + 80002b7c: 0000 unimp + 80002b7e: 0000 unimp + 80002b80: 0000 unimp + 80002b82: 0000 unimp + 80002b84: 0000 unimp + 80002b86: 0000 unimp + 80002b88: 0000 unimp + 80002b8a: 0000 unimp + 80002b8c: 0000 unimp + 80002b8e: 0000 unimp + 80002b90: 0000 unimp + 80002b92: 0000 unimp + 80002b94: 0000 unimp + 80002b96: 0000 unimp + 80002b98: 0000 unimp + 80002b9a: 0000 unimp + 80002b9c: 0000 unimp + 80002b9e: 0000 unimp + 80002ba0: 0000 unimp + 80002ba2: 0000 unimp + 80002ba4: 0000 unimp + 80002ba6: 0000 unimp + 80002ba8: 0000 unimp + 80002baa: 0000 unimp + 80002bac: 0000 unimp + 80002bae: 0000 unimp + 80002bb0: 0000 unimp + 80002bb2: 0000 unimp + 80002bb4: 0000 unimp + 80002bb6: 0000 unimp + 80002bb8: 0000 unimp + 80002bba: 0000 unimp + 80002bbc: 0000 unimp + 80002bbe: 0000 unimp + 80002bc0: 0000 unimp + 80002bc2: 0000 unimp + 80002bc4: 0000 unimp + 80002bc6: 0000 unimp + 80002bc8: 0000 unimp + 80002bca: 0000 unimp + 80002bcc: 0000 unimp + 80002bce: 0000 unimp + 80002bd0: 0000 unimp + 80002bd2: 0000 unimp + 80002bd4: 0000 unimp + 80002bd6: 0000 unimp + 80002bd8: 0000 unimp + 80002bda: 0000 unimp + 80002bdc: 0000 unimp + 80002bde: 0000 unimp + 80002be0: 0000 unimp + 80002be2: 0000 unimp + 80002be4: 0000 unimp + 80002be6: 0000 unimp + 80002be8: 0000 unimp + 80002bea: 0000 unimp + 80002bec: 0000 unimp + 80002bee: 0000 unimp + 80002bf0: 0000 unimp + 80002bf2: 0000 unimp + 80002bf4: 0000 unimp + 80002bf6: 0000 unimp + 80002bf8: 0000 unimp + 80002bfa: 0000 unimp + 80002bfc: 0000 unimp + 80002bfe: 0000 unimp + 80002c00: 0000 unimp + 80002c02: 0000 unimp + 80002c04: 0000 unimp + 80002c06: 0000 unimp + 80002c08: 0000 unimp + 80002c0a: 0000 unimp + 80002c0c: 0000 unimp + 80002c0e: 0000 unimp + 80002c10: 0000 unimp + 80002c12: 0000 unimp + 80002c14: 0000 unimp + 80002c16: 0000 unimp + 80002c18: 0000 unimp + 80002c1a: 0000 unimp + 80002c1c: 0000 unimp + 80002c1e: 0000 unimp + 80002c20: 0000 unimp + 80002c22: 0000 unimp + 80002c24: 0000 unimp + 80002c26: 0000 unimp + 80002c28: 0000 unimp + 80002c2a: 0000 unimp + 80002c2c: 0000 unimp + 80002c2e: 0000 unimp + 80002c30: 0000 unimp + 80002c32: 0000 unimp + 80002c34: 0000 unimp + 80002c36: 0000 unimp + 80002c38: 0000 unimp + 80002c3a: 0000 unimp + 80002c3c: 0000 unimp + 80002c3e: 0000 unimp + 80002c40: 0000 unimp + 80002c42: 0000 unimp + 80002c44: 0000 unimp + 80002c46: 0000 unimp + 80002c48: 0000 unimp + 80002c4a: 0000 unimp + 80002c4c: 0000 unimp + 80002c4e: 0000 unimp + 80002c50: 0000 unimp + 80002c52: 0000 unimp + 80002c54: 0000 unimp + 80002c56: 0000 unimp + 80002c58: 0000 unimp + 80002c5a: 0000 unimp + 80002c5c: 0000 unimp + 80002c5e: 0000 unimp + 80002c60: 0000 unimp + 80002c62: 0000 unimp + 80002c64: 0000 unimp + 80002c66: 0000 unimp + 80002c68: 0000 unimp + 80002c6a: 0000 unimp + 80002c6c: 0000 unimp + 80002c6e: 0000 unimp + 80002c70: 0000 unimp + 80002c72: 0000 unimp + 80002c74: 0000 unimp + 80002c76: 0000 unimp + 80002c78: 0000 unimp + 80002c7a: 0000 unimp + 80002c7c: 0000 unimp + 80002c7e: 0000 unimp + 80002c80: 0000 unimp + 80002c82: 0000 unimp + 80002c84: 0000 unimp + 80002c86: 0000 unimp + 80002c88: 0000 unimp + 80002c8a: 0000 unimp + 80002c8c: 0000 unimp + 80002c8e: 0000 unimp + 80002c90: 0000 unimp + 80002c92: 0000 unimp + 80002c94: 0000 unimp + 80002c96: 0000 unimp + 80002c98: 0000 unimp + 80002c9a: 0000 unimp + 80002c9c: 0000 unimp + 80002c9e: 0000 unimp + 80002ca0: 0000 unimp + 80002ca2: 0000 unimp + 80002ca4: 0000 unimp + 80002ca6: 0000 unimp + 80002ca8: 0000 unimp + 80002caa: 0000 unimp + 80002cac: 0000 unimp + 80002cae: 0000 unimp + 80002cb0: 0000 unimp + 80002cb2: 0000 unimp + 80002cb4: 0000 unimp + 80002cb6: 0000 unimp + 80002cb8: 0000 unimp + 80002cba: 0000 unimp + 80002cbc: 0000 unimp + 80002cbe: 0000 unimp + 80002cc0: 0000 unimp + 80002cc2: 0000 unimp + 80002cc4: 0000 unimp + 80002cc6: 0000 unimp + 80002cc8: 0000 unimp + 80002cca: 0000 unimp + 80002ccc: 0000 unimp + 80002cce: 0000 unimp + 80002cd0: 0000 unimp + 80002cd2: 0000 unimp + 80002cd4: 0000 unimp + 80002cd6: 0000 unimp + 80002cd8: 0000 unimp + 80002cda: 0000 unimp + 80002cdc: 0000 unimp + 80002cde: 0000 unimp + 80002ce0: 0000 unimp + 80002ce2: 0000 unimp + 80002ce4: 0000 unimp + 80002ce6: 0000 unimp + 80002ce8: 0000 unimp + 80002cea: 0000 unimp + 80002cec: 0000 unimp + 80002cee: 0000 unimp + 80002cf0: 0000 unimp + 80002cf2: 0000 unimp + 80002cf4: 0000 unimp + 80002cf6: 0000 unimp + 80002cf8: 0000 unimp + 80002cfa: 0000 unimp + 80002cfc: 0000 unimp + 80002cfe: 0000 unimp + 80002d00: 0000 unimp + 80002d02: 0000 unimp + 80002d04: 0000 unimp + 80002d06: 0000 unimp + 80002d08: 0000 unimp + 80002d0a: 0000 unimp + 80002d0c: 0000 unimp + 80002d0e: 0000 unimp + 80002d10: 0000 unimp + 80002d12: 0000 unimp + 80002d14: 0000 unimp + 80002d16: 0000 unimp + 80002d18: 0000 unimp + 80002d1a: 0000 unimp + 80002d1c: 0000 unimp + 80002d1e: 0000 unimp + 80002d20: 0000 unimp + 80002d22: 0000 unimp + 80002d24: 0000 unimp + 80002d26: 0000 unimp + 80002d28: 0000 unimp + 80002d2a: 0000 unimp + 80002d2c: 0000 unimp + 80002d2e: 0000 unimp + 80002d30: 0000 unimp + 80002d32: 0000 unimp + 80002d34: 0000 unimp + 80002d36: 0000 unimp + 80002d38: 0000 unimp + 80002d3a: 0000 unimp + 80002d3c: 0000 unimp + 80002d3e: 0000 unimp + 80002d40: 0000 unimp + 80002d42: 0000 unimp + 80002d44: 0000 unimp + 80002d46: 0000 unimp + 80002d48: 0000 unimp + 80002d4a: 0000 unimp + 80002d4c: 0000 unimp + 80002d4e: 0000 unimp + 80002d50: 0000 unimp + 80002d52: 0000 unimp + 80002d54: 0000 unimp + 80002d56: 0000 unimp + 80002d58: 0000 unimp + 80002d5a: 0000 unimp + 80002d5c: 0000 unimp + 80002d5e: 0000 unimp + 80002d60: 0000 unimp + 80002d62: 0000 unimp + 80002d64: 0000 unimp + 80002d66: 0000 unimp + 80002d68: 0000 unimp + 80002d6a: 0000 unimp + 80002d6c: 0000 unimp + 80002d6e: 0000 unimp + 80002d70: 0000 unimp + 80002d72: 0000 unimp + 80002d74: 0000 unimp + 80002d76: 0000 unimp + 80002d78: 0000 unimp + 80002d7a: 0000 unimp + 80002d7c: 0000 unimp + 80002d7e: 0000 unimp + 80002d80: 0000 unimp + 80002d82: 0000 unimp + 80002d84: 0000 unimp + 80002d86: 0000 unimp + 80002d88: 0000 unimp + 80002d8a: 0000 unimp + 80002d8c: 0000 unimp + 80002d8e: 0000 unimp + 80002d90: 0000 unimp + 80002d92: 0000 unimp + 80002d94: 0000 unimp + 80002d96: 0000 unimp + 80002d98: 0000 unimp + 80002d9a: 0000 unimp + 80002d9c: 0000 unimp + 80002d9e: 0000 unimp + 80002da0: 0000 unimp + 80002da2: 0000 unimp + 80002da4: 0000 unimp + 80002da6: 0000 unimp + 80002da8: 0000 unimp + 80002daa: 0000 unimp + 80002dac: 0000 unimp + 80002dae: 0000 unimp + 80002db0: 0000 unimp + 80002db2: 0000 unimp + 80002db4: 0000 unimp + 80002db6: 0000 unimp + 80002db8: 0000 unimp + 80002dba: 0000 unimp + 80002dbc: 0000 unimp + 80002dbe: 0000 unimp + 80002dc0: 0000 unimp + 80002dc2: 0000 unimp + 80002dc4: 0000 unimp + 80002dc6: 0000 unimp + 80002dc8: 0000 unimp + 80002dca: 0000 unimp + 80002dcc: 0000 unimp + 80002dce: 0000 unimp + 80002dd0: 0000 unimp + 80002dd2: 0000 unimp + 80002dd4: 0000 unimp + 80002dd6: 0000 unimp + 80002dd8: 0000 unimp + 80002dda: 0000 unimp + 80002ddc: 0000 unimp + 80002dde: 0000 unimp + 80002de0: 0000 unimp + 80002de2: 0000 unimp + 80002de4: 0000 unimp + 80002de6: 0000 unimp + 80002de8: 0000 unimp + 80002dea: 0000 unimp + 80002dec: 0000 unimp + 80002dee: 0000 unimp + 80002df0: 0000 unimp + 80002df2: 0000 unimp + 80002df4: 0000 unimp + 80002df6: 0000 unimp + 80002df8: 0000 unimp + 80002dfa: 0000 unimp + 80002dfc: 0000 unimp + 80002dfe: 0000 unimp + 80002e00: 0000 unimp + 80002e02: 0000 unimp + 80002e04: 0000 unimp + 80002e06: 0000 unimp + 80002e08: 0000 unimp + 80002e0a: 0000 unimp + 80002e0c: 0000 unimp + 80002e0e: 0000 unimp + 80002e10: 0000 unimp + 80002e12: 0000 unimp + 80002e14: 0000 unimp + 80002e16: 0000 unimp + 80002e18: 0000 unimp + 80002e1a: 0000 unimp + 80002e1c: 0000 unimp + 80002e1e: 0000 unimp + 80002e20: 0000 unimp + 80002e22: 0000 unimp + 80002e24: 0000 unimp + 80002e26: 0000 unimp + 80002e28: 0000 unimp + 80002e2a: 0000 unimp + 80002e2c: 0000 unimp + 80002e2e: 0000 unimp + 80002e30: 0000 unimp + 80002e32: 0000 unimp + 80002e34: 0000 unimp + 80002e36: 0000 unimp + 80002e38: 0000 unimp + 80002e3a: 0000 unimp + 80002e3c: 0000 unimp + 80002e3e: 0000 unimp + 80002e40: 0000 unimp + 80002e42: 0000 unimp + 80002e44: 0000 unimp + 80002e46: 0000 unimp + 80002e48: 0000 unimp + 80002e4a: 0000 unimp + 80002e4c: 0000 unimp + 80002e4e: 0000 unimp + 80002e50: 0000 unimp + 80002e52: 0000 unimp + 80002e54: 0000 unimp + 80002e56: 0000 unimp + 80002e58: 0000 unimp + 80002e5a: 0000 unimp + 80002e5c: 0000 unimp + 80002e5e: 0000 unimp + 80002e60: 0000 unimp + 80002e62: 0000 unimp + 80002e64: 0000 unimp + 80002e66: 0000 unimp + 80002e68: 0000 unimp + 80002e6a: 0000 unimp + 80002e6c: 0000 unimp + 80002e6e: 0000 unimp + 80002e70: 0000 unimp + 80002e72: 0000 unimp + 80002e74: 0000 unimp + 80002e76: 0000 unimp + 80002e78: 0000 unimp + 80002e7a: 0000 unimp + 80002e7c: 0000 unimp + 80002e7e: 0000 unimp + 80002e80: 0000 unimp + 80002e82: 0000 unimp + 80002e84: 0000 unimp + 80002e86: 0000 unimp + 80002e88: 0000 unimp + 80002e8a: 0000 unimp + 80002e8c: 0000 unimp + 80002e8e: 0000 unimp + 80002e90: 0000 unimp + 80002e92: 0000 unimp + 80002e94: 0000 unimp + 80002e96: 0000 unimp + 80002e98: 0000 unimp + 80002e9a: 0000 unimp + 80002e9c: 0000 unimp + 80002e9e: 0000 unimp + 80002ea0: 0000 unimp + 80002ea2: 0000 unimp + 80002ea4: 0000 unimp + 80002ea6: 0000 unimp + 80002ea8: 0000 unimp + 80002eaa: 0000 unimp + 80002eac: 0000 unimp + 80002eae: 0000 unimp + 80002eb0: 0000 unimp + 80002eb2: 0000 unimp + 80002eb4: 0000 unimp + 80002eb6: 0000 unimp + 80002eb8: 0000 unimp + 80002eba: 0000 unimp + 80002ebc: 0000 unimp + 80002ebe: 0000 unimp + 80002ec0: 0000 unimp + 80002ec2: 0000 unimp + 80002ec4: 0000 unimp + 80002ec6: 0000 unimp + 80002ec8: 0000 unimp + 80002eca: 0000 unimp + 80002ecc: 0000 unimp + 80002ece: 0000 unimp + 80002ed0: 0000 unimp + 80002ed2: 0000 unimp + 80002ed4: 0000 unimp + 80002ed6: 0000 unimp + 80002ed8: 0000 unimp + 80002eda: 0000 unimp + 80002edc: 0000 unimp + 80002ede: 0000 unimp + 80002ee0: 0000 unimp + 80002ee2: 0000 unimp + 80002ee4: 0000 unimp + 80002ee6: 0000 unimp + 80002ee8: 0000 unimp + 80002eea: 0000 unimp + 80002eec: 0000 unimp + 80002eee: 0000 unimp + 80002ef0: 0000 unimp + 80002ef2: 0000 unimp + 80002ef4: 0000 unimp + 80002ef6: 0000 unimp + 80002ef8: 0000 unimp + 80002efa: 0000 unimp + 80002efc: 0000 unimp + 80002efe: 0000 unimp + 80002f00: 0000 unimp + 80002f02: 0000 unimp + 80002f04: 0000 unimp + 80002f06: 0000 unimp + 80002f08: 0000 unimp + 80002f0a: 0000 unimp + 80002f0c: 0000 unimp + 80002f0e: 0000 unimp + 80002f10: 0000 unimp + 80002f12: 0000 unimp + 80002f14: 0000 unimp + 80002f16: 0000 unimp + 80002f18: 0000 unimp + 80002f1a: 0000 unimp + 80002f1c: 0000 unimp + 80002f1e: 0000 unimp + 80002f20: 0000 unimp + 80002f22: 0000 unimp + 80002f24: 0000 unimp + 80002f26: 0000 unimp + 80002f28: 0000 unimp + 80002f2a: 0000 unimp + 80002f2c: 0000 unimp + 80002f2e: 0000 unimp + 80002f30: 0000 unimp + 80002f32: 0000 unimp + 80002f34: 0000 unimp + 80002f36: 0000 unimp + 80002f38: 0000 unimp + 80002f3a: 0000 unimp + 80002f3c: 0000 unimp + 80002f3e: 0000 unimp + 80002f40: 0000 unimp + 80002f42: 0000 unimp + 80002f44: 0000 unimp + 80002f46: 0000 unimp + 80002f48: 0000 unimp + 80002f4a: 0000 unimp + 80002f4c: 0000 unimp + 80002f4e: 0000 unimp + 80002f50: 0000 unimp + 80002f52: 0000 unimp + 80002f54: 0000 unimp + 80002f56: 0000 unimp + 80002f58: 0000 unimp + 80002f5a: 0000 unimp + 80002f5c: 0000 unimp + 80002f5e: 0000 unimp + 80002f60: 0000 unimp + 80002f62: 0000 unimp + 80002f64: 0000 unimp + 80002f66: 0000 unimp + 80002f68: 0000 unimp + 80002f6a: 0000 unimp + 80002f6c: 0000 unimp + 80002f6e: 0000 unimp + 80002f70: 0000 unimp + 80002f72: 0000 unimp + 80002f74: 0000 unimp + 80002f76: 0000 unimp + 80002f78: 0000 unimp + 80002f7a: 0000 unimp + 80002f7c: 0000 unimp + 80002f7e: 0000 unimp + 80002f80: 0000 unimp + 80002f82: 0000 unimp + 80002f84: 0000 unimp + 80002f86: 0000 unimp + 80002f88: 0000 unimp + 80002f8a: 0000 unimp + 80002f8c: 0000 unimp + 80002f8e: 0000 unimp + 80002f90: 0000 unimp + 80002f92: 0000 unimp + 80002f94: 0000 unimp + 80002f96: 0000 unimp + 80002f98: 0000 unimp + 80002f9a: 0000 unimp + 80002f9c: 0000 unimp + 80002f9e: 0000 unimp + 80002fa0: 0000 unimp + 80002fa2: 0000 unimp + 80002fa4: 0000 unimp + 80002fa6: 0000 unimp + 80002fa8: 0000 unimp + 80002faa: 0000 unimp + 80002fac: 0000 unimp + 80002fae: 0000 unimp + 80002fb0: 0000 unimp + 80002fb2: 0000 unimp + 80002fb4: 0000 unimp + 80002fb6: 0000 unimp + 80002fb8: 0000 unimp + 80002fba: 0000 unimp + 80002fbc: 0000 unimp + 80002fbe: 0000 unimp + 80002fc0: 0000 unimp + 80002fc2: 0000 unimp + 80002fc4: 0000 unimp + 80002fc6: 0000 unimp + 80002fc8: 0000 unimp + 80002fca: 0000 unimp + 80002fcc: 0000 unimp + 80002fce: 0000 unimp + 80002fd0: 0000 unimp + 80002fd2: 0000 unimp + 80002fd4: 0000 unimp + 80002fd6: 0000 unimp + 80002fd8: 0000 unimp + 80002fda: 0000 unimp + 80002fdc: 0000 unimp + 80002fde: 0000 unimp + 80002fe0: 0000 unimp + 80002fe2: 0000 unimp + 80002fe4: 0000 unimp + 80002fe6: 0000 unimp + 80002fe8: 0000 unimp + 80002fea: 0000 unimp + 80002fec: 0000 unimp + 80002fee: 0000 unimp + 80002ff0: 0000 unimp + 80002ff2: 0000 unimp + 80002ff4: 0000 unimp + 80002ff6: 0000 unimp + 80002ff8: 0000 unimp + 80002ffa: 0000 unimp + 80002ffc: 0000 unimp + 80002ffe: 0000 unimp + +0000000080003000 : + 80003000: 00200193 li gp,2 + 80003004: 29a00593 li a1,666 + +0000000080003008 : + 80003008: 7f70106f j 80004ffe + 8000300c: 00000013 nop + +0000000080003010 : + 80003010: 3210 fld fa2,32(a2) + 80003012: 7654 ld a3,168(a2) + 80003014: ba98 fsd fa4,48(a3) + 80003016: fedc sd a5,184(a3) + 80003018: 3210 fld fa2,32(a2) + 8000301a: 7654 ld a3,168(a2) + 8000301c: ba98 fsd fa4,48(a3) + 8000301e: fedc sd a5,184(a3) + 80003020: 00000013 nop + 80003024: 00000013 nop + 80003028: 00000013 nop + 8000302c: 00000013 nop + 80003030: 00000013 nop + 80003034: 00000013 nop + 80003038: 00000013 nop + 8000303c: 00000013 nop + 80003040: 00000013 nop + 80003044: 00000013 nop + 80003048: 00000013 nop + 8000304c: 00000013 nop + 80003050: 00000013 nop + 80003054: 00000013 nop + 80003058: 00000013 nop + 8000305c: 00000013 nop + 80003060: 00000013 nop + 80003064: 00000013 nop + 80003068: 00000013 nop + 8000306c: 00000013 nop + 80003070: 00000013 nop + 80003074: 00000013 nop + 80003078: 00000013 nop + 8000307c: 00000013 nop + 80003080: 00000013 nop + 80003084: 00000013 nop + 80003088: 00000013 nop + 8000308c: 00000013 nop + 80003090: 00000013 nop + 80003094: 00000013 nop + 80003098: 00000013 nop + 8000309c: 00000013 nop + 800030a0: 00000013 nop + 800030a4: 00000013 nop + 800030a8: 00000013 nop + 800030ac: 00000013 nop + 800030b0: 00000013 nop + 800030b4: 00000013 nop + 800030b8: 00000013 nop + 800030bc: 00000013 nop + 800030c0: 00000013 nop + 800030c4: 00000013 nop + 800030c8: 00000013 nop + 800030cc: 00000013 nop + 800030d0: 00000013 nop + 800030d4: 00000013 nop + 800030d8: 00000013 nop + 800030dc: 00000013 nop + 800030e0: 00000013 nop + 800030e4: 00000013 nop + 800030e8: 00000013 nop + 800030ec: 00000013 nop + 800030f0: 00000013 nop + 800030f4: 00000013 nop + 800030f8: 00000013 nop + 800030fc: 00000013 nop + 80003100: 00000013 nop + 80003104: 00000013 nop + 80003108: 00000013 nop + 8000310c: 00000013 nop + 80003110: 00000013 nop + 80003114: 00000013 nop + 80003118: 00000013 nop + 8000311c: 00000013 nop + 80003120: 00000013 nop + 80003124: 00000013 nop + 80003128: 00000013 nop + 8000312c: 00000013 nop + 80003130: 00000013 nop + 80003134: 00000013 nop + 80003138: 00000013 nop + 8000313c: 00000013 nop + 80003140: 00000013 nop + 80003144: 00000013 nop + 80003148: 00000013 nop + 8000314c: 00000013 nop + 80003150: 00000013 nop + 80003154: 00000013 nop + 80003158: 00000013 nop + 8000315c: 00000013 nop + 80003160: 00000013 nop + 80003164: 00000013 nop + 80003168: 00000013 nop + 8000316c: 00000013 nop + 80003170: 00000013 nop + 80003174: 00000013 nop + 80003178: 00000013 nop + 8000317c: 00000013 nop + 80003180: 00000013 nop + 80003184: 00000013 nop + 80003188: 00000013 nop + 8000318c: 00000013 nop + 80003190: 00000013 nop + 80003194: 00000013 nop + 80003198: 00000013 nop + 8000319c: 00000013 nop + 800031a0: 00000013 nop + 800031a4: 00000013 nop + 800031a8: 00000013 nop + 800031ac: 00000013 nop + 800031b0: 00000013 nop + 800031b4: 00000013 nop + 800031b8: 00000013 nop + 800031bc: 00000013 nop + 800031c0: 00000013 nop + 800031c4: 00000013 nop + 800031c8: 00000013 nop + 800031cc: 00000013 nop + 800031d0: 00000013 nop + 800031d4: 00000013 nop + 800031d8: 00000013 nop + 800031dc: 00000013 nop + 800031e0: 00000013 nop + 800031e4: 00000013 nop + 800031e8: 00000013 nop + 800031ec: 00000013 nop + 800031f0: 00000013 nop + 800031f4: 00000013 nop + 800031f8: 00000013 nop + 800031fc: 00000013 nop + 80003200: 00000013 nop + 80003204: 00000013 nop + 80003208: 00000013 nop + 8000320c: 00000013 nop + 80003210: 00000013 nop + 80003214: 00000013 nop + 80003218: 00000013 nop + 8000321c: 00000013 nop + 80003220: 00000013 nop + 80003224: 00000013 nop + 80003228: 00000013 nop + 8000322c: 00000013 nop + 80003230: 00000013 nop + 80003234: 00000013 nop + 80003238: 00000013 nop + 8000323c: 00000013 nop + 80003240: 00000013 nop + 80003244: 00000013 nop + 80003248: 00000013 nop + 8000324c: 00000013 nop + 80003250: 00000013 nop + 80003254: 00000013 nop + 80003258: 00000013 nop + 8000325c: 00000013 nop + 80003260: 00000013 nop + 80003264: 00000013 nop + 80003268: 00000013 nop + 8000326c: 00000013 nop + 80003270: 00000013 nop + 80003274: 00000013 nop + 80003278: 00000013 nop + 8000327c: 00000013 nop + 80003280: 00000013 nop + 80003284: 00000013 nop + 80003288: 00000013 nop + 8000328c: 00000013 nop + 80003290: 00000013 nop + 80003294: 00000013 nop + 80003298: 00000013 nop + 8000329c: 00000013 nop + 800032a0: 00000013 nop + 800032a4: 00000013 nop + 800032a8: 00000013 nop + 800032ac: 00000013 nop + 800032b0: 00000013 nop + 800032b4: 00000013 nop + 800032b8: 00000013 nop + 800032bc: 00000013 nop + 800032c0: 00000013 nop + 800032c4: 00000013 nop + 800032c8: 00000013 nop + 800032cc: 00000013 nop + 800032d0: 00000013 nop + 800032d4: 00000013 nop + 800032d8: 00000013 nop + 800032dc: 00000013 nop + 800032e0: 00000013 nop + 800032e4: 00000013 nop + 800032e8: 00000013 nop + 800032ec: 00000013 nop + 800032f0: 00000013 nop + 800032f4: 00000013 nop + 800032f8: 00000013 nop + 800032fc: 00000013 nop + 80003300: 00000013 nop + 80003304: 00000013 nop + 80003308: 00000013 nop + 8000330c: 00000013 nop + 80003310: 00000013 nop + 80003314: 00000013 nop + 80003318: 00000013 nop + 8000331c: 00000013 nop + 80003320: 00000013 nop + 80003324: 00000013 nop + 80003328: 00000013 nop + 8000332c: 00000013 nop + 80003330: 00000013 nop + 80003334: 00000013 nop + 80003338: 00000013 nop + 8000333c: 00000013 nop + 80003340: 00000013 nop + 80003344: 00000013 nop + 80003348: 00000013 nop + 8000334c: 00000013 nop + 80003350: 00000013 nop + 80003354: 00000013 nop + 80003358: 00000013 nop + 8000335c: 00000013 nop + 80003360: 00000013 nop + 80003364: 00000013 nop + 80003368: 00000013 nop + 8000336c: 00000013 nop + 80003370: 00000013 nop + 80003374: 00000013 nop + 80003378: 00000013 nop + 8000337c: 00000013 nop + 80003380: 00000013 nop + 80003384: 00000013 nop + 80003388: 00000013 nop + 8000338c: 00000013 nop + 80003390: 00000013 nop + 80003394: 00000013 nop + 80003398: 00000013 nop + 8000339c: 00000013 nop + 800033a0: 00000013 nop + 800033a4: 00000013 nop + 800033a8: 00000013 nop + 800033ac: 00000013 nop + 800033b0: 00000013 nop + 800033b4: 00000013 nop + 800033b8: 00000013 nop + 800033bc: 00000013 nop + 800033c0: 00000013 nop + 800033c4: 00000013 nop + 800033c8: 00000013 nop + 800033cc: 00000013 nop + 800033d0: 00000013 nop + 800033d4: 00000013 nop + 800033d8: 00000013 nop + 800033dc: 00000013 nop + 800033e0: 00000013 nop + 800033e4: 00000013 nop + 800033e8: 00000013 nop + 800033ec: 00000013 nop + 800033f0: 00000013 nop + 800033f4: 00000013 nop + 800033f8: 00000013 nop + 800033fc: 00000013 nop + 80003400: 00000013 nop + 80003404: 00000013 nop + 80003408: 00000013 nop + 8000340c: 00000013 nop + 80003410: 00000013 nop + 80003414: 00000013 nop + 80003418: 00000013 nop + 8000341c: 00000013 nop + 80003420: 00000013 nop + 80003424: 00000013 nop + 80003428: 00000013 nop + 8000342c: 00000013 nop + 80003430: 00000013 nop + 80003434: 00000013 nop + 80003438: 00000013 nop + 8000343c: 00000013 nop + 80003440: 00000013 nop + 80003444: 00000013 nop + 80003448: 00000013 nop + 8000344c: 00000013 nop + 80003450: 00000013 nop + 80003454: 00000013 nop + 80003458: 00000013 nop + 8000345c: 00000013 nop + 80003460: 00000013 nop + 80003464: 00000013 nop + 80003468: 00000013 nop + 8000346c: 00000013 nop + 80003470: 00000013 nop + 80003474: 00000013 nop + 80003478: 00000013 nop + 8000347c: 00000013 nop + 80003480: 00000013 nop + 80003484: 00000013 nop + 80003488: 00000013 nop + 8000348c: 00000013 nop + 80003490: 00000013 nop + 80003494: 00000013 nop + 80003498: 00000013 nop + 8000349c: 00000013 nop + 800034a0: 00000013 nop + 800034a4: 00000013 nop + 800034a8: 00000013 nop + 800034ac: 00000013 nop + 800034b0: 00000013 nop + 800034b4: 00000013 nop + 800034b8: 00000013 nop + 800034bc: 00000013 nop + 800034c0: 00000013 nop + 800034c4: 00000013 nop + 800034c8: 00000013 nop + 800034cc: 00000013 nop + 800034d0: 00000013 nop + 800034d4: 00000013 nop + 800034d8: 00000013 nop + 800034dc: 00000013 nop + 800034e0: 00000013 nop + 800034e4: 00000013 nop + 800034e8: 00000013 nop + 800034ec: 00000013 nop + 800034f0: 00000013 nop + 800034f4: 00000013 nop + 800034f8: 00000013 nop + 800034fc: 00000013 nop + 80003500: 00000013 nop + 80003504: 00000013 nop + 80003508: 00000013 nop + 8000350c: 00000013 nop + 80003510: 00000013 nop + 80003514: 00000013 nop + 80003518: 00000013 nop + 8000351c: 00000013 nop + 80003520: 00000013 nop + 80003524: 00000013 nop + 80003528: 00000013 nop + 8000352c: 00000013 nop + 80003530: 00000013 nop + 80003534: 00000013 nop + 80003538: 00000013 nop + 8000353c: 00000013 nop + 80003540: 00000013 nop + 80003544: 00000013 nop + 80003548: 00000013 nop + 8000354c: 00000013 nop + 80003550: 00000013 nop + 80003554: 00000013 nop + 80003558: 00000013 nop + 8000355c: 00000013 nop + 80003560: 00000013 nop + 80003564: 00000013 nop + 80003568: 00000013 nop + 8000356c: 00000013 nop + 80003570: 00000013 nop + 80003574: 00000013 nop + 80003578: 00000013 nop + 8000357c: 00000013 nop + 80003580: 00000013 nop + 80003584: 00000013 nop + 80003588: 00000013 nop + 8000358c: 00000013 nop + 80003590: 00000013 nop + 80003594: 00000013 nop + 80003598: 00000013 nop + 8000359c: 00000013 nop + 800035a0: 00000013 nop + 800035a4: 00000013 nop + 800035a8: 00000013 nop + 800035ac: 00000013 nop + 800035b0: 00000013 nop + 800035b4: 00000013 nop + 800035b8: 00000013 nop + 800035bc: 00000013 nop + 800035c0: 00000013 nop + 800035c4: 00000013 nop + 800035c8: 00000013 nop + 800035cc: 00000013 nop + 800035d0: 00000013 nop + 800035d4: 00000013 nop + 800035d8: 00000013 nop + 800035dc: 00000013 nop + 800035e0: 00000013 nop + 800035e4: 00000013 nop + 800035e8: 00000013 nop + 800035ec: 00000013 nop + 800035f0: 00000013 nop + 800035f4: 00000013 nop + 800035f8: 00000013 nop + 800035fc: 00000013 nop + 80003600: 00000013 nop + 80003604: 00000013 nop + 80003608: 00000013 nop + 8000360c: 00000013 nop + 80003610: 00000013 nop + 80003614: 00000013 nop + 80003618: 00000013 nop + 8000361c: 00000013 nop + 80003620: 00000013 nop + 80003624: 00000013 nop + 80003628: 00000013 nop + 8000362c: 00000013 nop + 80003630: 00000013 nop + 80003634: 00000013 nop + 80003638: 00000013 nop + 8000363c: 00000013 nop + 80003640: 00000013 nop + 80003644: 00000013 nop + 80003648: 00000013 nop + 8000364c: 00000013 nop + 80003650: 00000013 nop + 80003654: 00000013 nop + 80003658: 00000013 nop + 8000365c: 00000013 nop + 80003660: 00000013 nop + 80003664: 00000013 nop + 80003668: 00000013 nop + 8000366c: 00000013 nop + 80003670: 00000013 nop + 80003674: 00000013 nop + 80003678: 00000013 nop + 8000367c: 00000013 nop + 80003680: 00000013 nop + 80003684: 00000013 nop + 80003688: 00000013 nop + 8000368c: 00000013 nop + 80003690: 00000013 nop + 80003694: 00000013 nop + 80003698: 00000013 nop + 8000369c: 00000013 nop + 800036a0: 00000013 nop + 800036a4: 00000013 nop + 800036a8: 00000013 nop + 800036ac: 00000013 nop + 800036b0: 00000013 nop + 800036b4: 00000013 nop + 800036b8: 00000013 nop + 800036bc: 00000013 nop + 800036c0: 00000013 nop + 800036c4: 00000013 nop + 800036c8: 00000013 nop + 800036cc: 00000013 nop + 800036d0: 00000013 nop + 800036d4: 00000013 nop + 800036d8: 00000013 nop + 800036dc: 00000013 nop + 800036e0: 00000013 nop + 800036e4: 00000013 nop + 800036e8: 00000013 nop + 800036ec: 00000013 nop + 800036f0: 00000013 nop + 800036f4: 00000013 nop + 800036f8: 00000013 nop + 800036fc: 00000013 nop + 80003700: 00000013 nop + 80003704: 00000013 nop + 80003708: 00000013 nop + 8000370c: 00000013 nop + 80003710: 00000013 nop + 80003714: 00000013 nop + 80003718: 00000013 nop + 8000371c: 00000013 nop + 80003720: 00000013 nop + 80003724: 00000013 nop + 80003728: 00000013 nop + 8000372c: 00000013 nop + 80003730: 00000013 nop + 80003734: 00000013 nop + 80003738: 00000013 nop + 8000373c: 00000013 nop + 80003740: 00000013 nop + 80003744: 00000013 nop + 80003748: 00000013 nop + 8000374c: 00000013 nop + 80003750: 00000013 nop + 80003754: 00000013 nop + 80003758: 00000013 nop + 8000375c: 00000013 nop + 80003760: 00000013 nop + 80003764: 00000013 nop + 80003768: 00000013 nop + 8000376c: 00000013 nop + 80003770: 00000013 nop + 80003774: 00000013 nop + 80003778: 00000013 nop + 8000377c: 00000013 nop + 80003780: 00000013 nop + 80003784: 00000013 nop + 80003788: 00000013 nop + 8000378c: 00000013 nop + 80003790: 00000013 nop + 80003794: 00000013 nop + 80003798: 00000013 nop + 8000379c: 00000013 nop + 800037a0: 00000013 nop + 800037a4: 00000013 nop + 800037a8: 00000013 nop + 800037ac: 00000013 nop + 800037b0: 00000013 nop + 800037b4: 00000013 nop + 800037b8: 00000013 nop + 800037bc: 00000013 nop + 800037c0: 00000013 nop + 800037c4: 00000013 nop + 800037c8: 00000013 nop + 800037cc: 00000013 nop + 800037d0: 00000013 nop + 800037d4: 00000013 nop + 800037d8: 00000013 nop + 800037dc: 00000013 nop + 800037e0: 00000013 nop + 800037e4: 00000013 nop + 800037e8: 00000013 nop + 800037ec: 00000013 nop + 800037f0: 00000013 nop + 800037f4: 00000013 nop + 800037f8: 00000013 nop + 800037fc: 00000013 nop + 80003800: 00000013 nop + 80003804: 00000013 nop + 80003808: 00000013 nop + 8000380c: 00000013 nop + 80003810: 00000013 nop + 80003814: 00000013 nop + 80003818: 00000013 nop + 8000381c: 00000013 nop + 80003820: 00000013 nop + 80003824: 00000013 nop + 80003828: 00000013 nop + 8000382c: 00000013 nop + 80003830: 00000013 nop + 80003834: 00000013 nop + 80003838: 00000013 nop + 8000383c: 00000013 nop + 80003840: 00000013 nop + 80003844: 00000013 nop + 80003848: 00000013 nop + 8000384c: 00000013 nop + 80003850: 00000013 nop + 80003854: 00000013 nop + 80003858: 00000013 nop + 8000385c: 00000013 nop + 80003860: 00000013 nop + 80003864: 00000013 nop + 80003868: 00000013 nop + 8000386c: 00000013 nop + 80003870: 00000013 nop + 80003874: 00000013 nop + 80003878: 00000013 nop + 8000387c: 00000013 nop + 80003880: 00000013 nop + 80003884: 00000013 nop + 80003888: 00000013 nop + 8000388c: 00000013 nop + 80003890: 00000013 nop + 80003894: 00000013 nop + 80003898: 00000013 nop + 8000389c: 00000013 nop + 800038a0: 00000013 nop + 800038a4: 00000013 nop + 800038a8: 00000013 nop + 800038ac: 00000013 nop + 800038b0: 00000013 nop + 800038b4: 00000013 nop + 800038b8: 00000013 nop + 800038bc: 00000013 nop + 800038c0: 00000013 nop + 800038c4: 00000013 nop + 800038c8: 00000013 nop + 800038cc: 00000013 nop + 800038d0: 00000013 nop + 800038d4: 00000013 nop + 800038d8: 00000013 nop + 800038dc: 00000013 nop + 800038e0: 00000013 nop + 800038e4: 00000013 nop + 800038e8: 00000013 nop + 800038ec: 00000013 nop + 800038f0: 00000013 nop + 800038f4: 00000013 nop + 800038f8: 00000013 nop + 800038fc: 00000013 nop + 80003900: 00000013 nop + 80003904: 00000013 nop + 80003908: 00000013 nop + 8000390c: 00000013 nop + 80003910: 00000013 nop + 80003914: 00000013 nop + 80003918: 00000013 nop + 8000391c: 00000013 nop + 80003920: 00000013 nop + 80003924: 00000013 nop + 80003928: 00000013 nop + 8000392c: 00000013 nop + 80003930: 00000013 nop + 80003934: 00000013 nop + 80003938: 00000013 nop + 8000393c: 00000013 nop + 80003940: 00000013 nop + 80003944: 00000013 nop + 80003948: 00000013 nop + 8000394c: 00000013 nop + 80003950: 00000013 nop + 80003954: 00000013 nop + 80003958: 00000013 nop + 8000395c: 00000013 nop + 80003960: 00000013 nop + 80003964: 00000013 nop + 80003968: 00000013 nop + 8000396c: 00000013 nop + 80003970: 00000013 nop + 80003974: 00000013 nop + 80003978: 00000013 nop + 8000397c: 00000013 nop + 80003980: 00000013 nop + 80003984: 00000013 nop + 80003988: 00000013 nop + 8000398c: 00000013 nop + 80003990: 00000013 nop + 80003994: 00000013 nop + 80003998: 00000013 nop + 8000399c: 00000013 nop + 800039a0: 00000013 nop + 800039a4: 00000013 nop + 800039a8: 00000013 nop + 800039ac: 00000013 nop + 800039b0: 00000013 nop + 800039b4: 00000013 nop + 800039b8: 00000013 nop + 800039bc: 00000013 nop + 800039c0: 00000013 nop + 800039c4: 00000013 nop + 800039c8: 00000013 nop + 800039cc: 00000013 nop + 800039d0: 00000013 nop + 800039d4: 00000013 nop + 800039d8: 00000013 nop + 800039dc: 00000013 nop + 800039e0: 00000013 nop + 800039e4: 00000013 nop + 800039e8: 00000013 nop + 800039ec: 00000013 nop + 800039f0: 00000013 nop + 800039f4: 00000013 nop + 800039f8: 00000013 nop + 800039fc: 00000013 nop + 80003a00: 00000013 nop + 80003a04: 00000013 nop + 80003a08: 00000013 nop + 80003a0c: 00000013 nop + 80003a10: 00000013 nop + 80003a14: 00000013 nop + 80003a18: 00000013 nop + 80003a1c: 00000013 nop + 80003a20: 00000013 nop + 80003a24: 00000013 nop + 80003a28: 00000013 nop + 80003a2c: 00000013 nop + 80003a30: 00000013 nop + 80003a34: 00000013 nop + 80003a38: 00000013 nop + 80003a3c: 00000013 nop + 80003a40: 00000013 nop + 80003a44: 00000013 nop + 80003a48: 00000013 nop + 80003a4c: 00000013 nop + 80003a50: 00000013 nop + 80003a54: 00000013 nop + 80003a58: 00000013 nop + 80003a5c: 00000013 nop + 80003a60: 00000013 nop + 80003a64: 00000013 nop + 80003a68: 00000013 nop + 80003a6c: 00000013 nop + 80003a70: 00000013 nop + 80003a74: 00000013 nop + 80003a78: 00000013 nop + 80003a7c: 00000013 nop + 80003a80: 00000013 nop + 80003a84: 00000013 nop + 80003a88: 00000013 nop + 80003a8c: 00000013 nop + 80003a90: 00000013 nop + 80003a94: 00000013 nop + 80003a98: 00000013 nop + 80003a9c: 00000013 nop + 80003aa0: 00000013 nop + 80003aa4: 00000013 nop + 80003aa8: 00000013 nop + 80003aac: 00000013 nop + 80003ab0: 00000013 nop + 80003ab4: 00000013 nop + 80003ab8: 00000013 nop + 80003abc: 00000013 nop + 80003ac0: 00000013 nop + 80003ac4: 00000013 nop + 80003ac8: 00000013 nop + 80003acc: 00000013 nop + 80003ad0: 00000013 nop + 80003ad4: 00000013 nop + 80003ad8: 00000013 nop + 80003adc: 00000013 nop + 80003ae0: 00000013 nop + 80003ae4: 00000013 nop + 80003ae8: 00000013 nop + 80003aec: 00000013 nop + 80003af0: 00000013 nop + 80003af4: 00000013 nop + 80003af8: 00000013 nop + 80003afc: 00000013 nop + 80003b00: 00000013 nop + 80003b04: 00000013 nop + 80003b08: 00000013 nop + 80003b0c: 00000013 nop + 80003b10: 00000013 nop + 80003b14: 00000013 nop + 80003b18: 00000013 nop + 80003b1c: 00000013 nop + 80003b20: 00000013 nop + 80003b24: 00000013 nop + 80003b28: 00000013 nop + 80003b2c: 00000013 nop + 80003b30: 00000013 nop + 80003b34: 00000013 nop + 80003b38: 00000013 nop + 80003b3c: 00000013 nop + 80003b40: 00000013 nop + 80003b44: 00000013 nop + 80003b48: 00000013 nop + 80003b4c: 00000013 nop + 80003b50: 00000013 nop + 80003b54: 00000013 nop + 80003b58: 00000013 nop + 80003b5c: 00000013 nop + 80003b60: 00000013 nop + 80003b64: 00000013 nop + 80003b68: 00000013 nop + 80003b6c: 00000013 nop + 80003b70: 00000013 nop + 80003b74: 00000013 nop + 80003b78: 00000013 nop + 80003b7c: 00000013 nop + 80003b80: 00000013 nop + 80003b84: 00000013 nop + 80003b88: 00000013 nop + 80003b8c: 00000013 nop + 80003b90: 00000013 nop + 80003b94: 00000013 nop + 80003b98: 00000013 nop + 80003b9c: 00000013 nop + 80003ba0: 00000013 nop + 80003ba4: 00000013 nop + 80003ba8: 00000013 nop + 80003bac: 00000013 nop + 80003bb0: 00000013 nop + 80003bb4: 00000013 nop + 80003bb8: 00000013 nop + 80003bbc: 00000013 nop + 80003bc0: 00000013 nop + 80003bc4: 00000013 nop + 80003bc8: 00000013 nop + 80003bcc: 00000013 nop + 80003bd0: 00000013 nop + 80003bd4: 00000013 nop + 80003bd8: 00000013 nop + 80003bdc: 00000013 nop + 80003be0: 00000013 nop + 80003be4: 00000013 nop + 80003be8: 00000013 nop + 80003bec: 00000013 nop + 80003bf0: 00000013 nop + 80003bf4: 00000013 nop + 80003bf8: 00000013 nop + 80003bfc: 00000013 nop + 80003c00: 00000013 nop + 80003c04: 00000013 nop + 80003c08: 00000013 nop + 80003c0c: 00000013 nop + 80003c10: 00000013 nop + 80003c14: 00000013 nop + 80003c18: 00000013 nop + 80003c1c: 00000013 nop + 80003c20: 00000013 nop + 80003c24: 00000013 nop + 80003c28: 00000013 nop + 80003c2c: 00000013 nop + 80003c30: 00000013 nop + 80003c34: 00000013 nop + 80003c38: 00000013 nop + 80003c3c: 00000013 nop + 80003c40: 00000013 nop + 80003c44: 00000013 nop + 80003c48: 00000013 nop + 80003c4c: 00000013 nop + 80003c50: 00000013 nop + 80003c54: 00000013 nop + 80003c58: 00000013 nop + 80003c5c: 00000013 nop + 80003c60: 00000013 nop + 80003c64: 00000013 nop + 80003c68: 00000013 nop + 80003c6c: 00000013 nop + 80003c70: 00000013 nop + 80003c74: 00000013 nop + 80003c78: 00000013 nop + 80003c7c: 00000013 nop + 80003c80: 00000013 nop + 80003c84: 00000013 nop + 80003c88: 00000013 nop + 80003c8c: 00000013 nop + 80003c90: 00000013 nop + 80003c94: 00000013 nop + 80003c98: 00000013 nop + 80003c9c: 00000013 nop + 80003ca0: 00000013 nop + 80003ca4: 00000013 nop + 80003ca8: 00000013 nop + 80003cac: 00000013 nop + 80003cb0: 00000013 nop + 80003cb4: 00000013 nop + 80003cb8: 00000013 nop + 80003cbc: 00000013 nop + 80003cc0: 00000013 nop + 80003cc4: 00000013 nop + 80003cc8: 00000013 nop + 80003ccc: 00000013 nop + 80003cd0: 00000013 nop + 80003cd4: 00000013 nop + 80003cd8: 00000013 nop + 80003cdc: 00000013 nop + 80003ce0: 00000013 nop + 80003ce4: 00000013 nop + 80003ce8: 00000013 nop + 80003cec: 00000013 nop + 80003cf0: 00000013 nop + 80003cf4: 00000013 nop + 80003cf8: 00000013 nop + 80003cfc: 00000013 nop + 80003d00: 00000013 nop + 80003d04: 00000013 nop + 80003d08: 00000013 nop + 80003d0c: 00000013 nop + 80003d10: 00000013 nop + 80003d14: 00000013 nop + 80003d18: 00000013 nop + 80003d1c: 00000013 nop + 80003d20: 00000013 nop + 80003d24: 00000013 nop + 80003d28: 00000013 nop + 80003d2c: 00000013 nop + 80003d30: 00000013 nop + 80003d34: 00000013 nop + 80003d38: 00000013 nop + 80003d3c: 00000013 nop + 80003d40: 00000013 nop + 80003d44: 00000013 nop + 80003d48: 00000013 nop + 80003d4c: 00000013 nop + 80003d50: 00000013 nop + 80003d54: 00000013 nop + 80003d58: 00000013 nop + 80003d5c: 00000013 nop + 80003d60: 00000013 nop + 80003d64: 00000013 nop + 80003d68: 00000013 nop + 80003d6c: 00000013 nop + 80003d70: 00000013 nop + 80003d74: 00000013 nop + 80003d78: 00000013 nop + 80003d7c: 00000013 nop + 80003d80: 00000013 nop + 80003d84: 00000013 nop + 80003d88: 00000013 nop + 80003d8c: 00000013 nop + 80003d90: 00000013 nop + 80003d94: 00000013 nop + 80003d98: 00000013 nop + 80003d9c: 00000013 nop + 80003da0: 00000013 nop + 80003da4: 00000013 nop + 80003da8: 00000013 nop + 80003dac: 00000013 nop + 80003db0: 00000013 nop + 80003db4: 00000013 nop + 80003db8: 00000013 nop + 80003dbc: 00000013 nop + 80003dc0: 00000013 nop + 80003dc4: 00000013 nop + 80003dc8: 00000013 nop + 80003dcc: 00000013 nop + 80003dd0: 00000013 nop + 80003dd4: 00000013 nop + 80003dd8: 00000013 nop + 80003ddc: 00000013 nop + 80003de0: 00000013 nop + 80003de4: 00000013 nop + 80003de8: 00000013 nop + 80003dec: 00000013 nop + 80003df0: 00000013 nop + 80003df4: 00000013 nop + 80003df8: 00000013 nop + 80003dfc: 00000013 nop + 80003e00: 00000013 nop + 80003e04: 00000013 nop + 80003e08: 00000013 nop + 80003e0c: 00000013 nop + 80003e10: 00000013 nop + 80003e14: 00000013 nop + 80003e18: 00000013 nop + 80003e1c: 00000013 nop + 80003e20: 00000013 nop + 80003e24: 00000013 nop + 80003e28: 00000013 nop + 80003e2c: 00000013 nop + 80003e30: 00000013 nop + 80003e34: 00000013 nop + 80003e38: 00000013 nop + 80003e3c: 00000013 nop + 80003e40: 00000013 nop + 80003e44: 00000013 nop + 80003e48: 00000013 nop + 80003e4c: 00000013 nop + 80003e50: 00000013 nop + 80003e54: 00000013 nop + 80003e58: 00000013 nop + 80003e5c: 00000013 nop + 80003e60: 00000013 nop + 80003e64: 00000013 nop + 80003e68: 00000013 nop + 80003e6c: 00000013 nop + 80003e70: 00000013 nop + 80003e74: 00000013 nop + 80003e78: 00000013 nop + 80003e7c: 00000013 nop + 80003e80: 00000013 nop + 80003e84: 00000013 nop + 80003e88: 00000013 nop + 80003e8c: 00000013 nop + 80003e90: 00000013 nop + 80003e94: 00000013 nop + 80003e98: 00000013 nop + 80003e9c: 00000013 nop + 80003ea0: 00000013 nop + 80003ea4: 00000013 nop + 80003ea8: 00000013 nop + 80003eac: 00000013 nop + 80003eb0: 00000013 nop + 80003eb4: 00000013 nop + 80003eb8: 00000013 nop + 80003ebc: 00000013 nop + 80003ec0: 00000013 nop + 80003ec4: 00000013 nop + 80003ec8: 00000013 nop + 80003ecc: 00000013 nop + 80003ed0: 00000013 nop + 80003ed4: 00000013 nop + 80003ed8: 00000013 nop + 80003edc: 00000013 nop + 80003ee0: 00000013 nop + 80003ee4: 00000013 nop + 80003ee8: 00000013 nop + 80003eec: 00000013 nop + 80003ef0: 00000013 nop + 80003ef4: 00000013 nop + 80003ef8: 00000013 nop + 80003efc: 00000013 nop + 80003f00: 00000013 nop + 80003f04: 00000013 nop + 80003f08: 00000013 nop + 80003f0c: 00000013 nop + 80003f10: 00000013 nop + 80003f14: 00000013 nop + 80003f18: 00000013 nop + 80003f1c: 00000013 nop + 80003f20: 00000013 nop + 80003f24: 00000013 nop + 80003f28: 00000013 nop + 80003f2c: 00000013 nop + 80003f30: 00000013 nop + 80003f34: 00000013 nop + 80003f38: 00000013 nop + 80003f3c: 00000013 nop + 80003f40: 00000013 nop + 80003f44: 00000013 nop + 80003f48: 00000013 nop + 80003f4c: 00000013 nop + 80003f50: 00000013 nop + 80003f54: 00000013 nop + 80003f58: 00000013 nop + 80003f5c: 00000013 nop + 80003f60: 00000013 nop + 80003f64: 00000013 nop + 80003f68: 00000013 nop + 80003f6c: 00000013 nop + 80003f70: 00000013 nop + 80003f74: 00000013 nop + 80003f78: 00000013 nop + 80003f7c: 00000013 nop + 80003f80: 00000013 nop + 80003f84: 00000013 nop + 80003f88: 00000013 nop + 80003f8c: 00000013 nop + 80003f90: 00000013 nop + 80003f94: 00000013 nop + 80003f98: 00000013 nop + 80003f9c: 00000013 nop + 80003fa0: 00000013 nop + 80003fa4: 00000013 nop + 80003fa8: 00000013 nop + 80003fac: 00000013 nop + 80003fb0: 00000013 nop + 80003fb4: 00000013 nop + 80003fb8: 00000013 nop + 80003fbc: 00000013 nop + 80003fc0: 00000013 nop + 80003fc4: 00000013 nop + 80003fc8: 00000013 nop + 80003fcc: 00000013 nop + 80003fd0: 00000013 nop + 80003fd4: 00000013 nop + 80003fd8: 00000013 nop + 80003fdc: 00000013 nop + 80003fe0: 00000013 nop + 80003fe4: 00000013 nop + 80003fe8: 00000013 nop + 80003fec: 00000013 nop + 80003ff0: 00000013 nop + 80003ff4: 00000013 nop + 80003ff8: 00000013 nop + 80003ffc: 00000013 nop + 80004000: 0000 unimp + 80004002: 0000 unimp + 80004004: 0000 unimp + 80004006: 0000 unimp + 80004008: 0000 unimp + 8000400a: 0000 unimp + 8000400c: 0000 unimp + 8000400e: 0000 unimp + 80004010: 0000 unimp + 80004012: 0000 unimp + 80004014: 0000 unimp + 80004016: 0000 unimp + 80004018: 0000 unimp + 8000401a: 0000 unimp + 8000401c: 0000 unimp + 8000401e: 0000 unimp + 80004020: 0000 unimp + 80004022: 0000 unimp + 80004024: 0000 unimp + 80004026: 0000 unimp + 80004028: 0000 unimp + 8000402a: 0000 unimp + 8000402c: 0000 unimp + 8000402e: 0000 unimp + 80004030: 0000 unimp + 80004032: 0000 unimp + 80004034: 0000 unimp + 80004036: 0000 unimp + 80004038: 0000 unimp + 8000403a: 0000 unimp + 8000403c: 0000 unimp + 8000403e: 0000 unimp + 80004040: 0000 unimp + 80004042: 0000 unimp + 80004044: 0000 unimp + 80004046: 0000 unimp + 80004048: 0000 unimp + 8000404a: 0000 unimp + 8000404c: 0000 unimp + 8000404e: 0000 unimp + 80004050: 0000 unimp + 80004052: 0000 unimp + 80004054: 0000 unimp + 80004056: 0000 unimp + 80004058: 0000 unimp + 8000405a: 0000 unimp + 8000405c: 0000 unimp + 8000405e: 0000 unimp + 80004060: 0000 unimp + 80004062: 0000 unimp + 80004064: 0000 unimp + 80004066: 0000 unimp + 80004068: 0000 unimp + 8000406a: 0000 unimp + 8000406c: 0000 unimp + 8000406e: 0000 unimp + 80004070: 0000 unimp + 80004072: 0000 unimp + 80004074: 0000 unimp + 80004076: 0000 unimp + 80004078: 0000 unimp + 8000407a: 0000 unimp + 8000407c: 0000 unimp + 8000407e: 0000 unimp + 80004080: 0000 unimp + 80004082: 0000 unimp + 80004084: 0000 unimp + 80004086: 0000 unimp + 80004088: 0000 unimp + 8000408a: 0000 unimp + 8000408c: 0000 unimp + 8000408e: 0000 unimp + 80004090: 0000 unimp + 80004092: 0000 unimp + 80004094: 0000 unimp + 80004096: 0000 unimp + 80004098: 0000 unimp + 8000409a: 0000 unimp + 8000409c: 0000 unimp + 8000409e: 0000 unimp + 800040a0: 0000 unimp + 800040a2: 0000 unimp + 800040a4: 0000 unimp + 800040a6: 0000 unimp + 800040a8: 0000 unimp + 800040aa: 0000 unimp + 800040ac: 0000 unimp + 800040ae: 0000 unimp + 800040b0: 0000 unimp + 800040b2: 0000 unimp + 800040b4: 0000 unimp + 800040b6: 0000 unimp + 800040b8: 0000 unimp + 800040ba: 0000 unimp + 800040bc: 0000 unimp + 800040be: 0000 unimp + 800040c0: 0000 unimp + 800040c2: 0000 unimp + 800040c4: 0000 unimp + 800040c6: 0000 unimp + 800040c8: 0000 unimp + 800040ca: 0000 unimp + 800040cc: 0000 unimp + 800040ce: 0000 unimp + 800040d0: 0000 unimp + 800040d2: 0000 unimp + 800040d4: 0000 unimp + 800040d6: 0000 unimp + 800040d8: 0000 unimp + 800040da: 0000 unimp + 800040dc: 0000 unimp + 800040de: 0000 unimp + 800040e0: 0000 unimp + 800040e2: 0000 unimp + 800040e4: 0000 unimp + 800040e6: 0000 unimp + 800040e8: 0000 unimp + 800040ea: 0000 unimp + 800040ec: 0000 unimp + 800040ee: 0000 unimp + 800040f0: 0000 unimp + 800040f2: 0000 unimp + 800040f4: 0000 unimp + 800040f6: 0000 unimp + 800040f8: 0000 unimp + 800040fa: 0000 unimp + 800040fc: 0000 unimp + 800040fe: 0000 unimp + 80004100: 0000 unimp + 80004102: 0000 unimp + 80004104: 0000 unimp + 80004106: 0000 unimp + 80004108: 0000 unimp + 8000410a: 0000 unimp + 8000410c: 0000 unimp + 8000410e: 0000 unimp + 80004110: 0000 unimp + 80004112: 0000 unimp + 80004114: 0000 unimp + 80004116: 0000 unimp + 80004118: 0000 unimp + 8000411a: 0000 unimp + 8000411c: 0000 unimp + 8000411e: 0000 unimp + 80004120: 0000 unimp + 80004122: 0000 unimp + 80004124: 0000 unimp + 80004126: 0000 unimp + 80004128: 0000 unimp + 8000412a: 0000 unimp + 8000412c: 0000 unimp + 8000412e: 0000 unimp + 80004130: 0000 unimp + 80004132: 0000 unimp + 80004134: 0000 unimp + 80004136: 0000 unimp + 80004138: 0000 unimp + 8000413a: 0000 unimp + 8000413c: 0000 unimp + 8000413e: 0000 unimp + 80004140: 0000 unimp + 80004142: 0000 unimp + 80004144: 0000 unimp + 80004146: 0000 unimp + 80004148: 0000 unimp + 8000414a: 0000 unimp + 8000414c: 0000 unimp + 8000414e: 0000 unimp + 80004150: 0000 unimp + 80004152: 0000 unimp + 80004154: 0000 unimp + 80004156: 0000 unimp + 80004158: 0000 unimp + 8000415a: 0000 unimp + 8000415c: 0000 unimp + 8000415e: 0000 unimp + 80004160: 0000 unimp + 80004162: 0000 unimp + 80004164: 0000 unimp + 80004166: 0000 unimp + 80004168: 0000 unimp + 8000416a: 0000 unimp + 8000416c: 0000 unimp + 8000416e: 0000 unimp + 80004170: 0000 unimp + 80004172: 0000 unimp + 80004174: 0000 unimp + 80004176: 0000 unimp + 80004178: 0000 unimp + 8000417a: 0000 unimp + 8000417c: 0000 unimp + 8000417e: 0000 unimp + 80004180: 0000 unimp + 80004182: 0000 unimp + 80004184: 0000 unimp + 80004186: 0000 unimp + 80004188: 0000 unimp + 8000418a: 0000 unimp + 8000418c: 0000 unimp + 8000418e: 0000 unimp + 80004190: 0000 unimp + 80004192: 0000 unimp + 80004194: 0000 unimp + 80004196: 0000 unimp + 80004198: 0000 unimp + 8000419a: 0000 unimp + 8000419c: 0000 unimp + 8000419e: 0000 unimp + 800041a0: 0000 unimp + 800041a2: 0000 unimp + 800041a4: 0000 unimp + 800041a6: 0000 unimp + 800041a8: 0000 unimp + 800041aa: 0000 unimp + 800041ac: 0000 unimp + 800041ae: 0000 unimp + 800041b0: 0000 unimp + 800041b2: 0000 unimp + 800041b4: 0000 unimp + 800041b6: 0000 unimp + 800041b8: 0000 unimp + 800041ba: 0000 unimp + 800041bc: 0000 unimp + 800041be: 0000 unimp + 800041c0: 0000 unimp + 800041c2: 0000 unimp + 800041c4: 0000 unimp + 800041c6: 0000 unimp + 800041c8: 0000 unimp + 800041ca: 0000 unimp + 800041cc: 0000 unimp + 800041ce: 0000 unimp + 800041d0: 0000 unimp + 800041d2: 0000 unimp + 800041d4: 0000 unimp + 800041d6: 0000 unimp + 800041d8: 0000 unimp + 800041da: 0000 unimp + 800041dc: 0000 unimp + 800041de: 0000 unimp + 800041e0: 0000 unimp + 800041e2: 0000 unimp + 800041e4: 0000 unimp + 800041e6: 0000 unimp + 800041e8: 0000 unimp + 800041ea: 0000 unimp + 800041ec: 0000 unimp + 800041ee: 0000 unimp + 800041f0: 0000 unimp + 800041f2: 0000 unimp + 800041f4: 0000 unimp + 800041f6: 0000 unimp + 800041f8: 0000 unimp + 800041fa: 0000 unimp + 800041fc: 0000 unimp + 800041fe: 0000 unimp + 80004200: 0000 unimp + 80004202: 0000 unimp + 80004204: 0000 unimp + 80004206: 0000 unimp + 80004208: 0000 unimp + 8000420a: 0000 unimp + 8000420c: 0000 unimp + 8000420e: 0000 unimp + 80004210: 0000 unimp + 80004212: 0000 unimp + 80004214: 0000 unimp + 80004216: 0000 unimp + 80004218: 0000 unimp + 8000421a: 0000 unimp + 8000421c: 0000 unimp + 8000421e: 0000 unimp + 80004220: 0000 unimp + 80004222: 0000 unimp + 80004224: 0000 unimp + 80004226: 0000 unimp + 80004228: 0000 unimp + 8000422a: 0000 unimp + 8000422c: 0000 unimp + 8000422e: 0000 unimp + 80004230: 0000 unimp + 80004232: 0000 unimp + 80004234: 0000 unimp + 80004236: 0000 unimp + 80004238: 0000 unimp + 8000423a: 0000 unimp + 8000423c: 0000 unimp + 8000423e: 0000 unimp + 80004240: 0000 unimp + 80004242: 0000 unimp + 80004244: 0000 unimp + 80004246: 0000 unimp + 80004248: 0000 unimp + 8000424a: 0000 unimp + 8000424c: 0000 unimp + 8000424e: 0000 unimp + 80004250: 0000 unimp + 80004252: 0000 unimp + 80004254: 0000 unimp + 80004256: 0000 unimp + 80004258: 0000 unimp + 8000425a: 0000 unimp + 8000425c: 0000 unimp + 8000425e: 0000 unimp + 80004260: 0000 unimp + 80004262: 0000 unimp + 80004264: 0000 unimp + 80004266: 0000 unimp + 80004268: 0000 unimp + 8000426a: 0000 unimp + 8000426c: 0000 unimp + 8000426e: 0000 unimp + 80004270: 0000 unimp + 80004272: 0000 unimp + 80004274: 0000 unimp + 80004276: 0000 unimp + 80004278: 0000 unimp + 8000427a: 0000 unimp + 8000427c: 0000 unimp + 8000427e: 0000 unimp + 80004280: 0000 unimp + 80004282: 0000 unimp + 80004284: 0000 unimp + 80004286: 0000 unimp + 80004288: 0000 unimp + 8000428a: 0000 unimp + 8000428c: 0000 unimp + 8000428e: 0000 unimp + 80004290: 0000 unimp + 80004292: 0000 unimp + 80004294: 0000 unimp + 80004296: 0000 unimp + 80004298: 0000 unimp + 8000429a: 0000 unimp + 8000429c: 0000 unimp + 8000429e: 0000 unimp + 800042a0: 0000 unimp + 800042a2: 0000 unimp + 800042a4: 0000 unimp + 800042a6: 0000 unimp + 800042a8: 0000 unimp + 800042aa: 0000 unimp + 800042ac: 0000 unimp + 800042ae: 0000 unimp + 800042b0: 0000 unimp + 800042b2: 0000 unimp + 800042b4: 0000 unimp + 800042b6: 0000 unimp + 800042b8: 0000 unimp + 800042ba: 0000 unimp + 800042bc: 0000 unimp + 800042be: 0000 unimp + 800042c0: 0000 unimp + 800042c2: 0000 unimp + 800042c4: 0000 unimp + 800042c6: 0000 unimp + 800042c8: 0000 unimp + 800042ca: 0000 unimp + 800042cc: 0000 unimp + 800042ce: 0000 unimp + 800042d0: 0000 unimp + 800042d2: 0000 unimp + 800042d4: 0000 unimp + 800042d6: 0000 unimp + 800042d8: 0000 unimp + 800042da: 0000 unimp + 800042dc: 0000 unimp + 800042de: 0000 unimp + 800042e0: 0000 unimp + 800042e2: 0000 unimp + 800042e4: 0000 unimp + 800042e6: 0000 unimp + 800042e8: 0000 unimp + 800042ea: 0000 unimp + 800042ec: 0000 unimp + 800042ee: 0000 unimp + 800042f0: 0000 unimp + 800042f2: 0000 unimp + 800042f4: 0000 unimp + 800042f6: 0000 unimp + 800042f8: 0000 unimp + 800042fa: 0000 unimp + 800042fc: 0000 unimp + 800042fe: 0000 unimp + 80004300: 0000 unimp + 80004302: 0000 unimp + 80004304: 0000 unimp + 80004306: 0000 unimp + 80004308: 0000 unimp + 8000430a: 0000 unimp + 8000430c: 0000 unimp + 8000430e: 0000 unimp + 80004310: 0000 unimp + 80004312: 0000 unimp + 80004314: 0000 unimp + 80004316: 0000 unimp + 80004318: 0000 unimp + 8000431a: 0000 unimp + 8000431c: 0000 unimp + 8000431e: 0000 unimp + 80004320: 0000 unimp + 80004322: 0000 unimp + 80004324: 0000 unimp + 80004326: 0000 unimp + 80004328: 0000 unimp + 8000432a: 0000 unimp + 8000432c: 0000 unimp + 8000432e: 0000 unimp + 80004330: 0000 unimp + 80004332: 0000 unimp + 80004334: 0000 unimp + 80004336: 0000 unimp + 80004338: 0000 unimp + 8000433a: 0000 unimp + 8000433c: 0000 unimp + 8000433e: 0000 unimp + 80004340: 0000 unimp + 80004342: 0000 unimp + 80004344: 0000 unimp + 80004346: 0000 unimp + 80004348: 0000 unimp + 8000434a: 0000 unimp + 8000434c: 0000 unimp + 8000434e: 0000 unimp + 80004350: 0000 unimp + 80004352: 0000 unimp + 80004354: 0000 unimp + 80004356: 0000 unimp + 80004358: 0000 unimp + 8000435a: 0000 unimp + 8000435c: 0000 unimp + 8000435e: 0000 unimp + 80004360: 0000 unimp + 80004362: 0000 unimp + 80004364: 0000 unimp + 80004366: 0000 unimp + 80004368: 0000 unimp + 8000436a: 0000 unimp + 8000436c: 0000 unimp + 8000436e: 0000 unimp + 80004370: 0000 unimp + 80004372: 0000 unimp + 80004374: 0000 unimp + 80004376: 0000 unimp + 80004378: 0000 unimp + 8000437a: 0000 unimp + 8000437c: 0000 unimp + 8000437e: 0000 unimp + 80004380: 0000 unimp + 80004382: 0000 unimp + 80004384: 0000 unimp + 80004386: 0000 unimp + 80004388: 0000 unimp + 8000438a: 0000 unimp + 8000438c: 0000 unimp + 8000438e: 0000 unimp + 80004390: 0000 unimp + 80004392: 0000 unimp + 80004394: 0000 unimp + 80004396: 0000 unimp + 80004398: 0000 unimp + 8000439a: 0000 unimp + 8000439c: 0000 unimp + 8000439e: 0000 unimp + 800043a0: 0000 unimp + 800043a2: 0000 unimp + 800043a4: 0000 unimp + 800043a6: 0000 unimp + 800043a8: 0000 unimp + 800043aa: 0000 unimp + 800043ac: 0000 unimp + 800043ae: 0000 unimp + 800043b0: 0000 unimp + 800043b2: 0000 unimp + 800043b4: 0000 unimp + 800043b6: 0000 unimp + 800043b8: 0000 unimp + 800043ba: 0000 unimp + 800043bc: 0000 unimp + 800043be: 0000 unimp + 800043c0: 0000 unimp + 800043c2: 0000 unimp + 800043c4: 0000 unimp + 800043c6: 0000 unimp + 800043c8: 0000 unimp + 800043ca: 0000 unimp + 800043cc: 0000 unimp + 800043ce: 0000 unimp + 800043d0: 0000 unimp + 800043d2: 0000 unimp + 800043d4: 0000 unimp + 800043d6: 0000 unimp + 800043d8: 0000 unimp + 800043da: 0000 unimp + 800043dc: 0000 unimp + 800043de: 0000 unimp + 800043e0: 0000 unimp + 800043e2: 0000 unimp + 800043e4: 0000 unimp + 800043e6: 0000 unimp + 800043e8: 0000 unimp + 800043ea: 0000 unimp + 800043ec: 0000 unimp + 800043ee: 0000 unimp + 800043f0: 0000 unimp + 800043f2: 0000 unimp + 800043f4: 0000 unimp + 800043f6: 0000 unimp + 800043f8: 0000 unimp + 800043fa: 0000 unimp + 800043fc: 0000 unimp + 800043fe: 0000 unimp + 80004400: 0000 unimp + 80004402: 0000 unimp + 80004404: 0000 unimp + 80004406: 0000 unimp + 80004408: 0000 unimp + 8000440a: 0000 unimp + 8000440c: 0000 unimp + 8000440e: 0000 unimp + 80004410: 0000 unimp + 80004412: 0000 unimp + 80004414: 0000 unimp + 80004416: 0000 unimp + 80004418: 0000 unimp + 8000441a: 0000 unimp + 8000441c: 0000 unimp + 8000441e: 0000 unimp + 80004420: 0000 unimp + 80004422: 0000 unimp + 80004424: 0000 unimp + 80004426: 0000 unimp + 80004428: 0000 unimp + 8000442a: 0000 unimp + 8000442c: 0000 unimp + 8000442e: 0000 unimp + 80004430: 0000 unimp + 80004432: 0000 unimp + 80004434: 0000 unimp + 80004436: 0000 unimp + 80004438: 0000 unimp + 8000443a: 0000 unimp + 8000443c: 0000 unimp + 8000443e: 0000 unimp + 80004440: 0000 unimp + 80004442: 0000 unimp + 80004444: 0000 unimp + 80004446: 0000 unimp + 80004448: 0000 unimp + 8000444a: 0000 unimp + 8000444c: 0000 unimp + 8000444e: 0000 unimp + 80004450: 0000 unimp + 80004452: 0000 unimp + 80004454: 0000 unimp + 80004456: 0000 unimp + 80004458: 0000 unimp + 8000445a: 0000 unimp + 8000445c: 0000 unimp + 8000445e: 0000 unimp + 80004460: 0000 unimp + 80004462: 0000 unimp + 80004464: 0000 unimp + 80004466: 0000 unimp + 80004468: 0000 unimp + 8000446a: 0000 unimp + 8000446c: 0000 unimp + 8000446e: 0000 unimp + 80004470: 0000 unimp + 80004472: 0000 unimp + 80004474: 0000 unimp + 80004476: 0000 unimp + 80004478: 0000 unimp + 8000447a: 0000 unimp + 8000447c: 0000 unimp + 8000447e: 0000 unimp + 80004480: 0000 unimp + 80004482: 0000 unimp + 80004484: 0000 unimp + 80004486: 0000 unimp + 80004488: 0000 unimp + 8000448a: 0000 unimp + 8000448c: 0000 unimp + 8000448e: 0000 unimp + 80004490: 0000 unimp + 80004492: 0000 unimp + 80004494: 0000 unimp + 80004496: 0000 unimp + 80004498: 0000 unimp + 8000449a: 0000 unimp + 8000449c: 0000 unimp + 8000449e: 0000 unimp + 800044a0: 0000 unimp + 800044a2: 0000 unimp + 800044a4: 0000 unimp + 800044a6: 0000 unimp + 800044a8: 0000 unimp + 800044aa: 0000 unimp + 800044ac: 0000 unimp + 800044ae: 0000 unimp + 800044b0: 0000 unimp + 800044b2: 0000 unimp + 800044b4: 0000 unimp + 800044b6: 0000 unimp + 800044b8: 0000 unimp + 800044ba: 0000 unimp + 800044bc: 0000 unimp + 800044be: 0000 unimp + 800044c0: 0000 unimp + 800044c2: 0000 unimp + 800044c4: 0000 unimp + 800044c6: 0000 unimp + 800044c8: 0000 unimp + 800044ca: 0000 unimp + 800044cc: 0000 unimp + 800044ce: 0000 unimp + 800044d0: 0000 unimp + 800044d2: 0000 unimp + 800044d4: 0000 unimp + 800044d6: 0000 unimp + 800044d8: 0000 unimp + 800044da: 0000 unimp + 800044dc: 0000 unimp + 800044de: 0000 unimp + 800044e0: 0000 unimp + 800044e2: 0000 unimp + 800044e4: 0000 unimp + 800044e6: 0000 unimp + 800044e8: 0000 unimp + 800044ea: 0000 unimp + 800044ec: 0000 unimp + 800044ee: 0000 unimp + 800044f0: 0000 unimp + 800044f2: 0000 unimp + 800044f4: 0000 unimp + 800044f6: 0000 unimp + 800044f8: 0000 unimp + 800044fa: 0000 unimp + 800044fc: 0000 unimp + 800044fe: 0000 unimp + 80004500: 0000 unimp + 80004502: 0000 unimp + 80004504: 0000 unimp + 80004506: 0000 unimp + 80004508: 0000 unimp + 8000450a: 0000 unimp + 8000450c: 0000 unimp + 8000450e: 0000 unimp + 80004510: 0000 unimp + 80004512: 0000 unimp + 80004514: 0000 unimp + 80004516: 0000 unimp + 80004518: 0000 unimp + 8000451a: 0000 unimp + 8000451c: 0000 unimp + 8000451e: 0000 unimp + 80004520: 0000 unimp + 80004522: 0000 unimp + 80004524: 0000 unimp + 80004526: 0000 unimp + 80004528: 0000 unimp + 8000452a: 0000 unimp + 8000452c: 0000 unimp + 8000452e: 0000 unimp + 80004530: 0000 unimp + 80004532: 0000 unimp + 80004534: 0000 unimp + 80004536: 0000 unimp + 80004538: 0000 unimp + 8000453a: 0000 unimp + 8000453c: 0000 unimp + 8000453e: 0000 unimp + 80004540: 0000 unimp + 80004542: 0000 unimp + 80004544: 0000 unimp + 80004546: 0000 unimp + 80004548: 0000 unimp + 8000454a: 0000 unimp + 8000454c: 0000 unimp + 8000454e: 0000 unimp + 80004550: 0000 unimp + 80004552: 0000 unimp + 80004554: 0000 unimp + 80004556: 0000 unimp + 80004558: 0000 unimp + 8000455a: 0000 unimp + 8000455c: 0000 unimp + 8000455e: 0000 unimp + 80004560: 0000 unimp + 80004562: 0000 unimp + 80004564: 0000 unimp + 80004566: 0000 unimp + 80004568: 0000 unimp + 8000456a: 0000 unimp + 8000456c: 0000 unimp + 8000456e: 0000 unimp + 80004570: 0000 unimp + 80004572: 0000 unimp + 80004574: 0000 unimp + 80004576: 0000 unimp + 80004578: 0000 unimp + 8000457a: 0000 unimp + 8000457c: 0000 unimp + 8000457e: 0000 unimp + 80004580: 0000 unimp + 80004582: 0000 unimp + 80004584: 0000 unimp + 80004586: 0000 unimp + 80004588: 0000 unimp + 8000458a: 0000 unimp + 8000458c: 0000 unimp + 8000458e: 0000 unimp + 80004590: 0000 unimp + 80004592: 0000 unimp + 80004594: 0000 unimp + 80004596: 0000 unimp + 80004598: 0000 unimp + 8000459a: 0000 unimp + 8000459c: 0000 unimp + 8000459e: 0000 unimp + 800045a0: 0000 unimp + 800045a2: 0000 unimp + 800045a4: 0000 unimp + 800045a6: 0000 unimp + 800045a8: 0000 unimp + 800045aa: 0000 unimp + 800045ac: 0000 unimp + 800045ae: 0000 unimp + 800045b0: 0000 unimp + 800045b2: 0000 unimp + 800045b4: 0000 unimp + 800045b6: 0000 unimp + 800045b8: 0000 unimp + 800045ba: 0000 unimp + 800045bc: 0000 unimp + 800045be: 0000 unimp + 800045c0: 0000 unimp + 800045c2: 0000 unimp + 800045c4: 0000 unimp + 800045c6: 0000 unimp + 800045c8: 0000 unimp + 800045ca: 0000 unimp + 800045cc: 0000 unimp + 800045ce: 0000 unimp + 800045d0: 0000 unimp + 800045d2: 0000 unimp + 800045d4: 0000 unimp + 800045d6: 0000 unimp + 800045d8: 0000 unimp + 800045da: 0000 unimp + 800045dc: 0000 unimp + 800045de: 0000 unimp + 800045e0: 0000 unimp + 800045e2: 0000 unimp + 800045e4: 0000 unimp + 800045e6: 0000 unimp + 800045e8: 0000 unimp + 800045ea: 0000 unimp + 800045ec: 0000 unimp + 800045ee: 0000 unimp + 800045f0: 0000 unimp + 800045f2: 0000 unimp + 800045f4: 0000 unimp + 800045f6: 0000 unimp + 800045f8: 0000 unimp + 800045fa: 0000 unimp + 800045fc: 0000 unimp + 800045fe: 0000 unimp + 80004600: 0000 unimp + 80004602: 0000 unimp + 80004604: 0000 unimp + 80004606: 0000 unimp + 80004608: 0000 unimp + 8000460a: 0000 unimp + 8000460c: 0000 unimp + 8000460e: 0000 unimp + 80004610: 0000 unimp + 80004612: 0000 unimp + 80004614: 0000 unimp + 80004616: 0000 unimp + 80004618: 0000 unimp + 8000461a: 0000 unimp + 8000461c: 0000 unimp + 8000461e: 0000 unimp + 80004620: 0000 unimp + 80004622: 0000 unimp + 80004624: 0000 unimp + 80004626: 0000 unimp + 80004628: 0000 unimp + 8000462a: 0000 unimp + 8000462c: 0000 unimp + 8000462e: 0000 unimp + 80004630: 0000 unimp + 80004632: 0000 unimp + 80004634: 0000 unimp + 80004636: 0000 unimp + 80004638: 0000 unimp + 8000463a: 0000 unimp + 8000463c: 0000 unimp + 8000463e: 0000 unimp + 80004640: 0000 unimp + 80004642: 0000 unimp + 80004644: 0000 unimp + 80004646: 0000 unimp + 80004648: 0000 unimp + 8000464a: 0000 unimp + 8000464c: 0000 unimp + 8000464e: 0000 unimp + 80004650: 0000 unimp + 80004652: 0000 unimp + 80004654: 0000 unimp + 80004656: 0000 unimp + 80004658: 0000 unimp + 8000465a: 0000 unimp + 8000465c: 0000 unimp + 8000465e: 0000 unimp + 80004660: 0000 unimp + 80004662: 0000 unimp + 80004664: 0000 unimp + 80004666: 0000 unimp + 80004668: 0000 unimp + 8000466a: 0000 unimp + 8000466c: 0000 unimp + 8000466e: 0000 unimp + 80004670: 0000 unimp + 80004672: 0000 unimp + 80004674: 0000 unimp + 80004676: 0000 unimp + 80004678: 0000 unimp + 8000467a: 0000 unimp + 8000467c: 0000 unimp + 8000467e: 0000 unimp + 80004680: 0000 unimp + 80004682: 0000 unimp + 80004684: 0000 unimp + 80004686: 0000 unimp + 80004688: 0000 unimp + 8000468a: 0000 unimp + 8000468c: 0000 unimp + 8000468e: 0000 unimp + 80004690: 0000 unimp + 80004692: 0000 unimp + 80004694: 0000 unimp + 80004696: 0000 unimp + 80004698: 0000 unimp + 8000469a: 0000 unimp + 8000469c: 0000 unimp + 8000469e: 0000 unimp + 800046a0: 0000 unimp + 800046a2: 0000 unimp + 800046a4: 0000 unimp + 800046a6: 0000 unimp + 800046a8: 0000 unimp + 800046aa: 0000 unimp + 800046ac: 0000 unimp + 800046ae: 0000 unimp + 800046b0: 0000 unimp + 800046b2: 0000 unimp + 800046b4: 0000 unimp + 800046b6: 0000 unimp + 800046b8: 0000 unimp + 800046ba: 0000 unimp + 800046bc: 0000 unimp + 800046be: 0000 unimp + 800046c0: 0000 unimp + 800046c2: 0000 unimp + 800046c4: 0000 unimp + 800046c6: 0000 unimp + 800046c8: 0000 unimp + 800046ca: 0000 unimp + 800046cc: 0000 unimp + 800046ce: 0000 unimp + 800046d0: 0000 unimp + 800046d2: 0000 unimp + 800046d4: 0000 unimp + 800046d6: 0000 unimp + 800046d8: 0000 unimp + 800046da: 0000 unimp + 800046dc: 0000 unimp + 800046de: 0000 unimp + 800046e0: 0000 unimp + 800046e2: 0000 unimp + 800046e4: 0000 unimp + 800046e6: 0000 unimp + 800046e8: 0000 unimp + 800046ea: 0000 unimp + 800046ec: 0000 unimp + 800046ee: 0000 unimp + 800046f0: 0000 unimp + 800046f2: 0000 unimp + 800046f4: 0000 unimp + 800046f6: 0000 unimp + 800046f8: 0000 unimp + 800046fa: 0000 unimp + 800046fc: 0000 unimp + 800046fe: 0000 unimp + 80004700: 0000 unimp + 80004702: 0000 unimp + 80004704: 0000 unimp + 80004706: 0000 unimp + 80004708: 0000 unimp + 8000470a: 0000 unimp + 8000470c: 0000 unimp + 8000470e: 0000 unimp + 80004710: 0000 unimp + 80004712: 0000 unimp + 80004714: 0000 unimp + 80004716: 0000 unimp + 80004718: 0000 unimp + 8000471a: 0000 unimp + 8000471c: 0000 unimp + 8000471e: 0000 unimp + 80004720: 0000 unimp + 80004722: 0000 unimp + 80004724: 0000 unimp + 80004726: 0000 unimp + 80004728: 0000 unimp + 8000472a: 0000 unimp + 8000472c: 0000 unimp + 8000472e: 0000 unimp + 80004730: 0000 unimp + 80004732: 0000 unimp + 80004734: 0000 unimp + 80004736: 0000 unimp + 80004738: 0000 unimp + 8000473a: 0000 unimp + 8000473c: 0000 unimp + 8000473e: 0000 unimp + 80004740: 0000 unimp + 80004742: 0000 unimp + 80004744: 0000 unimp + 80004746: 0000 unimp + 80004748: 0000 unimp + 8000474a: 0000 unimp + 8000474c: 0000 unimp + 8000474e: 0000 unimp + 80004750: 0000 unimp + 80004752: 0000 unimp + 80004754: 0000 unimp + 80004756: 0000 unimp + 80004758: 0000 unimp + 8000475a: 0000 unimp + 8000475c: 0000 unimp + 8000475e: 0000 unimp + 80004760: 0000 unimp + 80004762: 0000 unimp + 80004764: 0000 unimp + 80004766: 0000 unimp + 80004768: 0000 unimp + 8000476a: 0000 unimp + 8000476c: 0000 unimp + 8000476e: 0000 unimp + 80004770: 0000 unimp + 80004772: 0000 unimp + 80004774: 0000 unimp + 80004776: 0000 unimp + 80004778: 0000 unimp + 8000477a: 0000 unimp + 8000477c: 0000 unimp + 8000477e: 0000 unimp + 80004780: 0000 unimp + 80004782: 0000 unimp + 80004784: 0000 unimp + 80004786: 0000 unimp + 80004788: 0000 unimp + 8000478a: 0000 unimp + 8000478c: 0000 unimp + 8000478e: 0000 unimp + 80004790: 0000 unimp + 80004792: 0000 unimp + 80004794: 0000 unimp + 80004796: 0000 unimp + 80004798: 0000 unimp + 8000479a: 0000 unimp + 8000479c: 0000 unimp + 8000479e: 0000 unimp + 800047a0: 0000 unimp + 800047a2: 0000 unimp + 800047a4: 0000 unimp + 800047a6: 0000 unimp + 800047a8: 0000 unimp + 800047aa: 0000 unimp + 800047ac: 0000 unimp + 800047ae: 0000 unimp + 800047b0: 0000 unimp + 800047b2: 0000 unimp + 800047b4: 0000 unimp + 800047b6: 0000 unimp + 800047b8: 0000 unimp + 800047ba: 0000 unimp + 800047bc: 0000 unimp + 800047be: 0000 unimp + 800047c0: 0000 unimp + 800047c2: 0000 unimp + 800047c4: 0000 unimp + 800047c6: 0000 unimp + 800047c8: 0000 unimp + 800047ca: 0000 unimp + 800047cc: 0000 unimp + 800047ce: 0000 unimp + 800047d0: 0000 unimp + 800047d2: 0000 unimp + 800047d4: 0000 unimp + 800047d6: 0000 unimp + 800047d8: 0000 unimp + 800047da: 0000 unimp + 800047dc: 0000 unimp + 800047de: 0000 unimp + 800047e0: 0000 unimp + 800047e2: 0000 unimp + 800047e4: 0000 unimp + 800047e6: 0000 unimp + 800047e8: 0000 unimp + 800047ea: 0000 unimp + 800047ec: 0000 unimp + 800047ee: 0000 unimp + 800047f0: 0000 unimp + 800047f2: 0000 unimp + 800047f4: 0000 unimp + 800047f6: 0000 unimp + 800047f8: 0000 unimp + 800047fa: 0000 unimp + 800047fc: 0000 unimp + 800047fe: 0000 unimp + 80004800: 0000 unimp + 80004802: 0000 unimp + 80004804: 0000 unimp + 80004806: 0000 unimp + 80004808: 0000 unimp + 8000480a: 0000 unimp + 8000480c: 0000 unimp + 8000480e: 0000 unimp + 80004810: 0000 unimp + 80004812: 0000 unimp + 80004814: 0000 unimp + 80004816: 0000 unimp + 80004818: 0000 unimp + 8000481a: 0000 unimp + 8000481c: 0000 unimp + 8000481e: 0000 unimp + 80004820: 0000 unimp + 80004822: 0000 unimp + 80004824: 0000 unimp + 80004826: 0000 unimp + 80004828: 0000 unimp + 8000482a: 0000 unimp + 8000482c: 0000 unimp + 8000482e: 0000 unimp + 80004830: 0000 unimp + 80004832: 0000 unimp + 80004834: 0000 unimp + 80004836: 0000 unimp + 80004838: 0000 unimp + 8000483a: 0000 unimp + 8000483c: 0000 unimp + 8000483e: 0000 unimp + 80004840: 0000 unimp + 80004842: 0000 unimp + 80004844: 0000 unimp + 80004846: 0000 unimp + 80004848: 0000 unimp + 8000484a: 0000 unimp + 8000484c: 0000 unimp + 8000484e: 0000 unimp + 80004850: 0000 unimp + 80004852: 0000 unimp + 80004854: 0000 unimp + 80004856: 0000 unimp + 80004858: 0000 unimp + 8000485a: 0000 unimp + 8000485c: 0000 unimp + 8000485e: 0000 unimp + 80004860: 0000 unimp + 80004862: 0000 unimp + 80004864: 0000 unimp + 80004866: 0000 unimp + 80004868: 0000 unimp + 8000486a: 0000 unimp + 8000486c: 0000 unimp + 8000486e: 0000 unimp + 80004870: 0000 unimp + 80004872: 0000 unimp + 80004874: 0000 unimp + 80004876: 0000 unimp + 80004878: 0000 unimp + 8000487a: 0000 unimp + 8000487c: 0000 unimp + 8000487e: 0000 unimp + 80004880: 0000 unimp + 80004882: 0000 unimp + 80004884: 0000 unimp + 80004886: 0000 unimp + 80004888: 0000 unimp + 8000488a: 0000 unimp + 8000488c: 0000 unimp + 8000488e: 0000 unimp + 80004890: 0000 unimp + 80004892: 0000 unimp + 80004894: 0000 unimp + 80004896: 0000 unimp + 80004898: 0000 unimp + 8000489a: 0000 unimp + 8000489c: 0000 unimp + 8000489e: 0000 unimp + 800048a0: 0000 unimp + 800048a2: 0000 unimp + 800048a4: 0000 unimp + 800048a6: 0000 unimp + 800048a8: 0000 unimp + 800048aa: 0000 unimp + 800048ac: 0000 unimp + 800048ae: 0000 unimp + 800048b0: 0000 unimp + 800048b2: 0000 unimp + 800048b4: 0000 unimp + 800048b6: 0000 unimp + 800048b8: 0000 unimp + 800048ba: 0000 unimp + 800048bc: 0000 unimp + 800048be: 0000 unimp + 800048c0: 0000 unimp + 800048c2: 0000 unimp + 800048c4: 0000 unimp + 800048c6: 0000 unimp + 800048c8: 0000 unimp + 800048ca: 0000 unimp + 800048cc: 0000 unimp + 800048ce: 0000 unimp + 800048d0: 0000 unimp + 800048d2: 0000 unimp + 800048d4: 0000 unimp + 800048d6: 0000 unimp + 800048d8: 0000 unimp + 800048da: 0000 unimp + 800048dc: 0000 unimp + 800048de: 0000 unimp + 800048e0: 0000 unimp + 800048e2: 0000 unimp + 800048e4: 0000 unimp + 800048e6: 0000 unimp + 800048e8: 0000 unimp + 800048ea: 0000 unimp + 800048ec: 0000 unimp + 800048ee: 0000 unimp + 800048f0: 0000 unimp + 800048f2: 0000 unimp + 800048f4: 0000 unimp + 800048f6: 0000 unimp + 800048f8: 0000 unimp + 800048fa: 0000 unimp + 800048fc: 0000 unimp + 800048fe: 0000 unimp + 80004900: 0000 unimp + 80004902: 0000 unimp + 80004904: 0000 unimp + 80004906: 0000 unimp + 80004908: 0000 unimp + 8000490a: 0000 unimp + 8000490c: 0000 unimp + 8000490e: 0000 unimp + 80004910: 0000 unimp + 80004912: 0000 unimp + 80004914: 0000 unimp + 80004916: 0000 unimp + 80004918: 0000 unimp + 8000491a: 0000 unimp + 8000491c: 0000 unimp + 8000491e: 0000 unimp + 80004920: 0000 unimp + 80004922: 0000 unimp + 80004924: 0000 unimp + 80004926: 0000 unimp + 80004928: 0000 unimp + 8000492a: 0000 unimp + 8000492c: 0000 unimp + 8000492e: 0000 unimp + 80004930: 0000 unimp + 80004932: 0000 unimp + 80004934: 0000 unimp + 80004936: 0000 unimp + 80004938: 0000 unimp + 8000493a: 0000 unimp + 8000493c: 0000 unimp + 8000493e: 0000 unimp + 80004940: 0000 unimp + 80004942: 0000 unimp + 80004944: 0000 unimp + 80004946: 0000 unimp + 80004948: 0000 unimp + 8000494a: 0000 unimp + 8000494c: 0000 unimp + 8000494e: 0000 unimp + 80004950: 0000 unimp + 80004952: 0000 unimp + 80004954: 0000 unimp + 80004956: 0000 unimp + 80004958: 0000 unimp + 8000495a: 0000 unimp + 8000495c: 0000 unimp + 8000495e: 0000 unimp + 80004960: 0000 unimp + 80004962: 0000 unimp + 80004964: 0000 unimp + 80004966: 0000 unimp + 80004968: 0000 unimp + 8000496a: 0000 unimp + 8000496c: 0000 unimp + 8000496e: 0000 unimp + 80004970: 0000 unimp + 80004972: 0000 unimp + 80004974: 0000 unimp + 80004976: 0000 unimp + 80004978: 0000 unimp + 8000497a: 0000 unimp + 8000497c: 0000 unimp + 8000497e: 0000 unimp + 80004980: 0000 unimp + 80004982: 0000 unimp + 80004984: 0000 unimp + 80004986: 0000 unimp + 80004988: 0000 unimp + 8000498a: 0000 unimp + 8000498c: 0000 unimp + 8000498e: 0000 unimp + 80004990: 0000 unimp + 80004992: 0000 unimp + 80004994: 0000 unimp + 80004996: 0000 unimp + 80004998: 0000 unimp + 8000499a: 0000 unimp + 8000499c: 0000 unimp + 8000499e: 0000 unimp + 800049a0: 0000 unimp + 800049a2: 0000 unimp + 800049a4: 0000 unimp + 800049a6: 0000 unimp + 800049a8: 0000 unimp + 800049aa: 0000 unimp + 800049ac: 0000 unimp + 800049ae: 0000 unimp + 800049b0: 0000 unimp + 800049b2: 0000 unimp + 800049b4: 0000 unimp + 800049b6: 0000 unimp + 800049b8: 0000 unimp + 800049ba: 0000 unimp + 800049bc: 0000 unimp + 800049be: 0000 unimp + 800049c0: 0000 unimp + 800049c2: 0000 unimp + 800049c4: 0000 unimp + 800049c6: 0000 unimp + 800049c8: 0000 unimp + 800049ca: 0000 unimp + 800049cc: 0000 unimp + 800049ce: 0000 unimp + 800049d0: 0000 unimp + 800049d2: 0000 unimp + 800049d4: 0000 unimp + 800049d6: 0000 unimp + 800049d8: 0000 unimp + 800049da: 0000 unimp + 800049dc: 0000 unimp + 800049de: 0000 unimp + 800049e0: 0000 unimp + 800049e2: 0000 unimp + 800049e4: 0000 unimp + 800049e6: 0000 unimp + 800049e8: 0000 unimp + 800049ea: 0000 unimp + 800049ec: 0000 unimp + 800049ee: 0000 unimp + 800049f0: 0000 unimp + 800049f2: 0000 unimp + 800049f4: 0000 unimp + 800049f6: 0000 unimp + 800049f8: 0000 unimp + 800049fa: 0000 unimp + 800049fc: 0000 unimp + 800049fe: 0000 unimp + 80004a00: 0000 unimp + 80004a02: 0000 unimp + 80004a04: 0000 unimp + 80004a06: 0000 unimp + 80004a08: 0000 unimp + 80004a0a: 0000 unimp + 80004a0c: 0000 unimp + 80004a0e: 0000 unimp + 80004a10: 0000 unimp + 80004a12: 0000 unimp + 80004a14: 0000 unimp + 80004a16: 0000 unimp + 80004a18: 0000 unimp + 80004a1a: 0000 unimp + 80004a1c: 0000 unimp + 80004a1e: 0000 unimp + 80004a20: 0000 unimp + 80004a22: 0000 unimp + 80004a24: 0000 unimp + 80004a26: 0000 unimp + 80004a28: 0000 unimp + 80004a2a: 0000 unimp + 80004a2c: 0000 unimp + 80004a2e: 0000 unimp + 80004a30: 0000 unimp + 80004a32: 0000 unimp + 80004a34: 0000 unimp + 80004a36: 0000 unimp + 80004a38: 0000 unimp + 80004a3a: 0000 unimp + 80004a3c: 0000 unimp + 80004a3e: 0000 unimp + 80004a40: 0000 unimp + 80004a42: 0000 unimp + 80004a44: 0000 unimp + 80004a46: 0000 unimp + 80004a48: 0000 unimp + 80004a4a: 0000 unimp + 80004a4c: 0000 unimp + 80004a4e: 0000 unimp + 80004a50: 0000 unimp + 80004a52: 0000 unimp + 80004a54: 0000 unimp + 80004a56: 0000 unimp + 80004a58: 0000 unimp + 80004a5a: 0000 unimp + 80004a5c: 0000 unimp + 80004a5e: 0000 unimp + 80004a60: 0000 unimp + 80004a62: 0000 unimp + 80004a64: 0000 unimp + 80004a66: 0000 unimp + 80004a68: 0000 unimp + 80004a6a: 0000 unimp + 80004a6c: 0000 unimp + 80004a6e: 0000 unimp + 80004a70: 0000 unimp + 80004a72: 0000 unimp + 80004a74: 0000 unimp + 80004a76: 0000 unimp + 80004a78: 0000 unimp + 80004a7a: 0000 unimp + 80004a7c: 0000 unimp + 80004a7e: 0000 unimp + 80004a80: 0000 unimp + 80004a82: 0000 unimp + 80004a84: 0000 unimp + 80004a86: 0000 unimp + 80004a88: 0000 unimp + 80004a8a: 0000 unimp + 80004a8c: 0000 unimp + 80004a8e: 0000 unimp + 80004a90: 0000 unimp + 80004a92: 0000 unimp + 80004a94: 0000 unimp + 80004a96: 0000 unimp + 80004a98: 0000 unimp + 80004a9a: 0000 unimp + 80004a9c: 0000 unimp + 80004a9e: 0000 unimp + 80004aa0: 0000 unimp + 80004aa2: 0000 unimp + 80004aa4: 0000 unimp + 80004aa6: 0000 unimp + 80004aa8: 0000 unimp + 80004aaa: 0000 unimp + 80004aac: 0000 unimp + 80004aae: 0000 unimp + 80004ab0: 0000 unimp + 80004ab2: 0000 unimp + 80004ab4: 0000 unimp + 80004ab6: 0000 unimp + 80004ab8: 0000 unimp + 80004aba: 0000 unimp + 80004abc: 0000 unimp + 80004abe: 0000 unimp + 80004ac0: 0000 unimp + 80004ac2: 0000 unimp + 80004ac4: 0000 unimp + 80004ac6: 0000 unimp + 80004ac8: 0000 unimp + 80004aca: 0000 unimp + 80004acc: 0000 unimp + 80004ace: 0000 unimp + 80004ad0: 0000 unimp + 80004ad2: 0000 unimp + 80004ad4: 0000 unimp + 80004ad6: 0000 unimp + 80004ad8: 0000 unimp + 80004ada: 0000 unimp + 80004adc: 0000 unimp + 80004ade: 0000 unimp + 80004ae0: 0000 unimp + 80004ae2: 0000 unimp + 80004ae4: 0000 unimp + 80004ae6: 0000 unimp + 80004ae8: 0000 unimp + 80004aea: 0000 unimp + 80004aec: 0000 unimp + 80004aee: 0000 unimp + 80004af0: 0000 unimp + 80004af2: 0000 unimp + 80004af4: 0000 unimp + 80004af6: 0000 unimp + 80004af8: 0000 unimp + 80004afa: 0000 unimp + 80004afc: 0000 unimp + 80004afe: 0000 unimp + 80004b00: 0000 unimp + 80004b02: 0000 unimp + 80004b04: 0000 unimp + 80004b06: 0000 unimp + 80004b08: 0000 unimp + 80004b0a: 0000 unimp + 80004b0c: 0000 unimp + 80004b0e: 0000 unimp + 80004b10: 0000 unimp + 80004b12: 0000 unimp + 80004b14: 0000 unimp + 80004b16: 0000 unimp + 80004b18: 0000 unimp + 80004b1a: 0000 unimp + 80004b1c: 0000 unimp + 80004b1e: 0000 unimp + 80004b20: 0000 unimp + 80004b22: 0000 unimp + 80004b24: 0000 unimp + 80004b26: 0000 unimp + 80004b28: 0000 unimp + 80004b2a: 0000 unimp + 80004b2c: 0000 unimp + 80004b2e: 0000 unimp + 80004b30: 0000 unimp + 80004b32: 0000 unimp + 80004b34: 0000 unimp + 80004b36: 0000 unimp + 80004b38: 0000 unimp + 80004b3a: 0000 unimp + 80004b3c: 0000 unimp + 80004b3e: 0000 unimp + 80004b40: 0000 unimp + 80004b42: 0000 unimp + 80004b44: 0000 unimp + 80004b46: 0000 unimp + 80004b48: 0000 unimp + 80004b4a: 0000 unimp + 80004b4c: 0000 unimp + 80004b4e: 0000 unimp + 80004b50: 0000 unimp + 80004b52: 0000 unimp + 80004b54: 0000 unimp + 80004b56: 0000 unimp + 80004b58: 0000 unimp + 80004b5a: 0000 unimp + 80004b5c: 0000 unimp + 80004b5e: 0000 unimp + 80004b60: 0000 unimp + 80004b62: 0000 unimp + 80004b64: 0000 unimp + 80004b66: 0000 unimp + 80004b68: 0000 unimp + 80004b6a: 0000 unimp + 80004b6c: 0000 unimp + 80004b6e: 0000 unimp + 80004b70: 0000 unimp + 80004b72: 0000 unimp + 80004b74: 0000 unimp + 80004b76: 0000 unimp + 80004b78: 0000 unimp + 80004b7a: 0000 unimp + 80004b7c: 0000 unimp + 80004b7e: 0000 unimp + 80004b80: 0000 unimp + 80004b82: 0000 unimp + 80004b84: 0000 unimp + 80004b86: 0000 unimp + 80004b88: 0000 unimp + 80004b8a: 0000 unimp + 80004b8c: 0000 unimp + 80004b8e: 0000 unimp + 80004b90: 0000 unimp + 80004b92: 0000 unimp + 80004b94: 0000 unimp + 80004b96: 0000 unimp + 80004b98: 0000 unimp + 80004b9a: 0000 unimp + 80004b9c: 0000 unimp + 80004b9e: 0000 unimp + 80004ba0: 0000 unimp + 80004ba2: 0000 unimp + 80004ba4: 0000 unimp + 80004ba6: 0000 unimp + 80004ba8: 0000 unimp + 80004baa: 0000 unimp + 80004bac: 0000 unimp + 80004bae: 0000 unimp + 80004bb0: 0000 unimp + 80004bb2: 0000 unimp + 80004bb4: 0000 unimp + 80004bb6: 0000 unimp + 80004bb8: 0000 unimp + 80004bba: 0000 unimp + 80004bbc: 0000 unimp + 80004bbe: 0000 unimp + 80004bc0: 0000 unimp + 80004bc2: 0000 unimp + 80004bc4: 0000 unimp + 80004bc6: 0000 unimp + 80004bc8: 0000 unimp + 80004bca: 0000 unimp + 80004bcc: 0000 unimp + 80004bce: 0000 unimp + 80004bd0: 0000 unimp + 80004bd2: 0000 unimp + 80004bd4: 0000 unimp + 80004bd6: 0000 unimp + 80004bd8: 0000 unimp + 80004bda: 0000 unimp + 80004bdc: 0000 unimp + 80004bde: 0000 unimp + 80004be0: 0000 unimp + 80004be2: 0000 unimp + 80004be4: 0000 unimp + 80004be6: 0000 unimp + 80004be8: 0000 unimp + 80004bea: 0000 unimp + 80004bec: 0000 unimp + 80004bee: 0000 unimp + 80004bf0: 0000 unimp + 80004bf2: 0000 unimp + 80004bf4: 0000 unimp + 80004bf6: 0000 unimp + 80004bf8: 0000 unimp + 80004bfa: 0000 unimp + 80004bfc: 0000 unimp + 80004bfe: 0000 unimp + 80004c00: 0000 unimp + 80004c02: 0000 unimp + 80004c04: 0000 unimp + 80004c06: 0000 unimp + 80004c08: 0000 unimp + 80004c0a: 0000 unimp + 80004c0c: 0000 unimp + 80004c0e: 0000 unimp + 80004c10: 0000 unimp + 80004c12: 0000 unimp + 80004c14: 0000 unimp + 80004c16: 0000 unimp + 80004c18: 0000 unimp + 80004c1a: 0000 unimp + 80004c1c: 0000 unimp + 80004c1e: 0000 unimp + 80004c20: 0000 unimp + 80004c22: 0000 unimp + 80004c24: 0000 unimp + 80004c26: 0000 unimp + 80004c28: 0000 unimp + 80004c2a: 0000 unimp + 80004c2c: 0000 unimp + 80004c2e: 0000 unimp + 80004c30: 0000 unimp + 80004c32: 0000 unimp + 80004c34: 0000 unimp + 80004c36: 0000 unimp + 80004c38: 0000 unimp + 80004c3a: 0000 unimp + 80004c3c: 0000 unimp + 80004c3e: 0000 unimp + 80004c40: 0000 unimp + 80004c42: 0000 unimp + 80004c44: 0000 unimp + 80004c46: 0000 unimp + 80004c48: 0000 unimp + 80004c4a: 0000 unimp + 80004c4c: 0000 unimp + 80004c4e: 0000 unimp + 80004c50: 0000 unimp + 80004c52: 0000 unimp + 80004c54: 0000 unimp + 80004c56: 0000 unimp + 80004c58: 0000 unimp + 80004c5a: 0000 unimp + 80004c5c: 0000 unimp + 80004c5e: 0000 unimp + 80004c60: 0000 unimp + 80004c62: 0000 unimp + 80004c64: 0000 unimp + 80004c66: 0000 unimp + 80004c68: 0000 unimp + 80004c6a: 0000 unimp + 80004c6c: 0000 unimp + 80004c6e: 0000 unimp + 80004c70: 0000 unimp + 80004c72: 0000 unimp + 80004c74: 0000 unimp + 80004c76: 0000 unimp + 80004c78: 0000 unimp + 80004c7a: 0000 unimp + 80004c7c: 0000 unimp + 80004c7e: 0000 unimp + 80004c80: 0000 unimp + 80004c82: 0000 unimp + 80004c84: 0000 unimp + 80004c86: 0000 unimp + 80004c88: 0000 unimp + 80004c8a: 0000 unimp + 80004c8c: 0000 unimp + 80004c8e: 0000 unimp + 80004c90: 0000 unimp + 80004c92: 0000 unimp + 80004c94: 0000 unimp + 80004c96: 0000 unimp + 80004c98: 0000 unimp + 80004c9a: 0000 unimp + 80004c9c: 0000 unimp + 80004c9e: 0000 unimp + 80004ca0: 0000 unimp + 80004ca2: 0000 unimp + 80004ca4: 0000 unimp + 80004ca6: 0000 unimp + 80004ca8: 0000 unimp + 80004caa: 0000 unimp + 80004cac: 0000 unimp + 80004cae: 0000 unimp + 80004cb0: 0000 unimp + 80004cb2: 0000 unimp + 80004cb4: 0000 unimp + 80004cb6: 0000 unimp + 80004cb8: 0000 unimp + 80004cba: 0000 unimp + 80004cbc: 0000 unimp + 80004cbe: 0000 unimp + 80004cc0: 0000 unimp + 80004cc2: 0000 unimp + 80004cc4: 0000 unimp + 80004cc6: 0000 unimp + 80004cc8: 0000 unimp + 80004cca: 0000 unimp + 80004ccc: 0000 unimp + 80004cce: 0000 unimp + 80004cd0: 0000 unimp + 80004cd2: 0000 unimp + 80004cd4: 0000 unimp + 80004cd6: 0000 unimp + 80004cd8: 0000 unimp + 80004cda: 0000 unimp + 80004cdc: 0000 unimp + 80004cde: 0000 unimp + 80004ce0: 0000 unimp + 80004ce2: 0000 unimp + 80004ce4: 0000 unimp + 80004ce6: 0000 unimp + 80004ce8: 0000 unimp + 80004cea: 0000 unimp + 80004cec: 0000 unimp + 80004cee: 0000 unimp + 80004cf0: 0000 unimp + 80004cf2: 0000 unimp + 80004cf4: 0000 unimp + 80004cf6: 0000 unimp + 80004cf8: 0000 unimp + 80004cfa: 0000 unimp + 80004cfc: 0000 unimp + 80004cfe: 0000 unimp + 80004d00: 0000 unimp + 80004d02: 0000 unimp + 80004d04: 0000 unimp + 80004d06: 0000 unimp + 80004d08: 0000 unimp + 80004d0a: 0000 unimp + 80004d0c: 0000 unimp + 80004d0e: 0000 unimp + 80004d10: 0000 unimp + 80004d12: 0000 unimp + 80004d14: 0000 unimp + 80004d16: 0000 unimp + 80004d18: 0000 unimp + 80004d1a: 0000 unimp + 80004d1c: 0000 unimp + 80004d1e: 0000 unimp + 80004d20: 0000 unimp + 80004d22: 0000 unimp + 80004d24: 0000 unimp + 80004d26: 0000 unimp + 80004d28: 0000 unimp + 80004d2a: 0000 unimp + 80004d2c: 0000 unimp + 80004d2e: 0000 unimp + 80004d30: 0000 unimp + 80004d32: 0000 unimp + 80004d34: 0000 unimp + 80004d36: 0000 unimp + 80004d38: 0000 unimp + 80004d3a: 0000 unimp + 80004d3c: 0000 unimp + 80004d3e: 0000 unimp + 80004d40: 0000 unimp + 80004d42: 0000 unimp + 80004d44: 0000 unimp + 80004d46: 0000 unimp + 80004d48: 0000 unimp + 80004d4a: 0000 unimp + 80004d4c: 0000 unimp + 80004d4e: 0000 unimp + 80004d50: 0000 unimp + 80004d52: 0000 unimp + 80004d54: 0000 unimp + 80004d56: 0000 unimp + 80004d58: 0000 unimp + 80004d5a: 0000 unimp + 80004d5c: 0000 unimp + 80004d5e: 0000 unimp + 80004d60: 0000 unimp + 80004d62: 0000 unimp + 80004d64: 0000 unimp + 80004d66: 0000 unimp + 80004d68: 0000 unimp + 80004d6a: 0000 unimp + 80004d6c: 0000 unimp + 80004d6e: 0000 unimp + 80004d70: 0000 unimp + 80004d72: 0000 unimp + 80004d74: 0000 unimp + 80004d76: 0000 unimp + 80004d78: 0000 unimp + 80004d7a: 0000 unimp + 80004d7c: 0000 unimp + 80004d7e: 0000 unimp + 80004d80: 0000 unimp + 80004d82: 0000 unimp + 80004d84: 0000 unimp + 80004d86: 0000 unimp + 80004d88: 0000 unimp + 80004d8a: 0000 unimp + 80004d8c: 0000 unimp + 80004d8e: 0000 unimp + 80004d90: 0000 unimp + 80004d92: 0000 unimp + 80004d94: 0000 unimp + 80004d96: 0000 unimp + 80004d98: 0000 unimp + 80004d9a: 0000 unimp + 80004d9c: 0000 unimp + 80004d9e: 0000 unimp + 80004da0: 0000 unimp + 80004da2: 0000 unimp + 80004da4: 0000 unimp + 80004da6: 0000 unimp + 80004da8: 0000 unimp + 80004daa: 0000 unimp + 80004dac: 0000 unimp + 80004dae: 0000 unimp + 80004db0: 0000 unimp + 80004db2: 0000 unimp + 80004db4: 0000 unimp + 80004db6: 0000 unimp + 80004db8: 0000 unimp + 80004dba: 0000 unimp + 80004dbc: 0000 unimp + 80004dbe: 0000 unimp + 80004dc0: 0000 unimp + 80004dc2: 0000 unimp + 80004dc4: 0000 unimp + 80004dc6: 0000 unimp + 80004dc8: 0000 unimp + 80004dca: 0000 unimp + 80004dcc: 0000 unimp + 80004dce: 0000 unimp + 80004dd0: 0000 unimp + 80004dd2: 0000 unimp + 80004dd4: 0000 unimp + 80004dd6: 0000 unimp + 80004dd8: 0000 unimp + 80004dda: 0000 unimp + 80004ddc: 0000 unimp + 80004dde: 0000 unimp + 80004de0: 0000 unimp + 80004de2: 0000 unimp + 80004de4: 0000 unimp + 80004de6: 0000 unimp + 80004de8: 0000 unimp + 80004dea: 0000 unimp + 80004dec: 0000 unimp + 80004dee: 0000 unimp + 80004df0: 0000 unimp + 80004df2: 0000 unimp + 80004df4: 0000 unimp + 80004df6: 0000 unimp + 80004df8: 0000 unimp + 80004dfa: 0000 unimp + 80004dfc: 0000 unimp + 80004dfe: 0000 unimp + 80004e00: 0000 unimp + 80004e02: 0000 unimp + 80004e04: 0000 unimp + 80004e06: 0000 unimp + 80004e08: 0000 unimp + 80004e0a: 0000 unimp + 80004e0c: 0000 unimp + 80004e0e: 0000 unimp + 80004e10: 0000 unimp + 80004e12: 0000 unimp + 80004e14: 0000 unimp + 80004e16: 0000 unimp + 80004e18: 0000 unimp + 80004e1a: 0000 unimp + 80004e1c: 0000 unimp + 80004e1e: 0000 unimp + 80004e20: 0000 unimp + 80004e22: 0000 unimp + 80004e24: 0000 unimp + 80004e26: 0000 unimp + 80004e28: 0000 unimp + 80004e2a: 0000 unimp + 80004e2c: 0000 unimp + 80004e2e: 0000 unimp + 80004e30: 0000 unimp + 80004e32: 0000 unimp + 80004e34: 0000 unimp + 80004e36: 0000 unimp + 80004e38: 0000 unimp + 80004e3a: 0000 unimp + 80004e3c: 0000 unimp + 80004e3e: 0000 unimp + 80004e40: 0000 unimp + 80004e42: 0000 unimp + 80004e44: 0000 unimp + 80004e46: 0000 unimp + 80004e48: 0000 unimp + 80004e4a: 0000 unimp + 80004e4c: 0000 unimp + 80004e4e: 0000 unimp + 80004e50: 0000 unimp + 80004e52: 0000 unimp + 80004e54: 0000 unimp + 80004e56: 0000 unimp + 80004e58: 0000 unimp + 80004e5a: 0000 unimp + 80004e5c: 0000 unimp + 80004e5e: 0000 unimp + 80004e60: 0000 unimp + 80004e62: 0000 unimp + 80004e64: 0000 unimp + 80004e66: 0000 unimp + 80004e68: 0000 unimp + 80004e6a: 0000 unimp + 80004e6c: 0000 unimp + 80004e6e: 0000 unimp + 80004e70: 0000 unimp + 80004e72: 0000 unimp + 80004e74: 0000 unimp + 80004e76: 0000 unimp + 80004e78: 0000 unimp + 80004e7a: 0000 unimp + 80004e7c: 0000 unimp + 80004e7e: 0000 unimp + 80004e80: 0000 unimp + 80004e82: 0000 unimp + 80004e84: 0000 unimp + 80004e86: 0000 unimp + 80004e88: 0000 unimp + 80004e8a: 0000 unimp + 80004e8c: 0000 unimp + 80004e8e: 0000 unimp + 80004e90: 0000 unimp + 80004e92: 0000 unimp + 80004e94: 0000 unimp + 80004e96: 0000 unimp + 80004e98: 0000 unimp + 80004e9a: 0000 unimp + 80004e9c: 0000 unimp + 80004e9e: 0000 unimp + 80004ea0: 0000 unimp + 80004ea2: 0000 unimp + 80004ea4: 0000 unimp + 80004ea6: 0000 unimp + 80004ea8: 0000 unimp + 80004eaa: 0000 unimp + 80004eac: 0000 unimp + 80004eae: 0000 unimp + 80004eb0: 0000 unimp + 80004eb2: 0000 unimp + 80004eb4: 0000 unimp + 80004eb6: 0000 unimp + 80004eb8: 0000 unimp + 80004eba: 0000 unimp + 80004ebc: 0000 unimp + 80004ebe: 0000 unimp + 80004ec0: 0000 unimp + 80004ec2: 0000 unimp + 80004ec4: 0000 unimp + 80004ec6: 0000 unimp + 80004ec8: 0000 unimp + 80004eca: 0000 unimp + 80004ecc: 0000 unimp + 80004ece: 0000 unimp + 80004ed0: 0000 unimp + 80004ed2: 0000 unimp + 80004ed4: 0000 unimp + 80004ed6: 0000 unimp + 80004ed8: 0000 unimp + 80004eda: 0000 unimp + 80004edc: 0000 unimp + 80004ede: 0000 unimp + 80004ee0: 0000 unimp + 80004ee2: 0000 unimp + 80004ee4: 0000 unimp + 80004ee6: 0000 unimp + 80004ee8: 0000 unimp + 80004eea: 0000 unimp + 80004eec: 0000 unimp + 80004eee: 0000 unimp + 80004ef0: 0000 unimp + 80004ef2: 0000 unimp + 80004ef4: 0000 unimp + 80004ef6: 0000 unimp + 80004ef8: 0000 unimp + 80004efa: 0000 unimp + 80004efc: 0000 unimp + 80004efe: 0000 unimp + 80004f00: 0000 unimp + 80004f02: 0000 unimp + 80004f04: 0000 unimp + 80004f06: 0000 unimp + 80004f08: 0000 unimp + 80004f0a: 0000 unimp + 80004f0c: 0000 unimp + 80004f0e: 0000 unimp + 80004f10: 0000 unimp + 80004f12: 0000 unimp + 80004f14: 0000 unimp + 80004f16: 0000 unimp + 80004f18: 0000 unimp + 80004f1a: 0000 unimp + 80004f1c: 0000 unimp + 80004f1e: 0000 unimp + 80004f20: 0000 unimp + 80004f22: 0000 unimp + 80004f24: 0000 unimp + 80004f26: 0000 unimp + 80004f28: 0000 unimp + 80004f2a: 0000 unimp + 80004f2c: 0000 unimp + 80004f2e: 0000 unimp + 80004f30: 0000 unimp + 80004f32: 0000 unimp + 80004f34: 0000 unimp + 80004f36: 0000 unimp + 80004f38: 0000 unimp + 80004f3a: 0000 unimp + 80004f3c: 0000 unimp + 80004f3e: 0000 unimp + 80004f40: 0000 unimp + 80004f42: 0000 unimp + 80004f44: 0000 unimp + 80004f46: 0000 unimp + 80004f48: 0000 unimp + 80004f4a: 0000 unimp + 80004f4c: 0000 unimp + 80004f4e: 0000 unimp + 80004f50: 0000 unimp + 80004f52: 0000 unimp + 80004f54: 0000 unimp + 80004f56: 0000 unimp + 80004f58: 0000 unimp + 80004f5a: 0000 unimp + 80004f5c: 0000 unimp + 80004f5e: 0000 unimp + 80004f60: 0000 unimp + 80004f62: 0000 unimp + 80004f64: 0000 unimp + 80004f66: 0000 unimp + 80004f68: 0000 unimp + 80004f6a: 0000 unimp + 80004f6c: 0000 unimp + 80004f6e: 0000 unimp + 80004f70: 0000 unimp + 80004f72: 0000 unimp + 80004f74: 0000 unimp + 80004f76: 0000 unimp + 80004f78: 0000 unimp + 80004f7a: 0000 unimp + 80004f7c: 0000 unimp + 80004f7e: 0000 unimp + 80004f80: 0000 unimp + 80004f82: 0000 unimp + 80004f84: 0000 unimp + 80004f86: 0000 unimp + 80004f88: 0000 unimp + 80004f8a: 0000 unimp + 80004f8c: 0000 unimp + 80004f8e: 0000 unimp + 80004f90: 0000 unimp + 80004f92: 0000 unimp + 80004f94: 0000 unimp + 80004f96: 0000 unimp + 80004f98: 0000 unimp + 80004f9a: 0000 unimp + 80004f9c: 0000 unimp + 80004f9e: 0000 unimp + 80004fa0: 0000 unimp + 80004fa2: 0000 unimp + 80004fa4: 0000 unimp + 80004fa6: 0000 unimp + 80004fa8: 0000 unimp + 80004faa: 0000 unimp + 80004fac: 0000 unimp + 80004fae: 0000 unimp + 80004fb0: 0000 unimp + 80004fb2: 0000 unimp + 80004fb4: 0000 unimp + 80004fb6: 0000 unimp + 80004fb8: 0000 unimp + 80004fba: 0000 unimp + 80004fbc: 0000 unimp + 80004fbe: 0000 unimp + 80004fc0: 0000 unimp + 80004fc2: 0000 unimp + 80004fc4: 0000 unimp + 80004fc6: 0000 unimp + 80004fc8: 0000 unimp + 80004fca: 0000 unimp + 80004fcc: 0000 unimp + 80004fce: 0000 unimp + 80004fd0: 0000 unimp + 80004fd2: 0000 unimp + 80004fd4: 0000 unimp + 80004fd6: 0000 unimp + 80004fd8: 0000 unimp + 80004fda: 0000 unimp + 80004fdc: 0000 unimp + 80004fde: 0000 unimp + 80004fe0: 0000 unimp + 80004fe2: 0000 unimp + 80004fe4: 0000 unimp + 80004fe6: 0000 unimp + 80004fe8: 0000 unimp + 80004fea: 0000 unimp + 80004fec: 0000 unimp + 80004fee: 0000 unimp + 80004ff0: 0000 unimp + 80004ff2: 0000 unimp + 80004ff4: 0000 unimp + 80004ff6: 0000 unimp + 80004ff8: 0000 unimp + 80004ffa: 0000 unimp + 80004ffc: 0000 unimp + 80004ffe: 00158593 addi a1,a1,1 + 80005002: 29b00e93 li t4,667 + 80005006: 00200193 li gp,2 + 8000500a: 2dd59163 bne a1,t4,800052cc + 8000500e: 00001137 lui sp,0x1 + 80005012: 2341011b addiw sp,sp,564 + +0000000080005016 : + 80005016: 1fe8 addi a0,sp,1020 + 80005018: 00001eb7 lui t4,0x1 + 8000501c: 630e8e9b addiw t4,t4,1584 + 80005020: 00300193 li gp,3 + 80005024: 2bd51463 bne a0,t4,800052cc + +0000000080005028 : + 80005028: 617d addi sp,sp,496 + 8000502a: 0001 nop + 8000502c: 00001eb7 lui t4,0x1 + 80005030: 424e8e9b addiw t4,t4,1060 + 80005034: 00400193 li gp,4 + 80005038: 29d11a63 bne sp,t4,800052cc + +000000008000503c : + 8000503c: 7101 addi sp,sp,-512 + 8000503e: 0001 nop + 80005040: 00001eb7 lui t4,0x1 + 80005044: 224e8e9b addiw t4,t4,548 + 80005048: 00500193 li gp,5 + 8000504c: 29d11063 bne sp,t4,800052cc + 80005050: ffffe597 auipc a1,0xffffe + 80005054: fc058593 addi a1,a1,-64 # 80003010 + +0000000080005058 : + 80005058: 41c8 lw a0,4(a1) + 8000505a: 0505 addi a0,a0,1 + 8000505c: c1c8 sw a0,4(a1) + 8000505e: 41d0 lw a2,4(a1) + 80005060: fedcceb7 lui t4,0xfedcc + 80005064: a99e8e9b addiw t4,t4,-1383 + 80005068: 00600193 li gp,6 + 8000506c: 27d61063 bne a2,t4,800052cc + +0000000080005070 : + 80005070: 6188 ld a0,0(a1) + 80005072: 0505 addi a0,a0,1 + 80005074: e188 sd a0,0(a1) + 80005076: 6190 ld a2,0(a1) + 80005078: fff6eeb7 lui t4,0xfff6e + 8000507c: 5d5e8e9b addiw t4,t4,1493 + 80005080: 00ce9e93 slli t4,t4,0xc + 80005084: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff624cb> + 80005088: 00de9e93 slli t4,t4,0xd + 8000508c: 543e8e93 addi t4,t4,1347 + 80005090: 00ce9e93 slli t4,t4,0xc + 80005094: 211e8e93 addi t4,t4,529 + 80005098: 00700193 li gp,7 + 8000509c: 23d61863 bne a2,t4,800052cc + +00000000800050a0 : + 800050a0: 00106513 ori a0,zero,1 + 800050a4: 1541 addi a0,a0,-16 + 800050a6: 0001 nop + 800050a8: ff100e93 li t4,-15 + 800050ac: 00800193 li gp,8 + 800050b0: 21d51e63 bne a0,t4,800052cc + +00000000800050b4 : + 800050b4: 00106793 ori a5,zero,1 + 800050b8: 57c1 li a5,-16 + 800050ba: 0001 nop + 800050bc: ff000e93 li t4,-16 + 800050c0: 00900193 li gp,9 + 800050c4: 21d79463 bne a5,t4,800052cc + +00000000800050c8 : + 800050c8: 6188 ld a0,0(a1) + 800050ca: 357d addiw a0,a0,-1 + 800050cc: 76543eb7 lui t4,0x76543 + 800050d0: 210e8e9b addiw t4,t4,528 + 800050d4: 00a00193 li gp,10 + 800050d8: 1fd51a63 bne a0,t4,800052cc + +00000000800050dc : + 800050dc: 7405 lui s0,0xfffe1 + 800050de: 8431 srai s0,s0,0xc + 800050e0: fe100e93 li t4,-31 + 800050e4: 00b00193 li gp,11 + 800050e8: 1fd41263 bne s0,t4,800052cc + +00000000800050ec : + 800050ec: 7405 lui s0,0xfffe1 + 800050ee: 8031 srli s0,s0,0xc + 800050f0: 00100e9b addiw t4,zero,1 + 800050f4: 034e9e93 slli t4,t4,0x34 + 800050f8: fe1e8e93 addi t4,t4,-31 # 76542fe1 <_start-0x9abd01f> + 800050fc: 00c00193 li gp,12 + 80005100: 1dd41663 bne s0,t4,800052cc + +0000000080005104 : + 80005104: 5479 li s0,-2 + 80005106: 983d andi s0,s0,-17 + 80005108: fee00e93 li t4,-18 + 8000510c: 00e00193 li gp,14 + 80005110: 1bd41e63 bne s0,t4,800052cc + +0000000080005114 : + 80005114: 44d1 li s1,20 + 80005116: 4519 li a0,6 + 80005118: 8c89 sub s1,s1,a0 + 8000511a: 0001 nop + 8000511c: 00e00e93 li t4,14 + 80005120: 00f00193 li gp,15 + 80005124: 1bd49463 bne s1,t4,800052cc + +0000000080005128 : + 80005128: 44d1 li s1,20 + 8000512a: 4519 li a0,6 + 8000512c: 8ca9 xor s1,s1,a0 + 8000512e: 0001 nop + 80005130: 01200e93 li t4,18 + 80005134: 01000193 li gp,16 + 80005138: 19d49a63 bne s1,t4,800052cc + +000000008000513c : + 8000513c: 44d1 li s1,20 + 8000513e: 4519 li a0,6 + 80005140: 8cc9 or s1,s1,a0 + 80005142: 0001 nop + 80005144: 01600e93 li t4,22 + 80005148: 01100193 li gp,17 + 8000514c: 19d49063 bne s1,t4,800052cc + +0000000080005150 : + 80005150: 44d1 li s1,20 + 80005152: 4519 li a0,6 + 80005154: 8ce9 and s1,s1,a0 + 80005156: 0001 nop + 80005158: 00400e93 li t4,4 + 8000515c: 01200193 li gp,18 + 80005160: 17d49663 bne s1,t4,800052cc + +0000000080005164 : + 80005164: 800004b7 lui s1,0x80000 + 80005168: fff4849b addiw s1,s1,-1 + 8000516c: 557d li a0,-1 + 8000516e: 9c89 subw s1,s1,a0 + 80005170: 80000eb7 lui t4,0x80000 + 80005174: 01300193 li gp,19 + 80005178: 15d49a63 bne s1,t4,800052cc + +000000008000517c : + 8000517c: 800004b7 lui s1,0x80000 + 80005180: fff4849b addiw s1,s1,-1 + 80005184: 4505 li a0,1 + 80005186: 9ca9 addw s1,s1,a0 + 80005188: 80000eb7 lui t4,0x80000 + 8000518c: 01400193 li gp,20 + 80005190: 13d49e63 bne s1,t4,800052cc + +0000000080005194 : + 80005194: 00001437 lui s0,0x1 + 80005198: 2344041b addiw s0,s0,564 + 8000519c: 0412 slli s0,s0,0x4 + 8000519e: 0001 nop + 800051a0: 00012eb7 lui t4,0x12 + 800051a4: 340e8e9b addiw t4,t4,832 + 800051a8: 01500193 li gp,21 + 800051ac: 13d41063 bne s0,t4,800052cc + +00000000800051b0 : + 800051b0: 4081 li ra,0 + 800051b2: a011 j 800051b6 + 800051b4: a011 j 800051b8 + 800051b6: a011 j 800051ba + 800051b8: aa11 j 800052cc + 800051ba: 0001 nop + 800051bc: 00000e93 li t4,0 + 800051c0: 01e00193 li gp,30 + 800051c4: 11d09463 bne ra,t4,800052cc + +00000000800051c8 : + 800051c8: 4501 li a0,0 + 800051ca: c111 beqz a0,800051ce + 800051cc: a011 j 800051d0 + 800051ce: a011 j 800051d2 + 800051d0: a8f5 j 800052cc + 800051d2: 0001 nop + 800051d4: 00000e93 li t4,0 + 800051d8: 01f00193 li gp,31 + 800051dc: 0fd01863 bne zero,t4,800052cc + +00000000800051e0 : + 800051e0: 4505 li a0,1 + 800051e2: e111 bnez a0,800051e6 + 800051e4: a011 j 800051e8 + 800051e6: a011 j 800051ea + 800051e8: a0d5 j 800052cc + 800051ea: 0001 nop + 800051ec: 00000e93 li t4,0 + 800051f0: 02000193 li gp,32 + 800051f4: 0dd01c63 bne zero,t4,800052cc + +00000000800051f8 : + 800051f8: 4505 li a0,1 + 800051fa: c111 beqz a0,800051fe + 800051fc: a011 j 80005200 + 800051fe: a0f9 j 800052cc + 80005200: 00000e93 li t4,0 + 80005204: 02100193 li gp,33 + 80005208: 0dd01263 bne zero,t4,800052cc + +000000008000520c : + 8000520c: 4501 li a0,0 + 8000520e: e111 bnez a0,80005212 + 80005210: a011 j 80005214 + 80005212: a86d j 800052cc + 80005214: 00000e93 li t4,0 + 80005218: 02200193 li gp,34 + 8000521c: 0bd01863 bne zero,t4,800052cc + +0000000080005220 : + 80005220: 00000297 auipc t0,0x0 + 80005224: 00e28293 addi t0,t0,14 # 8000522e + 80005228: 4081 li ra,0 + 8000522a: 8282 jr t0 + 8000522c: a011 j 80005230 + 8000522e: a011 j 80005232 + 80005230: a871 j 800052cc + 80005232: 0001 nop + 80005234: 00000e93 li t4,0 + 80005238: 02300193 li gp,35 + 8000523c: 09d09863 bne ra,t4,800052cc + +0000000080005240 : + 80005240: 00000297 auipc t0,0x0 + 80005244: 00e28293 addi t0,t0,14 # 8000524e + 80005248: 4081 li ra,0 + 8000524a: 9282 jalr t0 + 8000524c: a011 j 80005250 + 8000524e: a011 j 80005252 + 80005250: a8b5 j 800052cc + 80005252: 405080b3 sub ra,ra,t0 + 80005256: 0001 nop + 80005258: ffe00e93 li t4,-2 + 8000525c: 02400193 li gp,36 + 80005260: 07d09663 bne ra,t4,800052cc + 80005264: ffffe117 auipc sp,0xffffe + 80005268: dac10113 addi sp,sp,-596 # 80003010 + +000000008000526c : + 8000526c: 4532 lw a0,12(sp) + 8000526e: 0505 addi a0,a0,1 + 80005270: c62a sw a0,12(sp) + 80005272: 4632 lw a2,12(sp) + 80005274: fedcceb7 lui t4,0xfedcc + 80005278: a99e8e9b addiw t4,t4,-1383 + 8000527c: 02800193 li gp,40 + 80005280: 05d61663 bne a2,t4,800052cc + +0000000080005284 : + 80005284: 6522 ld a0,8(sp) + 80005286: 0505 addi a0,a0,1 + 80005288: e42a sd a0,8(sp) + 8000528a: 6622 ld a2,8(sp) + 8000528c: fff6eeb7 lui t4,0xfff6e + 80005290: 5d5e8e9b addiw t4,t4,1493 + 80005294: 00ce9e93 slli t4,t4,0xc + 80005298: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff624cb> + 8000529c: 00de9e93 slli t4,t4,0xd + 800052a0: 543e8e93 addi t4,t4,1347 + 800052a4: 00ce9e93 slli t4,t4,0xc + 800052a8: 211e8e93 addi t4,t4,529 + 800052ac: 02900193 li gp,41 + 800052b0: 01d61e63 bne a2,t4,800052cc + +00000000800052b4 : + 800052b4: 12300513 li a0,291 + 800052b8: 82aa mv t0,a0 + 800052ba: 92aa add t0,t0,a0 + 800052bc: 24600e93 li t4,582 + 800052c0: 02a00193 li gp,42 + 800052c4: 01d29463 bne t0,t4,800052cc + 800052c8: 00301a63 bne zero,gp,800052dc + +00000000800052cc : + 800052cc: 00119513 slli a0,gp,0x1 + 800052d0: 00050063 beqz a0,800052d0 + 800052d4: 00156513 ori a0,a0,1 + 800052d8: 00000073 ecall + +00000000800052dc : + 800052dc: 00100513 li a0,1 + 800052e0: 00000073 ecall + 800052e4: c0001073 unimp + 800052e8: 0000 unimp + 800052ea: 0000 unimp + 800052ec: 0000 unimp + 800052ee: 0000 unimp + 800052f0: 0000 unimp + 800052f2: 0000 unimp + 800052f4: 0000 unimp + 800052f6: 0000 unimp + 800052f8: 0000 unimp + 800052fa: 0000 unimp + 800052fc: 0000 unimp + 800052fe: 0000 unimp + 80005300: 0000 unimp + 80005302: 0000 unimp + 80005304: 0000 unimp + 80005306: 0000 unimp + 80005308: 0000 unimp + 8000530a: 0000 unimp + 8000530c: 0000 unimp + 8000530e: 0000 unimp + 80005310: 0000 unimp + 80005312: 0000 unimp + 80005314: 0000 unimp + 80005316: 0000 unimp + 80005318: 0000 unimp + 8000531a: 0000 unimp + 8000531c: 0000 unimp + 8000531e: 0000 unimp + 80005320: 0000 unimp + 80005322: 0000 unimp + 80005324: 0000 unimp + 80005326: 0000 unimp + 80005328: 0000 unimp + 8000532a: 0000 unimp + 8000532c: 0000 unimp + 8000532e: 0000 unimp + 80005330: 0000 unimp + 80005332: 0000 unimp + 80005334: 0000 unimp + 80005336: 0000 unimp + 80005338: 0000 unimp + 8000533a: 0000 unimp + 8000533c: 0000 unimp + 8000533e: 0000 unimp + 80005340: 0000 unimp + 80005342: 0000 unimp + 80005344: 0000 unimp + 80005346: 0000 unimp + 80005348: 0000 unimp + 8000534a: 0000 unimp + 8000534c: 0000 unimp + 8000534e: 0000 unimp + 80005350: 0000 unimp + 80005352: 0000 unimp + 80005354: 0000 unimp + 80005356: 0000 unimp + 80005358: 0000 unimp + 8000535a: 0000 unimp + 8000535c: 0000 unimp + 8000535e: 0000 unimp + 80005360: 0000 unimp + 80005362: 0000 unimp + 80005364: 0000 unimp + 80005366: 0000 unimp + 80005368: 0000 unimp + 8000536a: 0000 unimp + 8000536c: 0000 unimp + 8000536e: 0000 unimp + 80005370: 0000 unimp + 80005372: 0000 unimp + 80005374: 0000 unimp + 80005376: 0000 unimp + 80005378: 0000 unimp + 8000537a: 0000 unimp + 8000537c: 0000 unimp + 8000537e: 0000 unimp + 80005380: 0000 unimp + 80005382: 0000 unimp + 80005384: 0000 unimp + 80005386: 0000 unimp + 80005388: 0000 unimp + 8000538a: 0000 unimp + 8000538c: 0000 unimp + 8000538e: 0000 unimp + 80005390: 0000 unimp + 80005392: 0000 unimp + 80005394: 0000 unimp + 80005396: 0000 unimp + 80005398: 0000 unimp + 8000539a: 0000 unimp + 8000539c: 0000 unimp + 8000539e: 0000 unimp + 800053a0: 0000 unimp + 800053a2: 0000 unimp + 800053a4: 0000 unimp + 800053a6: 0000 unimp + 800053a8: 0000 unimp + 800053aa: 0000 unimp + 800053ac: 0000 unimp + 800053ae: 0000 unimp + 800053b0: 0000 unimp + 800053b2: 0000 unimp + 800053b4: 0000 unimp + 800053b6: 0000 unimp + 800053b8: 0000 unimp + 800053ba: 0000 unimp + 800053bc: 0000 unimp + 800053be: 0000 unimp + 800053c0: 0000 unimp + 800053c2: 0000 unimp + 800053c4: 0000 unimp + 800053c6: 0000 unimp + 800053c8: 0000 unimp + 800053ca: 0000 unimp + 800053cc: 0000 unimp + 800053ce: 0000 unimp + 800053d0: 0000 unimp + 800053d2: 0000 unimp + 800053d4: 0000 unimp + 800053d6: 0000 unimp + 800053d8: 0000 unimp + 800053da: 0000 unimp + 800053dc: 0000 unimp + 800053de: 0000 unimp + 800053e0: 0000 unimp + 800053e2: 0000 unimp + 800053e4: 0000 unimp + 800053e6: 0000 unimp + 800053e8: 0000 unimp + 800053ea: 0000 unimp + 800053ec: 0000 unimp + 800053ee: 0000 unimp + 800053f0: 0000 unimp + 800053f2: 0000 unimp + 800053f4: 0000 unimp + 800053f6: 0000 unimp + 800053f8: 0000 unimp + 800053fa: 0000 unimp + 800053fc: 0000 unimp + 800053fe: 0000 unimp + 80005400: 0000 unimp + 80005402: 0000 unimp + 80005404: 0000 unimp + 80005406: 0000 unimp + 80005408: 0000 unimp + 8000540a: 0000 unimp + 8000540c: 0000 unimp + 8000540e: 0000 unimp + 80005410: 0000 unimp + 80005412: 0000 unimp + 80005414: 0000 unimp + 80005416: 0000 unimp + 80005418: 0000 unimp + 8000541a: 0000 unimp + 8000541c: 0000 unimp + 8000541e: 0000 unimp + 80005420: 0000 unimp + 80005422: 0000 unimp + 80005424: 0000 unimp + 80005426: 0000 unimp + 80005428: 0000 unimp + 8000542a: 0000 unimp + 8000542c: 0000 unimp + 8000542e: 0000 unimp + 80005430: 0000 unimp + 80005432: 0000 unimp + 80005434: 0000 unimp + 80005436: 0000 unimp + 80005438: 0000 unimp + 8000543a: 0000 unimp + 8000543c: 0000 unimp + 8000543e: 0000 unimp + 80005440: 0000 unimp + 80005442: 0000 unimp + 80005444: 0000 unimp + 80005446: 0000 unimp + 80005448: 0000 unimp + 8000544a: 0000 unimp + 8000544c: 0000 unimp + 8000544e: 0000 unimp + 80005450: 0000 unimp + 80005452: 0000 unimp + 80005454: 0000 unimp + 80005456: 0000 unimp + 80005458: 0000 unimp + 8000545a: 0000 unimp + 8000545c: 0000 unimp + 8000545e: 0000 unimp + 80005460: 0000 unimp + 80005462: 0000 unimp + 80005464: 0000 unimp + 80005466: 0000 unimp + 80005468: 0000 unimp + 8000546a: 0000 unimp + 8000546c: 0000 unimp + 8000546e: 0000 unimp + 80005470: 0000 unimp + 80005472: 0000 unimp + 80005474: 0000 unimp + 80005476: 0000 unimp + 80005478: 0000 unimp + 8000547a: 0000 unimp + 8000547c: 0000 unimp + 8000547e: 0000 unimp + 80005480: 0000 unimp + 80005482: 0000 unimp + 80005484: 0000 unimp + 80005486: 0000 unimp + 80005488: 0000 unimp + 8000548a: 0000 unimp + 8000548c: 0000 unimp + 8000548e: 0000 unimp + 80005490: 0000 unimp + 80005492: 0000 unimp + 80005494: 0000 unimp + 80005496: 0000 unimp + 80005498: 0000 unimp + 8000549a: 0000 unimp + 8000549c: 0000 unimp + 8000549e: 0000 unimp + 800054a0: 0000 unimp + 800054a2: 0000 unimp + 800054a4: 0000 unimp + 800054a6: 0000 unimp + 800054a8: 0000 unimp + 800054aa: 0000 unimp + 800054ac: 0000 unimp + 800054ae: 0000 unimp + 800054b0: 0000 unimp + 800054b2: 0000 unimp + 800054b4: 0000 unimp + 800054b6: 0000 unimp + 800054b8: 0000 unimp + 800054ba: 0000 unimp + 800054bc: 0000 unimp + 800054be: 0000 unimp + 800054c0: 0000 unimp + 800054c2: 0000 unimp + 800054c4: 0000 unimp + 800054c6: 0000 unimp + 800054c8: 0000 unimp + 800054ca: 0000 unimp + 800054cc: 0000 unimp + 800054ce: 0000 unimp + 800054d0: 0000 unimp + 800054d2: 0000 unimp + 800054d4: 0000 unimp + 800054d6: 0000 unimp + 800054d8: 0000 unimp + 800054da: 0000 unimp + 800054dc: 0000 unimp + 800054de: 0000 unimp + 800054e0: 0000 unimp + 800054e2: 0000 unimp + 800054e4: 0000 unimp + 800054e6: 0000 unimp + 800054e8: 0000 unimp + 800054ea: 0000 unimp + 800054ec: 0000 unimp + 800054ee: 0000 unimp + 800054f0: 0000 unimp + 800054f2: 0000 unimp + 800054f4: 0000 unimp + 800054f6: 0000 unimp + 800054f8: 0000 unimp + 800054fa: 0000 unimp + 800054fc: 0000 unimp + 800054fe: 0000 unimp + 80005500: 0000 unimp + 80005502: 0000 unimp + 80005504: 0000 unimp + 80005506: 0000 unimp + 80005508: 0000 unimp + 8000550a: 0000 unimp + 8000550c: 0000 unimp + 8000550e: 0000 unimp + 80005510: 0000 unimp + 80005512: 0000 unimp + 80005514: 0000 unimp + 80005516: 0000 unimp + 80005518: 0000 unimp + 8000551a: 0000 unimp + 8000551c: 0000 unimp + 8000551e: 0000 unimp + 80005520: 0000 unimp + 80005522: 0000 unimp + 80005524: 0000 unimp + 80005526: 0000 unimp + 80005528: 0000 unimp + 8000552a: 0000 unimp + 8000552c: 0000 unimp + 8000552e: 0000 unimp + 80005530: 0000 unimp + 80005532: 0000 unimp + 80005534: 0000 unimp + 80005536: 0000 unimp + 80005538: 0000 unimp + 8000553a: 0000 unimp + 8000553c: 0000 unimp + 8000553e: 0000 unimp + 80005540: 0000 unimp + 80005542: 0000 unimp + 80005544: 0000 unimp + 80005546: 0000 unimp + 80005548: 0000 unimp + 8000554a: 0000 unimp + 8000554c: 0000 unimp + 8000554e: 0000 unimp + 80005550: 0000 unimp + 80005552: 0000 unimp + 80005554: 0000 unimp + 80005556: 0000 unimp + 80005558: 0000 unimp + 8000555a: 0000 unimp + 8000555c: 0000 unimp + 8000555e: 0000 unimp + 80005560: 0000 unimp + 80005562: 0000 unimp + 80005564: 0000 unimp + 80005566: 0000 unimp + 80005568: 0000 unimp + 8000556a: 0000 unimp + 8000556c: 0000 unimp + 8000556e: 0000 unimp + 80005570: 0000 unimp + 80005572: 0000 unimp + 80005574: 0000 unimp + 80005576: 0000 unimp + 80005578: 0000 unimp + 8000557a: 0000 unimp + 8000557c: 0000 unimp + 8000557e: 0000 unimp + 80005580: 0000 unimp + 80005582: 0000 unimp + 80005584: 0000 unimp + 80005586: 0000 unimp + 80005588: 0000 unimp + 8000558a: 0000 unimp + 8000558c: 0000 unimp + 8000558e: 0000 unimp + 80005590: 0000 unimp + 80005592: 0000 unimp + 80005594: 0000 unimp + 80005596: 0000 unimp + 80005598: 0000 unimp + 8000559a: 0000 unimp + 8000559c: 0000 unimp + 8000559e: 0000 unimp + 800055a0: 0000 unimp + 800055a2: 0000 unimp + 800055a4: 0000 unimp + 800055a6: 0000 unimp + 800055a8: 0000 unimp + 800055aa: 0000 unimp + 800055ac: 0000 unimp + 800055ae: 0000 unimp + 800055b0: 0000 unimp + 800055b2: 0000 unimp + 800055b4: 0000 unimp + 800055b6: 0000 unimp + 800055b8: 0000 unimp + 800055ba: 0000 unimp + 800055bc: 0000 unimp + 800055be: 0000 unimp + 800055c0: 0000 unimp + 800055c2: 0000 unimp + 800055c4: 0000 unimp + 800055c6: 0000 unimp + 800055c8: 0000 unimp + 800055ca: 0000 unimp + 800055cc: 0000 unimp + 800055ce: 0000 unimp + 800055d0: 0000 unimp + 800055d2: 0000 unimp + 800055d4: 0000 unimp + 800055d6: 0000 unimp + 800055d8: 0000 unimp + 800055da: 0000 unimp + 800055dc: 0000 unimp + 800055de: 0000 unimp + 800055e0: 0000 unimp + 800055e2: 0000 unimp + 800055e4: 0000 unimp + 800055e6: 0000 unimp + 800055e8: 0000 unimp + 800055ea: 0000 unimp + 800055ec: 0000 unimp + 800055ee: 0000 unimp + 800055f0: 0000 unimp + 800055f2: 0000 unimp + 800055f4: 0000 unimp + 800055f6: 0000 unimp + 800055f8: 0000 unimp + 800055fa: 0000 unimp + 800055fc: 0000 unimp + 800055fe: 0000 unimp + 80005600: 0000 unimp + 80005602: 0000 unimp + 80005604: 0000 unimp + 80005606: 0000 unimp + 80005608: 0000 unimp + 8000560a: 0000 unimp + 8000560c: 0000 unimp + 8000560e: 0000 unimp + 80005610: 0000 unimp + 80005612: 0000 unimp + 80005614: 0000 unimp + 80005616: 0000 unimp + 80005618: 0000 unimp + 8000561a: 0000 unimp + 8000561c: 0000 unimp + 8000561e: 0000 unimp + 80005620: 0000 unimp + 80005622: 0000 unimp + 80005624: 0000 unimp + 80005626: 0000 unimp + 80005628: 0000 unimp + 8000562a: 0000 unimp + 8000562c: 0000 unimp + 8000562e: 0000 unimp + 80005630: 0000 unimp + 80005632: 0000 unimp + 80005634: 0000 unimp + 80005636: 0000 unimp + 80005638: 0000 unimp + 8000563a: 0000 unimp + 8000563c: 0000 unimp + 8000563e: 0000 unimp + 80005640: 0000 unimp + 80005642: 0000 unimp + 80005644: 0000 unimp + 80005646: 0000 unimp + 80005648: 0000 unimp + 8000564a: 0000 unimp + 8000564c: 0000 unimp + 8000564e: 0000 unimp + 80005650: 0000 unimp + 80005652: 0000 unimp + 80005654: 0000 unimp + 80005656: 0000 unimp + 80005658: 0000 unimp + 8000565a: 0000 unimp + 8000565c: 0000 unimp + 8000565e: 0000 unimp + 80005660: 0000 unimp + 80005662: 0000 unimp + 80005664: 0000 unimp + 80005666: 0000 unimp + 80005668: 0000 unimp + 8000566a: 0000 unimp + 8000566c: 0000 unimp + 8000566e: 0000 unimp + 80005670: 0000 unimp + 80005672: 0000 unimp + 80005674: 0000 unimp + 80005676: 0000 unimp + 80005678: 0000 unimp + 8000567a: 0000 unimp + 8000567c: 0000 unimp + 8000567e: 0000 unimp + 80005680: 0000 unimp + 80005682: 0000 unimp + 80005684: 0000 unimp + 80005686: 0000 unimp + 80005688: 0000 unimp + 8000568a: 0000 unimp + 8000568c: 0000 unimp + 8000568e: 0000 unimp + 80005690: 0000 unimp + 80005692: 0000 unimp + 80005694: 0000 unimp + 80005696: 0000 unimp + 80005698: 0000 unimp + 8000569a: 0000 unimp + 8000569c: 0000 unimp + 8000569e: 0000 unimp + 800056a0: 0000 unimp + 800056a2: 0000 unimp + 800056a4: 0000 unimp + 800056a6: 0000 unimp + 800056a8: 0000 unimp + 800056aa: 0000 unimp + 800056ac: 0000 unimp + 800056ae: 0000 unimp + 800056b0: 0000 unimp + 800056b2: 0000 unimp + 800056b4: 0000 unimp + 800056b6: 0000 unimp + 800056b8: 0000 unimp + 800056ba: 0000 unimp + 800056bc: 0000 unimp + 800056be: 0000 unimp + 800056c0: 0000 unimp + 800056c2: 0000 unimp + 800056c4: 0000 unimp + 800056c6: 0000 unimp + 800056c8: 0000 unimp + 800056ca: 0000 unimp + 800056cc: 0000 unimp + 800056ce: 0000 unimp + 800056d0: 0000 unimp + 800056d2: 0000 unimp + 800056d4: 0000 unimp + 800056d6: 0000 unimp + 800056d8: 0000 unimp + 800056da: 0000 unimp + 800056dc: 0000 unimp + 800056de: 0000 unimp + 800056e0: 0000 unimp + 800056e2: 0000 unimp + 800056e4: 0000 unimp + 800056e6: 0000 unimp + 800056e8: 0000 unimp + 800056ea: 0000 unimp + 800056ec: 0000 unimp + 800056ee: 0000 unimp + 800056f0: 0000 unimp + 800056f2: 0000 unimp + 800056f4: 0000 unimp + 800056f6: 0000 unimp + 800056f8: 0000 unimp + 800056fa: 0000 unimp + 800056fc: 0000 unimp + 800056fe: 0000 unimp + 80005700: 0000 unimp + 80005702: 0000 unimp + 80005704: 0000 unimp + 80005706: 0000 unimp + 80005708: 0000 unimp + 8000570a: 0000 unimp + 8000570c: 0000 unimp + 8000570e: 0000 unimp + 80005710: 0000 unimp + 80005712: 0000 unimp + 80005714: 0000 unimp + 80005716: 0000 unimp + 80005718: 0000 unimp + 8000571a: 0000 unimp + 8000571c: 0000 unimp + 8000571e: 0000 unimp + 80005720: 0000 unimp + 80005722: 0000 unimp + 80005724: 0000 unimp + 80005726: 0000 unimp + 80005728: 0000 unimp + 8000572a: 0000 unimp + 8000572c: 0000 unimp + 8000572e: 0000 unimp + 80005730: 0000 unimp + 80005732: 0000 unimp + 80005734: 0000 unimp + 80005736: 0000 unimp + 80005738: 0000 unimp + 8000573a: 0000 unimp + 8000573c: 0000 unimp + 8000573e: 0000 unimp + 80005740: 0000 unimp + 80005742: 0000 unimp + 80005744: 0000 unimp + 80005746: 0000 unimp + 80005748: 0000 unimp + 8000574a: 0000 unimp + 8000574c: 0000 unimp + 8000574e: 0000 unimp + 80005750: 0000 unimp + 80005752: 0000 unimp + 80005754: 0000 unimp + 80005756: 0000 unimp + 80005758: 0000 unimp + 8000575a: 0000 unimp + 8000575c: 0000 unimp + 8000575e: 0000 unimp + 80005760: 0000 unimp + 80005762: 0000 unimp + 80005764: 0000 unimp + 80005766: 0000 unimp + 80005768: 0000 unimp + 8000576a: 0000 unimp + 8000576c: 0000 unimp + 8000576e: 0000 unimp + 80005770: 0000 unimp + 80005772: 0000 unimp + 80005774: 0000 unimp + 80005776: 0000 unimp + 80005778: 0000 unimp + 8000577a: 0000 unimp + 8000577c: 0000 unimp + 8000577e: 0000 unimp + 80005780: 0000 unimp + 80005782: 0000 unimp + 80005784: 0000 unimp + 80005786: 0000 unimp + 80005788: 0000 unimp + 8000578a: 0000 unimp + 8000578c: 0000 unimp + 8000578e: 0000 unimp + 80005790: 0000 unimp + 80005792: 0000 unimp + 80005794: 0000 unimp + 80005796: 0000 unimp + 80005798: 0000 unimp + 8000579a: 0000 unimp + 8000579c: 0000 unimp + 8000579e: 0000 unimp + 800057a0: 0000 unimp + 800057a2: 0000 unimp + 800057a4: 0000 unimp + 800057a6: 0000 unimp + 800057a8: 0000 unimp + 800057aa: 0000 unimp + 800057ac: 0000 unimp + 800057ae: 0000 unimp + 800057b0: 0000 unimp + 800057b2: 0000 unimp + 800057b4: 0000 unimp + 800057b6: 0000 unimp + 800057b8: 0000 unimp + 800057ba: 0000 unimp + 800057bc: 0000 unimp + 800057be: 0000 unimp + 800057c0: 0000 unimp + 800057c2: 0000 unimp + 800057c4: 0000 unimp + 800057c6: 0000 unimp + 800057c8: 0000 unimp + 800057ca: 0000 unimp + 800057cc: 0000 unimp + 800057ce: 0000 unimp + 800057d0: 0000 unimp + 800057d2: 0000 unimp + 800057d4: 0000 unimp + 800057d6: 0000 unimp + 800057d8: 0000 unimp + 800057da: 0000 unimp + 800057dc: 0000 unimp + 800057de: 0000 unimp + 800057e0: 0000 unimp + 800057e2: 0000 unimp + 800057e4: 0000 unimp + 800057e6: 0000 unimp + 800057e8: 0000 unimp + 800057ea: 0000 unimp + 800057ec: 0000 unimp + 800057ee: 0000 unimp + 800057f0: 0000 unimp + 800057f2: 0000 unimp + 800057f4: 0000 unimp + 800057f6: 0000 unimp + 800057f8: 0000 unimp + 800057fa: 0000 unimp + 800057fc: 0000 unimp + 800057fe: 0000 unimp + 80005800: 0000 unimp + 80005802: 0000 unimp + 80005804: 0000 unimp + 80005806: 0000 unimp + 80005808: 0000 unimp + 8000580a: 0000 unimp + 8000580c: 0000 unimp + 8000580e: 0000 unimp + 80005810: 0000 unimp + 80005812: 0000 unimp + 80005814: 0000 unimp + 80005816: 0000 unimp + 80005818: 0000 unimp + 8000581a: 0000 unimp + 8000581c: 0000 unimp + 8000581e: 0000 unimp + 80005820: 0000 unimp + 80005822: 0000 unimp + 80005824: 0000 unimp + 80005826: 0000 unimp + 80005828: 0000 unimp + 8000582a: 0000 unimp + 8000582c: 0000 unimp + 8000582e: 0000 unimp + 80005830: 0000 unimp + 80005832: 0000 unimp + 80005834: 0000 unimp + 80005836: 0000 unimp + 80005838: 0000 unimp + 8000583a: 0000 unimp + 8000583c: 0000 unimp + 8000583e: 0000 unimp + 80005840: 0000 unimp + 80005842: 0000 unimp + 80005844: 0000 unimp + 80005846: 0000 unimp + 80005848: 0000 unimp + 8000584a: 0000 unimp + 8000584c: 0000 unimp + 8000584e: 0000 unimp + 80005850: 0000 unimp + 80005852: 0000 unimp + 80005854: 0000 unimp + 80005856: 0000 unimp + 80005858: 0000 unimp + 8000585a: 0000 unimp + 8000585c: 0000 unimp + 8000585e: 0000 unimp + 80005860: 0000 unimp + 80005862: 0000 unimp + 80005864: 0000 unimp + 80005866: 0000 unimp + 80005868: 0000 unimp + 8000586a: 0000 unimp + 8000586c: 0000 unimp + 8000586e: 0000 unimp + 80005870: 0000 unimp + 80005872: 0000 unimp + 80005874: 0000 unimp + 80005876: 0000 unimp + 80005878: 0000 unimp + 8000587a: 0000 unimp + 8000587c: 0000 unimp + 8000587e: 0000 unimp + 80005880: 0000 unimp + 80005882: 0000 unimp + 80005884: 0000 unimp + 80005886: 0000 unimp + 80005888: 0000 unimp + 8000588a: 0000 unimp + 8000588c: 0000 unimp + 8000588e: 0000 unimp + 80005890: 0000 unimp + 80005892: 0000 unimp + 80005894: 0000 unimp + 80005896: 0000 unimp + 80005898: 0000 unimp + 8000589a: 0000 unimp + 8000589c: 0000 unimp + 8000589e: 0000 unimp + 800058a0: 0000 unimp + 800058a2: 0000 unimp + 800058a4: 0000 unimp + 800058a6: 0000 unimp + 800058a8: 0000 unimp + 800058aa: 0000 unimp + 800058ac: 0000 unimp + 800058ae: 0000 unimp + 800058b0: 0000 unimp + 800058b2: 0000 unimp + 800058b4: 0000 unimp + 800058b6: 0000 unimp + 800058b8: 0000 unimp + 800058ba: 0000 unimp + 800058bc: 0000 unimp + 800058be: 0000 unimp + 800058c0: 0000 unimp + 800058c2: 0000 unimp + 800058c4: 0000 unimp + 800058c6: 0000 unimp + 800058c8: 0000 unimp + 800058ca: 0000 unimp + 800058cc: 0000 unimp + 800058ce: 0000 unimp + 800058d0: 0000 unimp + 800058d2: 0000 unimp + 800058d4: 0000 unimp + 800058d6: 0000 unimp + 800058d8: 0000 unimp + 800058da: 0000 unimp + 800058dc: 0000 unimp + 800058de: 0000 unimp + 800058e0: 0000 unimp + 800058e2: 0000 unimp + 800058e4: 0000 unimp + 800058e6: 0000 unimp + 800058e8: 0000 unimp + 800058ea: 0000 unimp + 800058ec: 0000 unimp + 800058ee: 0000 unimp + 800058f0: 0000 unimp + 800058f2: 0000 unimp + 800058f4: 0000 unimp + 800058f6: 0000 unimp + 800058f8: 0000 unimp + 800058fa: 0000 unimp + 800058fc: 0000 unimp + 800058fe: 0000 unimp + 80005900: 0000 unimp + 80005902: 0000 unimp + 80005904: 0000 unimp + 80005906: 0000 unimp + 80005908: 0000 unimp + 8000590a: 0000 unimp + 8000590c: 0000 unimp + 8000590e: 0000 unimp + 80005910: 0000 unimp + 80005912: 0000 unimp + 80005914: 0000 unimp + 80005916: 0000 unimp + 80005918: 0000 unimp + 8000591a: 0000 unimp + 8000591c: 0000 unimp + 8000591e: 0000 unimp + 80005920: 0000 unimp + 80005922: 0000 unimp + 80005924: 0000 unimp + 80005926: 0000 unimp + 80005928: 0000 unimp + 8000592a: 0000 unimp + 8000592c: 0000 unimp + 8000592e: 0000 unimp + 80005930: 0000 unimp + 80005932: 0000 unimp + 80005934: 0000 unimp + 80005936: 0000 unimp + 80005938: 0000 unimp + 8000593a: 0000 unimp + 8000593c: 0000 unimp + 8000593e: 0000 unimp + 80005940: 0000 unimp + 80005942: 0000 unimp + 80005944: 0000 unimp + 80005946: 0000 unimp + 80005948: 0000 unimp + 8000594a: 0000 unimp + 8000594c: 0000 unimp + 8000594e: 0000 unimp + 80005950: 0000 unimp + 80005952: 0000 unimp + 80005954: 0000 unimp + 80005956: 0000 unimp + 80005958: 0000 unimp + 8000595a: 0000 unimp + 8000595c: 0000 unimp + 8000595e: 0000 unimp + 80005960: 0000 unimp + 80005962: 0000 unimp + 80005964: 0000 unimp + 80005966: 0000 unimp + 80005968: 0000 unimp + 8000596a: 0000 unimp + 8000596c: 0000 unimp + 8000596e: 0000 unimp + 80005970: 0000 unimp + 80005972: 0000 unimp + 80005974: 0000 unimp + 80005976: 0000 unimp + 80005978: 0000 unimp + 8000597a: 0000 unimp + 8000597c: 0000 unimp + 8000597e: 0000 unimp + 80005980: 0000 unimp + 80005982: 0000 unimp + 80005984: 0000 unimp + 80005986: 0000 unimp + 80005988: 0000 unimp + 8000598a: 0000 unimp + 8000598c: 0000 unimp + 8000598e: 0000 unimp + 80005990: 0000 unimp + 80005992: 0000 unimp + 80005994: 0000 unimp + 80005996: 0000 unimp + 80005998: 0000 unimp + 8000599a: 0000 unimp + 8000599c: 0000 unimp + 8000599e: 0000 unimp + 800059a0: 0000 unimp + 800059a2: 0000 unimp + 800059a4: 0000 unimp + 800059a6: 0000 unimp + 800059a8: 0000 unimp + 800059aa: 0000 unimp + 800059ac: 0000 unimp + 800059ae: 0000 unimp + 800059b0: 0000 unimp + 800059b2: 0000 unimp + 800059b4: 0000 unimp + 800059b6: 0000 unimp + 800059b8: 0000 unimp + 800059ba: 0000 unimp + 800059bc: 0000 unimp + 800059be: 0000 unimp + 800059c0: 0000 unimp + 800059c2: 0000 unimp + 800059c4: 0000 unimp + 800059c6: 0000 unimp + 800059c8: 0000 unimp + 800059ca: 0000 unimp + 800059cc: 0000 unimp + 800059ce: 0000 unimp + 800059d0: 0000 unimp + 800059d2: 0000 unimp + 800059d4: 0000 unimp + 800059d6: 0000 unimp + 800059d8: 0000 unimp + 800059da: 0000 unimp + 800059dc: 0000 unimp + 800059de: 0000 unimp + 800059e0: 0000 unimp + 800059e2: 0000 unimp + 800059e4: 0000 unimp + 800059e6: 0000 unimp + 800059e8: 0000 unimp + 800059ea: 0000 unimp + 800059ec: 0000 unimp + 800059ee: 0000 unimp + 800059f0: 0000 unimp + 800059f2: 0000 unimp + 800059f4: 0000 unimp + 800059f6: 0000 unimp + 800059f8: 0000 unimp + 800059fa: 0000 unimp + 800059fc: 0000 unimp + 800059fe: 0000 unimp + 80005a00: 0000 unimp + 80005a02: 0000 unimp + 80005a04: 0000 unimp + 80005a06: 0000 unimp + 80005a08: 0000 unimp + 80005a0a: 0000 unimp + 80005a0c: 0000 unimp + 80005a0e: 0000 unimp + 80005a10: 0000 unimp + 80005a12: 0000 unimp + 80005a14: 0000 unimp + 80005a16: 0000 unimp + 80005a18: 0000 unimp + 80005a1a: 0000 unimp + 80005a1c: 0000 unimp + 80005a1e: 0000 unimp + 80005a20: 0000 unimp + 80005a22: 0000 unimp + 80005a24: 0000 unimp + 80005a26: 0000 unimp + 80005a28: 0000 unimp + 80005a2a: 0000 unimp + 80005a2c: 0000 unimp + 80005a2e: 0000 unimp + 80005a30: 0000 unimp + 80005a32: 0000 unimp + 80005a34: 0000 unimp + 80005a36: 0000 unimp + 80005a38: 0000 unimp + 80005a3a: 0000 unimp + 80005a3c: 0000 unimp + 80005a3e: 0000 unimp + 80005a40: 0000 unimp + 80005a42: 0000 unimp + 80005a44: 0000 unimp + 80005a46: 0000 unimp + 80005a48: 0000 unimp + 80005a4a: 0000 unimp + 80005a4c: 0000 unimp + 80005a4e: 0000 unimp + 80005a50: 0000 unimp + 80005a52: 0000 unimp + 80005a54: 0000 unimp + 80005a56: 0000 unimp + 80005a58: 0000 unimp + 80005a5a: 0000 unimp + 80005a5c: 0000 unimp + 80005a5e: 0000 unimp + 80005a60: 0000 unimp + 80005a62: 0000 unimp + 80005a64: 0000 unimp + 80005a66: 0000 unimp + 80005a68: 0000 unimp + 80005a6a: 0000 unimp + 80005a6c: 0000 unimp + 80005a6e: 0000 unimp + 80005a70: 0000 unimp + 80005a72: 0000 unimp + 80005a74: 0000 unimp + 80005a76: 0000 unimp + 80005a78: 0000 unimp + 80005a7a: 0000 unimp + 80005a7c: 0000 unimp + 80005a7e: 0000 unimp + 80005a80: 0000 unimp + 80005a82: 0000 unimp + 80005a84: 0000 unimp + 80005a86: 0000 unimp + 80005a88: 0000 unimp + 80005a8a: 0000 unimp + 80005a8c: 0000 unimp + 80005a8e: 0000 unimp + 80005a90: 0000 unimp + 80005a92: 0000 unimp + 80005a94: 0000 unimp + 80005a96: 0000 unimp + 80005a98: 0000 unimp + 80005a9a: 0000 unimp + 80005a9c: 0000 unimp + 80005a9e: 0000 unimp + 80005aa0: 0000 unimp + 80005aa2: 0000 unimp + 80005aa4: 0000 unimp + 80005aa6: 0000 unimp + 80005aa8: 0000 unimp + 80005aaa: 0000 unimp + 80005aac: 0000 unimp + 80005aae: 0000 unimp + 80005ab0: 0000 unimp + 80005ab2: 0000 unimp + 80005ab4: 0000 unimp + 80005ab6: 0000 unimp + 80005ab8: 0000 unimp + 80005aba: 0000 unimp + 80005abc: 0000 unimp + 80005abe: 0000 unimp + 80005ac0: 0000 unimp + 80005ac2: 0000 unimp + 80005ac4: 0000 unimp + 80005ac6: 0000 unimp + 80005ac8: 0000 unimp + 80005aca: 0000 unimp + 80005acc: 0000 unimp + 80005ace: 0000 unimp + 80005ad0: 0000 unimp + 80005ad2: 0000 unimp + 80005ad4: 0000 unimp + 80005ad6: 0000 unimp + 80005ad8: 0000 unimp + 80005ada: 0000 unimp + 80005adc: 0000 unimp + 80005ade: 0000 unimp + 80005ae0: 0000 unimp + 80005ae2: 0000 unimp + 80005ae4: 0000 unimp + 80005ae6: 0000 unimp + 80005ae8: 0000 unimp + 80005aea: 0000 unimp + 80005aec: 0000 unimp + 80005aee: 0000 unimp + 80005af0: 0000 unimp + 80005af2: 0000 unimp + 80005af4: 0000 unimp + 80005af6: 0000 unimp + 80005af8: 0000 unimp + 80005afa: 0000 unimp + 80005afc: 0000 unimp + 80005afe: 0000 unimp + 80005b00: 0000 unimp + 80005b02: 0000 unimp + 80005b04: 0000 unimp + 80005b06: 0000 unimp + 80005b08: 0000 unimp + 80005b0a: 0000 unimp + 80005b0c: 0000 unimp + 80005b0e: 0000 unimp + 80005b10: 0000 unimp + 80005b12: 0000 unimp + 80005b14: 0000 unimp + 80005b16: 0000 unimp + 80005b18: 0000 unimp + 80005b1a: 0000 unimp + 80005b1c: 0000 unimp + 80005b1e: 0000 unimp + 80005b20: 0000 unimp + 80005b22: 0000 unimp + 80005b24: 0000 unimp + 80005b26: 0000 unimp + 80005b28: 0000 unimp + 80005b2a: 0000 unimp + 80005b2c: 0000 unimp + 80005b2e: 0000 unimp + 80005b30: 0000 unimp + 80005b32: 0000 unimp + 80005b34: 0000 unimp + 80005b36: 0000 unimp + 80005b38: 0000 unimp + 80005b3a: 0000 unimp + 80005b3c: 0000 unimp + 80005b3e: 0000 unimp + 80005b40: 0000 unimp + 80005b42: 0000 unimp + 80005b44: 0000 unimp + 80005b46: 0000 unimp + 80005b48: 0000 unimp + 80005b4a: 0000 unimp + 80005b4c: 0000 unimp + 80005b4e: 0000 unimp + 80005b50: 0000 unimp + 80005b52: 0000 unimp + 80005b54: 0000 unimp + 80005b56: 0000 unimp + 80005b58: 0000 unimp + 80005b5a: 0000 unimp + 80005b5c: 0000 unimp + 80005b5e: 0000 unimp + 80005b60: 0000 unimp + 80005b62: 0000 unimp + 80005b64: 0000 unimp + 80005b66: 0000 unimp + 80005b68: 0000 unimp + 80005b6a: 0000 unimp + 80005b6c: 0000 unimp + 80005b6e: 0000 unimp + 80005b70: 0000 unimp + 80005b72: 0000 unimp + 80005b74: 0000 unimp + 80005b76: 0000 unimp + 80005b78: 0000 unimp + 80005b7a: 0000 unimp + 80005b7c: 0000 unimp + 80005b7e: 0000 unimp + 80005b80: 0000 unimp + 80005b82: 0000 unimp + 80005b84: 0000 unimp + 80005b86: 0000 unimp + 80005b88: 0000 unimp + 80005b8a: 0000 unimp + 80005b8c: 0000 unimp + 80005b8e: 0000 unimp + 80005b90: 0000 unimp + 80005b92: 0000 unimp + 80005b94: 0000 unimp + 80005b96: 0000 unimp + 80005b98: 0000 unimp + 80005b9a: 0000 unimp + 80005b9c: 0000 unimp + 80005b9e: 0000 unimp + 80005ba0: 0000 unimp + 80005ba2: 0000 unimp + 80005ba4: 0000 unimp + 80005ba6: 0000 unimp + 80005ba8: 0000 unimp + 80005baa: 0000 unimp + 80005bac: 0000 unimp + 80005bae: 0000 unimp + 80005bb0: 0000 unimp + 80005bb2: 0000 unimp + 80005bb4: 0000 unimp + 80005bb6: 0000 unimp + 80005bb8: 0000 unimp + 80005bba: 0000 unimp + 80005bbc: 0000 unimp + 80005bbe: 0000 unimp + 80005bc0: 0000 unimp + 80005bc2: 0000 unimp + 80005bc4: 0000 unimp + 80005bc6: 0000 unimp + 80005bc8: 0000 unimp + 80005bca: 0000 unimp + 80005bcc: 0000 unimp + 80005bce: 0000 unimp + 80005bd0: 0000 unimp + 80005bd2: 0000 unimp + 80005bd4: 0000 unimp + 80005bd6: 0000 unimp + 80005bd8: 0000 unimp + 80005bda: 0000 unimp + 80005bdc: 0000 unimp + 80005bde: 0000 unimp + 80005be0: 0000 unimp + 80005be2: 0000 unimp + 80005be4: 0000 unimp + 80005be6: 0000 unimp + 80005be8: 0000 unimp + 80005bea: 0000 unimp + 80005bec: 0000 unimp + 80005bee: 0000 unimp + 80005bf0: 0000 unimp + 80005bf2: 0000 unimp + 80005bf4: 0000 unimp + 80005bf6: 0000 unimp + 80005bf8: 0000 unimp + 80005bfa: 0000 unimp + 80005bfc: 0000 unimp + 80005bfe: 0000 unimp + 80005c00: 0000 unimp + 80005c02: 0000 unimp + 80005c04: 0000 unimp + 80005c06: 0000 unimp + 80005c08: 0000 unimp + 80005c0a: 0000 unimp + 80005c0c: 0000 unimp + 80005c0e: 0000 unimp + 80005c10: 0000 unimp + 80005c12: 0000 unimp + 80005c14: 0000 unimp + 80005c16: 0000 unimp + 80005c18: 0000 unimp + 80005c1a: 0000 unimp + 80005c1c: 0000 unimp + 80005c1e: 0000 unimp + 80005c20: 0000 unimp + 80005c22: 0000 unimp + 80005c24: 0000 unimp + 80005c26: 0000 unimp + 80005c28: 0000 unimp + 80005c2a: 0000 unimp + 80005c2c: 0000 unimp + 80005c2e: 0000 unimp + 80005c30: 0000 unimp + 80005c32: 0000 unimp + 80005c34: 0000 unimp + 80005c36: 0000 unimp + 80005c38: 0000 unimp + 80005c3a: 0000 unimp + 80005c3c: 0000 unimp + 80005c3e: 0000 unimp + 80005c40: 0000 unimp + 80005c42: 0000 unimp + 80005c44: 0000 unimp + 80005c46: 0000 unimp + 80005c48: 0000 unimp + 80005c4a: 0000 unimp + 80005c4c: 0000 unimp + 80005c4e: 0000 unimp + 80005c50: 0000 unimp + 80005c52: 0000 unimp + 80005c54: 0000 unimp + 80005c56: 0000 unimp + 80005c58: 0000 unimp + 80005c5a: 0000 unimp + 80005c5c: 0000 unimp + 80005c5e: 0000 unimp + 80005c60: 0000 unimp + 80005c62: 0000 unimp + 80005c64: 0000 unimp + 80005c66: 0000 unimp + 80005c68: 0000 unimp + 80005c6a: 0000 unimp + 80005c6c: 0000 unimp + 80005c6e: 0000 unimp + 80005c70: 0000 unimp + 80005c72: 0000 unimp + 80005c74: 0000 unimp + 80005c76: 0000 unimp + 80005c78: 0000 unimp + 80005c7a: 0000 unimp + 80005c7c: 0000 unimp + 80005c7e: 0000 unimp + 80005c80: 0000 unimp + 80005c82: 0000 unimp + 80005c84: 0000 unimp + 80005c86: 0000 unimp + 80005c88: 0000 unimp + 80005c8a: 0000 unimp + 80005c8c: 0000 unimp + 80005c8e: 0000 unimp + 80005c90: 0000 unimp + 80005c92: 0000 unimp + 80005c94: 0000 unimp + 80005c96: 0000 unimp + 80005c98: 0000 unimp + 80005c9a: 0000 unimp + 80005c9c: 0000 unimp + 80005c9e: 0000 unimp + 80005ca0: 0000 unimp + 80005ca2: 0000 unimp + 80005ca4: 0000 unimp + 80005ca6: 0000 unimp + 80005ca8: 0000 unimp + 80005caa: 0000 unimp + 80005cac: 0000 unimp + 80005cae: 0000 unimp + 80005cb0: 0000 unimp + 80005cb2: 0000 unimp + 80005cb4: 0000 unimp + 80005cb6: 0000 unimp + 80005cb8: 0000 unimp + 80005cba: 0000 unimp + 80005cbc: 0000 unimp + 80005cbe: 0000 unimp + 80005cc0: 0000 unimp + 80005cc2: 0000 unimp + 80005cc4: 0000 unimp + 80005cc6: 0000 unimp + 80005cc8: 0000 unimp + 80005cca: 0000 unimp + 80005ccc: 0000 unimp + 80005cce: 0000 unimp + 80005cd0: 0000 unimp + 80005cd2: 0000 unimp + 80005cd4: 0000 unimp + 80005cd6: 0000 unimp + 80005cd8: 0000 unimp + 80005cda: 0000 unimp + 80005cdc: 0000 unimp + 80005cde: 0000 unimp + 80005ce0: 0000 unimp + 80005ce2: 0000 unimp + 80005ce4: 0000 unimp + 80005ce6: 0000 unimp + 80005ce8: 0000 unimp + 80005cea: 0000 unimp + 80005cec: 0000 unimp + 80005cee: 0000 unimp + 80005cf0: 0000 unimp + 80005cf2: 0000 unimp + 80005cf4: 0000 unimp + 80005cf6: 0000 unimp + 80005cf8: 0000 unimp + 80005cfa: 0000 unimp + 80005cfc: 0000 unimp + 80005cfe: 0000 unimp + 80005d00: 0000 unimp + 80005d02: 0000 unimp + 80005d04: 0000 unimp + 80005d06: 0000 unimp + 80005d08: 0000 unimp + 80005d0a: 0000 unimp + 80005d0c: 0000 unimp + 80005d0e: 0000 unimp + 80005d10: 0000 unimp + 80005d12: 0000 unimp + 80005d14: 0000 unimp + 80005d16: 0000 unimp + 80005d18: 0000 unimp + 80005d1a: 0000 unimp + 80005d1c: 0000 unimp + 80005d1e: 0000 unimp + 80005d20: 0000 unimp + 80005d22: 0000 unimp + 80005d24: 0000 unimp + 80005d26: 0000 unimp + 80005d28: 0000 unimp + 80005d2a: 0000 unimp + 80005d2c: 0000 unimp + 80005d2e: 0000 unimp + 80005d30: 0000 unimp + 80005d32: 0000 unimp + 80005d34: 0000 unimp + 80005d36: 0000 unimp + 80005d38: 0000 unimp + 80005d3a: 0000 unimp + 80005d3c: 0000 unimp + 80005d3e: 0000 unimp + 80005d40: 0000 unimp + 80005d42: 0000 unimp + 80005d44: 0000 unimp + 80005d46: 0000 unimp + 80005d48: 0000 unimp + 80005d4a: 0000 unimp + 80005d4c: 0000 unimp + 80005d4e: 0000 unimp + 80005d50: 0000 unimp + 80005d52: 0000 unimp + 80005d54: 0000 unimp + 80005d56: 0000 unimp + 80005d58: 0000 unimp + 80005d5a: 0000 unimp + 80005d5c: 0000 unimp + 80005d5e: 0000 unimp + 80005d60: 0000 unimp + 80005d62: 0000 unimp + 80005d64: 0000 unimp + 80005d66: 0000 unimp + 80005d68: 0000 unimp + 80005d6a: 0000 unimp + 80005d6c: 0000 unimp + 80005d6e: 0000 unimp + 80005d70: 0000 unimp + 80005d72: 0000 unimp + 80005d74: 0000 unimp + 80005d76: 0000 unimp + 80005d78: 0000 unimp + 80005d7a: 0000 unimp + 80005d7c: 0000 unimp + 80005d7e: 0000 unimp + 80005d80: 0000 unimp + 80005d82: 0000 unimp + 80005d84: 0000 unimp + 80005d86: 0000 unimp + 80005d88: 0000 unimp + 80005d8a: 0000 unimp + 80005d8c: 0000 unimp + 80005d8e: 0000 unimp + 80005d90: 0000 unimp + 80005d92: 0000 unimp + 80005d94: 0000 unimp + 80005d96: 0000 unimp + 80005d98: 0000 unimp + 80005d9a: 0000 unimp + 80005d9c: 0000 unimp + 80005d9e: 0000 unimp + 80005da0: 0000 unimp + 80005da2: 0000 unimp + 80005da4: 0000 unimp + 80005da6: 0000 unimp + 80005da8: 0000 unimp + 80005daa: 0000 unimp + 80005dac: 0000 unimp + 80005dae: 0000 unimp + 80005db0: 0000 unimp + 80005db2: 0000 unimp + 80005db4: 0000 unimp + 80005db6: 0000 unimp + 80005db8: 0000 unimp + 80005dba: 0000 unimp + 80005dbc: 0000 unimp + 80005dbe: 0000 unimp + 80005dc0: 0000 unimp + 80005dc2: 0000 unimp + 80005dc4: 0000 unimp + 80005dc6: 0000 unimp + 80005dc8: 0000 unimp + 80005dca: 0000 unimp + 80005dcc: 0000 unimp + 80005dce: 0000 unimp + 80005dd0: 0000 unimp + 80005dd2: 0000 unimp + 80005dd4: 0000 unimp + 80005dd6: 0000 unimp + 80005dd8: 0000 unimp + 80005dda: 0000 unimp + 80005ddc: 0000 unimp + 80005dde: 0000 unimp + 80005de0: 0000 unimp + 80005de2: 0000 unimp + 80005de4: 0000 unimp + 80005de6: 0000 unimp + 80005de8: 0000 unimp + 80005dea: 0000 unimp + 80005dec: 0000 unimp + 80005dee: 0000 unimp + 80005df0: 0000 unimp + 80005df2: 0000 unimp + 80005df4: 0000 unimp + 80005df6: 0000 unimp + 80005df8: 0000 unimp + 80005dfa: 0000 unimp + 80005dfc: 0000 unimp + 80005dfe: 0000 unimp + 80005e00: 0000 unimp + 80005e02: 0000 unimp + 80005e04: 0000 unimp + 80005e06: 0000 unimp + 80005e08: 0000 unimp + 80005e0a: 0000 unimp + 80005e0c: 0000 unimp + 80005e0e: 0000 unimp + 80005e10: 0000 unimp + 80005e12: 0000 unimp + 80005e14: 0000 unimp + 80005e16: 0000 unimp + 80005e18: 0000 unimp + 80005e1a: 0000 unimp + 80005e1c: 0000 unimp + 80005e1e: 0000 unimp + 80005e20: 0000 unimp + 80005e22: 0000 unimp + 80005e24: 0000 unimp + 80005e26: 0000 unimp + 80005e28: 0000 unimp + 80005e2a: 0000 unimp + 80005e2c: 0000 unimp + 80005e2e: 0000 unimp + 80005e30: 0000 unimp + 80005e32: 0000 unimp + 80005e34: 0000 unimp + 80005e36: 0000 unimp + 80005e38: 0000 unimp + 80005e3a: 0000 unimp + 80005e3c: 0000 unimp + 80005e3e: 0000 unimp + 80005e40: 0000 unimp + 80005e42: 0000 unimp + 80005e44: 0000 unimp + 80005e46: 0000 unimp + 80005e48: 0000 unimp + 80005e4a: 0000 unimp + 80005e4c: 0000 unimp + 80005e4e: 0000 unimp + 80005e50: 0000 unimp + 80005e52: 0000 unimp + 80005e54: 0000 unimp + 80005e56: 0000 unimp + 80005e58: 0000 unimp + 80005e5a: 0000 unimp + 80005e5c: 0000 unimp + 80005e5e: 0000 unimp + 80005e60: 0000 unimp + 80005e62: 0000 unimp + 80005e64: 0000 unimp + 80005e66: 0000 unimp + 80005e68: 0000 unimp + 80005e6a: 0000 unimp + 80005e6c: 0000 unimp + 80005e6e: 0000 unimp + 80005e70: 0000 unimp + 80005e72: 0000 unimp + 80005e74: 0000 unimp + 80005e76: 0000 unimp + 80005e78: 0000 unimp + 80005e7a: 0000 unimp + 80005e7c: 0000 unimp + 80005e7e: 0000 unimp + 80005e80: 0000 unimp + 80005e82: 0000 unimp + 80005e84: 0000 unimp + 80005e86: 0000 unimp + 80005e88: 0000 unimp + 80005e8a: 0000 unimp + 80005e8c: 0000 unimp + 80005e8e: 0000 unimp + 80005e90: 0000 unimp + 80005e92: 0000 unimp + 80005e94: 0000 unimp + 80005e96: 0000 unimp + 80005e98: 0000 unimp + 80005e9a: 0000 unimp + 80005e9c: 0000 unimp + 80005e9e: 0000 unimp + 80005ea0: 0000 unimp + 80005ea2: 0000 unimp + 80005ea4: 0000 unimp + 80005ea6: 0000 unimp + 80005ea8: 0000 unimp + 80005eaa: 0000 unimp + 80005eac: 0000 unimp + 80005eae: 0000 unimp + 80005eb0: 0000 unimp + 80005eb2: 0000 unimp + 80005eb4: 0000 unimp + 80005eb6: 0000 unimp + 80005eb8: 0000 unimp + 80005eba: 0000 unimp + 80005ebc: 0000 unimp + 80005ebe: 0000 unimp + 80005ec0: 0000 unimp + 80005ec2: 0000 unimp + 80005ec4: 0000 unimp + 80005ec6: 0000 unimp + 80005ec8: 0000 unimp + 80005eca: 0000 unimp + 80005ecc: 0000 unimp + 80005ece: 0000 unimp + 80005ed0: 0000 unimp + 80005ed2: 0000 unimp + 80005ed4: 0000 unimp + 80005ed6: 0000 unimp + 80005ed8: 0000 unimp + 80005eda: 0000 unimp + 80005edc: 0000 unimp + 80005ede: 0000 unimp + 80005ee0: 0000 unimp + 80005ee2: 0000 unimp + 80005ee4: 0000 unimp + 80005ee6: 0000 unimp + 80005ee8: 0000 unimp + 80005eea: 0000 unimp + 80005eec: 0000 unimp + 80005eee: 0000 unimp + 80005ef0: 0000 unimp + 80005ef2: 0000 unimp + 80005ef4: 0000 unimp + 80005ef6: 0000 unimp + 80005ef8: 0000 unimp + 80005efa: 0000 unimp + 80005efc: 0000 unimp + 80005efe: 0000 unimp + 80005f00: 0000 unimp + 80005f02: 0000 unimp + 80005f04: 0000 unimp + 80005f06: 0000 unimp + 80005f08: 0000 unimp + 80005f0a: 0000 unimp + 80005f0c: 0000 unimp + 80005f0e: 0000 unimp + 80005f10: 0000 unimp + 80005f12: 0000 unimp + 80005f14: 0000 unimp + 80005f16: 0000 unimp + 80005f18: 0000 unimp + 80005f1a: 0000 unimp + 80005f1c: 0000 unimp + 80005f1e: 0000 unimp + 80005f20: 0000 unimp + 80005f22: 0000 unimp + 80005f24: 0000 unimp + 80005f26: 0000 unimp + 80005f28: 0000 unimp + 80005f2a: 0000 unimp + 80005f2c: 0000 unimp + 80005f2e: 0000 unimp + 80005f30: 0000 unimp + 80005f32: 0000 unimp + 80005f34: 0000 unimp + 80005f36: 0000 unimp + 80005f38: 0000 unimp + 80005f3a: 0000 unimp + 80005f3c: 0000 unimp + 80005f3e: 0000 unimp + 80005f40: 0000 unimp + 80005f42: 0000 unimp + 80005f44: 0000 unimp + 80005f46: 0000 unimp + 80005f48: 0000 unimp + 80005f4a: 0000 unimp + 80005f4c: 0000 unimp + 80005f4e: 0000 unimp + 80005f50: 0000 unimp + 80005f52: 0000 unimp + 80005f54: 0000 unimp + 80005f56: 0000 unimp + 80005f58: 0000 unimp + 80005f5a: 0000 unimp + 80005f5c: 0000 unimp + 80005f5e: 0000 unimp + 80005f60: 0000 unimp + 80005f62: 0000 unimp + 80005f64: 0000 unimp + 80005f66: 0000 unimp + 80005f68: 0000 unimp + 80005f6a: 0000 unimp + 80005f6c: 0000 unimp + 80005f6e: 0000 unimp + 80005f70: 0000 unimp + 80005f72: 0000 unimp + 80005f74: 0000 unimp + 80005f76: 0000 unimp + 80005f78: 0000 unimp + 80005f7a: 0000 unimp + 80005f7c: 0000 unimp + 80005f7e: 0000 unimp + 80005f80: 0000 unimp + 80005f82: 0000 unimp + 80005f84: 0000 unimp + 80005f86: 0000 unimp + 80005f88: 0000 unimp + 80005f8a: 0000 unimp + 80005f8c: 0000 unimp + 80005f8e: 0000 unimp + 80005f90: 0000 unimp + 80005f92: 0000 unimp + 80005f94: 0000 unimp + 80005f96: 0000 unimp + 80005f98: 0000 unimp + 80005f9a: 0000 unimp + 80005f9c: 0000 unimp + 80005f9e: 0000 unimp + 80005fa0: 0000 unimp + 80005fa2: 0000 unimp + 80005fa4: 0000 unimp + 80005fa6: 0000 unimp + 80005fa8: 0000 unimp + 80005faa: 0000 unimp + 80005fac: 0000 unimp + 80005fae: 0000 unimp + 80005fb0: 0000 unimp + 80005fb2: 0000 unimp + 80005fb4: 0000 unimp + 80005fb6: 0000 unimp + 80005fb8: 0000 unimp + 80005fba: 0000 unimp + 80005fbc: 0000 unimp + 80005fbe: 0000 unimp + 80005fc0: 0000 unimp + 80005fc2: 0000 unimp + 80005fc4: 0000 unimp + 80005fc6: 0000 unimp diff --git a/test/riscv/tests/rv64uc-v-rvc.elf b/test/riscv/tests/rv64uc-v-rvc.elf new file mode 100644 index 00000000..89152b9c Binary files /dev/null and b/test/riscv/tests/rv64uc-v-rvc.elf differ diff --git a/test/riscv/tests/rv64ui-p-add.elf b/test/riscv/tests/rv64ui-p-add.elf old mode 100755 new mode 100644 index cd560ee7..711d4fc8 Binary files a/test/riscv/tests/rv64ui-p-add.elf and b/test/riscv/tests/rv64ui-p-add.elf differ diff --git a/test/riscv/tests/rv64ui-p-addi.elf b/test/riscv/tests/rv64ui-p-addi.elf old mode 100755 new mode 100644 index 3cbc838d..511253ab Binary files a/test/riscv/tests/rv64ui-p-addi.elf and b/test/riscv/tests/rv64ui-p-addi.elf differ diff --git a/test/riscv/tests/rv64ui-p-addiw.elf b/test/riscv/tests/rv64ui-p-addiw.elf old mode 100755 new mode 100644 index adee4ac2..c58d5215 Binary files a/test/riscv/tests/rv64ui-p-addiw.elf and b/test/riscv/tests/rv64ui-p-addiw.elf differ diff --git a/test/riscv/tests/rv64ui-p-addw.elf b/test/riscv/tests/rv64ui-p-addw.elf old mode 100755 new mode 100644 index b36a71c1..b4cc4910 Binary files a/test/riscv/tests/rv64ui-p-addw.elf and b/test/riscv/tests/rv64ui-p-addw.elf differ diff --git a/test/riscv/tests/rv64ui-p-and.elf b/test/riscv/tests/rv64ui-p-and.elf old mode 100755 new mode 100644 index 66d59699..6450bbc4 Binary files a/test/riscv/tests/rv64ui-p-and.elf and b/test/riscv/tests/rv64ui-p-and.elf differ diff --git a/test/riscv/tests/rv64ui-p-andi.elf b/test/riscv/tests/rv64ui-p-andi.elf old mode 100755 new mode 100644 index 2886a877..26396d91 Binary files a/test/riscv/tests/rv64ui-p-andi.elf and b/test/riscv/tests/rv64ui-p-andi.elf differ diff --git a/test/riscv/tests/rv64ui-p-auipc.elf b/test/riscv/tests/rv64ui-p-auipc.elf old mode 100755 new mode 100644 index 4ef544d1..841136eb Binary files a/test/riscv/tests/rv64ui-p-auipc.elf and b/test/riscv/tests/rv64ui-p-auipc.elf differ diff --git a/test/riscv/tests/rv64ui-p-beq.elf b/test/riscv/tests/rv64ui-p-beq.elf old mode 100755 new mode 100644 index 38481b96..74d63921 Binary files a/test/riscv/tests/rv64ui-p-beq.elf and b/test/riscv/tests/rv64ui-p-beq.elf differ diff --git a/test/riscv/tests/rv64ui-p-bge.elf b/test/riscv/tests/rv64ui-p-bge.elf old mode 100755 new mode 100644 index 31d9ecd4..6a5c2ef2 Binary files a/test/riscv/tests/rv64ui-p-bge.elf and b/test/riscv/tests/rv64ui-p-bge.elf differ diff --git a/test/riscv/tests/rv64ui-p-bgeu.elf b/test/riscv/tests/rv64ui-p-bgeu.elf old mode 100755 new mode 100644 index a7e14bac..a1ae7fea Binary files a/test/riscv/tests/rv64ui-p-bgeu.elf and b/test/riscv/tests/rv64ui-p-bgeu.elf differ diff --git a/test/riscv/tests/rv64ui-p-blt.elf b/test/riscv/tests/rv64ui-p-blt.elf old mode 100755 new mode 100644 index eec6ce60..53f06fa5 Binary files a/test/riscv/tests/rv64ui-p-blt.elf and b/test/riscv/tests/rv64ui-p-blt.elf differ diff --git a/test/riscv/tests/rv64ui-p-bltu.elf b/test/riscv/tests/rv64ui-p-bltu.elf old mode 100755 new mode 100644 index 05ee4bec..a5d06391 Binary files a/test/riscv/tests/rv64ui-p-bltu.elf and b/test/riscv/tests/rv64ui-p-bltu.elf differ diff --git a/test/riscv/tests/rv64ui-p-bne.elf b/test/riscv/tests/rv64ui-p-bne.elf old mode 100755 new mode 100644 index f44e9132..9a83bec4 Binary files a/test/riscv/tests/rv64ui-p-bne.elf and b/test/riscv/tests/rv64ui-p-bne.elf differ diff --git a/test/riscv/tests/rv64ui-p-fence_i.elf b/test/riscv/tests/rv64ui-p-fence_i.elf old mode 100755 new mode 100644 index da16800e..9f8d7726 Binary files a/test/riscv/tests/rv64ui-p-fence_i.elf and b/test/riscv/tests/rv64ui-p-fence_i.elf differ diff --git a/test/riscv/tests/rv64ui-p-jal.elf b/test/riscv/tests/rv64ui-p-jal.elf old mode 100755 new mode 100644 index a6a2933f..3741bbb7 Binary files a/test/riscv/tests/rv64ui-p-jal.elf and b/test/riscv/tests/rv64ui-p-jal.elf differ diff --git a/test/riscv/tests/rv64ui-p-jalr.elf b/test/riscv/tests/rv64ui-p-jalr.elf old mode 100755 new mode 100644 index 709778a9..9682d86f Binary files a/test/riscv/tests/rv64ui-p-jalr.elf and b/test/riscv/tests/rv64ui-p-jalr.elf differ diff --git a/test/riscv/tests/rv64ui-p-lb.elf b/test/riscv/tests/rv64ui-p-lb.elf old mode 100755 new mode 100644 index c1723c06..7e0a8a40 Binary files a/test/riscv/tests/rv64ui-p-lb.elf and b/test/riscv/tests/rv64ui-p-lb.elf differ diff --git a/test/riscv/tests/rv64ui-p-lbu.elf b/test/riscv/tests/rv64ui-p-lbu.elf old mode 100755 new mode 100644 index e14ea798..14f1586b Binary files a/test/riscv/tests/rv64ui-p-lbu.elf and b/test/riscv/tests/rv64ui-p-lbu.elf differ diff --git a/test/riscv/tests/rv64ui-p-ld.elf b/test/riscv/tests/rv64ui-p-ld.elf old mode 100755 new mode 100644 index 5aa623b0..df2a7349 Binary files a/test/riscv/tests/rv64ui-p-ld.elf and b/test/riscv/tests/rv64ui-p-ld.elf differ diff --git a/test/riscv/tests/rv64ui-p-lh.elf b/test/riscv/tests/rv64ui-p-lh.elf old mode 100755 new mode 100644 index 30db6615..fcff462f Binary files a/test/riscv/tests/rv64ui-p-lh.elf and b/test/riscv/tests/rv64ui-p-lh.elf differ diff --git a/test/riscv/tests/rv64ui-p-lhu.elf b/test/riscv/tests/rv64ui-p-lhu.elf old mode 100755 new mode 100644 index bae5bc05..78bb0e92 Binary files a/test/riscv/tests/rv64ui-p-lhu.elf and b/test/riscv/tests/rv64ui-p-lhu.elf differ diff --git a/test/riscv/tests/rv64ui-p-lui.elf b/test/riscv/tests/rv64ui-p-lui.elf old mode 100755 new mode 100644 index 4bf8d97b..67dfe10e Binary files a/test/riscv/tests/rv64ui-p-lui.elf and b/test/riscv/tests/rv64ui-p-lui.elf differ diff --git a/test/riscv/tests/rv64ui-p-lw.elf b/test/riscv/tests/rv64ui-p-lw.elf old mode 100755 new mode 100644 index d371f1c9..714ae850 Binary files a/test/riscv/tests/rv64ui-p-lw.elf and b/test/riscv/tests/rv64ui-p-lw.elf differ diff --git a/test/riscv/tests/rv64ui-p-lwu.elf b/test/riscv/tests/rv64ui-p-lwu.elf old mode 100755 new mode 100644 index c7fedede..de88bd29 Binary files a/test/riscv/tests/rv64ui-p-lwu.elf and b/test/riscv/tests/rv64ui-p-lwu.elf differ diff --git a/test/riscv/tests/rv64ui-p-or.elf b/test/riscv/tests/rv64ui-p-or.elf old mode 100755 new mode 100644 index e180a180..fbd5299f Binary files a/test/riscv/tests/rv64ui-p-or.elf and b/test/riscv/tests/rv64ui-p-or.elf differ diff --git a/test/riscv/tests/rv64ui-p-ori.elf b/test/riscv/tests/rv64ui-p-ori.elf old mode 100755 new mode 100644 index c1f8f066..81868c2b Binary files a/test/riscv/tests/rv64ui-p-ori.elf and b/test/riscv/tests/rv64ui-p-ori.elf differ diff --git a/test/riscv/tests/rv64ui-p-sb.elf b/test/riscv/tests/rv64ui-p-sb.elf old mode 100755 new mode 100644 index 85999d6b..0f672c3d Binary files a/test/riscv/tests/rv64ui-p-sb.elf and b/test/riscv/tests/rv64ui-p-sb.elf differ diff --git a/test/riscv/tests/rv64ui-p-sd.elf b/test/riscv/tests/rv64ui-p-sd.elf old mode 100755 new mode 100644 index f6801dcf..8ebb0db0 Binary files a/test/riscv/tests/rv64ui-p-sd.elf and b/test/riscv/tests/rv64ui-p-sd.elf differ diff --git a/test/riscv/tests/rv64ui-p-sh.elf b/test/riscv/tests/rv64ui-p-sh.elf old mode 100755 new mode 100644 index 118eeb3f..5ba031e4 Binary files a/test/riscv/tests/rv64ui-p-sh.elf and b/test/riscv/tests/rv64ui-p-sh.elf differ diff --git a/test/riscv/tests/rv64ui-p-simple.elf b/test/riscv/tests/rv64ui-p-simple.elf old mode 100755 new mode 100644 index 541353b3..bc8cb92d Binary files a/test/riscv/tests/rv64ui-p-simple.elf and b/test/riscv/tests/rv64ui-p-simple.elf differ diff --git a/test/riscv/tests/rv64ui-p-sll.elf b/test/riscv/tests/rv64ui-p-sll.elf old mode 100755 new mode 100644 index ad48a8ea..75144abf Binary files a/test/riscv/tests/rv64ui-p-sll.elf and b/test/riscv/tests/rv64ui-p-sll.elf differ diff --git a/test/riscv/tests/rv64ui-p-slli.dump b/test/riscv/tests/rv64ui-p-slli.dump index de783cf8..f04acaad 100644 --- a/test/riscv/tests/rv64ui-p-slli.dump +++ b/test/riscv/tests/rv64ui-p-slli.dump @@ -82,28 +82,28 @@ Disassembly of section .text.init: 80000100: 00009f13 slli t5,ra,0x0 80000104: 00100e93 li t4,1 80000108: 00200193 li gp,2 - 8000010c: 2fdf1a63 bne t5,t4,80000400 + 8000010c: 2fdf1463 bne t5,t4,800003f4 0000000080000110 : 80000110: 00100093 li ra,1 80000114: 00109f13 slli t5,ra,0x1 80000118: 00200e93 li t4,2 8000011c: 00300193 li gp,3 - 80000120: 2fdf1063 bne t5,t4,80000400 + 80000120: 2ddf1a63 bne t5,t4,800003f4 0000000080000124 : 80000124: 00100093 li ra,1 80000128: 00709f13 slli t5,ra,0x7 8000012c: 08000e93 li t4,128 80000130: 00400193 li gp,4 - 80000134: 2ddf1663 bne t5,t4,80000400 + 80000134: 2ddf1063 bne t5,t4,800003f4 0000000080000138 : 80000138: 00100093 li ra,1 8000013c: 00e09f13 slli t5,ra,0xe 80000140: 00004eb7 lui t4,0x4 80000144: 00500193 li gp,5 - 80000148: 2bdf1c63 bne t5,t4,80000400 + 80000148: 2bdf1663 bne t5,t4,800003f4 000000008000014c : 8000014c: 00100093 li ra,1 @@ -111,42 +111,42 @@ Disassembly of section .text.init: 80000154: 00100e9b addiw t4,zero,1 80000158: 01fe9e93 slli t4,t4,0x1f 8000015c: 00600193 li gp,6 - 80000160: 2bdf1063 bne t5,t4,80000400 + 80000160: 29df1a63 bne t5,t4,800003f4 0000000080000164 : 80000164: fff00093 li ra,-1 80000168: 00009f13 slli t5,ra,0x0 8000016c: fff00e93 li t4,-1 80000170: 00700193 li gp,7 - 80000174: 29df1663 bne t5,t4,80000400 + 80000174: 29df1063 bne t5,t4,800003f4 0000000080000178 : 80000178: fff00093 li ra,-1 8000017c: 00109f13 slli t5,ra,0x1 80000180: ffe00e93 li t4,-2 80000184: 00800193 li gp,8 - 80000188: 27df1c63 bne t5,t4,80000400 + 80000188: 27df1663 bne t5,t4,800003f4 000000008000018c : 8000018c: fff00093 li ra,-1 80000190: 00709f13 slli t5,ra,0x7 80000194: f8000e93 li t4,-128 80000198: 00900193 li gp,9 - 8000019c: 27df1263 bne t5,t4,80000400 + 8000019c: 25df1c63 bne t5,t4,800003f4 00000000800001a0 : 800001a0: fff00093 li ra,-1 800001a4: 00e09f13 slli t5,ra,0xe 800001a8: ffffceb7 lui t4,0xffffc 800001ac: 00a00193 li gp,10 - 800001b0: 25df1863 bne t5,t4,80000400 + 800001b0: 25df1263 bne t5,t4,800003f4 00000000800001b4 : 800001b4: fff00093 li ra,-1 800001b8: 01f09f13 slli t5,ra,0x1f 800001bc: 80000eb7 lui t4,0x80000 800001c0: 00b00193 li gp,11 - 800001c4: 23df1e63 bne t5,t4,80000400 + 800001c4: 23df1863 bne t5,t4,800003f4 00000000800001c8 : 800001c8: 212120b7 lui ra,0x21212 @@ -155,7 +155,7 @@ Disassembly of section .text.init: 800001d4: 21212eb7 lui t4,0x21212 800001d8: 121e8e9b addiw t4,t4,289 800001dc: 00c00193 li gp,12 - 800001e0: 23df1063 bne t5,t4,80000400 + 800001e0: 21df1a63 bne t5,t4,800003f4 00000000800001e4 : 800001e4: 212120b7 lui ra,0x21212 @@ -164,7 +164,7 @@ Disassembly of section .text.init: 800001f0: 42424eb7 lui t4,0x42424 800001f4: 242e8e9b addiw t4,t4,578 800001f8: 00d00193 li gp,13 - 800001fc: 21df1263 bne t5,t4,80000400 + 800001fc: 1fdf1c63 bne t5,t4,800003f4 0000000080000200 : 80000200: 212120b7 lui ra,0x21212 @@ -175,7 +175,7 @@ Disassembly of section .text.init: 80000214: 00ce9e93 slli t4,t4,0xc 80000218: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> 8000021c: 00e00193 li gp,14 - 80000220: 1fdf1063 bne t5,t4,80000400 + 80000220: 1ddf1a63 bne t5,t4,800003f4 0000000080000224 : 80000224: 212120b7 lui ra,0x21212 @@ -185,7 +185,7 @@ Disassembly of section .text.init: 80000234: 121e8e9b addiw t4,t4,289 80000238: 00ee9e93 slli t4,t4,0xe 8000023c: 00f00193 li gp,15 - 80000240: 1ddf1063 bne t5,t4,80000400 + 80000240: 1bdf1a63 bne t5,t4,800003f4 0000000080000244 : 80000244: 212120b7 lui ra,0x21212 @@ -195,147 +195,150 @@ Disassembly of section .text.init: 80000254: 121e8e9b addiw t4,t4,289 80000258: 01fe9e93 slli t4,t4,0x1f 8000025c: 01000193 li gp,16 - 80000260: 1bdf1063 bne t5,t4,80000400 + 80000260: 19df1a63 bne t5,t4,800003f4 0000000080000264 : 80000264: 00100093 li ra,1 - 80000268: 03f00113 li sp,63 - 8000026c: 00209f33 sll t5,ra,sp - 80000270: fff00e9b addiw t4,zero,-1 - 80000274: 03fe9e93 slli t4,t4,0x3f - 80000278: 03200193 li gp,50 - 8000027c: 19df1263 bne t5,t4,80000400 - -0000000080000280 : - 80000280: fff00093 li ra,-1 - 80000284: 02700113 li sp,39 - 80000288: 00209f33 sll t5,ra,sp - 8000028c: fff00e9b addiw t4,zero,-1 - 80000290: 027e9e93 slli t4,t4,0x27 - 80000294: 03300193 li gp,51 - 80000298: 17df1463 bne t5,t4,80000400 - -000000008000029c : - 8000029c: 212120b7 lui ra,0x21212 - 800002a0: 1210809b addiw ra,ra,289 - 800002a4: 02b00113 li sp,43 - 800002a8: 00209f33 sll t5,ra,sp - 800002ac: 00012eb7 lui t4,0x12 - 800002b0: 121e8e9b addiw t4,t4,289 - 800002b4: 02be9e93 slli t4,t4,0x2b - 800002b8: 03400193 li gp,52 - 800002bc: 15df1263 bne t5,t4,80000400 - -00000000800002c0 : - 800002c0: 00100093 li ra,1 - 800002c4: 00709093 slli ra,ra,0x7 - 800002c8: 08000e93 li t4,128 - 800002cc: 01100193 li gp,17 - 800002d0: 13d09863 bne ra,t4,80000400 - -00000000800002d4 : - 800002d4: 00000213 li tp,0 - 800002d8: 00100093 li ra,1 - 800002dc: 00709f13 slli t5,ra,0x7 - 800002e0: 000f0313 mv t1,t5 - 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e8: 00200293 li t0,2 - 800002ec: fe5216e3 bne tp,t0,800002d8 - 800002f0: 08000e93 li t4,128 - 800002f4: 01200193 li gp,18 - 800002f8: 11d31463 bne t1,t4,80000400 - -00000000800002fc : - 800002fc: 00000213 li tp,0 - 80000300: 00100093 li ra,1 - 80000304: 00e09f13 slli t5,ra,0xe - 80000308: 00000013 nop - 8000030c: 000f0313 mv t1,t5 - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fe5214e3 bne tp,t0,80000300 - 8000031c: 00004eb7 lui t4,0x4 - 80000320: 01300193 li gp,19 - 80000324: 0dd31e63 bne t1,t4,80000400 - -0000000080000328 : - 80000328: 00000213 li tp,0 - 8000032c: 00100093 li ra,1 - 80000330: 01f09f13 slli t5,ra,0x1f - 80000334: 00000013 nop - 80000338: 00000013 nop - 8000033c: 000f0313 mv t1,t5 - 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000344: 00200293 li t0,2 - 80000348: fe5212e3 bne tp,t0,8000032c - 8000034c: 00100e9b addiw t4,zero,1 - 80000350: 01fe9e93 slli t4,t4,0x1f - 80000354: 01400193 li gp,20 - 80000358: 0bd31463 bne t1,t4,80000400 - -000000008000035c : - 8000035c: 00000213 li tp,0 - 80000360: 00100093 li ra,1 - 80000364: 00709f13 slli t5,ra,0x7 - 80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000036c: 00200293 li t0,2 - 80000370: fe5218e3 bne tp,t0,80000360 - 80000374: 08000e93 li t4,128 - 80000378: 01500193 li gp,21 - 8000037c: 09df1263 bne t5,t4,80000400 - -0000000080000380 : - 80000380: 00000213 li tp,0 - 80000384: 00100093 li ra,1 - 80000388: 00000013 nop - 8000038c: 00e09f13 slli t5,ra,0xe - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fe5216e3 bne tp,t0,80000384 - 8000039c: 00004eb7 lui t4,0x4 - 800003a0: 01600193 li gp,22 - 800003a4: 05df1e63 bne t5,t4,80000400 - -00000000800003a8 : - 800003a8: 00000213 li tp,0 - 800003ac: 00100093 li ra,1 - 800003b0: 00000013 nop - 800003b4: 00000013 nop - 800003b8: 01f09f13 slli t5,ra,0x1f - 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c0: 00200293 li t0,2 - 800003c4: fe5214e3 bne tp,t0,800003ac - 800003c8: 00100e9b addiw t4,zero,1 - 800003cc: 01fe9e93 slli t4,t4,0x1f - 800003d0: 01700193 li gp,23 - 800003d4: 03df1663 bne t5,t4,80000400 - -00000000800003d8 : - 800003d8: 01f01093 slli ra,zero,0x1f - 800003dc: 00000e93 li t4,0 - 800003e0: 01800193 li gp,24 - 800003e4: 01d09e63 bne ra,t4,80000400 - -00000000800003e8 : - 800003e8: 02100093 li ra,33 - 800003ec: 01409013 slli zero,ra,0x14 - 800003f0: 00000e93 li t4,0 - 800003f4: 01900193 li gp,25 - 800003f8: 01d01463 bne zero,t4,80000400 - 800003fc: 00301c63 bne zero,gp,80000414 - -0000000080000400 : - 80000400: 0ff0000f fence - 80000404: 00018063 beqz gp,80000404 - 80000408: 00119193 slli gp,gp,0x1 - 8000040c: 0011e193 ori gp,gp,1 + 80000268: 03f09f13 slli t5,ra,0x3f + 8000026c: fff00e9b addiw t4,zero,-1 + 80000270: 03fe9e93 slli t4,t4,0x3f + 80000274: 03200193 li gp,50 + 80000278: 17df1e63 bne t5,t4,800003f4 + +000000008000027c : + 8000027c: fff00093 li ra,-1 + 80000280: 02709f13 slli t5,ra,0x27 + 80000284: fff00e9b addiw t4,zero,-1 + 80000288: 027e9e93 slli t4,t4,0x27 + 8000028c: 03300193 li gp,51 + 80000290: 17df1263 bne t5,t4,800003f4 + +0000000080000294 : + 80000294: 212120b7 lui ra,0x21212 + 80000298: 1210809b addiw ra,ra,289 + 8000029c: 02b09f13 slli t5,ra,0x2b + 800002a0: 00012eb7 lui t4,0x12 + 800002a4: 121e8e9b addiw t4,t4,289 + 800002a8: 02be9e93 slli t4,t4,0x2b + 800002ac: 03400193 li gp,52 + 800002b0: 15df1263 bne t5,t4,800003f4 + +00000000800002b4 : + 800002b4: 00100093 li ra,1 + 800002b8: 00709093 slli ra,ra,0x7 + 800002bc: 08000e93 li t4,128 + 800002c0: 01100193 li gp,17 + 800002c4: 13d09863 bne ra,t4,800003f4 + +00000000800002c8 : + 800002c8: 00000213 li tp,0 + 800002cc: 00100093 li ra,1 + 800002d0: 00709f13 slli t5,ra,0x7 + 800002d4: 000f0313 mv t1,t5 + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5216e3 bne tp,t0,800002cc + 800002e4: 08000e93 li t4,128 + 800002e8: 01200193 li gp,18 + 800002ec: 11d31463 bne t1,t4,800003f4 + +00000000800002f0 : + 800002f0: 00000213 li tp,0 + 800002f4: 00100093 li ra,1 + 800002f8: 00e09f13 slli t5,ra,0xe + 800002fc: 00000013 nop + 80000300: 000f0313 mv t1,t5 + 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000308: 00200293 li t0,2 + 8000030c: fe5214e3 bne tp,t0,800002f4 + 80000310: 00004eb7 lui t4,0x4 + 80000314: 01300193 li gp,19 + 80000318: 0dd31e63 bne t1,t4,800003f4 + +000000008000031c : + 8000031c: 00000213 li tp,0 + 80000320: 00100093 li ra,1 + 80000324: 01f09f13 slli t5,ra,0x1f + 80000328: 00000013 nop + 8000032c: 00000013 nop + 80000330: 000f0313 mv t1,t5 + 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000338: 00200293 li t0,2 + 8000033c: fe5212e3 bne tp,t0,80000320 + 80000340: 00100e9b addiw t4,zero,1 + 80000344: 01fe9e93 slli t4,t4,0x1f + 80000348: 01400193 li gp,20 + 8000034c: 0bd31463 bne t1,t4,800003f4 + +0000000080000350 : + 80000350: 00000213 li tp,0 + 80000354: 00100093 li ra,1 + 80000358: 00709f13 slli t5,ra,0x7 + 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000360: 00200293 li t0,2 + 80000364: fe5218e3 bne tp,t0,80000354 + 80000368: 08000e93 li t4,128 + 8000036c: 01500193 li gp,21 + 80000370: 09df1263 bne t5,t4,800003f4 + +0000000080000374 : + 80000374: 00000213 li tp,0 + 80000378: 00100093 li ra,1 + 8000037c: 00000013 nop + 80000380: 00e09f13 slli t5,ra,0xe + 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000388: 00200293 li t0,2 + 8000038c: fe5216e3 bne tp,t0,80000378 + 80000390: 00004eb7 lui t4,0x4 + 80000394: 01600193 li gp,22 + 80000398: 05df1e63 bne t5,t4,800003f4 + +000000008000039c : + 8000039c: 00000213 li tp,0 + 800003a0: 00100093 li ra,1 + 800003a4: 00000013 nop + 800003a8: 00000013 nop + 800003ac: 01f09f13 slli t5,ra,0x1f + 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b4: 00200293 li t0,2 + 800003b8: fe5214e3 bne tp,t0,800003a0 + 800003bc: 00100e9b addiw t4,zero,1 + 800003c0: 01fe9e93 slli t4,t4,0x1f + 800003c4: 01700193 li gp,23 + 800003c8: 03df1663 bne t5,t4,800003f4 + +00000000800003cc : + 800003cc: 01f01093 slli ra,zero,0x1f + 800003d0: 00000e93 li t4,0 + 800003d4: 01800193 li gp,24 + 800003d8: 01d09e63 bne ra,t4,800003f4 + +00000000800003dc : + 800003dc: 02100093 li ra,33 + 800003e0: 01409013 slli zero,ra,0x14 + 800003e4: 00000e93 li t4,0 + 800003e8: 01900193 li gp,25 + 800003ec: 01d01463 bne zero,t4,800003f4 + 800003f0: 00301c63 bne zero,gp,80000408 + +00000000800003f4 : + 800003f4: 0ff0000f fence + 800003f8: 00018063 beqz gp,800003f8 + 800003fc: 00119193 slli gp,gp,0x1 + 80000400: 0011e193 ori gp,gp,1 + 80000404: 00000073 ecall + +0000000080000408 : + 80000408: 0ff0000f fence + 8000040c: 00100193 li gp,1 80000410: 00000073 ecall - -0000000080000414 : - 80000414: 0ff0000f fence - 80000418: 00100193 li gp,1 - 8000041c: 00000073 ecall - 80000420: c0001073 unimp + 80000414: c0001073 unimp + 80000418: 0000 unimp + 8000041a: 0000 unimp + 8000041c: 0000 unimp + 8000041e: 0000 unimp + 80000420: 0000 unimp + 80000422: 0000 unimp 80000424: 0000 unimp 80000426: 0000 unimp 80000428: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slli.elf b/test/riscv/tests/rv64ui-p-slli.elf old mode 100755 new mode 100644 index 12c898f3..5214f29b Binary files a/test/riscv/tests/rv64ui-p-slli.elf and b/test/riscv/tests/rv64ui-p-slli.elf differ diff --git a/test/riscv/tests/rv64ui-p-slliw.elf b/test/riscv/tests/rv64ui-p-slliw.elf old mode 100755 new mode 100644 index b8046e69..556a77e0 Binary files a/test/riscv/tests/rv64ui-p-slliw.elf and b/test/riscv/tests/rv64ui-p-slliw.elf differ diff --git a/test/riscv/tests/rv64ui-p-sllw.elf b/test/riscv/tests/rv64ui-p-sllw.elf old mode 100755 new mode 100644 index b722e66c..4a1c421d Binary files a/test/riscv/tests/rv64ui-p-sllw.elf and b/test/riscv/tests/rv64ui-p-sllw.elf differ diff --git a/test/riscv/tests/rv64ui-p-slt.elf b/test/riscv/tests/rv64ui-p-slt.elf old mode 100755 new mode 100644 index d5e3ee14..eef5e47c Binary files a/test/riscv/tests/rv64ui-p-slt.elf and b/test/riscv/tests/rv64ui-p-slt.elf differ diff --git a/test/riscv/tests/rv64ui-p-slti.elf b/test/riscv/tests/rv64ui-p-slti.elf old mode 100755 new mode 100644 index 3dbb9dcf..190f81fd Binary files a/test/riscv/tests/rv64ui-p-slti.elf and b/test/riscv/tests/rv64ui-p-slti.elf differ diff --git a/test/riscv/tests/rv64ui-p-sltiu.elf b/test/riscv/tests/rv64ui-p-sltiu.elf old mode 100755 new mode 100644 index 9eb7628a..8347ab89 Binary files a/test/riscv/tests/rv64ui-p-sltiu.elf and b/test/riscv/tests/rv64ui-p-sltiu.elf differ diff --git a/test/riscv/tests/rv64ui-p-sltu.elf b/test/riscv/tests/rv64ui-p-sltu.elf old mode 100755 new mode 100644 index 2c63f0bd..a1ef113c Binary files a/test/riscv/tests/rv64ui-p-sltu.elf and b/test/riscv/tests/rv64ui-p-sltu.elf differ diff --git a/test/riscv/tests/rv64ui-p-sra.elf b/test/riscv/tests/rv64ui-p-sra.elf old mode 100755 new mode 100644 index 9ed528bd..f03501d4 Binary files a/test/riscv/tests/rv64ui-p-sra.elf and b/test/riscv/tests/rv64ui-p-sra.elf differ diff --git a/test/riscv/tests/rv64ui-p-srai.elf b/test/riscv/tests/rv64ui-p-srai.elf old mode 100755 new mode 100644 index 4ffa0b72..c670ee92 Binary files a/test/riscv/tests/rv64ui-p-srai.elf and b/test/riscv/tests/rv64ui-p-srai.elf differ diff --git a/test/riscv/tests/rv64ui-p-sraiw.elf b/test/riscv/tests/rv64ui-p-sraiw.elf old mode 100755 new mode 100644 index 34dfe773..e4cab284 Binary files a/test/riscv/tests/rv64ui-p-sraiw.elf and b/test/riscv/tests/rv64ui-p-sraiw.elf differ diff --git a/test/riscv/tests/rv64ui-p-sraw.elf b/test/riscv/tests/rv64ui-p-sraw.elf old mode 100755 new mode 100644 index ec7baca6..40d2f2c4 Binary files a/test/riscv/tests/rv64ui-p-sraw.elf and b/test/riscv/tests/rv64ui-p-sraw.elf differ diff --git a/test/riscv/tests/rv64ui-p-srl.elf b/test/riscv/tests/rv64ui-p-srl.elf old mode 100755 new mode 100644 index 2da2e0ba..5abd6a01 Binary files a/test/riscv/tests/rv64ui-p-srl.elf and b/test/riscv/tests/rv64ui-p-srl.elf differ diff --git a/test/riscv/tests/rv64ui-p-srli.elf b/test/riscv/tests/rv64ui-p-srli.elf old mode 100755 new mode 100644 index 73d7db18..6e2f7948 Binary files a/test/riscv/tests/rv64ui-p-srli.elf and b/test/riscv/tests/rv64ui-p-srli.elf differ diff --git a/test/riscv/tests/rv64ui-p-srliw.elf b/test/riscv/tests/rv64ui-p-srliw.elf old mode 100755 new mode 100644 index 2dc12254..70758a3c Binary files a/test/riscv/tests/rv64ui-p-srliw.elf and b/test/riscv/tests/rv64ui-p-srliw.elf differ diff --git a/test/riscv/tests/rv64ui-p-srlw.elf b/test/riscv/tests/rv64ui-p-srlw.elf old mode 100755 new mode 100644 index 04a9c213..d1758021 Binary files a/test/riscv/tests/rv64ui-p-srlw.elf and b/test/riscv/tests/rv64ui-p-srlw.elf differ diff --git a/test/riscv/tests/rv64ui-p-sub.elf b/test/riscv/tests/rv64ui-p-sub.elf old mode 100755 new mode 100644 index 04699b73..ea64efd5 Binary files a/test/riscv/tests/rv64ui-p-sub.elf and b/test/riscv/tests/rv64ui-p-sub.elf differ diff --git a/test/riscv/tests/rv64ui-p-subw.elf b/test/riscv/tests/rv64ui-p-subw.elf old mode 100755 new mode 100644 index 569998ee..fd876f50 Binary files a/test/riscv/tests/rv64ui-p-subw.elf and b/test/riscv/tests/rv64ui-p-subw.elf differ diff --git a/test/riscv/tests/rv64ui-p-sw.elf b/test/riscv/tests/rv64ui-p-sw.elf old mode 100755 new mode 100644 index 0b7daaa8..fa60dda4 Binary files a/test/riscv/tests/rv64ui-p-sw.elf and b/test/riscv/tests/rv64ui-p-sw.elf differ diff --git a/test/riscv/tests/rv64ui-p-xor.elf b/test/riscv/tests/rv64ui-p-xor.elf old mode 100755 new mode 100644 index e610fc9c..0466245a Binary files a/test/riscv/tests/rv64ui-p-xor.elf and b/test/riscv/tests/rv64ui-p-xor.elf differ diff --git a/test/riscv/tests/rv64ui-p-xori.elf b/test/riscv/tests/rv64ui-p-xori.elf old mode 100755 new mode 100644 index 4e8f1fd3..fe522aff Binary files a/test/riscv/tests/rv64ui-p-xori.elf and b/test/riscv/tests/rv64ui-p-xori.elf differ diff --git a/test/riscv/tests/rv64ui-v-add.dump b/test/riscv/tests/rv64ui-v-add.dump new file mode 100644 index 00000000..8598d2b6 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-add.dump @@ -0,0 +1,1229 @@ + +rv64ui-v-add: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b8068693 addi a3,a3,-1152 # 80002fd8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: bb460613 addi a2,a2,-1100 # 80003068 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b7c60613 addi a2,a2,-1156 # 80003080 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: acc68693 addi a3,a3,-1332 # 80003020 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ae868693 addi a3,a3,-1304 # 80003158 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a6860613 addi a2,a2,-1432 # 80003130 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 99c68693 addi a3,a3,-1636 # 80003188 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 8bc68693 addi a3,a3,-1860 # 800030f8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 84c68693 addi a3,a3,-1972 # 800030c0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02100793 li a5,33 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0f1557b7 lui a5,0xf155 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 1b078793 addi a5,a5,432 # f1551b0 <_start-0x70eaae50> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 00208f33 add t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4fdf1063 bne t5,t4,80002fbc + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 00208f33 add t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 4ddf1463 bne t5,t4,80002fbc + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 00208f33 add t5,ra,sp + 80002b04: 00a00e93 li t4,10 + 80002b08: 00400193 li gp,4 + 80002b0c: 4bdf1863 bne t5,t4,80002fbc + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 00208f33 add t5,ra,sp + 80002b1c: ffff8eb7 lui t4,0xffff8 + 80002b20: 00500193 li gp,5 + 80002b24: 49df1c63 bne t5,t4,80002fbc + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 00208f33 add t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 49df1063 bne t5,t4,80002fbc + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 00208f33 add t5,ra,sp + 80002b4c: ffff0eb7 lui t4,0xffff0 + 80002b50: fffe8e9b addiw t4,t4,-1 + 80002b54: 00fe9e93 slli t4,t4,0xf + 80002b58: 00700193 li gp,7 + 80002b5c: 47df1063 bne t5,t4,80002fbc + +0000000080002b60 : + 80002b60: 00000093 li ra,0 + 80002b64: 00008137 lui sp,0x8 + 80002b68: fff1011b addiw sp,sp,-1 + 80002b6c: 00208f33 add t5,ra,sp + 80002b70: 00008eb7 lui t4,0x8 + 80002b74: fffe8e9b addiw t4,t4,-1 + 80002b78: 00800193 li gp,8 + 80002b7c: 45df1063 bne t5,t4,80002fbc + +0000000080002b80 : + 80002b80: 800000b7 lui ra,0x80000 + 80002b84: fff0809b addiw ra,ra,-1 + 80002b88: 00000113 li sp,0 + 80002b8c: 00208f33 add t5,ra,sp + 80002b90: 80000eb7 lui t4,0x80000 + 80002b94: fffe8e9b addiw t4,t4,-1 + 80002b98: 00900193 li gp,9 + 80002b9c: 43df1063 bne t5,t4,80002fbc + +0000000080002ba0 : + 80002ba0: 800000b7 lui ra,0x80000 + 80002ba4: fff0809b addiw ra,ra,-1 + 80002ba8: 00008137 lui sp,0x8 + 80002bac: fff1011b addiw sp,sp,-1 + 80002bb0: 00208f33 add t5,ra,sp + 80002bb4: 00010eb7 lui t4,0x10 + 80002bb8: 001e8e9b addiw t4,t4,1 + 80002bbc: 00fe9e93 slli t4,t4,0xf + 80002bc0: ffee8e93 addi t4,t4,-2 # fffe <_start-0x7fff0002> + 80002bc4: 00a00193 li gp,10 + 80002bc8: 3fdf1a63 bne t5,t4,80002fbc + +0000000080002bcc : + 80002bcc: 800000b7 lui ra,0x80000 + 80002bd0: 00008137 lui sp,0x8 + 80002bd4: fff1011b addiw sp,sp,-1 + 80002bd8: 00208f33 add t5,ra,sp + 80002bdc: 80008eb7 lui t4,0x80008 + 80002be0: fffe8e9b addiw t4,t4,-1 + 80002be4: 00b00193 li gp,11 + 80002be8: 3ddf1a63 bne t5,t4,80002fbc + +0000000080002bec : + 80002bec: 800000b7 lui ra,0x80000 + 80002bf0: fff0809b addiw ra,ra,-1 + 80002bf4: ffff8137 lui sp,0xffff8 + 80002bf8: 00208f33 add t5,ra,sp + 80002bfc: 7fff8eb7 lui t4,0x7fff8 + 80002c00: fffe8e9b addiw t4,t4,-1 + 80002c04: 00c00193 li gp,12 + 80002c08: 3bdf1a63 bne t5,t4,80002fbc + +0000000080002c0c : + 80002c0c: 00000093 li ra,0 + 80002c10: fff00113 li sp,-1 + 80002c14: 00208f33 add t5,ra,sp + 80002c18: fff00e93 li t4,-1 + 80002c1c: 00d00193 li gp,13 + 80002c20: 39df1e63 bne t5,t4,80002fbc + +0000000080002c24 : + 80002c24: fff00093 li ra,-1 + 80002c28: 00100113 li sp,1 + 80002c2c: 00208f33 add t5,ra,sp + 80002c30: 00000e93 li t4,0 + 80002c34: 00e00193 li gp,14 + 80002c38: 39df1263 bne t5,t4,80002fbc + +0000000080002c3c : + 80002c3c: fff00093 li ra,-1 + 80002c40: fff00113 li sp,-1 + 80002c44: 00208f33 add t5,ra,sp + 80002c48: ffe00e93 li t4,-2 + 80002c4c: 00f00193 li gp,15 + 80002c50: 37df1663 bne t5,t4,80002fbc + +0000000080002c54 : + 80002c54: 00100093 li ra,1 + 80002c58: 80000137 lui sp,0x80000 + 80002c5c: fff1011b addiw sp,sp,-1 + 80002c60: 00208f33 add t5,ra,sp + 80002c64: 00100e9b addiw t4,zero,1 + 80002c68: 01fe9e93 slli t4,t4,0x1f + 80002c6c: 01000193 li gp,16 + 80002c70: 35df1663 bne t5,t4,80002fbc + +0000000080002c74 : + 80002c74: 00d00093 li ra,13 + 80002c78: 00b00113 li sp,11 + 80002c7c: 002080b3 add ra,ra,sp + 80002c80: 01800e93 li t4,24 + 80002c84: 01100193 li gp,17 + 80002c88: 33d09a63 bne ra,t4,80002fbc + +0000000080002c8c : + 80002c8c: 00e00093 li ra,14 + 80002c90: 00b00113 li sp,11 + 80002c94: 00208133 add sp,ra,sp + 80002c98: 01900e93 li t4,25 + 80002c9c: 01200193 li gp,18 + 80002ca0: 31d11e63 bne sp,t4,80002fbc + +0000000080002ca4 : + 80002ca4: 00d00093 li ra,13 + 80002ca8: 001080b3 add ra,ra,ra + 80002cac: 01a00e93 li t4,26 + 80002cb0: 01300193 li gp,19 + 80002cb4: 31d09463 bne ra,t4,80002fbc + +0000000080002cb8 : + 80002cb8: 00000213 li tp,0 + 80002cbc: 00d00093 li ra,13 + 80002cc0: 00b00113 li sp,11 + 80002cc4: 00208f33 add t5,ra,sp + 80002cc8: 000f0313 mv t1,t5 + 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd0: 00200293 li t0,2 + 80002cd4: fe5214e3 bne tp,t0,80002cbc + 80002cd8: 01800e93 li t4,24 + 80002cdc: 01400193 li gp,20 + 80002ce0: 2dd31e63 bne t1,t4,80002fbc + +0000000080002ce4 : + 80002ce4: 00000213 li tp,0 + 80002ce8: 00e00093 li ra,14 + 80002cec: 00b00113 li sp,11 + 80002cf0: 00208f33 add t5,ra,sp + 80002cf4: 00000013 nop + 80002cf8: 000f0313 mv t1,t5 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fe5212e3 bne tp,t0,80002ce8 + 80002d08: 01900e93 li t4,25 + 80002d0c: 01500193 li gp,21 + 80002d10: 2bd31663 bne t1,t4,80002fbc + +0000000080002d14 : + 80002d14: 00000213 li tp,0 + 80002d18: 00f00093 li ra,15 + 80002d1c: 00b00113 li sp,11 + 80002d20: 00208f33 add t5,ra,sp + 80002d24: 00000013 nop + 80002d28: 00000013 nop + 80002d2c: 000f0313 mv t1,t5 + 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d34: 00200293 li t0,2 + 80002d38: fe5210e3 bne tp,t0,80002d18 + 80002d3c: 01a00e93 li t4,26 + 80002d40: 01600193 li gp,22 + 80002d44: 27d31c63 bne t1,t4,80002fbc + +0000000080002d48 : + 80002d48: 00000213 li tp,0 + 80002d4c: 00d00093 li ra,13 + 80002d50: 00b00113 li sp,11 + 80002d54: 00208f33 add t5,ra,sp + 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d5c: 00200293 li t0,2 + 80002d60: fe5216e3 bne tp,t0,80002d4c + 80002d64: 01800e93 li t4,24 + 80002d68: 01700193 li gp,23 + 80002d6c: 25df1863 bne t5,t4,80002fbc + +0000000080002d70 : + 80002d70: 00000213 li tp,0 + 80002d74: 00e00093 li ra,14 + 80002d78: 00b00113 li sp,11 + 80002d7c: 00000013 nop + 80002d80: 00208f33 add t5,ra,sp + 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d88: 00200293 li t0,2 + 80002d8c: fe5214e3 bne tp,t0,80002d74 + 80002d90: 01900e93 li t4,25 + 80002d94: 01800193 li gp,24 + 80002d98: 23df1263 bne t5,t4,80002fbc + +0000000080002d9c : + 80002d9c: 00000213 li tp,0 + 80002da0: 00f00093 li ra,15 + 80002da4: 00b00113 li sp,11 + 80002da8: 00000013 nop + 80002dac: 00000013 nop + 80002db0: 00208f33 add t5,ra,sp + 80002db4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db8: 00200293 li t0,2 + 80002dbc: fe5212e3 bne tp,t0,80002da0 + 80002dc0: 01a00e93 li t4,26 + 80002dc4: 01900193 li gp,25 + 80002dc8: 1fdf1a63 bne t5,t4,80002fbc + +0000000080002dcc : + 80002dcc: 00000213 li tp,0 + 80002dd0: 00d00093 li ra,13 + 80002dd4: 00000013 nop + 80002dd8: 00b00113 li sp,11 + 80002ddc: 00208f33 add t5,ra,sp + 80002de0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de4: 00200293 li t0,2 + 80002de8: fe5214e3 bne tp,t0,80002dd0 + 80002dec: 01800e93 li t4,24 + 80002df0: 01a00193 li gp,26 + 80002df4: 1ddf1463 bne t5,t4,80002fbc + +0000000080002df8 : + 80002df8: 00000213 li tp,0 + 80002dfc: 00e00093 li ra,14 + 80002e00: 00000013 nop + 80002e04: 00b00113 li sp,11 + 80002e08: 00000013 nop + 80002e0c: 00208f33 add t5,ra,sp + 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e14: 00200293 li t0,2 + 80002e18: fe5212e3 bne tp,t0,80002dfc + 80002e1c: 01900e93 li t4,25 + 80002e20: 01b00193 li gp,27 + 80002e24: 19df1c63 bne t5,t4,80002fbc + +0000000080002e28 : + 80002e28: 00000213 li tp,0 + 80002e2c: 00f00093 li ra,15 + 80002e30: 00000013 nop + 80002e34: 00000013 nop + 80002e38: 00b00113 li sp,11 + 80002e3c: 00208f33 add t5,ra,sp + 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e44: 00200293 li t0,2 + 80002e48: fe5212e3 bne tp,t0,80002e2c + 80002e4c: 01a00e93 li t4,26 + 80002e50: 01c00193 li gp,28 + 80002e54: 17df1463 bne t5,t4,80002fbc + +0000000080002e58 : + 80002e58: 00000213 li tp,0 + 80002e5c: 00b00113 li sp,11 + 80002e60: 00d00093 li ra,13 + 80002e64: 00208f33 add t5,ra,sp + 80002e68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e6c: 00200293 li t0,2 + 80002e70: fe5216e3 bne tp,t0,80002e5c + 80002e74: 01800e93 li t4,24 + 80002e78: 01d00193 li gp,29 + 80002e7c: 15df1063 bne t5,t4,80002fbc + +0000000080002e80 : + 80002e80: 00000213 li tp,0 + 80002e84: 00b00113 li sp,11 + 80002e88: 00e00093 li ra,14 + 80002e8c: 00000013 nop + 80002e90: 00208f33 add t5,ra,sp + 80002e94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e98: 00200293 li t0,2 + 80002e9c: fe5214e3 bne tp,t0,80002e84 + 80002ea0: 01900e93 li t4,25 + 80002ea4: 01e00193 li gp,30 + 80002ea8: 11df1a63 bne t5,t4,80002fbc + +0000000080002eac : + 80002eac: 00000213 li tp,0 + 80002eb0: 00b00113 li sp,11 + 80002eb4: 00f00093 li ra,15 + 80002eb8: 00000013 nop + 80002ebc: 00000013 nop + 80002ec0: 00208f33 add t5,ra,sp + 80002ec4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec8: 00200293 li t0,2 + 80002ecc: fe5212e3 bne tp,t0,80002eb0 + 80002ed0: 01a00e93 li t4,26 + 80002ed4: 01f00193 li gp,31 + 80002ed8: 0fdf1263 bne t5,t4,80002fbc + +0000000080002edc : + 80002edc: 00000213 li tp,0 + 80002ee0: 00b00113 li sp,11 + 80002ee4: 00000013 nop + 80002ee8: 00d00093 li ra,13 + 80002eec: 00208f33 add t5,ra,sp + 80002ef0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ef4: 00200293 li t0,2 + 80002ef8: fe5214e3 bne tp,t0,80002ee0 + 80002efc: 01800e93 li t4,24 + 80002f00: 02000193 li gp,32 + 80002f04: 0bdf1c63 bne t5,t4,80002fbc + +0000000080002f08 : + 80002f08: 00000213 li tp,0 + 80002f0c: 00b00113 li sp,11 + 80002f10: 00000013 nop + 80002f14: 00e00093 li ra,14 + 80002f18: 00000013 nop + 80002f1c: 00208f33 add t5,ra,sp + 80002f20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f24: 00200293 li t0,2 + 80002f28: fe5212e3 bne tp,t0,80002f0c + 80002f2c: 01900e93 li t4,25 + 80002f30: 02100193 li gp,33 + 80002f34: 09df1463 bne t5,t4,80002fbc + +0000000080002f38 : + 80002f38: 00000213 li tp,0 + 80002f3c: 00b00113 li sp,11 + 80002f40: 00000013 nop + 80002f44: 00000013 nop + 80002f48: 00f00093 li ra,15 + 80002f4c: 00208f33 add t5,ra,sp + 80002f50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f54: 00200293 li t0,2 + 80002f58: fe5212e3 bne tp,t0,80002f3c + 80002f5c: 01a00e93 li t4,26 + 80002f60: 02200193 li gp,34 + 80002f64: 05df1c63 bne t5,t4,80002fbc + +0000000080002f68 : + 80002f68: 00f00093 li ra,15 + 80002f6c: 00100133 add sp,zero,ra + 80002f70: 00f00e93 li t4,15 + 80002f74: 02300193 li gp,35 + 80002f78: 05d11263 bne sp,t4,80002fbc + +0000000080002f7c : + 80002f7c: 02000093 li ra,32 + 80002f80: 00008133 add sp,ra,zero + 80002f84: 02000e93 li t4,32 + 80002f88: 02400193 li gp,36 + 80002f8c: 03d11863 bne sp,t4,80002fbc + +0000000080002f90 : + 80002f90: 000000b3 add ra,zero,zero + 80002f94: 00000e93 li t4,0 + 80002f98: 02500193 li gp,37 + 80002f9c: 03d09063 bne ra,t4,80002fbc + +0000000080002fa0 : + 80002fa0: 01000093 li ra,16 + 80002fa4: 01e00113 li sp,30 + 80002fa8: 00208033 add zero,ra,sp + 80002fac: 00000e93 li t4,0 + 80002fb0: 02600193 li gp,38 + 80002fb4: 01d01463 bne zero,t4,80002fbc + 80002fb8: 00301a63 bne zero,gp,80002fcc + +0000000080002fbc : + 80002fbc: 00119513 slli a0,gp,0x1 + 80002fc0: 00050063 beqz a0,80002fc0 + 80002fc4: 00156513 ori a0,a0,1 + 80002fc8: 00000073 ecall + +0000000080002fcc : + 80002fcc: 00100513 li a0,1 + 80002fd0: 00000073 ecall + 80002fd4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-add.elf b/test/riscv/tests/rv64ui-v-add.elf new file mode 100644 index 00000000..d60d87a8 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-add.elf differ diff --git a/test/riscv/tests/rv64ui-v-addi.dump b/test/riscv/tests/rv64ui-v-addi.dump new file mode 100644 index 00000000..6c453f70 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-addi.dump @@ -0,0 +1,1051 @@ + +rv64ui-v-addi: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 92068693 addi a3,a3,-1760 # 80002d78 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 95460613 addi a2,a2,-1708 # 80002e08 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 91c60613 addi a2,a2,-1764 # 80002e20 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 86c68693 addi a3,a3,-1940 # 80002dc0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 88868693 addi a3,a3,-1912 # 80002ef8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 80860613 addi a2,a2,-2040 # 80002ed0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 73c68693 addi a3,a3,1852 # 80002f28 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 65c68693 addi a3,a3,1628 # 80002e98 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5ec68693 addi a3,a3,1516 # 80002e60 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01000793 li a5,16 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 04f557b7 lui a5,0x4f55 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 5a178793 addi a5,a5,1441 # 4f555a1 <_start-0x7b0aaa5f> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00008f13 mv t5,ra + 80002ad0: 00000e93 li t4,0 + 80002ad4: 00200193 li gp,2 + 80002ad8: 29df1263 bne t5,t4,80002d5c + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 00108f13 addi t5,ra,1 + 80002ae4: 00200e93 li t4,2 + 80002ae8: 00300193 li gp,3 + 80002aec: 27df1863 bne t5,t4,80002d5c + +0000000080002af0 : + 80002af0: 00300093 li ra,3 + 80002af4: 00708f13 addi t5,ra,7 + 80002af8: 00a00e93 li t4,10 + 80002afc: 00400193 li gp,4 + 80002b00: 25df1e63 bne t5,t4,80002d5c + +0000000080002b04 : + 80002b04: 00000093 li ra,0 + 80002b08: 80008f13 addi t5,ra,-2048 + 80002b0c: 80000e93 li t4,-2048 + 80002b10: 00500193 li gp,5 + 80002b14: 25df1463 bne t5,t4,80002d5c + +0000000080002b18 : + 80002b18: 800000b7 lui ra,0x80000 + 80002b1c: 00008f13 mv t5,ra + 80002b20: 80000eb7 lui t4,0x80000 + 80002b24: 00600193 li gp,6 + 80002b28: 23df1a63 bne t5,t4,80002d5c + +0000000080002b2c : + 80002b2c: 800000b7 lui ra,0x80000 + 80002b30: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> + 80002b34: fff00e9b addiw t4,zero,-1 + 80002b38: 01fe9e93 slli t4,t4,0x1f + 80002b3c: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> + 80002b40: 00700193 li gp,7 + 80002b44: 21df1c63 bne t5,t4,80002d5c + +0000000080002b48 : + 80002b48: 00000093 li ra,0 + 80002b4c: 7ff08f13 addi t5,ra,2047 + 80002b50: 7ff00e93 li t4,2047 + 80002b54: 00800193 li gp,8 + 80002b58: 21df1263 bne t5,t4,80002d5c + +0000000080002b5c : + 80002b5c: 800000b7 lui ra,0x80000 + 80002b60: fff0809b addiw ra,ra,-1 + 80002b64: 00008f13 mv t5,ra + 80002b68: 80000eb7 lui t4,0x80000 + 80002b6c: fffe8e9b addiw t4,t4,-1 + 80002b70: 00900193 li gp,9 + 80002b74: 1fdf1463 bne t5,t4,80002d5c + +0000000080002b78 : + 80002b78: 800000b7 lui ra,0x80000 + 80002b7c: fff0809b addiw ra,ra,-1 + 80002b80: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffff900f> + 80002b84: 00100e9b addiw t4,zero,1 + 80002b88: 01fe9e93 slli t4,t4,0x1f + 80002b8c: 7fee8e93 addi t4,t4,2046 # ffffffff800007fe <_end+0xfffffffeffff900e> + 80002b90: 00a00193 li gp,10 + 80002b94: 1ddf1463 bne t5,t4,80002d5c + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffff900f> + 80002ba0: 80000eb7 lui t4,0x80000 + 80002ba4: 7ffe8e9b addiw t4,t4,2047 + 80002ba8: 00b00193 li gp,11 + 80002bac: 1bdf1863 bne t5,t4,80002d5c + +0000000080002bb0 : + 80002bb0: 800000b7 lui ra,0x80000 + 80002bb4: fff0809b addiw ra,ra,-1 + 80002bb8: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> + 80002bbc: 7ffffeb7 lui t4,0x7ffff + 80002bc0: 7ffe8e9b addiw t4,t4,2047 + 80002bc4: 00c00193 li gp,12 + 80002bc8: 19df1a63 bne t5,t4,80002d5c + +0000000080002bcc : + 80002bcc: 00000093 li ra,0 + 80002bd0: fff08f13 addi t5,ra,-1 + 80002bd4: fff00e93 li t4,-1 + 80002bd8: 00d00193 li gp,13 + 80002bdc: 19df1063 bne t5,t4,80002d5c + +0000000080002be0 : + 80002be0: fff00093 li ra,-1 + 80002be4: 00108f13 addi t5,ra,1 + 80002be8: 00000e93 li t4,0 + 80002bec: 00e00193 li gp,14 + 80002bf0: 17df1663 bne t5,t4,80002d5c + +0000000080002bf4 : + 80002bf4: fff00093 li ra,-1 + 80002bf8: fff08f13 addi t5,ra,-1 + 80002bfc: ffe00e93 li t4,-2 + 80002c00: 00f00193 li gp,15 + 80002c04: 15df1c63 bne t5,t4,80002d5c + +0000000080002c08 : + 80002c08: 800000b7 lui ra,0x80000 + 80002c0c: fff0809b addiw ra,ra,-1 + 80002c10: 00108f13 addi t5,ra,1 # ffffffff80000001 <_end+0xfffffffeffff8811> + 80002c14: 00100e9b addiw t4,zero,1 + 80002c18: 01fe9e93 slli t4,t4,0x1f + 80002c1c: 01000193 li gp,16 + 80002c20: 13df1e63 bne t5,t4,80002d5c + +0000000080002c24 : + 80002c24: 00d00093 li ra,13 + 80002c28: 00b08093 addi ra,ra,11 + 80002c2c: 01800e93 li t4,24 + 80002c30: 01100193 li gp,17 + 80002c34: 13d09463 bne ra,t4,80002d5c + +0000000080002c38 : + 80002c38: 00000213 li tp,0 + 80002c3c: 00d00093 li ra,13 + 80002c40: 00b08f13 addi t5,ra,11 + 80002c44: 000f0313 mv t1,t5 + 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c4c: 00200293 li t0,2 + 80002c50: fe5216e3 bne tp,t0,80002c3c + 80002c54: 01800e93 li t4,24 + 80002c58: 01200193 li gp,18 + 80002c5c: 11d31063 bne t1,t4,80002d5c + +0000000080002c60 : + 80002c60: 00000213 li tp,0 + 80002c64: 00d00093 li ra,13 + 80002c68: 00a08f13 addi t5,ra,10 + 80002c6c: 00000013 nop + 80002c70: 000f0313 mv t1,t5 + 80002c74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c78: 00200293 li t0,2 + 80002c7c: fe5214e3 bne tp,t0,80002c64 + 80002c80: 01700e93 li t4,23 + 80002c84: 01300193 li gp,19 + 80002c88: 0dd31a63 bne t1,t4,80002d5c + +0000000080002c8c : + 80002c8c: 00000213 li tp,0 + 80002c90: 00d00093 li ra,13 + 80002c94: 00908f13 addi t5,ra,9 + 80002c98: 00000013 nop + 80002c9c: 00000013 nop + 80002ca0: 000f0313 mv t1,t5 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5212e3 bne tp,t0,80002c90 + 80002cb0: 01600e93 li t4,22 + 80002cb4: 01400193 li gp,20 + 80002cb8: 0bd31263 bne t1,t4,80002d5c + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 00d00093 li ra,13 + 80002cc4: 00b08f13 addi t5,ra,11 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fe5218e3 bne tp,t0,80002cc0 + 80002cd4: 01800e93 li t4,24 + 80002cd8: 01500193 li gp,21 + 80002cdc: 09df1063 bne t5,t4,80002d5c + +0000000080002ce0 : + 80002ce0: 00000213 li tp,0 + 80002ce4: 00d00093 li ra,13 + 80002ce8: 00000013 nop + 80002cec: 00a08f13 addi t5,ra,10 + 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf4: 00200293 li t0,2 + 80002cf8: fe5216e3 bne tp,t0,80002ce4 + 80002cfc: 01700e93 li t4,23 + 80002d00: 01600193 li gp,22 + 80002d04: 05df1c63 bne t5,t4,80002d5c + +0000000080002d08 : + 80002d08: 00000213 li tp,0 + 80002d0c: 00d00093 li ra,13 + 80002d10: 00000013 nop + 80002d14: 00000013 nop + 80002d18: 00908f13 addi t5,ra,9 + 80002d1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d20: 00200293 li t0,2 + 80002d24: fe5214e3 bne tp,t0,80002d0c + 80002d28: 01600e93 li t4,22 + 80002d2c: 01700193 li gp,23 + 80002d30: 03df1663 bne t5,t4,80002d5c + +0000000080002d34 : + 80002d34: 02000093 li ra,32 + 80002d38: 02000e93 li t4,32 + 80002d3c: 01800193 li gp,24 + 80002d40: 01d09e63 bne ra,t4,80002d5c + +0000000080002d44 : + 80002d44: 02100093 li ra,33 + 80002d48: 03208013 addi zero,ra,50 + 80002d4c: 00000e93 li t4,0 + 80002d50: 01900193 li gp,25 + 80002d54: 01d01463 bne zero,t4,80002d5c + 80002d58: 00301a63 bne zero,gp,80002d6c + +0000000080002d5c : + 80002d5c: 00119513 slli a0,gp,0x1 + 80002d60: 00050063 beqz a0,80002d60 + 80002d64: 00156513 ori a0,a0,1 + 80002d68: 00000073 ecall + +0000000080002d6c : + 80002d6c: 00100513 li a0,1 + 80002d70: 00000073 ecall + 80002d74: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addi.elf b/test/riscv/tests/rv64ui-v-addi.elf new file mode 100644 index 00000000..28d8b889 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-addi.elf differ diff --git a/test/riscv/tests/rv64ui-v-addiw.dump b/test/riscv/tests/rv64ui-v-addiw.dump new file mode 100644 index 00000000..d152915b --- /dev/null +++ b/test/riscv/tests/rv64ui-v-addiw.dump @@ -0,0 +1,1048 @@ + +rv64ui-v-addiw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 91868693 addi a3,a3,-1768 # 80002d70 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 94c60613 addi a2,a2,-1716 # 80002e00 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 91460613 addi a2,a2,-1772 # 80002e18 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 86468693 addi a3,a3,-1948 # 80002db8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 88068693 addi a3,a3,-1920 # 80002ef0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 80060613 addi a2,a2,-2048 # 80002ec8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 73468693 addi a3,a3,1844 # 80002f20 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 65468693 addi a3,a3,1620 # 80002e90 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5e468693 addi a3,a3,1508 # 80002e58 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00d00793 li a5,13 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 04c6e7b7 lui a5,0x4c6e + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 45678793 addi a5,a5,1110 # 4c6e456 <_start-0x7b391baa> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00008f1b sext.w t5,ra + 80002ad0: 00000e93 li t4,0 + 80002ad4: 00200193 li gp,2 + 80002ad8: 27df1c63 bne t5,t4,80002d50 + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 00108f1b addiw t5,ra,1 + 80002ae4: 00200e93 li t4,2 + 80002ae8: 00300193 li gp,3 + 80002aec: 27df1263 bne t5,t4,80002d50 + +0000000080002af0 : + 80002af0: 00300093 li ra,3 + 80002af4: 00708f1b addiw t5,ra,7 + 80002af8: 00a00e93 li t4,10 + 80002afc: 00400193 li gp,4 + 80002b00: 25df1863 bne t5,t4,80002d50 + +0000000080002b04 : + 80002b04: 00000093 li ra,0 + 80002b08: 80008f1b addiw t5,ra,-2048 + 80002b0c: 80000e93 li t4,-2048 + 80002b10: 00500193 li gp,5 + 80002b14: 23df1e63 bne t5,t4,80002d50 + +0000000080002b18 : + 80002b18: 800000b7 lui ra,0x80000 + 80002b1c: 00008f1b sext.w t5,ra + 80002b20: 80000eb7 lui t4,0x80000 + 80002b24: 00600193 li gp,6 + 80002b28: 23df1463 bne t5,t4,80002d50 + +0000000080002b2c : + 80002b2c: 800000b7 lui ra,0x80000 + 80002b30: 80008f1b addiw t5,ra,-2048 + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 800e8e9b addiw t4,t4,-2048 + 80002b3c: 00700193 li gp,7 + 80002b40: 21df1863 bne t5,t4,80002d50 + +0000000080002b44 : + 80002b44: 00000093 li ra,0 + 80002b48: 7ff08f1b addiw t5,ra,2047 + 80002b4c: 7ff00e93 li t4,2047 + 80002b50: 00800193 li gp,8 + 80002b54: 1fdf1e63 bne t5,t4,80002d50 + +0000000080002b58 : + 80002b58: 800000b7 lui ra,0x80000 + 80002b5c: fff0809b addiw ra,ra,-1 + 80002b60: 00008f1b sext.w t5,ra + 80002b64: 80000eb7 lui t4,0x80000 + 80002b68: fffe8e9b addiw t4,t4,-1 + 80002b6c: 00900193 li gp,9 + 80002b70: 1fdf1063 bne t5,t4,80002d50 + +0000000080002b74 : + 80002b74: 800000b7 lui ra,0x80000 + 80002b78: fff0809b addiw ra,ra,-1 + 80002b7c: 7ff08f1b addiw t5,ra,2047 + 80002b80: 80000eb7 lui t4,0x80000 + 80002b84: 7fee8e9b addiw t4,t4,2046 + 80002b88: 00a00193 li gp,10 + 80002b8c: 1ddf1263 bne t5,t4,80002d50 + +0000000080002b90 : + 80002b90: 800000b7 lui ra,0x80000 + 80002b94: 7ff08f1b addiw t5,ra,2047 + 80002b98: 80000eb7 lui t4,0x80000 + 80002b9c: 7ffe8e9b addiw t4,t4,2047 + 80002ba0: 00b00193 li gp,11 + 80002ba4: 1bdf1663 bne t5,t4,80002d50 + +0000000080002ba8 : + 80002ba8: 800000b7 lui ra,0x80000 + 80002bac: fff0809b addiw ra,ra,-1 + 80002bb0: 80008f1b addiw t5,ra,-2048 + 80002bb4: 7ffffeb7 lui t4,0x7ffff + 80002bb8: 7ffe8e9b addiw t4,t4,2047 + 80002bbc: 00c00193 li gp,12 + 80002bc0: 19df1863 bne t5,t4,80002d50 + +0000000080002bc4 : + 80002bc4: 00000093 li ra,0 + 80002bc8: fff08f1b addiw t5,ra,-1 + 80002bcc: fff00e93 li t4,-1 + 80002bd0: 00d00193 li gp,13 + 80002bd4: 17df1e63 bne t5,t4,80002d50 + +0000000080002bd8 : + 80002bd8: fff00093 li ra,-1 + 80002bdc: 00108f1b addiw t5,ra,1 + 80002be0: 00000e93 li t4,0 + 80002be4: 00e00193 li gp,14 + 80002be8: 17df1463 bne t5,t4,80002d50 + +0000000080002bec : + 80002bec: fff00093 li ra,-1 + 80002bf0: fff08f1b addiw t5,ra,-1 + 80002bf4: ffe00e93 li t4,-2 + 80002bf8: 00f00193 li gp,15 + 80002bfc: 15df1a63 bne t5,t4,80002d50 + +0000000080002c00 : + 80002c00: 800000b7 lui ra,0x80000 + 80002c04: fff0809b addiw ra,ra,-1 + 80002c08: 00108f1b addiw t5,ra,1 + 80002c0c: 80000eb7 lui t4,0x80000 + 80002c10: 01000193 li gp,16 + 80002c14: 13df1e63 bne t5,t4,80002d50 + +0000000080002c18 : + 80002c18: 00d00093 li ra,13 + 80002c1c: 00b0809b addiw ra,ra,11 + 80002c20: 01800e93 li t4,24 + 80002c24: 01100193 li gp,17 + 80002c28: 13d09463 bne ra,t4,80002d50 + +0000000080002c2c : + 80002c2c: 00000213 li tp,0 + 80002c30: 00d00093 li ra,13 + 80002c34: 00b08f1b addiw t5,ra,11 + 80002c38: 000f0313 mv t1,t5 + 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c40: 00200293 li t0,2 + 80002c44: fe5216e3 bne tp,t0,80002c30 + 80002c48: 01800e93 li t4,24 + 80002c4c: 01200193 li gp,18 + 80002c50: 11d31063 bne t1,t4,80002d50 + +0000000080002c54 : + 80002c54: 00000213 li tp,0 + 80002c58: 00d00093 li ra,13 + 80002c5c: 00a08f1b addiw t5,ra,10 + 80002c60: 00000013 nop + 80002c64: 000f0313 mv t1,t5 + 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c6c: 00200293 li t0,2 + 80002c70: fe5214e3 bne tp,t0,80002c58 + 80002c74: 01700e93 li t4,23 + 80002c78: 01300193 li gp,19 + 80002c7c: 0dd31a63 bne t1,t4,80002d50 + +0000000080002c80 : + 80002c80: 00000213 li tp,0 + 80002c84: 00d00093 li ra,13 + 80002c88: 00908f1b addiw t5,ra,9 + 80002c8c: 00000013 nop + 80002c90: 00000013 nop + 80002c94: 000f0313 mv t1,t5 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5212e3 bne tp,t0,80002c84 + 80002ca4: 01600e93 li t4,22 + 80002ca8: 01400193 li gp,20 + 80002cac: 0bd31263 bne t1,t4,80002d50 + +0000000080002cb0 : + 80002cb0: 00000213 li tp,0 + 80002cb4: 00d00093 li ra,13 + 80002cb8: 00b08f1b addiw t5,ra,11 + 80002cbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc0: 00200293 li t0,2 + 80002cc4: fe5218e3 bne tp,t0,80002cb4 + 80002cc8: 01800e93 li t4,24 + 80002ccc: 01500193 li gp,21 + 80002cd0: 09df1063 bne t5,t4,80002d50 + +0000000080002cd4 : + 80002cd4: 00000213 li tp,0 + 80002cd8: 00d00093 li ra,13 + 80002cdc: 00000013 nop + 80002ce0: 00a08f1b addiw t5,ra,10 + 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce8: 00200293 li t0,2 + 80002cec: fe5216e3 bne tp,t0,80002cd8 + 80002cf0: 01700e93 li t4,23 + 80002cf4: 01600193 li gp,22 + 80002cf8: 05df1c63 bne t5,t4,80002d50 + +0000000080002cfc : + 80002cfc: 00000213 li tp,0 + 80002d00: 00d00093 li ra,13 + 80002d04: 00000013 nop + 80002d08: 00000013 nop + 80002d0c: 00908f1b addiw t5,ra,9 + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fe5214e3 bne tp,t0,80002d00 + 80002d1c: 01600e93 li t4,22 + 80002d20: 01700193 li gp,23 + 80002d24: 03df1663 bne t5,t4,80002d50 + +0000000080002d28 : + 80002d28: 0200009b addiw ra,zero,32 + 80002d2c: 02000e93 li t4,32 + 80002d30: 01800193 li gp,24 + 80002d34: 01d09e63 bne ra,t4,80002d50 + +0000000080002d38 : + 80002d38: 02100093 li ra,33 + 80002d3c: 0320801b addiw zero,ra,50 + 80002d40: 00000e93 li t4,0 + 80002d44: 01900193 li gp,25 + 80002d48: 01d01463 bne zero,t4,80002d50 + 80002d4c: 00301a63 bne zero,gp,80002d60 + +0000000080002d50 : + 80002d50: 00119513 slli a0,gp,0x1 + 80002d54: 00050063 beqz a0,80002d54 + 80002d58: 00156513 ori a0,a0,1 + 80002d5c: 00000073 ecall + +0000000080002d60 : + 80002d60: 00100513 li a0,1 + 80002d64: 00000073 ecall + 80002d68: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addiw.elf b/test/riscv/tests/rv64ui-v-addiw.elf new file mode 100644 index 00000000..ddbea563 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-addiw.elf differ diff --git a/test/riscv/tests/rv64ui-v-addw.dump b/test/riscv/tests/rv64ui-v-addw.dump new file mode 100644 index 00000000..838371b6 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-addw.dump @@ -0,0 +1,1224 @@ + +rv64ui-v-addw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b7068693 addi a3,a3,-1168 # 80002fc8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: ba460613 addi a2,a2,-1116 # 80003058 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b6c60613 addi a2,a2,-1172 # 80003070 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: abc68693 addi a3,a3,-1348 # 80003010 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ad868693 addi a3,a3,-1320 # 80003148 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a5860613 addi a2,a2,-1448 # 80003120 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 98c68693 addi a3,a3,-1652 # 80003178 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 8ac68693 addi a3,a3,-1876 # 800030e8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 83c68693 addi a3,a3,-1988 # 800030b0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00800793 li a5,8 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 04c367b7 lui a5,0x4c36 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 29178793 addi a5,a5,657 # 4c36291 <_start-0x7b3c9d6f> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 00208f3b addw t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4ddf1663 bne t5,t4,80002fa8 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 00208f3b addw t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 4bdf1a63 bne t5,t4,80002fa8 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 00208f3b addw t5,ra,sp + 80002b04: 00a00e93 li t4,10 + 80002b08: 00400193 li gp,4 + 80002b0c: 49df1e63 bne t5,t4,80002fa8 + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 00208f3b addw t5,ra,sp + 80002b1c: ffff8eb7 lui t4,0xffff8 + 80002b20: 00500193 li gp,5 + 80002b24: 49df1263 bne t5,t4,80002fa8 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 00208f3b addw t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 47df1663 bne t5,t4,80002fa8 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 00208f3b addw t5,ra,sp + 80002b4c: 7fff8eb7 lui t4,0x7fff8 + 80002b50: 00700193 li gp,7 + 80002b54: 45df1a63 bne t5,t4,80002fa8 + +0000000080002b58 : + 80002b58: 00000093 li ra,0 + 80002b5c: 00008137 lui sp,0x8 + 80002b60: fff1011b addiw sp,sp,-1 + 80002b64: 00208f3b addw t5,ra,sp + 80002b68: 00008eb7 lui t4,0x8 + 80002b6c: fffe8e9b addiw t4,t4,-1 + 80002b70: 00800193 li gp,8 + 80002b74: 43df1a63 bne t5,t4,80002fa8 + +0000000080002b78 : + 80002b78: 800000b7 lui ra,0x80000 + 80002b7c: fff0809b addiw ra,ra,-1 + 80002b80: 00000113 li sp,0 + 80002b84: 00208f3b addw t5,ra,sp + 80002b88: 80000eb7 lui t4,0x80000 + 80002b8c: fffe8e9b addiw t4,t4,-1 + 80002b90: 00900193 li gp,9 + 80002b94: 41df1a63 bne t5,t4,80002fa8 + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: fff0809b addiw ra,ra,-1 + 80002ba0: 00008137 lui sp,0x8 + 80002ba4: fff1011b addiw sp,sp,-1 + 80002ba8: 00208f3b addw t5,ra,sp + 80002bac: 80008eb7 lui t4,0x80008 + 80002bb0: ffee8e9b addiw t4,t4,-2 + 80002bb4: 00a00193 li gp,10 + 80002bb8: 3fdf1863 bne t5,t4,80002fa8 + +0000000080002bbc : + 80002bbc: 800000b7 lui ra,0x80000 + 80002bc0: 00008137 lui sp,0x8 + 80002bc4: fff1011b addiw sp,sp,-1 + 80002bc8: 00208f3b addw t5,ra,sp + 80002bcc: 80008eb7 lui t4,0x80008 + 80002bd0: fffe8e9b addiw t4,t4,-1 + 80002bd4: 00b00193 li gp,11 + 80002bd8: 3ddf1863 bne t5,t4,80002fa8 + +0000000080002bdc : + 80002bdc: 800000b7 lui ra,0x80000 + 80002be0: fff0809b addiw ra,ra,-1 + 80002be4: ffff8137 lui sp,0xffff8 + 80002be8: 00208f3b addw t5,ra,sp + 80002bec: 7fff8eb7 lui t4,0x7fff8 + 80002bf0: fffe8e9b addiw t4,t4,-1 + 80002bf4: 00c00193 li gp,12 + 80002bf8: 3bdf1863 bne t5,t4,80002fa8 + +0000000080002bfc : + 80002bfc: 00000093 li ra,0 + 80002c00: fff00113 li sp,-1 + 80002c04: 00208f3b addw t5,ra,sp + 80002c08: fff00e93 li t4,-1 + 80002c0c: 00d00193 li gp,13 + 80002c10: 39df1c63 bne t5,t4,80002fa8 + +0000000080002c14 : + 80002c14: fff00093 li ra,-1 + 80002c18: 00100113 li sp,1 + 80002c1c: 00208f3b addw t5,ra,sp + 80002c20: 00000e93 li t4,0 + 80002c24: 00e00193 li gp,14 + 80002c28: 39df1063 bne t5,t4,80002fa8 + +0000000080002c2c : + 80002c2c: fff00093 li ra,-1 + 80002c30: fff00113 li sp,-1 + 80002c34: 00208f3b addw t5,ra,sp + 80002c38: ffe00e93 li t4,-2 + 80002c3c: 00f00193 li gp,15 + 80002c40: 37df1463 bne t5,t4,80002fa8 + +0000000080002c44 : + 80002c44: 00100093 li ra,1 + 80002c48: 80000137 lui sp,0x80000 + 80002c4c: fff1011b addiw sp,sp,-1 + 80002c50: 00208f3b addw t5,ra,sp + 80002c54: 80000eb7 lui t4,0x80000 + 80002c58: 01000193 li gp,16 + 80002c5c: 35df1663 bne t5,t4,80002fa8 + +0000000080002c60 : + 80002c60: 00d00093 li ra,13 + 80002c64: 00b00113 li sp,11 + 80002c68: 002080bb addw ra,ra,sp + 80002c6c: 01800e93 li t4,24 + 80002c70: 01100193 li gp,17 + 80002c74: 33d09a63 bne ra,t4,80002fa8 + +0000000080002c78 : + 80002c78: 00e00093 li ra,14 + 80002c7c: 00b00113 li sp,11 + 80002c80: 0020813b addw sp,ra,sp + 80002c84: 01900e93 li t4,25 + 80002c88: 01200193 li gp,18 + 80002c8c: 31d11e63 bne sp,t4,80002fa8 + +0000000080002c90 : + 80002c90: 00d00093 li ra,13 + 80002c94: 001080bb addw ra,ra,ra + 80002c98: 01a00e93 li t4,26 + 80002c9c: 01300193 li gp,19 + 80002ca0: 31d09463 bne ra,t4,80002fa8 + +0000000080002ca4 : + 80002ca4: 00000213 li tp,0 + 80002ca8: 00d00093 li ra,13 + 80002cac: 00b00113 li sp,11 + 80002cb0: 00208f3b addw t5,ra,sp + 80002cb4: 000f0313 mv t1,t5 + 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cbc: 00200293 li t0,2 + 80002cc0: fe5214e3 bne tp,t0,80002ca8 + 80002cc4: 01800e93 li t4,24 + 80002cc8: 01400193 li gp,20 + 80002ccc: 2dd31e63 bne t1,t4,80002fa8 + +0000000080002cd0 : + 80002cd0: 00000213 li tp,0 + 80002cd4: 00e00093 li ra,14 + 80002cd8: 00b00113 li sp,11 + 80002cdc: 00208f3b addw t5,ra,sp + 80002ce0: 00000013 nop + 80002ce4: 000f0313 mv t1,t5 + 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cec: 00200293 li t0,2 + 80002cf0: fe5212e3 bne tp,t0,80002cd4 + 80002cf4: 01900e93 li t4,25 + 80002cf8: 01500193 li gp,21 + 80002cfc: 2bd31663 bne t1,t4,80002fa8 + +0000000080002d00 : + 80002d00: 00000213 li tp,0 + 80002d04: 00f00093 li ra,15 + 80002d08: 00b00113 li sp,11 + 80002d0c: 00208f3b addw t5,ra,sp + 80002d10: 00000013 nop + 80002d14: 00000013 nop + 80002d18: 000f0313 mv t1,t5 + 80002d1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d20: 00200293 li t0,2 + 80002d24: fe5210e3 bne tp,t0,80002d04 + 80002d28: 01a00e93 li t4,26 + 80002d2c: 01600193 li gp,22 + 80002d30: 27d31c63 bne t1,t4,80002fa8 + +0000000080002d34 : + 80002d34: 00000213 li tp,0 + 80002d38: 00d00093 li ra,13 + 80002d3c: 00b00113 li sp,11 + 80002d40: 00208f3b addw t5,ra,sp + 80002d44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d48: 00200293 li t0,2 + 80002d4c: fe5216e3 bne tp,t0,80002d38 + 80002d50: 01800e93 li t4,24 + 80002d54: 01700193 li gp,23 + 80002d58: 25df1863 bne t5,t4,80002fa8 + +0000000080002d5c : + 80002d5c: 00000213 li tp,0 + 80002d60: 00e00093 li ra,14 + 80002d64: 00b00113 li sp,11 + 80002d68: 00000013 nop + 80002d6c: 00208f3b addw t5,ra,sp + 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d74: 00200293 li t0,2 + 80002d78: fe5214e3 bne tp,t0,80002d60 + 80002d7c: 01900e93 li t4,25 + 80002d80: 01800193 li gp,24 + 80002d84: 23df1263 bne t5,t4,80002fa8 + +0000000080002d88 : + 80002d88: 00000213 li tp,0 + 80002d8c: 00f00093 li ra,15 + 80002d90: 00b00113 li sp,11 + 80002d94: 00000013 nop + 80002d98: 00000013 nop + 80002d9c: 00208f3b addw t5,ra,sp + 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da4: 00200293 li t0,2 + 80002da8: fe5212e3 bne tp,t0,80002d8c + 80002dac: 01a00e93 li t4,26 + 80002db0: 01900193 li gp,25 + 80002db4: 1fdf1a63 bne t5,t4,80002fa8 + +0000000080002db8 : + 80002db8: 00000213 li tp,0 + 80002dbc: 00d00093 li ra,13 + 80002dc0: 00000013 nop + 80002dc4: 00b00113 li sp,11 + 80002dc8: 00208f3b addw t5,ra,sp + 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd0: 00200293 li t0,2 + 80002dd4: fe5214e3 bne tp,t0,80002dbc + 80002dd8: 01800e93 li t4,24 + 80002ddc: 01a00193 li gp,26 + 80002de0: 1ddf1463 bne t5,t4,80002fa8 + +0000000080002de4 : + 80002de4: 00000213 li tp,0 + 80002de8: 00e00093 li ra,14 + 80002dec: 00000013 nop + 80002df0: 00b00113 li sp,11 + 80002df4: 00000013 nop + 80002df8: 00208f3b addw t5,ra,sp + 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e00: 00200293 li t0,2 + 80002e04: fe5212e3 bne tp,t0,80002de8 + 80002e08: 01900e93 li t4,25 + 80002e0c: 01b00193 li gp,27 + 80002e10: 19df1c63 bne t5,t4,80002fa8 + +0000000080002e14 : + 80002e14: 00000213 li tp,0 + 80002e18: 00f00093 li ra,15 + 80002e1c: 00000013 nop + 80002e20: 00000013 nop + 80002e24: 00b00113 li sp,11 + 80002e28: 00208f3b addw t5,ra,sp + 80002e2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e30: 00200293 li t0,2 + 80002e34: fe5212e3 bne tp,t0,80002e18 + 80002e38: 01a00e93 li t4,26 + 80002e3c: 01c00193 li gp,28 + 80002e40: 17df1463 bne t5,t4,80002fa8 + +0000000080002e44 : + 80002e44: 00000213 li tp,0 + 80002e48: 00b00113 li sp,11 + 80002e4c: 00d00093 li ra,13 + 80002e50: 00208f3b addw t5,ra,sp + 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e58: 00200293 li t0,2 + 80002e5c: fe5216e3 bne tp,t0,80002e48 + 80002e60: 01800e93 li t4,24 + 80002e64: 01d00193 li gp,29 + 80002e68: 15df1063 bne t5,t4,80002fa8 + +0000000080002e6c : + 80002e6c: 00000213 li tp,0 + 80002e70: 00b00113 li sp,11 + 80002e74: 00e00093 li ra,14 + 80002e78: 00000013 nop + 80002e7c: 00208f3b addw t5,ra,sp + 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e84: 00200293 li t0,2 + 80002e88: fe5214e3 bne tp,t0,80002e70 + 80002e8c: 01900e93 li t4,25 + 80002e90: 01e00193 li gp,30 + 80002e94: 11df1a63 bne t5,t4,80002fa8 + +0000000080002e98 : + 80002e98: 00000213 li tp,0 + 80002e9c: 00b00113 li sp,11 + 80002ea0: 00f00093 li ra,15 + 80002ea4: 00000013 nop + 80002ea8: 00000013 nop + 80002eac: 00208f3b addw t5,ra,sp + 80002eb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb4: 00200293 li t0,2 + 80002eb8: fe5212e3 bne tp,t0,80002e9c + 80002ebc: 01a00e93 li t4,26 + 80002ec0: 01f00193 li gp,31 + 80002ec4: 0fdf1263 bne t5,t4,80002fa8 + +0000000080002ec8 : + 80002ec8: 00000213 li tp,0 + 80002ecc: 00b00113 li sp,11 + 80002ed0: 00000013 nop + 80002ed4: 00d00093 li ra,13 + 80002ed8: 00208f3b addw t5,ra,sp + 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee0: 00200293 li t0,2 + 80002ee4: fe5214e3 bne tp,t0,80002ecc + 80002ee8: 01800e93 li t4,24 + 80002eec: 02000193 li gp,32 + 80002ef0: 0bdf1c63 bne t5,t4,80002fa8 + +0000000080002ef4 : + 80002ef4: 00000213 li tp,0 + 80002ef8: 00b00113 li sp,11 + 80002efc: 00000013 nop + 80002f00: 00e00093 li ra,14 + 80002f04: 00000013 nop + 80002f08: 00208f3b addw t5,ra,sp + 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f10: 00200293 li t0,2 + 80002f14: fe5212e3 bne tp,t0,80002ef8 + 80002f18: 01900e93 li t4,25 + 80002f1c: 02100193 li gp,33 + 80002f20: 09df1463 bne t5,t4,80002fa8 + +0000000080002f24 : + 80002f24: 00000213 li tp,0 + 80002f28: 00b00113 li sp,11 + 80002f2c: 00000013 nop + 80002f30: 00000013 nop + 80002f34: 00f00093 li ra,15 + 80002f38: 00208f3b addw t5,ra,sp + 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f40: 00200293 li t0,2 + 80002f44: fe5212e3 bne tp,t0,80002f28 + 80002f48: 01a00e93 li t4,26 + 80002f4c: 02200193 li gp,34 + 80002f50: 05df1c63 bne t5,t4,80002fa8 + +0000000080002f54 : + 80002f54: 00f00093 li ra,15 + 80002f58: 0010013b addw sp,zero,ra + 80002f5c: 00f00e93 li t4,15 + 80002f60: 02300193 li gp,35 + 80002f64: 05d11263 bne sp,t4,80002fa8 + +0000000080002f68 : + 80002f68: 02000093 li ra,32 + 80002f6c: 0000813b addw sp,ra,zero + 80002f70: 02000e93 li t4,32 + 80002f74: 02400193 li gp,36 + 80002f78: 03d11863 bne sp,t4,80002fa8 + +0000000080002f7c : + 80002f7c: 000000bb addw ra,zero,zero + 80002f80: 00000e93 li t4,0 + 80002f84: 02500193 li gp,37 + 80002f88: 03d09063 bne ra,t4,80002fa8 + +0000000080002f8c : + 80002f8c: 01000093 li ra,16 + 80002f90: 01e00113 li sp,30 + 80002f94: 0020803b addw zero,ra,sp + 80002f98: 00000e93 li t4,0 + 80002f9c: 02600193 li gp,38 + 80002fa0: 01d01463 bne zero,t4,80002fa8 + 80002fa4: 00301a63 bne zero,gp,80002fb8 + +0000000080002fa8 : + 80002fa8: 00119513 slli a0,gp,0x1 + 80002fac: 00050063 beqz a0,80002fac + 80002fb0: 00156513 ori a0,a0,1 + 80002fb4: 00000073 ecall + +0000000080002fb8 : + 80002fb8: 00100513 li a0,1 + 80002fbc: 00000073 ecall + 80002fc0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addw.elf b/test/riscv/tests/rv64ui-v-addw.elf new file mode 100644 index 00000000..e78ff7a7 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-addw.elf differ diff --git a/test/riscv/tests/rv64ui-v-and.dump b/test/riscv/tests/rv64ui-v-and.dump new file mode 100644 index 00000000..063fbeb1 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-and.dump @@ -0,0 +1,1232 @@ + +rv64ui-v-and: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: be868693 addi a3,a3,-1048 # 80003040 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c1c60613 addi a2,a2,-996 # 800030d0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: be460613 addi a2,a2,-1052 # 800030e8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: b3468693 addi a3,a3,-1228 # 80003088 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b5068693 addi a3,a3,-1200 # 800031c0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: ad060613 addi a2,a2,-1328 # 80003198 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a0468693 addi a3,a3,-1532 # 800031f0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 92468693 addi a3,a3,-1756 # 80003160 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 8b468693 addi a3,a3,-1868 # 80003128 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 01200793 li a5,18 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a1787b7 lui a5,0xa178 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 4b678793 addi a5,a5,1206 # a1784b6 <_start-0x75e87b4a> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000100b7 lui ra,0x10 + 80002acc: f010809b addiw ra,ra,-255 + 80002ad0: 01009093 slli ra,ra,0x10 + 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002ad8: 0f0f1137 lui sp,0xf0f1 + 80002adc: f0f1011b addiw sp,sp,-241 + 80002ae0: 0020ff33 and t5,ra,sp + 80002ae4: 0f001eb7 lui t4,0xf001 + 80002ae8: f00e8e9b addiw t4,t4,-256 + 80002aec: 00200193 li gp,2 + 80002af0: 53df1863 bne t5,t4,80003020 + +0000000080002af4 : + 80002af4: 0ff010b7 lui ra,0xff01 + 80002af8: ff00809b addiw ra,ra,-16 + 80002afc: 000f1137 lui sp,0xf1 + 80002b00: f0f1011b addiw sp,sp,-241 + 80002b04: 00c11113 slli sp,sp,0xc + 80002b08: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b0c: 0020ff33 and t5,ra,sp + 80002b10: 00f00eb7 lui t4,0xf00 + 80002b14: 0f0e8e9b addiw t4,t4,240 + 80002b18: 00300193 li gp,3 + 80002b1c: 51df1263 bne t5,t4,80003020 + +0000000080002b20 : + 80002b20: 00ff00b7 lui ra,0xff0 + 80002b24: 0ff0809b addiw ra,ra,255 + 80002b28: 0f0f1137 lui sp,0xf0f1 + 80002b2c: f0f1011b addiw sp,sp,-241 + 80002b30: 0020ff33 and t5,ra,sp + 80002b34: 000f0eb7 lui t4,0xf0 + 80002b38: 00fe8e9b addiw t4,t4,15 + 80002b3c: 00400193 li gp,4 + 80002b40: 4fdf1063 bne t5,t4,80003020 + +0000000080002b44 : + 80002b44: 000f00b7 lui ra,0xf0 + 80002b48: 0ff0809b addiw ra,ra,255 + 80002b4c: 00c09093 slli ra,ra,0xc + 80002b50: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002b54: 000f1137 lui sp,0xf1 + 80002b58: f0f1011b addiw sp,sp,-241 + 80002b5c: 00c11113 slli sp,sp,0xc + 80002b60: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b64: 0020ff33 and t5,ra,sp + 80002b68: 000f0eb7 lui t4,0xf0 + 80002b6c: 00fe8e9b addiw t4,t4,15 + 80002b70: 00ce9e93 slli t4,t4,0xc + 80002b74: 00500193 li gp,5 + 80002b78: 4bdf1463 bne t5,t4,80003020 + +0000000080002b7c : + 80002b7c: 000100b7 lui ra,0x10 + 80002b80: f010809b addiw ra,ra,-255 + 80002b84: 01009093 slli ra,ra,0x10 + 80002b88: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002b8c: 0f0f1137 lui sp,0xf0f1 + 80002b90: f0f1011b addiw sp,sp,-241 + 80002b94: 0020f0b3 and ra,ra,sp + 80002b98: 0f001eb7 lui t4,0xf001 + 80002b9c: f00e8e9b addiw t4,t4,-256 + 80002ba0: 00600193 li gp,6 + 80002ba4: 47d09e63 bne ra,t4,80003020 + +0000000080002ba8 : + 80002ba8: 0ff010b7 lui ra,0xff01 + 80002bac: ff00809b addiw ra,ra,-16 + 80002bb0: 000f1137 lui sp,0xf1 + 80002bb4: f0f1011b addiw sp,sp,-241 + 80002bb8: 00c11113 slli sp,sp,0xc + 80002bbc: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002bc0: 0020f133 and sp,ra,sp + 80002bc4: 00f00eb7 lui t4,0xf00 + 80002bc8: 0f0e8e9b addiw t4,t4,240 + 80002bcc: 00700193 li gp,7 + 80002bd0: 45d11863 bne sp,t4,80003020 + +0000000080002bd4 : + 80002bd4: 000100b7 lui ra,0x10 + 80002bd8: f010809b addiw ra,ra,-255 + 80002bdc: 01009093 slli ra,ra,0x10 + 80002be0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002be4: 0010f0b3 and ra,ra,ra + 80002be8: 00010eb7 lui t4,0x10 + 80002bec: f01e8e9b addiw t4,t4,-255 + 80002bf0: 010e9e93 slli t4,t4,0x10 + 80002bf4: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002bf8: 00800193 li gp,8 + 80002bfc: 43d09263 bne ra,t4,80003020 + +0000000080002c00 : + 80002c00: 00000213 li tp,0 + 80002c04: 000100b7 lui ra,0x10 + 80002c08: f010809b addiw ra,ra,-255 + 80002c0c: 01009093 slli ra,ra,0x10 + 80002c10: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002c14: 0f0f1137 lui sp,0xf0f1 + 80002c18: f0f1011b addiw sp,sp,-241 + 80002c1c: 0020ff33 and t5,ra,sp + 80002c20: 000f0313 mv t1,t5 + 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c28: 00200293 li t0,2 + 80002c2c: fc521ce3 bne tp,t0,80002c04 + 80002c30: 0f001eb7 lui t4,0xf001 + 80002c34: f00e8e9b addiw t4,t4,-256 + 80002c38: 00900193 li gp,9 + 80002c3c: 3fd31263 bne t1,t4,80003020 + +0000000080002c40 : + 80002c40: 00000213 li tp,0 + 80002c44: 0ff010b7 lui ra,0xff01 + 80002c48: ff00809b addiw ra,ra,-16 + 80002c4c: 000f1137 lui sp,0xf1 + 80002c50: f0f1011b addiw sp,sp,-241 + 80002c54: 00c11113 slli sp,sp,0xc + 80002c58: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002c5c: 0020ff33 and t5,ra,sp + 80002c60: 00000013 nop + 80002c64: 000f0313 mv t1,t5 + 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c6c: 00200293 li t0,2 + 80002c70: fc521ae3 bne tp,t0,80002c44 + 80002c74: 00f00eb7 lui t4,0xf00 + 80002c78: 0f0e8e9b addiw t4,t4,240 + 80002c7c: 00a00193 li gp,10 + 80002c80: 3bd31063 bne t1,t4,80003020 + +0000000080002c84 : + 80002c84: 00000213 li tp,0 + 80002c88: 00ff00b7 lui ra,0xff0 + 80002c8c: 0ff0809b addiw ra,ra,255 + 80002c90: 0f0f1137 lui sp,0xf0f1 + 80002c94: f0f1011b addiw sp,sp,-241 + 80002c98: 0020ff33 and t5,ra,sp + 80002c9c: 00000013 nop + 80002ca0: 00000013 nop + 80002ca4: 000f0313 mv t1,t5 + 80002ca8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cac: 00200293 li t0,2 + 80002cb0: fc521ce3 bne tp,t0,80002c88 + 80002cb4: 000f0eb7 lui t4,0xf0 + 80002cb8: 00fe8e9b addiw t4,t4,15 + 80002cbc: 00b00193 li gp,11 + 80002cc0: 37d31063 bne t1,t4,80003020 + +0000000080002cc4 : + 80002cc4: 00000213 li tp,0 + 80002cc8: 000100b7 lui ra,0x10 + 80002ccc: f010809b addiw ra,ra,-255 + 80002cd0: 01009093 slli ra,ra,0x10 + 80002cd4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002cd8: 0f0f1137 lui sp,0xf0f1 + 80002cdc: f0f1011b addiw sp,sp,-241 + 80002ce0: 0020ff33 and t5,ra,sp + 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce8: 00200293 li t0,2 + 80002cec: fc521ee3 bne tp,t0,80002cc8 + 80002cf0: 0f001eb7 lui t4,0xf001 + 80002cf4: f00e8e9b addiw t4,t4,-256 + 80002cf8: 00c00193 li gp,12 + 80002cfc: 33df1263 bne t5,t4,80003020 + +0000000080002d00 : + 80002d00: 00000213 li tp,0 + 80002d04: 0ff010b7 lui ra,0xff01 + 80002d08: ff00809b addiw ra,ra,-16 + 80002d0c: 000f1137 lui sp,0xf1 + 80002d10: f0f1011b addiw sp,sp,-241 + 80002d14: 00c11113 slli sp,sp,0xc + 80002d18: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002d1c: 00000013 nop + 80002d20: 0020ff33 and t5,ra,sp + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fc521ce3 bne tp,t0,80002d04 + 80002d30: 00f00eb7 lui t4,0xf00 + 80002d34: 0f0e8e9b addiw t4,t4,240 + 80002d38: 00d00193 li gp,13 + 80002d3c: 2fdf1263 bne t5,t4,80003020 + +0000000080002d40 : + 80002d40: 00000213 li tp,0 + 80002d44: 00ff00b7 lui ra,0xff0 + 80002d48: 0ff0809b addiw ra,ra,255 + 80002d4c: 0f0f1137 lui sp,0xf0f1 + 80002d50: f0f1011b addiw sp,sp,-241 + 80002d54: 00000013 nop + 80002d58: 00000013 nop + 80002d5c: 0020ff33 and t5,ra,sp + 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d64: 00200293 li t0,2 + 80002d68: fc521ee3 bne tp,t0,80002d44 + 80002d6c: 000f0eb7 lui t4,0xf0 + 80002d70: 00fe8e9b addiw t4,t4,15 + 80002d74: 00e00193 li gp,14 + 80002d78: 2bdf1463 bne t5,t4,80003020 + +0000000080002d7c : + 80002d7c: 00000213 li tp,0 + 80002d80: 000100b7 lui ra,0x10 + 80002d84: f010809b addiw ra,ra,-255 + 80002d88: 01009093 slli ra,ra,0x10 + 80002d8c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002d90: 00000013 nop + 80002d94: 0f0f1137 lui sp,0xf0f1 + 80002d98: f0f1011b addiw sp,sp,-241 + 80002d9c: 0020ff33 and t5,ra,sp + 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da4: 00200293 li t0,2 + 80002da8: fc521ce3 bne tp,t0,80002d80 + 80002dac: 0f001eb7 lui t4,0xf001 + 80002db0: f00e8e9b addiw t4,t4,-256 + 80002db4: 00f00193 li gp,15 + 80002db8: 27df1463 bne t5,t4,80003020 + +0000000080002dbc : + 80002dbc: 00000213 li tp,0 + 80002dc0: 0ff010b7 lui ra,0xff01 + 80002dc4: ff00809b addiw ra,ra,-16 + 80002dc8: 00000013 nop + 80002dcc: 000f1137 lui sp,0xf1 + 80002dd0: f0f1011b addiw sp,sp,-241 + 80002dd4: 00c11113 slli sp,sp,0xc + 80002dd8: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002ddc: 00000013 nop + 80002de0: 0020ff33 and t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fc521ae3 bne tp,t0,80002dc0 + 80002df0: 00f00eb7 lui t4,0xf00 + 80002df4: 0f0e8e9b addiw t4,t4,240 + 80002df8: 01000193 li gp,16 + 80002dfc: 23df1263 bne t5,t4,80003020 + +0000000080002e00 : + 80002e00: 00000213 li tp,0 + 80002e04: 00ff00b7 lui ra,0xff0 + 80002e08: 0ff0809b addiw ra,ra,255 + 80002e0c: 00000013 nop + 80002e10: 00000013 nop + 80002e14: 0f0f1137 lui sp,0xf0f1 + 80002e18: f0f1011b addiw sp,sp,-241 + 80002e1c: 0020ff33 and t5,ra,sp + 80002e20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e24: 00200293 li t0,2 + 80002e28: fc521ee3 bne tp,t0,80002e04 + 80002e2c: 000f0eb7 lui t4,0xf0 + 80002e30: 00fe8e9b addiw t4,t4,15 + 80002e34: 01100193 li gp,17 + 80002e38: 1fdf1463 bne t5,t4,80003020 + +0000000080002e3c : + 80002e3c: 00000213 li tp,0 + 80002e40: 0f0f1137 lui sp,0xf0f1 + 80002e44: f0f1011b addiw sp,sp,-241 + 80002e48: 000100b7 lui ra,0x10 + 80002e4c: f010809b addiw ra,ra,-255 + 80002e50: 01009093 slli ra,ra,0x10 + 80002e54: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002e58: 0020ff33 and t5,ra,sp + 80002e5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e60: 00200293 li t0,2 + 80002e64: fc521ee3 bne tp,t0,80002e40 + 80002e68: 0f001eb7 lui t4,0xf001 + 80002e6c: f00e8e9b addiw t4,t4,-256 + 80002e70: 01200193 li gp,18 + 80002e74: 1bdf1663 bne t5,t4,80003020 + +0000000080002e78 : + 80002e78: 00000213 li tp,0 + 80002e7c: 000f1137 lui sp,0xf1 + 80002e80: f0f1011b addiw sp,sp,-241 + 80002e84: 00c11113 slli sp,sp,0xc + 80002e88: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002e8c: 0ff010b7 lui ra,0xff01 + 80002e90: ff00809b addiw ra,ra,-16 + 80002e94: 00000013 nop + 80002e98: 0020ff33 and t5,ra,sp + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fc521ce3 bne tp,t0,80002e7c + 80002ea8: 00f00eb7 lui t4,0xf00 + 80002eac: 0f0e8e9b addiw t4,t4,240 + 80002eb0: 01300193 li gp,19 + 80002eb4: 17df1663 bne t5,t4,80003020 + +0000000080002eb8 : + 80002eb8: 00000213 li tp,0 + 80002ebc: 0f0f1137 lui sp,0xf0f1 + 80002ec0: f0f1011b addiw sp,sp,-241 + 80002ec4: 00ff00b7 lui ra,0xff0 + 80002ec8: 0ff0809b addiw ra,ra,255 + 80002ecc: 00000013 nop + 80002ed0: 00000013 nop + 80002ed4: 0020ff33 and t5,ra,sp + 80002ed8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002edc: 00200293 li t0,2 + 80002ee0: fc521ee3 bne tp,t0,80002ebc + 80002ee4: 000f0eb7 lui t4,0xf0 + 80002ee8: 00fe8e9b addiw t4,t4,15 + 80002eec: 01400193 li gp,20 + 80002ef0: 13df1863 bne t5,t4,80003020 + +0000000080002ef4 : + 80002ef4: 00000213 li tp,0 + 80002ef8: 0f0f1137 lui sp,0xf0f1 + 80002efc: f0f1011b addiw sp,sp,-241 + 80002f00: 00000013 nop + 80002f04: 000100b7 lui ra,0x10 + 80002f08: f010809b addiw ra,ra,-255 + 80002f0c: 01009093 slli ra,ra,0x10 + 80002f10: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002f14: 0020ff33 and t5,ra,sp + 80002f18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f1c: 00200293 li t0,2 + 80002f20: fc521ce3 bne tp,t0,80002ef8 + 80002f24: 0f001eb7 lui t4,0xf001 + 80002f28: f00e8e9b addiw t4,t4,-256 + 80002f2c: 01500193 li gp,21 + 80002f30: 0fdf1863 bne t5,t4,80003020 + +0000000080002f34 : + 80002f34: 00000213 li tp,0 + 80002f38: 000f1137 lui sp,0xf1 + 80002f3c: f0f1011b addiw sp,sp,-241 + 80002f40: 00c11113 slli sp,sp,0xc + 80002f44: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002f48: 00000013 nop + 80002f4c: 0ff010b7 lui ra,0xff01 + 80002f50: ff00809b addiw ra,ra,-16 + 80002f54: 00000013 nop + 80002f58: 0020ff33 and t5,ra,sp + 80002f5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f60: 00200293 li t0,2 + 80002f64: fc521ae3 bne tp,t0,80002f38 + 80002f68: 00f00eb7 lui t4,0xf00 + 80002f6c: 0f0e8e9b addiw t4,t4,240 + 80002f70: 01600193 li gp,22 + 80002f74: 0bdf1663 bne t5,t4,80003020 + +0000000080002f78 : + 80002f78: 00000213 li tp,0 + 80002f7c: 0f0f1137 lui sp,0xf0f1 + 80002f80: f0f1011b addiw sp,sp,-241 + 80002f84: 00000013 nop + 80002f88: 00000013 nop + 80002f8c: 00ff00b7 lui ra,0xff0 + 80002f90: 0ff0809b addiw ra,ra,255 + 80002f94: 0020ff33 and t5,ra,sp + 80002f98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f9c: 00200293 li t0,2 + 80002fa0: fc521ee3 bne tp,t0,80002f7c + 80002fa4: 000f0eb7 lui t4,0xf0 + 80002fa8: 00fe8e9b addiw t4,t4,15 + 80002fac: 01700193 li gp,23 + 80002fb0: 07df1863 bne t5,t4,80003020 + +0000000080002fb4 : + 80002fb4: 000100b7 lui ra,0x10 + 80002fb8: f010809b addiw ra,ra,-255 + 80002fbc: 01009093 slli ra,ra,0x10 + 80002fc0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002fc4: 00107133 and sp,zero,ra + 80002fc8: 00000e93 li t4,0 + 80002fcc: 01800193 li gp,24 + 80002fd0: 05d11863 bne sp,t4,80003020 + +0000000080002fd4 : + 80002fd4: 00ff00b7 lui ra,0xff0 + 80002fd8: 0ff0809b addiw ra,ra,255 + 80002fdc: 0000f133 and sp,ra,zero + 80002fe0: 00000e93 li t4,0 + 80002fe4: 01900193 li gp,25 + 80002fe8: 03d11c63 bne sp,t4,80003020 + +0000000080002fec : + 80002fec: 000070b3 and ra,zero,zero + 80002ff0: 00000e93 li t4,0 + 80002ff4: 01a00193 li gp,26 + 80002ff8: 03d09463 bne ra,t4,80003020 + +0000000080002ffc : + 80002ffc: 111110b7 lui ra,0x11111 + 80003000: 1110809b addiw ra,ra,273 + 80003004: 22222137 lui sp,0x22222 + 80003008: 2221011b addiw sp,sp,546 + 8000300c: 0020f033 and zero,ra,sp + 80003010: 00000e93 li t4,0 + 80003014: 01b00193 li gp,27 + 80003018: 01d01463 bne zero,t4,80003020 + 8000301c: 00301a63 bne zero,gp,80003030 + +0000000080003020 : + 80003020: 00119513 slli a0,gp,0x1 + 80003024: 00050063 beqz a0,80003024 + 80003028: 00156513 ori a0,a0,1 + 8000302c: 00000073 ecall + +0000000080003030 : + 80003030: 00100513 li a0,1 + 80003034: 00000073 ecall + 80003038: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-and.elf b/test/riscv/tests/rv64ui-v-and.elf new file mode 100644 index 00000000..2cf4f37d Binary files /dev/null and b/test/riscv/tests/rv64ui-v-and.elf differ diff --git a/test/riscv/tests/rv64ui-v-andi.dump b/test/riscv/tests/rv64ui-v-andi.dump new file mode 100644 index 00000000..6503a378 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-andi.dump @@ -0,0 +1,990 @@ + +rv64ui-v-andi: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 88868693 addi a3,a3,-1912 # 80002ce0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 8bc60613 addi a2,a2,-1860 # 80002d70 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 88460613 addi a2,a2,-1916 # 80002d88 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 7d468693 addi a3,a3,2004 # 80002d28 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 7f068693 addi a3,a3,2032 # 80002e60 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 77060613 addi a2,a2,1904 # 80002e38 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 6a468693 addi a3,a3,1700 # 80002e90 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 5c468693 addi a3,a3,1476 # 80002e00 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 55468693 addi a3,a3,1364 # 80002dc8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01a00793 li a5,26 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 069897b7 lui a5,0x6989 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 68978793 addi a5,a5,1673 # 6989689 <_start-0x79676977> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000100b7 lui ra,0x10 + 80002acc: f010809b addiw ra,ra,-255 + 80002ad0: 01009093 slli ra,ra,0x10 + 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002ad8: f0f0ff13 andi t5,ra,-241 + 80002adc: 00010eb7 lui t4,0x10 + 80002ae0: f01e8e9b addiw t4,t4,-255 + 80002ae4: 010e9e93 slli t4,t4,0x10 + 80002ae8: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002aec: 00200193 li gp,2 + 80002af0: 1ddf1863 bne t5,t4,80002cc0 + +0000000080002af4 : + 80002af4: 0ff010b7 lui ra,0xff01 + 80002af8: ff00809b addiw ra,ra,-16 + 80002afc: 0f00ff13 andi t5,ra,240 + 80002b00: 0f000e93 li t4,240 + 80002b04: 00300193 li gp,3 + 80002b08: 1bdf1c63 bne t5,t4,80002cc0 + +0000000080002b0c : + 80002b0c: 00ff00b7 lui ra,0xff0 + 80002b10: 0ff0809b addiw ra,ra,255 + 80002b14: 70f0ff13 andi t5,ra,1807 + 80002b18: 00f00e93 li t4,15 + 80002b1c: 00400193 li gp,4 + 80002b20: 1bdf1063 bne t5,t4,80002cc0 + +0000000080002b24 : + 80002b24: 000f00b7 lui ra,0xf0 + 80002b28: 0ff0809b addiw ra,ra,255 + 80002b2c: 00c09093 slli ra,ra,0xc + 80002b30: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002b34: 0f00ff13 andi t5,ra,240 + 80002b38: 00000e93 li t4,0 + 80002b3c: 00500193 li gp,5 + 80002b40: 19df1063 bne t5,t4,80002cc0 + +0000000080002b44 : + 80002b44: 000100b7 lui ra,0x10 + 80002b48: f010809b addiw ra,ra,-255 + 80002b4c: 01009093 slli ra,ra,0x10 + 80002b50: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002b54: 0f00f093 andi ra,ra,240 + 80002b58: 00000e93 li t4,0 + 80002b5c: 00600193 li gp,6 + 80002b60: 17d09063 bne ra,t4,80002cc0 + +0000000080002b64 : + 80002b64: 00000213 li tp,0 + 80002b68: 0ff010b7 lui ra,0xff01 + 80002b6c: ff00809b addiw ra,ra,-16 + 80002b70: 70f0ff13 andi t5,ra,1807 + 80002b74: 000f0313 mv t1,t5 + 80002b78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b7c: 00200293 li t0,2 + 80002b80: fe5214e3 bne tp,t0,80002b68 + 80002b84: 70000e93 li t4,1792 + 80002b88: 00700193 li gp,7 + 80002b8c: 13d31a63 bne t1,t4,80002cc0 + +0000000080002b90 : + 80002b90: 00000213 li tp,0 + 80002b94: 00ff00b7 lui ra,0xff0 + 80002b98: 0ff0809b addiw ra,ra,255 + 80002b9c: 0f00ff13 andi t5,ra,240 + 80002ba0: 00000013 nop + 80002ba4: 000f0313 mv t1,t5 + 80002ba8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bac: 00200293 li t0,2 + 80002bb0: fe5212e3 bne tp,t0,80002b94 + 80002bb4: 0f000e93 li t4,240 + 80002bb8: 00800193 li gp,8 + 80002bbc: 11d31263 bne t1,t4,80002cc0 + +0000000080002bc0 : + 80002bc0: 00000213 li tp,0 + 80002bc4: 000f00b7 lui ra,0xf0 + 80002bc8: 0ff0809b addiw ra,ra,255 + 80002bcc: 00c09093 slli ra,ra,0xc + 80002bd0: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002bd4: f0f0ff13 andi t5,ra,-241 + 80002bd8: 00000013 nop + 80002bdc: 00000013 nop + 80002be0: 000f0313 mv t1,t5 + 80002be4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002be8: 00200293 li t0,2 + 80002bec: fc521ce3 bne tp,t0,80002bc4 + 80002bf0: 000f0eb7 lui t4,0xf0 + 80002bf4: 0ffe8e9b addiw t4,t4,255 + 80002bf8: 00ce9e93 slli t4,t4,0xc + 80002bfc: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002c00: 00900193 li gp,9 + 80002c04: 0bd31e63 bne t1,t4,80002cc0 + +0000000080002c08 : + 80002c08: 00000213 li tp,0 + 80002c0c: 0ff010b7 lui ra,0xff01 + 80002c10: ff00809b addiw ra,ra,-16 + 80002c14: 70f0ff13 andi t5,ra,1807 + 80002c18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c1c: 00200293 li t0,2 + 80002c20: fe5216e3 bne tp,t0,80002c0c + 80002c24: 70000e93 li t4,1792 + 80002c28: 00a00193 li gp,10 + 80002c2c: 09df1a63 bne t5,t4,80002cc0 + +0000000080002c30 : + 80002c30: 00000213 li tp,0 + 80002c34: 00ff00b7 lui ra,0xff0 + 80002c38: 0ff0809b addiw ra,ra,255 + 80002c3c: 00000013 nop + 80002c40: 0f00ff13 andi t5,ra,240 + 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c48: 00200293 li t0,2 + 80002c4c: fe5214e3 bne tp,t0,80002c34 + 80002c50: 0f000e93 li t4,240 + 80002c54: 00b00193 li gp,11 + 80002c58: 07df1463 bne t5,t4,80002cc0 + +0000000080002c5c : + 80002c5c: 00000213 li tp,0 + 80002c60: 000f00b7 lui ra,0xf0 + 80002c64: 0ff0809b addiw ra,ra,255 + 80002c68: 00c09093 slli ra,ra,0xc + 80002c6c: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002c70: 00000013 nop + 80002c74: 00000013 nop + 80002c78: 70f0ff13 andi t5,ra,1807 + 80002c7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c80: 00200293 li t0,2 + 80002c84: fc521ee3 bne tp,t0,80002c60 + 80002c88: 00f00e93 li t4,15 + 80002c8c: 00c00193 li gp,12 + 80002c90: 03df1863 bne t5,t4,80002cc0 + +0000000080002c94 : + 80002c94: 0f007093 andi ra,zero,240 + 80002c98: 00000e93 li t4,0 + 80002c9c: 00d00193 li gp,13 + 80002ca0: 03d09063 bne ra,t4,80002cc0 + +0000000080002ca4 : + 80002ca4: 00ff00b7 lui ra,0xff0 + 80002ca8: 0ff0809b addiw ra,ra,255 + 80002cac: 70f0f013 andi zero,ra,1807 + 80002cb0: 00000e93 li t4,0 + 80002cb4: 00e00193 li gp,14 + 80002cb8: 01d01463 bne zero,t4,80002cc0 + 80002cbc: 00301a63 bne zero,gp,80002cd0 + +0000000080002cc0 : + 80002cc0: 00119513 slli a0,gp,0x1 + 80002cc4: 00050063 beqz a0,80002cc4 + 80002cc8: 00156513 ori a0,a0,1 + 80002ccc: 00000073 ecall + +0000000080002cd0 : + 80002cd0: 00100513 li a0,1 + 80002cd4: 00000073 ecall + 80002cd8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-andi.elf b/test/riscv/tests/rv64ui-v-andi.elf new file mode 100644 index 00000000..02ec3d50 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-andi.elf differ diff --git a/test/riscv/tests/rv64ui-v-auipc.dump b/test/riscv/tests/rv64ui-v-auipc.dump new file mode 100644 index 00000000..bfa19dda --- /dev/null +++ b/test/riscv/tests/rv64ui-v-auipc.dump @@ -0,0 +1,859 @@ + +rv64ui-v-auipc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6d068693 addi a3,a3,1744 # 80002b28 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 70460613 addi a2,a2,1796 # 80002bb8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6cc60613 addi a2,a2,1740 # 80002bd0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 61c68693 addi a3,a3,1564 # 80002b70 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 63868693 addi a3,a3,1592 # 80002ca8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5b860613 addi a2,a2,1464 # 80002c80 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 4ec68693 addi a3,a3,1260 # 80002cd8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 40c68693 addi a3,a3,1036 # 80002c48 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 39c68693 addi a3,a3,924 # 80002c10 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02a00793 li a5,42 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0962a7b7 lui a5,0x962a + 80002a70: 000805b7 lui a1,0x80 + 80002a74: af278793 addi a5,a5,-1294 # 9629af2 <_start-0x769d650e> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00002517 auipc a0,0x2 + 80002acc: 71c50513 addi a0,a0,1820 # 800051e4 + 80002ad0: 004005ef jal a1,80002ad4 + 80002ad4: 40b50533 sub a0,a0,a1 + 80002ad8: 00002eb7 lui t4,0x2 + 80002adc: 710e8e9b addiw t4,t4,1808 + 80002ae0: 00200193 li gp,2 + 80002ae4: 03d51463 bne a0,t4,80002b0c + +0000000080002ae8 : + 80002ae8: ffffe517 auipc a0,0xffffe + 80002aec: 8fc50513 addi a0,a0,-1796 # 800003e4 + 80002af0: 004005ef jal a1,80002af4 + 80002af4: 40b50533 sub a0,a0,a1 + 80002af8: ffffeeb7 lui t4,0xffffe + 80002afc: 8f0e8e9b addiw t4,t4,-1808 + 80002b00: 00300193 li gp,3 + 80002b04: 01d51463 bne a0,t4,80002b0c + 80002b08: 00301a63 bne zero,gp,80002b1c + +0000000080002b0c : + 80002b0c: 00119513 slli a0,gp,0x1 + 80002b10: 00050063 beqz a0,80002b10 + 80002b14: 00156513 ori a0,a0,1 + 80002b18: 00000073 ecall + +0000000080002b1c : + 80002b1c: 00100513 li a0,1 + 80002b20: 00000073 ecall + 80002b24: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-auipc.elf b/test/riscv/tests/rv64ui-v-auipc.elf new file mode 100644 index 00000000..e0fc7d11 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-auipc.elf differ diff --git a/test/riscv/tests/rv64ui-v-beq.dump b/test/riscv/tests/rv64ui-v-beq.dump new file mode 100644 index 00000000..18ece1e2 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-beq.dump @@ -0,0 +1,1054 @@ + +rv64ui-v-beq: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 61c68693 addi a3,a3,1564 # 80002e90 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03400793 li a5,52 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 029747b7 lui a5,0x2974 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 93378793 addi a5,a5,-1741 # 2973933 <_start-0x7d68c6cd> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00000113 li sp,0 + 80002ad4: 00208663 beq ra,sp,80002ae0 + 80002ad8: 2a301863 bne zero,gp,80002d88 + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe208ee3 beq ra,sp,80002adc + 80002ae4: 2a301263 bne zero,gp,80002d88 + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: 00100093 li ra,1 + 80002af0: 00100113 li sp,1 + 80002af4: 00208663 beq ra,sp,80002b00 + 80002af8: 28301863 bne zero,gp,80002d88 + 80002afc: 00301663 bne zero,gp,80002b08 + 80002b00: fe208ee3 beq ra,sp,80002afc + 80002b04: 28301263 bne zero,gp,80002d88 + +0000000080002b08 : + 80002b08: 00400193 li gp,4 + 80002b0c: fff00093 li ra,-1 + 80002b10: fff00113 li sp,-1 + 80002b14: 00208663 beq ra,sp,80002b20 + 80002b18: 26301863 bne zero,gp,80002d88 + 80002b1c: 00301663 bne zero,gp,80002b28 + 80002b20: fe208ee3 beq ra,sp,80002b1c + 80002b24: 26301263 bne zero,gp,80002d88 + +0000000080002b28 : + 80002b28: 00500193 li gp,5 + 80002b2c: 00000093 li ra,0 + 80002b30: 00100113 li sp,1 + 80002b34: 00208463 beq ra,sp,80002b3c + 80002b38: 00301463 bne zero,gp,80002b40 + 80002b3c: 24301663 bne zero,gp,80002d88 + 80002b40: fe208ee3 beq ra,sp,80002b3c + +0000000080002b44 : + 80002b44: 00600193 li gp,6 + 80002b48: 00100093 li ra,1 + 80002b4c: 00000113 li sp,0 + 80002b50: 00208463 beq ra,sp,80002b58 + 80002b54: 00301463 bne zero,gp,80002b5c + 80002b58: 22301863 bne zero,gp,80002d88 + 80002b5c: fe208ee3 beq ra,sp,80002b58 + +0000000080002b60 : + 80002b60: 00700193 li gp,7 + 80002b64: fff00093 li ra,-1 + 80002b68: 00100113 li sp,1 + 80002b6c: 00208463 beq ra,sp,80002b74 + 80002b70: 00301463 bne zero,gp,80002b78 + 80002b74: 20301a63 bne zero,gp,80002d88 + 80002b78: fe208ee3 beq ra,sp,80002b74 + +0000000080002b7c : + 80002b7c: 00800193 li gp,8 + 80002b80: 00100093 li ra,1 + 80002b84: fff00113 li sp,-1 + 80002b88: 00208463 beq ra,sp,80002b90 + 80002b8c: 00301463 bne zero,gp,80002b94 + 80002b90: 1e301c63 bne zero,gp,80002d88 + 80002b94: fe208ee3 beq ra,sp,80002b90 + +0000000080002b98 : + 80002b98: 00900193 li gp,9 + 80002b9c: 00000213 li tp,0 + 80002ba0: 00000093 li ra,0 + 80002ba4: fff00113 li sp,-1 + 80002ba8: 1e208063 beq ra,sp,80002d88 + 80002bac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bb0: 00200293 li t0,2 + 80002bb4: fe5216e3 bne tp,t0,80002ba0 + +0000000080002bb8 : + 80002bb8: 00a00193 li gp,10 + 80002bbc: 00000213 li tp,0 + 80002bc0: 00000093 li ra,0 + 80002bc4: fff00113 li sp,-1 + 80002bc8: 00000013 nop + 80002bcc: 1a208e63 beq ra,sp,80002d88 + 80002bd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd4: 00200293 li t0,2 + 80002bd8: fe5214e3 bne tp,t0,80002bc0 + +0000000080002bdc : + 80002bdc: 00b00193 li gp,11 + 80002be0: 00000213 li tp,0 + 80002be4: 00000093 li ra,0 + 80002be8: fff00113 li sp,-1 + 80002bec: 00000013 nop + 80002bf0: 00000013 nop + 80002bf4: 18208a63 beq ra,sp,80002d88 + 80002bf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bfc: 00200293 li t0,2 + 80002c00: fe5212e3 bne tp,t0,80002be4 + +0000000080002c04 : + 80002c04: 00c00193 li gp,12 + 80002c08: 00000213 li tp,0 + 80002c0c: 00000093 li ra,0 + 80002c10: 00000013 nop + 80002c14: fff00113 li sp,-1 + 80002c18: 16208863 beq ra,sp,80002d88 + 80002c1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c20: 00200293 li t0,2 + 80002c24: fe5214e3 bne tp,t0,80002c0c + +0000000080002c28 : + 80002c28: 00d00193 li gp,13 + 80002c2c: 00000213 li tp,0 + 80002c30: 00000093 li ra,0 + 80002c34: 00000013 nop + 80002c38: fff00113 li sp,-1 + 80002c3c: 00000013 nop + 80002c40: 14208463 beq ra,sp,80002d88 + 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c48: 00200293 li t0,2 + 80002c4c: fe5212e3 bne tp,t0,80002c30 + +0000000080002c50 : + 80002c50: 00e00193 li gp,14 + 80002c54: 00000213 li tp,0 + 80002c58: 00000093 li ra,0 + 80002c5c: 00000013 nop + 80002c60: 00000013 nop + 80002c64: fff00113 li sp,-1 + 80002c68: 12208063 beq ra,sp,80002d88 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5212e3 bne tp,t0,80002c58 + +0000000080002c78 : + 80002c78: 00f00193 li gp,15 + 80002c7c: 00000213 li tp,0 + 80002c80: 00000093 li ra,0 + 80002c84: fff00113 li sp,-1 + 80002c88: 10208063 beq ra,sp,80002d88 + 80002c8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c90: 00200293 li t0,2 + 80002c94: fe5216e3 bne tp,t0,80002c80 + +0000000080002c98 : + 80002c98: 01000193 li gp,16 + 80002c9c: 00000213 li tp,0 + 80002ca0: 00000093 li ra,0 + 80002ca4: fff00113 li sp,-1 + 80002ca8: 00000013 nop + 80002cac: 0c208e63 beq ra,sp,80002d88 + 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cb4: 00200293 li t0,2 + 80002cb8: fe5214e3 bne tp,t0,80002ca0 + +0000000080002cbc : + 80002cbc: 01100193 li gp,17 + 80002cc0: 00000213 li tp,0 + 80002cc4: 00000093 li ra,0 + 80002cc8: fff00113 li sp,-1 + 80002ccc: 00000013 nop + 80002cd0: 00000013 nop + 80002cd4: 0a208a63 beq ra,sp,80002d88 + 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cdc: 00200293 li t0,2 + 80002ce0: fe5212e3 bne tp,t0,80002cc4 + +0000000080002ce4 : + 80002ce4: 01200193 li gp,18 + 80002ce8: 00000213 li tp,0 + 80002cec: 00000093 li ra,0 + 80002cf0: 00000013 nop + 80002cf4: fff00113 li sp,-1 + 80002cf8: 08208863 beq ra,sp,80002d88 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fe5214e3 bne tp,t0,80002cec + +0000000080002d08 : + 80002d08: 01300193 li gp,19 + 80002d0c: 00000213 li tp,0 + 80002d10: 00000093 li ra,0 + 80002d14: 00000013 nop + 80002d18: fff00113 li sp,-1 + 80002d1c: 00000013 nop + 80002d20: 06208463 beq ra,sp,80002d88 + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5212e3 bne tp,t0,80002d10 + +0000000080002d30 : + 80002d30: 01400193 li gp,20 + 80002d34: 00000213 li tp,0 + 80002d38: 00000093 li ra,0 + 80002d3c: 00000013 nop + 80002d40: 00000013 nop + 80002d44: fff00113 li sp,-1 + 80002d48: 04208063 beq ra,sp,80002d88 + 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d50: 00200293 li t0,2 + 80002d54: fe5212e3 bne tp,t0,80002d38 + +0000000080002d58 : + 80002d58: 00100093 li ra,1 + 80002d5c: 00000a63 beqz zero,80002d70 + 80002d60: 00108093 addi ra,ra,1 + 80002d64: 00108093 addi ra,ra,1 + 80002d68: 00108093 addi ra,ra,1 + 80002d6c: 00108093 addi ra,ra,1 + 80002d70: 00108093 addi ra,ra,1 + 80002d74: 00108093 addi ra,ra,1 + 80002d78: 00300e93 li t4,3 + 80002d7c: 01500193 li gp,21 + 80002d80: 01d09463 bne ra,t4,80002d88 + 80002d84: 00301a63 bne zero,gp,80002d98 + +0000000080002d88 : + 80002d88: 00119513 slli a0,gp,0x1 + 80002d8c: 00050063 beqz a0,80002d8c + 80002d90: 00156513 ori a0,a0,1 + 80002d94: 00000073 ecall + +0000000080002d98 : + 80002d98: 00100513 li a0,1 + 80002d9c: 00000073 ecall + 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-beq.elf b/test/riscv/tests/rv64ui-v-beq.elf new file mode 100644 index 00000000..a64100b1 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-beq.elf differ diff --git a/test/riscv/tests/rv64ui-v-bge.dump b/test/riscv/tests/rv64ui-v-bge.dump new file mode 100644 index 00000000..58215260 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-bge.dump @@ -0,0 +1,1084 @@ + +rv64ui-v-bge: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 9b068693 addi a3,a3,-1616 # 80002e08 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 9e460613 addi a2,a2,-1564 # 80002e98 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 9ac60613 addi a2,a2,-1620 # 80002eb0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 8fc68693 addi a3,a3,-1796 # 80002e50 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 91868693 addi a3,a3,-1768 # 80002f88 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 89860613 addi a2,a2,-1896 # 80002f60 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 7cc68693 addi a3,a3,1996 # 80002fb8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 6ec68693 addi a3,a3,1772 # 80002f28 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 67c68693 addi a3,a3,1660 # 80002ef0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01f00793 li a5,31 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 05e177b7 lui a5,0x5e17 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 4f578793 addi a5,a5,1269 # 5e174f5 <_start-0x7a1e8b0b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00000113 li sp,0 + 80002ad4: 0020d663 ble sp,ra,80002ae0 + 80002ad8: 30301863 bne zero,gp,80002de8 + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe20dee3 ble sp,ra,80002adc + 80002ae4: 30301263 bne zero,gp,80002de8 + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: 00100093 li ra,1 + 80002af0: 00100113 li sp,1 + 80002af4: 0020d663 ble sp,ra,80002b00 + 80002af8: 2e301863 bne zero,gp,80002de8 + 80002afc: 00301663 bne zero,gp,80002b08 + 80002b00: fe20dee3 ble sp,ra,80002afc + 80002b04: 2e301263 bne zero,gp,80002de8 + +0000000080002b08 : + 80002b08: 00400193 li gp,4 + 80002b0c: fff00093 li ra,-1 + 80002b10: fff00113 li sp,-1 + 80002b14: 0020d663 ble sp,ra,80002b20 + 80002b18: 2c301863 bne zero,gp,80002de8 + 80002b1c: 00301663 bne zero,gp,80002b28 + 80002b20: fe20dee3 ble sp,ra,80002b1c + 80002b24: 2c301263 bne zero,gp,80002de8 + +0000000080002b28 : + 80002b28: 00500193 li gp,5 + 80002b2c: 00100093 li ra,1 + 80002b30: 00000113 li sp,0 + 80002b34: 0020d663 ble sp,ra,80002b40 + 80002b38: 2a301863 bne zero,gp,80002de8 + 80002b3c: 00301663 bne zero,gp,80002b48 + 80002b40: fe20dee3 ble sp,ra,80002b3c + 80002b44: 2a301263 bne zero,gp,80002de8 + +0000000080002b48 : + 80002b48: 00600193 li gp,6 + 80002b4c: 00100093 li ra,1 + 80002b50: fff00113 li sp,-1 + 80002b54: 0020d663 ble sp,ra,80002b60 + 80002b58: 28301863 bne zero,gp,80002de8 + 80002b5c: 00301663 bne zero,gp,80002b68 + 80002b60: fe20dee3 ble sp,ra,80002b5c + 80002b64: 28301263 bne zero,gp,80002de8 + +0000000080002b68 : + 80002b68: 00700193 li gp,7 + 80002b6c: fff00093 li ra,-1 + 80002b70: ffe00113 li sp,-2 + 80002b74: 0020d663 ble sp,ra,80002b80 + 80002b78: 26301863 bne zero,gp,80002de8 + 80002b7c: 00301663 bne zero,gp,80002b88 + 80002b80: fe20dee3 ble sp,ra,80002b7c + 80002b84: 26301263 bne zero,gp,80002de8 + +0000000080002b88 : + 80002b88: 00800193 li gp,8 + 80002b8c: 00000093 li ra,0 + 80002b90: 00100113 li sp,1 + 80002b94: 0020d463 ble sp,ra,80002b9c + 80002b98: 00301463 bne zero,gp,80002ba0 + 80002b9c: 24301663 bne zero,gp,80002de8 + 80002ba0: fe20dee3 ble sp,ra,80002b9c + +0000000080002ba4 : + 80002ba4: 00900193 li gp,9 + 80002ba8: fff00093 li ra,-1 + 80002bac: 00100113 li sp,1 + 80002bb0: 0020d463 ble sp,ra,80002bb8 + 80002bb4: 00301463 bne zero,gp,80002bbc + 80002bb8: 22301863 bne zero,gp,80002de8 + 80002bbc: fe20dee3 ble sp,ra,80002bb8 + +0000000080002bc0 : + 80002bc0: 00a00193 li gp,10 + 80002bc4: ffe00093 li ra,-2 + 80002bc8: fff00113 li sp,-1 + 80002bcc: 0020d463 ble sp,ra,80002bd4 + 80002bd0: 00301463 bne zero,gp,80002bd8 + 80002bd4: 20301a63 bne zero,gp,80002de8 + 80002bd8: fe20dee3 ble sp,ra,80002bd4 + +0000000080002bdc : + 80002bdc: 00b00193 li gp,11 + 80002be0: ffe00093 li ra,-2 + 80002be4: 00100113 li sp,1 + 80002be8: 0020d463 ble sp,ra,80002bf0 + 80002bec: 00301463 bne zero,gp,80002bf4 + 80002bf0: 1e301c63 bne zero,gp,80002de8 + 80002bf4: fe20dee3 ble sp,ra,80002bf0 + +0000000080002bf8 : + 80002bf8: 00c00193 li gp,12 + 80002bfc: 00000213 li tp,0 + 80002c00: fff00093 li ra,-1 + 80002c04: 00000113 li sp,0 + 80002c08: 1e20d063 ble sp,ra,80002de8 + 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c10: 00200293 li t0,2 + 80002c14: fe5216e3 bne tp,t0,80002c00 + +0000000080002c18 : + 80002c18: 00d00193 li gp,13 + 80002c1c: 00000213 li tp,0 + 80002c20: fff00093 li ra,-1 + 80002c24: 00000113 li sp,0 + 80002c28: 00000013 nop + 80002c2c: 1a20de63 ble sp,ra,80002de8 + 80002c30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c34: 00200293 li t0,2 + 80002c38: fe5214e3 bne tp,t0,80002c20 + +0000000080002c3c : + 80002c3c: 00e00193 li gp,14 + 80002c40: 00000213 li tp,0 + 80002c44: fff00093 li ra,-1 + 80002c48: 00000113 li sp,0 + 80002c4c: 00000013 nop + 80002c50: 00000013 nop + 80002c54: 1820da63 ble sp,ra,80002de8 + 80002c58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c5c: 00200293 li t0,2 + 80002c60: fe5212e3 bne tp,t0,80002c44 + +0000000080002c64 : + 80002c64: 00f00193 li gp,15 + 80002c68: 00000213 li tp,0 + 80002c6c: fff00093 li ra,-1 + 80002c70: 00000013 nop + 80002c74: 00000113 li sp,0 + 80002c78: 1620d863 ble sp,ra,80002de8 + 80002c7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c80: 00200293 li t0,2 + 80002c84: fe5214e3 bne tp,t0,80002c6c + +0000000080002c88 : + 80002c88: 01000193 li gp,16 + 80002c8c: 00000213 li tp,0 + 80002c90: fff00093 li ra,-1 + 80002c94: 00000013 nop + 80002c98: 00000113 li sp,0 + 80002c9c: 00000013 nop + 80002ca0: 1420d463 ble sp,ra,80002de8 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5212e3 bne tp,t0,80002c90 + +0000000080002cb0 : + 80002cb0: 01100193 li gp,17 + 80002cb4: 00000213 li tp,0 + 80002cb8: fff00093 li ra,-1 + 80002cbc: 00000013 nop + 80002cc0: 00000013 nop + 80002cc4: 00000113 li sp,0 + 80002cc8: 1220d063 ble sp,ra,80002de8 + 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd0: 00200293 li t0,2 + 80002cd4: fe5212e3 bne tp,t0,80002cb8 + +0000000080002cd8 : + 80002cd8: 01200193 li gp,18 + 80002cdc: 00000213 li tp,0 + 80002ce0: fff00093 li ra,-1 + 80002ce4: 00000113 li sp,0 + 80002ce8: 1020d063 ble sp,ra,80002de8 + 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf0: 00200293 li t0,2 + 80002cf4: fe5216e3 bne tp,t0,80002ce0 + +0000000080002cf8 : + 80002cf8: 01300193 li gp,19 + 80002cfc: 00000213 li tp,0 + 80002d00: fff00093 li ra,-1 + 80002d04: 00000113 li sp,0 + 80002d08: 00000013 nop + 80002d0c: 0c20de63 ble sp,ra,80002de8 + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fe5214e3 bne tp,t0,80002d00 + +0000000080002d1c : + 80002d1c: 01400193 li gp,20 + 80002d20: 00000213 li tp,0 + 80002d24: fff00093 li ra,-1 + 80002d28: 00000113 li sp,0 + 80002d2c: 00000013 nop + 80002d30: 00000013 nop + 80002d34: 0a20da63 ble sp,ra,80002de8 + 80002d38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d3c: 00200293 li t0,2 + 80002d40: fe5212e3 bne tp,t0,80002d24 + +0000000080002d44 : + 80002d44: 01500193 li gp,21 + 80002d48: 00000213 li tp,0 + 80002d4c: fff00093 li ra,-1 + 80002d50: 00000013 nop + 80002d54: 00000113 li sp,0 + 80002d58: 0820d863 ble sp,ra,80002de8 + 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d60: 00200293 li t0,2 + 80002d64: fe5214e3 bne tp,t0,80002d4c + +0000000080002d68 : + 80002d68: 01600193 li gp,22 + 80002d6c: 00000213 li tp,0 + 80002d70: fff00093 li ra,-1 + 80002d74: 00000013 nop + 80002d78: 00000113 li sp,0 + 80002d7c: 00000013 nop + 80002d80: 0620d463 ble sp,ra,80002de8 + 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d88: 00200293 li t0,2 + 80002d8c: fe5212e3 bne tp,t0,80002d70 + +0000000080002d90 : + 80002d90: 01700193 li gp,23 + 80002d94: 00000213 li tp,0 + 80002d98: fff00093 li ra,-1 + 80002d9c: 00000013 nop + 80002da0: 00000013 nop + 80002da4: 00000113 li sp,0 + 80002da8: 0420d063 ble sp,ra,80002de8 + 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db0: 00200293 li t0,2 + 80002db4: fe5212e3 bne tp,t0,80002d98 + +0000000080002db8 : + 80002db8: 00100093 li ra,1 + 80002dbc: 0000da63 bgez ra,80002dd0 + 80002dc0: 00108093 addi ra,ra,1 + 80002dc4: 00108093 addi ra,ra,1 + 80002dc8: 00108093 addi ra,ra,1 + 80002dcc: 00108093 addi ra,ra,1 + 80002dd0: 00108093 addi ra,ra,1 + 80002dd4: 00108093 addi ra,ra,1 + 80002dd8: 00300e93 li t4,3 + 80002ddc: 01800193 li gp,24 + 80002de0: 01d09463 bne ra,t4,80002de8 + 80002de4: 00301a63 bne zero,gp,80002df8 + +0000000080002de8 : + 80002de8: 00119513 slli a0,gp,0x1 + 80002dec: 00050063 beqz a0,80002dec + 80002df0: 00156513 ori a0,a0,1 + 80002df4: 00000073 ecall + +0000000080002df8 : + 80002df8: 00100513 li a0,1 + 80002dfc: 00000073 ecall + 80002e00: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bge.elf b/test/riscv/tests/rv64ui-v-bge.elf new file mode 100644 index 00000000..74af9d1f Binary files /dev/null and b/test/riscv/tests/rv64ui-v-bge.elf differ diff --git a/test/riscv/tests/rv64ui-v-bgeu.dump b/test/riscv/tests/rv64ui-v-bgeu.dump new file mode 100644 index 00000000..9544e42f --- /dev/null +++ b/test/riscv/tests/rv64ui-v-bgeu.dump @@ -0,0 +1,1138 @@ + +rv64ui-v-bgeu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: a8868693 addi a3,a3,-1400 # 80002ee0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: abc60613 addi a2,a2,-1348 # 80002f70 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: a8460613 addi a2,a2,-1404 # 80002f88 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 9d468693 addi a3,a3,-1580 # 80002f28 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 9f068693 addi a3,a3,-1552 # 80003060 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 97060613 addi a2,a2,-1680 # 80003038 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 8a468693 addi a3,a3,-1884 # 80003090 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 7c468693 addi a3,a3,1988 # 80003000 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 75468693 addi a3,a3,1876 # 80002fc8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03d00793 li a5,61 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 02e567b7 lui a5,0x2e56 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: eb078793 addi a5,a5,-336 # 2e55eb0 <_start-0x7d1aa150> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00000113 li sp,0 + 80002ad4: 0020f663 bleu sp,ra,80002ae0 + 80002ad8: 3e301463 bne zero,gp,80002ec0 + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe20fee3 bleu sp,ra,80002adc + 80002ae4: 3c301e63 bne zero,gp,80002ec0 + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: 00100093 li ra,1 + 80002af0: 00100113 li sp,1 + 80002af4: 0020f663 bleu sp,ra,80002b00 + 80002af8: 3c301463 bne zero,gp,80002ec0 + 80002afc: 00301663 bne zero,gp,80002b08 + 80002b00: fe20fee3 bleu sp,ra,80002afc + 80002b04: 3a301e63 bne zero,gp,80002ec0 + +0000000080002b08 : + 80002b08: 00400193 li gp,4 + 80002b0c: 0010009b addiw ra,zero,1 + 80002b10: 02009093 slli ra,ra,0x20 + 80002b14: fff08093 addi ra,ra,-1 + 80002b18: 0010011b addiw sp,zero,1 + 80002b1c: 02011113 slli sp,sp,0x20 + 80002b20: fff10113 addi sp,sp,-1 + 80002b24: 0020f663 bleu sp,ra,80002b30 + 80002b28: 38301c63 bne zero,gp,80002ec0 + 80002b2c: 00301663 bne zero,gp,80002b38 + 80002b30: fe20fee3 bleu sp,ra,80002b2c + 80002b34: 38301663 bne zero,gp,80002ec0 + +0000000080002b38 : + 80002b38: 00500193 li gp,5 + 80002b3c: 00100093 li ra,1 + 80002b40: 00000113 li sp,0 + 80002b44: 0020f663 bleu sp,ra,80002b50 + 80002b48: 36301c63 bne zero,gp,80002ec0 + 80002b4c: 00301663 bne zero,gp,80002b58 + 80002b50: fe20fee3 bleu sp,ra,80002b4c + 80002b54: 36301663 bne zero,gp,80002ec0 + +0000000080002b58 : + 80002b58: 00600193 li gp,6 + 80002b5c: 0010009b addiw ra,zero,1 + 80002b60: 02009093 slli ra,ra,0x20 + 80002b64: fff08093 addi ra,ra,-1 + 80002b68: 0010011b addiw sp,zero,1 + 80002b6c: 02011113 slli sp,sp,0x20 + 80002b70: ffe10113 addi sp,sp,-2 + 80002b74: 0020f663 bleu sp,ra,80002b80 + 80002b78: 34301463 bne zero,gp,80002ec0 + 80002b7c: 00301663 bne zero,gp,80002b88 + 80002b80: fe20fee3 bleu sp,ra,80002b7c + 80002b84: 32301e63 bne zero,gp,80002ec0 + +0000000080002b88 : + 80002b88: 00700193 li gp,7 + 80002b8c: 0010009b addiw ra,zero,1 + 80002b90: 02009093 slli ra,ra,0x20 + 80002b94: fff08093 addi ra,ra,-1 + 80002b98: 00000113 li sp,0 + 80002b9c: 0020f663 bleu sp,ra,80002ba8 + 80002ba0: 32301063 bne zero,gp,80002ec0 + 80002ba4: 00301663 bne zero,gp,80002bb0 + 80002ba8: fe20fee3 bleu sp,ra,80002ba4 + 80002bac: 30301a63 bne zero,gp,80002ec0 + +0000000080002bb0 : + 80002bb0: 00800193 li gp,8 + 80002bb4: 00000093 li ra,0 + 80002bb8: 00100113 li sp,1 + 80002bbc: 0020f463 bleu sp,ra,80002bc4 + 80002bc0: 00301463 bne zero,gp,80002bc8 + 80002bc4: 2e301e63 bne zero,gp,80002ec0 + 80002bc8: fe20fee3 bleu sp,ra,80002bc4 + +0000000080002bcc : + 80002bcc: 00900193 li gp,9 + 80002bd0: 0010009b addiw ra,zero,1 + 80002bd4: 02009093 slli ra,ra,0x20 + 80002bd8: ffe08093 addi ra,ra,-2 + 80002bdc: 0010011b addiw sp,zero,1 + 80002be0: 02011113 slli sp,sp,0x20 + 80002be4: fff10113 addi sp,sp,-1 + 80002be8: 0020f463 bleu sp,ra,80002bf0 + 80002bec: 00301463 bne zero,gp,80002bf4 + 80002bf0: 2c301863 bne zero,gp,80002ec0 + 80002bf4: fe20fee3 bleu sp,ra,80002bf0 + +0000000080002bf8 : + 80002bf8: 00a00193 li gp,10 + 80002bfc: 00000093 li ra,0 + 80002c00: 0010011b addiw sp,zero,1 + 80002c04: 02011113 slli sp,sp,0x20 + 80002c08: fff10113 addi sp,sp,-1 + 80002c0c: 0020f463 bleu sp,ra,80002c14 + 80002c10: 00301463 bne zero,gp,80002c18 + 80002c14: 2a301663 bne zero,gp,80002ec0 + 80002c18: fe20fee3 bleu sp,ra,80002c14 + +0000000080002c1c : + 80002c1c: 00b00193 li gp,11 + 80002c20: 800000b7 lui ra,0x80000 + 80002c24: fff0809b addiw ra,ra,-1 + 80002c28: 0010011b addiw sp,zero,1 + 80002c2c: 01f11113 slli sp,sp,0x1f + 80002c30: 0020f463 bleu sp,ra,80002c38 + 80002c34: 00301463 bne zero,gp,80002c3c + 80002c38: 28301463 bne zero,gp,80002ec0 + 80002c3c: fe20fee3 bleu sp,ra,80002c38 + +0000000080002c40 : + 80002c40: 00c00193 li gp,12 + 80002c44: 00000213 li tp,0 + 80002c48: 00f0009b addiw ra,zero,15 + 80002c4c: 01c09093 slli ra,ra,0x1c + 80002c50: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> + 80002c54: 00f0011b addiw sp,zero,15 + 80002c58: 01c11113 slli sp,sp,0x1c + 80002c5c: 2620f263 bleu sp,ra,80002ec0 + 80002c60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c64: 00200293 li t0,2 + 80002c68: fe5210e3 bne tp,t0,80002c48 + +0000000080002c6c : + 80002c6c: 00d00193 li gp,13 + 80002c70: 00000213 li tp,0 + 80002c74: 00f0009b addiw ra,zero,15 + 80002c78: 01c09093 slli ra,ra,0x1c + 80002c7c: fff08093 addi ra,ra,-1 + 80002c80: 00f0011b addiw sp,zero,15 + 80002c84: 01c11113 slli sp,sp,0x1c + 80002c88: 00000013 nop + 80002c8c: 2220fa63 bleu sp,ra,80002ec0 + 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c94: 00200293 li t0,2 + 80002c98: fc521ee3 bne tp,t0,80002c74 + +0000000080002c9c : + 80002c9c: 00e00193 li gp,14 + 80002ca0: 00000213 li tp,0 + 80002ca4: 00f0009b addiw ra,zero,15 + 80002ca8: 01c09093 slli ra,ra,0x1c + 80002cac: fff08093 addi ra,ra,-1 + 80002cb0: 00f0011b addiw sp,zero,15 + 80002cb4: 01c11113 slli sp,sp,0x1c + 80002cb8: 00000013 nop + 80002cbc: 00000013 nop + 80002cc0: 2020f063 bleu sp,ra,80002ec0 + 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc8: 00200293 li t0,2 + 80002ccc: fc521ce3 bne tp,t0,80002ca4 + +0000000080002cd0 : + 80002cd0: 00f00193 li gp,15 + 80002cd4: 00000213 li tp,0 + 80002cd8: 00f0009b addiw ra,zero,15 + 80002cdc: 01c09093 slli ra,ra,0x1c + 80002ce0: fff08093 addi ra,ra,-1 + 80002ce4: 00000013 nop + 80002ce8: 00f0011b addiw sp,zero,15 + 80002cec: 01c11113 slli sp,sp,0x1c + 80002cf0: 1c20f863 bleu sp,ra,80002ec0 + 80002cf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf8: 00200293 li t0,2 + 80002cfc: fc521ee3 bne tp,t0,80002cd8 + +0000000080002d00 : + 80002d00: 01000193 li gp,16 + 80002d04: 00000213 li tp,0 + 80002d08: 00f0009b addiw ra,zero,15 + 80002d0c: 01c09093 slli ra,ra,0x1c + 80002d10: fff08093 addi ra,ra,-1 + 80002d14: 00000013 nop + 80002d18: 00f0011b addiw sp,zero,15 + 80002d1c: 01c11113 slli sp,sp,0x1c + 80002d20: 00000013 nop + 80002d24: 1820fe63 bleu sp,ra,80002ec0 + 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d2c: 00200293 li t0,2 + 80002d30: fc521ce3 bne tp,t0,80002d08 + +0000000080002d34 : + 80002d34: 01100193 li gp,17 + 80002d38: 00000213 li tp,0 + 80002d3c: 00f0009b addiw ra,zero,15 + 80002d40: 01c09093 slli ra,ra,0x1c + 80002d44: fff08093 addi ra,ra,-1 + 80002d48: 00000013 nop + 80002d4c: 00000013 nop + 80002d50: 00f0011b addiw sp,zero,15 + 80002d54: 01c11113 slli sp,sp,0x1c + 80002d58: 1620f463 bleu sp,ra,80002ec0 + 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d60: 00200293 li t0,2 + 80002d64: fc521ce3 bne tp,t0,80002d3c + +0000000080002d68 : + 80002d68: 01200193 li gp,18 + 80002d6c: 00000213 li tp,0 + 80002d70: 00f0009b addiw ra,zero,15 + 80002d74: 01c09093 slli ra,ra,0x1c + 80002d78: fff08093 addi ra,ra,-1 + 80002d7c: 00f0011b addiw sp,zero,15 + 80002d80: 01c11113 slli sp,sp,0x1c + 80002d84: 1220fe63 bleu sp,ra,80002ec0 + 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d8c: 00200293 li t0,2 + 80002d90: fe5210e3 bne tp,t0,80002d70 + +0000000080002d94 : + 80002d94: 01300193 li gp,19 + 80002d98: 00000213 li tp,0 + 80002d9c: 00f0009b addiw ra,zero,15 + 80002da0: 01c09093 slli ra,ra,0x1c + 80002da4: fff08093 addi ra,ra,-1 + 80002da8: 00f0011b addiw sp,zero,15 + 80002dac: 01c11113 slli sp,sp,0x1c + 80002db0: 00000013 nop + 80002db4: 1020f663 bleu sp,ra,80002ec0 + 80002db8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dbc: 00200293 li t0,2 + 80002dc0: fc521ee3 bne tp,t0,80002d9c + +0000000080002dc4 : + 80002dc4: 01400193 li gp,20 + 80002dc8: 00000213 li tp,0 + 80002dcc: 00f0009b addiw ra,zero,15 + 80002dd0: 01c09093 slli ra,ra,0x1c + 80002dd4: fff08093 addi ra,ra,-1 + 80002dd8: 00f0011b addiw sp,zero,15 + 80002ddc: 01c11113 slli sp,sp,0x1c + 80002de0: 00000013 nop + 80002de4: 00000013 nop + 80002de8: 0c20fc63 bleu sp,ra,80002ec0 + 80002dec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002df0: 00200293 li t0,2 + 80002df4: fc521ce3 bne tp,t0,80002dcc + +0000000080002df8 : + 80002df8: 01500193 li gp,21 + 80002dfc: 00000213 li tp,0 + 80002e00: 00f0009b addiw ra,zero,15 + 80002e04: 01c09093 slli ra,ra,0x1c + 80002e08: fff08093 addi ra,ra,-1 + 80002e0c: 00000013 nop + 80002e10: 00f0011b addiw sp,zero,15 + 80002e14: 01c11113 slli sp,sp,0x1c + 80002e18: 0a20f463 bleu sp,ra,80002ec0 + 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e20: 00200293 li t0,2 + 80002e24: fc521ee3 bne tp,t0,80002e00 + +0000000080002e28 : + 80002e28: 01600193 li gp,22 + 80002e2c: 00000213 li tp,0 + 80002e30: 00f0009b addiw ra,zero,15 + 80002e34: 01c09093 slli ra,ra,0x1c + 80002e38: fff08093 addi ra,ra,-1 + 80002e3c: 00000013 nop + 80002e40: 00f0011b addiw sp,zero,15 + 80002e44: 01c11113 slli sp,sp,0x1c + 80002e48: 00000013 nop + 80002e4c: 0620fa63 bleu sp,ra,80002ec0 + 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e54: 00200293 li t0,2 + 80002e58: fc521ce3 bne tp,t0,80002e30 + +0000000080002e5c : + 80002e5c: 01700193 li gp,23 + 80002e60: 00000213 li tp,0 + 80002e64: 00f0009b addiw ra,zero,15 + 80002e68: 01c09093 slli ra,ra,0x1c + 80002e6c: fff08093 addi ra,ra,-1 + 80002e70: 00000013 nop + 80002e74: 00000013 nop + 80002e78: 00f0011b addiw sp,zero,15 + 80002e7c: 01c11113 slli sp,sp,0x1c + 80002e80: 0420f063 bleu sp,ra,80002ec0 + 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e88: 00200293 li t0,2 + 80002e8c: fc521ce3 bne tp,t0,80002e64 + +0000000080002e90 : + 80002e90: 00100093 li ra,1 + 80002e94: 0000fa63 bleu zero,ra,80002ea8 + 80002e98: 00108093 addi ra,ra,1 + 80002e9c: 00108093 addi ra,ra,1 + 80002ea0: 00108093 addi ra,ra,1 + 80002ea4: 00108093 addi ra,ra,1 + 80002ea8: 00108093 addi ra,ra,1 + 80002eac: 00108093 addi ra,ra,1 + 80002eb0: 00300e93 li t4,3 + 80002eb4: 01800193 li gp,24 + 80002eb8: 01d09463 bne ra,t4,80002ec0 + 80002ebc: 00301a63 bne zero,gp,80002ed0 + +0000000080002ec0 : + 80002ec0: 00119513 slli a0,gp,0x1 + 80002ec4: 00050063 beqz a0,80002ec4 + 80002ec8: 00156513 ori a0,a0,1 + 80002ecc: 00000073 ecall + +0000000080002ed0 : + 80002ed0: 00100513 li a0,1 + 80002ed4: 00000073 ecall + 80002ed8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bgeu.elf b/test/riscv/tests/rv64ui-v-bgeu.elf new file mode 100644 index 00000000..469b8175 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-bgeu.elf differ diff --git a/test/riscv/tests/rv64ui-v-blt.dump b/test/riscv/tests/rv64ui-v-blt.dump new file mode 100644 index 00000000..c0eaae64 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-blt.dump @@ -0,0 +1,1054 @@ + +rv64ui-v-blt: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 61c68693 addi a3,a3,1564 # 80002e90 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01300793 li a5,19 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 01a3a7b7 lui a5,0x1a3a + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b4178793 addi a5,a5,-1215 # 1a39b41 <_start-0x7e5c64bf> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00100113 li sp,1 + 80002ad4: 0020c663 blt ra,sp,80002ae0 + 80002ad8: 2a301863 bne zero,gp,80002d88 + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe20cee3 blt ra,sp,80002adc + 80002ae4: 2a301263 bne zero,gp,80002d88 + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: fff00093 li ra,-1 + 80002af0: 00100113 li sp,1 + 80002af4: 0020c663 blt ra,sp,80002b00 + 80002af8: 28301863 bne zero,gp,80002d88 + 80002afc: 00301663 bne zero,gp,80002b08 + 80002b00: fe20cee3 blt ra,sp,80002afc + 80002b04: 28301263 bne zero,gp,80002d88 + +0000000080002b08 : + 80002b08: 00400193 li gp,4 + 80002b0c: ffe00093 li ra,-2 + 80002b10: fff00113 li sp,-1 + 80002b14: 0020c663 blt ra,sp,80002b20 + 80002b18: 26301863 bne zero,gp,80002d88 + 80002b1c: 00301663 bne zero,gp,80002b28 + 80002b20: fe20cee3 blt ra,sp,80002b1c + 80002b24: 26301263 bne zero,gp,80002d88 + +0000000080002b28 : + 80002b28: 00500193 li gp,5 + 80002b2c: 00100093 li ra,1 + 80002b30: 00000113 li sp,0 + 80002b34: 0020c463 blt ra,sp,80002b3c + 80002b38: 00301463 bne zero,gp,80002b40 + 80002b3c: 24301663 bne zero,gp,80002d88 + 80002b40: fe20cee3 blt ra,sp,80002b3c + +0000000080002b44 : + 80002b44: 00600193 li gp,6 + 80002b48: 00100093 li ra,1 + 80002b4c: fff00113 li sp,-1 + 80002b50: 0020c463 blt ra,sp,80002b58 + 80002b54: 00301463 bne zero,gp,80002b5c + 80002b58: 22301863 bne zero,gp,80002d88 + 80002b5c: fe20cee3 blt ra,sp,80002b58 + +0000000080002b60 : + 80002b60: 00700193 li gp,7 + 80002b64: fff00093 li ra,-1 + 80002b68: ffe00113 li sp,-2 + 80002b6c: 0020c463 blt ra,sp,80002b74 + 80002b70: 00301463 bne zero,gp,80002b78 + 80002b74: 20301a63 bne zero,gp,80002d88 + 80002b78: fe20cee3 blt ra,sp,80002b74 + +0000000080002b7c : + 80002b7c: 00800193 li gp,8 + 80002b80: 00100093 li ra,1 + 80002b84: ffe00113 li sp,-2 + 80002b88: 0020c463 blt ra,sp,80002b90 + 80002b8c: 00301463 bne zero,gp,80002b94 + 80002b90: 1e301c63 bne zero,gp,80002d88 + 80002b94: fe20cee3 blt ra,sp,80002b90 + +0000000080002b98 : + 80002b98: 00900193 li gp,9 + 80002b9c: 00000213 li tp,0 + 80002ba0: 00000093 li ra,0 + 80002ba4: fff00113 li sp,-1 + 80002ba8: 1e20c063 blt ra,sp,80002d88 + 80002bac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bb0: 00200293 li t0,2 + 80002bb4: fe5216e3 bne tp,t0,80002ba0 + +0000000080002bb8 : + 80002bb8: 00a00193 li gp,10 + 80002bbc: 00000213 li tp,0 + 80002bc0: 00000093 li ra,0 + 80002bc4: fff00113 li sp,-1 + 80002bc8: 00000013 nop + 80002bcc: 1a20ce63 blt ra,sp,80002d88 + 80002bd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd4: 00200293 li t0,2 + 80002bd8: fe5214e3 bne tp,t0,80002bc0 + +0000000080002bdc : + 80002bdc: 00b00193 li gp,11 + 80002be0: 00000213 li tp,0 + 80002be4: 00000093 li ra,0 + 80002be8: fff00113 li sp,-1 + 80002bec: 00000013 nop + 80002bf0: 00000013 nop + 80002bf4: 1820ca63 blt ra,sp,80002d88 + 80002bf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bfc: 00200293 li t0,2 + 80002c00: fe5212e3 bne tp,t0,80002be4 + +0000000080002c04 : + 80002c04: 00c00193 li gp,12 + 80002c08: 00000213 li tp,0 + 80002c0c: 00000093 li ra,0 + 80002c10: 00000013 nop + 80002c14: fff00113 li sp,-1 + 80002c18: 1620c863 blt ra,sp,80002d88 + 80002c1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c20: 00200293 li t0,2 + 80002c24: fe5214e3 bne tp,t0,80002c0c + +0000000080002c28 : + 80002c28: 00d00193 li gp,13 + 80002c2c: 00000213 li tp,0 + 80002c30: 00000093 li ra,0 + 80002c34: 00000013 nop + 80002c38: fff00113 li sp,-1 + 80002c3c: 00000013 nop + 80002c40: 1420c463 blt ra,sp,80002d88 + 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c48: 00200293 li t0,2 + 80002c4c: fe5212e3 bne tp,t0,80002c30 + +0000000080002c50 : + 80002c50: 00e00193 li gp,14 + 80002c54: 00000213 li tp,0 + 80002c58: 00000093 li ra,0 + 80002c5c: 00000013 nop + 80002c60: 00000013 nop + 80002c64: fff00113 li sp,-1 + 80002c68: 1220c063 blt ra,sp,80002d88 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5212e3 bne tp,t0,80002c58 + +0000000080002c78 : + 80002c78: 00f00193 li gp,15 + 80002c7c: 00000213 li tp,0 + 80002c80: 00000093 li ra,0 + 80002c84: fff00113 li sp,-1 + 80002c88: 1020c063 blt ra,sp,80002d88 + 80002c8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c90: 00200293 li t0,2 + 80002c94: fe5216e3 bne tp,t0,80002c80 + +0000000080002c98 : + 80002c98: 01000193 li gp,16 + 80002c9c: 00000213 li tp,0 + 80002ca0: 00000093 li ra,0 + 80002ca4: fff00113 li sp,-1 + 80002ca8: 00000013 nop + 80002cac: 0c20ce63 blt ra,sp,80002d88 + 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cb4: 00200293 li t0,2 + 80002cb8: fe5214e3 bne tp,t0,80002ca0 + +0000000080002cbc : + 80002cbc: 01100193 li gp,17 + 80002cc0: 00000213 li tp,0 + 80002cc4: 00000093 li ra,0 + 80002cc8: fff00113 li sp,-1 + 80002ccc: 00000013 nop + 80002cd0: 00000013 nop + 80002cd4: 0a20ca63 blt ra,sp,80002d88 + 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cdc: 00200293 li t0,2 + 80002ce0: fe5212e3 bne tp,t0,80002cc4 + +0000000080002ce4 : + 80002ce4: 01200193 li gp,18 + 80002ce8: 00000213 li tp,0 + 80002cec: 00000093 li ra,0 + 80002cf0: 00000013 nop + 80002cf4: fff00113 li sp,-1 + 80002cf8: 0820c863 blt ra,sp,80002d88 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fe5214e3 bne tp,t0,80002cec + +0000000080002d08 : + 80002d08: 01300193 li gp,19 + 80002d0c: 00000213 li tp,0 + 80002d10: 00000093 li ra,0 + 80002d14: 00000013 nop + 80002d18: fff00113 li sp,-1 + 80002d1c: 00000013 nop + 80002d20: 0620c463 blt ra,sp,80002d88 + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5212e3 bne tp,t0,80002d10 + +0000000080002d30 : + 80002d30: 01400193 li gp,20 + 80002d34: 00000213 li tp,0 + 80002d38: 00000093 li ra,0 + 80002d3c: 00000013 nop + 80002d40: 00000013 nop + 80002d44: fff00113 li sp,-1 + 80002d48: 0420c063 blt ra,sp,80002d88 + 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d50: 00200293 li t0,2 + 80002d54: fe5212e3 bne tp,t0,80002d38 + +0000000080002d58 : + 80002d58: 00100093 li ra,1 + 80002d5c: 00104a63 bgtz ra,80002d70 + 80002d60: 00108093 addi ra,ra,1 + 80002d64: 00108093 addi ra,ra,1 + 80002d68: 00108093 addi ra,ra,1 + 80002d6c: 00108093 addi ra,ra,1 + 80002d70: 00108093 addi ra,ra,1 + 80002d74: 00108093 addi ra,ra,1 + 80002d78: 00300e93 li t4,3 + 80002d7c: 01500193 li gp,21 + 80002d80: 01d09463 bne ra,t4,80002d88 + 80002d84: 00301a63 bne zero,gp,80002d98 + +0000000080002d88 : + 80002d88: 00119513 slli a0,gp,0x1 + 80002d8c: 00050063 beqz a0,80002d8c + 80002d90: 00156513 ori a0,a0,1 + 80002d94: 00000073 ecall + +0000000080002d98 : + 80002d98: 00100513 li a0,1 + 80002d9c: 00000073 ecall + 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-blt.elf b/test/riscv/tests/rv64ui-v-blt.elf new file mode 100644 index 00000000..1232ebb1 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-blt.elf differ diff --git a/test/riscv/tests/rv64ui-v-bltu.dump b/test/riscv/tests/rv64ui-v-bltu.dump new file mode 100644 index 00000000..bf46506a --- /dev/null +++ b/test/riscv/tests/rv64ui-v-bltu.dump @@ -0,0 +1,1104 @@ + +rv64ui-v-bltu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: a1868693 addi a3,a3,-1512 # 80002e70 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: a4c60613 addi a2,a2,-1460 # 80002f00 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: a1460613 addi a2,a2,-1516 # 80002f18 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 96468693 addi a3,a3,-1692 # 80002eb8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 98068693 addi a3,a3,-1664 # 80002ff0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 90060613 addi a2,a2,-1792 # 80002fc8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 83468693 addi a3,a3,-1996 # 80003020 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 75468693 addi a3,a3,1876 # 80002f90 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 6e468693 addi a3,a3,1764 # 80002f58 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03800793 li a5,56 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 09c3b7b7 lui a5,0x9c3b + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 9db78793 addi a5,a5,-1573 # 9c3a9db <_start-0x763c5625> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00100113 li sp,1 + 80002ad4: 0020e663 bltu ra,sp,80002ae0 + 80002ad8: 36301c63 bne zero,gp,80002e50 + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe20eee3 bltu ra,sp,80002adc + 80002ae4: 36301663 bne zero,gp,80002e50 + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: 0010009b addiw ra,zero,1 + 80002af0: 02009093 slli ra,ra,0x20 + 80002af4: ffe08093 addi ra,ra,-2 + 80002af8: 0010011b addiw sp,zero,1 + 80002afc: 02011113 slli sp,sp,0x20 + 80002b00: fff10113 addi sp,sp,-1 + 80002b04: 0020e663 bltu ra,sp,80002b10 + 80002b08: 34301463 bne zero,gp,80002e50 + 80002b0c: 00301663 bne zero,gp,80002b18 + 80002b10: fe20eee3 bltu ra,sp,80002b0c + 80002b14: 32301e63 bne zero,gp,80002e50 + +0000000080002b18 : + 80002b18: 00400193 li gp,4 + 80002b1c: 00000093 li ra,0 + 80002b20: 0010011b addiw sp,zero,1 + 80002b24: 02011113 slli sp,sp,0x20 + 80002b28: fff10113 addi sp,sp,-1 + 80002b2c: 0020e663 bltu ra,sp,80002b38 + 80002b30: 32301063 bne zero,gp,80002e50 + 80002b34: 00301663 bne zero,gp,80002b40 + 80002b38: fe20eee3 bltu ra,sp,80002b34 + 80002b3c: 30301a63 bne zero,gp,80002e50 + +0000000080002b40 : + 80002b40: 00500193 li gp,5 + 80002b44: 00100093 li ra,1 + 80002b48: 00000113 li sp,0 + 80002b4c: 0020e463 bltu ra,sp,80002b54 + 80002b50: 00301463 bne zero,gp,80002b58 + 80002b54: 2e301e63 bne zero,gp,80002e50 + 80002b58: fe20eee3 bltu ra,sp,80002b54 + +0000000080002b5c : + 80002b5c: 00600193 li gp,6 + 80002b60: 0010009b addiw ra,zero,1 + 80002b64: 02009093 slli ra,ra,0x20 + 80002b68: fff08093 addi ra,ra,-1 + 80002b6c: 0010011b addiw sp,zero,1 + 80002b70: 02011113 slli sp,sp,0x20 + 80002b74: ffe10113 addi sp,sp,-2 + 80002b78: 0020e463 bltu ra,sp,80002b80 + 80002b7c: 00301463 bne zero,gp,80002b84 + 80002b80: 2c301863 bne zero,gp,80002e50 + 80002b84: fe20eee3 bltu ra,sp,80002b80 + +0000000080002b88 : + 80002b88: 00700193 li gp,7 + 80002b8c: 0010009b addiw ra,zero,1 + 80002b90: 02009093 slli ra,ra,0x20 + 80002b94: fff08093 addi ra,ra,-1 + 80002b98: 00000113 li sp,0 + 80002b9c: 0020e463 bltu ra,sp,80002ba4 + 80002ba0: 00301463 bne zero,gp,80002ba8 + 80002ba4: 2a301663 bne zero,gp,80002e50 + 80002ba8: fe20eee3 bltu ra,sp,80002ba4 + +0000000080002bac : + 80002bac: 00800193 li gp,8 + 80002bb0: 0010009b addiw ra,zero,1 + 80002bb4: 01f09093 slli ra,ra,0x1f + 80002bb8: 80000137 lui sp,0x80000 + 80002bbc: fff1011b addiw sp,sp,-1 + 80002bc0: 0020e463 bltu ra,sp,80002bc8 + 80002bc4: 00301463 bne zero,gp,80002bcc + 80002bc8: 28301463 bne zero,gp,80002e50 + 80002bcc: fe20eee3 bltu ra,sp,80002bc8 + +0000000080002bd0 : + 80002bd0: 00900193 li gp,9 + 80002bd4: 00000213 li tp,0 + 80002bd8: 00f0009b addiw ra,zero,15 + 80002bdc: 01c09093 slli ra,ra,0x1c + 80002be0: 00f0011b addiw sp,zero,15 + 80002be4: 01c11113 slli sp,sp,0x1c + 80002be8: fff10113 addi sp,sp,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> + 80002bec: 2620e263 bltu ra,sp,80002e50 + 80002bf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bf4: 00200293 li t0,2 + 80002bf8: fe5210e3 bne tp,t0,80002bd8 + +0000000080002bfc : + 80002bfc: 00a00193 li gp,10 + 80002c00: 00000213 li tp,0 + 80002c04: 00f0009b addiw ra,zero,15 + 80002c08: 01c09093 slli ra,ra,0x1c + 80002c0c: 00f0011b addiw sp,zero,15 + 80002c10: 01c11113 slli sp,sp,0x1c + 80002c14: fff10113 addi sp,sp,-1 + 80002c18: 00000013 nop + 80002c1c: 2220ea63 bltu ra,sp,80002e50 + 80002c20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c24: 00200293 li t0,2 + 80002c28: fc521ee3 bne tp,t0,80002c04 + +0000000080002c2c : + 80002c2c: 00b00193 li gp,11 + 80002c30: 00000213 li tp,0 + 80002c34: 00f0009b addiw ra,zero,15 + 80002c38: 01c09093 slli ra,ra,0x1c + 80002c3c: 00f0011b addiw sp,zero,15 + 80002c40: 01c11113 slli sp,sp,0x1c + 80002c44: fff10113 addi sp,sp,-1 + 80002c48: 00000013 nop + 80002c4c: 00000013 nop + 80002c50: 2020e063 bltu ra,sp,80002e50 + 80002c54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c58: 00200293 li t0,2 + 80002c5c: fc521ce3 bne tp,t0,80002c34 + +0000000080002c60 : + 80002c60: 00c00193 li gp,12 + 80002c64: 00000213 li tp,0 + 80002c68: 00f0009b addiw ra,zero,15 + 80002c6c: 01c09093 slli ra,ra,0x1c + 80002c70: 00000013 nop + 80002c74: 00f0011b addiw sp,zero,15 + 80002c78: 01c11113 slli sp,sp,0x1c + 80002c7c: fff10113 addi sp,sp,-1 + 80002c80: 1c20e863 bltu ra,sp,80002e50 + 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c88: 00200293 li t0,2 + 80002c8c: fc521ee3 bne tp,t0,80002c68 + +0000000080002c90 : + 80002c90: 00d00193 li gp,13 + 80002c94: 00000213 li tp,0 + 80002c98: 00f0009b addiw ra,zero,15 + 80002c9c: 01c09093 slli ra,ra,0x1c + 80002ca0: 00000013 nop + 80002ca4: 00f0011b addiw sp,zero,15 + 80002ca8: 01c11113 slli sp,sp,0x1c + 80002cac: fff10113 addi sp,sp,-1 + 80002cb0: 00000013 nop + 80002cb4: 1820ee63 bltu ra,sp,80002e50 + 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cbc: 00200293 li t0,2 + 80002cc0: fc521ce3 bne tp,t0,80002c98 + +0000000080002cc4 : + 80002cc4: 00e00193 li gp,14 + 80002cc8: 00000213 li tp,0 + 80002ccc: 00f0009b addiw ra,zero,15 + 80002cd0: 01c09093 slli ra,ra,0x1c + 80002cd4: 00000013 nop + 80002cd8: 00000013 nop + 80002cdc: 00f0011b addiw sp,zero,15 + 80002ce0: 01c11113 slli sp,sp,0x1c + 80002ce4: fff10113 addi sp,sp,-1 + 80002ce8: 1620e463 bltu ra,sp,80002e50 + 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf0: 00200293 li t0,2 + 80002cf4: fc521ce3 bne tp,t0,80002ccc + +0000000080002cf8 : + 80002cf8: 00f00193 li gp,15 + 80002cfc: 00000213 li tp,0 + 80002d00: 00f0009b addiw ra,zero,15 + 80002d04: 01c09093 slli ra,ra,0x1c + 80002d08: 00f0011b addiw sp,zero,15 + 80002d0c: 01c11113 slli sp,sp,0x1c + 80002d10: fff10113 addi sp,sp,-1 + 80002d14: 1220ee63 bltu ra,sp,80002e50 + 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d1c: 00200293 li t0,2 + 80002d20: fe5210e3 bne tp,t0,80002d00 + +0000000080002d24 : + 80002d24: 01000193 li gp,16 + 80002d28: 00000213 li tp,0 + 80002d2c: 00f0009b addiw ra,zero,15 + 80002d30: 01c09093 slli ra,ra,0x1c + 80002d34: 00f0011b addiw sp,zero,15 + 80002d38: 01c11113 slli sp,sp,0x1c + 80002d3c: fff10113 addi sp,sp,-1 + 80002d40: 00000013 nop + 80002d44: 1020e663 bltu ra,sp,80002e50 + 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d4c: 00200293 li t0,2 + 80002d50: fc521ee3 bne tp,t0,80002d2c + +0000000080002d54 : + 80002d54: 01100193 li gp,17 + 80002d58: 00000213 li tp,0 + 80002d5c: 00f0009b addiw ra,zero,15 + 80002d60: 01c09093 slli ra,ra,0x1c + 80002d64: 00f0011b addiw sp,zero,15 + 80002d68: 01c11113 slli sp,sp,0x1c + 80002d6c: fff10113 addi sp,sp,-1 + 80002d70: 00000013 nop + 80002d74: 00000013 nop + 80002d78: 0c20ec63 bltu ra,sp,80002e50 + 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d80: 00200293 li t0,2 + 80002d84: fc521ce3 bne tp,t0,80002d5c + +0000000080002d88 : + 80002d88: 01200193 li gp,18 + 80002d8c: 00000213 li tp,0 + 80002d90: 00f0009b addiw ra,zero,15 + 80002d94: 01c09093 slli ra,ra,0x1c + 80002d98: 00000013 nop + 80002d9c: 00f0011b addiw sp,zero,15 + 80002da0: 01c11113 slli sp,sp,0x1c + 80002da4: fff10113 addi sp,sp,-1 + 80002da8: 0a20e463 bltu ra,sp,80002e50 + 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db0: 00200293 li t0,2 + 80002db4: fc521ee3 bne tp,t0,80002d90 + +0000000080002db8 : + 80002db8: 01300193 li gp,19 + 80002dbc: 00000213 li tp,0 + 80002dc0: 00f0009b addiw ra,zero,15 + 80002dc4: 01c09093 slli ra,ra,0x1c + 80002dc8: 00000013 nop + 80002dcc: 00f0011b addiw sp,zero,15 + 80002dd0: 01c11113 slli sp,sp,0x1c + 80002dd4: fff10113 addi sp,sp,-1 + 80002dd8: 00000013 nop + 80002ddc: 0620ea63 bltu ra,sp,80002e50 + 80002de0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de4: 00200293 li t0,2 + 80002de8: fc521ce3 bne tp,t0,80002dc0 + +0000000080002dec : + 80002dec: 01400193 li gp,20 + 80002df0: 00000213 li tp,0 + 80002df4: 00f0009b addiw ra,zero,15 + 80002df8: 01c09093 slli ra,ra,0x1c + 80002dfc: 00000013 nop + 80002e00: 00000013 nop + 80002e04: 00f0011b addiw sp,zero,15 + 80002e08: 01c11113 slli sp,sp,0x1c + 80002e0c: fff10113 addi sp,sp,-1 + 80002e10: 0420e063 bltu ra,sp,80002e50 + 80002e14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e18: 00200293 li t0,2 + 80002e1c: fc521ce3 bne tp,t0,80002df4 + +0000000080002e20 : + 80002e20: 00100093 li ra,1 + 80002e24: 00106a63 bltu zero,ra,80002e38 + 80002e28: 00108093 addi ra,ra,1 + 80002e2c: 00108093 addi ra,ra,1 + 80002e30: 00108093 addi ra,ra,1 + 80002e34: 00108093 addi ra,ra,1 + 80002e38: 00108093 addi ra,ra,1 + 80002e3c: 00108093 addi ra,ra,1 + 80002e40: 00300e93 li t4,3 + 80002e44: 01500193 li gp,21 + 80002e48: 01d09463 bne ra,t4,80002e50 + 80002e4c: 00301a63 bne zero,gp,80002e60 + +0000000080002e50 : + 80002e50: 00119513 slli a0,gp,0x1 + 80002e54: 00050063 beqz a0,80002e54 + 80002e58: 00156513 ori a0,a0,1 + 80002e5c: 00000073 ecall + +0000000080002e60 : + 80002e60: 00100513 li a0,1 + 80002e64: 00000073 ecall + 80002e68: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bltu.elf b/test/riscv/tests/rv64ui-v-bltu.elf new file mode 100644 index 00000000..4109accb Binary files /dev/null and b/test/riscv/tests/rv64ui-v-bltu.elf differ diff --git a/test/riscv/tests/rv64ui-v-bne.dump b/test/riscv/tests/rv64ui-v-bne.dump new file mode 100644 index 00000000..63ec2886 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-bne.dump @@ -0,0 +1,1055 @@ + +rv64ui-v-bne: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 61c68693 addi a3,a3,1564 # 80002e90 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02600793 li a5,38 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0802e7b7 lui a5,0x802e + 80002a70: 000805b7 lui a1,0x80 + 80002a74: d7978793 addi a5,a5,-647 # 802dd79 <_start-0x77fd2287> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 00100113 li sp,1 + 80002ad4: 00209663 bne ra,sp,80002ae0 + 80002ad8: 2a301a63 bne zero,gp,80002d8c + 80002adc: 00301663 bne zero,gp,80002ae8 + 80002ae0: fe209ee3 bne ra,sp,80002adc + 80002ae4: 2a301463 bne zero,gp,80002d8c + +0000000080002ae8 : + 80002ae8: 00300193 li gp,3 + 80002aec: 00100093 li ra,1 + 80002af0: 00000113 li sp,0 + 80002af4: 00209663 bne ra,sp,80002b00 + 80002af8: 28301a63 bne zero,gp,80002d8c + 80002afc: 00301663 bne zero,gp,80002b08 + 80002b00: fe209ee3 bne ra,sp,80002afc + 80002b04: 28301463 bne zero,gp,80002d8c + +0000000080002b08 : + 80002b08: 00400193 li gp,4 + 80002b0c: fff00093 li ra,-1 + 80002b10: 00100113 li sp,1 + 80002b14: 00209663 bne ra,sp,80002b20 + 80002b18: 26301a63 bne zero,gp,80002d8c + 80002b1c: 00301663 bne zero,gp,80002b28 + 80002b20: fe209ee3 bne ra,sp,80002b1c + 80002b24: 26301463 bne zero,gp,80002d8c + +0000000080002b28 : + 80002b28: 00500193 li gp,5 + 80002b2c: 00100093 li ra,1 + 80002b30: fff00113 li sp,-1 + 80002b34: 00209663 bne ra,sp,80002b40 + 80002b38: 24301a63 bne zero,gp,80002d8c + 80002b3c: 00301663 bne zero,gp,80002b48 + 80002b40: fe209ee3 bne ra,sp,80002b3c + 80002b44: 24301463 bne zero,gp,80002d8c + +0000000080002b48 : + 80002b48: 00600193 li gp,6 + 80002b4c: 00000093 li ra,0 + 80002b50: 00000113 li sp,0 + 80002b54: 00209463 bne ra,sp,80002b5c + 80002b58: 00301463 bne zero,gp,80002b60 + 80002b5c: 22301863 bne zero,gp,80002d8c + 80002b60: fe209ee3 bne ra,sp,80002b5c + +0000000080002b64 : + 80002b64: 00700193 li gp,7 + 80002b68: 00100093 li ra,1 + 80002b6c: 00100113 li sp,1 + 80002b70: 00209463 bne ra,sp,80002b78 + 80002b74: 00301463 bne zero,gp,80002b7c + 80002b78: 20301a63 bne zero,gp,80002d8c + 80002b7c: fe209ee3 bne ra,sp,80002b78 + +0000000080002b80 : + 80002b80: 00800193 li gp,8 + 80002b84: fff00093 li ra,-1 + 80002b88: fff00113 li sp,-1 + 80002b8c: 00209463 bne ra,sp,80002b94 + 80002b90: 00301463 bne zero,gp,80002b98 + 80002b94: 1e301c63 bne zero,gp,80002d8c + 80002b98: fe209ee3 bne ra,sp,80002b94 + +0000000080002b9c : + 80002b9c: 00900193 li gp,9 + 80002ba0: 00000213 li tp,0 + 80002ba4: 00000093 li ra,0 + 80002ba8: 00000113 li sp,0 + 80002bac: 1e209063 bne ra,sp,80002d8c + 80002bb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bb4: 00200293 li t0,2 + 80002bb8: fe5216e3 bne tp,t0,80002ba4 + +0000000080002bbc : + 80002bbc: 00a00193 li gp,10 + 80002bc0: 00000213 li tp,0 + 80002bc4: 00000093 li ra,0 + 80002bc8: 00000113 li sp,0 + 80002bcc: 00000013 nop + 80002bd0: 1a209e63 bne ra,sp,80002d8c + 80002bd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd8: 00200293 li t0,2 + 80002bdc: fe5214e3 bne tp,t0,80002bc4 + +0000000080002be0 : + 80002be0: 00b00193 li gp,11 + 80002be4: 00000213 li tp,0 + 80002be8: 00000093 li ra,0 + 80002bec: 00000113 li sp,0 + 80002bf0: 00000013 nop + 80002bf4: 00000013 nop + 80002bf8: 18209a63 bne ra,sp,80002d8c + 80002bfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c00: 00200293 li t0,2 + 80002c04: fe5212e3 bne tp,t0,80002be8 + +0000000080002c08 : + 80002c08: 00c00193 li gp,12 + 80002c0c: 00000213 li tp,0 + 80002c10: 00000093 li ra,0 + 80002c14: 00000013 nop + 80002c18: 00000113 li sp,0 + 80002c1c: 16209863 bne ra,sp,80002d8c + 80002c20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c24: 00200293 li t0,2 + 80002c28: fe5214e3 bne tp,t0,80002c10 + +0000000080002c2c : + 80002c2c: 00d00193 li gp,13 + 80002c30: 00000213 li tp,0 + 80002c34: 00000093 li ra,0 + 80002c38: 00000013 nop + 80002c3c: 00000113 li sp,0 + 80002c40: 00000013 nop + 80002c44: 14209463 bne ra,sp,80002d8c + 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c4c: 00200293 li t0,2 + 80002c50: fe5212e3 bne tp,t0,80002c34 + +0000000080002c54 : + 80002c54: 00e00193 li gp,14 + 80002c58: 00000213 li tp,0 + 80002c5c: 00000093 li ra,0 + 80002c60: 00000013 nop + 80002c64: 00000013 nop + 80002c68: 00000113 li sp,0 + 80002c6c: 12209063 bne ra,sp,80002d8c + 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c74: 00200293 li t0,2 + 80002c78: fe5212e3 bne tp,t0,80002c5c + +0000000080002c7c : + 80002c7c: 00f00193 li gp,15 + 80002c80: 00000213 li tp,0 + 80002c84: 00000093 li ra,0 + 80002c88: 00000113 li sp,0 + 80002c8c: 10209063 bne ra,sp,80002d8c + 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c94: 00200293 li t0,2 + 80002c98: fe5216e3 bne tp,t0,80002c84 + +0000000080002c9c : + 80002c9c: 01000193 li gp,16 + 80002ca0: 00000213 li tp,0 + 80002ca4: 00000093 li ra,0 + 80002ca8: 00000113 li sp,0 + 80002cac: 00000013 nop + 80002cb0: 0c209e63 bne ra,sp,80002d8c + 80002cb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cb8: 00200293 li t0,2 + 80002cbc: fe5214e3 bne tp,t0,80002ca4 + +0000000080002cc0 : + 80002cc0: 01100193 li gp,17 + 80002cc4: 00000213 li tp,0 + 80002cc8: 00000093 li ra,0 + 80002ccc: 00000113 li sp,0 + 80002cd0: 00000013 nop + 80002cd4: 00000013 nop + 80002cd8: 0a209a63 bne ra,sp,80002d8c + 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce0: 00200293 li t0,2 + 80002ce4: fe5212e3 bne tp,t0,80002cc8 + +0000000080002ce8 : + 80002ce8: 01200193 li gp,18 + 80002cec: 00000213 li tp,0 + 80002cf0: 00000093 li ra,0 + 80002cf4: 00000013 nop + 80002cf8: 00000113 li sp,0 + 80002cfc: 08209863 bne ra,sp,80002d8c + 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d04: 00200293 li t0,2 + 80002d08: fe5214e3 bne tp,t0,80002cf0 + +0000000080002d0c : + 80002d0c: 01300193 li gp,19 + 80002d10: 00000213 li tp,0 + 80002d14: 00000093 li ra,0 + 80002d18: 00000013 nop + 80002d1c: 00000113 li sp,0 + 80002d20: 00000013 nop + 80002d24: 06209463 bne ra,sp,80002d8c + 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d2c: 00200293 li t0,2 + 80002d30: fe5212e3 bne tp,t0,80002d14 + +0000000080002d34 : + 80002d34: 01400193 li gp,20 + 80002d38: 00000213 li tp,0 + 80002d3c: 00000093 li ra,0 + 80002d40: 00000013 nop + 80002d44: 00000013 nop + 80002d48: 00000113 li sp,0 + 80002d4c: 04209063 bne ra,sp,80002d8c + 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d54: 00200293 li t0,2 + 80002d58: fe5212e3 bne tp,t0,80002d3c + +0000000080002d5c : + 80002d5c: 00100093 li ra,1 + 80002d60: 00009a63 bnez ra,80002d74 + 80002d64: 00108093 addi ra,ra,1 + 80002d68: 00108093 addi ra,ra,1 + 80002d6c: 00108093 addi ra,ra,1 + 80002d70: 00108093 addi ra,ra,1 + 80002d74: 00108093 addi ra,ra,1 + 80002d78: 00108093 addi ra,ra,1 + 80002d7c: 00300e93 li t4,3 + 80002d80: 01500193 li gp,21 + 80002d84: 01d09463 bne ra,t4,80002d8c + 80002d88: 00301a63 bne zero,gp,80002d9c + +0000000080002d8c : + 80002d8c: 00119513 slli a0,gp,0x1 + 80002d90: 00050063 beqz a0,80002d90 + 80002d94: 00156513 ori a0,a0,1 + 80002d98: 00000073 ecall + +0000000080002d9c : + 80002d9c: 00100513 li a0,1 + 80002da0: 00000073 ecall + 80002da4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bne.elf b/test/riscv/tests/rv64ui-v-bne.elf new file mode 100644 index 00000000..fa480bf2 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-bne.elf differ diff --git a/test/riscv/tests/rv64ui-v-fence_i.dump b/test/riscv/tests/rv64ui-v-fence_i.dump new file mode 100644 index 00000000..b559930c --- /dev/null +++ b/test/riscv/tests/rv64ui-v-fence_i.dump @@ -0,0 +1,959 @@ + +rv64ui-v-fence_i: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: ad050513 addi a0,a0,-1328 # 80002b00 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 7d868693 addi a3,a3,2008 # 80002c30 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 80c60613 addi a2,a2,-2036 # 80002cc0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 7d460613 addi a2,a2,2004 # 80002cd8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 72468693 addi a3,a3,1828 # 80002c78 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 74068693 addi a3,a3,1856 # 80002db0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 6c060613 addi a2,a2,1728 # 80002d88 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 5f468693 addi a3,a3,1524 # 80002de0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 51468693 addi a3,a3,1300 # 80002d50 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 4a468693 addi a3,a3,1188 # 80002d18 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03300793 li a5,51 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 032fe7b7 lui a5,0x32fe + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 19f78793 addi a5,a5,415 # 32fe19f <_start-0x7cd01e61> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + 80002ac8: 0000 unimp + 80002aca: 0000 unimp + 80002acc: 0000 unimp + 80002ace: 0000 unimp + 80002ad0: 0000 unimp + 80002ad2: 0000 unimp + 80002ad4: 0000 unimp + 80002ad6: 0000 unimp + 80002ad8: 0000 unimp + 80002ada: 0000 unimp + 80002adc: 0000 unimp + 80002ade: 0000 unimp + 80002ae0: 0000 unimp + 80002ae2: 0000 unimp + 80002ae4: 0000 unimp + 80002ae6: 0000 unimp + 80002ae8: 0000 unimp + 80002aea: 0000 unimp + 80002aec: 0000 unimp + 80002aee: 0000 unimp + 80002af0: 0000 unimp + 80002af2: 0000 unimp + 80002af4: 0000 unimp + 80002af6: 0000 unimp + 80002af8: 0000 unimp + 80002afa: 0000 unimp + 80002afc: 0000 unimp + 80002afe: 0000 unimp + +0000000080002b00 : + 80002b00: 06f00693 li a3,111 + 80002b04: 00000517 auipc a0,0x0 + 80002b08: 4fc51503 lh a0,1276(a0) # 80003000 + 80002b0c: 00000597 auipc a1,0x0 + 80002b10: 4f659583 lh a1,1270(a1) # 80003002 + 80002b14: 00000013 nop + 80002b18: 00000013 nop + 80002b1c: 00000013 nop + 80002b20: 00000013 nop + 80002b24: 00000013 nop + 80002b28: 00000013 nop + 80002b2c: 00000013 nop + 80002b30: 00000013 nop + 80002b34: 00000013 nop + 80002b38: 00000013 nop + 80002b3c: 00000013 nop + 80002b40: 00000297 auipc t0,0x0 + 80002b44: 00a29a23 sh a0,20(t0) # 80002b54 + 80002b48: 00000297 auipc t0,0x0 + 80002b4c: 00b29723 sh a1,14(t0) # 80002b56 + 80002b50: 0000100f fence.i + 80002b54: 0de68693 addi a3,a3,222 + +0000000080002b58 : + 80002b58: 00000013 nop + 80002b5c: 1bc00e93 li t4,444 + 80002b60: 00200193 li gp,2 + 80002b64: 07d69a63 bne a3,t4,80002bd8 + 80002b68: 06400713 li a4,100 + 80002b6c: fff70713 addi a4,a4,-1 + 80002b70: fe071ee3 bnez a4,80002b6c + 80002b74: 00000297 auipc t0,0x0 + 80002b78: 04a29623 sh a0,76(t0) # 80002bc0 + 80002b7c: 00000297 auipc t0,0x0 + 80002b80: 04b29323 sh a1,70(t0) # 80002bc2 + 80002b84: 0000100f fence.i + 80002b88: 00000013 nop + 80002b8c: 00000013 nop + 80002b90: 00000013 nop + 80002b94: 00000013 nop + 80002b98: 00000013 nop + 80002b9c: 00000013 nop + 80002ba0: 00000013 nop + 80002ba4: 00000013 nop + 80002ba8: 00000013 nop + 80002bac: 00000013 nop + 80002bb0: 00000013 nop + 80002bb4: 00000013 nop + 80002bb8: 00000013 nop + 80002bbc: 00000013 nop + 80002bc0: 22b68693 addi a3,a3,555 + +0000000080002bc4 : + 80002bc4: 00000013 nop + 80002bc8: 30900e93 li t4,777 + 80002bcc: 00300193 li gp,3 + 80002bd0: 01d69463 bne a3,t4,80002bd8 + 80002bd4: 00301a63 bne zero,gp,80002be8 + +0000000080002bd8 : + 80002bd8: 00119513 slli a0,gp,0x1 + 80002bdc: 00050063 beqz a0,80002bdc + 80002be0: 00156513 ori a0,a0,1 + 80002be4: 00000073 ecall + +0000000080002be8 : + 80002be8: 00100513 li a0,1 + 80002bec: 00000073 ecall + 80002bf0: c0001073 unimp + 80002bf4: 0000 unimp + 80002bf6: 0000 unimp + 80002bf8: 0000 unimp + 80002bfa: 0000 unimp + 80002bfc: 0000 unimp + 80002bfe: 0000 unimp + 80002c00: 0000 unimp + 80002c02: 0000 unimp + 80002c04: 0000 unimp + 80002c06: 0000 unimp + 80002c08: 0000 unimp + 80002c0a: 0000 unimp + 80002c0c: 0000 unimp + 80002c0e: 0000 unimp + 80002c10: 0000 unimp + 80002c12: 0000 unimp + 80002c14: 0000 unimp + 80002c16: 0000 unimp + 80002c18: 0000 unimp + 80002c1a: 0000 unimp + 80002c1c: 0000 unimp + 80002c1e: 0000 unimp + 80002c20: 0000 unimp + 80002c22: 0000 unimp + 80002c24: 0000 unimp + 80002c26: 0000 unimp + 80002c28: 0000 unimp + 80002c2a: 0000 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 14d68693 addi a3,a3,333 diff --git a/test/riscv/tests/rv64ui-v-fence_i.elf b/test/riscv/tests/rv64ui-v-fence_i.elf new file mode 100644 index 00000000..5ab09908 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-fence_i.elf differ diff --git a/test/riscv/tests/rv64ui-v-jal.dump b/test/riscv/tests/rv64ui-v-jal.dump new file mode 100644 index 00000000..a22031d1 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-jal.dump @@ -0,0 +1,867 @@ + +rv64ui-v-jal: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6e068693 addi a3,a3,1760 # 80002b38 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 71460613 addi a2,a2,1812 # 80002bc8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6dc60613 addi a2,a2,1756 # 80002be0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 62c68693 addi a3,a3,1580 # 80002b80 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 64868693 addi a3,a3,1608 # 80002cb8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5c860613 addi a2,a2,1480 # 80002c90 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 4fc68693 addi a3,a3,1276 # 80002ce8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 41c68693 addi a3,a3,1052 # 80002c58 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3ac68693 addi a3,a3,940 # 80002c20 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02d00793 li a5,45 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0e1d97b7 lui a5,0xe1d9 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: ad378793 addi a5,a5,-1325 # e1d8ad3 <_start-0x71e2752d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000093 li ra,0 + 80002ad0: 0100026f jal tp,80002ae0 + +0000000080002ad4 : + 80002ad4: 00000013 nop + 80002ad8: 00000013 nop + 80002adc: 0400006f j 80002b1c + +0000000080002ae0 : + 80002ae0: 00000117 auipc sp,0x0 + 80002ae4: ff410113 addi sp,sp,-12 # 80002ad4 + 80002ae8: 02411a63 bne sp,tp,80002b1c + +0000000080002aec : + 80002aec: 00100093 li ra,1 + 80002af0: 0140006f j 80002b04 + 80002af4: 00108093 addi ra,ra,1 + 80002af8: 00108093 addi ra,ra,1 + 80002afc: 00108093 addi ra,ra,1 + 80002b00: 00108093 addi ra,ra,1 + 80002b04: 00108093 addi ra,ra,1 + 80002b08: 00108093 addi ra,ra,1 + 80002b0c: 00300e93 li t4,3 + 80002b10: 00300193 li gp,3 + 80002b14: 01d09463 bne ra,t4,80002b1c + 80002b18: 00301a63 bne zero,gp,80002b2c + +0000000080002b1c : + 80002b1c: 00119513 slli a0,gp,0x1 + 80002b20: 00050063 beqz a0,80002b20 + 80002b24: 00156513 ori a0,a0,1 + 80002b28: 00000073 ecall + +0000000080002b2c : + 80002b2c: 00100513 li a0,1 + 80002b30: 00000073 ecall + 80002b34: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-jal.elf b/test/riscv/tests/rv64ui-v-jal.elf new file mode 100644 index 00000000..82efaa89 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-jal.elf differ diff --git a/test/riscv/tests/rv64ui-v-jalr.dump b/test/riscv/tests/rv64ui-v-jalr.dump new file mode 100644 index 00000000..4b43b163 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-jalr.dump @@ -0,0 +1,905 @@ + +rv64ui-v-jalr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 76068693 addi a3,a3,1888 # 80002bb8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 79460613 addi a2,a2,1940 # 80002c48 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 75c60613 addi a2,a2,1884 # 80002c60 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6ac68693 addi a3,a3,1708 # 80002c00 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6c868693 addi a3,a3,1736 # 80002d38 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 64860613 addi a2,a2,1608 # 80002d10 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 57c68693 addi a3,a3,1404 # 80002d68 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 49c68693 addi a3,a3,1180 # 80002cd8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 42c68693 addi a3,a3,1068 # 80002ca0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01600793 li a5,22 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 044267b7 lui a5,0x4426 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 9b478793 addi a5,a5,-1612 # 44259b4 <_start-0x7bbda64c> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00200193 li gp,2 + 80002acc: 00000293 li t0,0 + 80002ad0: 00000317 auipc t1,0x0 + 80002ad4: 01030313 addi t1,t1,16 # 80002ae0 + 80002ad8: 000302e7 jalr t0,t1 + +0000000080002adc : + 80002adc: 0c00006f j 80002b9c + +0000000080002ae0 : + 80002ae0: 00000317 auipc t1,0x0 + 80002ae4: ffc30313 addi t1,t1,-4 # 80002adc + 80002ae8: 0a629a63 bne t0,t1,80002b9c + +0000000080002aec : + 80002aec: 00400193 li gp,4 + 80002af0: 00000213 li tp,0 + 80002af4: 00000317 auipc t1,0x0 + 80002af8: 01030313 addi t1,t1,16 # 80002b04 + 80002afc: 000309e7 jalr s3,t1 + 80002b00: 08301e63 bne zero,gp,80002b9c + 80002b04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b08: 00200293 li t0,2 + 80002b0c: fe5214e3 bne tp,t0,80002af4 + +0000000080002b10 : + 80002b10: 00500193 li gp,5 + 80002b14: 00000213 li tp,0 + 80002b18: 00000317 auipc t1,0x0 + 80002b1c: 01430313 addi t1,t1,20 # 80002b2c + 80002b20: 00000013 nop + 80002b24: 000309e7 jalr s3,t1 + 80002b28: 06301a63 bne zero,gp,80002b9c + 80002b2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b30: 00200293 li t0,2 + 80002b34: fe5212e3 bne tp,t0,80002b18 + +0000000080002b38 : + 80002b38: 00600193 li gp,6 + 80002b3c: 00000213 li tp,0 + 80002b40: 00000317 auipc t1,0x0 + 80002b44: 01830313 addi t1,t1,24 # 80002b58 + 80002b48: 00000013 nop + 80002b4c: 00000013 nop + 80002b50: 000309e7 jalr s3,t1 + 80002b54: 04301463 bne zero,gp,80002b9c + 80002b58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b5c: 00200293 li t0,2 + 80002b60: fe5210e3 bne tp,t0,80002b40 + +0000000080002b64 : + 80002b64: 00100293 li t0,1 + 80002b68: 00000317 auipc t1,0x0 + 80002b6c: 01c30313 addi t1,t1,28 # 80002b84 + 80002b70: ffc30067 jr -4(t1) + 80002b74: 00128293 addi t0,t0,1 + 80002b78: 00128293 addi t0,t0,1 + 80002b7c: 00128293 addi t0,t0,1 + 80002b80: 00128293 addi t0,t0,1 + 80002b84: 00128293 addi t0,t0,1 + 80002b88: 00128293 addi t0,t0,1 + 80002b8c: 00400e93 li t4,4 + 80002b90: 00700193 li gp,7 + 80002b94: 01d29463 bne t0,t4,80002b9c + 80002b98: 00301a63 bne zero,gp,80002bac + +0000000080002b9c : + 80002b9c: 00119513 slli a0,gp,0x1 + 80002ba0: 00050063 beqz a0,80002ba0 + 80002ba4: 00156513 ori a0,a0,1 + 80002ba8: 00000073 ecall + +0000000080002bac : + 80002bac: 00100513 li a0,1 + 80002bb0: 00000073 ecall + 80002bb4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-jalr.elf b/test/riscv/tests/rv64ui-v-jalr.elf new file mode 100644 index 00000000..80442747 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-jalr.elf differ diff --git a/test/riscv/tests/rv64ui-v-lb.dump b/test/riscv/tests/rv64ui-v-lb.dump new file mode 100644 index 00000000..fc9d680e --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lb.dump @@ -0,0 +1,1037 @@ + +rv64ui-v-lb: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 8d868693 addi a3,a3,-1832 # 80002d30 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 90c60613 addi a2,a2,-1780 # 80002dc0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 8d460613 addi a2,a2,-1836 # 80002dd8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 82468693 addi a3,a3,-2012 # 80002d78 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 84068693 addi a3,a3,-1984 # 80002eb0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7c060613 addi a2,a2,1984 # 80002e88 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 6f468693 addi a3,a3,1780 # 80002ee0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 61468693 addi a3,a3,1556 # 80002e50 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5a468693 addi a3,a3,1444 # 80002e18 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00600793 li a5,6 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0c1067b7 lui a5,0xc106 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 32278793 addi a5,a5,802 # c106322 <_start-0x73ef9cde> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 00008f03 lb t5,0(ra) + 80002ad4: fff00e93 li t4,-1 + 80002ad8: 00200193 li gp,2 + 80002adc: 23df1c63 bne t5,t4,80002d14 + +0000000080002ae0 : + 80002ae0: 00000097 auipc ra,0x0 + 80002ae4: 52008093 addi ra,ra,1312 # 80003000 + 80002ae8: 00108f03 lb t5,1(ra) + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 23df1063 bne t5,t4,80002d14 + +0000000080002af8 : + 80002af8: 00000097 auipc ra,0x0 + 80002afc: 50808093 addi ra,ra,1288 # 80003000 + 80002b00: 00208f03 lb t5,2(ra) + 80002b04: ff000e93 li t4,-16 + 80002b08: 00400193 li gp,4 + 80002b0c: 21df1463 bne t5,t4,80002d14 + +0000000080002b10 : + 80002b10: 00000097 auipc ra,0x0 + 80002b14: 4f008093 addi ra,ra,1264 # 80003000 + 80002b18: 00308f03 lb t5,3(ra) + 80002b1c: 00f00e93 li t4,15 + 80002b20: 00500193 li gp,5 + 80002b24: 1fdf1863 bne t5,t4,80002d14 + +0000000080002b28 : + 80002b28: 00000097 auipc ra,0x0 + 80002b2c: 4db08093 addi ra,ra,1243 # 80003003 + 80002b30: ffd08f03 lb t5,-3(ra) + 80002b34: fff00e93 li t4,-1 + 80002b38: 00600193 li gp,6 + 80002b3c: 1ddf1c63 bne t5,t4,80002d14 + +0000000080002b40 : + 80002b40: 00000097 auipc ra,0x0 + 80002b44: 4c308093 addi ra,ra,1219 # 80003003 + 80002b48: ffe08f03 lb t5,-2(ra) + 80002b4c: 00000e93 li t4,0 + 80002b50: 00700193 li gp,7 + 80002b54: 1ddf1063 bne t5,t4,80002d14 + +0000000080002b58 : + 80002b58: 00000097 auipc ra,0x0 + 80002b5c: 4ab08093 addi ra,ra,1195 # 80003003 + 80002b60: fff08f03 lb t5,-1(ra) + 80002b64: ff000e93 li t4,-16 + 80002b68: 00800193 li gp,8 + 80002b6c: 1bdf1463 bne t5,t4,80002d14 + +0000000080002b70 : + 80002b70: 00000097 auipc ra,0x0 + 80002b74: 49308093 addi ra,ra,1171 # 80003003 + 80002b78: 00008f03 lb t5,0(ra) + 80002b7c: 00f00e93 li t4,15 + 80002b80: 00900193 li gp,9 + 80002b84: 19df1863 bne t5,t4,80002d14 + +0000000080002b88 : + 80002b88: 00000097 auipc ra,0x0 + 80002b8c: 47808093 addi ra,ra,1144 # 80003000 + 80002b90: fe008093 addi ra,ra,-32 + 80002b94: 02008283 lb t0,32(ra) + 80002b98: fff00e93 li t4,-1 + 80002b9c: 00a00193 li gp,10 + 80002ba0: 17d29a63 bne t0,t4,80002d14 + +0000000080002ba4 : + 80002ba4: 00000097 auipc ra,0x0 + 80002ba8: 45c08093 addi ra,ra,1116 # 80003000 + 80002bac: ffa08093 addi ra,ra,-6 + 80002bb0: 00708283 lb t0,7(ra) + 80002bb4: 00000e93 li t4,0 + 80002bb8: 00b00193 li gp,11 + 80002bbc: 15d29c63 bne t0,t4,80002d14 + +0000000080002bc0 : + 80002bc0: 00c00193 li gp,12 + 80002bc4: 00000213 li tp,0 + 80002bc8: 00000097 auipc ra,0x0 + 80002bcc: 43908093 addi ra,ra,1081 # 80003001 + 80002bd0: 00108f03 lb t5,1(ra) + 80002bd4: 000f0313 mv t1,t5 + 80002bd8: ff000e93 li t4,-16 + 80002bdc: 13d31c63 bne t1,t4,80002d14 + 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002be4: 00200293 li t0,2 + 80002be8: fe5210e3 bne tp,t0,80002bc8 + +0000000080002bec : + 80002bec: 00d00193 li gp,13 + 80002bf0: 00000213 li tp,0 + 80002bf4: 00000097 auipc ra,0x0 + 80002bf8: 40e08093 addi ra,ra,1038 # 80003002 + 80002bfc: 00108f03 lb t5,1(ra) + 80002c00: 00000013 nop + 80002c04: 000f0313 mv t1,t5 + 80002c08: 00f00e93 li t4,15 + 80002c0c: 11d31463 bne t1,t4,80002d14 + 80002c10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c14: 00200293 li t0,2 + 80002c18: fc521ee3 bne tp,t0,80002bf4 + +0000000080002c1c : + 80002c1c: 00e00193 li gp,14 + 80002c20: 00000213 li tp,0 + 80002c24: 00000097 auipc ra,0x0 + 80002c28: 3dc08093 addi ra,ra,988 # 80003000 + 80002c2c: 00108f03 lb t5,1(ra) + 80002c30: 00000013 nop + 80002c34: 00000013 nop + 80002c38: 000f0313 mv t1,t5 + 80002c3c: 00000e93 li t4,0 + 80002c40: 0dd31a63 bne t1,t4,80002d14 + 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c48: 00200293 li t0,2 + 80002c4c: fc521ce3 bne tp,t0,80002c24 + +0000000080002c50 : + 80002c50: 00f00193 li gp,15 + 80002c54: 00000213 li tp,0 + 80002c58: 00000097 auipc ra,0x0 + 80002c5c: 3a908093 addi ra,ra,937 # 80003001 + 80002c60: 00108f03 lb t5,1(ra) + 80002c64: ff000e93 li t4,-16 + 80002c68: 0bdf1663 bne t5,t4,80002d14 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5212e3 bne tp,t0,80002c58 + +0000000080002c78 : + 80002c78: 01000193 li gp,16 + 80002c7c: 00000213 li tp,0 + 80002c80: 00000097 auipc ra,0x0 + 80002c84: 38208093 addi ra,ra,898 # 80003002 + 80002c88: 00000013 nop + 80002c8c: 00108f03 lb t5,1(ra) + 80002c90: 00f00e93 li t4,15 + 80002c94: 09df1063 bne t5,t4,80002d14 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5210e3 bne tp,t0,80002c80 + +0000000080002ca4 : + 80002ca4: 01100193 li gp,17 + 80002ca8: 00000213 li tp,0 + 80002cac: 00000097 auipc ra,0x0 + 80002cb0: 35408093 addi ra,ra,852 # 80003000 + 80002cb4: 00000013 nop + 80002cb8: 00000013 nop + 80002cbc: 00108f03 lb t5,1(ra) + 80002cc0: 00000e93 li t4,0 + 80002cc4: 05df1863 bne t5,t4,80002d14 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fc521ee3 bne tp,t0,80002cac + +0000000080002cd4 : + 80002cd4: 00000297 auipc t0,0x0 + 80002cd8: 32c28293 addi t0,t0,812 # 80003000 + 80002cdc: 00028103 lb sp,0(t0) + 80002ce0: 00200113 li sp,2 + 80002ce4: 00200e93 li t4,2 + 80002ce8: 01200193 li gp,18 + 80002cec: 03d11463 bne sp,t4,80002d14 + +0000000080002cf0 : + 80002cf0: 00000297 auipc t0,0x0 + 80002cf4: 31028293 addi t0,t0,784 # 80003000 + 80002cf8: 00028103 lb sp,0(t0) + 80002cfc: 00000013 nop + 80002d00: 00200113 li sp,2 + 80002d04: 00200e93 li t4,2 + 80002d08: 01300193 li gp,19 + 80002d0c: 01d11463 bne sp,t4,80002d14 + 80002d10: 00301a63 bne zero,gp,80002d24 + +0000000080002d14 : + 80002d14: 00119513 slli a0,gp,0x1 + 80002d18: 00050063 beqz a0,80002d18 + 80002d1c: 00156513 ori a0,a0,1 + 80002d20: 00000073 ecall + +0000000080002d24 : + 80002d24: 00100513 li a0,1 + 80002d28: 00000073 ecall + 80002d2c: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 0xff + +0000000080003001 : + 80003001: sd s0,32(s0) + +0000000080003002 : + 80003002: addi a2,sp,988 + +0000000080003003 : + 80003003: 0f Address 0x0000000080003003 is out of bounds. + + 80003007: diff --git a/test/riscv/tests/rv64ui-v-lb.elf b/test/riscv/tests/rv64ui-v-lb.elf new file mode 100644 index 00000000..438c0905 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lb.elf differ diff --git a/test/riscv/tests/rv64ui-v-lbu.dump b/test/riscv/tests/rv64ui-v-lbu.dump new file mode 100644 index 00000000..8de55fb8 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lbu.dump @@ -0,0 +1,1037 @@ + +rv64ui-v-lbu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 8d868693 addi a3,a3,-1832 # 80002d30 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 90c60613 addi a2,a2,-1780 # 80002dc0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 8d460613 addi a2,a2,-1836 # 80002dd8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 82468693 addi a3,a3,-2012 # 80002d78 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 84068693 addi a3,a3,-1984 # 80002eb0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7c060613 addi a2,a2,1984 # 80002e88 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 6f468693 addi a3,a3,1780 # 80002ee0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 61468693 addi a3,a3,1556 # 80002e50 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5a468693 addi a3,a3,1444 # 80002e18 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00d00793 li a5,13 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 04c8f7b7 lui a5,0x4c8f + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 8a478793 addi a5,a5,-1884 # 4c8e8a4 <_start-0x7b37175c> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 0000cf03 lbu t5,0(ra) + 80002ad4: 0ff00e93 li t4,255 + 80002ad8: 00200193 li gp,2 + 80002adc: 23df1c63 bne t5,t4,80002d14 + +0000000080002ae0 : + 80002ae0: 00000097 auipc ra,0x0 + 80002ae4: 52008093 addi ra,ra,1312 # 80003000 + 80002ae8: 0010cf03 lbu t5,1(ra) + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 23df1063 bne t5,t4,80002d14 + +0000000080002af8 : + 80002af8: 00000097 auipc ra,0x0 + 80002afc: 50808093 addi ra,ra,1288 # 80003000 + 80002b00: 0020cf03 lbu t5,2(ra) + 80002b04: 0f000e93 li t4,240 + 80002b08: 00400193 li gp,4 + 80002b0c: 21df1463 bne t5,t4,80002d14 + +0000000080002b10 : + 80002b10: 00000097 auipc ra,0x0 + 80002b14: 4f008093 addi ra,ra,1264 # 80003000 + 80002b18: 0030cf03 lbu t5,3(ra) + 80002b1c: 00f00e93 li t4,15 + 80002b20: 00500193 li gp,5 + 80002b24: 1fdf1863 bne t5,t4,80002d14 + +0000000080002b28 : + 80002b28: 00000097 auipc ra,0x0 + 80002b2c: 4db08093 addi ra,ra,1243 # 80003003 + 80002b30: ffd0cf03 lbu t5,-3(ra) + 80002b34: 0ff00e93 li t4,255 + 80002b38: 00600193 li gp,6 + 80002b3c: 1ddf1c63 bne t5,t4,80002d14 + +0000000080002b40 : + 80002b40: 00000097 auipc ra,0x0 + 80002b44: 4c308093 addi ra,ra,1219 # 80003003 + 80002b48: ffe0cf03 lbu t5,-2(ra) + 80002b4c: 00000e93 li t4,0 + 80002b50: 00700193 li gp,7 + 80002b54: 1ddf1063 bne t5,t4,80002d14 + +0000000080002b58 : + 80002b58: 00000097 auipc ra,0x0 + 80002b5c: 4ab08093 addi ra,ra,1195 # 80003003 + 80002b60: fff0cf03 lbu t5,-1(ra) + 80002b64: 0f000e93 li t4,240 + 80002b68: 00800193 li gp,8 + 80002b6c: 1bdf1463 bne t5,t4,80002d14 + +0000000080002b70 : + 80002b70: 00000097 auipc ra,0x0 + 80002b74: 49308093 addi ra,ra,1171 # 80003003 + 80002b78: 0000cf03 lbu t5,0(ra) + 80002b7c: 00f00e93 li t4,15 + 80002b80: 00900193 li gp,9 + 80002b84: 19df1863 bne t5,t4,80002d14 + +0000000080002b88 : + 80002b88: 00000097 auipc ra,0x0 + 80002b8c: 47808093 addi ra,ra,1144 # 80003000 + 80002b90: fe008093 addi ra,ra,-32 + 80002b94: 0200c283 lbu t0,32(ra) + 80002b98: 0ff00e93 li t4,255 + 80002b9c: 00a00193 li gp,10 + 80002ba0: 17d29a63 bne t0,t4,80002d14 + +0000000080002ba4 : + 80002ba4: 00000097 auipc ra,0x0 + 80002ba8: 45c08093 addi ra,ra,1116 # 80003000 + 80002bac: ffa08093 addi ra,ra,-6 + 80002bb0: 0070c283 lbu t0,7(ra) + 80002bb4: 00000e93 li t4,0 + 80002bb8: 00b00193 li gp,11 + 80002bbc: 15d29c63 bne t0,t4,80002d14 + +0000000080002bc0 : + 80002bc0: 00c00193 li gp,12 + 80002bc4: 00000213 li tp,0 + 80002bc8: 00000097 auipc ra,0x0 + 80002bcc: 43908093 addi ra,ra,1081 # 80003001 + 80002bd0: 0010cf03 lbu t5,1(ra) + 80002bd4: 000f0313 mv t1,t5 + 80002bd8: 0f000e93 li t4,240 + 80002bdc: 13d31c63 bne t1,t4,80002d14 + 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002be4: 00200293 li t0,2 + 80002be8: fe5210e3 bne tp,t0,80002bc8 + +0000000080002bec : + 80002bec: 00d00193 li gp,13 + 80002bf0: 00000213 li tp,0 + 80002bf4: 00000097 auipc ra,0x0 + 80002bf8: 40e08093 addi ra,ra,1038 # 80003002 + 80002bfc: 0010cf03 lbu t5,1(ra) + 80002c00: 00000013 nop + 80002c04: 000f0313 mv t1,t5 + 80002c08: 00f00e93 li t4,15 + 80002c0c: 11d31463 bne t1,t4,80002d14 + 80002c10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c14: 00200293 li t0,2 + 80002c18: fc521ee3 bne tp,t0,80002bf4 + +0000000080002c1c : + 80002c1c: 00e00193 li gp,14 + 80002c20: 00000213 li tp,0 + 80002c24: 00000097 auipc ra,0x0 + 80002c28: 3dc08093 addi ra,ra,988 # 80003000 + 80002c2c: 0010cf03 lbu t5,1(ra) + 80002c30: 00000013 nop + 80002c34: 00000013 nop + 80002c38: 000f0313 mv t1,t5 + 80002c3c: 00000e93 li t4,0 + 80002c40: 0dd31a63 bne t1,t4,80002d14 + 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c48: 00200293 li t0,2 + 80002c4c: fc521ce3 bne tp,t0,80002c24 + +0000000080002c50 : + 80002c50: 00f00193 li gp,15 + 80002c54: 00000213 li tp,0 + 80002c58: 00000097 auipc ra,0x0 + 80002c5c: 3a908093 addi ra,ra,937 # 80003001 + 80002c60: 0010cf03 lbu t5,1(ra) + 80002c64: 0f000e93 li t4,240 + 80002c68: 0bdf1663 bne t5,t4,80002d14 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5212e3 bne tp,t0,80002c58 + +0000000080002c78 : + 80002c78: 01000193 li gp,16 + 80002c7c: 00000213 li tp,0 + 80002c80: 00000097 auipc ra,0x0 + 80002c84: 38208093 addi ra,ra,898 # 80003002 + 80002c88: 00000013 nop + 80002c8c: 0010cf03 lbu t5,1(ra) + 80002c90: 00f00e93 li t4,15 + 80002c94: 09df1063 bne t5,t4,80002d14 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5210e3 bne tp,t0,80002c80 + +0000000080002ca4 : + 80002ca4: 01100193 li gp,17 + 80002ca8: 00000213 li tp,0 + 80002cac: 00000097 auipc ra,0x0 + 80002cb0: 35408093 addi ra,ra,852 # 80003000 + 80002cb4: 00000013 nop + 80002cb8: 00000013 nop + 80002cbc: 0010cf03 lbu t5,1(ra) + 80002cc0: 00000e93 li t4,0 + 80002cc4: 05df1863 bne t5,t4,80002d14 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fc521ee3 bne tp,t0,80002cac + +0000000080002cd4 : + 80002cd4: 00000297 auipc t0,0x0 + 80002cd8: 32c28293 addi t0,t0,812 # 80003000 + 80002cdc: 0002c103 lbu sp,0(t0) + 80002ce0: 00200113 li sp,2 + 80002ce4: 00200e93 li t4,2 + 80002ce8: 01200193 li gp,18 + 80002cec: 03d11463 bne sp,t4,80002d14 + +0000000080002cf0 : + 80002cf0: 00000297 auipc t0,0x0 + 80002cf4: 31028293 addi t0,t0,784 # 80003000 + 80002cf8: 0002c103 lbu sp,0(t0) + 80002cfc: 00000013 nop + 80002d00: 00200113 li sp,2 + 80002d04: 00200e93 li t4,2 + 80002d08: 01300193 li gp,19 + 80002d0c: 01d11463 bne sp,t4,80002d14 + 80002d10: 00301a63 bne zero,gp,80002d24 + +0000000080002d14 : + 80002d14: 00119513 slli a0,gp,0x1 + 80002d18: 00050063 beqz a0,80002d18 + 80002d1c: 00156513 ori a0,a0,1 + 80002d20: 00000073 ecall + +0000000080002d24 : + 80002d24: 00100513 li a0,1 + 80002d28: 00000073 ecall + 80002d2c: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 0xff + +0000000080003001 : + 80003001: sd s0,32(s0) + +0000000080003002 : + 80003002: addi a2,sp,988 + +0000000080003003 : + 80003003: 0f Address 0x0000000080003003 is out of bounds. + + 80003007: diff --git a/test/riscv/tests/rv64ui-v-lbu.elf b/test/riscv/tests/rv64ui-v-lbu.elf new file mode 100644 index 00000000..2f2023bb Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lbu.elf differ diff --git a/test/riscv/tests/rv64ui-v-ld.dump b/test/riscv/tests/rv64ui-v-ld.dump new file mode 100644 index 00000000..3d8b640c --- /dev/null +++ b/test/riscv/tests/rv64ui-v-ld.dump @@ -0,0 +1,1141 @@ + +rv64ui-v-ld: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000a117 auipc sp,0xa + 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00003617 auipc a2,0x3 + 80002318: cec60613 addi a2,a2,-788 # 80005000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00007797 auipc a5,0x7 + 80002334: 4b878793 addi a5,a5,1208 # 800097e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00007717 auipc a4,0x7 + 80002348: 49c70713 addi a4,a4,1180 # 800097e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00007897 auipc a7,0x7 + 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00007797 auipc a5,0x7 + 80002384: 07078793 addi a5,a5,112 # 800093f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00007797 auipc a5,0x7 + 80002448: 3807be23 sd zero,924(a5) # 800097e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: a5868693 addi a3,a3,-1448 # 80002eb0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: a8c60613 addi a2,a2,-1396 # 80002f40 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: a5460613 addi a2,a2,-1452 # 80002f58 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 9a468693 addi a3,a3,-1628 # 80002ef8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 9c068693 addi a3,a3,-1600 # 80003030 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 94060613 addi a2,a2,-1728 # 80003008 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00007d17 auipc s10,0x7 + 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 + 80002724: 00003b97 auipc s7,0x3 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00007a17 auipc s4,0x7 + 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00007717 auipc a4,0x7 + 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00007717 auipc a4,0x7 + 800027d4: 00f73823 sd a5,16(a4) # 800097e0 + 800027d8: 00007717 auipc a4,0x7 + 800027dc: 00f73823 sd a5,16(a4) # 800097e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 87468693 addi a3,a3,-1932 # 80003060 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 79468693 addi a3,a3,1940 # 80002fd0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 72468693 addi a3,a3,1828 # 80002f98 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00003697 auipc a3,0x3 + 800028e0: 72468693 addi a3,a3,1828 # 80006000 + 800028e4: 00004717 auipc a4,0x4 + 800028e8: 71c70713 addi a4,a4,1820 # 80007000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00005797 auipc a5,0x5 + 800028f8: 70c78793 addi a5,a5,1804 # 80008000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00002897 auipc a7,0x2 + 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00003697 auipc a3,0x3 + 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00002617 auipc a2,0x2 + 80002938: 6cc60613 addi a2,a2,1740 # 80005000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00005697 auipc a3,0x5 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 + 8000294c: 00003717 auipc a4,0x3 + 80002950: 6af73a23 sd a5,1716(a4) # 80006000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00006697 auipc a3,0x6 + 800029c0: 64468693 addi a3,a3,1604 # 80009000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00007617 auipc a2,0x7 + 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 + 800029d4: 00007797 auipc a5,0x7 + 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 + 800029dc: 00007317 auipc t1,0x7 + 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 + 800029e4: 02d00793 li a5,45 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00007797 auipc a5,0x7 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 055417b7 lui a5,0x5541 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b2578793 addi a5,a5,-1243 # 5540b25 <_start-0x7aabf4db> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00001097 auipc ra,0x1 + 80002acc: 53808093 addi ra,ra,1336 # 80004000 + 80002ad0: 0000bf03 ld t5,0(ra) + 80002ad4: 00ff0eb7 lui t4,0xff0 + 80002ad8: 0ffe8e9b addiw t4,t4,255 + 80002adc: 010e9e93 slli t4,t4,0x10 + 80002ae0: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 80002ae4: 010e9e93 slli t4,t4,0x10 + 80002ae8: 0ffe8e93 addi t4,t4,255 + 80002aec: 00200193 li gp,2 + 80002af0: 3bdf1263 bne t5,t4,80002e94 + +0000000080002af4 : + 80002af4: 00001097 auipc ra,0x1 + 80002af8: 50c08093 addi ra,ra,1292 # 80004000 + 80002afc: 0080bf03 ld t5,8(ra) + 80002b00: ff010eb7 lui t4,0xff010 + 80002b04: f01e8e9b addiw t4,t4,-255 + 80002b08: 010e9e93 slli t4,t4,0x10 + 80002b0c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> + 80002b10: 010e9e93 slli t4,t4,0x10 + 80002b14: f00e8e93 addi t4,t4,-256 + 80002b18: 00300193 li gp,3 + 80002b1c: 37df1c63 bne t5,t4,80002e94 + +0000000080002b20 : + 80002b20: 00001097 auipc ra,0x1 + 80002b24: 4e008093 addi ra,ra,1248 # 80004000 + 80002b28: 0100bf03 ld t5,16(ra) + 80002b2c: 00010eb7 lui t4,0x10 + 80002b30: f01e8e9b addiw t4,t4,-255 + 80002b34: 010e9e93 slli t4,t4,0x10 + 80002b38: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80002b3c: 010e9e93 slli t4,t4,0x10 + 80002b40: f01e8e93 addi t4,t4,-255 + 80002b44: 00ce9e93 slli t4,t4,0xc + 80002b48: ff0e8e93 addi t4,t4,-16 + 80002b4c: 00400193 li gp,4 + 80002b50: 35df1263 bne t5,t4,80002e94 + +0000000080002b54 : + 80002b54: 00001097 auipc ra,0x1 + 80002b58: 4ac08093 addi ra,ra,1196 # 80004000 + 80002b5c: 0180bf03 ld t5,24(ra) + 80002b60: ffff0eb7 lui t4,0xffff0 + 80002b64: 0ffe8e9b addiw t4,t4,255 + 80002b68: 010e9e93 slli t4,t4,0x10 + 80002b6c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> + 80002b70: 010e9e93 slli t4,t4,0x10 + 80002b74: 0ffe8e93 addi t4,t4,255 + 80002b78: 00ce9e93 slli t4,t4,0xc + 80002b7c: 00fe8e93 addi t4,t4,15 + 80002b80: 00500193 li gp,5 + 80002b84: 31df1863 bne t5,t4,80002e94 + +0000000080002b88 : + 80002b88: 00001097 auipc ra,0x1 + 80002b8c: 49008093 addi ra,ra,1168 # 80004018 + 80002b90: fe80bf03 ld t5,-24(ra) + 80002b94: 00ff0eb7 lui t4,0xff0 + 80002b98: 0ffe8e9b addiw t4,t4,255 + 80002b9c: 010e9e93 slli t4,t4,0x10 + 80002ba0: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 80002ba4: 010e9e93 slli t4,t4,0x10 + 80002ba8: 0ffe8e93 addi t4,t4,255 + 80002bac: 00600193 li gp,6 + 80002bb0: 2fdf1263 bne t5,t4,80002e94 + +0000000080002bb4 : + 80002bb4: 00001097 auipc ra,0x1 + 80002bb8: 46408093 addi ra,ra,1124 # 80004018 + 80002bbc: ff00bf03 ld t5,-16(ra) + 80002bc0: ff010eb7 lui t4,0xff010 + 80002bc4: f01e8e9b addiw t4,t4,-255 + 80002bc8: 010e9e93 slli t4,t4,0x10 + 80002bcc: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> + 80002bd0: 010e9e93 slli t4,t4,0x10 + 80002bd4: f00e8e93 addi t4,t4,-256 + 80002bd8: 00700193 li gp,7 + 80002bdc: 2bdf1c63 bne t5,t4,80002e94 + +0000000080002be0 : + 80002be0: 00001097 auipc ra,0x1 + 80002be4: 43808093 addi ra,ra,1080 # 80004018 + 80002be8: ff80bf03 ld t5,-8(ra) + 80002bec: 00010eb7 lui t4,0x10 + 80002bf0: f01e8e9b addiw t4,t4,-255 + 80002bf4: 010e9e93 slli t4,t4,0x10 + 80002bf8: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80002bfc: 010e9e93 slli t4,t4,0x10 + 80002c00: f01e8e93 addi t4,t4,-255 + 80002c04: 00ce9e93 slli t4,t4,0xc + 80002c08: ff0e8e93 addi t4,t4,-16 + 80002c0c: 00800193 li gp,8 + 80002c10: 29df1263 bne t5,t4,80002e94 + +0000000080002c14 : + 80002c14: 00001097 auipc ra,0x1 + 80002c18: 40408093 addi ra,ra,1028 # 80004018 + 80002c1c: 0000bf03 ld t5,0(ra) + 80002c20: ffff0eb7 lui t4,0xffff0 + 80002c24: 0ffe8e9b addiw t4,t4,255 + 80002c28: 010e9e93 slli t4,t4,0x10 + 80002c2c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> + 80002c30: 010e9e93 slli t4,t4,0x10 + 80002c34: 0ffe8e93 addi t4,t4,255 + 80002c38: 00ce9e93 slli t4,t4,0xc + 80002c3c: 00fe8e93 addi t4,t4,15 + 80002c40: 00900193 li gp,9 + 80002c44: 25df1863 bne t5,t4,80002e94 + +0000000080002c48 : + 80002c48: 00001097 auipc ra,0x1 + 80002c4c: 3b808093 addi ra,ra,952 # 80004000 + 80002c50: fe008093 addi ra,ra,-32 + 80002c54: 0200b283 ld t0,32(ra) + 80002c58: 00ff0eb7 lui t4,0xff0 + 80002c5c: 0ffe8e9b addiw t4,t4,255 + 80002c60: 010e9e93 slli t4,t4,0x10 + 80002c64: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 80002c68: 010e9e93 slli t4,t4,0x10 + 80002c6c: 0ffe8e93 addi t4,t4,255 + 80002c70: 00a00193 li gp,10 + 80002c74: 23d29063 bne t0,t4,80002e94 + +0000000080002c78 : + 80002c78: 00001097 auipc ra,0x1 + 80002c7c: 38808093 addi ra,ra,904 # 80004000 + 80002c80: ffd08093 addi ra,ra,-3 + 80002c84: 00b0b283 ld t0,11(ra) + 80002c88: ff010eb7 lui t4,0xff010 + 80002c8c: f01e8e9b addiw t4,t4,-255 + 80002c90: 010e9e93 slli t4,t4,0x10 + 80002c94: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> + 80002c98: 010e9e93 slli t4,t4,0x10 + 80002c9c: f00e8e93 addi t4,t4,-256 + 80002ca0: 00b00193 li gp,11 + 80002ca4: 1fd29863 bne t0,t4,80002e94 + +0000000080002ca8 : + 80002ca8: 00c00193 li gp,12 + 80002cac: 00000213 li tp,0 + 80002cb0: 00001097 auipc ra,0x1 + 80002cb4: 35808093 addi ra,ra,856 # 80004008 + 80002cb8: 0080bf03 ld t5,8(ra) + 80002cbc: 000f0313 mv t1,t5 + 80002cc0: 00010eb7 lui t4,0x10 + 80002cc4: f01e8e9b addiw t4,t4,-255 + 80002cc8: 010e9e93 slli t4,t4,0x10 + 80002ccc: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80002cd0: 010e9e93 slli t4,t4,0x10 + 80002cd4: f01e8e93 addi t4,t4,-255 + 80002cd8: 00ce9e93 slli t4,t4,0xc + 80002cdc: ff0e8e93 addi t4,t4,-16 + 80002ce0: 1bd31a63 bne t1,t4,80002e94 + 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce8: 00200293 li t0,2 + 80002cec: fc5212e3 bne tp,t0,80002cb0 + +0000000080002cf0 : + 80002cf0: 00d00193 li gp,13 + 80002cf4: 00000213 li tp,0 + 80002cf8: 00001097 auipc ra,0x1 + 80002cfc: 31808093 addi ra,ra,792 # 80004010 + 80002d00: 0080bf03 ld t5,8(ra) + 80002d04: 00000013 nop + 80002d08: 000f0313 mv t1,t5 + 80002d0c: ffff0eb7 lui t4,0xffff0 + 80002d10: 0ffe8e9b addiw t4,t4,255 + 80002d14: 010e9e93 slli t4,t4,0x10 + 80002d18: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> + 80002d1c: 010e9e93 slli t4,t4,0x10 + 80002d20: 0ffe8e93 addi t4,t4,255 + 80002d24: 00ce9e93 slli t4,t4,0xc + 80002d28: 00fe8e93 addi t4,t4,15 + 80002d2c: 17d31463 bne t1,t4,80002e94 + 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d34: 00200293 li t0,2 + 80002d38: fc5210e3 bne tp,t0,80002cf8 + +0000000080002d3c : + 80002d3c: 00e00193 li gp,14 + 80002d40: 00000213 li tp,0 + 80002d44: 00001097 auipc ra,0x1 + 80002d48: 2bc08093 addi ra,ra,700 # 80004000 + 80002d4c: 0080bf03 ld t5,8(ra) + 80002d50: 00000013 nop + 80002d54: 00000013 nop + 80002d58: 000f0313 mv t1,t5 + 80002d5c: ff010eb7 lui t4,0xff010 + 80002d60: f01e8e9b addiw t4,t4,-255 + 80002d64: 010e9e93 slli t4,t4,0x10 + 80002d68: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> + 80002d6c: 010e9e93 slli t4,t4,0x10 + 80002d70: f00e8e93 addi t4,t4,-256 + 80002d74: 13d31063 bne t1,t4,80002e94 + 80002d78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d7c: 00200293 li t0,2 + 80002d80: fc5212e3 bne tp,t0,80002d44 + +0000000080002d84 : + 80002d84: 00f00193 li gp,15 + 80002d88: 00000213 li tp,0 + 80002d8c: 00001097 auipc ra,0x1 + 80002d90: 27c08093 addi ra,ra,636 # 80004008 + 80002d94: 0080bf03 ld t5,8(ra) + 80002d98: 00010eb7 lui t4,0x10 + 80002d9c: f01e8e9b addiw t4,t4,-255 + 80002da0: 010e9e93 slli t4,t4,0x10 + 80002da4: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80002da8: 010e9e93 slli t4,t4,0x10 + 80002dac: f01e8e93 addi t4,t4,-255 + 80002db0: 00ce9e93 slli t4,t4,0xc + 80002db4: ff0e8e93 addi t4,t4,-16 + 80002db8: 0ddf1e63 bne t5,t4,80002e94 + 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dc0: 00200293 li t0,2 + 80002dc4: fc5214e3 bne tp,t0,80002d8c + +0000000080002dc8 : + 80002dc8: 01000193 li gp,16 + 80002dcc: 00000213 li tp,0 + 80002dd0: 00001097 auipc ra,0x1 + 80002dd4: 24008093 addi ra,ra,576 # 80004010 + 80002dd8: 00000013 nop + 80002ddc: 0080bf03 ld t5,8(ra) + 80002de0: ffff0eb7 lui t4,0xffff0 + 80002de4: 0ffe8e9b addiw t4,t4,255 + 80002de8: 010e9e93 slli t4,t4,0x10 + 80002dec: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> + 80002df0: 010e9e93 slli t4,t4,0x10 + 80002df4: 0ffe8e93 addi t4,t4,255 + 80002df8: 00ce9e93 slli t4,t4,0xc + 80002dfc: 00fe8e93 addi t4,t4,15 + 80002e00: 09df1a63 bne t5,t4,80002e94 + 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e08: 00200293 li t0,2 + 80002e0c: fc5212e3 bne tp,t0,80002dd0 + +0000000080002e10 : + 80002e10: 01100193 li gp,17 + 80002e14: 00000213 li tp,0 + 80002e18: 00001097 auipc ra,0x1 + 80002e1c: 1e808093 addi ra,ra,488 # 80004000 + 80002e20: 00000013 nop + 80002e24: 00000013 nop + 80002e28: 0080bf03 ld t5,8(ra) + 80002e2c: ff010eb7 lui t4,0xff010 + 80002e30: f01e8e9b addiw t4,t4,-255 + 80002e34: 010e9e93 slli t4,t4,0x10 + 80002e38: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> + 80002e3c: 010e9e93 slli t4,t4,0x10 + 80002e40: f00e8e93 addi t4,t4,-256 + 80002e44: 05df1863 bne t5,t4,80002e94 + 80002e48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e4c: 00200293 li t0,2 + 80002e50: fc5214e3 bne tp,t0,80002e18 + +0000000080002e54 : + 80002e54: 00001297 auipc t0,0x1 + 80002e58: 1ac28293 addi t0,t0,428 # 80004000 + 80002e5c: 0002b103 ld sp,0(t0) + 80002e60: 00200113 li sp,2 + 80002e64: 00200e93 li t4,2 + 80002e68: 01200193 li gp,18 + 80002e6c: 03d11463 bne sp,t4,80002e94 + +0000000080002e70 : + 80002e70: 00001297 auipc t0,0x1 + 80002e74: 19028293 addi t0,t0,400 # 80004000 + 80002e78: 0002b103 ld sp,0(t0) + 80002e7c: 00000013 nop + 80002e80: 00200113 li sp,2 + 80002e84: 00200e93 li t4,2 + 80002e88: 01300193 li gp,19 + 80002e8c: 01d11463 bne sp,t4,80002e94 + 80002e90: 00301a63 bne zero,gp,80002ea4 + +0000000080002e94 : + 80002e94: 00119513 slli a0,gp,0x1 + 80002e98: 00050063 beqz a0,80002e98 + 80002e9c: 00156513 ori a0,a0,1 + 80002ea0: 00000073 ecall + +0000000080002ea4 : + 80002ea4: 00100513 li a0,1 + 80002ea8: 00000073 ecall + 80002eac: c0001073 unimp + +Disassembly of section .data: + +0000000080004000 : + 80004000: 00ff 0xff + 80004002: 00ff 0xff + 80004004: 00ff 0xff + 80004006: 00ff 0xff + +0000000080004008 : + 80004008: ff00 sd s0,56(a4) + 8000400a: ff00 sd s0,56(a4) + 8000400c: ff00 sd s0,56(a4) + 8000400e: ff00 sd s0,56(a4) + +0000000080004010 : + 80004010: 0ff0 addi a2,sp,988 + 80004012: 0ff0 addi a2,sp,988 + 80004014: 0ff0 addi a2,sp,988 + 80004016: 0ff0 addi a2,sp,988 + +0000000080004018 : + 80004018: f00ff00f 0xf00ff00f + 8000401c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-ld.elf b/test/riscv/tests/rv64ui-v-ld.elf new file mode 100644 index 00000000..29406988 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-ld.elf differ diff --git a/test/riscv/tests/rv64ui-v-lh.dump b/test/riscv/tests/rv64ui-v-lh.dump new file mode 100644 index 00000000..50f2fddc --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lh.dump @@ -0,0 +1,1043 @@ + +rv64ui-v-lh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 8f868693 addi a3,a3,-1800 # 80002d50 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 92c60613 addi a2,a2,-1748 # 80002de0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 8f460613 addi a2,a2,-1804 # 80002df8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 84468693 addi a3,a3,-1980 # 80002d98 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 86068693 addi a3,a3,-1952 # 80002ed0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7e060613 addi a2,a2,2016 # 80002ea8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 71468693 addi a3,a3,1812 # 80002f00 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 63468693 addi a3,a3,1588 # 80002e70 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5c468693 addi a3,a3,1476 # 80002e38 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00700793 li a5,7 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 039687b7 lui a5,0x3968 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: c8378793 addi a5,a5,-893 # 3967c83 <_start-0x7c69837d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 00009f03 lh t5,0(ra) + 80002ad4: 0ff00e93 li t4,255 + 80002ad8: 00200193 li gp,2 + 80002adc: 25df1c63 bne t5,t4,80002d34 + +0000000080002ae0 : + 80002ae0: 00000097 auipc ra,0x0 + 80002ae4: 52008093 addi ra,ra,1312 # 80003000 + 80002ae8: 00209f03 lh t5,2(ra) + 80002aec: f0000e93 li t4,-256 + 80002af0: 00300193 li gp,3 + 80002af4: 25df1063 bne t5,t4,80002d34 + +0000000080002af8 : + 80002af8: 00000097 auipc ra,0x0 + 80002afc: 50808093 addi ra,ra,1288 # 80003000 + 80002b00: 00409f03 lh t5,4(ra) + 80002b04: 00001eb7 lui t4,0x1 + 80002b08: ff0e8e9b addiw t4,t4,-16 + 80002b0c: 00400193 li gp,4 + 80002b10: 23df1263 bne t5,t4,80002d34 + +0000000080002b14 : + 80002b14: 00000097 auipc ra,0x0 + 80002b18: 4ec08093 addi ra,ra,1260 # 80003000 + 80002b1c: 00609f03 lh t5,6(ra) + 80002b20: fffffeb7 lui t4,0xfffff + 80002b24: 00fe8e9b addiw t4,t4,15 + 80002b28: 00500193 li gp,5 + 80002b2c: 21df1463 bne t5,t4,80002d34 + +0000000080002b30 : + 80002b30: 00000097 auipc ra,0x0 + 80002b34: 4d608093 addi ra,ra,1238 # 80003006 + 80002b38: ffa09f03 lh t5,-6(ra) + 80002b3c: 0ff00e93 li t4,255 + 80002b40: 00600193 li gp,6 + 80002b44: 1fdf1863 bne t5,t4,80002d34 + +0000000080002b48 : + 80002b48: 00000097 auipc ra,0x0 + 80002b4c: 4be08093 addi ra,ra,1214 # 80003006 + 80002b50: ffc09f03 lh t5,-4(ra) + 80002b54: f0000e93 li t4,-256 + 80002b58: 00700193 li gp,7 + 80002b5c: 1ddf1c63 bne t5,t4,80002d34 + +0000000080002b60 : + 80002b60: 00000097 auipc ra,0x0 + 80002b64: 4a608093 addi ra,ra,1190 # 80003006 + 80002b68: ffe09f03 lh t5,-2(ra) + 80002b6c: 00001eb7 lui t4,0x1 + 80002b70: ff0e8e9b addiw t4,t4,-16 + 80002b74: 00800193 li gp,8 + 80002b78: 1bdf1e63 bne t5,t4,80002d34 + +0000000080002b7c : + 80002b7c: 00000097 auipc ra,0x0 + 80002b80: 48a08093 addi ra,ra,1162 # 80003006 + 80002b84: 00009f03 lh t5,0(ra) + 80002b88: fffffeb7 lui t4,0xfffff + 80002b8c: 00fe8e9b addiw t4,t4,15 + 80002b90: 00900193 li gp,9 + 80002b94: 1bdf1063 bne t5,t4,80002d34 + +0000000080002b98 : + 80002b98: 00000097 auipc ra,0x0 + 80002b9c: 46808093 addi ra,ra,1128 # 80003000 + 80002ba0: fe008093 addi ra,ra,-32 + 80002ba4: 02009283 lh t0,32(ra) + 80002ba8: 0ff00e93 li t4,255 + 80002bac: 00a00193 li gp,10 + 80002bb0: 19d29263 bne t0,t4,80002d34 + +0000000080002bb4 : + 80002bb4: 00000097 auipc ra,0x0 + 80002bb8: 44c08093 addi ra,ra,1100 # 80003000 + 80002bbc: ffb08093 addi ra,ra,-5 + 80002bc0: 00709283 lh t0,7(ra) + 80002bc4: f0000e93 li t4,-256 + 80002bc8: 00b00193 li gp,11 + 80002bcc: 17d29463 bne t0,t4,80002d34 + +0000000080002bd0 : + 80002bd0: 00c00193 li gp,12 + 80002bd4: 00000213 li tp,0 + 80002bd8: 00000097 auipc ra,0x0 + 80002bdc: 42a08093 addi ra,ra,1066 # 80003002 + 80002be0: 00209f03 lh t5,2(ra) + 80002be4: 000f0313 mv t1,t5 + 80002be8: 00001eb7 lui t4,0x1 + 80002bec: ff0e8e9b addiw t4,t4,-16 + 80002bf0: 15d31263 bne t1,t4,80002d34 + 80002bf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bf8: 00200293 li t0,2 + 80002bfc: fc521ee3 bne tp,t0,80002bd8 + +0000000080002c00 : + 80002c00: 00d00193 li gp,13 + 80002c04: 00000213 li tp,0 + 80002c08: 00000097 auipc ra,0x0 + 80002c0c: 3fc08093 addi ra,ra,1020 # 80003004 + 80002c10: 00209f03 lh t5,2(ra) + 80002c14: 00000013 nop + 80002c18: 000f0313 mv t1,t5 + 80002c1c: fffffeb7 lui t4,0xfffff + 80002c20: 00fe8e9b addiw t4,t4,15 + 80002c24: 11d31863 bne t1,t4,80002d34 + 80002c28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c2c: 00200293 li t0,2 + 80002c30: fc521ce3 bne tp,t0,80002c08 + +0000000080002c34 : + 80002c34: 00e00193 li gp,14 + 80002c38: 00000213 li tp,0 + 80002c3c: 00000097 auipc ra,0x0 + 80002c40: 3c408093 addi ra,ra,964 # 80003000 + 80002c44: 00209f03 lh t5,2(ra) + 80002c48: 00000013 nop + 80002c4c: 00000013 nop + 80002c50: 000f0313 mv t1,t5 + 80002c54: f0000e93 li t4,-256 + 80002c58: 0dd31e63 bne t1,t4,80002d34 + 80002c5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c60: 00200293 li t0,2 + 80002c64: fc521ce3 bne tp,t0,80002c3c + +0000000080002c68 : + 80002c68: 00f00193 li gp,15 + 80002c6c: 00000213 li tp,0 + 80002c70: 00000097 auipc ra,0x0 + 80002c74: 39208093 addi ra,ra,914 # 80003002 + 80002c78: 00209f03 lh t5,2(ra) + 80002c7c: 00001eb7 lui t4,0x1 + 80002c80: ff0e8e9b addiw t4,t4,-16 + 80002c84: 0bdf1863 bne t5,t4,80002d34 + 80002c88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c8c: 00200293 li t0,2 + 80002c90: fe5210e3 bne tp,t0,80002c70 + +0000000080002c94 : + 80002c94: 01000193 li gp,16 + 80002c98: 00000213 li tp,0 + 80002c9c: 00000097 auipc ra,0x0 + 80002ca0: 36808093 addi ra,ra,872 # 80003004 + 80002ca4: 00000013 nop + 80002ca8: 00209f03 lh t5,2(ra) + 80002cac: fffffeb7 lui t4,0xfffff + 80002cb0: 00fe8e9b addiw t4,t4,15 + 80002cb4: 09df1063 bne t5,t4,80002d34 + 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cbc: 00200293 li t0,2 + 80002cc0: fc521ee3 bne tp,t0,80002c9c + +0000000080002cc4 : + 80002cc4: 01100193 li gp,17 + 80002cc8: 00000213 li tp,0 + 80002ccc: 00000097 auipc ra,0x0 + 80002cd0: 33408093 addi ra,ra,820 # 80003000 + 80002cd4: 00000013 nop + 80002cd8: 00000013 nop + 80002cdc: 00209f03 lh t5,2(ra) + 80002ce0: f0000e93 li t4,-256 + 80002ce4: 05df1863 bne t5,t4,80002d34 + 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cec: 00200293 li t0,2 + 80002cf0: fc521ee3 bne tp,t0,80002ccc + +0000000080002cf4 : + 80002cf4: 00000297 auipc t0,0x0 + 80002cf8: 30c28293 addi t0,t0,780 # 80003000 + 80002cfc: 00029103 lh sp,0(t0) + 80002d00: 00200113 li sp,2 + 80002d04: 00200e93 li t4,2 + 80002d08: 01200193 li gp,18 + 80002d0c: 03d11463 bne sp,t4,80002d34 + +0000000080002d10 : + 80002d10: 00000297 auipc t0,0x0 + 80002d14: 2f028293 addi t0,t0,752 # 80003000 + 80002d18: 00029103 lh sp,0(t0) + 80002d1c: 00000013 nop + 80002d20: 00200113 li sp,2 + 80002d24: 00200e93 li t4,2 + 80002d28: 01300193 li gp,19 + 80002d2c: 01d11463 bne sp,t4,80002d34 + 80002d30: 00301a63 bne zero,gp,80002d44 + +0000000080002d34 : + 80002d34: 00119513 slli a0,gp,0x1 + 80002d38: 00050063 beqz a0,80002d38 + 80002d3c: 00156513 ori a0,a0,1 + 80002d40: 00000073 ecall + +0000000080002d44 : + 80002d44: 00100513 li a0,1 + 80002d48: 00000073 ecall + 80002d4c: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 00ff 0xff + +0000000080003002 : + 80003002: ff00 sd s0,56(a4) + +0000000080003004 : + 80003004: 0ff0 addi a2,sp,988 + +0000000080003006 : + 80003006: 0xf00f diff --git a/test/riscv/tests/rv64ui-v-lh.elf b/test/riscv/tests/rv64ui-v-lh.elf new file mode 100644 index 00000000..7d91368b Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lh.elf differ diff --git a/test/riscv/tests/rv64ui-v-lhu.dump b/test/riscv/tests/rv64ui-v-lhu.dump new file mode 100644 index 00000000..45585fe4 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lhu.dump @@ -0,0 +1,1048 @@ + +rv64ui-v-lhu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 91068693 addi a3,a3,-1776 # 80002d68 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 94460613 addi a2,a2,-1724 # 80002df8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 90c60613 addi a2,a2,-1780 # 80002e10 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 85c68693 addi a3,a3,-1956 # 80002db0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 87868693 addi a3,a3,-1928 # 80002ee8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7f860613 addi a2,a2,2040 # 80002ec0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 72c68693 addi a3,a3,1836 # 80002f18 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 64c68693 addi a3,a3,1612 # 80002e88 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5dc68693 addi a3,a3,1500 # 80002e50 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03b00793 li a5,59 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 007667b7 lui a5,0x766 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: efb78793 addi a5,a5,-261 # 765efb <_start-0x7f89a105> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 0000df03 lhu t5,0(ra) + 80002ad4: 0ff00e93 li t4,255 + 80002ad8: 00200193 li gp,2 + 80002adc: 27df1663 bne t5,t4,80002d48 + +0000000080002ae0 : + 80002ae0: 00000097 auipc ra,0x0 + 80002ae4: 52008093 addi ra,ra,1312 # 80003000 + 80002ae8: 0020df03 lhu t5,2(ra) + 80002aec: 00010eb7 lui t4,0x10 + 80002af0: f00e8e9b addiw t4,t4,-256 + 80002af4: 00300193 li gp,3 + 80002af8: 25df1863 bne t5,t4,80002d48 + +0000000080002afc : + 80002afc: 00000097 auipc ra,0x0 + 80002b00: 50408093 addi ra,ra,1284 # 80003000 + 80002b04: 0040df03 lhu t5,4(ra) + 80002b08: 00001eb7 lui t4,0x1 + 80002b0c: ff0e8e9b addiw t4,t4,-16 + 80002b10: 00400193 li gp,4 + 80002b14: 23df1a63 bne t5,t4,80002d48 + +0000000080002b18 : + 80002b18: 00000097 auipc ra,0x0 + 80002b1c: 4e808093 addi ra,ra,1256 # 80003000 + 80002b20: 0060df03 lhu t5,6(ra) + 80002b24: 0000feb7 lui t4,0xf + 80002b28: 00fe8e9b addiw t4,t4,15 + 80002b2c: 00500193 li gp,5 + 80002b30: 21df1c63 bne t5,t4,80002d48 + +0000000080002b34 : + 80002b34: 00000097 auipc ra,0x0 + 80002b38: 4d208093 addi ra,ra,1234 # 80003006 + 80002b3c: ffa0df03 lhu t5,-6(ra) + 80002b40: 0ff00e93 li t4,255 + 80002b44: 00600193 li gp,6 + 80002b48: 21df1063 bne t5,t4,80002d48 + +0000000080002b4c : + 80002b4c: 00000097 auipc ra,0x0 + 80002b50: 4ba08093 addi ra,ra,1210 # 80003006 + 80002b54: ffc0df03 lhu t5,-4(ra) + 80002b58: 00010eb7 lui t4,0x10 + 80002b5c: f00e8e9b addiw t4,t4,-256 + 80002b60: 00700193 li gp,7 + 80002b64: 1fdf1263 bne t5,t4,80002d48 + +0000000080002b68 : + 80002b68: 00000097 auipc ra,0x0 + 80002b6c: 49e08093 addi ra,ra,1182 # 80003006 + 80002b70: ffe0df03 lhu t5,-2(ra) + 80002b74: 00001eb7 lui t4,0x1 + 80002b78: ff0e8e9b addiw t4,t4,-16 + 80002b7c: 00800193 li gp,8 + 80002b80: 1ddf1463 bne t5,t4,80002d48 + +0000000080002b84 : + 80002b84: 00000097 auipc ra,0x0 + 80002b88: 48208093 addi ra,ra,1154 # 80003006 + 80002b8c: 0000df03 lhu t5,0(ra) + 80002b90: 0000feb7 lui t4,0xf + 80002b94: 00fe8e9b addiw t4,t4,15 + 80002b98: 00900193 li gp,9 + 80002b9c: 1bdf1663 bne t5,t4,80002d48 + +0000000080002ba0 : + 80002ba0: 00000097 auipc ra,0x0 + 80002ba4: 46008093 addi ra,ra,1120 # 80003000 + 80002ba8: fe008093 addi ra,ra,-32 + 80002bac: 0200d283 lhu t0,32(ra) + 80002bb0: 0ff00e93 li t4,255 + 80002bb4: 00a00193 li gp,10 + 80002bb8: 19d29863 bne t0,t4,80002d48 + +0000000080002bbc : + 80002bbc: 00000097 auipc ra,0x0 + 80002bc0: 44408093 addi ra,ra,1092 # 80003000 + 80002bc4: ffb08093 addi ra,ra,-5 + 80002bc8: 0070d283 lhu t0,7(ra) + 80002bcc: 00010eb7 lui t4,0x10 + 80002bd0: f00e8e9b addiw t4,t4,-256 + 80002bd4: 00b00193 li gp,11 + 80002bd8: 17d29863 bne t0,t4,80002d48 + +0000000080002bdc : + 80002bdc: 00c00193 li gp,12 + 80002be0: 00000213 li tp,0 + 80002be4: 00000097 auipc ra,0x0 + 80002be8: 41e08093 addi ra,ra,1054 # 80003002 + 80002bec: 0020df03 lhu t5,2(ra) + 80002bf0: 000f0313 mv t1,t5 + 80002bf4: 00001eb7 lui t4,0x1 + 80002bf8: ff0e8e9b addiw t4,t4,-16 + 80002bfc: 15d31663 bne t1,t4,80002d48 + 80002c00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c04: 00200293 li t0,2 + 80002c08: fc521ee3 bne tp,t0,80002be4 + +0000000080002c0c : + 80002c0c: 00d00193 li gp,13 + 80002c10: 00000213 li tp,0 + 80002c14: 00000097 auipc ra,0x0 + 80002c18: 3f008093 addi ra,ra,1008 # 80003004 + 80002c1c: 0020df03 lhu t5,2(ra) + 80002c20: 00000013 nop + 80002c24: 000f0313 mv t1,t5 + 80002c28: 0000feb7 lui t4,0xf + 80002c2c: 00fe8e9b addiw t4,t4,15 + 80002c30: 11d31c63 bne t1,t4,80002d48 + 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c38: 00200293 li t0,2 + 80002c3c: fc521ce3 bne tp,t0,80002c14 + +0000000080002c40 : + 80002c40: 00e00193 li gp,14 + 80002c44: 00000213 li tp,0 + 80002c48: 00000097 auipc ra,0x0 + 80002c4c: 3b808093 addi ra,ra,952 # 80003000 + 80002c50: 0020df03 lhu t5,2(ra) + 80002c54: 00000013 nop + 80002c58: 00000013 nop + 80002c5c: 000f0313 mv t1,t5 + 80002c60: 00010eb7 lui t4,0x10 + 80002c64: f00e8e9b addiw t4,t4,-256 + 80002c68: 0fd31063 bne t1,t4,80002d48 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fc521ae3 bne tp,t0,80002c48 + +0000000080002c78 : + 80002c78: 00f00193 li gp,15 + 80002c7c: 00000213 li tp,0 + 80002c80: 00000097 auipc ra,0x0 + 80002c84: 38208093 addi ra,ra,898 # 80003002 + 80002c88: 0020df03 lhu t5,2(ra) + 80002c8c: 00001eb7 lui t4,0x1 + 80002c90: ff0e8e9b addiw t4,t4,-16 + 80002c94: 0bdf1a63 bne t5,t4,80002d48 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5210e3 bne tp,t0,80002c80 + +0000000080002ca4 : + 80002ca4: 01000193 li gp,16 + 80002ca8: 00000213 li tp,0 + 80002cac: 00000097 auipc ra,0x0 + 80002cb0: 35808093 addi ra,ra,856 # 80003004 + 80002cb4: 00000013 nop + 80002cb8: 0020df03 lhu t5,2(ra) + 80002cbc: 0000feb7 lui t4,0xf + 80002cc0: 00fe8e9b addiw t4,t4,15 + 80002cc4: 09df1263 bne t5,t4,80002d48 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fc521ee3 bne tp,t0,80002cac + +0000000080002cd4 : + 80002cd4: 01100193 li gp,17 + 80002cd8: 00000213 li tp,0 + 80002cdc: 00000097 auipc ra,0x0 + 80002ce0: 32408093 addi ra,ra,804 # 80003000 + 80002ce4: 00000013 nop + 80002ce8: 00000013 nop + 80002cec: 0020df03 lhu t5,2(ra) + 80002cf0: 00010eb7 lui t4,0x10 + 80002cf4: f00e8e9b addiw t4,t4,-256 + 80002cf8: 05df1863 bne t5,t4,80002d48 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fc521ce3 bne tp,t0,80002cdc + +0000000080002d08 : + 80002d08: 00000297 auipc t0,0x0 + 80002d0c: 2f828293 addi t0,t0,760 # 80003000 + 80002d10: 0002d103 lhu sp,0(t0) + 80002d14: 00200113 li sp,2 + 80002d18: 00200e93 li t4,2 + 80002d1c: 01200193 li gp,18 + 80002d20: 03d11463 bne sp,t4,80002d48 + +0000000080002d24 : + 80002d24: 00000297 auipc t0,0x0 + 80002d28: 2dc28293 addi t0,t0,732 # 80003000 + 80002d2c: 0002d103 lhu sp,0(t0) + 80002d30: 00000013 nop + 80002d34: 00200113 li sp,2 + 80002d38: 00200e93 li t4,2 + 80002d3c: 01300193 li gp,19 + 80002d40: 01d11463 bne sp,t4,80002d48 + 80002d44: 00301a63 bne zero,gp,80002d58 + +0000000080002d48 : + 80002d48: 00119513 slli a0,gp,0x1 + 80002d4c: 00050063 beqz a0,80002d4c + 80002d50: 00156513 ori a0,a0,1 + 80002d54: 00000073 ecall + +0000000080002d58 : + 80002d58: 00100513 li a0,1 + 80002d5c: 00000073 ecall + 80002d60: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 00ff 0xff + +0000000080003002 : + 80003002: ff00 sd s0,56(a4) + +0000000080003004 : + 80003004: 0ff0 addi a2,sp,988 + +0000000080003006 : + 80003006: 0xf00f diff --git a/test/riscv/tests/rv64ui-v-lhu.elf b/test/riscv/tests/rv64ui-v-lhu.elf new file mode 100644 index 00000000..af1ebeec Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lhu.elf differ diff --git a/test/riscv/tests/rv64ui-v-lui.dump b/test/riscv/tests/rv64ui-v-lui.dump new file mode 100644 index 00000000..6de22b61 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lui.dump @@ -0,0 +1,872 @@ + +rv64ui-v-lui: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 63c68693 addi a3,a3,1596 # 80002b90 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 65868693 addi a3,a3,1624 # 80002cc8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 42c68693 addi a3,a3,1068 # 80002c68 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 3bc68693 addi a3,a3,956 # 80002c30 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00e00793 li a5,14 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0caa87b7 lui a5,0xcaa8 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 51978793 addi a5,a5,1305 # caa8519 <_start-0x73557ae7> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000000b7 lui ra,0x0 + 80002acc: 00000e93 li t4,0 + 80002ad0: 00200193 li gp,2 + 80002ad4: 05d09a63 bne ra,t4,80002b28 + +0000000080002ad8 : + 80002ad8: fffff0b7 lui ra,0xfffff + 80002adc: 4010d093 srai ra,ra,0x1 + 80002ae0: 80000e93 li t4,-2048 + 80002ae4: 00300193 li gp,3 + 80002ae8: 05d09063 bne ra,t4,80002b28 + +0000000080002aec : + 80002aec: 7ffff0b7 lui ra,0x7ffff + 80002af0: 4140d093 srai ra,ra,0x14 + 80002af4: 7ff00e93 li t4,2047 + 80002af8: 00400193 li gp,4 + 80002afc: 03d09663 bne ra,t4,80002b28 + +0000000080002b00 : + 80002b00: 800000b7 lui ra,0x80000 + 80002b04: 4140d093 srai ra,ra,0x14 + 80002b08: 80000e93 li t4,-2048 + 80002b0c: 00500193 li gp,5 + 80002b10: 01d09c63 bne ra,t4,80002b28 + +0000000080002b14 : + 80002b14: 80000037 lui zero,0x80000 + 80002b18: 00000e93 li t4,0 + 80002b1c: 00600193 li gp,6 + 80002b20: 01d01463 bne zero,t4,80002b28 + 80002b24: 00301a63 bne zero,gp,80002b38 + +0000000080002b28 : + 80002b28: 00119513 slli a0,gp,0x1 + 80002b2c: 00050063 beqz a0,80002b2c + 80002b30: 00156513 ori a0,a0,1 + 80002b34: 00000073 ecall + +0000000080002b38 : + 80002b38: 00100513 li a0,1 + 80002b3c: 00000073 ecall + 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-lui.elf b/test/riscv/tests/rv64ui-v-lui.elf new file mode 100644 index 00000000..3cab9504 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lui.elf differ diff --git a/test/riscv/tests/rv64ui-v-lw.dump b/test/riscv/tests/rv64ui-v-lw.dump new file mode 100644 index 00000000..4208d276 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lw.dump @@ -0,0 +1,1054 @@ + +rv64ui-v-lw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 91868693 addi a3,a3,-1768 # 80002d70 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 94c60613 addi a2,a2,-1716 # 80002e00 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 91460613 addi a2,a2,-1772 # 80002e18 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 86468693 addi a3,a3,-1948 # 80002db8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 88068693 addi a3,a3,-1920 # 80002ef0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 80060613 addi a2,a2,-2048 # 80002ec8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 73468693 addi a3,a3,1844 # 80002f20 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 65468693 addi a3,a3,1620 # 80002e90 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5e468693 addi a3,a3,1508 # 80002e58 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00800793 li a5,8 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 03dd47b7 lui a5,0x3dd4 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: ebd78793 addi a5,a5,-323 # 3dd3ebd <_start-0x7c22c143> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 0000af03 lw t5,0(ra) + 80002ad4: 00ff0eb7 lui t4,0xff0 + 80002ad8: 0ffe8e9b addiw t4,t4,255 + 80002adc: 00200193 li gp,2 + 80002ae0: 27df1a63 bne t5,t4,80002d54 + +0000000080002ae4 : + 80002ae4: 00000097 auipc ra,0x0 + 80002ae8: 51c08093 addi ra,ra,1308 # 80003000 + 80002aec: 0040af03 lw t5,4(ra) + 80002af0: ff010eb7 lui t4,0xff010 + 80002af4: f00e8e9b addiw t4,t4,-256 + 80002af8: 00300193 li gp,3 + 80002afc: 25df1c63 bne t5,t4,80002d54 + +0000000080002b00 : + 80002b00: 00000097 auipc ra,0x0 + 80002b04: 50008093 addi ra,ra,1280 # 80003000 + 80002b08: 0080af03 lw t5,8(ra) + 80002b0c: 0ff01eb7 lui t4,0xff01 + 80002b10: ff0e8e9b addiw t4,t4,-16 + 80002b14: 00400193 li gp,4 + 80002b18: 23df1e63 bne t5,t4,80002d54 + +0000000080002b1c : + 80002b1c: 00000097 auipc ra,0x0 + 80002b20: 4e408093 addi ra,ra,1252 # 80003000 + 80002b24: 00c0af03 lw t5,12(ra) + 80002b28: f00ffeb7 lui t4,0xf00ff + 80002b2c: 00fe8e9b addiw t4,t4,15 + 80002b30: 00500193 li gp,5 + 80002b34: 23df1063 bne t5,t4,80002d54 + +0000000080002b38 : + 80002b38: 00000097 auipc ra,0x0 + 80002b3c: 4d408093 addi ra,ra,1236 # 8000300c + 80002b40: ff40af03 lw t5,-12(ra) + 80002b44: 00ff0eb7 lui t4,0xff0 + 80002b48: 0ffe8e9b addiw t4,t4,255 + 80002b4c: 00600193 li gp,6 + 80002b50: 21df1263 bne t5,t4,80002d54 + +0000000080002b54 : + 80002b54: 00000097 auipc ra,0x0 + 80002b58: 4b808093 addi ra,ra,1208 # 8000300c + 80002b5c: ff80af03 lw t5,-8(ra) + 80002b60: ff010eb7 lui t4,0xff010 + 80002b64: f00e8e9b addiw t4,t4,-256 + 80002b68: 00700193 li gp,7 + 80002b6c: 1fdf1463 bne t5,t4,80002d54 + +0000000080002b70 : + 80002b70: 00000097 auipc ra,0x0 + 80002b74: 49c08093 addi ra,ra,1180 # 8000300c + 80002b78: ffc0af03 lw t5,-4(ra) + 80002b7c: 0ff01eb7 lui t4,0xff01 + 80002b80: ff0e8e9b addiw t4,t4,-16 + 80002b84: 00800193 li gp,8 + 80002b88: 1ddf1663 bne t5,t4,80002d54 + +0000000080002b8c : + 80002b8c: 00000097 auipc ra,0x0 + 80002b90: 48008093 addi ra,ra,1152 # 8000300c + 80002b94: 0000af03 lw t5,0(ra) + 80002b98: f00ffeb7 lui t4,0xf00ff + 80002b9c: 00fe8e9b addiw t4,t4,15 + 80002ba0: 00900193 li gp,9 + 80002ba4: 1bdf1863 bne t5,t4,80002d54 + +0000000080002ba8 : + 80002ba8: 00000097 auipc ra,0x0 + 80002bac: 45808093 addi ra,ra,1112 # 80003000 + 80002bb0: fe008093 addi ra,ra,-32 + 80002bb4: 0200a283 lw t0,32(ra) + 80002bb8: 00ff0eb7 lui t4,0xff0 + 80002bbc: 0ffe8e9b addiw t4,t4,255 + 80002bc0: 00a00193 li gp,10 + 80002bc4: 19d29863 bne t0,t4,80002d54 + +0000000080002bc8 : + 80002bc8: 00000097 auipc ra,0x0 + 80002bcc: 43808093 addi ra,ra,1080 # 80003000 + 80002bd0: ffd08093 addi ra,ra,-3 + 80002bd4: 0070a283 lw t0,7(ra) + 80002bd8: ff010eb7 lui t4,0xff010 + 80002bdc: f00e8e9b addiw t4,t4,-256 + 80002be0: 00b00193 li gp,11 + 80002be4: 17d29863 bne t0,t4,80002d54 + +0000000080002be8 : + 80002be8: 00c00193 li gp,12 + 80002bec: 00000213 li tp,0 + 80002bf0: 00000097 auipc ra,0x0 + 80002bf4: 41408093 addi ra,ra,1044 # 80003004 + 80002bf8: 0040af03 lw t5,4(ra) + 80002bfc: 000f0313 mv t1,t5 + 80002c00: 0ff01eb7 lui t4,0xff01 + 80002c04: ff0e8e9b addiw t4,t4,-16 + 80002c08: 15d31663 bne t1,t4,80002d54 + 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c10: 00200293 li t0,2 + 80002c14: fc521ee3 bne tp,t0,80002bf0 + +0000000080002c18 : + 80002c18: 00d00193 li gp,13 + 80002c1c: 00000213 li tp,0 + 80002c20: 00000097 auipc ra,0x0 + 80002c24: 3e808093 addi ra,ra,1000 # 80003008 + 80002c28: 0040af03 lw t5,4(ra) + 80002c2c: 00000013 nop + 80002c30: 000f0313 mv t1,t5 + 80002c34: f00ffeb7 lui t4,0xf00ff + 80002c38: 00fe8e9b addiw t4,t4,15 + 80002c3c: 11d31c63 bne t1,t4,80002d54 + 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c44: 00200293 li t0,2 + 80002c48: fc521ce3 bne tp,t0,80002c20 + +0000000080002c4c : + 80002c4c: 00e00193 li gp,14 + 80002c50: 00000213 li tp,0 + 80002c54: 00000097 auipc ra,0x0 + 80002c58: 3ac08093 addi ra,ra,940 # 80003000 + 80002c5c: 0040af03 lw t5,4(ra) + 80002c60: 00000013 nop + 80002c64: 00000013 nop + 80002c68: 000f0313 mv t1,t5 + 80002c6c: ff010eb7 lui t4,0xff010 + 80002c70: f00e8e9b addiw t4,t4,-256 + 80002c74: 0fd31063 bne t1,t4,80002d54 + 80002c78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c7c: 00200293 li t0,2 + 80002c80: fc521ae3 bne tp,t0,80002c54 + +0000000080002c84 : + 80002c84: 00f00193 li gp,15 + 80002c88: 00000213 li tp,0 + 80002c8c: 00000097 auipc ra,0x0 + 80002c90: 37808093 addi ra,ra,888 # 80003004 + 80002c94: 0040af03 lw t5,4(ra) + 80002c98: 0ff01eb7 lui t4,0xff01 + 80002c9c: ff0e8e9b addiw t4,t4,-16 + 80002ca0: 0bdf1a63 bne t5,t4,80002d54 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5210e3 bne tp,t0,80002c8c + +0000000080002cb0 : + 80002cb0: 01000193 li gp,16 + 80002cb4: 00000213 li tp,0 + 80002cb8: 00000097 auipc ra,0x0 + 80002cbc: 35008093 addi ra,ra,848 # 80003008 + 80002cc0: 00000013 nop + 80002cc4: 0040af03 lw t5,4(ra) + 80002cc8: f00ffeb7 lui t4,0xf00ff + 80002ccc: 00fe8e9b addiw t4,t4,15 + 80002cd0: 09df1263 bne t5,t4,80002d54 + 80002cd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd8: 00200293 li t0,2 + 80002cdc: fc521ee3 bne tp,t0,80002cb8 + +0000000080002ce0 : + 80002ce0: 01100193 li gp,17 + 80002ce4: 00000213 li tp,0 + 80002ce8: 00000097 auipc ra,0x0 + 80002cec: 31808093 addi ra,ra,792 # 80003000 + 80002cf0: 00000013 nop + 80002cf4: 00000013 nop + 80002cf8: 0040af03 lw t5,4(ra) + 80002cfc: ff010eb7 lui t4,0xff010 + 80002d00: f00e8e9b addiw t4,t4,-256 + 80002d04: 05df1863 bne t5,t4,80002d54 + 80002d08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d0c: 00200293 li t0,2 + 80002d10: fc521ce3 bne tp,t0,80002ce8 + +0000000080002d14 : + 80002d14: 00000297 auipc t0,0x0 + 80002d18: 2ec28293 addi t0,t0,748 # 80003000 + 80002d1c: 0002a103 lw sp,0(t0) + 80002d20: 00200113 li sp,2 + 80002d24: 00200e93 li t4,2 + 80002d28: 01200193 li gp,18 + 80002d2c: 03d11463 bne sp,t4,80002d54 + +0000000080002d30 : + 80002d30: 00000297 auipc t0,0x0 + 80002d34: 2d028293 addi t0,t0,720 # 80003000 + 80002d38: 0002a103 lw sp,0(t0) + 80002d3c: 00000013 nop + 80002d40: 00200113 li sp,2 + 80002d44: 00200e93 li t4,2 + 80002d48: 01300193 li gp,19 + 80002d4c: 01d11463 bne sp,t4,80002d54 + 80002d50: 00301a63 bne zero,gp,80002d64 + +0000000080002d54 : + 80002d54: 00119513 slli a0,gp,0x1 + 80002d58: 00050063 beqz a0,80002d58 + 80002d5c: 00156513 ori a0,a0,1 + 80002d60: 00000073 ecall + +0000000080002d64 : + 80002d64: 00100513 li a0,1 + 80002d68: 00000073 ecall + 80002d6c: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 00ff 0xff + 80003002: 00ff 0xff + +0000000080003004 : + 80003004: ff00 sd s0,56(a4) + 80003006: ff00 sd s0,56(a4) + +0000000080003008 : + 80003008: 0ff0 addi a2,sp,988 + 8000300a: 0ff0 addi a2,sp,988 + +000000008000300c : + 8000300c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-lw.elf b/test/riscv/tests/rv64ui-v-lw.elf new file mode 100644 index 00000000..d73403be Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lw.elf differ diff --git a/test/riscv/tests/rv64ui-v-lwu.dump b/test/riscv/tests/rv64ui-v-lwu.dump new file mode 100644 index 00000000..aa0fb7d0 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-lwu.dump @@ -0,0 +1,1072 @@ + +rv64ui-v-lwu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 96068693 addi a3,a3,-1696 # 80002db8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 99460613 addi a2,a2,-1644 # 80002e48 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 95c60613 addi a2,a2,-1700 # 80002e60 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 8ac68693 addi a3,a3,-1876 # 80002e00 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8c868693 addi a3,a3,-1848 # 80002f38 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 84860613 addi a2,a2,-1976 # 80002f10 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 77c68693 addi a3,a3,1916 # 80002f68 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 69c68693 addi a3,a3,1692 # 80002ed8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 62c68693 addi a3,a3,1580 # 80002ea0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00200793 li a5,2 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 046f07b7 lui a5,0x46f0 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b8378793 addi a5,a5,-1149 # 46efb83 <_start-0x7b91047d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000097 auipc ra,0x0 + 80002acc: 53808093 addi ra,ra,1336 # 80003000 + 80002ad0: 0000ef03 lwu t5,0(ra) + 80002ad4: 00ff0eb7 lui t4,0xff0 + 80002ad8: 0ffe8e9b addiw t4,t4,255 + 80002adc: 00200193 li gp,2 + 80002ae0: 2bdf1e63 bne t5,t4,80002d9c + +0000000080002ae4 : + 80002ae4: 00000097 auipc ra,0x0 + 80002ae8: 51c08093 addi ra,ra,1308 # 80003000 + 80002aec: 0040ef03 lwu t5,4(ra) + 80002af0: 00010eb7 lui t4,0x10 + 80002af4: f01e8e9b addiw t4,t4,-255 + 80002af8: 010e9e93 slli t4,t4,0x10 + 80002afc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002b00: 00300193 li gp,3 + 80002b04: 29df1c63 bne t5,t4,80002d9c + +0000000080002b08 : + 80002b08: 00000097 auipc ra,0x0 + 80002b0c: 4f808093 addi ra,ra,1272 # 80003000 + 80002b10: 0080ef03 lwu t5,8(ra) + 80002b14: 0ff01eb7 lui t4,0xff01 + 80002b18: ff0e8e9b addiw t4,t4,-16 + 80002b1c: 00400193 li gp,4 + 80002b20: 27df1e63 bne t5,t4,80002d9c + +0000000080002b24 : + 80002b24: 00000097 auipc ra,0x0 + 80002b28: 4dc08093 addi ra,ra,1244 # 80003000 + 80002b2c: 00c0ef03 lwu t5,12(ra) + 80002b30: 000f0eb7 lui t4,0xf0 + 80002b34: 0ffe8e9b addiw t4,t4,255 + 80002b38: 00ce9e93 slli t4,t4,0xc + 80002b3c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002b40: 00500193 li gp,5 + 80002b44: 25df1c63 bne t5,t4,80002d9c + +0000000080002b48 : + 80002b48: 00000097 auipc ra,0x0 + 80002b4c: 4c408093 addi ra,ra,1220 # 8000300c + 80002b50: ff40ef03 lwu t5,-12(ra) + 80002b54: 00ff0eb7 lui t4,0xff0 + 80002b58: 0ffe8e9b addiw t4,t4,255 + 80002b5c: 00600193 li gp,6 + 80002b60: 23df1e63 bne t5,t4,80002d9c + +0000000080002b64 : + 80002b64: 00000097 auipc ra,0x0 + 80002b68: 4a808093 addi ra,ra,1192 # 8000300c + 80002b6c: ff80ef03 lwu t5,-8(ra) + 80002b70: 00010eb7 lui t4,0x10 + 80002b74: f01e8e9b addiw t4,t4,-255 + 80002b78: 010e9e93 slli t4,t4,0x10 + 80002b7c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002b80: 00700193 li gp,7 + 80002b84: 21df1c63 bne t5,t4,80002d9c + +0000000080002b88 : + 80002b88: 00000097 auipc ra,0x0 + 80002b8c: 48408093 addi ra,ra,1156 # 8000300c + 80002b90: ffc0ef03 lwu t5,-4(ra) + 80002b94: 0ff01eb7 lui t4,0xff01 + 80002b98: ff0e8e9b addiw t4,t4,-16 + 80002b9c: 00800193 li gp,8 + 80002ba0: 1fdf1e63 bne t5,t4,80002d9c + +0000000080002ba4 : + 80002ba4: 00000097 auipc ra,0x0 + 80002ba8: 46808093 addi ra,ra,1128 # 8000300c + 80002bac: 0000ef03 lwu t5,0(ra) + 80002bb0: 000f0eb7 lui t4,0xf0 + 80002bb4: 0ffe8e9b addiw t4,t4,255 + 80002bb8: 00ce9e93 slli t4,t4,0xc + 80002bbc: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002bc0: 00900193 li gp,9 + 80002bc4: 1ddf1c63 bne t5,t4,80002d9c + +0000000080002bc8 : + 80002bc8: 00000097 auipc ra,0x0 + 80002bcc: 43808093 addi ra,ra,1080 # 80003000 + 80002bd0: fe008093 addi ra,ra,-32 + 80002bd4: 0200e283 lwu t0,32(ra) + 80002bd8: 00ff0eb7 lui t4,0xff0 + 80002bdc: 0ffe8e9b addiw t4,t4,255 + 80002be0: 00a00193 li gp,10 + 80002be4: 1bd29c63 bne t0,t4,80002d9c + +0000000080002be8 : + 80002be8: 00000097 auipc ra,0x0 + 80002bec: 41808093 addi ra,ra,1048 # 80003000 + 80002bf0: ffd08093 addi ra,ra,-3 + 80002bf4: 0070e283 lwu t0,7(ra) + 80002bf8: 00010eb7 lui t4,0x10 + 80002bfc: f01e8e9b addiw t4,t4,-255 + 80002c00: 010e9e93 slli t4,t4,0x10 + 80002c04: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002c08: 00b00193 li gp,11 + 80002c0c: 19d29863 bne t0,t4,80002d9c + +0000000080002c10 : + 80002c10: 00c00193 li gp,12 + 80002c14: 00000213 li tp,0 + 80002c18: 00000097 auipc ra,0x0 + 80002c1c: 3ec08093 addi ra,ra,1004 # 80003004 + 80002c20: 0040ef03 lwu t5,4(ra) + 80002c24: 000f0313 mv t1,t5 + 80002c28: 0ff01eb7 lui t4,0xff01 + 80002c2c: ff0e8e9b addiw t4,t4,-16 + 80002c30: 17d31663 bne t1,t4,80002d9c + 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c38: 00200293 li t0,2 + 80002c3c: fc521ee3 bne tp,t0,80002c18 + +0000000080002c40 : + 80002c40: 00d00193 li gp,13 + 80002c44: 00000213 li tp,0 + 80002c48: 00000097 auipc ra,0x0 + 80002c4c: 3c008093 addi ra,ra,960 # 80003008 + 80002c50: 0040ef03 lwu t5,4(ra) + 80002c54: 00000013 nop + 80002c58: 000f0313 mv t1,t5 + 80002c5c: 000f0eb7 lui t4,0xf0 + 80002c60: 0ffe8e9b addiw t4,t4,255 + 80002c64: 00ce9e93 slli t4,t4,0xc + 80002c68: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002c6c: 13d31863 bne t1,t4,80002d9c + 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c74: 00200293 li t0,2 + 80002c78: fc5218e3 bne tp,t0,80002c48 + +0000000080002c7c : + 80002c7c: 00e00193 li gp,14 + 80002c80: 00000213 li tp,0 + 80002c84: 00000097 auipc ra,0x0 + 80002c88: 37c08093 addi ra,ra,892 # 80003000 + 80002c8c: 0040ef03 lwu t5,4(ra) + 80002c90: 00000013 nop + 80002c94: 00000013 nop + 80002c98: 000f0313 mv t1,t5 + 80002c9c: 00010eb7 lui t4,0x10 + 80002ca0: f01e8e9b addiw t4,t4,-255 + 80002ca4: 010e9e93 slli t4,t4,0x10 + 80002ca8: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002cac: 0fd31863 bne t1,t4,80002d9c + 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cb4: 00200293 li t0,2 + 80002cb8: fc5216e3 bne tp,t0,80002c84 + +0000000080002cbc : + 80002cbc: 00f00193 li gp,15 + 80002cc0: 00000213 li tp,0 + 80002cc4: 00000097 auipc ra,0x0 + 80002cc8: 34008093 addi ra,ra,832 # 80003004 + 80002ccc: 0040ef03 lwu t5,4(ra) + 80002cd0: 0ff01eb7 lui t4,0xff01 + 80002cd4: ff0e8e9b addiw t4,t4,-16 + 80002cd8: 0ddf1263 bne t5,t4,80002d9c + 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce0: 00200293 li t0,2 + 80002ce4: fe5210e3 bne tp,t0,80002cc4 + +0000000080002ce8 : + 80002ce8: 01000193 li gp,16 + 80002cec: 00000213 li tp,0 + 80002cf0: 00000097 auipc ra,0x0 + 80002cf4: 31808093 addi ra,ra,792 # 80003008 + 80002cf8: 00000013 nop + 80002cfc: 0040ef03 lwu t5,4(ra) + 80002d00: 000f0eb7 lui t4,0xf0 + 80002d04: 0ffe8e9b addiw t4,t4,255 + 80002d08: 00ce9e93 slli t4,t4,0xc + 80002d0c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002d10: 09df1663 bne t5,t4,80002d9c + 80002d14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d18: 00200293 li t0,2 + 80002d1c: fc521ae3 bne tp,t0,80002cf0 + +0000000080002d20 : + 80002d20: 01100193 li gp,17 + 80002d24: 00000213 li tp,0 + 80002d28: 00000097 auipc ra,0x0 + 80002d2c: 2d808093 addi ra,ra,728 # 80003000 + 80002d30: 00000013 nop + 80002d34: 00000013 nop + 80002d38: 0040ef03 lwu t5,4(ra) + 80002d3c: 00010eb7 lui t4,0x10 + 80002d40: f01e8e9b addiw t4,t4,-255 + 80002d44: 010e9e93 slli t4,t4,0x10 + 80002d48: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002d4c: 05df1863 bne t5,t4,80002d9c + 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d54: 00200293 li t0,2 + 80002d58: fc5218e3 bne tp,t0,80002d28 + +0000000080002d5c : + 80002d5c: 00000297 auipc t0,0x0 + 80002d60: 2a428293 addi t0,t0,676 # 80003000 + 80002d64: 0002e103 lwu sp,0(t0) + 80002d68: 00200113 li sp,2 + 80002d6c: 00200e93 li t4,2 + 80002d70: 01200193 li gp,18 + 80002d74: 03d11463 bne sp,t4,80002d9c + +0000000080002d78 : + 80002d78: 00000297 auipc t0,0x0 + 80002d7c: 28828293 addi t0,t0,648 # 80003000 + 80002d80: 0002e103 lwu sp,0(t0) + 80002d84: 00000013 nop + 80002d88: 00200113 li sp,2 + 80002d8c: 00200e93 li t4,2 + 80002d90: 01300193 li gp,19 + 80002d94: 01d11463 bne sp,t4,80002d9c + 80002d98: 00301a63 bne zero,gp,80002dac + +0000000080002d9c : + 80002d9c: 00119513 slli a0,gp,0x1 + 80002da0: 00050063 beqz a0,80002da0 + 80002da4: 00156513 ori a0,a0,1 + 80002da8: 00000073 ecall + +0000000080002dac : + 80002dac: 00100513 li a0,1 + 80002db0: 00000073 ecall + 80002db4: c0001073 unimp + +Disassembly of section .data: + +0000000080003000 : + 80003000: 00ff 0xff + 80003002: 00ff 0xff + +0000000080003004 : + 80003004: ff00 sd s0,56(a4) + 80003006: ff00 sd s0,56(a4) + +0000000080003008 : + 80003008: 0ff0 addi a2,sp,988 + 8000300a: 0ff0 addi a2,sp,988 + +000000008000300c : + 8000300c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-lwu.elf b/test/riscv/tests/rv64ui-v-lwu.elf new file mode 100644 index 00000000..2cd5e0bd Binary files /dev/null and b/test/riscv/tests/rv64ui-v-lwu.elf differ diff --git a/test/riscv/tests/rv64ui-v-or.dump b/test/riscv/tests/rv64ui-v-or.dump new file mode 100644 index 00000000..c5e0940a --- /dev/null +++ b/test/riscv/tests/rv64ui-v-or.dump @@ -0,0 +1,1265 @@ + +rv64ui-v-or: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c6868693 addi a3,a3,-920 # 800030c0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c9c60613 addi a2,a2,-868 # 80003150 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c6460613 addi a2,a2,-924 # 80003168 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: bb468693 addi a3,a3,-1100 # 80003108 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: bd068693 addi a3,a3,-1072 # 80003240 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b5060613 addi a2,a2,-1200 # 80003218 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a8468693 addi a3,a3,-1404 # 80003270 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 9a468693 addi a3,a3,-1628 # 800031e0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 93468693 addi a3,a3,-1740 # 800031a8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03800793 li a5,56 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 039357b7 lui a5,0x3935 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: f5d78793 addi a5,a5,-163 # 3934f5d <_start-0x7c6cb0a3> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000100b7 lui ra,0x10 + 80002acc: f010809b addiw ra,ra,-255 + 80002ad0: 01009093 slli ra,ra,0x10 + 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002ad8: 0f0f1137 lui sp,0xf0f1 + 80002adc: f0f1011b addiw sp,sp,-241 + 80002ae0: 0020ef33 or t5,ra,sp + 80002ae4: 00001eb7 lui t4,0x1 + 80002ae8: ff1e8e9b addiw t4,t4,-15 + 80002aec: 014e9e93 slli t4,t4,0x14 + 80002af0: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002af4: 00200193 li gp,2 + 80002af8: 5bdf1663 bne t5,t4,800030a4 + +0000000080002afc : + 80002afc: 0ff010b7 lui ra,0xff01 + 80002b00: ff00809b addiw ra,ra,-16 + 80002b04: 000f1137 lui sp,0xf1 + 80002b08: f0f1011b addiw sp,sp,-241 + 80002b0c: 00c11113 slli sp,sp,0xc + 80002b10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b14: 0020ef33 or t5,ra,sp + 80002b18: 00010eb7 lui t4,0x10 + 80002b1c: ff1e8e9b addiw t4,t4,-15 + 80002b20: 010e9e93 slli t4,t4,0x10 + 80002b24: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002b28: 00300193 li gp,3 + 80002b2c: 57df1c63 bne t5,t4,800030a4 + +0000000080002b30 : + 80002b30: 00ff00b7 lui ra,0xff0 + 80002b34: 0ff0809b addiw ra,ra,255 + 80002b38: 0f0f1137 lui sp,0xf0f1 + 80002b3c: f0f1011b addiw sp,sp,-241 + 80002b40: 0020ef33 or t5,ra,sp + 80002b44: 0fff1eb7 lui t4,0xfff1 + 80002b48: fffe8e9b addiw t4,t4,-1 + 80002b4c: 00400193 li gp,4 + 80002b50: 55df1a63 bne t5,t4,800030a4 + +0000000080002b54 : + 80002b54: 000f00b7 lui ra,0xf0 + 80002b58: 0ff0809b addiw ra,ra,255 + 80002b5c: 00c09093 slli ra,ra,0xc + 80002b60: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002b64: 000f1137 lui sp,0xf1 + 80002b68: f0f1011b addiw sp,sp,-241 + 80002b6c: 00c11113 slli sp,sp,0xc + 80002b70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b74: 0020ef33 or t5,ra,sp + 80002b78: 000f1eb7 lui t4,0xf1 + 80002b7c: fffe8e9b addiw t4,t4,-1 + 80002b80: 00ce9e93 slli t4,t4,0xc + 80002b84: 0ffe8e93 addi t4,t4,255 # f10ff <_start-0x7ff0ef01> + 80002b88: 00500193 li gp,5 + 80002b8c: 51df1c63 bne t5,t4,800030a4 + +0000000080002b90 : + 80002b90: 000100b7 lui ra,0x10 + 80002b94: f010809b addiw ra,ra,-255 + 80002b98: 01009093 slli ra,ra,0x10 + 80002b9c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002ba0: 0f0f1137 lui sp,0xf0f1 + 80002ba4: f0f1011b addiw sp,sp,-241 + 80002ba8: 0020e0b3 or ra,ra,sp + 80002bac: 00001eb7 lui t4,0x1 + 80002bb0: ff1e8e9b addiw t4,t4,-15 + 80002bb4: 014e9e93 slli t4,t4,0x14 + 80002bb8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002bbc: 00600193 li gp,6 + 80002bc0: 4fd09263 bne ra,t4,800030a4 + +0000000080002bc4 : + 80002bc4: 000100b7 lui ra,0x10 + 80002bc8: f010809b addiw ra,ra,-255 + 80002bcc: 01009093 slli ra,ra,0x10 + 80002bd0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002bd4: 0f0f1137 lui sp,0xf0f1 + 80002bd8: f0f1011b addiw sp,sp,-241 + 80002bdc: 0020e133 or sp,ra,sp + 80002be0: 00001eb7 lui t4,0x1 + 80002be4: ff1e8e9b addiw t4,t4,-15 + 80002be8: 014e9e93 slli t4,t4,0x14 + 80002bec: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002bf0: 00700193 li gp,7 + 80002bf4: 4bd11863 bne sp,t4,800030a4 + +0000000080002bf8 : + 80002bf8: 000100b7 lui ra,0x10 + 80002bfc: f010809b addiw ra,ra,-255 + 80002c00: 01009093 slli ra,ra,0x10 + 80002c04: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002c08: 0010e0b3 or ra,ra,ra + 80002c0c: 00010eb7 lui t4,0x10 + 80002c10: f01e8e9b addiw t4,t4,-255 + 80002c14: 010e9e93 slli t4,t4,0x10 + 80002c18: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002c1c: 00800193 li gp,8 + 80002c20: 49d09263 bne ra,t4,800030a4 + +0000000080002c24 : + 80002c24: 00000213 li tp,0 + 80002c28: 000100b7 lui ra,0x10 + 80002c2c: f010809b addiw ra,ra,-255 + 80002c30: 01009093 slli ra,ra,0x10 + 80002c34: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002c38: 0f0f1137 lui sp,0xf0f1 + 80002c3c: f0f1011b addiw sp,sp,-241 + 80002c40: 0020ef33 or t5,ra,sp + 80002c44: 000f0313 mv t1,t5 + 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c4c: 00200293 li t0,2 + 80002c50: fc521ce3 bne tp,t0,80002c28 + 80002c54: 00001eb7 lui t4,0x1 + 80002c58: ff1e8e9b addiw t4,t4,-15 + 80002c5c: 014e9e93 slli t4,t4,0x14 + 80002c60: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002c64: 00900193 li gp,9 + 80002c68: 43d31e63 bne t1,t4,800030a4 + +0000000080002c6c : + 80002c6c: 00000213 li tp,0 + 80002c70: 0ff010b7 lui ra,0xff01 + 80002c74: ff00809b addiw ra,ra,-16 + 80002c78: 000f1137 lui sp,0xf1 + 80002c7c: f0f1011b addiw sp,sp,-241 + 80002c80: 00c11113 slli sp,sp,0xc + 80002c84: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002c88: 0020ef33 or t5,ra,sp + 80002c8c: 00000013 nop + 80002c90: 000f0313 mv t1,t5 + 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c98: 00200293 li t0,2 + 80002c9c: fc521ae3 bne tp,t0,80002c70 + 80002ca0: 00010eb7 lui t4,0x10 + 80002ca4: ff1e8e9b addiw t4,t4,-15 + 80002ca8: 010e9e93 slli t4,t4,0x10 + 80002cac: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002cb0: 00a00193 li gp,10 + 80002cb4: 3fd31863 bne t1,t4,800030a4 + +0000000080002cb8 : + 80002cb8: 00000213 li tp,0 + 80002cbc: 00ff00b7 lui ra,0xff0 + 80002cc0: 0ff0809b addiw ra,ra,255 + 80002cc4: 0f0f1137 lui sp,0xf0f1 + 80002cc8: f0f1011b addiw sp,sp,-241 + 80002ccc: 0020ef33 or t5,ra,sp + 80002cd0: 00000013 nop + 80002cd4: 00000013 nop + 80002cd8: 000f0313 mv t1,t5 + 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce0: 00200293 li t0,2 + 80002ce4: fc521ce3 bne tp,t0,80002cbc + 80002ce8: 0fff1eb7 lui t4,0xfff1 + 80002cec: fffe8e9b addiw t4,t4,-1 + 80002cf0: 00b00193 li gp,11 + 80002cf4: 3bd31863 bne t1,t4,800030a4 + +0000000080002cf8 : + 80002cf8: 00000213 li tp,0 + 80002cfc: 000100b7 lui ra,0x10 + 80002d00: f010809b addiw ra,ra,-255 + 80002d04: 01009093 slli ra,ra,0x10 + 80002d08: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002d0c: 0f0f1137 lui sp,0xf0f1 + 80002d10: f0f1011b addiw sp,sp,-241 + 80002d14: 0020ef33 or t5,ra,sp + 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d1c: 00200293 li t0,2 + 80002d20: fc521ee3 bne tp,t0,80002cfc + 80002d24: 00001eb7 lui t4,0x1 + 80002d28: ff1e8e9b addiw t4,t4,-15 + 80002d2c: 014e9e93 slli t4,t4,0x14 + 80002d30: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002d34: 00c00193 li gp,12 + 80002d38: 37df1663 bne t5,t4,800030a4 + +0000000080002d3c : + 80002d3c: 00000213 li tp,0 + 80002d40: 0ff010b7 lui ra,0xff01 + 80002d44: ff00809b addiw ra,ra,-16 + 80002d48: 000f1137 lui sp,0xf1 + 80002d4c: f0f1011b addiw sp,sp,-241 + 80002d50: 00c11113 slli sp,sp,0xc + 80002d54: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002d58: 00000013 nop + 80002d5c: 0020ef33 or t5,ra,sp + 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d64: 00200293 li t0,2 + 80002d68: fc521ce3 bne tp,t0,80002d40 + 80002d6c: 00010eb7 lui t4,0x10 + 80002d70: ff1e8e9b addiw t4,t4,-15 + 80002d74: 010e9e93 slli t4,t4,0x10 + 80002d78: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002d7c: 00d00193 li gp,13 + 80002d80: 33df1263 bne t5,t4,800030a4 + +0000000080002d84 : + 80002d84: 00000213 li tp,0 + 80002d88: 00ff00b7 lui ra,0xff0 + 80002d8c: 0ff0809b addiw ra,ra,255 + 80002d90: 0f0f1137 lui sp,0xf0f1 + 80002d94: f0f1011b addiw sp,sp,-241 + 80002d98: 00000013 nop + 80002d9c: 00000013 nop + 80002da0: 0020ef33 or t5,ra,sp + 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da8: 00200293 li t0,2 + 80002dac: fc521ee3 bne tp,t0,80002d88 + 80002db0: 0fff1eb7 lui t4,0xfff1 + 80002db4: fffe8e9b addiw t4,t4,-1 + 80002db8: 00e00193 li gp,14 + 80002dbc: 2fdf1463 bne t5,t4,800030a4 + +0000000080002dc0 : + 80002dc0: 00000213 li tp,0 + 80002dc4: 000100b7 lui ra,0x10 + 80002dc8: f010809b addiw ra,ra,-255 + 80002dcc: 01009093 slli ra,ra,0x10 + 80002dd0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002dd4: 00000013 nop + 80002dd8: 0f0f1137 lui sp,0xf0f1 + 80002ddc: f0f1011b addiw sp,sp,-241 + 80002de0: 0020ef33 or t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fc521ce3 bne tp,t0,80002dc4 + 80002df0: 00001eb7 lui t4,0x1 + 80002df4: ff1e8e9b addiw t4,t4,-15 + 80002df8: 014e9e93 slli t4,t4,0x14 + 80002dfc: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002e00: 00f00193 li gp,15 + 80002e04: 2bdf1063 bne t5,t4,800030a4 + +0000000080002e08 : + 80002e08: 00000213 li tp,0 + 80002e0c: 0ff010b7 lui ra,0xff01 + 80002e10: ff00809b addiw ra,ra,-16 + 80002e14: 00000013 nop + 80002e18: 000f1137 lui sp,0xf1 + 80002e1c: f0f1011b addiw sp,sp,-241 + 80002e20: 00c11113 slli sp,sp,0xc + 80002e24: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002e28: 00000013 nop + 80002e2c: 0020ef33 or t5,ra,sp + 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e34: 00200293 li t0,2 + 80002e38: fc521ae3 bne tp,t0,80002e0c + 80002e3c: 00010eb7 lui t4,0x10 + 80002e40: ff1e8e9b addiw t4,t4,-15 + 80002e44: 010e9e93 slli t4,t4,0x10 + 80002e48: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002e4c: 01000193 li gp,16 + 80002e50: 25df1a63 bne t5,t4,800030a4 + +0000000080002e54 : + 80002e54: 00000213 li tp,0 + 80002e58: 00ff00b7 lui ra,0xff0 + 80002e5c: 0ff0809b addiw ra,ra,255 + 80002e60: 00000013 nop + 80002e64: 00000013 nop + 80002e68: 0f0f1137 lui sp,0xf0f1 + 80002e6c: f0f1011b addiw sp,sp,-241 + 80002e70: 0020ef33 or t5,ra,sp + 80002e74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e78: 00200293 li t0,2 + 80002e7c: fc521ee3 bne tp,t0,80002e58 + 80002e80: 0fff1eb7 lui t4,0xfff1 + 80002e84: fffe8e9b addiw t4,t4,-1 + 80002e88: 01100193 li gp,17 + 80002e8c: 21df1c63 bne t5,t4,800030a4 + +0000000080002e90 : + 80002e90: 00000213 li tp,0 + 80002e94: 0f0f1137 lui sp,0xf0f1 + 80002e98: f0f1011b addiw sp,sp,-241 + 80002e9c: 000100b7 lui ra,0x10 + 80002ea0: f010809b addiw ra,ra,-255 + 80002ea4: 01009093 slli ra,ra,0x10 + 80002ea8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002eac: 0020ef33 or t5,ra,sp + 80002eb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb4: 00200293 li t0,2 + 80002eb8: fc521ee3 bne tp,t0,80002e94 + 80002ebc: 00001eb7 lui t4,0x1 + 80002ec0: ff1e8e9b addiw t4,t4,-15 + 80002ec4: 014e9e93 slli t4,t4,0x14 + 80002ec8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002ecc: 01200193 li gp,18 + 80002ed0: 1ddf1a63 bne t5,t4,800030a4 + +0000000080002ed4 : + 80002ed4: 00000213 li tp,0 + 80002ed8: 000f1137 lui sp,0xf1 + 80002edc: f0f1011b addiw sp,sp,-241 + 80002ee0: 00c11113 slli sp,sp,0xc + 80002ee4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002ee8: 0ff010b7 lui ra,0xff01 + 80002eec: ff00809b addiw ra,ra,-16 + 80002ef0: 00000013 nop + 80002ef4: 0020ef33 or t5,ra,sp + 80002ef8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002efc: 00200293 li t0,2 + 80002f00: fc521ce3 bne tp,t0,80002ed8 + 80002f04: 00010eb7 lui t4,0x10 + 80002f08: ff1e8e9b addiw t4,t4,-15 + 80002f0c: 010e9e93 slli t4,t4,0x10 + 80002f10: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002f14: 01300193 li gp,19 + 80002f18: 19df1663 bne t5,t4,800030a4 + +0000000080002f1c : + 80002f1c: 00000213 li tp,0 + 80002f20: 0f0f1137 lui sp,0xf0f1 + 80002f24: f0f1011b addiw sp,sp,-241 + 80002f28: 00ff00b7 lui ra,0xff0 + 80002f2c: 0ff0809b addiw ra,ra,255 + 80002f30: 00000013 nop + 80002f34: 00000013 nop + 80002f38: 0020ef33 or t5,ra,sp + 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f40: 00200293 li t0,2 + 80002f44: fc521ee3 bne tp,t0,80002f20 + 80002f48: 0fff1eb7 lui t4,0xfff1 + 80002f4c: fffe8e9b addiw t4,t4,-1 + 80002f50: 01400193 li gp,20 + 80002f54: 15df1863 bne t5,t4,800030a4 + +0000000080002f58 : + 80002f58: 00000213 li tp,0 + 80002f5c: 0f0f1137 lui sp,0xf0f1 + 80002f60: f0f1011b addiw sp,sp,-241 + 80002f64: 00000013 nop + 80002f68: 000100b7 lui ra,0x10 + 80002f6c: f010809b addiw ra,ra,-255 + 80002f70: 01009093 slli ra,ra,0x10 + 80002f74: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002f78: 0020ef33 or t5,ra,sp + 80002f7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f80: 00200293 li t0,2 + 80002f84: fc521ce3 bne tp,t0,80002f5c + 80002f88: 00001eb7 lui t4,0x1 + 80002f8c: ff1e8e9b addiw t4,t4,-15 + 80002f90: 014e9e93 slli t4,t4,0x14 + 80002f94: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80002f98: 01500193 li gp,21 + 80002f9c: 11df1463 bne t5,t4,800030a4 + +0000000080002fa0 : + 80002fa0: 00000213 li tp,0 + 80002fa4: 000f1137 lui sp,0xf1 + 80002fa8: f0f1011b addiw sp,sp,-241 + 80002fac: 00c11113 slli sp,sp,0xc + 80002fb0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002fb4: 00000013 nop + 80002fb8: 0ff010b7 lui ra,0xff01 + 80002fbc: ff00809b addiw ra,ra,-16 + 80002fc0: 00000013 nop + 80002fc4: 0020ef33 or t5,ra,sp + 80002fc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fcc: 00200293 li t0,2 + 80002fd0: fc521ae3 bne tp,t0,80002fa4 + 80002fd4: 00010eb7 lui t4,0x10 + 80002fd8: ff1e8e9b addiw t4,t4,-15 + 80002fdc: 010e9e93 slli t4,t4,0x10 + 80002fe0: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002fe4: 01600193 li gp,22 + 80002fe8: 0bdf1e63 bne t5,t4,800030a4 + +0000000080002fec : + 80002fec: 00000213 li tp,0 + 80002ff0: 0f0f1137 lui sp,0xf0f1 + 80002ff4: f0f1011b addiw sp,sp,-241 + 80002ff8: 00000013 nop + 80002ffc: 00000013 nop + 80003000: 00ff00b7 lui ra,0xff0 + 80003004: 0ff0809b addiw ra,ra,255 + 80003008: 0020ef33 or t5,ra,sp + 8000300c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003010: 00200293 li t0,2 + 80003014: fc521ee3 bne tp,t0,80002ff0 + 80003018: 0fff1eb7 lui t4,0xfff1 + 8000301c: fffe8e9b addiw t4,t4,-1 + 80003020: 01700193 li gp,23 + 80003024: 09df1063 bne t5,t4,800030a4 + +0000000080003028 : + 80003028: 000100b7 lui ra,0x10 + 8000302c: f010809b addiw ra,ra,-255 + 80003030: 01009093 slli ra,ra,0x10 + 80003034: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80003038: 00106133 or sp,zero,ra + 8000303c: 00010eb7 lui t4,0x10 + 80003040: f01e8e9b addiw t4,t4,-255 + 80003044: 010e9e93 slli t4,t4,0x10 + 80003048: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000304c: 01800193 li gp,24 + 80003050: 05d11a63 bne sp,t4,800030a4 + +0000000080003054 : + 80003054: 00ff00b7 lui ra,0xff0 + 80003058: 0ff0809b addiw ra,ra,255 + 8000305c: 0000e133 or sp,ra,zero + 80003060: 00ff0eb7 lui t4,0xff0 + 80003064: 0ffe8e9b addiw t4,t4,255 + 80003068: 01900193 li gp,25 + 8000306c: 03d11c63 bne sp,t4,800030a4 + +0000000080003070 : + 80003070: 000060b3 or ra,zero,zero + 80003074: 00000e93 li t4,0 + 80003078: 01a00193 li gp,26 + 8000307c: 03d09463 bne ra,t4,800030a4 + +0000000080003080 : + 80003080: 111110b7 lui ra,0x11111 + 80003084: 1110809b addiw ra,ra,273 + 80003088: 22222137 lui sp,0x22222 + 8000308c: 2221011b addiw sp,sp,546 + 80003090: 0020e033 or zero,ra,sp + 80003094: 00000e93 li t4,0 + 80003098: 01b00193 li gp,27 + 8000309c: 01d01463 bne zero,t4,800030a4 + 800030a0: 00301a63 bne zero,gp,800030b4 + +00000000800030a4 : + 800030a4: 00119513 slli a0,gp,0x1 + 800030a8: 00050063 beqz a0,800030a8 + 800030ac: 00156513 ori a0,a0,1 + 800030b0: 00000073 ecall + +00000000800030b4 : + 800030b4: 00100513 li a0,1 + 800030b8: 00000073 ecall + 800030bc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-or.elf b/test/riscv/tests/rv64ui-v-or.elf new file mode 100644 index 00000000..cf601403 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-or.elf differ diff --git a/test/riscv/tests/rv64ui-v-ori.dump b/test/riscv/tests/rv64ui-v-ori.dump new file mode 100644 index 00000000..9b536c5f --- /dev/null +++ b/test/riscv/tests/rv64ui-v-ori.dump @@ -0,0 +1,987 @@ + +rv64ui-v-ori: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 87868693 addi a3,a3,-1928 # 80002cd0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 8ac60613 addi a2,a2,-1876 # 80002d60 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 87460613 addi a2,a2,-1932 # 80002d78 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 7c468693 addi a3,a3,1988 # 80002d18 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 7e068693 addi a3,a3,2016 # 80002e50 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 76060613 addi a2,a2,1888 # 80002e28 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 69468693 addi a3,a3,1684 # 80002e80 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 5b468693 addi a3,a3,1460 # 80002df0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 54468693 addi a3,a3,1348 # 80002db8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00d00793 li a5,13 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a6287b7 lui a5,0xa628 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: a5878793 addi a5,a5,-1448 # a627a58 <_start-0x759d85a8> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: ff0100b7 lui ra,0xff010 + 80002acc: f000809b addiw ra,ra,-256 + 80002ad0: f0f0ef13 ori t5,ra,-241 + 80002ad4: f0f00e93 li t4,-241 + 80002ad8: 00200193 li gp,2 + 80002adc: 1ddf1c63 bne t5,t4,80002cb4 + +0000000080002ae0 : + 80002ae0: 0ff010b7 lui ra,0xff01 + 80002ae4: ff00809b addiw ra,ra,-16 + 80002ae8: 0f00ef13 ori t5,ra,240 + 80002aec: 0ff01eb7 lui t4,0xff01 + 80002af0: ff0e8e9b addiw t4,t4,-16 + 80002af4: 00300193 li gp,3 + 80002af8: 1bdf1e63 bne t5,t4,80002cb4 + +0000000080002afc : + 80002afc: 00ff00b7 lui ra,0xff0 + 80002b00: 0ff0809b addiw ra,ra,255 + 80002b04: 70f0ef13 ori t5,ra,1807 + 80002b08: 00ff0eb7 lui t4,0xff0 + 80002b0c: 7ffe8e9b addiw t4,t4,2047 + 80002b10: 00400193 li gp,4 + 80002b14: 1bdf1063 bne t5,t4,80002cb4 + +0000000080002b18 : + 80002b18: f00ff0b7 lui ra,0xf00ff + 80002b1c: 00f0809b addiw ra,ra,15 + 80002b20: 0f00ef13 ori t5,ra,240 + 80002b24: f00ffeb7 lui t4,0xf00ff + 80002b28: 0ffe8e9b addiw t4,t4,255 + 80002b2c: 00500193 li gp,5 + 80002b30: 19df1263 bne t5,t4,80002cb4 + +0000000080002b34 : + 80002b34: 000100b7 lui ra,0x10 + 80002b38: f010809b addiw ra,ra,-255 + 80002b3c: 01009093 slli ra,ra,0x10 + 80002b40: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002b44: 0f00e093 ori ra,ra,240 + 80002b48: 00010eb7 lui t4,0x10 + 80002b4c: f01e8e9b addiw t4,t4,-255 + 80002b50: 010e9e93 slli t4,t4,0x10 + 80002b54: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80002b58: 00600193 li gp,6 + 80002b5c: 15d09c63 bne ra,t4,80002cb4 + +0000000080002b60 : + 80002b60: 00000213 li tp,0 + 80002b64: 0ff010b7 lui ra,0xff01 + 80002b68: ff00809b addiw ra,ra,-16 + 80002b6c: 0f00ef13 ori t5,ra,240 + 80002b70: 000f0313 mv t1,t5 + 80002b74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b78: 00200293 li t0,2 + 80002b7c: fe5214e3 bne tp,t0,80002b64 + 80002b80: 0ff01eb7 lui t4,0xff01 + 80002b84: ff0e8e9b addiw t4,t4,-16 + 80002b88: 00700193 li gp,7 + 80002b8c: 13d31463 bne t1,t4,80002cb4 + +0000000080002b90 : + 80002b90: 00000213 li tp,0 + 80002b94: 00ff00b7 lui ra,0xff0 + 80002b98: 0ff0809b addiw ra,ra,255 + 80002b9c: 70f0ef13 ori t5,ra,1807 + 80002ba0: 00000013 nop + 80002ba4: 000f0313 mv t1,t5 + 80002ba8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bac: 00200293 li t0,2 + 80002bb0: fe5212e3 bne tp,t0,80002b94 + 80002bb4: 00ff0eb7 lui t4,0xff0 + 80002bb8: 7ffe8e9b addiw t4,t4,2047 + 80002bbc: 00800193 li gp,8 + 80002bc0: 0fd31a63 bne t1,t4,80002cb4 + +0000000080002bc4 : + 80002bc4: 00000213 li tp,0 + 80002bc8: f00ff0b7 lui ra,0xf00ff + 80002bcc: 00f0809b addiw ra,ra,15 + 80002bd0: 0f00ef13 ori t5,ra,240 + 80002bd4: 00000013 nop + 80002bd8: 00000013 nop + 80002bdc: 000f0313 mv t1,t5 + 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002be4: 00200293 li t0,2 + 80002be8: fe5210e3 bne tp,t0,80002bc8 + 80002bec: f00ffeb7 lui t4,0xf00ff + 80002bf0: 0ffe8e9b addiw t4,t4,255 + 80002bf4: 00900193 li gp,9 + 80002bf8: 0bd31e63 bne t1,t4,80002cb4 + +0000000080002bfc : + 80002bfc: 00000213 li tp,0 + 80002c00: 0ff010b7 lui ra,0xff01 + 80002c04: ff00809b addiw ra,ra,-16 + 80002c08: 0f00ef13 ori t5,ra,240 + 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c10: 00200293 li t0,2 + 80002c14: fe5216e3 bne tp,t0,80002c00 + 80002c18: 0ff01eb7 lui t4,0xff01 + 80002c1c: ff0e8e9b addiw t4,t4,-16 + 80002c20: 00a00193 li gp,10 + 80002c24: 09df1863 bne t5,t4,80002cb4 + +0000000080002c28 : + 80002c28: 00000213 li tp,0 + 80002c2c: 00ff00b7 lui ra,0xff0 + 80002c30: 0ff0809b addiw ra,ra,255 + 80002c34: 00000013 nop + 80002c38: f0f0ef13 ori t5,ra,-241 + 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c40: 00200293 li t0,2 + 80002c44: fe5214e3 bne tp,t0,80002c2c + 80002c48: fff00e93 li t4,-1 + 80002c4c: 00b00193 li gp,11 + 80002c50: 07df1263 bne t5,t4,80002cb4 + +0000000080002c54 : + 80002c54: 00000213 li tp,0 + 80002c58: f00ff0b7 lui ra,0xf00ff + 80002c5c: 00f0809b addiw ra,ra,15 + 80002c60: 00000013 nop + 80002c64: 00000013 nop + 80002c68: 0f00ef13 ori t5,ra,240 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5212e3 bne tp,t0,80002c58 + 80002c78: f00ffeb7 lui t4,0xf00ff + 80002c7c: 0ffe8e9b addiw t4,t4,255 + 80002c80: 00c00193 li gp,12 + 80002c84: 03df1863 bne t5,t4,80002cb4 + +0000000080002c88 : + 80002c88: 0f006093 ori ra,zero,240 + 80002c8c: 0f000e93 li t4,240 + 80002c90: 00d00193 li gp,13 + 80002c94: 03d09063 bne ra,t4,80002cb4 + +0000000080002c98 : + 80002c98: 00ff00b7 lui ra,0xff0 + 80002c9c: 0ff0809b addiw ra,ra,255 + 80002ca0: 70f0e013 ori zero,ra,1807 + 80002ca4: 00000e93 li t4,0 + 80002ca8: 00e00193 li gp,14 + 80002cac: 01d01463 bne zero,t4,80002cb4 + 80002cb0: 00301a63 bne zero,gp,80002cc4 + +0000000080002cb4 : + 80002cb4: 00119513 slli a0,gp,0x1 + 80002cb8: 00050063 beqz a0,80002cb8 + 80002cbc: 00156513 ori a0,a0,1 + 80002cc0: 00000073 ecall + +0000000080002cc4 : + 80002cc4: 00100513 li a0,1 + 80002cc8: 00000073 ecall + 80002ccc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-ori.elf b/test/riscv/tests/rv64ui-v-ori.elf new file mode 100644 index 00000000..db589c1d Binary files /dev/null and b/test/riscv/tests/rv64ui-v-ori.elf differ diff --git a/test/riscv/tests/rv64ui-v-sb.dump b/test/riscv/tests/rv64ui-v-sb.dump new file mode 100644 index 00000000..52b1645b --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sb.dump @@ -0,0 +1,1169 @@ + +rv64ui-v-sb: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000a117 auipc sp,0xa + 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00003617 auipc a2,0x3 + 80002318: cec60613 addi a2,a2,-788 # 80005000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00007797 auipc a5,0x7 + 80002334: 4b878793 addi a5,a5,1208 # 800097e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00007717 auipc a4,0x7 + 80002348: 49c70713 addi a4,a4,1180 # 800097e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00007897 auipc a7,0x7 + 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00007797 auipc a5,0x7 + 80002384: 07078793 addi a5,a5,112 # 800093f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00007797 auipc a5,0x7 + 80002448: 3807be23 sd zero,924(a5) # 800097e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: a8068693 addi a3,a3,-1408 # 80002ed8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: ab460613 addi a2,a2,-1356 # 80002f68 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: a7c60613 addi a2,a2,-1412 # 80002f80 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 9cc68693 addi a3,a3,-1588 # 80002f20 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 9e868693 addi a3,a3,-1560 # 80003058 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 96860613 addi a2,a2,-1688 # 80003030 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00007d17 auipc s10,0x7 + 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 + 80002724: 00003b97 auipc s7,0x3 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00007a17 auipc s4,0x7 + 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00007717 auipc a4,0x7 + 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00007717 auipc a4,0x7 + 800027d4: 00f73823 sd a5,16(a4) # 800097e0 + 800027d8: 00007717 auipc a4,0x7 + 800027dc: 00f73823 sd a5,16(a4) # 800097e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 89c68693 addi a3,a3,-1892 # 80003088 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 7bc68693 addi a3,a3,1980 # 80002ff8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 74c68693 addi a3,a3,1868 # 80002fc0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00003697 auipc a3,0x3 + 800028e0: 72468693 addi a3,a3,1828 # 80006000 + 800028e4: 00004717 auipc a4,0x4 + 800028e8: 71c70713 addi a4,a4,1820 # 80007000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00005797 auipc a5,0x5 + 800028f8: 70c78793 addi a5,a5,1804 # 80008000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00002897 auipc a7,0x2 + 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00003697 auipc a3,0x3 + 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00002617 auipc a2,0x2 + 80002938: 6cc60613 addi a2,a2,1740 # 80005000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00005697 auipc a3,0x5 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 + 8000294c: 00003717 auipc a4,0x3 + 80002950: 6af73a23 sd a5,1716(a4) # 80006000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00006697 auipc a3,0x6 + 800029c0: 64468693 addi a3,a3,1604 # 80009000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00007617 auipc a2,0x7 + 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 + 800029d4: 00007797 auipc a5,0x7 + 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 + 800029dc: 00007317 auipc t1,0x7 + 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 + 800029e4: 01300793 li a5,19 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00007797 auipc a5,0x7 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 061a97b7 lui a5,0x61a9 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 7fc78793 addi a5,a5,2044 # 61a97fc <_start-0x79e56804> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00001097 auipc ra,0x1 + 80002acc: 53808093 addi ra,ra,1336 # 80004000 + 80002ad0: faa00113 li sp,-86 + 80002ad4: 00208023 sb sp,0(ra) + 80002ad8: 00008f03 lb t5,0(ra) + 80002adc: faa00e93 li t4,-86 + 80002ae0: 00200193 li gp,2 + 80002ae4: 3ddf1c63 bne t5,t4,80002ebc + +0000000080002ae8 : + 80002ae8: 00001097 auipc ra,0x1 + 80002aec: 51808093 addi ra,ra,1304 # 80004000 + 80002af0: 00000113 li sp,0 + 80002af4: 002080a3 sb sp,1(ra) + 80002af8: 00108f03 lb t5,1(ra) + 80002afc: 00000e93 li t4,0 + 80002b00: 00300193 li gp,3 + 80002b04: 3bdf1c63 bne t5,t4,80002ebc + +0000000080002b08 : + 80002b08: 00001097 auipc ra,0x1 + 80002b0c: 4f808093 addi ra,ra,1272 # 80004000 + 80002b10: fffff137 lui sp,0xfffff + 80002b14: fa01011b addiw sp,sp,-96 + 80002b18: 00208123 sb sp,2(ra) + 80002b1c: 00209f03 lh t5,2(ra) + 80002b20: fffffeb7 lui t4,0xfffff + 80002b24: fa0e8e9b addiw t4,t4,-96 + 80002b28: 00400193 li gp,4 + 80002b2c: 39df1863 bne t5,t4,80002ebc + +0000000080002b30 : + 80002b30: 00001097 auipc ra,0x1 + 80002b34: 4d008093 addi ra,ra,1232 # 80004000 + 80002b38: 00a00113 li sp,10 + 80002b3c: 002081a3 sb sp,3(ra) + 80002b40: 00308f03 lb t5,3(ra) + 80002b44: 00a00e93 li t4,10 + 80002b48: 00500193 li gp,5 + 80002b4c: 37df1863 bne t5,t4,80002ebc + +0000000080002b50 : + 80002b50: 00001097 auipc ra,0x1 + 80002b54: 4b708093 addi ra,ra,1207 # 80004007 + 80002b58: faa00113 li sp,-86 + 80002b5c: fe208ea3 sb sp,-3(ra) + 80002b60: ffd08f03 lb t5,-3(ra) + 80002b64: faa00e93 li t4,-86 + 80002b68: 00600193 li gp,6 + 80002b6c: 35df1863 bne t5,t4,80002ebc + +0000000080002b70 : + 80002b70: 00001097 auipc ra,0x1 + 80002b74: 49708093 addi ra,ra,1175 # 80004007 + 80002b78: 00000113 li sp,0 + 80002b7c: fe208f23 sb sp,-2(ra) + 80002b80: ffe08f03 lb t5,-2(ra) + 80002b84: 00000e93 li t4,0 + 80002b88: 00700193 li gp,7 + 80002b8c: 33df1863 bne t5,t4,80002ebc + +0000000080002b90 : + 80002b90: 00001097 auipc ra,0x1 + 80002b94: 47708093 addi ra,ra,1143 # 80004007 + 80002b98: fa000113 li sp,-96 + 80002b9c: fe208fa3 sb sp,-1(ra) + 80002ba0: fff08f03 lb t5,-1(ra) + 80002ba4: fa000e93 li t4,-96 + 80002ba8: 00800193 li gp,8 + 80002bac: 31df1863 bne t5,t4,80002ebc + +0000000080002bb0 : + 80002bb0: 00001097 auipc ra,0x1 + 80002bb4: 45708093 addi ra,ra,1111 # 80004007 + 80002bb8: 00a00113 li sp,10 + 80002bbc: 00208023 sb sp,0(ra) + 80002bc0: 00008f03 lb t5,0(ra) + 80002bc4: 00a00e93 li t4,10 + 80002bc8: 00900193 li gp,9 + 80002bcc: 2fdf1863 bne t5,t4,80002ebc + +0000000080002bd0 : + 80002bd0: 00001097 auipc ra,0x1 + 80002bd4: 43808093 addi ra,ra,1080 # 80004008 + 80002bd8: 12345137 lui sp,0x12345 + 80002bdc: 6781011b addiw sp,sp,1656 + 80002be0: fe008213 addi tp,ra,-32 + 80002be4: 02220023 sb sp,32(tp) # 20 <_start-0x7fffffe0> + 80002be8: 00008283 lb t0,0(ra) + 80002bec: 07800e93 li t4,120 + 80002bf0: 00a00193 li gp,10 + 80002bf4: 2dd29463 bne t0,t4,80002ebc + +0000000080002bf8 : + 80002bf8: 00001097 auipc ra,0x1 + 80002bfc: 41008093 addi ra,ra,1040 # 80004008 + 80002c00: 00003137 lui sp,0x3 + 80002c04: 0981011b addiw sp,sp,152 + 80002c08: ffa08093 addi ra,ra,-6 + 80002c0c: 002083a3 sb sp,7(ra) + 80002c10: 00001217 auipc tp,0x1 + 80002c14: 3f920213 addi tp,tp,1017 # 80004009 + 80002c18: 00020283 lb t0,0(tp) # 0 <_start-0x80000000> + 80002c1c: f9800e93 li t4,-104 + 80002c20: 00b00193 li gp,11 + 80002c24: 29d29c63 bne t0,t4,80002ebc + +0000000080002c28 : + 80002c28: 00c00193 li gp,12 + 80002c2c: 00000213 li tp,0 + 80002c30: fdd00093 li ra,-35 + 80002c34: 00001117 auipc sp,0x1 + 80002c38: 3cc10113 addi sp,sp,972 # 80004000 + 80002c3c: 00110023 sb ra,0(sp) + 80002c40: 00010f03 lb t5,0(sp) + 80002c44: fdd00e93 li t4,-35 + 80002c48: 27df1a63 bne t5,t4,80002ebc + 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c50: 00200293 li t0,2 + 80002c54: fc521ee3 bne tp,t0,80002c30 + +0000000080002c58 : + 80002c58: 00d00193 li gp,13 + 80002c5c: 00000213 li tp,0 + 80002c60: fcd00093 li ra,-51 + 80002c64: 00001117 auipc sp,0x1 + 80002c68: 39c10113 addi sp,sp,924 # 80004000 + 80002c6c: 00000013 nop + 80002c70: 001100a3 sb ra,1(sp) + 80002c74: 00110f03 lb t5,1(sp) + 80002c78: fcd00e93 li t4,-51 + 80002c7c: 25df1063 bne t5,t4,80002ebc + 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c84: 00200293 li t0,2 + 80002c88: fc521ce3 bne tp,t0,80002c60 + +0000000080002c8c : + 80002c8c: 00e00193 li gp,14 + 80002c90: 00000213 li tp,0 + 80002c94: fcc00093 li ra,-52 + 80002c98: 00001117 auipc sp,0x1 + 80002c9c: 36810113 addi sp,sp,872 # 80004000 + 80002ca0: 00000013 nop + 80002ca4: 00000013 nop + 80002ca8: 00110123 sb ra,2(sp) + 80002cac: 00210f03 lb t5,2(sp) + 80002cb0: fcc00e93 li t4,-52 + 80002cb4: 21df1463 bne t5,t4,80002ebc + 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cbc: 00200293 li t0,2 + 80002cc0: fc521ae3 bne tp,t0,80002c94 + +0000000080002cc4 : + 80002cc4: 00f00193 li gp,15 + 80002cc8: 00000213 li tp,0 + 80002ccc: fbc00093 li ra,-68 + 80002cd0: 00000013 nop + 80002cd4: 00001117 auipc sp,0x1 + 80002cd8: 32c10113 addi sp,sp,812 # 80004000 + 80002cdc: 001101a3 sb ra,3(sp) + 80002ce0: 00310f03 lb t5,3(sp) + 80002ce4: fbc00e93 li t4,-68 + 80002ce8: 1ddf1a63 bne t5,t4,80002ebc + 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf0: 00200293 li t0,2 + 80002cf4: fc521ce3 bne tp,t0,80002ccc + +0000000080002cf8 : + 80002cf8: 01000193 li gp,16 + 80002cfc: 00000213 li tp,0 + 80002d00: fbb00093 li ra,-69 + 80002d04: 00000013 nop + 80002d08: 00001117 auipc sp,0x1 + 80002d0c: 2f810113 addi sp,sp,760 # 80004000 + 80002d10: 00000013 nop + 80002d14: 00110223 sb ra,4(sp) + 80002d18: 00410f03 lb t5,4(sp) + 80002d1c: fbb00e93 li t4,-69 + 80002d20: 19df1e63 bne t5,t4,80002ebc + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fc521ae3 bne tp,t0,80002d00 + +0000000080002d30 : + 80002d30: 01100193 li gp,17 + 80002d34: 00000213 li tp,0 + 80002d38: fab00093 li ra,-85 + 80002d3c: 00000013 nop + 80002d40: 00000013 nop + 80002d44: 00001117 auipc sp,0x1 + 80002d48: 2bc10113 addi sp,sp,700 # 80004000 + 80002d4c: 001102a3 sb ra,5(sp) + 80002d50: 00510f03 lb t5,5(sp) + 80002d54: fab00e93 li t4,-85 + 80002d58: 17df1263 bne t5,t4,80002ebc + 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d60: 00200293 li t0,2 + 80002d64: fc521ae3 bne tp,t0,80002d38 + +0000000080002d68 : + 80002d68: 01200193 li gp,18 + 80002d6c: 00000213 li tp,0 + 80002d70: 00001117 auipc sp,0x1 + 80002d74: 29010113 addi sp,sp,656 # 80004000 + 80002d78: 03300093 li ra,51 + 80002d7c: 00110023 sb ra,0(sp) + 80002d80: 00010f03 lb t5,0(sp) + 80002d84: 03300e93 li t4,51 + 80002d88: 13df1a63 bne t5,t4,80002ebc + 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d90: 00200293 li t0,2 + 80002d94: fc521ee3 bne tp,t0,80002d70 + +0000000080002d98 : + 80002d98: 01300193 li gp,19 + 80002d9c: 00000213 li tp,0 + 80002da0: 00001117 auipc sp,0x1 + 80002da4: 26010113 addi sp,sp,608 # 80004000 + 80002da8: 02300093 li ra,35 + 80002dac: 00000013 nop + 80002db0: 001100a3 sb ra,1(sp) + 80002db4: 00110f03 lb t5,1(sp) + 80002db8: 02300e93 li t4,35 + 80002dbc: 11df1063 bne t5,t4,80002ebc + 80002dc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dc4: 00200293 li t0,2 + 80002dc8: fc521ce3 bne tp,t0,80002da0 + +0000000080002dcc : + 80002dcc: 01400193 li gp,20 + 80002dd0: 00000213 li tp,0 + 80002dd4: 00001117 auipc sp,0x1 + 80002dd8: 22c10113 addi sp,sp,556 # 80004000 + 80002ddc: 02200093 li ra,34 + 80002de0: 00000013 nop + 80002de4: 00000013 nop + 80002de8: 00110123 sb ra,2(sp) + 80002dec: 00210f03 lb t5,2(sp) + 80002df0: 02200e93 li t4,34 + 80002df4: 0ddf1463 bne t5,t4,80002ebc + 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dfc: 00200293 li t0,2 + 80002e00: fc521ae3 bne tp,t0,80002dd4 + +0000000080002e04 : + 80002e04: 01500193 li gp,21 + 80002e08: 00000213 li tp,0 + 80002e0c: 00001117 auipc sp,0x1 + 80002e10: 1f410113 addi sp,sp,500 # 80004000 + 80002e14: 00000013 nop + 80002e18: 01200093 li ra,18 + 80002e1c: 001101a3 sb ra,3(sp) + 80002e20: 00310f03 lb t5,3(sp) + 80002e24: 01200e93 li t4,18 + 80002e28: 09df1a63 bne t5,t4,80002ebc + 80002e2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e30: 00200293 li t0,2 + 80002e34: fc521ce3 bne tp,t0,80002e0c + +0000000080002e38 : + 80002e38: 01600193 li gp,22 + 80002e3c: 00000213 li tp,0 + 80002e40: 00001117 auipc sp,0x1 + 80002e44: 1c010113 addi sp,sp,448 # 80004000 + 80002e48: 00000013 nop + 80002e4c: 01100093 li ra,17 + 80002e50: 00000013 nop + 80002e54: 00110223 sb ra,4(sp) + 80002e58: 00410f03 lb t5,4(sp) + 80002e5c: 01100e93 li t4,17 + 80002e60: 05df1e63 bne t5,t4,80002ebc + 80002e64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e68: 00200293 li t0,2 + 80002e6c: fc521ae3 bne tp,t0,80002e40 + +0000000080002e70 : + 80002e70: 01700193 li gp,23 + 80002e74: 00000213 li tp,0 + 80002e78: 00001117 auipc sp,0x1 + 80002e7c: 18810113 addi sp,sp,392 # 80004000 + 80002e80: 00000013 nop + 80002e84: 00000013 nop + 80002e88: 00100093 li ra,1 + 80002e8c: 001102a3 sb ra,5(sp) + 80002e90: 00510f03 lb t5,5(sp) + 80002e94: 00100e93 li t4,1 + 80002e98: 03df1263 bne t5,t4,80002ebc + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fc521ae3 bne tp,t0,80002e78 + 80002ea8: 0ef00513 li a0,239 + 80002eac: 00001597 auipc a1,0x1 + 80002eb0: 15458593 addi a1,a1,340 # 80004000 + 80002eb4: 00a581a3 sb a0,3(a1) + 80002eb8: 00301a63 bne zero,gp,80002ecc + +0000000080002ebc : + 80002ebc: 00119513 slli a0,gp,0x1 + 80002ec0: 00050063 beqz a0,80002ec0 + 80002ec4: 00156513 ori a0,a0,1 + 80002ec8: 00000073 ecall + +0000000080002ecc : + 80002ecc: 00100513 li a0,1 + 80002ed0: 00000073 ecall + 80002ed4: c0001073 unimp + +Disassembly of section .data: + +0000000080004000 : + 80004000: jal t6,800026fe + +0000000080004001 : + 80004001: jal t6,800026ff + +0000000080004002 : + 80004002: jal t6,80002700 + +0000000080004003 : + 80004003: jal t6,80002701 + +0000000080004004 : + 80004004: jal t6,80002702 + +0000000080004005 : + 80004005: jal t6,80002703 + +0000000080004006 : + 80004006: jal t6,80002704 + +0000000080004007 : + 80004007: jal t6,80012007 <_end+0x8817> + +0000000080004008 : + 80004008: jal t6,80012008 <_end+0x8818> + +0000000080004009 : + 80004009: ef Address 0x0000000080004009 is out of bounds. + + 8000400d: diff --git a/test/riscv/tests/rv64ui-v-sb.elf b/test/riscv/tests/rv64ui-v-sb.elf new file mode 100644 index 00000000..72d0ab55 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sb.elf differ diff --git a/test/riscv/tests/rv64ui-v-sd.dump b/test/riscv/tests/rv64ui-v-sd.dump new file mode 100644 index 00000000..3fc62989 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sd.dump @@ -0,0 +1,1325 @@ + +rv64ui-v-sd: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000a117 auipc sp,0xa + 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00003617 auipc a2,0x3 + 80002318: cec60613 addi a2,a2,-788 # 80005000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00007797 auipc a5,0x7 + 80002334: 4b878793 addi a5,a5,1208 # 800097e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00007717 auipc a4,0x7 + 80002348: 49c70713 addi a4,a4,1180 # 800097e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00007897 auipc a7,0x7 + 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00007797 auipc a5,0x7 + 80002384: 07078793 addi a5,a5,112 # 800093f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00007797 auipc a5,0x7 + 80002448: 3807be23 sd zero,924(a5) # 800097e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: cd068693 addi a3,a3,-816 # 80003128 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: d0460613 addi a2,a2,-764 # 800031b8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: ccc60613 addi a2,a2,-820 # 800031d0 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: c1c68693 addi a3,a3,-996 # 80003170 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: c3868693 addi a3,a3,-968 # 800032a8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: bb860613 addi a2,a2,-1096 # 80003280 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00007d17 auipc s10,0x7 + 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 + 80002724: 00003b97 auipc s7,0x3 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00007a17 auipc s4,0x7 + 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00007717 auipc a4,0x7 + 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00007717 auipc a4,0x7 + 800027d4: 00f73823 sd a5,16(a4) # 800097e0 + 800027d8: 00007717 auipc a4,0x7 + 800027dc: 00f73823 sd a5,16(a4) # 800097e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: aec68693 addi a3,a3,-1300 # 800032d8 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: a0c68693 addi a3,a3,-1524 # 80003248 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 99c68693 addi a3,a3,-1636 # 80003210 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00003697 auipc a3,0x3 + 800028e0: 72468693 addi a3,a3,1828 # 80006000 + 800028e4: 00004717 auipc a4,0x4 + 800028e8: 71c70713 addi a4,a4,1820 # 80007000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00005797 auipc a5,0x5 + 800028f8: 70c78793 addi a5,a5,1804 # 80008000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00002897 auipc a7,0x2 + 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00003697 auipc a3,0x3 + 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00002617 auipc a2,0x2 + 80002938: 6cc60613 addi a2,a2,1740 # 80005000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00005697 auipc a3,0x5 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 + 8000294c: 00003717 auipc a4,0x3 + 80002950: 6af73a23 sd a5,1716(a4) # 80006000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00006697 auipc a3,0x6 + 800029c0: 64468693 addi a3,a3,1604 # 80009000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00007617 auipc a2,0x7 + 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 + 800029d4: 00007797 auipc a5,0x7 + 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 + 800029dc: 00007317 auipc t1,0x7 + 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 + 800029e4: 00a00793 li a5,10 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00007797 auipc a5,0x7 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 036b47b7 lui a5,0x36b4 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: c8578793 addi a5,a5,-891 # 36b3c85 <_start-0x7c94c37b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00001097 auipc ra,0x1 + 80002acc: 53808093 addi ra,ra,1336 # 80004000 + 80002ad0: 00550137 lui sp,0x550 + 80002ad4: 0551011b addiw sp,sp,85 + 80002ad8: 01011113 slli sp,sp,0x10 + 80002adc: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> + 80002ae0: 01111113 slli sp,sp,0x11 + 80002ae4: 0aa10113 addi sp,sp,170 + 80002ae8: 0020b023 sd sp,0(ra) + 80002aec: 0000bf03 ld t5,0(ra) + 80002af0: 00550eb7 lui t4,0x550 + 80002af4: 055e8e9b addiw t4,t4,85 + 80002af8: 010e9e93 slli t4,t4,0x10 + 80002afc: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> + 80002b00: 011e9e93 slli t4,t4,0x11 + 80002b04: 0aae8e93 addi t4,t4,170 + 80002b08: 00200193 li gp,2 + 80002b0c: 61df1063 bne t5,t4,8000310c + +0000000080002b10 : + 80002b10: 00001097 auipc ra,0x1 + 80002b14: 4f008093 addi ra,ra,1264 # 80004000 + 80002b18: ffd50137 lui sp,0xffd50 + 80002b1c: 0551011b addiw sp,sp,85 + 80002b20: 01011113 slli sp,sp,0x10 + 80002b24: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> + 80002b28: 00d11113 slli sp,sp,0xd + 80002b2c: 00b10113 addi sp,sp,11 + 80002b30: 00c11113 slli sp,sp,0xc + 80002b34: a0010113 addi sp,sp,-1536 + 80002b38: 0020b423 sd sp,8(ra) + 80002b3c: 0080bf03 ld t5,8(ra) + 80002b40: ffd50eb7 lui t4,0xffd50 + 80002b44: 055e8e9b addiw t4,t4,85 + 80002b48: 010e9e93 slli t4,t4,0x10 + 80002b4c: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> + 80002b50: 00de9e93 slli t4,t4,0xd + 80002b54: 00be8e93 addi t4,t4,11 + 80002b58: 00ce9e93 slli t4,t4,0xc + 80002b5c: a00e8e93 addi t4,t4,-1536 + 80002b60: 00300193 li gp,3 + 80002b64: 5bdf1463 bne t5,t4,8000310c + +0000000080002b68 : + 80002b68: 00001097 auipc ra,0x1 + 80002b6c: 49808093 addi ra,ra,1176 # 80004000 + 80002b70: 00550137 lui sp,0x550 + 80002b74: 0551011b addiw sp,sp,85 + 80002b78: 00d11113 slli sp,sp,0xd + 80002b7c: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> + 80002b80: 00c11113 slli sp,sp,0xc + 80002b84: a0110113 addi sp,sp,-1535 + 80002b88: 00c11113 slli sp,sp,0xc + 80002b8c: aa010113 addi sp,sp,-1376 + 80002b90: 0020b823 sd sp,16(ra) + 80002b94: 0100bf03 ld t5,16(ra) + 80002b98: 00550eb7 lui t4,0x550 + 80002b9c: 055e8e9b addiw t4,t4,85 + 80002ba0: 00de9e93 slli t4,t4,0xd + 80002ba4: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> + 80002ba8: 00ce9e93 slli t4,t4,0xc + 80002bac: a01e8e93 addi t4,t4,-1535 + 80002bb0: 00ce9e93 slli t4,t4,0xc + 80002bb4: aa0e8e93 addi t4,t4,-1376 + 80002bb8: 00400193 li gp,4 + 80002bbc: 55df1863 bne t5,t4,8000310c + +0000000080002bc0 : + 80002bc0: 00001097 auipc ra,0x1 + 80002bc4: 44008093 addi ra,ra,1088 # 80004000 + 80002bc8: fffd0137 lui sp,0xfffd0 + 80002bcc: 0551011b addiw sp,sp,85 + 80002bd0: 01011113 slli sp,sp,0x10 + 80002bd4: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> + 80002bd8: 01011113 slli sp,sp,0x10 + 80002bdc: 05510113 addi sp,sp,85 + 80002be0: 00d11113 slli sp,sp,0xd + 80002be4: 00a10113 addi sp,sp,10 + 80002be8: 0020bc23 sd sp,24(ra) + 80002bec: 0180bf03 ld t5,24(ra) + 80002bf0: fffd0eb7 lui t4,0xfffd0 + 80002bf4: 055e8e9b addiw t4,t4,85 + 80002bf8: 010e9e93 slli t4,t4,0x10 + 80002bfc: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> + 80002c00: 010e9e93 slli t4,t4,0x10 + 80002c04: 055e8e93 addi t4,t4,85 + 80002c08: 00de9e93 slli t4,t4,0xd + 80002c0c: 00ae8e93 addi t4,t4,10 + 80002c10: 00500193 li gp,5 + 80002c14: 4fdf1c63 bne t5,t4,8000310c + +0000000080002c18 : + 80002c18: 00001097 auipc ra,0x1 + 80002c1c: 42008093 addi ra,ra,1056 # 80004038 + 80002c20: 00550137 lui sp,0x550 + 80002c24: 0551011b addiw sp,sp,85 + 80002c28: 01011113 slli sp,sp,0x10 + 80002c2c: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> + 80002c30: 01111113 slli sp,sp,0x11 + 80002c34: 0aa10113 addi sp,sp,170 + 80002c38: fe20b423 sd sp,-24(ra) + 80002c3c: fe80bf03 ld t5,-24(ra) + 80002c40: 00550eb7 lui t4,0x550 + 80002c44: 055e8e9b addiw t4,t4,85 + 80002c48: 010e9e93 slli t4,t4,0x10 + 80002c4c: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> + 80002c50: 011e9e93 slli t4,t4,0x11 + 80002c54: 0aae8e93 addi t4,t4,170 + 80002c58: 00600193 li gp,6 + 80002c5c: 4bdf1863 bne t5,t4,8000310c + +0000000080002c60 : + 80002c60: 00001097 auipc ra,0x1 + 80002c64: 3d808093 addi ra,ra,984 # 80004038 + 80002c68: ffd50137 lui sp,0xffd50 + 80002c6c: 0551011b addiw sp,sp,85 + 80002c70: 01011113 slli sp,sp,0x10 + 80002c74: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> + 80002c78: 00d11113 slli sp,sp,0xd + 80002c7c: 00b10113 addi sp,sp,11 + 80002c80: 00c11113 slli sp,sp,0xc + 80002c84: a0010113 addi sp,sp,-1536 + 80002c88: fe20b823 sd sp,-16(ra) + 80002c8c: ff00bf03 ld t5,-16(ra) + 80002c90: ffd50eb7 lui t4,0xffd50 + 80002c94: 055e8e9b addiw t4,t4,85 + 80002c98: 010e9e93 slli t4,t4,0x10 + 80002c9c: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> + 80002ca0: 00de9e93 slli t4,t4,0xd + 80002ca4: 00be8e93 addi t4,t4,11 + 80002ca8: 00ce9e93 slli t4,t4,0xc + 80002cac: a00e8e93 addi t4,t4,-1536 + 80002cb0: 00700193 li gp,7 + 80002cb4: 45df1c63 bne t5,t4,8000310c + +0000000080002cb8 : + 80002cb8: 00001097 auipc ra,0x1 + 80002cbc: 38008093 addi ra,ra,896 # 80004038 + 80002cc0: 00550137 lui sp,0x550 + 80002cc4: 0551011b addiw sp,sp,85 + 80002cc8: 00d11113 slli sp,sp,0xd + 80002ccc: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> + 80002cd0: 00c11113 slli sp,sp,0xc + 80002cd4: a0110113 addi sp,sp,-1535 + 80002cd8: 00c11113 slli sp,sp,0xc + 80002cdc: aa010113 addi sp,sp,-1376 + 80002ce0: fe20bc23 sd sp,-8(ra) + 80002ce4: ff80bf03 ld t5,-8(ra) + 80002ce8: 00550eb7 lui t4,0x550 + 80002cec: 055e8e9b addiw t4,t4,85 + 80002cf0: 00de9e93 slli t4,t4,0xd + 80002cf4: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> + 80002cf8: 00ce9e93 slli t4,t4,0xc + 80002cfc: a01e8e93 addi t4,t4,-1535 + 80002d00: 00ce9e93 slli t4,t4,0xc + 80002d04: aa0e8e93 addi t4,t4,-1376 + 80002d08: 00800193 li gp,8 + 80002d0c: 41df1063 bne t5,t4,8000310c + +0000000080002d10 : + 80002d10: 00001097 auipc ra,0x1 + 80002d14: 32808093 addi ra,ra,808 # 80004038 + 80002d18: fffd0137 lui sp,0xfffd0 + 80002d1c: 0551011b addiw sp,sp,85 + 80002d20: 01011113 slli sp,sp,0x10 + 80002d24: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> + 80002d28: 01011113 slli sp,sp,0x10 + 80002d2c: 05510113 addi sp,sp,85 + 80002d30: 00d11113 slli sp,sp,0xd + 80002d34: 00a10113 addi sp,sp,10 + 80002d38: 0020b023 sd sp,0(ra) + 80002d3c: 0000bf03 ld t5,0(ra) + 80002d40: fffd0eb7 lui t4,0xfffd0 + 80002d44: 055e8e9b addiw t4,t4,85 + 80002d48: 010e9e93 slli t4,t4,0x10 + 80002d4c: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> + 80002d50: 010e9e93 slli t4,t4,0x10 + 80002d54: 055e8e93 addi t4,t4,85 + 80002d58: 00de9e93 slli t4,t4,0xd + 80002d5c: 00ae8e93 addi t4,t4,10 + 80002d60: 00900193 li gp,9 + 80002d64: 3bdf1463 bne t5,t4,8000310c + +0000000080002d68 : + 80002d68: 00001097 auipc ra,0x1 + 80002d6c: 2d808093 addi ra,ra,728 # 80004040 + 80002d70: 00247137 lui sp,0x247 + 80002d74: 8ad1011b addiw sp,sp,-1875 + 80002d78: 00e11113 slli sp,sp,0xe + 80002d7c: c0910113 addi sp,sp,-1015 # 246c09 <_start-0x7fdb93f7> + 80002d80: 00d11113 slli sp,sp,0xd + 80002d84: 34510113 addi sp,sp,837 + 80002d88: 00c11113 slli sp,sp,0xc + 80002d8c: 67810113 addi sp,sp,1656 + 80002d90: fe008213 addi tp,ra,-32 + 80002d94: 02223023 sd sp,32(tp) # 20 <_start-0x7fffffe0> + 80002d98: 0000b283 ld t0,0(ra) + 80002d9c: 00247eb7 lui t4,0x247 + 80002da0: 8ade8e9b addiw t4,t4,-1875 + 80002da4: 00ee9e93 slli t4,t4,0xe + 80002da8: c09e8e93 addi t4,t4,-1015 # 246c09 <_start-0x7fdb93f7> + 80002dac: 00de9e93 slli t4,t4,0xd + 80002db0: 345e8e93 addi t4,t4,837 + 80002db4: 00ce9e93 slli t4,t4,0xc + 80002db8: 678e8e93 addi t4,t4,1656 + 80002dbc: 00a00193 li gp,10 + 80002dc0: 35d29663 bne t0,t4,8000310c + +0000000080002dc4 : + 80002dc4: 00001097 auipc ra,0x1 + 80002dc8: 27c08093 addi ra,ra,636 # 80004040 + 80002dcc: 00b04137 lui sp,0xb04 + 80002dd0: 2611011b addiw sp,sp,609 + 80002dd4: 00c11113 slli sp,sp,0xc + 80002dd8: 30b10113 addi sp,sp,779 # b0430b <_start-0x7f4fbcf5> + 80002ddc: 00f11113 slli sp,sp,0xf + 80002de0: 21310113 addi sp,sp,531 + 80002de4: 00c11113 slli sp,sp,0xc + 80002de8: 09810113 addi sp,sp,152 + 80002dec: ffd08093 addi ra,ra,-3 + 80002df0: 0020b5a3 sd sp,11(ra) + 80002df4: 00001217 auipc tp,0x1 + 80002df8: 25420213 addi tp,tp,596 # 80004048 + 80002dfc: 00023283 ld t0,0(tp) # 0 <_start-0x80000000> + 80002e00: 00b04eb7 lui t4,0xb04 + 80002e04: 261e8e9b addiw t4,t4,609 + 80002e08: 00ce9e93 slli t4,t4,0xc + 80002e0c: 30be8e93 addi t4,t4,779 # b0430b <_start-0x7f4fbcf5> + 80002e10: 00fe9e93 slli t4,t4,0xf + 80002e14: 213e8e93 addi t4,t4,531 + 80002e18: 00ce9e93 slli t4,t4,0xc + 80002e1c: 098e8e93 addi t4,t4,152 + 80002e20: 00b00193 li gp,11 + 80002e24: 2fd29463 bne t0,t4,8000310c + +0000000080002e28 : + 80002e28: 00c00193 li gp,12 + 80002e2c: 00000213 li tp,0 + 80002e30: 0abbd0b7 lui ra,0xabbd + 80002e34: cdd0809b addiw ra,ra,-803 + 80002e38: 00001117 auipc sp,0x1 + 80002e3c: 1c810113 addi sp,sp,456 # 80004000 + 80002e40: 00113023 sd ra,0(sp) + 80002e44: 00013f03 ld t5,0(sp) + 80002e48: 0abbdeb7 lui t4,0xabbd + 80002e4c: cdde8e9b addiw t4,t4,-803 + 80002e50: 2bdf1e63 bne t5,t4,8000310c + 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e58: 00200293 li t0,2 + 80002e5c: fc521ae3 bne tp,t0,80002e30 + +0000000080002e60 : + 80002e60: 00d00193 li gp,13 + 80002e64: 00000213 li tp,0 + 80002e68: 0aabc0b7 lui ra,0xaabc + 80002e6c: ccd0809b addiw ra,ra,-819 + 80002e70: 00001117 auipc sp,0x1 + 80002e74: 19010113 addi sp,sp,400 # 80004000 + 80002e78: 00000013 nop + 80002e7c: 00113423 sd ra,8(sp) + 80002e80: 00813f03 ld t5,8(sp) + 80002e84: 0aabceb7 lui t4,0xaabc + 80002e88: ccde8e9b addiw t4,t4,-819 + 80002e8c: 29df1063 bne t5,t4,8000310c + 80002e90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e94: 00200293 li t0,2 + 80002e98: fc5218e3 bne tp,t0,80002e68 + +0000000080002e9c : + 80002e9c: 00e00193 li gp,14 + 80002ea0: 00000213 li tp,0 + 80002ea4: 0daac0b7 lui ra,0xdaac + 80002ea8: bcc0809b addiw ra,ra,-1076 + 80002eac: 00001117 auipc sp,0x1 + 80002eb0: 15410113 addi sp,sp,340 # 80004000 + 80002eb4: 00000013 nop + 80002eb8: 00000013 nop + 80002ebc: 00113823 sd ra,16(sp) + 80002ec0: 01013f03 ld t5,16(sp) + 80002ec4: 0daaceb7 lui t4,0xdaac + 80002ec8: bcce8e9b addiw t4,t4,-1076 + 80002ecc: 25df1063 bne t5,t4,8000310c + 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ed4: 00200293 li t0,2 + 80002ed8: fc5216e3 bne tp,t0,80002ea4 + +0000000080002edc : + 80002edc: 00f00193 li gp,15 + 80002ee0: 00000213 li tp,0 + 80002ee4: 0ddab0b7 lui ra,0xddab + 80002ee8: bbc0809b addiw ra,ra,-1092 + 80002eec: 00000013 nop + 80002ef0: 00001117 auipc sp,0x1 + 80002ef4: 11010113 addi sp,sp,272 # 80004000 + 80002ef8: 00113c23 sd ra,24(sp) + 80002efc: 01813f03 ld t5,24(sp) + 80002f00: 0ddabeb7 lui t4,0xddab + 80002f04: bbce8e9b addiw t4,t4,-1092 + 80002f08: 21df1263 bne t5,t4,8000310c + 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f10: 00200293 li t0,2 + 80002f14: fc5218e3 bne tp,t0,80002ee4 + +0000000080002f18 : + 80002f18: 01000193 li gp,16 + 80002f1c: 00000213 li tp,0 + 80002f20: 0cddb0b7 lui ra,0xcddb + 80002f24: abb0809b addiw ra,ra,-1349 + 80002f28: 00000013 nop + 80002f2c: 00001117 auipc sp,0x1 + 80002f30: 0d410113 addi sp,sp,212 # 80004000 + 80002f34: 00000013 nop + 80002f38: 02113023 sd ra,32(sp) + 80002f3c: 02013f03 ld t5,32(sp) + 80002f40: 0cddbeb7 lui t4,0xcddb + 80002f44: abbe8e9b addiw t4,t4,-1349 + 80002f48: 1ddf1263 bne t5,t4,8000310c + 80002f4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f50: 00200293 li t0,2 + 80002f54: fc5216e3 bne tp,t0,80002f20 + +0000000080002f58 : + 80002f58: 01100193 li gp,17 + 80002f5c: 00000213 li tp,0 + 80002f60: 0ccde0b7 lui ra,0xccde + 80002f64: aab0809b addiw ra,ra,-1365 + 80002f68: 00000013 nop + 80002f6c: 00000013 nop + 80002f70: 00001117 auipc sp,0x1 + 80002f74: 09010113 addi sp,sp,144 # 80004000 + 80002f78: 02113423 sd ra,40(sp) + 80002f7c: 02813f03 ld t5,40(sp) + 80002f80: 0ccdeeb7 lui t4,0xccde + 80002f84: aabe8e9b addiw t4,t4,-1365 + 80002f88: 19df1263 bne t5,t4,8000310c + 80002f8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f90: 00200293 li t0,2 + 80002f94: fc5216e3 bne tp,t0,80002f60 + +0000000080002f98 : + 80002f98: 01200193 li gp,18 + 80002f9c: 00000213 li tp,0 + 80002fa0: 00001117 auipc sp,0x1 + 80002fa4: 06010113 addi sp,sp,96 # 80004000 + 80002fa8: 001120b7 lui ra,0x112 + 80002fac: 2330809b addiw ra,ra,563 + 80002fb0: 00113023 sd ra,0(sp) + 80002fb4: 00013f03 ld t5,0(sp) + 80002fb8: 00112eb7 lui t4,0x112 + 80002fbc: 233e8e9b addiw t4,t4,563 + 80002fc0: 15df1663 bne t5,t4,8000310c + 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fc8: 00200293 li t0,2 + 80002fcc: fc521ae3 bne tp,t0,80002fa0 + +0000000080002fd0 : + 80002fd0: 01300193 li gp,19 + 80002fd4: 00000213 li tp,0 + 80002fd8: 00001117 auipc sp,0x1 + 80002fdc: 02810113 addi sp,sp,40 # 80004000 + 80002fe0: 300110b7 lui ra,0x30011 + 80002fe4: 2230809b addiw ra,ra,547 + 80002fe8: 00000013 nop + 80002fec: 00113423 sd ra,8(sp) + 80002ff0: 00813f03 ld t5,8(sp) + 80002ff4: 30011eb7 lui t4,0x30011 + 80002ff8: 223e8e9b addiw t4,t4,547 + 80002ffc: 11df1863 bne t5,t4,8000310c + 80003000: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003004: 00200293 li t0,2 + 80003008: fc5218e3 bne tp,t0,80002fd8 + +000000008000300c : + 8000300c: 01400193 li gp,20 + 80003010: 00000213 li tp,0 + 80003014: 00001117 auipc sp,0x1 + 80003018: fec10113 addi sp,sp,-20 # 80004000 + 8000301c: 330010b7 lui ra,0x33001 + 80003020: 1220809b addiw ra,ra,290 + 80003024: 00000013 nop + 80003028: 00000013 nop + 8000302c: 00113823 sd ra,16(sp) + 80003030: 01013f03 ld t5,16(sp) + 80003034: 33001eb7 lui t4,0x33001 + 80003038: 122e8e9b addiw t4,t4,290 + 8000303c: 0ddf1863 bne t5,t4,8000310c + 80003040: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003044: 00200293 li t0,2 + 80003048: fc5216e3 bne tp,t0,80003014 + +000000008000304c : + 8000304c: 01500193 li gp,21 + 80003050: 00000213 li tp,0 + 80003054: 00001117 auipc sp,0x1 + 80003058: fac10113 addi sp,sp,-84 # 80004000 + 8000305c: 00000013 nop + 80003060: 233000b7 lui ra,0x23300 + 80003064: 1120809b addiw ra,ra,274 + 80003068: 00113c23 sd ra,24(sp) + 8000306c: 01813f03 ld t5,24(sp) + 80003070: 23300eb7 lui t4,0x23300 + 80003074: 112e8e9b addiw t4,t4,274 + 80003078: 09df1a63 bne t5,t4,8000310c + 8000307c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003080: 00200293 li t0,2 + 80003084: fc5218e3 bne tp,t0,80003054 + +0000000080003088 : + 80003088: 01600193 li gp,22 + 8000308c: 00000213 li tp,0 + 80003090: 00001117 auipc sp,0x1 + 80003094: f7010113 addi sp,sp,-144 # 80004000 + 80003098: 00000013 nop + 8000309c: 223300b7 lui ra,0x22330 + 800030a0: 0110809b addiw ra,ra,17 + 800030a4: 00000013 nop + 800030a8: 02113023 sd ra,32(sp) + 800030ac: 02013f03 ld t5,32(sp) + 800030b0: 22330eb7 lui t4,0x22330 + 800030b4: 011e8e9b addiw t4,t4,17 + 800030b8: 05df1a63 bne t5,t4,8000310c + 800030bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800030c0: 00200293 li t0,2 + 800030c4: fc5216e3 bne tp,t0,80003090 + +00000000800030c8 : + 800030c8: 01700193 li gp,23 + 800030cc: 00000213 li tp,0 + 800030d0: 00001117 auipc sp,0x1 + 800030d4: f3010113 addi sp,sp,-208 # 80004000 + 800030d8: 00000013 nop + 800030dc: 00000013 nop + 800030e0: 122330b7 lui ra,0x12233 + 800030e4: 0010809b addiw ra,ra,1 + 800030e8: 02113423 sd ra,40(sp) + 800030ec: 02813f03 ld t5,40(sp) + 800030f0: 12233eb7 lui t4,0x12233 + 800030f4: 001e8e9b addiw t4,t4,1 + 800030f8: 01df1a63 bne t5,t4,8000310c + 800030fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003100: 00200293 li t0,2 + 80003104: fc5216e3 bne tp,t0,800030d0 + 80003108: 00301a63 bne zero,gp,8000311c + +000000008000310c : + 8000310c: 00119513 slli a0,gp,0x1 + 80003110: 00050063 beqz a0,80003110 + 80003114: 00156513 ori a0,a0,1 + 80003118: 00000073 ecall + +000000008000311c : + 8000311c: 00100513 li a0,1 + 80003120: 00000073 ecall + 80003124: c0001073 unimp + +Disassembly of section .data: + +0000000080004000 : + 80004000: deadbeef jal t4,7ffdf5ea <_start-0x20a16> + 80004004: deadbeef jal t4,7ffdf5ee <_start-0x20a12> + +0000000080004008 : + 80004008: deadbeef jal t4,7ffdf5f2 <_start-0x20a0e> + 8000400c: deadbeef jal t4,7ffdf5f6 <_start-0x20a0a> + +0000000080004010 : + 80004010: deadbeef jal t4,7ffdf5fa <_start-0x20a06> + 80004014: deadbeef jal t4,7ffdf5fe <_start-0x20a02> + +0000000080004018 : + 80004018: deadbeef jal t4,7ffdf602 <_start-0x209fe> + 8000401c: deadbeef jal t4,7ffdf606 <_start-0x209fa> + +0000000080004020 : + 80004020: deadbeef jal t4,7ffdf60a <_start-0x209f6> + 80004024: deadbeef jal t4,7ffdf60e <_start-0x209f2> + +0000000080004028 : + 80004028: deadbeef jal t4,7ffdf612 <_start-0x209ee> + 8000402c: deadbeef jal t4,7ffdf616 <_start-0x209ea> + +0000000080004030 : + 80004030: deadbeef jal t4,7ffdf61a <_start-0x209e6> + 80004034: deadbeef jal t4,7ffdf61e <_start-0x209e2> + +0000000080004038 : + 80004038: deadbeef jal t4,7ffdf622 <_start-0x209de> + 8000403c: deadbeef jal t4,7ffdf626 <_start-0x209da> + +0000000080004040 : + 80004040: deadbeef jal t4,7ffdf62a <_start-0x209d6> + 80004044: deadbeef jal t4,7ffdf62e <_start-0x209d2> + +0000000080004048 : + 80004048: deadbeef jal t4,7ffdf632 <_start-0x209ce> + 8000404c: deadbeef jal t4,7ffdf636 <_start-0x209ca> diff --git a/test/riscv/tests/rv64ui-v-sd.elf b/test/riscv/tests/rv64ui-v-sd.elf new file mode 100644 index 00000000..b1660db0 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sd.elf differ diff --git a/test/riscv/tests/rv64ui-v-sh.dump b/test/riscv/tests/rv64ui-v-sh.dump new file mode 100644 index 00000000..62862d9e --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sh.dump @@ -0,0 +1,1200 @@ + +rv64ui-v-sh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000a117 auipc sp,0xa + 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00003617 auipc a2,0x3 + 80002318: cec60613 addi a2,a2,-788 # 80005000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00007797 auipc a5,0x7 + 80002334: 4b878793 addi a5,a5,1208 # 800097e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00007717 auipc a4,0x7 + 80002348: 49c70713 addi a4,a4,1180 # 800097e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00007897 auipc a7,0x7 + 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00007797 auipc a5,0x7 + 80002384: 07078793 addi a5,a5,112 # 800093f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00007797 auipc a5,0x7 + 80002448: 3807be23 sd zero,924(a5) # 800097e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b0868693 addi a3,a3,-1272 # 80002f60 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b3c60613 addi a2,a2,-1220 # 80002ff0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b0460613 addi a2,a2,-1276 # 80003008 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: a5468693 addi a3,a3,-1452 # 80002fa8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: a7068693 addi a3,a3,-1424 # 800030e0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 9f060613 addi a2,a2,-1552 # 800030b8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00007d17 auipc s10,0x7 + 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 + 80002724: 00003b97 auipc s7,0x3 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00007a17 auipc s4,0x7 + 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00007717 auipc a4,0x7 + 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00007717 auipc a4,0x7 + 800027d4: 00f73823 sd a5,16(a4) # 800097e0 + 800027d8: 00007717 auipc a4,0x7 + 800027dc: 00f73823 sd a5,16(a4) # 800097e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 92468693 addi a3,a3,-1756 # 80003110 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 84468693 addi a3,a3,-1980 # 80003080 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 7d468693 addi a3,a3,2004 # 80003048 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00003697 auipc a3,0x3 + 800028e0: 72468693 addi a3,a3,1828 # 80006000 + 800028e4: 00004717 auipc a4,0x4 + 800028e8: 71c70713 addi a4,a4,1820 # 80007000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00005797 auipc a5,0x5 + 800028f8: 70c78793 addi a5,a5,1804 # 80008000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00002897 auipc a7,0x2 + 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00003697 auipc a3,0x3 + 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00002617 auipc a2,0x2 + 80002938: 6cc60613 addi a2,a2,1740 # 80005000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00005697 auipc a3,0x5 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 + 8000294c: 00003717 auipc a4,0x3 + 80002950: 6af73a23 sd a5,1716(a4) # 80006000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00006697 auipc a3,0x6 + 800029c0: 64468693 addi a3,a3,1604 # 80009000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00007617 auipc a2,0x7 + 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 + 800029d4: 00007797 auipc a5,0x7 + 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 + 800029dc: 00007317 auipc t1,0x7 + 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 + 800029e4: 03300793 li a5,51 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00007797 auipc a5,0x7 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0adbd7b7 lui a5,0xadbd + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 91078793 addi a5,a5,-1776 # adbc910 <_start-0x752436f0> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00001097 auipc ra,0x1 + 80002acc: 53808093 addi ra,ra,1336 # 80004000 + 80002ad0: 0aa00113 li sp,170 + 80002ad4: 00209023 sh sp,0(ra) + 80002ad8: 00009f03 lh t5,0(ra) + 80002adc: 0aa00e93 li t4,170 + 80002ae0: 00200193 li gp,2 + 80002ae4: 45df1e63 bne t5,t4,80002f40 + +0000000080002ae8 : + 80002ae8: 00001097 auipc ra,0x1 + 80002aec: 51808093 addi ra,ra,1304 # 80004000 + 80002af0: ffffb137 lui sp,0xffffb + 80002af4: a001011b addiw sp,sp,-1536 + 80002af8: 00209123 sh sp,2(ra) + 80002afc: 00209f03 lh t5,2(ra) + 80002b00: ffffbeb7 lui t4,0xffffb + 80002b04: a00e8e9b addiw t4,t4,-1536 + 80002b08: 00300193 li gp,3 + 80002b0c: 43df1a63 bne t5,t4,80002f40 + +0000000080002b10 : + 80002b10: 00001097 auipc ra,0x1 + 80002b14: 4f008093 addi ra,ra,1264 # 80004000 + 80002b18: beef1137 lui sp,0xbeef1 + 80002b1c: aa01011b addiw sp,sp,-1376 + 80002b20: 00209223 sh sp,4(ra) + 80002b24: 0040af03 lw t5,4(ra) + 80002b28: beef1eb7 lui t4,0xbeef1 + 80002b2c: aa0e8e9b addiw t4,t4,-1376 + 80002b30: 00400193 li gp,4 + 80002b34: 41df1663 bne t5,t4,80002f40 + +0000000080002b38 : + 80002b38: 00001097 auipc ra,0x1 + 80002b3c: 4c808093 addi ra,ra,1224 # 80004000 + 80002b40: ffffa137 lui sp,0xffffa + 80002b44: 00a1011b addiw sp,sp,10 + 80002b48: 00209323 sh sp,6(ra) + 80002b4c: 00609f03 lh t5,6(ra) + 80002b50: ffffaeb7 lui t4,0xffffa + 80002b54: 00ae8e9b addiw t4,t4,10 + 80002b58: 00500193 li gp,5 + 80002b5c: 3fdf1263 bne t5,t4,80002f40 + +0000000080002b60 : + 80002b60: 00001097 auipc ra,0x1 + 80002b64: 4ae08093 addi ra,ra,1198 # 8000400e + 80002b68: 0aa00113 li sp,170 + 80002b6c: fe209d23 sh sp,-6(ra) + 80002b70: ffa09f03 lh t5,-6(ra) + 80002b74: 0aa00e93 li t4,170 + 80002b78: 00600193 li gp,6 + 80002b7c: 3ddf1263 bne t5,t4,80002f40 + +0000000080002b80 : + 80002b80: 00001097 auipc ra,0x1 + 80002b84: 48e08093 addi ra,ra,1166 # 8000400e + 80002b88: ffffb137 lui sp,0xffffb + 80002b8c: a001011b addiw sp,sp,-1536 + 80002b90: fe209e23 sh sp,-4(ra) + 80002b94: ffc09f03 lh t5,-4(ra) + 80002b98: ffffbeb7 lui t4,0xffffb + 80002b9c: a00e8e9b addiw t4,t4,-1536 + 80002ba0: 00700193 li gp,7 + 80002ba4: 39df1e63 bne t5,t4,80002f40 + +0000000080002ba8 : + 80002ba8: 00001097 auipc ra,0x1 + 80002bac: 46608093 addi ra,ra,1126 # 8000400e + 80002bb0: 00001137 lui sp,0x1 + 80002bb4: aa01011b addiw sp,sp,-1376 + 80002bb8: fe209f23 sh sp,-2(ra) + 80002bbc: ffe09f03 lh t5,-2(ra) + 80002bc0: 00001eb7 lui t4,0x1 + 80002bc4: aa0e8e9b addiw t4,t4,-1376 + 80002bc8: 00800193 li gp,8 + 80002bcc: 37df1a63 bne t5,t4,80002f40 + +0000000080002bd0 : + 80002bd0: 00001097 auipc ra,0x1 + 80002bd4: 43e08093 addi ra,ra,1086 # 8000400e + 80002bd8: ffffa137 lui sp,0xffffa + 80002bdc: 00a1011b addiw sp,sp,10 + 80002be0: 00209023 sh sp,0(ra) + 80002be4: 00009f03 lh t5,0(ra) + 80002be8: ffffaeb7 lui t4,0xffffa + 80002bec: 00ae8e9b addiw t4,t4,10 + 80002bf0: 00900193 li gp,9 + 80002bf4: 35df1663 bne t5,t4,80002f40 + +0000000080002bf8 : + 80002bf8: 00001097 auipc ra,0x1 + 80002bfc: 41808093 addi ra,ra,1048 # 80004010 + 80002c00: 12345137 lui sp,0x12345 + 80002c04: 6781011b addiw sp,sp,1656 + 80002c08: fe008213 addi tp,ra,-32 + 80002c0c: 02221023 sh sp,32(tp) # 20 <_start-0x7fffffe0> + 80002c10: 00009283 lh t0,0(ra) + 80002c14: 00005eb7 lui t4,0x5 + 80002c18: 678e8e9b addiw t4,t4,1656 + 80002c1c: 00a00193 li gp,10 + 80002c20: 33d29063 bne t0,t4,80002f40 + +0000000080002c24 : + 80002c24: 00001097 auipc ra,0x1 + 80002c28: 3ec08093 addi ra,ra,1004 # 80004010 + 80002c2c: 00003137 lui sp,0x3 + 80002c30: 0981011b addiw sp,sp,152 + 80002c34: ffb08093 addi ra,ra,-5 + 80002c38: 002093a3 sh sp,7(ra) + 80002c3c: 00001217 auipc tp,0x1 + 80002c40: 3d620213 addi tp,tp,982 # 80004012 + 80002c44: 00021283 lh t0,0(tp) # 0 <_start-0x80000000> + 80002c48: 00003eb7 lui t4,0x3 + 80002c4c: 098e8e9b addiw t4,t4,152 + 80002c50: 00b00193 li gp,11 + 80002c54: 2fd29663 bne t0,t4,80002f40 + +0000000080002c58 : + 80002c58: 00c00193 li gp,12 + 80002c5c: 00000213 li tp,0 + 80002c60: ffffd0b7 lui ra,0xffffd + 80002c64: cdd0809b addiw ra,ra,-803 + 80002c68: 00001117 auipc sp,0x1 + 80002c6c: 39810113 addi sp,sp,920 # 80004000 + 80002c70: 00111023 sh ra,0(sp) + 80002c74: 00011f03 lh t5,0(sp) + 80002c78: ffffdeb7 lui t4,0xffffd + 80002c7c: cdde8e9b addiw t4,t4,-803 + 80002c80: 2ddf1063 bne t5,t4,80002f40 + 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c88: 00200293 li t0,2 + 80002c8c: fc521ae3 bne tp,t0,80002c60 + +0000000080002c90 : + 80002c90: 00d00193 li gp,13 + 80002c94: 00000213 li tp,0 + 80002c98: ffffc0b7 lui ra,0xffffc + 80002c9c: ccd0809b addiw ra,ra,-819 + 80002ca0: 00001117 auipc sp,0x1 + 80002ca4: 36010113 addi sp,sp,864 # 80004000 + 80002ca8: 00000013 nop + 80002cac: 00111123 sh ra,2(sp) + 80002cb0: 00211f03 lh t5,2(sp) + 80002cb4: ffffceb7 lui t4,0xffffc + 80002cb8: ccde8e9b addiw t4,t4,-819 + 80002cbc: 29df1263 bne t5,t4,80002f40 + 80002cc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc4: 00200293 li t0,2 + 80002cc8: fc5218e3 bne tp,t0,80002c98 + +0000000080002ccc : + 80002ccc: 00e00193 li gp,14 + 80002cd0: 00000213 li tp,0 + 80002cd4: ffffc0b7 lui ra,0xffffc + 80002cd8: bcc0809b addiw ra,ra,-1076 + 80002cdc: 00001117 auipc sp,0x1 + 80002ce0: 32410113 addi sp,sp,804 # 80004000 + 80002ce4: 00000013 nop + 80002ce8: 00000013 nop + 80002cec: 00111223 sh ra,4(sp) + 80002cf0: 00411f03 lh t5,4(sp) + 80002cf4: ffffceb7 lui t4,0xffffc + 80002cf8: bcce8e9b addiw t4,t4,-1076 + 80002cfc: 25df1263 bne t5,t4,80002f40 + 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d04: 00200293 li t0,2 + 80002d08: fc5216e3 bne tp,t0,80002cd4 + +0000000080002d0c : + 80002d0c: 00f00193 li gp,15 + 80002d10: 00000213 li tp,0 + 80002d14: ffffb0b7 lui ra,0xffffb + 80002d18: bbc0809b addiw ra,ra,-1092 + 80002d1c: 00000013 nop + 80002d20: 00001117 auipc sp,0x1 + 80002d24: 2e010113 addi sp,sp,736 # 80004000 + 80002d28: 00111323 sh ra,6(sp) + 80002d2c: 00611f03 lh t5,6(sp) + 80002d30: ffffbeb7 lui t4,0xffffb + 80002d34: bbce8e9b addiw t4,t4,-1092 + 80002d38: 21df1463 bne t5,t4,80002f40 + 80002d3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d40: 00200293 li t0,2 + 80002d44: fc5218e3 bne tp,t0,80002d14 + +0000000080002d48 : + 80002d48: 01000193 li gp,16 + 80002d4c: 00000213 li tp,0 + 80002d50: ffffb0b7 lui ra,0xffffb + 80002d54: abb0809b addiw ra,ra,-1349 + 80002d58: 00000013 nop + 80002d5c: 00001117 auipc sp,0x1 + 80002d60: 2a410113 addi sp,sp,676 # 80004000 + 80002d64: 00000013 nop + 80002d68: 00111423 sh ra,8(sp) + 80002d6c: 00811f03 lh t5,8(sp) + 80002d70: ffffbeb7 lui t4,0xffffb + 80002d74: abbe8e9b addiw t4,t4,-1349 + 80002d78: 1ddf1463 bne t5,t4,80002f40 + 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d80: 00200293 li t0,2 + 80002d84: fc5216e3 bne tp,t0,80002d50 + +0000000080002d88 : + 80002d88: 01100193 li gp,17 + 80002d8c: 00000213 li tp,0 + 80002d90: ffffe0b7 lui ra,0xffffe + 80002d94: aab0809b addiw ra,ra,-1365 + 80002d98: 00000013 nop + 80002d9c: 00000013 nop + 80002da0: 00001117 auipc sp,0x1 + 80002da4: 26010113 addi sp,sp,608 # 80004000 + 80002da8: 00111523 sh ra,10(sp) + 80002dac: 00a11f03 lh t5,10(sp) + 80002db0: ffffeeb7 lui t4,0xffffe + 80002db4: aabe8e9b addiw t4,t4,-1365 + 80002db8: 19df1463 bne t5,t4,80002f40 + 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dc0: 00200293 li t0,2 + 80002dc4: fc5216e3 bne tp,t0,80002d90 + +0000000080002dc8 : + 80002dc8: 01200193 li gp,18 + 80002dcc: 00000213 li tp,0 + 80002dd0: 00001117 auipc sp,0x1 + 80002dd4: 23010113 addi sp,sp,560 # 80004000 + 80002dd8: 000020b7 lui ra,0x2 + 80002ddc: 2330809b addiw ra,ra,563 + 80002de0: 00111023 sh ra,0(sp) + 80002de4: 00011f03 lh t5,0(sp) + 80002de8: 00002eb7 lui t4,0x2 + 80002dec: 233e8e9b addiw t4,t4,563 + 80002df0: 15df1863 bne t5,t4,80002f40 + 80002df4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002df8: 00200293 li t0,2 + 80002dfc: fc521ae3 bne tp,t0,80002dd0 + +0000000080002e00 : + 80002e00: 01300193 li gp,19 + 80002e04: 00000213 li tp,0 + 80002e08: 00001117 auipc sp,0x1 + 80002e0c: 1f810113 addi sp,sp,504 # 80004000 + 80002e10: 000010b7 lui ra,0x1 + 80002e14: 2230809b addiw ra,ra,547 + 80002e18: 00000013 nop + 80002e1c: 00111123 sh ra,2(sp) + 80002e20: 00211f03 lh t5,2(sp) + 80002e24: 00001eb7 lui t4,0x1 + 80002e28: 223e8e9b addiw t4,t4,547 + 80002e2c: 11df1a63 bne t5,t4,80002f40 + 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e34: 00200293 li t0,2 + 80002e38: fc5218e3 bne tp,t0,80002e08 + +0000000080002e3c : + 80002e3c: 01400193 li gp,20 + 80002e40: 00000213 li tp,0 + 80002e44: 00001117 auipc sp,0x1 + 80002e48: 1bc10113 addi sp,sp,444 # 80004000 + 80002e4c: 000010b7 lui ra,0x1 + 80002e50: 1220809b addiw ra,ra,290 + 80002e54: 00000013 nop + 80002e58: 00000013 nop + 80002e5c: 00111223 sh ra,4(sp) + 80002e60: 00411f03 lh t5,4(sp) + 80002e64: 00001eb7 lui t4,0x1 + 80002e68: 122e8e9b addiw t4,t4,290 + 80002e6c: 0ddf1a63 bne t5,t4,80002f40 + 80002e70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e74: 00200293 li t0,2 + 80002e78: fc5216e3 bne tp,t0,80002e44 + +0000000080002e7c : + 80002e7c: 01500193 li gp,21 + 80002e80: 00000213 li tp,0 + 80002e84: 00001117 auipc sp,0x1 + 80002e88: 17c10113 addi sp,sp,380 # 80004000 + 80002e8c: 00000013 nop + 80002e90: 11200093 li ra,274 + 80002e94: 00111323 sh ra,6(sp) + 80002e98: 00611f03 lh t5,6(sp) + 80002e9c: 11200e93 li t4,274 + 80002ea0: 0bdf1063 bne t5,t4,80002f40 + 80002ea4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea8: 00200293 li t0,2 + 80002eac: fc521ce3 bne tp,t0,80002e84 + +0000000080002eb0 : + 80002eb0: 01600193 li gp,22 + 80002eb4: 00000213 li tp,0 + 80002eb8: 00001117 auipc sp,0x1 + 80002ebc: 14810113 addi sp,sp,328 # 80004000 + 80002ec0: 00000013 nop + 80002ec4: 01100093 li ra,17 + 80002ec8: 00000013 nop + 80002ecc: 00111423 sh ra,8(sp) + 80002ed0: 00811f03 lh t5,8(sp) + 80002ed4: 01100e93 li t4,17 + 80002ed8: 07df1463 bne t5,t4,80002f40 + 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee0: 00200293 li t0,2 + 80002ee4: fc521ae3 bne tp,t0,80002eb8 + +0000000080002ee8 : + 80002ee8: 01700193 li gp,23 + 80002eec: 00000213 li tp,0 + 80002ef0: 00001117 auipc sp,0x1 + 80002ef4: 11010113 addi sp,sp,272 # 80004000 + 80002ef8: 00000013 nop + 80002efc: 00000013 nop + 80002f00: 000030b7 lui ra,0x3 + 80002f04: 0010809b addiw ra,ra,1 + 80002f08: 00111523 sh ra,10(sp) + 80002f0c: 00a11f03 lh t5,10(sp) + 80002f10: 00003eb7 lui t4,0x3 + 80002f14: 001e8e9b addiw t4,t4,1 + 80002f18: 03df1463 bne t5,t4,80002f40 + 80002f1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f20: 00200293 li t0,2 + 80002f24: fc5216e3 bne tp,t0,80002ef0 + 80002f28: 0000c537 lui a0,0xc + 80002f2c: eef5051b addiw a0,a0,-273 + 80002f30: 00001597 auipc a1,0x1 + 80002f34: 0d058593 addi a1,a1,208 # 80004000 + 80002f38: 00a59323 sh a0,6(a1) + 80002f3c: 00301a63 bne zero,gp,80002f50 + +0000000080002f40 : + 80002f40: 00119513 slli a0,gp,0x1 + 80002f44: 00050063 beqz a0,80002f44 + 80002f48: 00156513 ori a0,a0,1 + 80002f4c: 00000073 ecall + +0000000080002f50 : + 80002f50: 00100513 li a0,1 + 80002f54: 00000073 ecall + 80002f58: c0001073 unimp + +Disassembly of section .data: + +0000000080004000 : + 80004000: jal t4,7ffff3ee <_start-0xc12> + +0000000080004002 : + 80004002: jal t4,7ffff3f0 <_start-0xc10> + +0000000080004004 : + 80004004: jal t4,7ffff3f2 <_start-0xc0e> + +0000000080004006 : + 80004006: jal t4,7ffff3f4 <_start-0xc0c> + +0000000080004008 : + 80004008: jal t4,7ffff3f6 <_start-0xc0a> + +000000008000400a : + 8000400a: jal t4,7ffff3f8 <_start-0xc08> + +000000008000400c : + 8000400c: jal t4,7ffff3fa <_start-0xc06> + +000000008000400e : + 8000400e: jal t4,7ffff3fc <_start-0xc04> + +0000000080004010 : + 80004010: jal t4,7ffff3fe <_start-0xc02> + +0000000080004012 : + 80004012: jal t4,8000f012 <_end+0x5822> diff --git a/test/riscv/tests/rv64ui-v-sh.elf b/test/riscv/tests/rv64ui-v-sh.elf new file mode 100644 index 00000000..a3a67da2 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sh.elf differ diff --git a/test/riscv/tests/rv64ui-v-simple.dump b/test/riscv/tests/rv64ui-v-simple.dump new file mode 100644 index 00000000..0c3cc1cc --- /dev/null +++ b/test/riscv/tests/rv64ui-v-simple.dump @@ -0,0 +1,832 @@ + +rv64ui-v-simple: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 68068693 addi a3,a3,1664 # 80002ad8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 6b460613 addi a2,a2,1716 # 80002b68 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 67c60613 addi a2,a2,1660 # 80002b80 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 5cc68693 addi a3,a3,1484 # 80002b20 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 5e868693 addi a3,a3,1512 # 80002c58 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 56860613 addi a2,a2,1384 # 80002c30 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 49c68693 addi a3,a3,1180 # 80002c88 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 3bc68693 addi a3,a3,956 # 80002bf8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 34c68693 addi a3,a3,844 # 80002bc0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03000793 li a5,48 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 07a657b7 lui a5,0x7a65 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: bab78793 addi a5,a5,-1109 # 7a64bab <_start-0x7859b455> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00100513 li a0,1 + 80002acc: 00000073 ecall + 80002ad0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-simple.elf b/test/riscv/tests/rv64ui-v-simple.elf new file mode 100644 index 00000000..04140b00 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-simple.elf differ diff --git a/test/riscv/tests/rv64ui-v-sll.dump b/test/riscv/tests/rv64ui-v-sll.dump new file mode 100644 index 00000000..6b4b00b0 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sll.dump @@ -0,0 +1,1315 @@ + +rv64ui-v-sll: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c9868693 addi a3,a3,-872 # 800030f0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: ccc60613 addi a2,a2,-820 # 80003180 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c9460613 addi a2,a2,-876 # 80003198 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: be468693 addi a3,a3,-1052 # 80003138 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: c0068693 addi a3,a3,-1024 # 80003270 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b8060613 addi a2,a2,-1152 # 80003248 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: ab468693 addi a3,a3,-1356 # 800032a0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 9d468693 addi a3,a3,-1580 # 80003210 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 96468693 addi a3,a3,-1692 # 800031d8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02b00793 li a5,43 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 063c27b7 lui a5,0x63c2 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 9ad78793 addi a5,a5,-1619 # 63c19ad <_start-0x79c3e653> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00100093 li ra,1 + 80002acc: 00000113 li sp,0 + 80002ad0: 00209f33 sll t5,ra,sp + 80002ad4: 00100e93 li t4,1 + 80002ad8: 00200193 li gp,2 + 80002adc: 5fdf1c63 bne t5,t4,800030d4 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 00209f33 sll t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 5fdf1063 bne t5,t4,800030d4 + +0000000080002af8 : + 80002af8: 00100093 li ra,1 + 80002afc: 00700113 li sp,7 + 80002b00: 00209f33 sll t5,ra,sp + 80002b04: 08000e93 li t4,128 + 80002b08: 00400193 li gp,4 + 80002b0c: 5ddf1463 bne t5,t4,800030d4 + +0000000080002b10 : + 80002b10: 00100093 li ra,1 + 80002b14: 00e00113 li sp,14 + 80002b18: 00209f33 sll t5,ra,sp + 80002b1c: 00004eb7 lui t4,0x4 + 80002b20: 00500193 li gp,5 + 80002b24: 5bdf1863 bne t5,t4,800030d4 + +0000000080002b28 : + 80002b28: 00100093 li ra,1 + 80002b2c: 01f00113 li sp,31 + 80002b30: 00209f33 sll t5,ra,sp + 80002b34: 00100e9b addiw t4,zero,1 + 80002b38: 01fe9e93 slli t4,t4,0x1f + 80002b3c: 00600193 li gp,6 + 80002b40: 59df1a63 bne t5,t4,800030d4 + +0000000080002b44 : + 80002b44: fff00093 li ra,-1 + 80002b48: 00000113 li sp,0 + 80002b4c: 00209f33 sll t5,ra,sp + 80002b50: fff00e93 li t4,-1 + 80002b54: 00700193 li gp,7 + 80002b58: 57df1e63 bne t5,t4,800030d4 + +0000000080002b5c : + 80002b5c: fff00093 li ra,-1 + 80002b60: 00100113 li sp,1 + 80002b64: 00209f33 sll t5,ra,sp + 80002b68: ffe00e93 li t4,-2 + 80002b6c: 00800193 li gp,8 + 80002b70: 57df1263 bne t5,t4,800030d4 + +0000000080002b74 : + 80002b74: fff00093 li ra,-1 + 80002b78: 00700113 li sp,7 + 80002b7c: 00209f33 sll t5,ra,sp + 80002b80: f8000e93 li t4,-128 + 80002b84: 00900193 li gp,9 + 80002b88: 55df1663 bne t5,t4,800030d4 + +0000000080002b8c : + 80002b8c: fff00093 li ra,-1 + 80002b90: 00e00113 li sp,14 + 80002b94: 00209f33 sll t5,ra,sp + 80002b98: ffffceb7 lui t4,0xffffc + 80002b9c: 00a00193 li gp,10 + 80002ba0: 53df1a63 bne t5,t4,800030d4 + +0000000080002ba4 : + 80002ba4: fff00093 li ra,-1 + 80002ba8: 01f00113 li sp,31 + 80002bac: 00209f33 sll t5,ra,sp + 80002bb0: 80000eb7 lui t4,0x80000 + 80002bb4: 00b00193 li gp,11 + 80002bb8: 51df1e63 bne t5,t4,800030d4 + +0000000080002bbc : + 80002bbc: 212120b7 lui ra,0x21212 + 80002bc0: 1210809b addiw ra,ra,289 + 80002bc4: 00000113 li sp,0 + 80002bc8: 00209f33 sll t5,ra,sp + 80002bcc: 21212eb7 lui t4,0x21212 + 80002bd0: 121e8e9b addiw t4,t4,289 + 80002bd4: 00c00193 li gp,12 + 80002bd8: 4fdf1e63 bne t5,t4,800030d4 + +0000000080002bdc : + 80002bdc: 212120b7 lui ra,0x21212 + 80002be0: 1210809b addiw ra,ra,289 + 80002be4: 00100113 li sp,1 + 80002be8: 00209f33 sll t5,ra,sp + 80002bec: 42424eb7 lui t4,0x42424 + 80002bf0: 242e8e9b addiw t4,t4,578 + 80002bf4: 00d00193 li gp,13 + 80002bf8: 4ddf1e63 bne t5,t4,800030d4 + +0000000080002bfc : + 80002bfc: 212120b7 lui ra,0x21212 + 80002c00: 1210809b addiw ra,ra,289 + 80002c04: 00700113 li sp,7 + 80002c08: 00209f33 sll t5,ra,sp + 80002c0c: 01091eb7 lui t4,0x1091 + 80002c10: 909e8e9b addiw t4,t4,-1783 + 80002c14: 00ce9e93 slli t4,t4,0xc + 80002c18: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 80002c1c: 00e00193 li gp,14 + 80002c20: 4bdf1a63 bne t5,t4,800030d4 + +0000000080002c24 : + 80002c24: 212120b7 lui ra,0x21212 + 80002c28: 1210809b addiw ra,ra,289 + 80002c2c: 00e00113 li sp,14 + 80002c30: 00209f33 sll t5,ra,sp + 80002c34: 21212eb7 lui t4,0x21212 + 80002c38: 121e8e9b addiw t4,t4,289 + 80002c3c: 00ee9e93 slli t4,t4,0xe + 80002c40: 00f00193 li gp,15 + 80002c44: 49df1863 bne t5,t4,800030d4 + +0000000080002c48 : + 80002c48: 212120b7 lui ra,0x21212 + 80002c4c: 1210809b addiw ra,ra,289 + 80002c50: 01f00113 li sp,31 + 80002c54: 00209f33 sll t5,ra,sp + 80002c58: 21212eb7 lui t4,0x21212 + 80002c5c: 121e8e9b addiw t4,t4,289 + 80002c60: 01fe9e93 slli t4,t4,0x1f + 80002c64: 01000193 li gp,16 + 80002c68: 47df1663 bne t5,t4,800030d4 + +0000000080002c6c : + 80002c6c: 212120b7 lui ra,0x21212 + 80002c70: 1210809b addiw ra,ra,289 + 80002c74: fc000113 li sp,-64 + 80002c78: 00209f33 sll t5,ra,sp + 80002c7c: 21212eb7 lui t4,0x21212 + 80002c80: 121e8e9b addiw t4,t4,289 + 80002c84: 01100193 li gp,17 + 80002c88: 45df1663 bne t5,t4,800030d4 + +0000000080002c8c : + 80002c8c: 212120b7 lui ra,0x21212 + 80002c90: 1210809b addiw ra,ra,289 + 80002c94: fc100113 li sp,-63 + 80002c98: 00209f33 sll t5,ra,sp + 80002c9c: 42424eb7 lui t4,0x42424 + 80002ca0: 242e8e9b addiw t4,t4,578 + 80002ca4: 01200193 li gp,18 + 80002ca8: 43df1663 bne t5,t4,800030d4 + +0000000080002cac : + 80002cac: 212120b7 lui ra,0x21212 + 80002cb0: 1210809b addiw ra,ra,289 + 80002cb4: fc700113 li sp,-57 + 80002cb8: 00209f33 sll t5,ra,sp + 80002cbc: 01091eb7 lui t4,0x1091 + 80002cc0: 909e8e9b addiw t4,t4,-1783 + 80002cc4: 00ce9e93 slli t4,t4,0xc + 80002cc8: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 80002ccc: 01300193 li gp,19 + 80002cd0: 41df1263 bne t5,t4,800030d4 + +0000000080002cd4 : + 80002cd4: 212120b7 lui ra,0x21212 + 80002cd8: 1210809b addiw ra,ra,289 + 80002cdc: fce00113 li sp,-50 + 80002ce0: 00209f33 sll t5,ra,sp + 80002ce4: 21212eb7 lui t4,0x21212 + 80002ce8: 121e8e9b addiw t4,t4,289 + 80002cec: 00ee9e93 slli t4,t4,0xe + 80002cf0: 01400193 li gp,20 + 80002cf4: 3fdf1063 bne t5,t4,800030d4 + +0000000080002cf8 : + 80002cf8: 212120b7 lui ra,0x21212 + 80002cfc: 1210809b addiw ra,ra,289 + 80002d00: fff00113 li sp,-1 + 80002d04: 00209f33 sll t5,ra,sp + 80002d08: fff00e9b addiw t4,zero,-1 + 80002d0c: 03fe9e93 slli t4,t4,0x3f + 80002d10: 01500193 li gp,21 + 80002d14: 3ddf1063 bne t5,t4,800030d4 + +0000000080002d18 : + 80002d18: 00100093 li ra,1 + 80002d1c: 03f00113 li sp,63 + 80002d20: 00209f33 sll t5,ra,sp + 80002d24: fff00e9b addiw t4,zero,-1 + 80002d28: 03fe9e93 slli t4,t4,0x3f + 80002d2c: 03200193 li gp,50 + 80002d30: 3bdf1263 bne t5,t4,800030d4 + +0000000080002d34 : + 80002d34: fff00093 li ra,-1 + 80002d38: 02700113 li sp,39 + 80002d3c: 00209f33 sll t5,ra,sp + 80002d40: fff00e9b addiw t4,zero,-1 + 80002d44: 027e9e93 slli t4,t4,0x27 + 80002d48: 03300193 li gp,51 + 80002d4c: 39df1463 bne t5,t4,800030d4 + +0000000080002d50 : + 80002d50: 212120b7 lui ra,0x21212 + 80002d54: 1210809b addiw ra,ra,289 + 80002d58: 02b00113 li sp,43 + 80002d5c: 00209f33 sll t5,ra,sp + 80002d60: 00012eb7 lui t4,0x12 + 80002d64: 121e8e9b addiw t4,t4,289 + 80002d68: 02be9e93 slli t4,t4,0x2b + 80002d6c: 03400193 li gp,52 + 80002d70: 37df1263 bne t5,t4,800030d4 + +0000000080002d74 : + 80002d74: 00100093 li ra,1 + 80002d78: 00700113 li sp,7 + 80002d7c: 002090b3 sll ra,ra,sp + 80002d80: 08000e93 li t4,128 + 80002d84: 01600193 li gp,22 + 80002d88: 35d09663 bne ra,t4,800030d4 + +0000000080002d8c : + 80002d8c: 00100093 li ra,1 + 80002d90: 00e00113 li sp,14 + 80002d94: 00209133 sll sp,ra,sp + 80002d98: 00004eb7 lui t4,0x4 + 80002d9c: 01700193 li gp,23 + 80002da0: 33d11a63 bne sp,t4,800030d4 + +0000000080002da4 : + 80002da4: 00300093 li ra,3 + 80002da8: 001090b3 sll ra,ra,ra + 80002dac: 01800e93 li t4,24 + 80002db0: 01800193 li gp,24 + 80002db4: 33d09063 bne ra,t4,800030d4 + +0000000080002db8 : + 80002db8: 00000213 li tp,0 + 80002dbc: 00100093 li ra,1 + 80002dc0: 00700113 li sp,7 + 80002dc4: 00209f33 sll t5,ra,sp + 80002dc8: 000f0313 mv t1,t5 + 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd0: 00200293 li t0,2 + 80002dd4: fe5214e3 bne tp,t0,80002dbc + 80002dd8: 08000e93 li t4,128 + 80002ddc: 01900193 li gp,25 + 80002de0: 2fd31a63 bne t1,t4,800030d4 + +0000000080002de4 : + 80002de4: 00000213 li tp,0 + 80002de8: 00100093 li ra,1 + 80002dec: 00e00113 li sp,14 + 80002df0: 00209f33 sll t5,ra,sp + 80002df4: 00000013 nop + 80002df8: 000f0313 mv t1,t5 + 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e00: 00200293 li t0,2 + 80002e04: fe5212e3 bne tp,t0,80002de8 + 80002e08: 00004eb7 lui t4,0x4 + 80002e0c: 01a00193 li gp,26 + 80002e10: 2dd31263 bne t1,t4,800030d4 + +0000000080002e14 : + 80002e14: 00000213 li tp,0 + 80002e18: 00100093 li ra,1 + 80002e1c: 01f00113 li sp,31 + 80002e20: 00209f33 sll t5,ra,sp + 80002e24: 00000013 nop + 80002e28: 00000013 nop + 80002e2c: 000f0313 mv t1,t5 + 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e34: 00200293 li t0,2 + 80002e38: fe5210e3 bne tp,t0,80002e18 + 80002e3c: 00100e9b addiw t4,zero,1 + 80002e40: 01fe9e93 slli t4,t4,0x1f + 80002e44: 01b00193 li gp,27 + 80002e48: 29d31663 bne t1,t4,800030d4 + +0000000080002e4c : + 80002e4c: 00000213 li tp,0 + 80002e50: 00100093 li ra,1 + 80002e54: 00700113 li sp,7 + 80002e58: 00209f33 sll t5,ra,sp + 80002e5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e60: 00200293 li t0,2 + 80002e64: fe5216e3 bne tp,t0,80002e50 + 80002e68: 08000e93 li t4,128 + 80002e6c: 01c00193 li gp,28 + 80002e70: 27df1263 bne t5,t4,800030d4 + +0000000080002e74 : + 80002e74: 00000213 li tp,0 + 80002e78: 00100093 li ra,1 + 80002e7c: 00e00113 li sp,14 + 80002e80: 00000013 nop + 80002e84: 00209f33 sll t5,ra,sp + 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e8c: 00200293 li t0,2 + 80002e90: fe5214e3 bne tp,t0,80002e78 + 80002e94: 00004eb7 lui t4,0x4 + 80002e98: 01d00193 li gp,29 + 80002e9c: 23df1c63 bne t5,t4,800030d4 + +0000000080002ea0 : + 80002ea0: 00000213 li tp,0 + 80002ea4: 00100093 li ra,1 + 80002ea8: 01f00113 li sp,31 + 80002eac: 00000013 nop + 80002eb0: 00000013 nop + 80002eb4: 00209f33 sll t5,ra,sp + 80002eb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ebc: 00200293 li t0,2 + 80002ec0: fe5212e3 bne tp,t0,80002ea4 + 80002ec4: 00100e9b addiw t4,zero,1 + 80002ec8: 01fe9e93 slli t4,t4,0x1f + 80002ecc: 01e00193 li gp,30 + 80002ed0: 21df1263 bne t5,t4,800030d4 + +0000000080002ed4 : + 80002ed4: 00000213 li tp,0 + 80002ed8: 00100093 li ra,1 + 80002edc: 00000013 nop + 80002ee0: 00700113 li sp,7 + 80002ee4: 00209f33 sll t5,ra,sp + 80002ee8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eec: 00200293 li t0,2 + 80002ef0: fe5214e3 bne tp,t0,80002ed8 + 80002ef4: 08000e93 li t4,128 + 80002ef8: 01f00193 li gp,31 + 80002efc: 1ddf1c63 bne t5,t4,800030d4 + +0000000080002f00 : + 80002f00: 00000213 li tp,0 + 80002f04: 00100093 li ra,1 + 80002f08: 00000013 nop + 80002f0c: 00e00113 li sp,14 + 80002f10: 00000013 nop + 80002f14: 00209f33 sll t5,ra,sp + 80002f18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f1c: 00200293 li t0,2 + 80002f20: fe5212e3 bne tp,t0,80002f04 + 80002f24: 00004eb7 lui t4,0x4 + 80002f28: 02000193 li gp,32 + 80002f2c: 1bdf1463 bne t5,t4,800030d4 + +0000000080002f30 : + 80002f30: 00000213 li tp,0 + 80002f34: 00100093 li ra,1 + 80002f38: 00000013 nop + 80002f3c: 00000013 nop + 80002f40: 01f00113 li sp,31 + 80002f44: 00209f33 sll t5,ra,sp + 80002f48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f4c: 00200293 li t0,2 + 80002f50: fe5212e3 bne tp,t0,80002f34 + 80002f54: 00100e9b addiw t4,zero,1 + 80002f58: 01fe9e93 slli t4,t4,0x1f + 80002f5c: 02100193 li gp,33 + 80002f60: 17df1a63 bne t5,t4,800030d4 + +0000000080002f64 : + 80002f64: 00000213 li tp,0 + 80002f68: 00700113 li sp,7 + 80002f6c: 00100093 li ra,1 + 80002f70: 00209f33 sll t5,ra,sp + 80002f74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f78: 00200293 li t0,2 + 80002f7c: fe5216e3 bne tp,t0,80002f68 + 80002f80: 08000e93 li t4,128 + 80002f84: 02200193 li gp,34 + 80002f88: 15df1663 bne t5,t4,800030d4 + +0000000080002f8c : + 80002f8c: 00000213 li tp,0 + 80002f90: 00e00113 li sp,14 + 80002f94: 00100093 li ra,1 + 80002f98: 00000013 nop + 80002f9c: 00209f33 sll t5,ra,sp + 80002fa0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fa4: 00200293 li t0,2 + 80002fa8: fe5214e3 bne tp,t0,80002f90 + 80002fac: 00004eb7 lui t4,0x4 + 80002fb0: 02300193 li gp,35 + 80002fb4: 13df1063 bne t5,t4,800030d4 + +0000000080002fb8 : + 80002fb8: 00000213 li tp,0 + 80002fbc: 01f00113 li sp,31 + 80002fc0: 00100093 li ra,1 + 80002fc4: 00000013 nop + 80002fc8: 00000013 nop + 80002fcc: 00209f33 sll t5,ra,sp + 80002fd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fd4: 00200293 li t0,2 + 80002fd8: fe5212e3 bne tp,t0,80002fbc + 80002fdc: 00100e9b addiw t4,zero,1 + 80002fe0: 01fe9e93 slli t4,t4,0x1f + 80002fe4: 02400193 li gp,36 + 80002fe8: 0fdf1663 bne t5,t4,800030d4 + +0000000080002fec : + 80002fec: 00000213 li tp,0 + 80002ff0: 00700113 li sp,7 + 80002ff4: 00000013 nop + 80002ff8: 00100093 li ra,1 + 80002ffc: 00209f33 sll t5,ra,sp + 80003000: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003004: 00200293 li t0,2 + 80003008: fe5214e3 bne tp,t0,80002ff0 + 8000300c: 08000e93 li t4,128 + 80003010: 02500193 li gp,37 + 80003014: 0ddf1063 bne t5,t4,800030d4 + +0000000080003018 : + 80003018: 00000213 li tp,0 + 8000301c: 00e00113 li sp,14 + 80003020: 00000013 nop + 80003024: 00100093 li ra,1 + 80003028: 00000013 nop + 8000302c: 00209f33 sll t5,ra,sp + 80003030: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003034: 00200293 li t0,2 + 80003038: fe5212e3 bne tp,t0,8000301c + 8000303c: 00004eb7 lui t4,0x4 + 80003040: 02600193 li gp,38 + 80003044: 09df1863 bne t5,t4,800030d4 + +0000000080003048 : + 80003048: 00000213 li tp,0 + 8000304c: 01f00113 li sp,31 + 80003050: 00000013 nop + 80003054: 00000013 nop + 80003058: 00100093 li ra,1 + 8000305c: 00209f33 sll t5,ra,sp + 80003060: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003064: 00200293 li t0,2 + 80003068: fe5212e3 bne tp,t0,8000304c + 8000306c: 00100e9b addiw t4,zero,1 + 80003070: 01fe9e93 slli t4,t4,0x1f + 80003074: 02700193 li gp,39 + 80003078: 05df1e63 bne t5,t4,800030d4 + +000000008000307c : + 8000307c: 00f00093 li ra,15 + 80003080: 00101133 sll sp,zero,ra + 80003084: 00000e93 li t4,0 + 80003088: 02800193 li gp,40 + 8000308c: 05d11463 bne sp,t4,800030d4 + +0000000080003090 : + 80003090: 02000093 li ra,32 + 80003094: 00009133 sll sp,ra,zero + 80003098: 02000e93 li t4,32 + 8000309c: 02900193 li gp,41 + 800030a0: 03d11a63 bne sp,t4,800030d4 + +00000000800030a4 : + 800030a4: 000010b3 sll ra,zero,zero + 800030a8: 00000e93 li t4,0 + 800030ac: 02a00193 li gp,42 + 800030b0: 03d09263 bne ra,t4,800030d4 + +00000000800030b4 : + 800030b4: 40000093 li ra,1024 + 800030b8: 00001137 lui sp,0x1 + 800030bc: 8001011b addiw sp,sp,-2048 + 800030c0: 00209033 sll zero,ra,sp + 800030c4: 00000e93 li t4,0 + 800030c8: 02b00193 li gp,43 + 800030cc: 01d01463 bne zero,t4,800030d4 + 800030d0: 00301a63 bne zero,gp,800030e4 + +00000000800030d4 : + 800030d4: 00119513 slli a0,gp,0x1 + 800030d8: 00050063 beqz a0,800030d8 + 800030dc: 00156513 ori a0,a0,1 + 800030e0: 00000073 ecall + +00000000800030e4 : + 800030e4: 00100513 li a0,1 + 800030e8: 00000073 ecall + 800030ec: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sll.elf b/test/riscv/tests/rv64ui-v-sll.elf new file mode 100644 index 00000000..a32b39ed Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sll.elf differ diff --git a/test/riscv/tests/rv64ui-v-slli.dump b/test/riscv/tests/rv64ui-v-slli.dump new file mode 100644 index 00000000..2808442b --- /dev/null +++ b/test/riscv/tests/rv64ui-v-slli.dump @@ -0,0 +1,1082 @@ + +rv64ui-v-slli: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 98868693 addi a3,a3,-1656 # 80002de0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 9bc60613 addi a2,a2,-1604 # 80002e70 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 98460613 addi a2,a2,-1660 # 80002e88 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 8d468693 addi a3,a3,-1836 # 80002e28 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8f068693 addi a3,a3,-1808 # 80002f60 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 87060613 addi a2,a2,-1936 # 80002f38 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 7a468693 addi a3,a3,1956 # 80002f90 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 6c468693 addi a3,a3,1732 # 80002f00 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 65468693 addi a3,a3,1620 # 80002ec8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02100793 li a5,33 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0f9957b7 lui a5,0xf995 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 0d278793 addi a5,a5,210 # f9950d2 <_start-0x7066af2e> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00100093 li ra,1 + 80002acc: 00009f13 slli t5,ra,0x0 + 80002ad0: 00100e93 li t4,1 + 80002ad4: 00200193 li gp,2 + 80002ad8: 2fdf1463 bne t5,t4,80002dc0 + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 00109f13 slli t5,ra,0x1 + 80002ae4: 00200e93 li t4,2 + 80002ae8: 00300193 li gp,3 + 80002aec: 2ddf1a63 bne t5,t4,80002dc0 + +0000000080002af0 : + 80002af0: 00100093 li ra,1 + 80002af4: 00709f13 slli t5,ra,0x7 + 80002af8: 08000e93 li t4,128 + 80002afc: 00400193 li gp,4 + 80002b00: 2ddf1063 bne t5,t4,80002dc0 + +0000000080002b04 : + 80002b04: 00100093 li ra,1 + 80002b08: 00e09f13 slli t5,ra,0xe + 80002b0c: 00004eb7 lui t4,0x4 + 80002b10: 00500193 li gp,5 + 80002b14: 2bdf1663 bne t5,t4,80002dc0 + +0000000080002b18 : + 80002b18: 00100093 li ra,1 + 80002b1c: 01f09f13 slli t5,ra,0x1f + 80002b20: 00100e9b addiw t4,zero,1 + 80002b24: 01fe9e93 slli t4,t4,0x1f + 80002b28: 00600193 li gp,6 + 80002b2c: 29df1a63 bne t5,t4,80002dc0 + +0000000080002b30 : + 80002b30: fff00093 li ra,-1 + 80002b34: 00009f13 slli t5,ra,0x0 + 80002b38: fff00e93 li t4,-1 + 80002b3c: 00700193 li gp,7 + 80002b40: 29df1063 bne t5,t4,80002dc0 + +0000000080002b44 : + 80002b44: fff00093 li ra,-1 + 80002b48: 00109f13 slli t5,ra,0x1 + 80002b4c: ffe00e93 li t4,-2 + 80002b50: 00800193 li gp,8 + 80002b54: 27df1663 bne t5,t4,80002dc0 + +0000000080002b58 : + 80002b58: fff00093 li ra,-1 + 80002b5c: 00709f13 slli t5,ra,0x7 + 80002b60: f8000e93 li t4,-128 + 80002b64: 00900193 li gp,9 + 80002b68: 25df1c63 bne t5,t4,80002dc0 + +0000000080002b6c : + 80002b6c: fff00093 li ra,-1 + 80002b70: 00e09f13 slli t5,ra,0xe + 80002b74: ffffceb7 lui t4,0xffffc + 80002b78: 00a00193 li gp,10 + 80002b7c: 25df1263 bne t5,t4,80002dc0 + +0000000080002b80 : + 80002b80: fff00093 li ra,-1 + 80002b84: 01f09f13 slli t5,ra,0x1f + 80002b88: 80000eb7 lui t4,0x80000 + 80002b8c: 00b00193 li gp,11 + 80002b90: 23df1863 bne t5,t4,80002dc0 + +0000000080002b94 : + 80002b94: 212120b7 lui ra,0x21212 + 80002b98: 1210809b addiw ra,ra,289 + 80002b9c: 00009f13 slli t5,ra,0x0 + 80002ba0: 21212eb7 lui t4,0x21212 + 80002ba4: 121e8e9b addiw t4,t4,289 + 80002ba8: 00c00193 li gp,12 + 80002bac: 21df1a63 bne t5,t4,80002dc0 + +0000000080002bb0 : + 80002bb0: 212120b7 lui ra,0x21212 + 80002bb4: 1210809b addiw ra,ra,289 + 80002bb8: 00109f13 slli t5,ra,0x1 + 80002bbc: 42424eb7 lui t4,0x42424 + 80002bc0: 242e8e9b addiw t4,t4,578 + 80002bc4: 00d00193 li gp,13 + 80002bc8: 1fdf1c63 bne t5,t4,80002dc0 + +0000000080002bcc : + 80002bcc: 212120b7 lui ra,0x21212 + 80002bd0: 1210809b addiw ra,ra,289 + 80002bd4: 00709f13 slli t5,ra,0x7 + 80002bd8: 01091eb7 lui t4,0x1091 + 80002bdc: 909e8e9b addiw t4,t4,-1783 + 80002be0: 00ce9e93 slli t4,t4,0xc + 80002be4: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 80002be8: 00e00193 li gp,14 + 80002bec: 1ddf1a63 bne t5,t4,80002dc0 + +0000000080002bf0 : + 80002bf0: 212120b7 lui ra,0x21212 + 80002bf4: 1210809b addiw ra,ra,289 + 80002bf8: 00e09f13 slli t5,ra,0xe + 80002bfc: 21212eb7 lui t4,0x21212 + 80002c00: 121e8e9b addiw t4,t4,289 + 80002c04: 00ee9e93 slli t4,t4,0xe + 80002c08: 00f00193 li gp,15 + 80002c0c: 1bdf1a63 bne t5,t4,80002dc0 + +0000000080002c10 : + 80002c10: 212120b7 lui ra,0x21212 + 80002c14: 1210809b addiw ra,ra,289 + 80002c18: 01f09f13 slli t5,ra,0x1f + 80002c1c: 21212eb7 lui t4,0x21212 + 80002c20: 121e8e9b addiw t4,t4,289 + 80002c24: 01fe9e93 slli t4,t4,0x1f + 80002c28: 01000193 li gp,16 + 80002c2c: 19df1a63 bne t5,t4,80002dc0 + +0000000080002c30 : + 80002c30: 00100093 li ra,1 + 80002c34: 03f09f13 slli t5,ra,0x3f + 80002c38: fff00e9b addiw t4,zero,-1 + 80002c3c: 03fe9e93 slli t4,t4,0x3f + 80002c40: 03200193 li gp,50 + 80002c44: 17df1e63 bne t5,t4,80002dc0 + +0000000080002c48 : + 80002c48: fff00093 li ra,-1 + 80002c4c: 02709f13 slli t5,ra,0x27 + 80002c50: fff00e9b addiw t4,zero,-1 + 80002c54: 027e9e93 slli t4,t4,0x27 + 80002c58: 03300193 li gp,51 + 80002c5c: 17df1263 bne t5,t4,80002dc0 + +0000000080002c60 : + 80002c60: 212120b7 lui ra,0x21212 + 80002c64: 1210809b addiw ra,ra,289 + 80002c68: 02b09f13 slli t5,ra,0x2b + 80002c6c: 00012eb7 lui t4,0x12 + 80002c70: 121e8e9b addiw t4,t4,289 + 80002c74: 02be9e93 slli t4,t4,0x2b + 80002c78: 03400193 li gp,52 + 80002c7c: 15df1263 bne t5,t4,80002dc0 + +0000000080002c80 : + 80002c80: 00100093 li ra,1 + 80002c84: 00709093 slli ra,ra,0x7 + 80002c88: 08000e93 li t4,128 + 80002c8c: 01100193 li gp,17 + 80002c90: 13d09863 bne ra,t4,80002dc0 + +0000000080002c94 : + 80002c94: 00000213 li tp,0 + 80002c98: 00100093 li ra,1 + 80002c9c: 00709f13 slli t5,ra,0x7 + 80002ca0: 000f0313 mv t1,t5 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5216e3 bne tp,t0,80002c98 + 80002cb0: 08000e93 li t4,128 + 80002cb4: 01200193 li gp,18 + 80002cb8: 11d31463 bne t1,t4,80002dc0 + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 00100093 li ra,1 + 80002cc4: 00e09f13 slli t5,ra,0xe + 80002cc8: 00000013 nop + 80002ccc: 000f0313 mv t1,t5 + 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd4: 00200293 li t0,2 + 80002cd8: fe5214e3 bne tp,t0,80002cc0 + 80002cdc: 00004eb7 lui t4,0x4 + 80002ce0: 01300193 li gp,19 + 80002ce4: 0dd31e63 bne t1,t4,80002dc0 + +0000000080002ce8 : + 80002ce8: 00000213 li tp,0 + 80002cec: 00100093 li ra,1 + 80002cf0: 01f09f13 slli t5,ra,0x1f + 80002cf4: 00000013 nop + 80002cf8: 00000013 nop + 80002cfc: 000f0313 mv t1,t5 + 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d04: 00200293 li t0,2 + 80002d08: fe5212e3 bne tp,t0,80002cec + 80002d0c: 00100e9b addiw t4,zero,1 + 80002d10: 01fe9e93 slli t4,t4,0x1f + 80002d14: 01400193 li gp,20 + 80002d18: 0bd31463 bne t1,t4,80002dc0 + +0000000080002d1c : + 80002d1c: 00000213 li tp,0 + 80002d20: 00100093 li ra,1 + 80002d24: 00709f13 slli t5,ra,0x7 + 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d2c: 00200293 li t0,2 + 80002d30: fe5218e3 bne tp,t0,80002d20 + 80002d34: 08000e93 li t4,128 + 80002d38: 01500193 li gp,21 + 80002d3c: 09df1263 bne t5,t4,80002dc0 + +0000000080002d40 : + 80002d40: 00000213 li tp,0 + 80002d44: 00100093 li ra,1 + 80002d48: 00000013 nop + 80002d4c: 00e09f13 slli t5,ra,0xe + 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d54: 00200293 li t0,2 + 80002d58: fe5216e3 bne tp,t0,80002d44 + 80002d5c: 00004eb7 lui t4,0x4 + 80002d60: 01600193 li gp,22 + 80002d64: 05df1e63 bne t5,t4,80002dc0 + +0000000080002d68 : + 80002d68: 00000213 li tp,0 + 80002d6c: 00100093 li ra,1 + 80002d70: 00000013 nop + 80002d74: 00000013 nop + 80002d78: 01f09f13 slli t5,ra,0x1f + 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d80: 00200293 li t0,2 + 80002d84: fe5214e3 bne tp,t0,80002d6c + 80002d88: 00100e9b addiw t4,zero,1 + 80002d8c: 01fe9e93 slli t4,t4,0x1f + 80002d90: 01700193 li gp,23 + 80002d94: 03df1663 bne t5,t4,80002dc0 + +0000000080002d98 : + 80002d98: 01f01093 slli ra,zero,0x1f + 80002d9c: 00000e93 li t4,0 + 80002da0: 01800193 li gp,24 + 80002da4: 01d09e63 bne ra,t4,80002dc0 + +0000000080002da8 : + 80002da8: 02100093 li ra,33 + 80002dac: 01409013 slli zero,ra,0x14 + 80002db0: 00000e93 li t4,0 + 80002db4: 01900193 li gp,25 + 80002db8: 01d01463 bne zero,t4,80002dc0 + 80002dbc: 00301a63 bne zero,gp,80002dd0 + +0000000080002dc0 : + 80002dc0: 00119513 slli a0,gp,0x1 + 80002dc4: 00050063 beqz a0,80002dc4 + 80002dc8: 00156513 ori a0,a0,1 + 80002dcc: 00000073 ecall + +0000000080002dd0 : + 80002dd0: 00100513 li a0,1 + 80002dd4: 00000073 ecall + 80002dd8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slli.elf b/test/riscv/tests/rv64ui-v-slli.elf new file mode 100644 index 00000000..2b9e327a Binary files /dev/null and b/test/riscv/tests/rv64ui-v-slli.elf differ diff --git a/test/riscv/tests/rv64ui-v-slliw.dump b/test/riscv/tests/rv64ui-v-slliw.dump new file mode 100644 index 00000000..25efc0d9 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-slliw.dump @@ -0,0 +1,1047 @@ + +rv64ui-v-slliw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 91068693 addi a3,a3,-1776 # 80002d68 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 94460613 addi a2,a2,-1724 # 80002df8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 90c60613 addi a2,a2,-1780 # 80002e10 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 85c68693 addi a3,a3,-1956 # 80002db0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 87868693 addi a3,a3,-1928 # 80002ee8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7f860613 addi a2,a2,2040 # 80002ec0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 72c68693 addi a3,a3,1836 # 80002f18 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 64c68693 addi a3,a3,1612 # 80002e88 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5dc68693 addi a3,a3,1500 # 80002e50 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01000793 li a5,16 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a2947b7 lui a5,0xa294 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: def78793 addi a5,a5,-529 # a293def <_start-0x75d6c211> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00100093 li ra,1 + 80002acc: 00009f1b slliw t5,ra,0x0 + 80002ad0: 00100e93 li t4,1 + 80002ad4: 00200193 li gp,2 + 80002ad8: 27df1a63 bne t5,t4,80002d4c + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 00109f1b slliw t5,ra,0x1 + 80002ae4: 00200e93 li t4,2 + 80002ae8: 00300193 li gp,3 + 80002aec: 27df1063 bne t5,t4,80002d4c + +0000000080002af0 : + 80002af0: 00100093 li ra,1 + 80002af4: 00709f1b slliw t5,ra,0x7 + 80002af8: 08000e93 li t4,128 + 80002afc: 00400193 li gp,4 + 80002b00: 25df1663 bne t5,t4,80002d4c + +0000000080002b04 : + 80002b04: 00100093 li ra,1 + 80002b08: 00e09f1b slliw t5,ra,0xe + 80002b0c: 00004eb7 lui t4,0x4 + 80002b10: 00500193 li gp,5 + 80002b14: 23df1c63 bne t5,t4,80002d4c + +0000000080002b18 : + 80002b18: 00100093 li ra,1 + 80002b1c: 01f09f1b slliw t5,ra,0x1f + 80002b20: 80000eb7 lui t4,0x80000 + 80002b24: 00600193 li gp,6 + 80002b28: 23df1263 bne t5,t4,80002d4c + +0000000080002b2c : + 80002b2c: fff00093 li ra,-1 + 80002b30: 00009f1b slliw t5,ra,0x0 + 80002b34: fff00e93 li t4,-1 + 80002b38: 00700193 li gp,7 + 80002b3c: 21df1863 bne t5,t4,80002d4c + +0000000080002b40 : + 80002b40: fff00093 li ra,-1 + 80002b44: 00109f1b slliw t5,ra,0x1 + 80002b48: ffe00e93 li t4,-2 + 80002b4c: 00800193 li gp,8 + 80002b50: 1fdf1e63 bne t5,t4,80002d4c + +0000000080002b54 : + 80002b54: fff00093 li ra,-1 + 80002b58: 00709f1b slliw t5,ra,0x7 + 80002b5c: f8000e93 li t4,-128 + 80002b60: 00900193 li gp,9 + 80002b64: 1fdf1463 bne t5,t4,80002d4c + +0000000080002b68 : + 80002b68: fff00093 li ra,-1 + 80002b6c: 00e09f1b slliw t5,ra,0xe + 80002b70: ffffceb7 lui t4,0xffffc + 80002b74: 00a00193 li gp,10 + 80002b78: 1ddf1a63 bne t5,t4,80002d4c + +0000000080002b7c : + 80002b7c: fff00093 li ra,-1 + 80002b80: 01f09f1b slliw t5,ra,0x1f + 80002b84: 80000eb7 lui t4,0x80000 + 80002b88: 00b00193 li gp,11 + 80002b8c: 1ddf1063 bne t5,t4,80002d4c + +0000000080002b90 : + 80002b90: 212120b7 lui ra,0x21212 + 80002b94: 1210809b addiw ra,ra,289 + 80002b98: 00009f1b slliw t5,ra,0x0 + 80002b9c: 21212eb7 lui t4,0x21212 + 80002ba0: 121e8e9b addiw t4,t4,289 + 80002ba4: 00c00193 li gp,12 + 80002ba8: 1bdf1263 bne t5,t4,80002d4c + +0000000080002bac : + 80002bac: 212120b7 lui ra,0x21212 + 80002bb0: 1210809b addiw ra,ra,289 + 80002bb4: 00109f1b slliw t5,ra,0x1 + 80002bb8: 42424eb7 lui t4,0x42424 + 80002bbc: 242e8e9b addiw t4,t4,578 + 80002bc0: 00d00193 li gp,13 + 80002bc4: 19df1463 bne t5,t4,80002d4c + +0000000080002bc8 : + 80002bc8: 212120b7 lui ra,0x21212 + 80002bcc: 1210809b addiw ra,ra,289 + 80002bd0: 00709f1b slliw t5,ra,0x7 + 80002bd4: 90909eb7 lui t4,0x90909 + 80002bd8: 080e8e9b addiw t4,t4,128 + 80002bdc: 00e00193 li gp,14 + 80002be0: 17df1663 bne t5,t4,80002d4c + +0000000080002be4 : + 80002be4: 212120b7 lui ra,0x21212 + 80002be8: 1210809b addiw ra,ra,289 + 80002bec: 00e09f1b slliw t5,ra,0xe + 80002bf0: 48484eb7 lui t4,0x48484 + 80002bf4: 00f00193 li gp,15 + 80002bf8: 15df1a63 bne t5,t4,80002d4c + +0000000080002bfc : + 80002bfc: 212120b7 lui ra,0x21212 + 80002c00: 1210809b addiw ra,ra,289 + 80002c04: 01f09f1b slliw t5,ra,0x1f + 80002c08: 80000eb7 lui t4,0x80000 + 80002c0c: 01000193 li gp,16 + 80002c10: 13df1e63 bne t5,t4,80002d4c + +0000000080002c14 : + 80002c14: 00100093 li ra,1 + 80002c18: 0070909b slliw ra,ra,0x7 + 80002c1c: 08000e93 li t4,128 + 80002c20: 01100193 li gp,17 + 80002c24: 13d09463 bne ra,t4,80002d4c + +0000000080002c28 : + 80002c28: 00000213 li tp,0 + 80002c2c: 00100093 li ra,1 + 80002c30: 00709f1b slliw t5,ra,0x7 + 80002c34: 000f0313 mv t1,t5 + 80002c38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c3c: 00200293 li t0,2 + 80002c40: fe5216e3 bne tp,t0,80002c2c + 80002c44: 08000e93 li t4,128 + 80002c48: 01200193 li gp,18 + 80002c4c: 11d31063 bne t1,t4,80002d4c + +0000000080002c50 : + 80002c50: 00000213 li tp,0 + 80002c54: 00100093 li ra,1 + 80002c58: 00e09f1b slliw t5,ra,0xe + 80002c5c: 00000013 nop + 80002c60: 000f0313 mv t1,t5 + 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c68: 00200293 li t0,2 + 80002c6c: fe5214e3 bne tp,t0,80002c54 + 80002c70: 00004eb7 lui t4,0x4 + 80002c74: 01300193 li gp,19 + 80002c78: 0dd31a63 bne t1,t4,80002d4c + +0000000080002c7c : + 80002c7c: 00000213 li tp,0 + 80002c80: 00100093 li ra,1 + 80002c84: 01f09f1b slliw t5,ra,0x1f + 80002c88: 00000013 nop + 80002c8c: 00000013 nop + 80002c90: 000f0313 mv t1,t5 + 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c98: 00200293 li t0,2 + 80002c9c: fe5212e3 bne tp,t0,80002c80 + 80002ca0: 80000eb7 lui t4,0x80000 + 80002ca4: 01400193 li gp,20 + 80002ca8: 0bd31263 bne t1,t4,80002d4c + +0000000080002cac : + 80002cac: 00000213 li tp,0 + 80002cb0: 00100093 li ra,1 + 80002cb4: 00709f1b slliw t5,ra,0x7 + 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cbc: 00200293 li t0,2 + 80002cc0: fe5218e3 bne tp,t0,80002cb0 + 80002cc4: 08000e93 li t4,128 + 80002cc8: 01500193 li gp,21 + 80002ccc: 09df1063 bne t5,t4,80002d4c + +0000000080002cd0 : + 80002cd0: 00000213 li tp,0 + 80002cd4: 00100093 li ra,1 + 80002cd8: 00000013 nop + 80002cdc: 00e09f1b slliw t5,ra,0xe + 80002ce0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce4: 00200293 li t0,2 + 80002ce8: fe5216e3 bne tp,t0,80002cd4 + 80002cec: 00004eb7 lui t4,0x4 + 80002cf0: 01600193 li gp,22 + 80002cf4: 05df1c63 bne t5,t4,80002d4c + +0000000080002cf8 : + 80002cf8: 00000213 li tp,0 + 80002cfc: 00100093 li ra,1 + 80002d00: 00000013 nop + 80002d04: 00000013 nop + 80002d08: 01f09f1b slliw t5,ra,0x1f + 80002d0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d10: 00200293 li t0,2 + 80002d14: fe5214e3 bne tp,t0,80002cfc + 80002d18: 80000eb7 lui t4,0x80000 + 80002d1c: 01700193 li gp,23 + 80002d20: 03df1663 bne t5,t4,80002d4c + +0000000080002d24 : + 80002d24: 01f0109b slliw ra,zero,0x1f + 80002d28: 00000e93 li t4,0 + 80002d2c: 01800193 li gp,24 + 80002d30: 01d09e63 bne ra,t4,80002d4c + +0000000080002d34 : + 80002d34: 01f00093 li ra,31 + 80002d38: 01c0901b slliw zero,ra,0x1c + 80002d3c: 00000e93 li t4,0 + 80002d40: 01900193 li gp,25 + 80002d44: 01d01463 bne zero,t4,80002d4c + 80002d48: 00301a63 bne zero,gp,80002d5c + +0000000080002d4c : + 80002d4c: 00119513 slli a0,gp,0x1 + 80002d50: 00050063 beqz a0,80002d50 + 80002d54: 00156513 ori a0,a0,1 + 80002d58: 00000073 ecall + +0000000080002d5c : + 80002d5c: 00100513 li a0,1 + 80002d60: 00000073 ecall + 80002d64: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slliw.elf b/test/riscv/tests/rv64ui-v-slliw.elf new file mode 100644 index 00000000..dd80f11c Binary files /dev/null and b/test/riscv/tests/rv64ui-v-slliw.elf differ diff --git a/test/riscv/tests/rv64ui-v-sllw.dump b/test/riscv/tests/rv64ui-v-sllw.dump new file mode 100644 index 00000000..e44d86e7 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sllw.dump @@ -0,0 +1,1269 @@ + +rv64ui-v-sllw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: bf868693 addi a3,a3,-1032 # 80003050 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c2c60613 addi a2,a2,-980 # 800030e0 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: bf460613 addi a2,a2,-1036 # 800030f8 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: b4468693 addi a3,a3,-1212 # 80003098 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b6068693 addi a3,a3,-1184 # 800031d0 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: ae060613 addi a2,a2,-1312 # 800031a8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a1468693 addi a3,a3,-1516 # 80003200 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 93468693 addi a3,a3,-1740 # 80003170 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 8c468693 addi a3,a3,-1852 # 80003138 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02f00793 li a5,47 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 09afd7b7 lui a5,0x9afd + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 1b578793 addi a5,a5,437 # 9afd1b5 <_start-0x76502e4b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00100093 li ra,1 + 80002acc: 00000113 li sp,0 + 80002ad0: 00209f3b sllw t5,ra,sp + 80002ad4: 00100e93 li t4,1 + 80002ad8: 00200193 li gp,2 + 80002adc: 55df1c63 bne t5,t4,80003034 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 00209f3b sllw t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 55df1063 bne t5,t4,80003034 + +0000000080002af8 : + 80002af8: 00100093 li ra,1 + 80002afc: 00700113 li sp,7 + 80002b00: 00209f3b sllw t5,ra,sp + 80002b04: 08000e93 li t4,128 + 80002b08: 00400193 li gp,4 + 80002b0c: 53df1463 bne t5,t4,80003034 + +0000000080002b10 : + 80002b10: 00100093 li ra,1 + 80002b14: 00e00113 li sp,14 + 80002b18: 00209f3b sllw t5,ra,sp + 80002b1c: 00004eb7 lui t4,0x4 + 80002b20: 00500193 li gp,5 + 80002b24: 51df1863 bne t5,t4,80003034 + +0000000080002b28 : + 80002b28: 00100093 li ra,1 + 80002b2c: 01f00113 li sp,31 + 80002b30: 00209f3b sllw t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 4fdf1c63 bne t5,t4,80003034 + +0000000080002b40 : + 80002b40: fff00093 li ra,-1 + 80002b44: 00000113 li sp,0 + 80002b48: 00209f3b sllw t5,ra,sp + 80002b4c: fff00e93 li t4,-1 + 80002b50: 00700193 li gp,7 + 80002b54: 4fdf1063 bne t5,t4,80003034 + +0000000080002b58 : + 80002b58: fff00093 li ra,-1 + 80002b5c: 00100113 li sp,1 + 80002b60: 00209f3b sllw t5,ra,sp + 80002b64: ffe00e93 li t4,-2 + 80002b68: 00800193 li gp,8 + 80002b6c: 4ddf1463 bne t5,t4,80003034 + +0000000080002b70 : + 80002b70: fff00093 li ra,-1 + 80002b74: 00700113 li sp,7 + 80002b78: 00209f3b sllw t5,ra,sp + 80002b7c: f8000e93 li t4,-128 + 80002b80: 00900193 li gp,9 + 80002b84: 4bdf1863 bne t5,t4,80003034 + +0000000080002b88 : + 80002b88: fff00093 li ra,-1 + 80002b8c: 00e00113 li sp,14 + 80002b90: 00209f3b sllw t5,ra,sp + 80002b94: ffffceb7 lui t4,0xffffc + 80002b98: 00a00193 li gp,10 + 80002b9c: 49df1c63 bne t5,t4,80003034 + +0000000080002ba0 : + 80002ba0: fff00093 li ra,-1 + 80002ba4: 01f00113 li sp,31 + 80002ba8: 00209f3b sllw t5,ra,sp + 80002bac: 80000eb7 lui t4,0x80000 + 80002bb0: 00b00193 li gp,11 + 80002bb4: 49df1063 bne t5,t4,80003034 + +0000000080002bb8 : + 80002bb8: 212120b7 lui ra,0x21212 + 80002bbc: 1210809b addiw ra,ra,289 + 80002bc0: 00000113 li sp,0 + 80002bc4: 00209f3b sllw t5,ra,sp + 80002bc8: 21212eb7 lui t4,0x21212 + 80002bcc: 121e8e9b addiw t4,t4,289 + 80002bd0: 00c00193 li gp,12 + 80002bd4: 47df1063 bne t5,t4,80003034 + +0000000080002bd8 : + 80002bd8: 212120b7 lui ra,0x21212 + 80002bdc: 1210809b addiw ra,ra,289 + 80002be0: 00100113 li sp,1 + 80002be4: 00209f3b sllw t5,ra,sp + 80002be8: 42424eb7 lui t4,0x42424 + 80002bec: 242e8e9b addiw t4,t4,578 + 80002bf0: 00d00193 li gp,13 + 80002bf4: 45df1063 bne t5,t4,80003034 + +0000000080002bf8 : + 80002bf8: 212120b7 lui ra,0x21212 + 80002bfc: 1210809b addiw ra,ra,289 + 80002c00: 00700113 li sp,7 + 80002c04: 00209f3b sllw t5,ra,sp + 80002c08: 90909eb7 lui t4,0x90909 + 80002c0c: 080e8e9b addiw t4,t4,128 + 80002c10: 00e00193 li gp,14 + 80002c14: 43df1063 bne t5,t4,80003034 + +0000000080002c18 : + 80002c18: 212120b7 lui ra,0x21212 + 80002c1c: 1210809b addiw ra,ra,289 + 80002c20: 00e00113 li sp,14 + 80002c24: 00209f3b sllw t5,ra,sp + 80002c28: 48484eb7 lui t4,0x48484 + 80002c2c: 00f00193 li gp,15 + 80002c30: 41df1263 bne t5,t4,80003034 + +0000000080002c34 : + 80002c34: 212120b7 lui ra,0x21212 + 80002c38: 1210809b addiw ra,ra,289 + 80002c3c: 01f00113 li sp,31 + 80002c40: 00209f3b sllw t5,ra,sp + 80002c44: 80000eb7 lui t4,0x80000 + 80002c48: 01000193 li gp,16 + 80002c4c: 3fdf1463 bne t5,t4,80003034 + +0000000080002c50 : + 80002c50: 212120b7 lui ra,0x21212 + 80002c54: 1210809b addiw ra,ra,289 + 80002c58: fe000113 li sp,-32 + 80002c5c: 00209f3b sllw t5,ra,sp + 80002c60: 21212eb7 lui t4,0x21212 + 80002c64: 121e8e9b addiw t4,t4,289 + 80002c68: 01100193 li gp,17 + 80002c6c: 3ddf1463 bne t5,t4,80003034 + +0000000080002c70 : + 80002c70: 212120b7 lui ra,0x21212 + 80002c74: 1210809b addiw ra,ra,289 + 80002c78: fe100113 li sp,-31 + 80002c7c: 00209f3b sllw t5,ra,sp + 80002c80: 42424eb7 lui t4,0x42424 + 80002c84: 242e8e9b addiw t4,t4,578 + 80002c88: 01200193 li gp,18 + 80002c8c: 3bdf1463 bne t5,t4,80003034 + +0000000080002c90 : + 80002c90: 212120b7 lui ra,0x21212 + 80002c94: 1210809b addiw ra,ra,289 + 80002c98: fe700113 li sp,-25 + 80002c9c: 00209f3b sllw t5,ra,sp + 80002ca0: 90909eb7 lui t4,0x90909 + 80002ca4: 080e8e9b addiw t4,t4,128 + 80002ca8: 01300193 li gp,19 + 80002cac: 39df1463 bne t5,t4,80003034 + +0000000080002cb0 : + 80002cb0: 212120b7 lui ra,0x21212 + 80002cb4: 1210809b addiw ra,ra,289 + 80002cb8: fee00113 li sp,-18 + 80002cbc: 00209f3b sllw t5,ra,sp + 80002cc0: 48484eb7 lui t4,0x48484 + 80002cc4: 01400193 li gp,20 + 80002cc8: 37df1663 bne t5,t4,80003034 + +0000000080002ccc : + 80002ccc: 212120b7 lui ra,0x21212 + 80002cd0: 1210809b addiw ra,ra,289 + 80002cd4: fff00113 li sp,-1 + 80002cd8: 00209f3b sllw t5,ra,sp + 80002cdc: 80000eb7 lui t4,0x80000 + 80002ce0: 01500193 li gp,21 + 80002ce4: 35df1863 bne t5,t4,80003034 + +0000000080002ce8 : + 80002ce8: 00100093 li ra,1 + 80002cec: 00700113 li sp,7 + 80002cf0: 002090bb sllw ra,ra,sp + 80002cf4: 08000e93 li t4,128 + 80002cf8: 01600193 li gp,22 + 80002cfc: 33d09c63 bne ra,t4,80003034 + +0000000080002d00 : + 80002d00: 00100093 li ra,1 + 80002d04: 00e00113 li sp,14 + 80002d08: 0020913b sllw sp,ra,sp + 80002d0c: 00004eb7 lui t4,0x4 + 80002d10: 01700193 li gp,23 + 80002d14: 33d11063 bne sp,t4,80003034 + +0000000080002d18 : + 80002d18: 00300093 li ra,3 + 80002d1c: 001090bb sllw ra,ra,ra + 80002d20: 01800e93 li t4,24 + 80002d24: 01800193 li gp,24 + 80002d28: 31d09663 bne ra,t4,80003034 + +0000000080002d2c : + 80002d2c: 00000213 li tp,0 + 80002d30: 00100093 li ra,1 + 80002d34: 00700113 li sp,7 + 80002d38: 00209f3b sllw t5,ra,sp + 80002d3c: 000f0313 mv t1,t5 + 80002d40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d44: 00200293 li t0,2 + 80002d48: fe5214e3 bne tp,t0,80002d30 + 80002d4c: 08000e93 li t4,128 + 80002d50: 01900193 li gp,25 + 80002d54: 2fd31063 bne t1,t4,80003034 + +0000000080002d58 : + 80002d58: 00000213 li tp,0 + 80002d5c: 00100093 li ra,1 + 80002d60: 00e00113 li sp,14 + 80002d64: 00209f3b sllw t5,ra,sp + 80002d68: 00000013 nop + 80002d6c: 000f0313 mv t1,t5 + 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d74: 00200293 li t0,2 + 80002d78: fe5212e3 bne tp,t0,80002d5c + 80002d7c: 00004eb7 lui t4,0x4 + 80002d80: 01a00193 li gp,26 + 80002d84: 2bd31863 bne t1,t4,80003034 + +0000000080002d88 : + 80002d88: 00000213 li tp,0 + 80002d8c: 00100093 li ra,1 + 80002d90: 01f00113 li sp,31 + 80002d94: 00209f3b sllw t5,ra,sp + 80002d98: 00000013 nop + 80002d9c: 00000013 nop + 80002da0: 000f0313 mv t1,t5 + 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da8: 00200293 li t0,2 + 80002dac: fe5210e3 bne tp,t0,80002d8c + 80002db0: 80000eb7 lui t4,0x80000 + 80002db4: 01b00193 li gp,27 + 80002db8: 27d31e63 bne t1,t4,80003034 + +0000000080002dbc : + 80002dbc: 00000213 li tp,0 + 80002dc0: 00100093 li ra,1 + 80002dc4: 00700113 li sp,7 + 80002dc8: 00209f3b sllw t5,ra,sp + 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd0: 00200293 li t0,2 + 80002dd4: fe5216e3 bne tp,t0,80002dc0 + 80002dd8: 08000e93 li t4,128 + 80002ddc: 01c00193 li gp,28 + 80002de0: 25df1a63 bne t5,t4,80003034 + +0000000080002de4 : + 80002de4: 00000213 li tp,0 + 80002de8: 00100093 li ra,1 + 80002dec: 00e00113 li sp,14 + 80002df0: 00000013 nop + 80002df4: 00209f3b sllw t5,ra,sp + 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dfc: 00200293 li t0,2 + 80002e00: fe5214e3 bne tp,t0,80002de8 + 80002e04: 00004eb7 lui t4,0x4 + 80002e08: 01d00193 li gp,29 + 80002e0c: 23df1463 bne t5,t4,80003034 + +0000000080002e10 : + 80002e10: 00000213 li tp,0 + 80002e14: 00100093 li ra,1 + 80002e18: 01f00113 li sp,31 + 80002e1c: 00000013 nop + 80002e20: 00000013 nop + 80002e24: 00209f3b sllw t5,ra,sp + 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e2c: 00200293 li t0,2 + 80002e30: fe5212e3 bne tp,t0,80002e14 + 80002e34: 80000eb7 lui t4,0x80000 + 80002e38: 01e00193 li gp,30 + 80002e3c: 1fdf1c63 bne t5,t4,80003034 + +0000000080002e40 : + 80002e40: 00000213 li tp,0 + 80002e44: 00100093 li ra,1 + 80002e48: 00000013 nop + 80002e4c: 00700113 li sp,7 + 80002e50: 00209f3b sllw t5,ra,sp + 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e58: 00200293 li t0,2 + 80002e5c: fe5214e3 bne tp,t0,80002e44 + 80002e60: 08000e93 li t4,128 + 80002e64: 01f00193 li gp,31 + 80002e68: 1ddf1663 bne t5,t4,80003034 + +0000000080002e6c : + 80002e6c: 00000213 li tp,0 + 80002e70: 00100093 li ra,1 + 80002e74: 00000013 nop + 80002e78: 00e00113 li sp,14 + 80002e7c: 00000013 nop + 80002e80: 00209f3b sllw t5,ra,sp + 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e88: 00200293 li t0,2 + 80002e8c: fe5212e3 bne tp,t0,80002e70 + 80002e90: 00004eb7 lui t4,0x4 + 80002e94: 02000193 li gp,32 + 80002e98: 19df1e63 bne t5,t4,80003034 + +0000000080002e9c : + 80002e9c: 00000213 li tp,0 + 80002ea0: 00100093 li ra,1 + 80002ea4: 00000013 nop + 80002ea8: 00000013 nop + 80002eac: 01f00113 li sp,31 + 80002eb0: 00209f3b sllw t5,ra,sp + 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb8: 00200293 li t0,2 + 80002ebc: fe5212e3 bne tp,t0,80002ea0 + 80002ec0: 80000eb7 lui t4,0x80000 + 80002ec4: 02100193 li gp,33 + 80002ec8: 17df1663 bne t5,t4,80003034 + +0000000080002ecc : + 80002ecc: 00000213 li tp,0 + 80002ed0: 00700113 li sp,7 + 80002ed4: 00100093 li ra,1 + 80002ed8: 00209f3b sllw t5,ra,sp + 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee0: 00200293 li t0,2 + 80002ee4: fe5216e3 bne tp,t0,80002ed0 + 80002ee8: 08000e93 li t4,128 + 80002eec: 02200193 li gp,34 + 80002ef0: 15df1263 bne t5,t4,80003034 + +0000000080002ef4 : + 80002ef4: 00000213 li tp,0 + 80002ef8: 00e00113 li sp,14 + 80002efc: 00100093 li ra,1 + 80002f00: 00000013 nop + 80002f04: 00209f3b sllw t5,ra,sp + 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f0c: 00200293 li t0,2 + 80002f10: fe5214e3 bne tp,t0,80002ef8 + 80002f14: 00004eb7 lui t4,0x4 + 80002f18: 02300193 li gp,35 + 80002f1c: 11df1c63 bne t5,t4,80003034 + +0000000080002f20 : + 80002f20: 00000213 li tp,0 + 80002f24: 01f00113 li sp,31 + 80002f28: 00100093 li ra,1 + 80002f2c: 00000013 nop + 80002f30: 00000013 nop + 80002f34: 00209f3b sllw t5,ra,sp + 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f3c: 00200293 li t0,2 + 80002f40: fe5212e3 bne tp,t0,80002f24 + 80002f44: 80000eb7 lui t4,0x80000 + 80002f48: 02400193 li gp,36 + 80002f4c: 0fdf1463 bne t5,t4,80003034 + +0000000080002f50 : + 80002f50: 00000213 li tp,0 + 80002f54: 00700113 li sp,7 + 80002f58: 00000013 nop + 80002f5c: 00100093 li ra,1 + 80002f60: 00209f3b sllw t5,ra,sp + 80002f64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f68: 00200293 li t0,2 + 80002f6c: fe5214e3 bne tp,t0,80002f54 + 80002f70: 08000e93 li t4,128 + 80002f74: 02500193 li gp,37 + 80002f78: 0bdf1e63 bne t5,t4,80003034 + +0000000080002f7c : + 80002f7c: 00000213 li tp,0 + 80002f80: 00e00113 li sp,14 + 80002f84: 00000013 nop + 80002f88: 00100093 li ra,1 + 80002f8c: 00000013 nop + 80002f90: 00209f3b sllw t5,ra,sp + 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f98: 00200293 li t0,2 + 80002f9c: fe5212e3 bne tp,t0,80002f80 + 80002fa0: 00004eb7 lui t4,0x4 + 80002fa4: 02600193 li gp,38 + 80002fa8: 09df1663 bne t5,t4,80003034 + +0000000080002fac : + 80002fac: 00000213 li tp,0 + 80002fb0: 01f00113 li sp,31 + 80002fb4: 00000013 nop + 80002fb8: 00000013 nop + 80002fbc: 00100093 li ra,1 + 80002fc0: 00209f3b sllw t5,ra,sp + 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fc8: 00200293 li t0,2 + 80002fcc: fe5212e3 bne tp,t0,80002fb0 + 80002fd0: 80000eb7 lui t4,0x80000 + 80002fd4: 02700193 li gp,39 + 80002fd8: 05df1e63 bne t5,t4,80003034 + +0000000080002fdc : + 80002fdc: 00f00093 li ra,15 + 80002fe0: 0010113b sllw sp,zero,ra + 80002fe4: 00000e93 li t4,0 + 80002fe8: 02800193 li gp,40 + 80002fec: 05d11463 bne sp,t4,80003034 + +0000000080002ff0 : + 80002ff0: 02000093 li ra,32 + 80002ff4: 0000913b sllw sp,ra,zero + 80002ff8: 02000e93 li t4,32 + 80002ffc: 02900193 li gp,41 + 80003000: 03d11a63 bne sp,t4,80003034 + +0000000080003004 : + 80003004: 000010bb sllw ra,zero,zero + 80003008: 00000e93 li t4,0 + 8000300c: 02a00193 li gp,42 + 80003010: 03d09263 bne ra,t4,80003034 + +0000000080003014 : + 80003014: 40000093 li ra,1024 + 80003018: 00001137 lui sp,0x1 + 8000301c: 8001011b addiw sp,sp,-2048 + 80003020: 0020903b sllw zero,ra,sp + 80003024: 00000e93 li t4,0 + 80003028: 02b00193 li gp,43 + 8000302c: 01d01463 bne zero,t4,80003034 + 80003030: 00301a63 bne zero,gp,80003044 + +0000000080003034 : + 80003034: 00119513 slli a0,gp,0x1 + 80003038: 00050063 beqz a0,80003038 + 8000303c: 00156513 ori a0,a0,1 + 80003040: 00000073 ecall + +0000000080003044 : + 80003044: 00100513 li a0,1 + 80003048: 00000073 ecall + 8000304c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sllw.elf b/test/riscv/tests/rv64ui-v-sllw.elf new file mode 100644 index 00000000..9ae693bd Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sllw.elf differ diff --git a/test/riscv/tests/rv64ui-v-slt.dump b/test/riscv/tests/rv64ui-v-slt.dump new file mode 100644 index 00000000..dd39ae72 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-slt.dump @@ -0,0 +1,1218 @@ + +rv64ui-v-slt: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b5868693 addi a3,a3,-1192 # 80002fb0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b8c60613 addi a2,a2,-1140 # 80003040 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b5460613 addi a2,a2,-1196 # 80003058 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: aa468693 addi a3,a3,-1372 # 80002ff8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ac068693 addi a3,a3,-1344 # 80003130 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a4060613 addi a2,a2,-1472 # 80003108 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 97468693 addi a3,a3,-1676 # 80003160 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 89468693 addi a3,a3,-1900 # 800030d0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 82468693 addi a3,a3,-2012 # 80003098 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00300793 li a5,3 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0c8c27b7 lui a5,0xc8c2 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: a2878793 addi a5,a5,-1496 # c8c1a28 <_start-0x7373e5d8> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 0020af33 slt t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4bdf1a63 bne t5,t4,80002f90 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0020af33 slt t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 49df1e63 bne t5,t4,80002f90 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 0020af33 slt t5,ra,sp + 80002b04: 00100e93 li t4,1 + 80002b08: 00400193 li gp,4 + 80002b0c: 49df1263 bne t5,t4,80002f90 + +0000000080002b10 : + 80002b10: 00700093 li ra,7 + 80002b14: 00300113 li sp,3 + 80002b18: 0020af33 slt t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 47df1663 bne t5,t4,80002f90 + +0000000080002b28 : + 80002b28: 00000093 li ra,0 + 80002b2c: ffff8137 lui sp,0xffff8 + 80002b30: 0020af33 slt t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 45df1a63 bne t5,t4,80002f90 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: 00000113 li sp,0 + 80002b48: 0020af33 slt t5,ra,sp + 80002b4c: 00100e93 li t4,1 + 80002b50: 00700193 li gp,7 + 80002b54: 43df1e63 bne t5,t4,80002f90 + +0000000080002b58 : + 80002b58: 800000b7 lui ra,0x80000 + 80002b5c: ffff8137 lui sp,0xffff8 + 80002b60: 0020af33 slt t5,ra,sp + 80002b64: 00100e93 li t4,1 + 80002b68: 00800193 li gp,8 + 80002b6c: 43df1263 bne t5,t4,80002f90 + +0000000080002b70 : + 80002b70: 00000093 li ra,0 + 80002b74: 00008137 lui sp,0x8 + 80002b78: fff1011b addiw sp,sp,-1 + 80002b7c: 0020af33 slt t5,ra,sp + 80002b80: 00100e93 li t4,1 + 80002b84: 00900193 li gp,9 + 80002b88: 41df1463 bne t5,t4,80002f90 + +0000000080002b8c : + 80002b8c: 800000b7 lui ra,0x80000 + 80002b90: fff0809b addiw ra,ra,-1 + 80002b94: 00000113 li sp,0 + 80002b98: 0020af33 slt t5,ra,sp + 80002b9c: 00000e93 li t4,0 + 80002ba0: 00a00193 li gp,10 + 80002ba4: 3fdf1663 bne t5,t4,80002f90 + +0000000080002ba8 : + 80002ba8: 800000b7 lui ra,0x80000 + 80002bac: fff0809b addiw ra,ra,-1 + 80002bb0: 00008137 lui sp,0x8 + 80002bb4: fff1011b addiw sp,sp,-1 + 80002bb8: 0020af33 slt t5,ra,sp + 80002bbc: 00000e93 li t4,0 + 80002bc0: 00b00193 li gp,11 + 80002bc4: 3ddf1663 bne t5,t4,80002f90 + +0000000080002bc8 : + 80002bc8: 800000b7 lui ra,0x80000 + 80002bcc: 00008137 lui sp,0x8 + 80002bd0: fff1011b addiw sp,sp,-1 + 80002bd4: 0020af33 slt t5,ra,sp + 80002bd8: 00100e93 li t4,1 + 80002bdc: 00c00193 li gp,12 + 80002be0: 3bdf1863 bne t5,t4,80002f90 + +0000000080002be4 : + 80002be4: 800000b7 lui ra,0x80000 + 80002be8: fff0809b addiw ra,ra,-1 + 80002bec: ffff8137 lui sp,0xffff8 + 80002bf0: 0020af33 slt t5,ra,sp + 80002bf4: 00000e93 li t4,0 + 80002bf8: 00d00193 li gp,13 + 80002bfc: 39df1a63 bne t5,t4,80002f90 + +0000000080002c00 : + 80002c00: 00000093 li ra,0 + 80002c04: fff00113 li sp,-1 + 80002c08: 0020af33 slt t5,ra,sp + 80002c0c: 00000e93 li t4,0 + 80002c10: 00e00193 li gp,14 + 80002c14: 37df1e63 bne t5,t4,80002f90 + +0000000080002c18 : + 80002c18: fff00093 li ra,-1 + 80002c1c: 00100113 li sp,1 + 80002c20: 0020af33 slt t5,ra,sp + 80002c24: 00100e93 li t4,1 + 80002c28: 00f00193 li gp,15 + 80002c2c: 37df1263 bne t5,t4,80002f90 + +0000000080002c30 : + 80002c30: fff00093 li ra,-1 + 80002c34: fff00113 li sp,-1 + 80002c38: 0020af33 slt t5,ra,sp + 80002c3c: 00000e93 li t4,0 + 80002c40: 01000193 li gp,16 + 80002c44: 35df1663 bne t5,t4,80002f90 + +0000000080002c48 : + 80002c48: 00e00093 li ra,14 + 80002c4c: 00d00113 li sp,13 + 80002c50: 0020a0b3 slt ra,ra,sp + 80002c54: 00000e93 li t4,0 + 80002c58: 01100193 li gp,17 + 80002c5c: 33d09a63 bne ra,t4,80002f90 + +0000000080002c60 : + 80002c60: 00b00093 li ra,11 + 80002c64: 00d00113 li sp,13 + 80002c68: 0020a133 slt sp,ra,sp + 80002c6c: 00100e93 li t4,1 + 80002c70: 01200193 li gp,18 + 80002c74: 31d11e63 bne sp,t4,80002f90 + +0000000080002c78 : + 80002c78: 00d00093 li ra,13 + 80002c7c: 0010a0b3 slt ra,ra,ra + 80002c80: 00000e93 li t4,0 + 80002c84: 01300193 li gp,19 + 80002c88: 31d09463 bne ra,t4,80002f90 + +0000000080002c8c : + 80002c8c: 00000213 li tp,0 + 80002c90: 00b00093 li ra,11 + 80002c94: 00d00113 li sp,13 + 80002c98: 0020af33 slt t5,ra,sp + 80002c9c: 000f0313 mv t1,t5 + 80002ca0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca4: 00200293 li t0,2 + 80002ca8: fe5214e3 bne tp,t0,80002c90 + 80002cac: 00100e93 li t4,1 + 80002cb0: 01400193 li gp,20 + 80002cb4: 2dd31e63 bne t1,t4,80002f90 + +0000000080002cb8 : + 80002cb8: 00000213 li tp,0 + 80002cbc: 00e00093 li ra,14 + 80002cc0: 00d00113 li sp,13 + 80002cc4: 0020af33 slt t5,ra,sp + 80002cc8: 00000013 nop + 80002ccc: 000f0313 mv t1,t5 + 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd4: 00200293 li t0,2 + 80002cd8: fe5212e3 bne tp,t0,80002cbc + 80002cdc: 00000e93 li t4,0 + 80002ce0: 01500193 li gp,21 + 80002ce4: 2bd31663 bne t1,t4,80002f90 + +0000000080002ce8 : + 80002ce8: 00000213 li tp,0 + 80002cec: 00c00093 li ra,12 + 80002cf0: 00d00113 li sp,13 + 80002cf4: 0020af33 slt t5,ra,sp + 80002cf8: 00000013 nop + 80002cfc: 00000013 nop + 80002d00: 000f0313 mv t1,t5 + 80002d04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d08: 00200293 li t0,2 + 80002d0c: fe5210e3 bne tp,t0,80002cec + 80002d10: 00100e93 li t4,1 + 80002d14: 01600193 li gp,22 + 80002d18: 27d31c63 bne t1,t4,80002f90 + +0000000080002d1c : + 80002d1c: 00000213 li tp,0 + 80002d20: 00e00093 li ra,14 + 80002d24: 00d00113 li sp,13 + 80002d28: 0020af33 slt t5,ra,sp + 80002d2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d30: 00200293 li t0,2 + 80002d34: fe5216e3 bne tp,t0,80002d20 + 80002d38: 00000e93 li t4,0 + 80002d3c: 01700193 li gp,23 + 80002d40: 25df1863 bne t5,t4,80002f90 + +0000000080002d44 : + 80002d44: 00000213 li tp,0 + 80002d48: 00b00093 li ra,11 + 80002d4c: 00d00113 li sp,13 + 80002d50: 00000013 nop + 80002d54: 0020af33 slt t5,ra,sp + 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d5c: 00200293 li t0,2 + 80002d60: fe5214e3 bne tp,t0,80002d48 + 80002d64: 00100e93 li t4,1 + 80002d68: 01800193 li gp,24 + 80002d6c: 23df1263 bne t5,t4,80002f90 + +0000000080002d70 : + 80002d70: 00000213 li tp,0 + 80002d74: 00f00093 li ra,15 + 80002d78: 00d00113 li sp,13 + 80002d7c: 00000013 nop + 80002d80: 00000013 nop + 80002d84: 0020af33 slt t5,ra,sp + 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d8c: 00200293 li t0,2 + 80002d90: fe5212e3 bne tp,t0,80002d74 + 80002d94: 00000e93 li t4,0 + 80002d98: 01900193 li gp,25 + 80002d9c: 1fdf1a63 bne t5,t4,80002f90 + +0000000080002da0 : + 80002da0: 00000213 li tp,0 + 80002da4: 00a00093 li ra,10 + 80002da8: 00000013 nop + 80002dac: 00d00113 li sp,13 + 80002db0: 0020af33 slt t5,ra,sp + 80002db4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db8: 00200293 li t0,2 + 80002dbc: fe5214e3 bne tp,t0,80002da4 + 80002dc0: 00100e93 li t4,1 + 80002dc4: 01a00193 li gp,26 + 80002dc8: 1ddf1463 bne t5,t4,80002f90 + +0000000080002dcc : + 80002dcc: 00000213 li tp,0 + 80002dd0: 01000093 li ra,16 + 80002dd4: 00000013 nop + 80002dd8: 00d00113 li sp,13 + 80002ddc: 00000013 nop + 80002de0: 0020af33 slt t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fe5212e3 bne tp,t0,80002dd0 + 80002df0: 00000e93 li t4,0 + 80002df4: 01b00193 li gp,27 + 80002df8: 19df1c63 bne t5,t4,80002f90 + +0000000080002dfc : + 80002dfc: 00000213 li tp,0 + 80002e00: 00900093 li ra,9 + 80002e04: 00000013 nop + 80002e08: 00000013 nop + 80002e0c: 00d00113 li sp,13 + 80002e10: 0020af33 slt t5,ra,sp + 80002e14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e18: 00200293 li t0,2 + 80002e1c: fe5212e3 bne tp,t0,80002e00 + 80002e20: 00100e93 li t4,1 + 80002e24: 01c00193 li gp,28 + 80002e28: 17df1463 bne t5,t4,80002f90 + +0000000080002e2c : + 80002e2c: 00000213 li tp,0 + 80002e30: 00d00113 li sp,13 + 80002e34: 01100093 li ra,17 + 80002e38: 0020af33 slt t5,ra,sp + 80002e3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e40: 00200293 li t0,2 + 80002e44: fe5216e3 bne tp,t0,80002e30 + 80002e48: 00000e93 li t4,0 + 80002e4c: 01d00193 li gp,29 + 80002e50: 15df1063 bne t5,t4,80002f90 + +0000000080002e54 : + 80002e54: 00000213 li tp,0 + 80002e58: 00d00113 li sp,13 + 80002e5c: 00800093 li ra,8 + 80002e60: 00000013 nop + 80002e64: 0020af33 slt t5,ra,sp + 80002e68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e6c: 00200293 li t0,2 + 80002e70: fe5214e3 bne tp,t0,80002e58 + 80002e74: 00100e93 li t4,1 + 80002e78: 01e00193 li gp,30 + 80002e7c: 11df1a63 bne t5,t4,80002f90 + +0000000080002e80 : + 80002e80: 00000213 li tp,0 + 80002e84: 00d00113 li sp,13 + 80002e88: 01200093 li ra,18 + 80002e8c: 00000013 nop + 80002e90: 00000013 nop + 80002e94: 0020af33 slt t5,ra,sp + 80002e98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e9c: 00200293 li t0,2 + 80002ea0: fe5212e3 bne tp,t0,80002e84 + 80002ea4: 00000e93 li t4,0 + 80002ea8: 01f00193 li gp,31 + 80002eac: 0fdf1263 bne t5,t4,80002f90 + +0000000080002eb0 : + 80002eb0: 00000213 li tp,0 + 80002eb4: 00d00113 li sp,13 + 80002eb8: 00000013 nop + 80002ebc: 00700093 li ra,7 + 80002ec0: 0020af33 slt t5,ra,sp + 80002ec4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec8: 00200293 li t0,2 + 80002ecc: fe5214e3 bne tp,t0,80002eb4 + 80002ed0: 00100e93 li t4,1 + 80002ed4: 02000193 li gp,32 + 80002ed8: 0bdf1c63 bne t5,t4,80002f90 + +0000000080002edc : + 80002edc: 00000213 li tp,0 + 80002ee0: 00d00113 li sp,13 + 80002ee4: 00000013 nop + 80002ee8: 01300093 li ra,19 + 80002eec: 00000013 nop + 80002ef0: 0020af33 slt t5,ra,sp + 80002ef4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ef8: 00200293 li t0,2 + 80002efc: fe5212e3 bne tp,t0,80002ee0 + 80002f00: 00000e93 li t4,0 + 80002f04: 02100193 li gp,33 + 80002f08: 09df1463 bne t5,t4,80002f90 + +0000000080002f0c : + 80002f0c: 00000213 li tp,0 + 80002f10: 00d00113 li sp,13 + 80002f14: 00000013 nop + 80002f18: 00000013 nop + 80002f1c: 00600093 li ra,6 + 80002f20: 0020af33 slt t5,ra,sp + 80002f24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f28: 00200293 li t0,2 + 80002f2c: fe5212e3 bne tp,t0,80002f10 + 80002f30: 00100e93 li t4,1 + 80002f34: 02200193 li gp,34 + 80002f38: 05df1c63 bne t5,t4,80002f90 + +0000000080002f3c : + 80002f3c: fff00093 li ra,-1 + 80002f40: 00102133 sgtz sp,ra + 80002f44: 00000e93 li t4,0 + 80002f48: 02300193 li gp,35 + 80002f4c: 05d11263 bne sp,t4,80002f90 + +0000000080002f50 : + 80002f50: fff00093 li ra,-1 + 80002f54: 0000a133 sltz sp,ra + 80002f58: 00100e93 li t4,1 + 80002f5c: 02400193 li gp,36 + 80002f60: 03d11863 bne sp,t4,80002f90 + +0000000080002f64 : + 80002f64: 000020b3 sltz ra,zero + 80002f68: 00000e93 li t4,0 + 80002f6c: 02500193 li gp,37 + 80002f70: 03d09063 bne ra,t4,80002f90 + +0000000080002f74 : + 80002f74: 01000093 li ra,16 + 80002f78: 01e00113 li sp,30 + 80002f7c: 0020a033 slt zero,ra,sp + 80002f80: 00000e93 li t4,0 + 80002f84: 02600193 li gp,38 + 80002f88: 01d01463 bne zero,t4,80002f90 + 80002f8c: 00301a63 bne zero,gp,80002fa0 + +0000000080002f90 : + 80002f90: 00119513 slli a0,gp,0x1 + 80002f94: 00050063 beqz a0,80002f94 + 80002f98: 00156513 ori a0,a0,1 + 80002f9c: 00000073 ecall + +0000000080002fa0 : + 80002fa0: 00100513 li a0,1 + 80002fa4: 00000073 ecall + 80002fa8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slt.elf b/test/riscv/tests/rv64ui-v-slt.elf new file mode 100644 index 00000000..318b70db Binary files /dev/null and b/test/riscv/tests/rv64ui-v-slt.elf differ diff --git a/test/riscv/tests/rv64ui-v-slti.dump b/test/riscv/tests/rv64ui-v-slti.dump new file mode 100644 index 00000000..56b39654 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-slti.dump @@ -0,0 +1,1043 @@ + +rv64ui-v-slti: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 90068693 addi a3,a3,-1792 # 80002d58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 93460613 addi a2,a2,-1740 # 80002de8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 8fc60613 addi a2,a2,-1796 # 80002e00 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 84c68693 addi a3,a3,-1972 # 80002da0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 86868693 addi a3,a3,-1944 # 80002ed8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7e860613 addi a2,a2,2024 # 80002eb0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 71c68693 addi a3,a3,1820 # 80002f08 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 63c68693 addi a3,a3,1596 # 80002e78 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5cc68693 addi a3,a3,1484 # 80002e40 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00800793 li a5,8 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 01e147b7 lui a5,0x1e14 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 4e578793 addi a5,a5,1253 # 1e144e5 <_start-0x7e1ebb1b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 0000af13 slti t5,ra,0 + 80002ad0: 00000e93 li t4,0 + 80002ad4: 00200193 li gp,2 + 80002ad8: 27df1263 bne t5,t4,80002d3c + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 0010af13 slti t5,ra,1 + 80002ae4: 00000e93 li t4,0 + 80002ae8: 00300193 li gp,3 + 80002aec: 25df1863 bne t5,t4,80002d3c + +0000000080002af0 : + 80002af0: 00300093 li ra,3 + 80002af4: 0070af13 slti t5,ra,7 + 80002af8: 00100e93 li t4,1 + 80002afc: 00400193 li gp,4 + 80002b00: 23df1e63 bne t5,t4,80002d3c + +0000000080002b04 : + 80002b04: 00700093 li ra,7 + 80002b08: 0030af13 slti t5,ra,3 + 80002b0c: 00000e93 li t4,0 + 80002b10: 00500193 li gp,5 + 80002b14: 23df1463 bne t5,t4,80002d3c + +0000000080002b18 : + 80002b18: 00000093 li ra,0 + 80002b1c: 8000af13 slti t5,ra,-2048 + 80002b20: 00000e93 li t4,0 + 80002b24: 00600193 li gp,6 + 80002b28: 21df1a63 bne t5,t4,80002d3c + +0000000080002b2c : + 80002b2c: 800000b7 lui ra,0x80000 + 80002b30: 0000af13 slti t5,ra,0 + 80002b34: 00100e93 li t4,1 + 80002b38: 00700193 li gp,7 + 80002b3c: 21df1063 bne t5,t4,80002d3c + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: 8000af13 slti t5,ra,-2048 + 80002b48: 00100e93 li t4,1 + 80002b4c: 00800193 li gp,8 + 80002b50: 1fdf1663 bne t5,t4,80002d3c + +0000000080002b54 : + 80002b54: 00000093 li ra,0 + 80002b58: 7ff0af13 slti t5,ra,2047 + 80002b5c: 00100e93 li t4,1 + 80002b60: 00900193 li gp,9 + 80002b64: 1ddf1c63 bne t5,t4,80002d3c + +0000000080002b68 : + 80002b68: 800000b7 lui ra,0x80000 + 80002b6c: fff0809b addiw ra,ra,-1 + 80002b70: 0000af13 slti t5,ra,0 + 80002b74: 00000e93 li t4,0 + 80002b78: 00a00193 li gp,10 + 80002b7c: 1ddf1063 bne t5,t4,80002d3c + +0000000080002b80 : + 80002b80: 800000b7 lui ra,0x80000 + 80002b84: fff0809b addiw ra,ra,-1 + 80002b88: 7ff0af13 slti t5,ra,2047 + 80002b8c: 00000e93 li t4,0 + 80002b90: 00b00193 li gp,11 + 80002b94: 1bdf1463 bne t5,t4,80002d3c + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: 7ff0af13 slti t5,ra,2047 + 80002ba0: 00100e93 li t4,1 + 80002ba4: 00c00193 li gp,12 + 80002ba8: 19df1a63 bne t5,t4,80002d3c + +0000000080002bac : + 80002bac: 800000b7 lui ra,0x80000 + 80002bb0: fff0809b addiw ra,ra,-1 + 80002bb4: 8000af13 slti t5,ra,-2048 + 80002bb8: 00000e93 li t4,0 + 80002bbc: 00d00193 li gp,13 + 80002bc0: 17df1e63 bne t5,t4,80002d3c + +0000000080002bc4 : + 80002bc4: 00000093 li ra,0 + 80002bc8: fff0af13 slti t5,ra,-1 + 80002bcc: 00000e93 li t4,0 + 80002bd0: 00e00193 li gp,14 + 80002bd4: 17df1463 bne t5,t4,80002d3c + +0000000080002bd8 : + 80002bd8: fff00093 li ra,-1 + 80002bdc: 0010af13 slti t5,ra,1 + 80002be0: 00100e93 li t4,1 + 80002be4: 00f00193 li gp,15 + 80002be8: 15df1a63 bne t5,t4,80002d3c + +0000000080002bec : + 80002bec: fff00093 li ra,-1 + 80002bf0: fff0af13 slti t5,ra,-1 + 80002bf4: 00000e93 li t4,0 + 80002bf8: 01000193 li gp,16 + 80002bfc: 15df1063 bne t5,t4,80002d3c + +0000000080002c00 : + 80002c00: 00b00093 li ra,11 + 80002c04: 00d0a093 slti ra,ra,13 + 80002c08: 00100e93 li t4,1 + 80002c0c: 01100193 li gp,17 + 80002c10: 13d09663 bne ra,t4,80002d3c + +0000000080002c14 : + 80002c14: 00000213 li tp,0 + 80002c18: 00f00093 li ra,15 + 80002c1c: 00a0af13 slti t5,ra,10 + 80002c20: 000f0313 mv t1,t5 + 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c28: 00200293 li t0,2 + 80002c2c: fe5216e3 bne tp,t0,80002c18 + 80002c30: 00000e93 li t4,0 + 80002c34: 01200193 li gp,18 + 80002c38: 11d31263 bne t1,t4,80002d3c + +0000000080002c3c : + 80002c3c: 00000213 li tp,0 + 80002c40: 00a00093 li ra,10 + 80002c44: 0100af13 slti t5,ra,16 + 80002c48: 00000013 nop + 80002c4c: 000f0313 mv t1,t5 + 80002c50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c54: 00200293 li t0,2 + 80002c58: fe5214e3 bne tp,t0,80002c40 + 80002c5c: 00100e93 li t4,1 + 80002c60: 01300193 li gp,19 + 80002c64: 0dd31c63 bne t1,t4,80002d3c + +0000000080002c68 : + 80002c68: 00000213 li tp,0 + 80002c6c: 01000093 li ra,16 + 80002c70: 0090af13 slti t5,ra,9 + 80002c74: 00000013 nop + 80002c78: 00000013 nop + 80002c7c: 000f0313 mv t1,t5 + 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c84: 00200293 li t0,2 + 80002c88: fe5212e3 bne tp,t0,80002c6c + 80002c8c: 00000e93 li t4,0 + 80002c90: 01400193 li gp,20 + 80002c94: 0bd31463 bne t1,t4,80002d3c + +0000000080002c98 : + 80002c98: 00000213 li tp,0 + 80002c9c: 00b00093 li ra,11 + 80002ca0: 00f0af13 slti t5,ra,15 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5218e3 bne tp,t0,80002c9c + 80002cb0: 00100e93 li t4,1 + 80002cb4: 01500193 li gp,21 + 80002cb8: 09df1263 bne t5,t4,80002d3c + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 01100093 li ra,17 + 80002cc4: 00000013 nop + 80002cc8: 0080af13 slti t5,ra,8 + 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd0: 00200293 li t0,2 + 80002cd4: fe5216e3 bne tp,t0,80002cc0 + 80002cd8: 00000e93 li t4,0 + 80002cdc: 01600193 li gp,22 + 80002ce0: 05df1e63 bne t5,t4,80002d3c + +0000000080002ce4 : + 80002ce4: 00000213 li tp,0 + 80002ce8: 00c00093 li ra,12 + 80002cec: 00000013 nop + 80002cf0: 00000013 nop + 80002cf4: 00e0af13 slti t5,ra,14 + 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cfc: 00200293 li t0,2 + 80002d00: fe5214e3 bne tp,t0,80002ce8 + 80002d04: 00100e93 li t4,1 + 80002d08: 01700193 li gp,23 + 80002d0c: 03df1863 bne t5,t4,80002d3c + +0000000080002d10 : + 80002d10: fff02093 slti ra,zero,-1 + 80002d14: 00000e93 li t4,0 + 80002d18: 01800193 li gp,24 + 80002d1c: 03d09063 bne ra,t4,80002d3c + +0000000080002d20 : + 80002d20: 00ff00b7 lui ra,0xff0 + 80002d24: 0ff0809b addiw ra,ra,255 + 80002d28: fff0a013 slti zero,ra,-1 + 80002d2c: 00000e93 li t4,0 + 80002d30: 01900193 li gp,25 + 80002d34: 01d01463 bne zero,t4,80002d3c + 80002d38: 00301a63 bne zero,gp,80002d4c + +0000000080002d3c : + 80002d3c: 00119513 slli a0,gp,0x1 + 80002d40: 00050063 beqz a0,80002d40 + 80002d44: 00156513 ori a0,a0,1 + 80002d48: 00000073 ecall + +0000000080002d4c : + 80002d4c: 00100513 li a0,1 + 80002d50: 00000073 ecall + 80002d54: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slti.elf b/test/riscv/tests/rv64ui-v-slti.elf new file mode 100644 index 00000000..477b7049 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-slti.elf differ diff --git a/test/riscv/tests/rv64ui-v-sltiu.dump b/test/riscv/tests/rv64ui-v-sltiu.dump new file mode 100644 index 00000000..98f8b1a5 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sltiu.dump @@ -0,0 +1,1043 @@ + +rv64ui-v-sltiu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 90068693 addi a3,a3,-1792 # 80002d58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 93460613 addi a2,a2,-1740 # 80002de8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 8fc60613 addi a2,a2,-1796 # 80002e00 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 84c68693 addi a3,a3,-1972 # 80002da0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 86868693 addi a3,a3,-1944 # 80002ed8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 7e860613 addi a2,a2,2024 # 80002eb0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 71c68693 addi a3,a3,1820 # 80002f08 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 63c68693 addi a3,a3,1596 # 80002e78 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5cc68693 addi a3,a3,1484 # 80002e40 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02100793 li a5,33 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 04ec47b7 lui a5,0x4ec4 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b3078793 addi a5,a5,-1232 # 4ec3b30 <_start-0x7b13c4d0> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 0000bf13 sltiu t5,ra,0 + 80002ad0: 00000e93 li t4,0 + 80002ad4: 00200193 li gp,2 + 80002ad8: 27df1263 bne t5,t4,80002d3c + +0000000080002adc : + 80002adc: 00100093 li ra,1 + 80002ae0: 0010bf13 seqz t5,ra + 80002ae4: 00000e93 li t4,0 + 80002ae8: 00300193 li gp,3 + 80002aec: 25df1863 bne t5,t4,80002d3c + +0000000080002af0 : + 80002af0: 00300093 li ra,3 + 80002af4: 0070bf13 sltiu t5,ra,7 + 80002af8: 00100e93 li t4,1 + 80002afc: 00400193 li gp,4 + 80002b00: 23df1e63 bne t5,t4,80002d3c + +0000000080002b04 : + 80002b04: 00700093 li ra,7 + 80002b08: 0030bf13 sltiu t5,ra,3 + 80002b0c: 00000e93 li t4,0 + 80002b10: 00500193 li gp,5 + 80002b14: 23df1463 bne t5,t4,80002d3c + +0000000080002b18 : + 80002b18: 00000093 li ra,0 + 80002b1c: 8000bf13 sltiu t5,ra,-2048 + 80002b20: 00100e93 li t4,1 + 80002b24: 00600193 li gp,6 + 80002b28: 21df1a63 bne t5,t4,80002d3c + +0000000080002b2c : + 80002b2c: 800000b7 lui ra,0x80000 + 80002b30: 0000bf13 sltiu t5,ra,0 + 80002b34: 00000e93 li t4,0 + 80002b38: 00700193 li gp,7 + 80002b3c: 21df1063 bne t5,t4,80002d3c + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: 8000bf13 sltiu t5,ra,-2048 + 80002b48: 00100e93 li t4,1 + 80002b4c: 00800193 li gp,8 + 80002b50: 1fdf1663 bne t5,t4,80002d3c + +0000000080002b54 : + 80002b54: 00000093 li ra,0 + 80002b58: 7ff0bf13 sltiu t5,ra,2047 + 80002b5c: 00100e93 li t4,1 + 80002b60: 00900193 li gp,9 + 80002b64: 1ddf1c63 bne t5,t4,80002d3c + +0000000080002b68 : + 80002b68: 800000b7 lui ra,0x80000 + 80002b6c: fff0809b addiw ra,ra,-1 + 80002b70: 0000bf13 sltiu t5,ra,0 + 80002b74: 00000e93 li t4,0 + 80002b78: 00a00193 li gp,10 + 80002b7c: 1ddf1063 bne t5,t4,80002d3c + +0000000080002b80 : + 80002b80: 800000b7 lui ra,0x80000 + 80002b84: fff0809b addiw ra,ra,-1 + 80002b88: 7ff0bf13 sltiu t5,ra,2047 + 80002b8c: 00000e93 li t4,0 + 80002b90: 00b00193 li gp,11 + 80002b94: 1bdf1463 bne t5,t4,80002d3c + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: 7ff0bf13 sltiu t5,ra,2047 + 80002ba0: 00000e93 li t4,0 + 80002ba4: 00c00193 li gp,12 + 80002ba8: 19df1a63 bne t5,t4,80002d3c + +0000000080002bac : + 80002bac: 800000b7 lui ra,0x80000 + 80002bb0: fff0809b addiw ra,ra,-1 + 80002bb4: 8000bf13 sltiu t5,ra,-2048 + 80002bb8: 00100e93 li t4,1 + 80002bbc: 00d00193 li gp,13 + 80002bc0: 17df1e63 bne t5,t4,80002d3c + +0000000080002bc4 : + 80002bc4: 00000093 li ra,0 + 80002bc8: fff0bf13 sltiu t5,ra,-1 + 80002bcc: 00100e93 li t4,1 + 80002bd0: 00e00193 li gp,14 + 80002bd4: 17df1463 bne t5,t4,80002d3c + +0000000080002bd8 : + 80002bd8: fff00093 li ra,-1 + 80002bdc: 0010bf13 seqz t5,ra + 80002be0: 00000e93 li t4,0 + 80002be4: 00f00193 li gp,15 + 80002be8: 15df1a63 bne t5,t4,80002d3c + +0000000080002bec : + 80002bec: fff00093 li ra,-1 + 80002bf0: fff0bf13 sltiu t5,ra,-1 + 80002bf4: 00000e93 li t4,0 + 80002bf8: 01000193 li gp,16 + 80002bfc: 15df1063 bne t5,t4,80002d3c + +0000000080002c00 : + 80002c00: 00b00093 li ra,11 + 80002c04: 00d0b093 sltiu ra,ra,13 + 80002c08: 00100e93 li t4,1 + 80002c0c: 01100193 li gp,17 + 80002c10: 13d09663 bne ra,t4,80002d3c + +0000000080002c14 : + 80002c14: 00000213 li tp,0 + 80002c18: 00f00093 li ra,15 + 80002c1c: 00a0bf13 sltiu t5,ra,10 + 80002c20: 000f0313 mv t1,t5 + 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c28: 00200293 li t0,2 + 80002c2c: fe5216e3 bne tp,t0,80002c18 + 80002c30: 00000e93 li t4,0 + 80002c34: 01200193 li gp,18 + 80002c38: 11d31263 bne t1,t4,80002d3c + +0000000080002c3c : + 80002c3c: 00000213 li tp,0 + 80002c40: 00a00093 li ra,10 + 80002c44: 0100bf13 sltiu t5,ra,16 + 80002c48: 00000013 nop + 80002c4c: 000f0313 mv t1,t5 + 80002c50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c54: 00200293 li t0,2 + 80002c58: fe5214e3 bne tp,t0,80002c40 + 80002c5c: 00100e93 li t4,1 + 80002c60: 01300193 li gp,19 + 80002c64: 0dd31c63 bne t1,t4,80002d3c + +0000000080002c68 : + 80002c68: 00000213 li tp,0 + 80002c6c: 01000093 li ra,16 + 80002c70: 0090bf13 sltiu t5,ra,9 + 80002c74: 00000013 nop + 80002c78: 00000013 nop + 80002c7c: 000f0313 mv t1,t5 + 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c84: 00200293 li t0,2 + 80002c88: fe5212e3 bne tp,t0,80002c6c + 80002c8c: 00000e93 li t4,0 + 80002c90: 01400193 li gp,20 + 80002c94: 0bd31463 bne t1,t4,80002d3c + +0000000080002c98 : + 80002c98: 00000213 li tp,0 + 80002c9c: 00b00093 li ra,11 + 80002ca0: 00f0bf13 sltiu t5,ra,15 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5218e3 bne tp,t0,80002c9c + 80002cb0: 00100e93 li t4,1 + 80002cb4: 01500193 li gp,21 + 80002cb8: 09df1263 bne t5,t4,80002d3c + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 01100093 li ra,17 + 80002cc4: 00000013 nop + 80002cc8: 0080bf13 sltiu t5,ra,8 + 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd0: 00200293 li t0,2 + 80002cd4: fe5216e3 bne tp,t0,80002cc0 + 80002cd8: 00000e93 li t4,0 + 80002cdc: 01600193 li gp,22 + 80002ce0: 05df1e63 bne t5,t4,80002d3c + +0000000080002ce4 : + 80002ce4: 00000213 li tp,0 + 80002ce8: 00c00093 li ra,12 + 80002cec: 00000013 nop + 80002cf0: 00000013 nop + 80002cf4: 00e0bf13 sltiu t5,ra,14 + 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cfc: 00200293 li t0,2 + 80002d00: fe5214e3 bne tp,t0,80002ce8 + 80002d04: 00100e93 li t4,1 + 80002d08: 01700193 li gp,23 + 80002d0c: 03df1863 bne t5,t4,80002d3c + +0000000080002d10 : + 80002d10: fff03093 sltiu ra,zero,-1 + 80002d14: 00100e93 li t4,1 + 80002d18: 01800193 li gp,24 + 80002d1c: 03d09063 bne ra,t4,80002d3c + +0000000080002d20 : + 80002d20: 00ff00b7 lui ra,0xff0 + 80002d24: 0ff0809b addiw ra,ra,255 + 80002d28: fff0b013 sltiu zero,ra,-1 + 80002d2c: 00000e93 li t4,0 + 80002d30: 01900193 li gp,25 + 80002d34: 01d01463 bne zero,t4,80002d3c + 80002d38: 00301a63 bne zero,gp,80002d4c + +0000000080002d3c : + 80002d3c: 00119513 slli a0,gp,0x1 + 80002d40: 00050063 beqz a0,80002d40 + 80002d44: 00156513 ori a0,a0,1 + 80002d48: 00000073 ecall + +0000000080002d4c : + 80002d4c: 00100513 li a0,1 + 80002d50: 00000073 ecall + 80002d54: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sltiu.elf b/test/riscv/tests/rv64ui-v-sltiu.elf new file mode 100644 index 00000000..197c5002 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sltiu.elf differ diff --git a/test/riscv/tests/rv64ui-v-sltu.dump b/test/riscv/tests/rv64ui-v-sltu.dump new file mode 100644 index 00000000..281d657f --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sltu.dump @@ -0,0 +1,1235 @@ + +rv64ui-v-sltu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b9868693 addi a3,a3,-1128 # 80002ff0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: bcc60613 addi a2,a2,-1076 # 80003080 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b9460613 addi a2,a2,-1132 # 80003098 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: ae468693 addi a3,a3,-1308 # 80003038 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b0068693 addi a3,a3,-1280 # 80003170 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a8060613 addi a2,a2,-1408 # 80003148 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 9b468693 addi a3,a3,-1612 # 800031a0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 8d468693 addi a3,a3,-1836 # 80003110 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 86468693 addi a3,a3,-1948 # 800030d8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00c00793 li a5,12 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 069e57b7 lui a5,0x69e5 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 8d578793 addi a5,a5,-1835 # 69e48d5 <_start-0x7961b72b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 0020bf33 sltu t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4fdf1c63 bne t5,t4,80002fd4 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0020bf33 sltu t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 4fdf1063 bne t5,t4,80002fd4 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 0020bf33 sltu t5,ra,sp + 80002b04: 00100e93 li t4,1 + 80002b08: 00400193 li gp,4 + 80002b0c: 4ddf1463 bne t5,t4,80002fd4 + +0000000080002b10 : + 80002b10: 00700093 li ra,7 + 80002b14: 00300113 li sp,3 + 80002b18: 0020bf33 sltu t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 4bdf1863 bne t5,t4,80002fd4 + +0000000080002b28 : + 80002b28: 00000093 li ra,0 + 80002b2c: 00020137 lui sp,0x20 + 80002b30: fff1011b addiw sp,sp,-1 + 80002b34: 00f11113 slli sp,sp,0xf + 80002b38: 0020bf33 sltu t5,ra,sp + 80002b3c: 00100e93 li t4,1 + 80002b40: 00600193 li gp,6 + 80002b44: 49df1863 bne t5,t4,80002fd4 + +0000000080002b48 : + 80002b48: 0010009b addiw ra,zero,1 + 80002b4c: 01f09093 slli ra,ra,0x1f + 80002b50: 00000113 li sp,0 + 80002b54: 0020bf33 sltu t5,ra,sp + 80002b58: 00000e93 li t4,0 + 80002b5c: 00700193 li gp,7 + 80002b60: 47df1a63 bne t5,t4,80002fd4 + +0000000080002b64 : + 80002b64: 0010009b addiw ra,zero,1 + 80002b68: 01f09093 slli ra,ra,0x1f + 80002b6c: 00020137 lui sp,0x20 + 80002b70: fff1011b addiw sp,sp,-1 + 80002b74: 00f11113 slli sp,sp,0xf + 80002b78: 0020bf33 sltu t5,ra,sp + 80002b7c: 00100e93 li t4,1 + 80002b80: 00800193 li gp,8 + 80002b84: 45df1863 bne t5,t4,80002fd4 + +0000000080002b88 : + 80002b88: 00000093 li ra,0 + 80002b8c: 00008137 lui sp,0x8 + 80002b90: fff1011b addiw sp,sp,-1 + 80002b94: 0020bf33 sltu t5,ra,sp + 80002b98: 00100e93 li t4,1 + 80002b9c: 00900193 li gp,9 + 80002ba0: 43df1a63 bne t5,t4,80002fd4 + +0000000080002ba4 : + 80002ba4: 800000b7 lui ra,0x80000 + 80002ba8: fff0809b addiw ra,ra,-1 + 80002bac: 00000113 li sp,0 + 80002bb0: 0020bf33 sltu t5,ra,sp + 80002bb4: 00000e93 li t4,0 + 80002bb8: 00a00193 li gp,10 + 80002bbc: 41df1c63 bne t5,t4,80002fd4 + +0000000080002bc0 : + 80002bc0: 800000b7 lui ra,0x80000 + 80002bc4: fff0809b addiw ra,ra,-1 + 80002bc8: 00008137 lui sp,0x8 + 80002bcc: fff1011b addiw sp,sp,-1 + 80002bd0: 0020bf33 sltu t5,ra,sp + 80002bd4: 00000e93 li t4,0 + 80002bd8: 00b00193 li gp,11 + 80002bdc: 3fdf1c63 bne t5,t4,80002fd4 + +0000000080002be0 : + 80002be0: 0010009b addiw ra,zero,1 + 80002be4: 01f09093 slli ra,ra,0x1f + 80002be8: 00008137 lui sp,0x8 + 80002bec: fff1011b addiw sp,sp,-1 + 80002bf0: 0020bf33 sltu t5,ra,sp + 80002bf4: 00000e93 li t4,0 + 80002bf8: 00c00193 li gp,12 + 80002bfc: 3ddf1c63 bne t5,t4,80002fd4 + +0000000080002c00 : + 80002c00: 800000b7 lui ra,0x80000 + 80002c04: fff0809b addiw ra,ra,-1 + 80002c08: 00020137 lui sp,0x20 + 80002c0c: fff1011b addiw sp,sp,-1 + 80002c10: 00f11113 slli sp,sp,0xf + 80002c14: 0020bf33 sltu t5,ra,sp + 80002c18: 00100e93 li t4,1 + 80002c1c: 00d00193 li gp,13 + 80002c20: 3bdf1a63 bne t5,t4,80002fd4 + +0000000080002c24 : + 80002c24: 00000093 li ra,0 + 80002c28: 0010011b addiw sp,zero,1 + 80002c2c: 02011113 slli sp,sp,0x20 + 80002c30: fff10113 addi sp,sp,-1 # 1ffff <_start-0x7ffe0001> + 80002c34: 0020bf33 sltu t5,ra,sp + 80002c38: 00100e93 li t4,1 + 80002c3c: 00e00193 li gp,14 + 80002c40: 39df1a63 bne t5,t4,80002fd4 + +0000000080002c44 : + 80002c44: 0010009b addiw ra,zero,1 + 80002c48: 02009093 slli ra,ra,0x20 + 80002c4c: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> + 80002c50: 00100113 li sp,1 + 80002c54: 0020bf33 sltu t5,ra,sp + 80002c58: 00000e93 li t4,0 + 80002c5c: 00f00193 li gp,15 + 80002c60: 37df1a63 bne t5,t4,80002fd4 + +0000000080002c64 : + 80002c64: 0010009b addiw ra,zero,1 + 80002c68: 02009093 slli ra,ra,0x20 + 80002c6c: fff08093 addi ra,ra,-1 + 80002c70: 0010011b addiw sp,zero,1 + 80002c74: 02011113 slli sp,sp,0x20 + 80002c78: fff10113 addi sp,sp,-1 + 80002c7c: 0020bf33 sltu t5,ra,sp + 80002c80: 00000e93 li t4,0 + 80002c84: 01000193 li gp,16 + 80002c88: 35df1663 bne t5,t4,80002fd4 + +0000000080002c8c : + 80002c8c: 00e00093 li ra,14 + 80002c90: 00d00113 li sp,13 + 80002c94: 0020b0b3 sltu ra,ra,sp + 80002c98: 00000e93 li t4,0 + 80002c9c: 01100193 li gp,17 + 80002ca0: 33d09a63 bne ra,t4,80002fd4 + +0000000080002ca4 : + 80002ca4: 00b00093 li ra,11 + 80002ca8: 00d00113 li sp,13 + 80002cac: 0020b133 sltu sp,ra,sp + 80002cb0: 00100e93 li t4,1 + 80002cb4: 01200193 li gp,18 + 80002cb8: 31d11e63 bne sp,t4,80002fd4 + +0000000080002cbc : + 80002cbc: 00d00093 li ra,13 + 80002cc0: 0010b0b3 sltu ra,ra,ra + 80002cc4: 00000e93 li t4,0 + 80002cc8: 01300193 li gp,19 + 80002ccc: 31d09463 bne ra,t4,80002fd4 + +0000000080002cd0 : + 80002cd0: 00000213 li tp,0 + 80002cd4: 00b00093 li ra,11 + 80002cd8: 00d00113 li sp,13 + 80002cdc: 0020bf33 sltu t5,ra,sp + 80002ce0: 000f0313 mv t1,t5 + 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce8: 00200293 li t0,2 + 80002cec: fe5214e3 bne tp,t0,80002cd4 + 80002cf0: 00100e93 li t4,1 + 80002cf4: 01400193 li gp,20 + 80002cf8: 2dd31e63 bne t1,t4,80002fd4 + +0000000080002cfc : + 80002cfc: 00000213 li tp,0 + 80002d00: 00e00093 li ra,14 + 80002d04: 00d00113 li sp,13 + 80002d08: 0020bf33 sltu t5,ra,sp + 80002d0c: 00000013 nop + 80002d10: 000f0313 mv t1,t5 + 80002d14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d18: 00200293 li t0,2 + 80002d1c: fe5212e3 bne tp,t0,80002d00 + 80002d20: 00000e93 li t4,0 + 80002d24: 01500193 li gp,21 + 80002d28: 2bd31663 bne t1,t4,80002fd4 + +0000000080002d2c : + 80002d2c: 00000213 li tp,0 + 80002d30: 00c00093 li ra,12 + 80002d34: 00d00113 li sp,13 + 80002d38: 0020bf33 sltu t5,ra,sp + 80002d3c: 00000013 nop + 80002d40: 00000013 nop + 80002d44: 000f0313 mv t1,t5 + 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d4c: 00200293 li t0,2 + 80002d50: fe5210e3 bne tp,t0,80002d30 + 80002d54: 00100e93 li t4,1 + 80002d58: 01600193 li gp,22 + 80002d5c: 27d31c63 bne t1,t4,80002fd4 + +0000000080002d60 : + 80002d60: 00000213 li tp,0 + 80002d64: 00e00093 li ra,14 + 80002d68: 00d00113 li sp,13 + 80002d6c: 0020bf33 sltu t5,ra,sp + 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d74: 00200293 li t0,2 + 80002d78: fe5216e3 bne tp,t0,80002d64 + 80002d7c: 00000e93 li t4,0 + 80002d80: 01700193 li gp,23 + 80002d84: 25df1863 bne t5,t4,80002fd4 + +0000000080002d88 : + 80002d88: 00000213 li tp,0 + 80002d8c: 00b00093 li ra,11 + 80002d90: 00d00113 li sp,13 + 80002d94: 00000013 nop + 80002d98: 0020bf33 sltu t5,ra,sp + 80002d9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da0: 00200293 li t0,2 + 80002da4: fe5214e3 bne tp,t0,80002d8c + 80002da8: 00100e93 li t4,1 + 80002dac: 01800193 li gp,24 + 80002db0: 23df1263 bne t5,t4,80002fd4 + +0000000080002db4 : + 80002db4: 00000213 li tp,0 + 80002db8: 00f00093 li ra,15 + 80002dbc: 00d00113 li sp,13 + 80002dc0: 00000013 nop + 80002dc4: 00000013 nop + 80002dc8: 0020bf33 sltu t5,ra,sp + 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd0: 00200293 li t0,2 + 80002dd4: fe5212e3 bne tp,t0,80002db8 + 80002dd8: 00000e93 li t4,0 + 80002ddc: 01900193 li gp,25 + 80002de0: 1fdf1a63 bne t5,t4,80002fd4 + +0000000080002de4 : + 80002de4: 00000213 li tp,0 + 80002de8: 00a00093 li ra,10 + 80002dec: 00000013 nop + 80002df0: 00d00113 li sp,13 + 80002df4: 0020bf33 sltu t5,ra,sp + 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dfc: 00200293 li t0,2 + 80002e00: fe5214e3 bne tp,t0,80002de8 + 80002e04: 00100e93 li t4,1 + 80002e08: 01a00193 li gp,26 + 80002e0c: 1ddf1463 bne t5,t4,80002fd4 + +0000000080002e10 : + 80002e10: 00000213 li tp,0 + 80002e14: 01000093 li ra,16 + 80002e18: 00000013 nop + 80002e1c: 00d00113 li sp,13 + 80002e20: 00000013 nop + 80002e24: 0020bf33 sltu t5,ra,sp + 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e2c: 00200293 li t0,2 + 80002e30: fe5212e3 bne tp,t0,80002e14 + 80002e34: 00000e93 li t4,0 + 80002e38: 01b00193 li gp,27 + 80002e3c: 19df1c63 bne t5,t4,80002fd4 + +0000000080002e40 : + 80002e40: 00000213 li tp,0 + 80002e44: 00900093 li ra,9 + 80002e48: 00000013 nop + 80002e4c: 00000013 nop + 80002e50: 00d00113 li sp,13 + 80002e54: 0020bf33 sltu t5,ra,sp + 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e5c: 00200293 li t0,2 + 80002e60: fe5212e3 bne tp,t0,80002e44 + 80002e64: 00100e93 li t4,1 + 80002e68: 01c00193 li gp,28 + 80002e6c: 17df1463 bne t5,t4,80002fd4 + +0000000080002e70 : + 80002e70: 00000213 li tp,0 + 80002e74: 00d00113 li sp,13 + 80002e78: 01100093 li ra,17 + 80002e7c: 0020bf33 sltu t5,ra,sp + 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e84: 00200293 li t0,2 + 80002e88: fe5216e3 bne tp,t0,80002e74 + 80002e8c: 00000e93 li t4,0 + 80002e90: 01d00193 li gp,29 + 80002e94: 15df1063 bne t5,t4,80002fd4 + +0000000080002e98 : + 80002e98: 00000213 li tp,0 + 80002e9c: 00d00113 li sp,13 + 80002ea0: 00800093 li ra,8 + 80002ea4: 00000013 nop + 80002ea8: 0020bf33 sltu t5,ra,sp + 80002eac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb0: 00200293 li t0,2 + 80002eb4: fe5214e3 bne tp,t0,80002e9c + 80002eb8: 00100e93 li t4,1 + 80002ebc: 01e00193 li gp,30 + 80002ec0: 11df1a63 bne t5,t4,80002fd4 + +0000000080002ec4 : + 80002ec4: 00000213 li tp,0 + 80002ec8: 00d00113 li sp,13 + 80002ecc: 01200093 li ra,18 + 80002ed0: 00000013 nop + 80002ed4: 00000013 nop + 80002ed8: 0020bf33 sltu t5,ra,sp + 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee0: 00200293 li t0,2 + 80002ee4: fe5212e3 bne tp,t0,80002ec8 + 80002ee8: 00000e93 li t4,0 + 80002eec: 01f00193 li gp,31 + 80002ef0: 0fdf1263 bne t5,t4,80002fd4 + +0000000080002ef4 : + 80002ef4: 00000213 li tp,0 + 80002ef8: 00d00113 li sp,13 + 80002efc: 00000013 nop + 80002f00: 00700093 li ra,7 + 80002f04: 0020bf33 sltu t5,ra,sp + 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f0c: 00200293 li t0,2 + 80002f10: fe5214e3 bne tp,t0,80002ef8 + 80002f14: 00100e93 li t4,1 + 80002f18: 02000193 li gp,32 + 80002f1c: 0bdf1c63 bne t5,t4,80002fd4 + +0000000080002f20 : + 80002f20: 00000213 li tp,0 + 80002f24: 00d00113 li sp,13 + 80002f28: 00000013 nop + 80002f2c: 01300093 li ra,19 + 80002f30: 00000013 nop + 80002f34: 0020bf33 sltu t5,ra,sp + 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f3c: 00200293 li t0,2 + 80002f40: fe5212e3 bne tp,t0,80002f24 + 80002f44: 00000e93 li t4,0 + 80002f48: 02100193 li gp,33 + 80002f4c: 09df1463 bne t5,t4,80002fd4 + +0000000080002f50 : + 80002f50: 00000213 li tp,0 + 80002f54: 00d00113 li sp,13 + 80002f58: 00000013 nop + 80002f5c: 00000013 nop + 80002f60: 00600093 li ra,6 + 80002f64: 0020bf33 sltu t5,ra,sp + 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f6c: 00200293 li t0,2 + 80002f70: fe5212e3 bne tp,t0,80002f54 + 80002f74: 00100e93 li t4,1 + 80002f78: 02200193 li gp,34 + 80002f7c: 05df1c63 bne t5,t4,80002fd4 + +0000000080002f80 : + 80002f80: fff00093 li ra,-1 + 80002f84: 00103133 snez sp,ra + 80002f88: 00100e93 li t4,1 + 80002f8c: 02300193 li gp,35 + 80002f90: 05d11263 bne sp,t4,80002fd4 + +0000000080002f94 : + 80002f94: fff00093 li ra,-1 + 80002f98: 0000b133 sltu sp,ra,zero + 80002f9c: 00000e93 li t4,0 + 80002fa0: 02400193 li gp,36 + 80002fa4: 03d11863 bne sp,t4,80002fd4 + +0000000080002fa8 : + 80002fa8: 000030b3 snez ra,zero + 80002fac: 00000e93 li t4,0 + 80002fb0: 02500193 li gp,37 + 80002fb4: 03d09063 bne ra,t4,80002fd4 + +0000000080002fb8 : + 80002fb8: 01000093 li ra,16 + 80002fbc: 01e00113 li sp,30 + 80002fc0: 0020b033 sltu zero,ra,sp + 80002fc4: 00000e93 li t4,0 + 80002fc8: 02600193 li gp,38 + 80002fcc: 01d01463 bne zero,t4,80002fd4 + 80002fd0: 00301a63 bne zero,gp,80002fe4 + +0000000080002fd4 : + 80002fd4: 00119513 slli a0,gp,0x1 + 80002fd8: 00050063 beqz a0,80002fd8 + 80002fdc: 00156513 ori a0,a0,1 + 80002fe0: 00000073 ecall + +0000000080002fe4 : + 80002fe4: 00100513 li a0,1 + 80002fe8: 00000073 ecall + 80002fec: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sltu.elf b/test/riscv/tests/rv64ui-v-sltu.elf new file mode 100644 index 00000000..0bd9f902 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sltu.elf differ diff --git a/test/riscv/tests/rv64ui-v-sra.dump b/test/riscv/tests/rv64ui-v-sra.dump new file mode 100644 index 00000000..37705cb9 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sra.dump @@ -0,0 +1,1281 @@ + +rv64ui-v-sra: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c2868693 addi a3,a3,-984 # 80003080 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c5c60613 addi a2,a2,-932 # 80003110 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c2460613 addi a2,a2,-988 # 80003128 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: b7468693 addi a3,a3,-1164 # 800030c8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b9068693 addi a3,a3,-1136 # 80003200 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b1060613 addi a2,a2,-1264 # 800031d8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a4468693 addi a3,a3,-1468 # 80003230 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 96468693 addi a3,a3,-1692 # 800031a0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 8f468693 addi a3,a3,-1804 # 80003168 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02e00793 li a5,46 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a2f77b7 lui a5,0xa2f7 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 09e78793 addi a5,a5,158 # a2f709e <_start-0x75d08f62> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 00000113 li sp,0 + 80002ad0: 4020df33 sra t5,ra,sp + 80002ad4: 80000eb7 lui t4,0x80000 + 80002ad8: 00200193 li gp,2 + 80002adc: 59df1463 bne t5,t4,80003064 + +0000000080002ae0 : + 80002ae0: 800000b7 lui ra,0x80000 + 80002ae4: 00100113 li sp,1 + 80002ae8: 4020df33 sra t5,ra,sp + 80002aec: c0000eb7 lui t4,0xc0000 + 80002af0: 00300193 li gp,3 + 80002af4: 57df1863 bne t5,t4,80003064 + +0000000080002af8 : + 80002af8: 800000b7 lui ra,0x80000 + 80002afc: 00700113 li sp,7 + 80002b00: 4020df33 sra t5,ra,sp + 80002b04: ff000eb7 lui t4,0xff000 + 80002b08: 00400193 li gp,4 + 80002b0c: 55df1c63 bne t5,t4,80003064 + +0000000080002b10 : + 80002b10: 800000b7 lui ra,0x80000 + 80002b14: 00e00113 li sp,14 + 80002b18: 4020df33 sra t5,ra,sp + 80002b1c: fffe0eb7 lui t4,0xfffe0 + 80002b20: 00500193 li gp,5 + 80002b24: 55df1063 bne t5,t4,80003064 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 0010809b addiw ra,ra,1 + 80002b30: 01f00113 li sp,31 + 80002b34: 4020df33 sra t5,ra,sp + 80002b38: fff00e93 li t4,-1 + 80002b3c: 00600193 li gp,6 + 80002b40: 53df1263 bne t5,t4,80003064 + +0000000080002b44 : + 80002b44: 800000b7 lui ra,0x80000 + 80002b48: fff0809b addiw ra,ra,-1 + 80002b4c: 00000113 li sp,0 + 80002b50: 4020df33 sra t5,ra,sp + 80002b54: 80000eb7 lui t4,0x80000 + 80002b58: fffe8e9b addiw t4,t4,-1 + 80002b5c: 00700193 li gp,7 + 80002b60: 51df1263 bne t5,t4,80003064 + +0000000080002b64 : + 80002b64: 800000b7 lui ra,0x80000 + 80002b68: fff0809b addiw ra,ra,-1 + 80002b6c: 00100113 li sp,1 + 80002b70: 4020df33 sra t5,ra,sp + 80002b74: 40000eb7 lui t4,0x40000 + 80002b78: fffe8e9b addiw t4,t4,-1 + 80002b7c: 00800193 li gp,8 + 80002b80: 4fdf1263 bne t5,t4,80003064 + +0000000080002b84 : + 80002b84: 800000b7 lui ra,0x80000 + 80002b88: fff0809b addiw ra,ra,-1 + 80002b8c: 00700113 li sp,7 + 80002b90: 4020df33 sra t5,ra,sp + 80002b94: 01000eb7 lui t4,0x1000 + 80002b98: fffe8e9b addiw t4,t4,-1 + 80002b9c: 00900193 li gp,9 + 80002ba0: 4ddf1263 bne t5,t4,80003064 + +0000000080002ba4 : + 80002ba4: 800000b7 lui ra,0x80000 + 80002ba8: fff0809b addiw ra,ra,-1 + 80002bac: 00e00113 li sp,14 + 80002bb0: 4020df33 sra t5,ra,sp + 80002bb4: 00020eb7 lui t4,0x20 + 80002bb8: fffe8e9b addiw t4,t4,-1 + 80002bbc: 00a00193 li gp,10 + 80002bc0: 4bdf1263 bne t5,t4,80003064 + +0000000080002bc4 : + 80002bc4: 800000b7 lui ra,0x80000 + 80002bc8: fff0809b addiw ra,ra,-1 + 80002bcc: 01f00113 li sp,31 + 80002bd0: 4020df33 sra t5,ra,sp + 80002bd4: 00000e93 li t4,0 + 80002bd8: 00b00193 li gp,11 + 80002bdc: 49df1463 bne t5,t4,80003064 + +0000000080002be0 : + 80002be0: 818180b7 lui ra,0x81818 + 80002be4: 1810809b addiw ra,ra,385 + 80002be8: 00000113 li sp,0 + 80002bec: 4020df33 sra t5,ra,sp + 80002bf0: 81818eb7 lui t4,0x81818 + 80002bf4: 181e8e9b addiw t4,t4,385 + 80002bf8: 00c00193 li gp,12 + 80002bfc: 47df1463 bne t5,t4,80003064 + +0000000080002c00 : + 80002c00: 818180b7 lui ra,0x81818 + 80002c04: 1810809b addiw ra,ra,385 + 80002c08: 00100113 li sp,1 + 80002c0c: 4020df33 sra t5,ra,sp + 80002c10: c0c0ceb7 lui t4,0xc0c0c + 80002c14: 0c0e8e9b addiw t4,t4,192 + 80002c18: 00d00193 li gp,13 + 80002c1c: 45df1463 bne t5,t4,80003064 + +0000000080002c20 : + 80002c20: 818180b7 lui ra,0x81818 + 80002c24: 1810809b addiw ra,ra,385 + 80002c28: 00700113 li sp,7 + 80002c2c: 4020df33 sra t5,ra,sp + 80002c30: ff030eb7 lui t4,0xff030 + 80002c34: 303e8e9b addiw t4,t4,771 + 80002c38: 00e00193 li gp,14 + 80002c3c: 43df1463 bne t5,t4,80003064 + +0000000080002c40 : + 80002c40: 818180b7 lui ra,0x81818 + 80002c44: 1810809b addiw ra,ra,385 + 80002c48: 00e00113 li sp,14 + 80002c4c: 4020df33 sra t5,ra,sp + 80002c50: fffe0eb7 lui t4,0xfffe0 + 80002c54: 606e8e9b addiw t4,t4,1542 + 80002c58: 00f00193 li gp,15 + 80002c5c: 41df1463 bne t5,t4,80003064 + +0000000080002c60 : + 80002c60: 818180b7 lui ra,0x81818 + 80002c64: 1810809b addiw ra,ra,385 + 80002c68: 01f00113 li sp,31 + 80002c6c: 4020df33 sra t5,ra,sp + 80002c70: fff00e93 li t4,-1 + 80002c74: 01000193 li gp,16 + 80002c78: 3fdf1663 bne t5,t4,80003064 + +0000000080002c7c : + 80002c7c: 818180b7 lui ra,0x81818 + 80002c80: 1810809b addiw ra,ra,385 + 80002c84: fc000113 li sp,-64 + 80002c88: 4020df33 sra t5,ra,sp + 80002c8c: 81818eb7 lui t4,0x81818 + 80002c90: 181e8e9b addiw t4,t4,385 + 80002c94: 01100193 li gp,17 + 80002c98: 3ddf1663 bne t5,t4,80003064 + +0000000080002c9c : + 80002c9c: 818180b7 lui ra,0x81818 + 80002ca0: 1810809b addiw ra,ra,385 + 80002ca4: fc100113 li sp,-63 + 80002ca8: 4020df33 sra t5,ra,sp + 80002cac: c0c0ceb7 lui t4,0xc0c0c + 80002cb0: 0c0e8e9b addiw t4,t4,192 + 80002cb4: 01200193 li gp,18 + 80002cb8: 3bdf1663 bne t5,t4,80003064 + +0000000080002cbc : + 80002cbc: 818180b7 lui ra,0x81818 + 80002cc0: 1810809b addiw ra,ra,385 + 80002cc4: fc700113 li sp,-57 + 80002cc8: 4020df33 sra t5,ra,sp + 80002ccc: ff030eb7 lui t4,0xff030 + 80002cd0: 303e8e9b addiw t4,t4,771 + 80002cd4: 01300193 li gp,19 + 80002cd8: 39df1663 bne t5,t4,80003064 + +0000000080002cdc : + 80002cdc: 818180b7 lui ra,0x81818 + 80002ce0: 1810809b addiw ra,ra,385 + 80002ce4: fce00113 li sp,-50 + 80002ce8: 4020df33 sra t5,ra,sp + 80002cec: fffe0eb7 lui t4,0xfffe0 + 80002cf0: 606e8e9b addiw t4,t4,1542 + 80002cf4: 01400193 li gp,20 + 80002cf8: 37df1663 bne t5,t4,80003064 + +0000000080002cfc : + 80002cfc: 818180b7 lui ra,0x81818 + 80002d00: 1810809b addiw ra,ra,385 + 80002d04: fff00113 li sp,-1 + 80002d08: 4020df33 sra t5,ra,sp + 80002d0c: fff00e93 li t4,-1 + 80002d10: 01500193 li gp,21 + 80002d14: 35df1863 bne t5,t4,80003064 + +0000000080002d18 : + 80002d18: 800000b7 lui ra,0x80000 + 80002d1c: 00700113 li sp,7 + 80002d20: 4020d0b3 sra ra,ra,sp + 80002d24: ff000eb7 lui t4,0xff000 + 80002d28: 01600193 li gp,22 + 80002d2c: 33d09c63 bne ra,t4,80003064 + +0000000080002d30 : + 80002d30: 800000b7 lui ra,0x80000 + 80002d34: 00e00113 li sp,14 + 80002d38: 4020d133 sra sp,ra,sp + 80002d3c: fffe0eb7 lui t4,0xfffe0 + 80002d40: 01700193 li gp,23 + 80002d44: 33d11063 bne sp,t4,80003064 + +0000000080002d48 : + 80002d48: 00700093 li ra,7 + 80002d4c: 4010d0b3 sra ra,ra,ra + 80002d50: 00000e93 li t4,0 + 80002d54: 01800193 li gp,24 + 80002d58: 31d09663 bne ra,t4,80003064 + +0000000080002d5c : + 80002d5c: 00000213 li tp,0 + 80002d60: 800000b7 lui ra,0x80000 + 80002d64: 00700113 li sp,7 + 80002d68: 4020df33 sra t5,ra,sp + 80002d6c: 000f0313 mv t1,t5 + 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d74: 00200293 li t0,2 + 80002d78: fe5214e3 bne tp,t0,80002d60 + 80002d7c: ff000eb7 lui t4,0xff000 + 80002d80: 01900193 li gp,25 + 80002d84: 2fd31063 bne t1,t4,80003064 + +0000000080002d88 : + 80002d88: 00000213 li tp,0 + 80002d8c: 800000b7 lui ra,0x80000 + 80002d90: 00e00113 li sp,14 + 80002d94: 4020df33 sra t5,ra,sp + 80002d98: 00000013 nop + 80002d9c: 000f0313 mv t1,t5 + 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da4: 00200293 li t0,2 + 80002da8: fe5212e3 bne tp,t0,80002d8c + 80002dac: fffe0eb7 lui t4,0xfffe0 + 80002db0: 01a00193 li gp,26 + 80002db4: 2bd31863 bne t1,t4,80003064 + +0000000080002db8 : + 80002db8: 00000213 li tp,0 + 80002dbc: 800000b7 lui ra,0x80000 + 80002dc0: 01f00113 li sp,31 + 80002dc4: 4020df33 sra t5,ra,sp + 80002dc8: 00000013 nop + 80002dcc: 00000013 nop + 80002dd0: 000f0313 mv t1,t5 + 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd8: 00200293 li t0,2 + 80002ddc: fe5210e3 bne tp,t0,80002dbc + 80002de0: fff00e93 li t4,-1 + 80002de4: 01b00193 li gp,27 + 80002de8: 27d31e63 bne t1,t4,80003064 + +0000000080002dec : + 80002dec: 00000213 li tp,0 + 80002df0: 800000b7 lui ra,0x80000 + 80002df4: 00700113 li sp,7 + 80002df8: 4020df33 sra t5,ra,sp + 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e00: 00200293 li t0,2 + 80002e04: fe5216e3 bne tp,t0,80002df0 + 80002e08: ff000eb7 lui t4,0xff000 + 80002e0c: 01c00193 li gp,28 + 80002e10: 25df1a63 bne t5,t4,80003064 + +0000000080002e14 : + 80002e14: 00000213 li tp,0 + 80002e18: 800000b7 lui ra,0x80000 + 80002e1c: 00e00113 li sp,14 + 80002e20: 00000013 nop + 80002e24: 4020df33 sra t5,ra,sp + 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e2c: 00200293 li t0,2 + 80002e30: fe5214e3 bne tp,t0,80002e18 + 80002e34: fffe0eb7 lui t4,0xfffe0 + 80002e38: 01d00193 li gp,29 + 80002e3c: 23df1463 bne t5,t4,80003064 + +0000000080002e40 : + 80002e40: 00000213 li tp,0 + 80002e44: 800000b7 lui ra,0x80000 + 80002e48: 01f00113 li sp,31 + 80002e4c: 00000013 nop + 80002e50: 00000013 nop + 80002e54: 4020df33 sra t5,ra,sp + 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e5c: 00200293 li t0,2 + 80002e60: fe5212e3 bne tp,t0,80002e44 + 80002e64: fff00e93 li t4,-1 + 80002e68: 01e00193 li gp,30 + 80002e6c: 1fdf1c63 bne t5,t4,80003064 + +0000000080002e70 : + 80002e70: 00000213 li tp,0 + 80002e74: 800000b7 lui ra,0x80000 + 80002e78: 00000013 nop + 80002e7c: 00700113 li sp,7 + 80002e80: 4020df33 sra t5,ra,sp + 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e88: 00200293 li t0,2 + 80002e8c: fe5214e3 bne tp,t0,80002e74 + 80002e90: ff000eb7 lui t4,0xff000 + 80002e94: 01f00193 li gp,31 + 80002e98: 1ddf1663 bne t5,t4,80003064 + +0000000080002e9c : + 80002e9c: 00000213 li tp,0 + 80002ea0: 800000b7 lui ra,0x80000 + 80002ea4: 00000013 nop + 80002ea8: 00e00113 li sp,14 + 80002eac: 00000013 nop + 80002eb0: 4020df33 sra t5,ra,sp + 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb8: 00200293 li t0,2 + 80002ebc: fe5212e3 bne tp,t0,80002ea0 + 80002ec0: fffe0eb7 lui t4,0xfffe0 + 80002ec4: 02000193 li gp,32 + 80002ec8: 19df1e63 bne t5,t4,80003064 + +0000000080002ecc : + 80002ecc: 00000213 li tp,0 + 80002ed0: 800000b7 lui ra,0x80000 + 80002ed4: 00000013 nop + 80002ed8: 00000013 nop + 80002edc: 01f00113 li sp,31 + 80002ee0: 4020df33 sra t5,ra,sp + 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee8: 00200293 li t0,2 + 80002eec: fe5212e3 bne tp,t0,80002ed0 + 80002ef0: fff00e93 li t4,-1 + 80002ef4: 02100193 li gp,33 + 80002ef8: 17df1663 bne t5,t4,80003064 + +0000000080002efc : + 80002efc: 00000213 li tp,0 + 80002f00: 00700113 li sp,7 + 80002f04: 800000b7 lui ra,0x80000 + 80002f08: 4020df33 sra t5,ra,sp + 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f10: 00200293 li t0,2 + 80002f14: fe5216e3 bne tp,t0,80002f00 + 80002f18: ff000eb7 lui t4,0xff000 + 80002f1c: 02200193 li gp,34 + 80002f20: 15df1263 bne t5,t4,80003064 + +0000000080002f24 : + 80002f24: 00000213 li tp,0 + 80002f28: 00e00113 li sp,14 + 80002f2c: 800000b7 lui ra,0x80000 + 80002f30: 00000013 nop + 80002f34: 4020df33 sra t5,ra,sp + 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f3c: 00200293 li t0,2 + 80002f40: fe5214e3 bne tp,t0,80002f28 + 80002f44: fffe0eb7 lui t4,0xfffe0 + 80002f48: 02300193 li gp,35 + 80002f4c: 11df1c63 bne t5,t4,80003064 + +0000000080002f50 : + 80002f50: 00000213 li tp,0 + 80002f54: 01f00113 li sp,31 + 80002f58: 800000b7 lui ra,0x80000 + 80002f5c: 00000013 nop + 80002f60: 00000013 nop + 80002f64: 4020df33 sra t5,ra,sp + 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f6c: 00200293 li t0,2 + 80002f70: fe5212e3 bne tp,t0,80002f54 + 80002f74: fff00e93 li t4,-1 + 80002f78: 02400193 li gp,36 + 80002f7c: 0fdf1463 bne t5,t4,80003064 + +0000000080002f80 : + 80002f80: 00000213 li tp,0 + 80002f84: 00700113 li sp,7 + 80002f88: 00000013 nop + 80002f8c: 800000b7 lui ra,0x80000 + 80002f90: 4020df33 sra t5,ra,sp + 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f98: 00200293 li t0,2 + 80002f9c: fe5214e3 bne tp,t0,80002f84 + 80002fa0: ff000eb7 lui t4,0xff000 + 80002fa4: 02500193 li gp,37 + 80002fa8: 0bdf1e63 bne t5,t4,80003064 + +0000000080002fac : + 80002fac: 00000213 li tp,0 + 80002fb0: 00e00113 li sp,14 + 80002fb4: 00000013 nop + 80002fb8: 800000b7 lui ra,0x80000 + 80002fbc: 00000013 nop + 80002fc0: 4020df33 sra t5,ra,sp + 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fc8: 00200293 li t0,2 + 80002fcc: fe5212e3 bne tp,t0,80002fb0 + 80002fd0: fffe0eb7 lui t4,0xfffe0 + 80002fd4: 02600193 li gp,38 + 80002fd8: 09df1663 bne t5,t4,80003064 + +0000000080002fdc : + 80002fdc: 00000213 li tp,0 + 80002fe0: 01f00113 li sp,31 + 80002fe4: 00000013 nop + 80002fe8: 00000013 nop + 80002fec: 800000b7 lui ra,0x80000 + 80002ff0: 4020df33 sra t5,ra,sp + 80002ff4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ff8: 00200293 li t0,2 + 80002ffc: fe5212e3 bne tp,t0,80002fe0 + 80003000: fff00e93 li t4,-1 + 80003004: 02700193 li gp,39 + 80003008: 05df1e63 bne t5,t4,80003064 + +000000008000300c : + 8000300c: 00f00093 li ra,15 + 80003010: 40105133 sra sp,zero,ra + 80003014: 00000e93 li t4,0 + 80003018: 02800193 li gp,40 + 8000301c: 05d11463 bne sp,t4,80003064 + +0000000080003020 : + 80003020: 02000093 li ra,32 + 80003024: 4000d133 sra sp,ra,zero + 80003028: 02000e93 li t4,32 + 8000302c: 02900193 li gp,41 + 80003030: 03d11a63 bne sp,t4,80003064 + +0000000080003034 : + 80003034: 400050b3 sra ra,zero,zero + 80003038: 00000e93 li t4,0 + 8000303c: 02a00193 li gp,42 + 80003040: 03d09263 bne ra,t4,80003064 + +0000000080003044 : + 80003044: 40000093 li ra,1024 + 80003048: 00001137 lui sp,0x1 + 8000304c: 8001011b addiw sp,sp,-2048 + 80003050: 4020d033 sra zero,ra,sp + 80003054: 00000e93 li t4,0 + 80003058: 02b00193 li gp,43 + 8000305c: 01d01463 bne zero,t4,80003064 + 80003060: 00301a63 bne zero,gp,80003074 + +0000000080003064 : + 80003064: 00119513 slli a0,gp,0x1 + 80003068: 00050063 beqz a0,80003068 + 8000306c: 00156513 ori a0,a0,1 + 80003070: 00000073 ecall + +0000000080003074 : + 80003074: 00100513 li a0,1 + 80003078: 00000073 ecall + 8000307c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sra.elf b/test/riscv/tests/rv64ui-v-sra.elf new file mode 100644 index 00000000..bfbb9dc1 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sra.elf differ diff --git a/test/riscv/tests/rv64ui-v-srai.dump b/test/riscv/tests/rv64ui-v-srai.dump new file mode 100644 index 00000000..8926e559 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-srai.dump @@ -0,0 +1,1062 @@ + +rv64ui-v-srai: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 61c68693 addi a3,a3,1564 # 80002e90 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00400793 li a5,4 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 00a547b7 lui a5,0xa54 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: f8778793 addi a5,a5,-121 # a53f87 <_start-0x7f5ac079> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: fff0009b addiw ra,zero,-1 + 80002acc: 02709093 slli ra,ra,0x27 + 80002ad0: 4000df13 srai t5,ra,0x0 + 80002ad4: fff00e9b addiw t4,zero,-1 + 80002ad8: 027e9e93 slli t4,t4,0x27 + 80002adc: 00200193 li gp,2 + 80002ae0: 2bdf1463 bne t5,t4,80002d88 + +0000000080002ae4 : + 80002ae4: 800000b7 lui ra,0x80000 + 80002ae8: 4010df13 srai t5,ra,0x1 + 80002aec: c0000eb7 lui t4,0xc0000 + 80002af0: 00300193 li gp,3 + 80002af4: 29df1a63 bne t5,t4,80002d88 + +0000000080002af8 : + 80002af8: 800000b7 lui ra,0x80000 + 80002afc: 4070df13 srai t5,ra,0x7 + 80002b00: ff000eb7 lui t4,0xff000 + 80002b04: 00400193 li gp,4 + 80002b08: 29df1063 bne t5,t4,80002d88 + +0000000080002b0c : + 80002b0c: 800000b7 lui ra,0x80000 + 80002b10: 40e0df13 srai t5,ra,0xe + 80002b14: fffe0eb7 lui t4,0xfffe0 + 80002b18: 00500193 li gp,5 + 80002b1c: 27df1663 bne t5,t4,80002d88 + +0000000080002b20 : + 80002b20: 800000b7 lui ra,0x80000 + 80002b24: 0010809b addiw ra,ra,1 + 80002b28: 41f0df13 srai t5,ra,0x1f + 80002b2c: fff00e93 li t4,-1 + 80002b30: 00600193 li gp,6 + 80002b34: 25df1a63 bne t5,t4,80002d88 + +0000000080002b38 : + 80002b38: 800000b7 lui ra,0x80000 + 80002b3c: fff0809b addiw ra,ra,-1 + 80002b40: 4000df13 srai t5,ra,0x0 + 80002b44: 80000eb7 lui t4,0x80000 + 80002b48: fffe8e9b addiw t4,t4,-1 + 80002b4c: 00700193 li gp,7 + 80002b50: 23df1c63 bne t5,t4,80002d88 + +0000000080002b54 : + 80002b54: 800000b7 lui ra,0x80000 + 80002b58: fff0809b addiw ra,ra,-1 + 80002b5c: 4010df13 srai t5,ra,0x1 + 80002b60: 40000eb7 lui t4,0x40000 + 80002b64: fffe8e9b addiw t4,t4,-1 + 80002b68: 00800193 li gp,8 + 80002b6c: 21df1e63 bne t5,t4,80002d88 + +0000000080002b70 : + 80002b70: 800000b7 lui ra,0x80000 + 80002b74: fff0809b addiw ra,ra,-1 + 80002b78: 4070df13 srai t5,ra,0x7 + 80002b7c: 01000eb7 lui t4,0x1000 + 80002b80: fffe8e9b addiw t4,t4,-1 + 80002b84: 00900193 li gp,9 + 80002b88: 21df1063 bne t5,t4,80002d88 + +0000000080002b8c : + 80002b8c: 800000b7 lui ra,0x80000 + 80002b90: fff0809b addiw ra,ra,-1 + 80002b94: 40e0df13 srai t5,ra,0xe + 80002b98: 00020eb7 lui t4,0x20 + 80002b9c: fffe8e9b addiw t4,t4,-1 + 80002ba0: 00a00193 li gp,10 + 80002ba4: 1fdf1263 bne t5,t4,80002d88 + +0000000080002ba8 : + 80002ba8: 800000b7 lui ra,0x80000 + 80002bac: fff0809b addiw ra,ra,-1 + 80002bb0: 41f0df13 srai t5,ra,0x1f + 80002bb4: 00000e93 li t4,0 + 80002bb8: 00b00193 li gp,11 + 80002bbc: 1ddf1663 bne t5,t4,80002d88 + +0000000080002bc0 : + 80002bc0: 818180b7 lui ra,0x81818 + 80002bc4: 1810809b addiw ra,ra,385 + 80002bc8: 4000df13 srai t5,ra,0x0 + 80002bcc: 81818eb7 lui t4,0x81818 + 80002bd0: 181e8e9b addiw t4,t4,385 + 80002bd4: 00c00193 li gp,12 + 80002bd8: 1bdf1863 bne t5,t4,80002d88 + +0000000080002bdc : + 80002bdc: 818180b7 lui ra,0x81818 + 80002be0: 1810809b addiw ra,ra,385 + 80002be4: 4010df13 srai t5,ra,0x1 + 80002be8: c0c0ceb7 lui t4,0xc0c0c + 80002bec: 0c0e8e9b addiw t4,t4,192 + 80002bf0: 00d00193 li gp,13 + 80002bf4: 19df1a63 bne t5,t4,80002d88 + +0000000080002bf8 : + 80002bf8: 818180b7 lui ra,0x81818 + 80002bfc: 1810809b addiw ra,ra,385 + 80002c00: 4070df13 srai t5,ra,0x7 + 80002c04: ff030eb7 lui t4,0xff030 + 80002c08: 303e8e9b addiw t4,t4,771 + 80002c0c: 00e00193 li gp,14 + 80002c10: 17df1c63 bne t5,t4,80002d88 + +0000000080002c14 : + 80002c14: 818180b7 lui ra,0x81818 + 80002c18: 1810809b addiw ra,ra,385 + 80002c1c: 40e0df13 srai t5,ra,0xe + 80002c20: fffe0eb7 lui t4,0xfffe0 + 80002c24: 606e8e9b addiw t4,t4,1542 + 80002c28: 00f00193 li gp,15 + 80002c2c: 15df1e63 bne t5,t4,80002d88 + +0000000080002c30 : + 80002c30: 818180b7 lui ra,0x81818 + 80002c34: 1810809b addiw ra,ra,385 + 80002c38: 41f0df13 srai t5,ra,0x1f + 80002c3c: fff00e93 li t4,-1 + 80002c40: 01000193 li gp,16 + 80002c44: 15df1263 bne t5,t4,80002d88 + +0000000080002c48 : + 80002c48: 800000b7 lui ra,0x80000 + 80002c4c: 4070d093 srai ra,ra,0x7 + 80002c50: ff000eb7 lui t4,0xff000 + 80002c54: 01100193 li gp,17 + 80002c58: 13d09863 bne ra,t4,80002d88 + +0000000080002c5c : + 80002c5c: 00000213 li tp,0 + 80002c60: 800000b7 lui ra,0x80000 + 80002c64: 4070df13 srai t5,ra,0x7 + 80002c68: 000f0313 mv t1,t5 + 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c70: 00200293 li t0,2 + 80002c74: fe5216e3 bne tp,t0,80002c60 + 80002c78: ff000eb7 lui t4,0xff000 + 80002c7c: 01200193 li gp,18 + 80002c80: 11d31463 bne t1,t4,80002d88 + +0000000080002c84 : + 80002c84: 00000213 li tp,0 + 80002c88: 800000b7 lui ra,0x80000 + 80002c8c: 40e0df13 srai t5,ra,0xe + 80002c90: 00000013 nop + 80002c94: 000f0313 mv t1,t5 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5214e3 bne tp,t0,80002c88 + 80002ca4: fffe0eb7 lui t4,0xfffe0 + 80002ca8: 01300193 li gp,19 + 80002cac: 0dd31e63 bne t1,t4,80002d88 + +0000000080002cb0 : + 80002cb0: 00000213 li tp,0 + 80002cb4: 800000b7 lui ra,0x80000 + 80002cb8: 0010809b addiw ra,ra,1 + 80002cbc: 41f0df13 srai t5,ra,0x1f + 80002cc0: 00000013 nop + 80002cc4: 00000013 nop + 80002cc8: 000f0313 mv t1,t5 + 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd0: 00200293 li t0,2 + 80002cd4: fe5210e3 bne tp,t0,80002cb4 + 80002cd8: fff00e93 li t4,-1 + 80002cdc: 01400193 li gp,20 + 80002ce0: 0bd31463 bne t1,t4,80002d88 + +0000000080002ce4 : + 80002ce4: 00000213 li tp,0 + 80002ce8: 800000b7 lui ra,0x80000 + 80002cec: 4070df13 srai t5,ra,0x7 + 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf4: 00200293 li t0,2 + 80002cf8: fe5218e3 bne tp,t0,80002ce8 + 80002cfc: ff000eb7 lui t4,0xff000 + 80002d00: 01500193 li gp,21 + 80002d04: 09df1263 bne t5,t4,80002d88 + +0000000080002d08 : + 80002d08: 00000213 li tp,0 + 80002d0c: 800000b7 lui ra,0x80000 + 80002d10: 00000013 nop + 80002d14: 40e0df13 srai t5,ra,0xe + 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d1c: 00200293 li t0,2 + 80002d20: fe5216e3 bne tp,t0,80002d0c + 80002d24: fffe0eb7 lui t4,0xfffe0 + 80002d28: 01600193 li gp,22 + 80002d2c: 05df1e63 bne t5,t4,80002d88 + +0000000080002d30 : + 80002d30: 00000213 li tp,0 + 80002d34: 800000b7 lui ra,0x80000 + 80002d38: 0010809b addiw ra,ra,1 + 80002d3c: 00000013 nop + 80002d40: 00000013 nop + 80002d44: 41f0df13 srai t5,ra,0x1f + 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d4c: 00200293 li t0,2 + 80002d50: fe5212e3 bne tp,t0,80002d34 + 80002d54: fff00e93 li t4,-1 + 80002d58: 01700193 li gp,23 + 80002d5c: 03df1663 bne t5,t4,80002d88 + +0000000080002d60 : + 80002d60: 40405093 srai ra,zero,0x4 + 80002d64: 00000e93 li t4,0 + 80002d68: 01800193 li gp,24 + 80002d6c: 01d09e63 bne ra,t4,80002d88 + +0000000080002d70 : + 80002d70: 02100093 li ra,33 + 80002d74: 40a0d013 srai zero,ra,0xa + 80002d78: 00000e93 li t4,0 + 80002d7c: 01900193 li gp,25 + 80002d80: 01d01463 bne zero,t4,80002d88 + 80002d84: 00301a63 bne zero,gp,80002d98 + +0000000080002d88 : + 80002d88: 00119513 slli a0,gp,0x1 + 80002d8c: 00050063 beqz a0,80002d8c + 80002d90: 00156513 ori a0,a0,1 + 80002d94: 00000073 ecall + +0000000080002d98 : + 80002d98: 00100513 li a0,1 + 80002d9c: 00000073 ecall + 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srai.elf b/test/riscv/tests/rv64ui-v-srai.elf new file mode 100644 index 00000000..a84338f4 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-srai.elf differ diff --git a/test/riscv/tests/rv64ui-v-sraiw.dump b/test/riscv/tests/rv64ui-v-sraiw.dump new file mode 100644 index 00000000..276de6b8 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sraiw.dump @@ -0,0 +1,1076 @@ + +rv64ui-v-sraiw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 97868693 addi a3,a3,-1672 # 80002dd0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 9ac60613 addi a2,a2,-1620 # 80002e60 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 97460613 addi a2,a2,-1676 # 80002e78 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 8c468693 addi a3,a3,-1852 # 80002e18 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8e068693 addi a3,a3,-1824 # 80002f50 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 86060613 addi a2,a2,-1952 # 80002f28 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 79468693 addi a3,a3,1940 # 80002f80 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 6b468693 addi a3,a3,1716 # 80002ef0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 64468693 addi a3,a3,1604 # 80002eb8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 00800793 li a5,8 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0e8fe7b7 lui a5,0xe8fe + 80002a70: 000805b7 lui a1,0x80 + 80002a74: ca478793 addi a5,a5,-860 # e8fdca4 <_start-0x7170235c> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 4000df1b sraiw t5,ra,0x0 + 80002ad0: 80000eb7 lui t4,0x80000 + 80002ad4: 00200193 li gp,2 + 80002ad8: 2ddf1c63 bne t5,t4,80002db0 + +0000000080002adc : + 80002adc: 800000b7 lui ra,0x80000 + 80002ae0: 4010df1b sraiw t5,ra,0x1 + 80002ae4: c0000eb7 lui t4,0xc0000 + 80002ae8: 00300193 li gp,3 + 80002aec: 2ddf1263 bne t5,t4,80002db0 + +0000000080002af0 : + 80002af0: 800000b7 lui ra,0x80000 + 80002af4: 4070df1b sraiw t5,ra,0x7 + 80002af8: ff000eb7 lui t4,0xff000 + 80002afc: 00400193 li gp,4 + 80002b00: 2bdf1863 bne t5,t4,80002db0 + +0000000080002b04 : + 80002b04: 800000b7 lui ra,0x80000 + 80002b08: 40e0df1b sraiw t5,ra,0xe + 80002b0c: fffe0eb7 lui t4,0xfffe0 + 80002b10: 00500193 li gp,5 + 80002b14: 29df1e63 bne t5,t4,80002db0 + +0000000080002b18 : + 80002b18: 800000b7 lui ra,0x80000 + 80002b1c: 0010809b addiw ra,ra,1 + 80002b20: 41f0df1b sraiw t5,ra,0x1f + 80002b24: fff00e93 li t4,-1 + 80002b28: 00600193 li gp,6 + 80002b2c: 29df1263 bne t5,t4,80002db0 + +0000000080002b30 : + 80002b30: 800000b7 lui ra,0x80000 + 80002b34: fff0809b addiw ra,ra,-1 + 80002b38: 4000df1b sraiw t5,ra,0x0 + 80002b3c: 80000eb7 lui t4,0x80000 + 80002b40: fffe8e9b addiw t4,t4,-1 + 80002b44: 00700193 li gp,7 + 80002b48: 27df1463 bne t5,t4,80002db0 + +0000000080002b4c : + 80002b4c: 800000b7 lui ra,0x80000 + 80002b50: fff0809b addiw ra,ra,-1 + 80002b54: 4010df1b sraiw t5,ra,0x1 + 80002b58: 40000eb7 lui t4,0x40000 + 80002b5c: fffe8e9b addiw t4,t4,-1 + 80002b60: 00800193 li gp,8 + 80002b64: 25df1663 bne t5,t4,80002db0 + +0000000080002b68 : + 80002b68: 800000b7 lui ra,0x80000 + 80002b6c: fff0809b addiw ra,ra,-1 + 80002b70: 4070df1b sraiw t5,ra,0x7 + 80002b74: 01000eb7 lui t4,0x1000 + 80002b78: fffe8e9b addiw t4,t4,-1 + 80002b7c: 00900193 li gp,9 + 80002b80: 23df1863 bne t5,t4,80002db0 + +0000000080002b84 : + 80002b84: 800000b7 lui ra,0x80000 + 80002b88: fff0809b addiw ra,ra,-1 + 80002b8c: 40e0df1b sraiw t5,ra,0xe + 80002b90: 00020eb7 lui t4,0x20 + 80002b94: fffe8e9b addiw t4,t4,-1 + 80002b98: 00a00193 li gp,10 + 80002b9c: 21df1a63 bne t5,t4,80002db0 + +0000000080002ba0 : + 80002ba0: 800000b7 lui ra,0x80000 + 80002ba4: fff0809b addiw ra,ra,-1 + 80002ba8: 41f0df1b sraiw t5,ra,0x1f + 80002bac: 00000e93 li t4,0 + 80002bb0: 00b00193 li gp,11 + 80002bb4: 1fdf1e63 bne t5,t4,80002db0 + +0000000080002bb8 : + 80002bb8: 818180b7 lui ra,0x81818 + 80002bbc: 1810809b addiw ra,ra,385 + 80002bc0: 4000df1b sraiw t5,ra,0x0 + 80002bc4: 81818eb7 lui t4,0x81818 + 80002bc8: 181e8e9b addiw t4,t4,385 + 80002bcc: 00c00193 li gp,12 + 80002bd0: 1fdf1063 bne t5,t4,80002db0 + +0000000080002bd4 : + 80002bd4: 818180b7 lui ra,0x81818 + 80002bd8: 1810809b addiw ra,ra,385 + 80002bdc: 4010df1b sraiw t5,ra,0x1 + 80002be0: c0c0ceb7 lui t4,0xc0c0c + 80002be4: 0c0e8e9b addiw t4,t4,192 + 80002be8: 00d00193 li gp,13 + 80002bec: 1ddf1263 bne t5,t4,80002db0 + +0000000080002bf0 : + 80002bf0: 818180b7 lui ra,0x81818 + 80002bf4: 1810809b addiw ra,ra,385 + 80002bf8: 4070df1b sraiw t5,ra,0x7 + 80002bfc: ff030eb7 lui t4,0xff030 + 80002c00: 303e8e9b addiw t4,t4,771 + 80002c04: 00e00193 li gp,14 + 80002c08: 1bdf1463 bne t5,t4,80002db0 + +0000000080002c0c : + 80002c0c: 818180b7 lui ra,0x81818 + 80002c10: 1810809b addiw ra,ra,385 + 80002c14: 40e0df1b sraiw t5,ra,0xe + 80002c18: fffe0eb7 lui t4,0xfffe0 + 80002c1c: 606e8e9b addiw t4,t4,1542 + 80002c20: 00f00193 li gp,15 + 80002c24: 19df1663 bne t5,t4,80002db0 + +0000000080002c28 : + 80002c28: 818180b7 lui ra,0x81818 + 80002c2c: 1810809b addiw ra,ra,385 + 80002c30: 41f0df1b sraiw t5,ra,0x1f + 80002c34: fff00e93 li t4,-1 + 80002c38: 01000193 li gp,16 + 80002c3c: 17df1a63 bne t5,t4,80002db0 + +0000000080002c40 : + 80002c40: 800000b7 lui ra,0x80000 + 80002c44: 4070d09b sraiw ra,ra,0x7 + 80002c48: ff000eb7 lui t4,0xff000 + 80002c4c: 01100193 li gp,17 + 80002c50: 17d09063 bne ra,t4,80002db0 + +0000000080002c54 : + 80002c54: 00000213 li tp,0 + 80002c58: 800000b7 lui ra,0x80000 + 80002c5c: 4070df1b sraiw t5,ra,0x7 + 80002c60: 000f0313 mv t1,t5 + 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c68: 00200293 li t0,2 + 80002c6c: fe5216e3 bne tp,t0,80002c58 + 80002c70: ff000eb7 lui t4,0xff000 + 80002c74: 01200193 li gp,18 + 80002c78: 13d31c63 bne t1,t4,80002db0 + +0000000080002c7c : + 80002c7c: 00000213 li tp,0 + 80002c80: 800000b7 lui ra,0x80000 + 80002c84: 40e0df1b sraiw t5,ra,0xe + 80002c88: 00000013 nop + 80002c8c: 000f0313 mv t1,t5 + 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c94: 00200293 li t0,2 + 80002c98: fe5214e3 bne tp,t0,80002c80 + 80002c9c: fffe0eb7 lui t4,0xfffe0 + 80002ca0: 01300193 li gp,19 + 80002ca4: 11d31663 bne t1,t4,80002db0 + +0000000080002ca8 : + 80002ca8: 00000213 li tp,0 + 80002cac: 800000b7 lui ra,0x80000 + 80002cb0: 0010809b addiw ra,ra,1 + 80002cb4: 41f0df1b sraiw t5,ra,0x1f + 80002cb8: 00000013 nop + 80002cbc: 00000013 nop + 80002cc0: 000f0313 mv t1,t5 + 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc8: 00200293 li t0,2 + 80002ccc: fe5210e3 bne tp,t0,80002cac + 80002cd0: fff00e93 li t4,-1 + 80002cd4: 01400193 li gp,20 + 80002cd8: 0dd31c63 bne t1,t4,80002db0 + +0000000080002cdc : + 80002cdc: 00000213 li tp,0 + 80002ce0: 800000b7 lui ra,0x80000 + 80002ce4: 4070df1b sraiw t5,ra,0x7 + 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cec: 00200293 li t0,2 + 80002cf0: fe5218e3 bne tp,t0,80002ce0 + 80002cf4: ff000eb7 lui t4,0xff000 + 80002cf8: 01500193 li gp,21 + 80002cfc: 0bdf1a63 bne t5,t4,80002db0 + +0000000080002d00 : + 80002d00: 00000213 li tp,0 + 80002d04: 800000b7 lui ra,0x80000 + 80002d08: 00000013 nop + 80002d0c: 40e0df1b sraiw t5,ra,0xe + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fe5216e3 bne tp,t0,80002d04 + 80002d1c: fffe0eb7 lui t4,0xfffe0 + 80002d20: 01600193 li gp,22 + 80002d24: 09df1663 bne t5,t4,80002db0 + +0000000080002d28 : + 80002d28: 00000213 li tp,0 + 80002d2c: 800000b7 lui ra,0x80000 + 80002d30: 0010809b addiw ra,ra,1 + 80002d34: 00000013 nop + 80002d38: 00000013 nop + 80002d3c: 41f0df1b sraiw t5,ra,0x1f + 80002d40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d44: 00200293 li t0,2 + 80002d48: fe5212e3 bne tp,t0,80002d2c + 80002d4c: fff00e93 li t4,-1 + 80002d50: 01700193 li gp,23 + 80002d54: 05df1e63 bne t5,t4,80002db0 + +0000000080002d58 : + 80002d58: 41f0509b sraiw ra,zero,0x1f + 80002d5c: 00000e93 li t4,0 + 80002d60: 01800193 li gp,24 + 80002d64: 05d09663 bne ra,t4,80002db0 + +0000000080002d68 : + 80002d68: 01f00093 li ra,31 + 80002d6c: 41c0d01b sraiw zero,ra,0x1c + 80002d70: 00000e93 li t4,0 + 80002d74: 01900193 li gp,25 + 80002d78: 03d01c63 bne zero,t4,80002db0 + +0000000080002d7c : + 80002d7c: 0070009b addiw ra,zero,7 + 80002d80: 03509093 slli ra,ra,0x35 + 80002d84: 41c0df1b sraiw t5,ra,0x1c + 80002d88: 00000e93 li t4,0 + 80002d8c: 01a00193 li gp,26 + 80002d90: 03df1063 bne t5,t4,80002db0 + +0000000080002d94 : + 80002d94: 00f0009b addiw ra,zero,15 + 80002d98: 01c09093 slli ra,ra,0x1c + 80002d9c: 4040df1b sraiw t5,ra,0x4 + 80002da0: ff000eb7 lui t4,0xff000 + 80002da4: 01b00193 li gp,27 + 80002da8: 01df1463 bne t5,t4,80002db0 + 80002dac: 00301a63 bne zero,gp,80002dc0 + +0000000080002db0 : + 80002db0: 00119513 slli a0,gp,0x1 + 80002db4: 00050063 beqz a0,80002db4 + 80002db8: 00156513 ori a0,a0,1 + 80002dbc: 00000073 ecall + +0000000080002dc0 : + 80002dc0: 00100513 li a0,1 + 80002dc4: 00000073 ecall + 80002dc8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sraiw.elf b/test/riscv/tests/rv64ui-v-sraiw.elf new file mode 100644 index 00000000..9a16cd8e Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sraiw.elf differ diff --git a/test/riscv/tests/rv64ui-v-sraw.dump b/test/riscv/tests/rv64ui-v-sraw.dump new file mode 100644 index 00000000..a2eaf367 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sraw.dump @@ -0,0 +1,1281 @@ + +rv64ui-v-sraw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c2868693 addi a3,a3,-984 # 80003080 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c5c60613 addi a2,a2,-932 # 80003110 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c2460613 addi a2,a2,-988 # 80003128 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: b7468693 addi a3,a3,-1164 # 800030c8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b9068693 addi a3,a3,-1136 # 80003200 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b1060613 addi a2,a2,-1264 # 800031d8 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a4468693 addi a3,a3,-1468 # 80003230 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 96468693 addi a3,a3,-1692 # 800031a0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 8f468693 addi a3,a3,-1804 # 80003168 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03400793 li a5,52 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 077137b7 lui a5,0x7713 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 07b78793 addi a5,a5,123 # 771307b <_start-0x788ecf85> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 00000113 li sp,0 + 80002ad0: 4020df3b sraw t5,ra,sp + 80002ad4: 80000eb7 lui t4,0x80000 + 80002ad8: 00200193 li gp,2 + 80002adc: 59df1463 bne t5,t4,80003064 + +0000000080002ae0 : + 80002ae0: 800000b7 lui ra,0x80000 + 80002ae4: 00100113 li sp,1 + 80002ae8: 4020df3b sraw t5,ra,sp + 80002aec: c0000eb7 lui t4,0xc0000 + 80002af0: 00300193 li gp,3 + 80002af4: 57df1863 bne t5,t4,80003064 + +0000000080002af8 : + 80002af8: 800000b7 lui ra,0x80000 + 80002afc: 00700113 li sp,7 + 80002b00: 4020df3b sraw t5,ra,sp + 80002b04: ff000eb7 lui t4,0xff000 + 80002b08: 00400193 li gp,4 + 80002b0c: 55df1c63 bne t5,t4,80003064 + +0000000080002b10 : + 80002b10: 800000b7 lui ra,0x80000 + 80002b14: 00e00113 li sp,14 + 80002b18: 4020df3b sraw t5,ra,sp + 80002b1c: fffe0eb7 lui t4,0xfffe0 + 80002b20: 00500193 li gp,5 + 80002b24: 55df1063 bne t5,t4,80003064 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 0010809b addiw ra,ra,1 + 80002b30: 01f00113 li sp,31 + 80002b34: 4020df3b sraw t5,ra,sp + 80002b38: fff00e93 li t4,-1 + 80002b3c: 00600193 li gp,6 + 80002b40: 53df1263 bne t5,t4,80003064 + +0000000080002b44 : + 80002b44: 800000b7 lui ra,0x80000 + 80002b48: fff0809b addiw ra,ra,-1 + 80002b4c: 00000113 li sp,0 + 80002b50: 4020df3b sraw t5,ra,sp + 80002b54: 80000eb7 lui t4,0x80000 + 80002b58: fffe8e9b addiw t4,t4,-1 + 80002b5c: 00700193 li gp,7 + 80002b60: 51df1263 bne t5,t4,80003064 + +0000000080002b64 : + 80002b64: 800000b7 lui ra,0x80000 + 80002b68: fff0809b addiw ra,ra,-1 + 80002b6c: 00100113 li sp,1 + 80002b70: 4020df3b sraw t5,ra,sp + 80002b74: 40000eb7 lui t4,0x40000 + 80002b78: fffe8e9b addiw t4,t4,-1 + 80002b7c: 00800193 li gp,8 + 80002b80: 4fdf1263 bne t5,t4,80003064 + +0000000080002b84 : + 80002b84: 800000b7 lui ra,0x80000 + 80002b88: fff0809b addiw ra,ra,-1 + 80002b8c: 00700113 li sp,7 + 80002b90: 4020df3b sraw t5,ra,sp + 80002b94: 01000eb7 lui t4,0x1000 + 80002b98: fffe8e9b addiw t4,t4,-1 + 80002b9c: 00900193 li gp,9 + 80002ba0: 4ddf1263 bne t5,t4,80003064 + +0000000080002ba4 : + 80002ba4: 800000b7 lui ra,0x80000 + 80002ba8: fff0809b addiw ra,ra,-1 + 80002bac: 00e00113 li sp,14 + 80002bb0: 4020df3b sraw t5,ra,sp + 80002bb4: 00020eb7 lui t4,0x20 + 80002bb8: fffe8e9b addiw t4,t4,-1 + 80002bbc: 00a00193 li gp,10 + 80002bc0: 4bdf1263 bne t5,t4,80003064 + +0000000080002bc4 : + 80002bc4: 800000b7 lui ra,0x80000 + 80002bc8: fff0809b addiw ra,ra,-1 + 80002bcc: 01f00113 li sp,31 + 80002bd0: 4020df3b sraw t5,ra,sp + 80002bd4: 00000e93 li t4,0 + 80002bd8: 00b00193 li gp,11 + 80002bdc: 49df1463 bne t5,t4,80003064 + +0000000080002be0 : + 80002be0: 818180b7 lui ra,0x81818 + 80002be4: 1810809b addiw ra,ra,385 + 80002be8: 00000113 li sp,0 + 80002bec: 4020df3b sraw t5,ra,sp + 80002bf0: 81818eb7 lui t4,0x81818 + 80002bf4: 181e8e9b addiw t4,t4,385 + 80002bf8: 00c00193 li gp,12 + 80002bfc: 47df1463 bne t5,t4,80003064 + +0000000080002c00 : + 80002c00: 818180b7 lui ra,0x81818 + 80002c04: 1810809b addiw ra,ra,385 + 80002c08: 00100113 li sp,1 + 80002c0c: 4020df3b sraw t5,ra,sp + 80002c10: c0c0ceb7 lui t4,0xc0c0c + 80002c14: 0c0e8e9b addiw t4,t4,192 + 80002c18: 00d00193 li gp,13 + 80002c1c: 45df1463 bne t5,t4,80003064 + +0000000080002c20 : + 80002c20: 818180b7 lui ra,0x81818 + 80002c24: 1810809b addiw ra,ra,385 + 80002c28: 00700113 li sp,7 + 80002c2c: 4020df3b sraw t5,ra,sp + 80002c30: ff030eb7 lui t4,0xff030 + 80002c34: 303e8e9b addiw t4,t4,771 + 80002c38: 00e00193 li gp,14 + 80002c3c: 43df1463 bne t5,t4,80003064 + +0000000080002c40 : + 80002c40: 818180b7 lui ra,0x81818 + 80002c44: 1810809b addiw ra,ra,385 + 80002c48: 00e00113 li sp,14 + 80002c4c: 4020df3b sraw t5,ra,sp + 80002c50: fffe0eb7 lui t4,0xfffe0 + 80002c54: 606e8e9b addiw t4,t4,1542 + 80002c58: 00f00193 li gp,15 + 80002c5c: 41df1463 bne t5,t4,80003064 + +0000000080002c60 : + 80002c60: 818180b7 lui ra,0x81818 + 80002c64: 1810809b addiw ra,ra,385 + 80002c68: 01f00113 li sp,31 + 80002c6c: 4020df3b sraw t5,ra,sp + 80002c70: fff00e93 li t4,-1 + 80002c74: 01000193 li gp,16 + 80002c78: 3fdf1663 bne t5,t4,80003064 + +0000000080002c7c : + 80002c7c: 818180b7 lui ra,0x81818 + 80002c80: 1810809b addiw ra,ra,385 + 80002c84: fe000113 li sp,-32 + 80002c88: 4020df3b sraw t5,ra,sp + 80002c8c: 81818eb7 lui t4,0x81818 + 80002c90: 181e8e9b addiw t4,t4,385 + 80002c94: 01100193 li gp,17 + 80002c98: 3ddf1663 bne t5,t4,80003064 + +0000000080002c9c : + 80002c9c: 818180b7 lui ra,0x81818 + 80002ca0: 1810809b addiw ra,ra,385 + 80002ca4: fe100113 li sp,-31 + 80002ca8: 4020df3b sraw t5,ra,sp + 80002cac: c0c0ceb7 lui t4,0xc0c0c + 80002cb0: 0c0e8e9b addiw t4,t4,192 + 80002cb4: 01200193 li gp,18 + 80002cb8: 3bdf1663 bne t5,t4,80003064 + +0000000080002cbc : + 80002cbc: 818180b7 lui ra,0x81818 + 80002cc0: 1810809b addiw ra,ra,385 + 80002cc4: fe700113 li sp,-25 + 80002cc8: 4020df3b sraw t5,ra,sp + 80002ccc: ff030eb7 lui t4,0xff030 + 80002cd0: 303e8e9b addiw t4,t4,771 + 80002cd4: 01300193 li gp,19 + 80002cd8: 39df1663 bne t5,t4,80003064 + +0000000080002cdc : + 80002cdc: 818180b7 lui ra,0x81818 + 80002ce0: 1810809b addiw ra,ra,385 + 80002ce4: fee00113 li sp,-18 + 80002ce8: 4020df3b sraw t5,ra,sp + 80002cec: fffe0eb7 lui t4,0xfffe0 + 80002cf0: 606e8e9b addiw t4,t4,1542 + 80002cf4: 01400193 li gp,20 + 80002cf8: 37df1663 bne t5,t4,80003064 + +0000000080002cfc : + 80002cfc: 818180b7 lui ra,0x81818 + 80002d00: 1810809b addiw ra,ra,385 + 80002d04: fff00113 li sp,-1 + 80002d08: 4020df3b sraw t5,ra,sp + 80002d0c: fff00e93 li t4,-1 + 80002d10: 01500193 li gp,21 + 80002d14: 35df1863 bne t5,t4,80003064 + +0000000080002d18 : + 80002d18: 800000b7 lui ra,0x80000 + 80002d1c: 00700113 li sp,7 + 80002d20: 4020d0bb sraw ra,ra,sp + 80002d24: ff000eb7 lui t4,0xff000 + 80002d28: 01600193 li gp,22 + 80002d2c: 33d09c63 bne ra,t4,80003064 + +0000000080002d30 : + 80002d30: 800000b7 lui ra,0x80000 + 80002d34: 00e00113 li sp,14 + 80002d38: 4020d13b sraw sp,ra,sp + 80002d3c: fffe0eb7 lui t4,0xfffe0 + 80002d40: 01700193 li gp,23 + 80002d44: 33d11063 bne sp,t4,80003064 + +0000000080002d48 : + 80002d48: 00700093 li ra,7 + 80002d4c: 4010d0bb sraw ra,ra,ra + 80002d50: 00000e93 li t4,0 + 80002d54: 01800193 li gp,24 + 80002d58: 31d09663 bne ra,t4,80003064 + +0000000080002d5c : + 80002d5c: 00000213 li tp,0 + 80002d60: 800000b7 lui ra,0x80000 + 80002d64: 00700113 li sp,7 + 80002d68: 4020df3b sraw t5,ra,sp + 80002d6c: 000f0313 mv t1,t5 + 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d74: 00200293 li t0,2 + 80002d78: fe5214e3 bne tp,t0,80002d60 + 80002d7c: ff000eb7 lui t4,0xff000 + 80002d80: 01900193 li gp,25 + 80002d84: 2fd31063 bne t1,t4,80003064 + +0000000080002d88 : + 80002d88: 00000213 li tp,0 + 80002d8c: 800000b7 lui ra,0x80000 + 80002d90: 00e00113 li sp,14 + 80002d94: 4020df3b sraw t5,ra,sp + 80002d98: 00000013 nop + 80002d9c: 000f0313 mv t1,t5 + 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da4: 00200293 li t0,2 + 80002da8: fe5212e3 bne tp,t0,80002d8c + 80002dac: fffe0eb7 lui t4,0xfffe0 + 80002db0: 01a00193 li gp,26 + 80002db4: 2bd31863 bne t1,t4,80003064 + +0000000080002db8 : + 80002db8: 00000213 li tp,0 + 80002dbc: 800000b7 lui ra,0x80000 + 80002dc0: 01f00113 li sp,31 + 80002dc4: 4020df3b sraw t5,ra,sp + 80002dc8: 00000013 nop + 80002dcc: 00000013 nop + 80002dd0: 000f0313 mv t1,t5 + 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd8: 00200293 li t0,2 + 80002ddc: fe5210e3 bne tp,t0,80002dbc + 80002de0: fff00e93 li t4,-1 + 80002de4: 01b00193 li gp,27 + 80002de8: 27d31e63 bne t1,t4,80003064 + +0000000080002dec : + 80002dec: 00000213 li tp,0 + 80002df0: 800000b7 lui ra,0x80000 + 80002df4: 00700113 li sp,7 + 80002df8: 4020df3b sraw t5,ra,sp + 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e00: 00200293 li t0,2 + 80002e04: fe5216e3 bne tp,t0,80002df0 + 80002e08: ff000eb7 lui t4,0xff000 + 80002e0c: 01c00193 li gp,28 + 80002e10: 25df1a63 bne t5,t4,80003064 + +0000000080002e14 : + 80002e14: 00000213 li tp,0 + 80002e18: 800000b7 lui ra,0x80000 + 80002e1c: 00e00113 li sp,14 + 80002e20: 00000013 nop + 80002e24: 4020df3b sraw t5,ra,sp + 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e2c: 00200293 li t0,2 + 80002e30: fe5214e3 bne tp,t0,80002e18 + 80002e34: fffe0eb7 lui t4,0xfffe0 + 80002e38: 01d00193 li gp,29 + 80002e3c: 23df1463 bne t5,t4,80003064 + +0000000080002e40 : + 80002e40: 00000213 li tp,0 + 80002e44: 800000b7 lui ra,0x80000 + 80002e48: 01f00113 li sp,31 + 80002e4c: 00000013 nop + 80002e50: 00000013 nop + 80002e54: 4020df3b sraw t5,ra,sp + 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e5c: 00200293 li t0,2 + 80002e60: fe5212e3 bne tp,t0,80002e44 + 80002e64: fff00e93 li t4,-1 + 80002e68: 01e00193 li gp,30 + 80002e6c: 1fdf1c63 bne t5,t4,80003064 + +0000000080002e70 : + 80002e70: 00000213 li tp,0 + 80002e74: 800000b7 lui ra,0x80000 + 80002e78: 00000013 nop + 80002e7c: 00700113 li sp,7 + 80002e80: 4020df3b sraw t5,ra,sp + 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e88: 00200293 li t0,2 + 80002e8c: fe5214e3 bne tp,t0,80002e74 + 80002e90: ff000eb7 lui t4,0xff000 + 80002e94: 01f00193 li gp,31 + 80002e98: 1ddf1663 bne t5,t4,80003064 + +0000000080002e9c : + 80002e9c: 00000213 li tp,0 + 80002ea0: 800000b7 lui ra,0x80000 + 80002ea4: 00000013 nop + 80002ea8: 00e00113 li sp,14 + 80002eac: 00000013 nop + 80002eb0: 4020df3b sraw t5,ra,sp + 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002eb8: 00200293 li t0,2 + 80002ebc: fe5212e3 bne tp,t0,80002ea0 + 80002ec0: fffe0eb7 lui t4,0xfffe0 + 80002ec4: 02000193 li gp,32 + 80002ec8: 19df1e63 bne t5,t4,80003064 + +0000000080002ecc : + 80002ecc: 00000213 li tp,0 + 80002ed0: 800000b7 lui ra,0x80000 + 80002ed4: 00000013 nop + 80002ed8: 00000013 nop + 80002edc: 01f00113 li sp,31 + 80002ee0: 4020df3b sraw t5,ra,sp + 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee8: 00200293 li t0,2 + 80002eec: fe5212e3 bne tp,t0,80002ed0 + 80002ef0: fff00e93 li t4,-1 + 80002ef4: 02100193 li gp,33 + 80002ef8: 17df1663 bne t5,t4,80003064 + +0000000080002efc : + 80002efc: 00000213 li tp,0 + 80002f00: 00700113 li sp,7 + 80002f04: 800000b7 lui ra,0x80000 + 80002f08: 4020df3b sraw t5,ra,sp + 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f10: 00200293 li t0,2 + 80002f14: fe5216e3 bne tp,t0,80002f00 + 80002f18: ff000eb7 lui t4,0xff000 + 80002f1c: 02200193 li gp,34 + 80002f20: 15df1263 bne t5,t4,80003064 + +0000000080002f24 : + 80002f24: 00000213 li tp,0 + 80002f28: 00e00113 li sp,14 + 80002f2c: 800000b7 lui ra,0x80000 + 80002f30: 00000013 nop + 80002f34: 4020df3b sraw t5,ra,sp + 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f3c: 00200293 li t0,2 + 80002f40: fe5214e3 bne tp,t0,80002f28 + 80002f44: fffe0eb7 lui t4,0xfffe0 + 80002f48: 02300193 li gp,35 + 80002f4c: 11df1c63 bne t5,t4,80003064 + +0000000080002f50 : + 80002f50: 00000213 li tp,0 + 80002f54: 01f00113 li sp,31 + 80002f58: 800000b7 lui ra,0x80000 + 80002f5c: 00000013 nop + 80002f60: 00000013 nop + 80002f64: 4020df3b sraw t5,ra,sp + 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f6c: 00200293 li t0,2 + 80002f70: fe5212e3 bne tp,t0,80002f54 + 80002f74: fff00e93 li t4,-1 + 80002f78: 02400193 li gp,36 + 80002f7c: 0fdf1463 bne t5,t4,80003064 + +0000000080002f80 : + 80002f80: 00000213 li tp,0 + 80002f84: 00700113 li sp,7 + 80002f88: 00000013 nop + 80002f8c: 800000b7 lui ra,0x80000 + 80002f90: 4020df3b sraw t5,ra,sp + 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f98: 00200293 li t0,2 + 80002f9c: fe5214e3 bne tp,t0,80002f84 + 80002fa0: ff000eb7 lui t4,0xff000 + 80002fa4: 02500193 li gp,37 + 80002fa8: 0bdf1e63 bne t5,t4,80003064 + +0000000080002fac : + 80002fac: 00000213 li tp,0 + 80002fb0: 00e00113 li sp,14 + 80002fb4: 00000013 nop + 80002fb8: 800000b7 lui ra,0x80000 + 80002fbc: 00000013 nop + 80002fc0: 4020df3b sraw t5,ra,sp + 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fc8: 00200293 li t0,2 + 80002fcc: fe5212e3 bne tp,t0,80002fb0 + 80002fd0: fffe0eb7 lui t4,0xfffe0 + 80002fd4: 02600193 li gp,38 + 80002fd8: 09df1663 bne t5,t4,80003064 + +0000000080002fdc : + 80002fdc: 00000213 li tp,0 + 80002fe0: 01f00113 li sp,31 + 80002fe4: 00000013 nop + 80002fe8: 00000013 nop + 80002fec: 800000b7 lui ra,0x80000 + 80002ff0: 4020df3b sraw t5,ra,sp + 80002ff4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ff8: 00200293 li t0,2 + 80002ffc: fe5212e3 bne tp,t0,80002fe0 + 80003000: fff00e93 li t4,-1 + 80003004: 02700193 li gp,39 + 80003008: 05df1e63 bne t5,t4,80003064 + +000000008000300c : + 8000300c: 00f00093 li ra,15 + 80003010: 4010513b sraw sp,zero,ra + 80003014: 00000e93 li t4,0 + 80003018: 02800193 li gp,40 + 8000301c: 05d11463 bne sp,t4,80003064 + +0000000080003020 : + 80003020: 02000093 li ra,32 + 80003024: 4000d13b sraw sp,ra,zero + 80003028: 02000e93 li t4,32 + 8000302c: 02900193 li gp,41 + 80003030: 03d11a63 bne sp,t4,80003064 + +0000000080003034 : + 80003034: 400050bb sraw ra,zero,zero + 80003038: 00000e93 li t4,0 + 8000303c: 02a00193 li gp,42 + 80003040: 03d09263 bne ra,t4,80003064 + +0000000080003044 : + 80003044: 40000093 li ra,1024 + 80003048: 00001137 lui sp,0x1 + 8000304c: 8001011b addiw sp,sp,-2048 + 80003050: 4020d03b sraw zero,ra,sp + 80003054: 00000e93 li t4,0 + 80003058: 02b00193 li gp,43 + 8000305c: 01d01463 bne zero,t4,80003064 + 80003060: 00301a63 bne zero,gp,80003074 + +0000000080003064 : + 80003064: 00119513 slli a0,gp,0x1 + 80003068: 00050063 beqz a0,80003068 + 8000306c: 00156513 ori a0,a0,1 + 80003070: 00000073 ecall + +0000000080003074 : + 80003074: 00100513 li a0,1 + 80003078: 00000073 ecall + 8000307c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sraw.elf b/test/riscv/tests/rv64ui-v-sraw.elf new file mode 100644 index 00000000..8894a1c3 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sraw.elf differ diff --git a/test/riscv/tests/rv64ui-v-srl.dump b/test/riscv/tests/rv64ui-v-srl.dump new file mode 100644 index 00000000..1fb24ac1 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-srl.dump @@ -0,0 +1,1308 @@ + +rv64ui-v-srl: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c9868693 addi a3,a3,-872 # 800030f0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: ccc60613 addi a2,a2,-820 # 80003180 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c9460613 addi a2,a2,-876 # 80003198 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: be468693 addi a3,a3,-1052 # 80003138 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: c0068693 addi a3,a3,-1024 # 80003270 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b8060613 addi a2,a2,-1152 # 80003248 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: ab468693 addi a3,a3,-1356 # 800032a0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 9d468693 addi a3,a3,-1580 # 80003210 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 96468693 addi a3,a3,-1692 # 800031d8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02700793 li a5,39 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 01e8a7b7 lui a5,0x1e8a + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 84078793 addi a5,a5,-1984 # 1e89840 <_start-0x7e1767c0> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 00000113 li sp,0 + 80002ad0: 0020df33 srl t5,ra,sp + 80002ad4: 80000eb7 lui t4,0x80000 + 80002ad8: 00200193 li gp,2 + 80002adc: 5fdf1a63 bne t5,t4,800030d0 + +0000000080002ae0 : + 80002ae0: 800000b7 lui ra,0x80000 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0020df33 srl t5,ra,sp + 80002aec: 00100e9b addiw t4,zero,1 + 80002af0: 021e9e93 slli t4,t4,0x21 + 80002af4: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> + 80002af8: 01ee9e93 slli t4,t4,0x1e + 80002afc: 00300193 li gp,3 + 80002b00: 5ddf1863 bne t5,t4,800030d0 + +0000000080002b04 : + 80002b04: 800000b7 lui ra,0x80000 + 80002b08: 00700113 li sp,7 + 80002b0c: 0020df33 srl t5,ra,sp + 80002b10: 00100e9b addiw t4,zero,1 + 80002b14: 021e9e93 slli t4,t4,0x21 + 80002b18: fffe8e93 addi t4,t4,-1 + 80002b1c: 018e9e93 slli t4,t4,0x18 + 80002b20: 00400193 li gp,4 + 80002b24: 5bdf1663 bne t5,t4,800030d0 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00e00113 li sp,14 + 80002b30: 0020df33 srl t5,ra,sp + 80002b34: 00100e9b addiw t4,zero,1 + 80002b38: 021e9e93 slli t4,t4,0x21 + 80002b3c: fffe8e93 addi t4,t4,-1 + 80002b40: 011e9e93 slli t4,t4,0x11 + 80002b44: 00500193 li gp,5 + 80002b48: 59df1463 bne t5,t4,800030d0 + +0000000080002b4c : + 80002b4c: 800000b7 lui ra,0x80000 + 80002b50: 0010809b addiw ra,ra,1 + 80002b54: 01f00113 li sp,31 + 80002b58: 0020df33 srl t5,ra,sp + 80002b5c: 00100e9b addiw t4,zero,1 + 80002b60: 021e9e93 slli t4,t4,0x21 + 80002b64: fffe8e93 addi t4,t4,-1 + 80002b68: 00600193 li gp,6 + 80002b6c: 57df1263 bne t5,t4,800030d0 + +0000000080002b70 : + 80002b70: fff00093 li ra,-1 + 80002b74: 00000113 li sp,0 + 80002b78: 0020df33 srl t5,ra,sp + 80002b7c: fff00e93 li t4,-1 + 80002b80: 00700193 li gp,7 + 80002b84: 55df1663 bne t5,t4,800030d0 + +0000000080002b88 : + 80002b88: fff00093 li ra,-1 + 80002b8c: 00100113 li sp,1 + 80002b90: 0020df33 srl t5,ra,sp + 80002b94: fff00e9b addiw t4,zero,-1 + 80002b98: 03fe9e93 slli t4,t4,0x3f + 80002b9c: fffe8e93 addi t4,t4,-1 + 80002ba0: 00800193 li gp,8 + 80002ba4: 53df1663 bne t5,t4,800030d0 + +0000000080002ba8 : + 80002ba8: fff00093 li ra,-1 + 80002bac: 00700113 li sp,7 + 80002bb0: 0020df33 srl t5,ra,sp + 80002bb4: 00100e9b addiw t4,zero,1 + 80002bb8: 039e9e93 slli t4,t4,0x39 + 80002bbc: fffe8e93 addi t4,t4,-1 + 80002bc0: 00900193 li gp,9 + 80002bc4: 51df1663 bne t5,t4,800030d0 + +0000000080002bc8 : + 80002bc8: fff00093 li ra,-1 + 80002bcc: 00e00113 li sp,14 + 80002bd0: 0020df33 srl t5,ra,sp + 80002bd4: 00100e9b addiw t4,zero,1 + 80002bd8: 032e9e93 slli t4,t4,0x32 + 80002bdc: fffe8e93 addi t4,t4,-1 + 80002be0: 00a00193 li gp,10 + 80002be4: 4fdf1663 bne t5,t4,800030d0 + +0000000080002be8 : + 80002be8: fff00093 li ra,-1 + 80002bec: 01f00113 li sp,31 + 80002bf0: 0020df33 srl t5,ra,sp + 80002bf4: 00100e9b addiw t4,zero,1 + 80002bf8: 021e9e93 slli t4,t4,0x21 + 80002bfc: fffe8e93 addi t4,t4,-1 + 80002c00: 00b00193 li gp,11 + 80002c04: 4ddf1663 bne t5,t4,800030d0 + +0000000080002c08 : + 80002c08: 212120b7 lui ra,0x21212 + 80002c0c: 1210809b addiw ra,ra,289 + 80002c10: 00000113 li sp,0 + 80002c14: 0020df33 srl t5,ra,sp + 80002c18: 21212eb7 lui t4,0x21212 + 80002c1c: 121e8e9b addiw t4,t4,289 + 80002c20: 00c00193 li gp,12 + 80002c24: 4bdf1663 bne t5,t4,800030d0 + +0000000080002c28 : + 80002c28: 212120b7 lui ra,0x21212 + 80002c2c: 1210809b addiw ra,ra,289 + 80002c30: 00100113 li sp,1 + 80002c34: 0020df33 srl t5,ra,sp + 80002c38: 10909eb7 lui t4,0x10909 + 80002c3c: 090e8e9b addiw t4,t4,144 + 80002c40: 00d00193 li gp,13 + 80002c44: 49df1663 bne t5,t4,800030d0 + +0000000080002c48 : + 80002c48: 212120b7 lui ra,0x21212 + 80002c4c: 1210809b addiw ra,ra,289 + 80002c50: 00700113 li sp,7 + 80002c54: 0020df33 srl t5,ra,sp + 80002c58: 00424eb7 lui t4,0x424 + 80002c5c: 242e8e9b addiw t4,t4,578 + 80002c60: 00e00193 li gp,14 + 80002c64: 47df1663 bne t5,t4,800030d0 + +0000000080002c68 : + 80002c68: 212120b7 lui ra,0x21212 + 80002c6c: 1210809b addiw ra,ra,289 + 80002c70: 00e00113 li sp,14 + 80002c74: 0020df33 srl t5,ra,sp + 80002c78: 00008eb7 lui t4,0x8 + 80002c7c: 484e8e9b addiw t4,t4,1156 + 80002c80: 00f00193 li gp,15 + 80002c84: 45df1663 bne t5,t4,800030d0 + +0000000080002c88 : + 80002c88: 212120b7 lui ra,0x21212 + 80002c8c: 1210809b addiw ra,ra,289 + 80002c90: 01f00113 li sp,31 + 80002c94: 0020df33 srl t5,ra,sp + 80002c98: 00000e93 li t4,0 + 80002c9c: 01000193 li gp,16 + 80002ca0: 43df1863 bne t5,t4,800030d0 + +0000000080002ca4 : + 80002ca4: 212120b7 lui ra,0x21212 + 80002ca8: 1210809b addiw ra,ra,289 + 80002cac: fc000113 li sp,-64 + 80002cb0: 0020df33 srl t5,ra,sp + 80002cb4: 21212eb7 lui t4,0x21212 + 80002cb8: 121e8e9b addiw t4,t4,289 + 80002cbc: 01100193 li gp,17 + 80002cc0: 41df1863 bne t5,t4,800030d0 + +0000000080002cc4 : + 80002cc4: 212120b7 lui ra,0x21212 + 80002cc8: 1210809b addiw ra,ra,289 + 80002ccc: fc100113 li sp,-63 + 80002cd0: 0020df33 srl t5,ra,sp + 80002cd4: 10909eb7 lui t4,0x10909 + 80002cd8: 090e8e9b addiw t4,t4,144 + 80002cdc: 01200193 li gp,18 + 80002ce0: 3fdf1863 bne t5,t4,800030d0 + +0000000080002ce4 : + 80002ce4: 212120b7 lui ra,0x21212 + 80002ce8: 1210809b addiw ra,ra,289 + 80002cec: fc700113 li sp,-57 + 80002cf0: 0020df33 srl t5,ra,sp + 80002cf4: 00424eb7 lui t4,0x424 + 80002cf8: 242e8e9b addiw t4,t4,578 + 80002cfc: 01300193 li gp,19 + 80002d00: 3ddf1863 bne t5,t4,800030d0 + +0000000080002d04 : + 80002d04: 212120b7 lui ra,0x21212 + 80002d08: 1210809b addiw ra,ra,289 + 80002d0c: fce00113 li sp,-50 + 80002d10: 0020df33 srl t5,ra,sp + 80002d14: 00008eb7 lui t4,0x8 + 80002d18: 484e8e9b addiw t4,t4,1156 + 80002d1c: 01400193 li gp,20 + 80002d20: 3bdf1863 bne t5,t4,800030d0 + +0000000080002d24 : + 80002d24: 212120b7 lui ra,0x21212 + 80002d28: 1210809b addiw ra,ra,289 + 80002d2c: fff00113 li sp,-1 + 80002d30: 0020df33 srl t5,ra,sp + 80002d34: 00000e93 li t4,0 + 80002d38: 01500193 li gp,21 + 80002d3c: 39df1a63 bne t5,t4,800030d0 + +0000000080002d40 : + 80002d40: 0010009b addiw ra,zero,1 + 80002d44: 01f09093 slli ra,ra,0x1f + 80002d48: 00700113 li sp,7 + 80002d4c: 0020d0b3 srl ra,ra,sp + 80002d50: 01000eb7 lui t4,0x1000 + 80002d54: 01600193 li gp,22 + 80002d58: 37d09c63 bne ra,t4,800030d0 + +0000000080002d5c : + 80002d5c: 0010009b addiw ra,zero,1 + 80002d60: 01f09093 slli ra,ra,0x1f + 80002d64: 00e00113 li sp,14 + 80002d68: 0020d133 srl sp,ra,sp + 80002d6c: 00020eb7 lui t4,0x20 + 80002d70: 01700193 li gp,23 + 80002d74: 35d11e63 bne sp,t4,800030d0 + +0000000080002d78 : + 80002d78: 00700093 li ra,7 + 80002d7c: 0010d0b3 srl ra,ra,ra + 80002d80: 00000e93 li t4,0 + 80002d84: 01800193 li gp,24 + 80002d88: 35d09463 bne ra,t4,800030d0 + +0000000080002d8c : + 80002d8c: 00000213 li tp,0 + 80002d90: 0010009b addiw ra,zero,1 + 80002d94: 01f09093 slli ra,ra,0x1f + 80002d98: 00700113 li sp,7 + 80002d9c: 0020df33 srl t5,ra,sp + 80002da0: 000f0313 mv t1,t5 + 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002da8: 00200293 li t0,2 + 80002dac: fe5212e3 bne tp,t0,80002d90 + 80002db0: 01000eb7 lui t4,0x1000 + 80002db4: 01900193 li gp,25 + 80002db8: 31d31c63 bne t1,t4,800030d0 + +0000000080002dbc : + 80002dbc: 00000213 li tp,0 + 80002dc0: 0010009b addiw ra,zero,1 + 80002dc4: 01f09093 slli ra,ra,0x1f + 80002dc8: 00e00113 li sp,14 + 80002dcc: 0020df33 srl t5,ra,sp + 80002dd0: 00000013 nop + 80002dd4: 000f0313 mv t1,t5 + 80002dd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ddc: 00200293 li t0,2 + 80002de0: fe5210e3 bne tp,t0,80002dc0 + 80002de4: 00020eb7 lui t4,0x20 + 80002de8: 01a00193 li gp,26 + 80002dec: 2fd31263 bne t1,t4,800030d0 + +0000000080002df0 : + 80002df0: 00000213 li tp,0 + 80002df4: 0010009b addiw ra,zero,1 + 80002df8: 01f09093 slli ra,ra,0x1f + 80002dfc: 01f00113 li sp,31 + 80002e00: 0020df33 srl t5,ra,sp + 80002e04: 00000013 nop + 80002e08: 00000013 nop + 80002e0c: 000f0313 mv t1,t5 + 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e14: 00200293 li t0,2 + 80002e18: fc521ee3 bne tp,t0,80002df4 + 80002e1c: 00100e93 li t4,1 + 80002e20: 01b00193 li gp,27 + 80002e24: 2bd31663 bne t1,t4,800030d0 + +0000000080002e28 : + 80002e28: 00000213 li tp,0 + 80002e2c: 0010009b addiw ra,zero,1 + 80002e30: 01f09093 slli ra,ra,0x1f + 80002e34: 00700113 li sp,7 + 80002e38: 0020df33 srl t5,ra,sp + 80002e3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e40: 00200293 li t0,2 + 80002e44: fe5214e3 bne tp,t0,80002e2c + 80002e48: 01000eb7 lui t4,0x1000 + 80002e4c: 01c00193 li gp,28 + 80002e50: 29df1063 bne t5,t4,800030d0 + +0000000080002e54 : + 80002e54: 00000213 li tp,0 + 80002e58: 0010009b addiw ra,zero,1 + 80002e5c: 01f09093 slli ra,ra,0x1f + 80002e60: 00e00113 li sp,14 + 80002e64: 00000013 nop + 80002e68: 0020df33 srl t5,ra,sp + 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e70: 00200293 li t0,2 + 80002e74: fe5212e3 bne tp,t0,80002e58 + 80002e78: 00020eb7 lui t4,0x20 + 80002e7c: 01d00193 li gp,29 + 80002e80: 25df1863 bne t5,t4,800030d0 + +0000000080002e84 : + 80002e84: 00000213 li tp,0 + 80002e88: 0010009b addiw ra,zero,1 + 80002e8c: 01f09093 slli ra,ra,0x1f + 80002e90: 01f00113 li sp,31 + 80002e94: 00000013 nop + 80002e98: 00000013 nop + 80002e9c: 0020df33 srl t5,ra,sp + 80002ea0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea4: 00200293 li t0,2 + 80002ea8: fe5210e3 bne tp,t0,80002e88 + 80002eac: 00100e93 li t4,1 + 80002eb0: 01e00193 li gp,30 + 80002eb4: 21df1e63 bne t5,t4,800030d0 + +0000000080002eb8 : + 80002eb8: 00000213 li tp,0 + 80002ebc: 0010009b addiw ra,zero,1 + 80002ec0: 01f09093 slli ra,ra,0x1f + 80002ec4: 00000013 nop + 80002ec8: 00700113 li sp,7 + 80002ecc: 0020df33 srl t5,ra,sp + 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ed4: 00200293 li t0,2 + 80002ed8: fe5212e3 bne tp,t0,80002ebc + 80002edc: 01000eb7 lui t4,0x1000 + 80002ee0: 01f00193 li gp,31 + 80002ee4: 1fdf1663 bne t5,t4,800030d0 + +0000000080002ee8 : + 80002ee8: 00000213 li tp,0 + 80002eec: 0010009b addiw ra,zero,1 + 80002ef0: 01f09093 slli ra,ra,0x1f + 80002ef4: 00000013 nop + 80002ef8: 00e00113 li sp,14 + 80002efc: 00000013 nop + 80002f00: 0020df33 srl t5,ra,sp + 80002f04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f08: 00200293 li t0,2 + 80002f0c: fe5210e3 bne tp,t0,80002eec + 80002f10: 00020eb7 lui t4,0x20 + 80002f14: 02000193 li gp,32 + 80002f18: 1bdf1c63 bne t5,t4,800030d0 + +0000000080002f1c : + 80002f1c: 00000213 li tp,0 + 80002f20: 0010009b addiw ra,zero,1 + 80002f24: 01f09093 slli ra,ra,0x1f + 80002f28: 00000013 nop + 80002f2c: 00000013 nop + 80002f30: 01f00113 li sp,31 + 80002f34: 0020df33 srl t5,ra,sp + 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f3c: 00200293 li t0,2 + 80002f40: fe5210e3 bne tp,t0,80002f20 + 80002f44: 00100e93 li t4,1 + 80002f48: 02100193 li gp,33 + 80002f4c: 19df1263 bne t5,t4,800030d0 + +0000000080002f50 : + 80002f50: 00000213 li tp,0 + 80002f54: 00700113 li sp,7 + 80002f58: 0010009b addiw ra,zero,1 + 80002f5c: 01f09093 slli ra,ra,0x1f + 80002f60: 0020df33 srl t5,ra,sp + 80002f64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f68: 00200293 li t0,2 + 80002f6c: fe5214e3 bne tp,t0,80002f54 + 80002f70: 01000eb7 lui t4,0x1000 + 80002f74: 02200193 li gp,34 + 80002f78: 15df1c63 bne t5,t4,800030d0 + +0000000080002f7c : + 80002f7c: 00000213 li tp,0 + 80002f80: 00e00113 li sp,14 + 80002f84: 0010009b addiw ra,zero,1 + 80002f88: 01f09093 slli ra,ra,0x1f + 80002f8c: 00000013 nop + 80002f90: 0020df33 srl t5,ra,sp + 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f98: 00200293 li t0,2 + 80002f9c: fe5212e3 bne tp,t0,80002f80 + 80002fa0: 00020eb7 lui t4,0x20 + 80002fa4: 02300193 li gp,35 + 80002fa8: 13df1463 bne t5,t4,800030d0 + +0000000080002fac : + 80002fac: 00000213 li tp,0 + 80002fb0: 01f00113 li sp,31 + 80002fb4: 0010009b addiw ra,zero,1 + 80002fb8: 01f09093 slli ra,ra,0x1f + 80002fbc: 00000013 nop + 80002fc0: 00000013 nop + 80002fc4: 0020df33 srl t5,ra,sp + 80002fc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fcc: 00200293 li t0,2 + 80002fd0: fe5210e3 bne tp,t0,80002fb0 + 80002fd4: 00100e93 li t4,1 + 80002fd8: 02400193 li gp,36 + 80002fdc: 0fdf1a63 bne t5,t4,800030d0 + +0000000080002fe0 : + 80002fe0: 00000213 li tp,0 + 80002fe4: 00700113 li sp,7 + 80002fe8: 00000013 nop + 80002fec: 0010009b addiw ra,zero,1 + 80002ff0: 01f09093 slli ra,ra,0x1f + 80002ff4: 0020df33 srl t5,ra,sp + 80002ff8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ffc: 00200293 li t0,2 + 80003000: fe5212e3 bne tp,t0,80002fe4 + 80003004: 01000eb7 lui t4,0x1000 + 80003008: 02500193 li gp,37 + 8000300c: 0ddf1263 bne t5,t4,800030d0 + +0000000080003010 : + 80003010: 00000213 li tp,0 + 80003014: 00e00113 li sp,14 + 80003018: 00000013 nop + 8000301c: 0010009b addiw ra,zero,1 + 80003020: 01f09093 slli ra,ra,0x1f + 80003024: 00000013 nop + 80003028: 0020df33 srl t5,ra,sp + 8000302c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003030: 00200293 li t0,2 + 80003034: fe5210e3 bne tp,t0,80003014 + 80003038: 00020eb7 lui t4,0x20 + 8000303c: 02600193 li gp,38 + 80003040: 09df1863 bne t5,t4,800030d0 + +0000000080003044 : + 80003044: 00000213 li tp,0 + 80003048: 01f00113 li sp,31 + 8000304c: 00000013 nop + 80003050: 00000013 nop + 80003054: 0010009b addiw ra,zero,1 + 80003058: 01f09093 slli ra,ra,0x1f + 8000305c: 0020df33 srl t5,ra,sp + 80003060: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80003064: 00200293 li t0,2 + 80003068: fe5210e3 bne tp,t0,80003048 + 8000306c: 00100e93 li t4,1 + 80003070: 02700193 li gp,39 + 80003074: 05df1e63 bne t5,t4,800030d0 + +0000000080003078 : + 80003078: 00f00093 li ra,15 + 8000307c: 00105133 srl sp,zero,ra + 80003080: 00000e93 li t4,0 + 80003084: 02800193 li gp,40 + 80003088: 05d11463 bne sp,t4,800030d0 + +000000008000308c : + 8000308c: 02000093 li ra,32 + 80003090: 0000d133 srl sp,ra,zero + 80003094: 02000e93 li t4,32 + 80003098: 02900193 li gp,41 + 8000309c: 03d11a63 bne sp,t4,800030d0 + +00000000800030a0 : + 800030a0: 000050b3 srl ra,zero,zero + 800030a4: 00000e93 li t4,0 + 800030a8: 02a00193 li gp,42 + 800030ac: 03d09263 bne ra,t4,800030d0 + +00000000800030b0 : + 800030b0: 40000093 li ra,1024 + 800030b4: 00001137 lui sp,0x1 + 800030b8: 8001011b addiw sp,sp,-2048 + 800030bc: 0020d033 srl zero,ra,sp + 800030c0: 00000e93 li t4,0 + 800030c4: 02b00193 li gp,43 + 800030c8: 01d01463 bne zero,t4,800030d0 + 800030cc: 00301a63 bne zero,gp,800030e0 + +00000000800030d0 : + 800030d0: 00119513 slli a0,gp,0x1 + 800030d4: 00050063 beqz a0,800030d4 + 800030d8: 00156513 ori a0,a0,1 + 800030dc: 00000073 ecall + +00000000800030e0 : + 800030e0: 00100513 li a0,1 + 800030e4: 00000073 ecall + 800030e8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srl.elf b/test/riscv/tests/rv64ui-v-srl.elf new file mode 100644 index 00000000..eb8b7327 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-srl.elf differ diff --git a/test/riscv/tests/rv64ui-v-srli.dump b/test/riscv/tests/rv64ui-v-srli.dump new file mode 100644 index 00000000..d900518e --- /dev/null +++ b/test/riscv/tests/rv64ui-v-srli.dump @@ -0,0 +1,1077 @@ + +rv64ui-v-srli: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 98868693 addi a3,a3,-1656 # 80002de0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 9bc60613 addi a2,a2,-1604 # 80002e70 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 98460613 addi a2,a2,-1660 # 80002e88 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 8d468693 addi a3,a3,-1836 # 80002e28 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 8f068693 addi a3,a3,-1808 # 80002f60 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 87060613 addi a2,a2,-1936 # 80002f38 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 7a468693 addi a3,a3,1956 # 80002f90 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 6c468693 addi a3,a3,1732 # 80002f00 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 65468693 addi a3,a3,1620 # 80002ec8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02e00793 li a5,46 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0d3727b7 lui a5,0xd372 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 50c78793 addi a5,a5,1292 # d37250c <_start-0x72c8daf4> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 0000df13 srli t5,ra,0x0 + 80002ad0: 80000eb7 lui t4,0x80000 + 80002ad4: 00200193 li gp,2 + 80002ad8: 2fdf1663 bne t5,t4,80002dc4 + +0000000080002adc : + 80002adc: 800000b7 lui ra,0x80000 + 80002ae0: 0010df13 srli t5,ra,0x1 + 80002ae4: 00100e9b addiw t4,zero,1 + 80002ae8: 021e9e93 slli t4,t4,0x21 + 80002aec: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffff880f> + 80002af0: 01ee9e93 slli t4,t4,0x1e + 80002af4: 00300193 li gp,3 + 80002af8: 2ddf1663 bne t5,t4,80002dc4 + +0000000080002afc : + 80002afc: 800000b7 lui ra,0x80000 + 80002b00: 0070df13 srli t5,ra,0x7 + 80002b04: 00100e9b addiw t4,zero,1 + 80002b08: 021e9e93 slli t4,t4,0x21 + 80002b0c: fffe8e93 addi t4,t4,-1 + 80002b10: 018e9e93 slli t4,t4,0x18 + 80002b14: 00400193 li gp,4 + 80002b18: 2bdf1663 bne t5,t4,80002dc4 + +0000000080002b1c : + 80002b1c: 800000b7 lui ra,0x80000 + 80002b20: 00e0df13 srli t5,ra,0xe + 80002b24: 00100e9b addiw t4,zero,1 + 80002b28: 021e9e93 slli t4,t4,0x21 + 80002b2c: fffe8e93 addi t4,t4,-1 + 80002b30: 011e9e93 slli t4,t4,0x11 + 80002b34: 00500193 li gp,5 + 80002b38: 29df1663 bne t5,t4,80002dc4 + +0000000080002b3c : + 80002b3c: 800000b7 lui ra,0x80000 + 80002b40: 0010809b addiw ra,ra,1 + 80002b44: 01f0df13 srli t5,ra,0x1f + 80002b48: 00100e9b addiw t4,zero,1 + 80002b4c: 021e9e93 slli t4,t4,0x21 + 80002b50: fffe8e93 addi t4,t4,-1 + 80002b54: 00600193 li gp,6 + 80002b58: 27df1663 bne t5,t4,80002dc4 + +0000000080002b5c : + 80002b5c: fff00093 li ra,-1 + 80002b60: 0000df13 srli t5,ra,0x0 + 80002b64: fff00e93 li t4,-1 + 80002b68: 00700193 li gp,7 + 80002b6c: 25df1c63 bne t5,t4,80002dc4 + +0000000080002b70 : + 80002b70: fff00093 li ra,-1 + 80002b74: 0010df13 srli t5,ra,0x1 + 80002b78: fff00e9b addiw t4,zero,-1 + 80002b7c: 03fe9e93 slli t4,t4,0x3f + 80002b80: fffe8e93 addi t4,t4,-1 + 80002b84: 00800193 li gp,8 + 80002b88: 23df1e63 bne t5,t4,80002dc4 + +0000000080002b8c : + 80002b8c: fff00093 li ra,-1 + 80002b90: 0070df13 srli t5,ra,0x7 + 80002b94: 00100e9b addiw t4,zero,1 + 80002b98: 039e9e93 slli t4,t4,0x39 + 80002b9c: fffe8e93 addi t4,t4,-1 + 80002ba0: 00900193 li gp,9 + 80002ba4: 23df1063 bne t5,t4,80002dc4 + +0000000080002ba8 : + 80002ba8: fff00093 li ra,-1 + 80002bac: 00e0df13 srli t5,ra,0xe + 80002bb0: 00100e9b addiw t4,zero,1 + 80002bb4: 032e9e93 slli t4,t4,0x32 + 80002bb8: fffe8e93 addi t4,t4,-1 + 80002bbc: 00a00193 li gp,10 + 80002bc0: 21df1263 bne t5,t4,80002dc4 + +0000000080002bc4 : + 80002bc4: fff00093 li ra,-1 + 80002bc8: 01f0df13 srli t5,ra,0x1f + 80002bcc: 00100e9b addiw t4,zero,1 + 80002bd0: 021e9e93 slli t4,t4,0x21 + 80002bd4: fffe8e93 addi t4,t4,-1 + 80002bd8: 00b00193 li gp,11 + 80002bdc: 1fdf1463 bne t5,t4,80002dc4 + +0000000080002be0 : + 80002be0: 212120b7 lui ra,0x21212 + 80002be4: 1210809b addiw ra,ra,289 + 80002be8: 0000df13 srli t5,ra,0x0 + 80002bec: 21212eb7 lui t4,0x21212 + 80002bf0: 121e8e9b addiw t4,t4,289 + 80002bf4: 00c00193 li gp,12 + 80002bf8: 1ddf1663 bne t5,t4,80002dc4 + +0000000080002bfc : + 80002bfc: 212120b7 lui ra,0x21212 + 80002c00: 1210809b addiw ra,ra,289 + 80002c04: 0010df13 srli t5,ra,0x1 + 80002c08: 10909eb7 lui t4,0x10909 + 80002c0c: 090e8e9b addiw t4,t4,144 + 80002c10: 00d00193 li gp,13 + 80002c14: 1bdf1863 bne t5,t4,80002dc4 + +0000000080002c18 : + 80002c18: 212120b7 lui ra,0x21212 + 80002c1c: 1210809b addiw ra,ra,289 + 80002c20: 0070df13 srli t5,ra,0x7 + 80002c24: 00424eb7 lui t4,0x424 + 80002c28: 242e8e9b addiw t4,t4,578 + 80002c2c: 00e00193 li gp,14 + 80002c30: 19df1a63 bne t5,t4,80002dc4 + +0000000080002c34 : + 80002c34: 212120b7 lui ra,0x21212 + 80002c38: 1210809b addiw ra,ra,289 + 80002c3c: 00e0df13 srli t5,ra,0xe + 80002c40: 00008eb7 lui t4,0x8 + 80002c44: 484e8e9b addiw t4,t4,1156 + 80002c48: 00f00193 li gp,15 + 80002c4c: 17df1c63 bne t5,t4,80002dc4 + +0000000080002c50 : + 80002c50: 212120b7 lui ra,0x21212 + 80002c54: 1210809b addiw ra,ra,289 + 80002c58: 01f0df13 srli t5,ra,0x1f + 80002c5c: 00000e93 li t4,0 + 80002c60: 01000193 li gp,16 + 80002c64: 17df1063 bne t5,t4,80002dc4 + +0000000080002c68 : + 80002c68: 0010009b addiw ra,zero,1 + 80002c6c: 01f09093 slli ra,ra,0x1f + 80002c70: 0070d093 srli ra,ra,0x7 + 80002c74: 01000eb7 lui t4,0x1000 + 80002c78: 01100193 li gp,17 + 80002c7c: 15d09463 bne ra,t4,80002dc4 + +0000000080002c80 : + 80002c80: 00000213 li tp,0 + 80002c84: 0010009b addiw ra,zero,1 + 80002c88: 01f09093 slli ra,ra,0x1f + 80002c8c: 0070df13 srli t5,ra,0x7 + 80002c90: 000f0313 mv t1,t5 + 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c98: 00200293 li t0,2 + 80002c9c: fe5214e3 bne tp,t0,80002c84 + 80002ca0: 01000eb7 lui t4,0x1000 + 80002ca4: 01200193 li gp,18 + 80002ca8: 11d31e63 bne t1,t4,80002dc4 + +0000000080002cac : + 80002cac: 00000213 li tp,0 + 80002cb0: 0010009b addiw ra,zero,1 + 80002cb4: 01f09093 slli ra,ra,0x1f + 80002cb8: 00e0df13 srli t5,ra,0xe + 80002cbc: 00000013 nop + 80002cc0: 000f0313 mv t1,t5 + 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc8: 00200293 li t0,2 + 80002ccc: fe5212e3 bne tp,t0,80002cb0 + 80002cd0: 00020eb7 lui t4,0x20 + 80002cd4: 01300193 li gp,19 + 80002cd8: 0fd31663 bne t1,t4,80002dc4 + +0000000080002cdc : + 80002cdc: 00000213 li tp,0 + 80002ce0: 0010009b addiw ra,zero,1 + 80002ce4: 01f09093 slli ra,ra,0x1f + 80002ce8: 00108093 addi ra,ra,1 # 21212001 <_start-0x5ededfff> + 80002cec: 01f0df13 srli t5,ra,0x1f + 80002cf0: 00000013 nop + 80002cf4: 00000013 nop + 80002cf8: 000f0313 mv t1,t5 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fc521ee3 bne tp,t0,80002ce0 + 80002d08: 00100e93 li t4,1 + 80002d0c: 01400193 li gp,20 + 80002d10: 0bd31a63 bne t1,t4,80002dc4 + +0000000080002d14 : + 80002d14: 00000213 li tp,0 + 80002d18: 0010009b addiw ra,zero,1 + 80002d1c: 01f09093 slli ra,ra,0x1f + 80002d20: 0070df13 srli t5,ra,0x7 + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5216e3 bne tp,t0,80002d18 + 80002d30: 01000eb7 lui t4,0x1000 + 80002d34: 01500193 li gp,21 + 80002d38: 09df1663 bne t5,t4,80002dc4 + +0000000080002d3c : + 80002d3c: 00000213 li tp,0 + 80002d40: 0010009b addiw ra,zero,1 + 80002d44: 01f09093 slli ra,ra,0x1f + 80002d48: 00000013 nop + 80002d4c: 00e0df13 srli t5,ra,0xe + 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d54: 00200293 li t0,2 + 80002d58: fe5214e3 bne tp,t0,80002d40 + 80002d5c: 00020eb7 lui t4,0x20 + 80002d60: 01600193 li gp,22 + 80002d64: 07df1063 bne t5,t4,80002dc4 + +0000000080002d68 : + 80002d68: 00000213 li tp,0 + 80002d6c: 0010009b addiw ra,zero,1 + 80002d70: 01f09093 slli ra,ra,0x1f + 80002d74: 00108093 addi ra,ra,1 + 80002d78: 00000013 nop + 80002d7c: 00000013 nop + 80002d80: 01f0df13 srli t5,ra,0x1f + 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d88: 00200293 li t0,2 + 80002d8c: fe5210e3 bne tp,t0,80002d6c + 80002d90: 00100e93 li t4,1 + 80002d94: 01700193 li gp,23 + 80002d98: 03df1663 bne t5,t4,80002dc4 + +0000000080002d9c : + 80002d9c: 00405093 srli ra,zero,0x4 + 80002da0: 00000e93 li t4,0 + 80002da4: 01800193 li gp,24 + 80002da8: 01d09e63 bne ra,t4,80002dc4 + +0000000080002dac : + 80002dac: 02100093 li ra,33 + 80002db0: 00a0d013 srli zero,ra,0xa + 80002db4: 00000e93 li t4,0 + 80002db8: 01900193 li gp,25 + 80002dbc: 01d01463 bne zero,t4,80002dc4 + 80002dc0: 00301a63 bne zero,gp,80002dd4 + +0000000080002dc4 : + 80002dc4: 00119513 slli a0,gp,0x1 + 80002dc8: 00050063 beqz a0,80002dc8 + 80002dcc: 00156513 ori a0,a0,1 + 80002dd0: 00000073 ecall + +0000000080002dd4 : + 80002dd4: 00100513 li a0,1 + 80002dd8: 00000073 ecall + 80002ddc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srli.elf b/test/riscv/tests/rv64ui-v-srli.elf new file mode 100644 index 00000000..4a1f2d68 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-srli.elf differ diff --git a/test/riscv/tests/rv64ui-v-srliw.dump b/test/riscv/tests/rv64ui-v-srliw.dump new file mode 100644 index 00000000..919e1deb --- /dev/null +++ b/test/riscv/tests/rv64ui-v-srliw.dump @@ -0,0 +1,1054 @@ + +rv64ui-v-srliw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 93068693 addi a3,a3,-1744 # 80002d88 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 96460613 addi a2,a2,-1692 # 80002e18 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 92c60613 addi a2,a2,-1748 # 80002e30 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 87c68693 addi a3,a3,-1924 # 80002dd0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 89868693 addi a3,a3,-1896 # 80002f08 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 81860613 addi a2,a2,-2024 # 80002ee0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 74c68693 addi a3,a3,1868 # 80002f38 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 66c68693 addi a3,a3,1644 # 80002ea8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 5fc68693 addi a3,a3,1532 # 80002e70 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02200793 li a5,34 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 029637b7 lui a5,0x2963 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 15178793 addi a5,a5,337 # 2963151 <_start-0x7d69ceaf> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 0000df1b srliw t5,ra,0x0 + 80002ad0: 80000eb7 lui t4,0x80000 + 80002ad4: 00200193 li gp,2 + 80002ad8: 29df1863 bne t5,t4,80002d68 + +0000000080002adc : + 80002adc: 800000b7 lui ra,0x80000 + 80002ae0: 0010df1b srliw t5,ra,0x1 + 80002ae4: 40000eb7 lui t4,0x40000 + 80002ae8: 00300193 li gp,3 + 80002aec: 27df1e63 bne t5,t4,80002d68 + +0000000080002af0 : + 80002af0: 800000b7 lui ra,0x80000 + 80002af4: 0070df1b srliw t5,ra,0x7 + 80002af8: 01000eb7 lui t4,0x1000 + 80002afc: 00400193 li gp,4 + 80002b00: 27df1463 bne t5,t4,80002d68 + +0000000080002b04 : + 80002b04: 800000b7 lui ra,0x80000 + 80002b08: 00e0df1b srliw t5,ra,0xe + 80002b0c: 00020eb7 lui t4,0x20 + 80002b10: 00500193 li gp,5 + 80002b14: 25df1a63 bne t5,t4,80002d68 + +0000000080002b18 : + 80002b18: 800000b7 lui ra,0x80000 + 80002b1c: 0010809b addiw ra,ra,1 + 80002b20: 01f0df1b srliw t5,ra,0x1f + 80002b24: 00100e93 li t4,1 + 80002b28: 00600193 li gp,6 + 80002b2c: 23df1e63 bne t5,t4,80002d68 + +0000000080002b30 : + 80002b30: fff00093 li ra,-1 + 80002b34: 0000df1b srliw t5,ra,0x0 + 80002b38: fff00e93 li t4,-1 + 80002b3c: 00700193 li gp,7 + 80002b40: 23df1463 bne t5,t4,80002d68 + +0000000080002b44 : + 80002b44: fff00093 li ra,-1 + 80002b48: 0010df1b srliw t5,ra,0x1 + 80002b4c: 80000eb7 lui t4,0x80000 + 80002b50: fffe8e9b addiw t4,t4,-1 + 80002b54: 00800193 li gp,8 + 80002b58: 21df1863 bne t5,t4,80002d68 + +0000000080002b5c : + 80002b5c: fff00093 li ra,-1 + 80002b60: 0070df1b srliw t5,ra,0x7 + 80002b64: 02000eb7 lui t4,0x2000 + 80002b68: fffe8e9b addiw t4,t4,-1 + 80002b6c: 00900193 li gp,9 + 80002b70: 1fdf1c63 bne t5,t4,80002d68 + +0000000080002b74 : + 80002b74: fff00093 li ra,-1 + 80002b78: 00e0df1b srliw t5,ra,0xe + 80002b7c: 00040eb7 lui t4,0x40 + 80002b80: fffe8e9b addiw t4,t4,-1 + 80002b84: 00a00193 li gp,10 + 80002b88: 1fdf1063 bne t5,t4,80002d68 + +0000000080002b8c : + 80002b8c: fff00093 li ra,-1 + 80002b90: 01f0df1b srliw t5,ra,0x1f + 80002b94: 00100e93 li t4,1 + 80002b98: 00b00193 li gp,11 + 80002b9c: 1ddf1663 bne t5,t4,80002d68 + +0000000080002ba0 : + 80002ba0: 212120b7 lui ra,0x21212 + 80002ba4: 1210809b addiw ra,ra,289 + 80002ba8: 0000df1b srliw t5,ra,0x0 + 80002bac: 21212eb7 lui t4,0x21212 + 80002bb0: 121e8e9b addiw t4,t4,289 + 80002bb4: 00c00193 li gp,12 + 80002bb8: 1bdf1863 bne t5,t4,80002d68 + +0000000080002bbc : + 80002bbc: 212120b7 lui ra,0x21212 + 80002bc0: 1210809b addiw ra,ra,289 + 80002bc4: 0010df1b srliw t5,ra,0x1 + 80002bc8: 10909eb7 lui t4,0x10909 + 80002bcc: 090e8e9b addiw t4,t4,144 + 80002bd0: 00d00193 li gp,13 + 80002bd4: 19df1a63 bne t5,t4,80002d68 + +0000000080002bd8 : + 80002bd8: 212120b7 lui ra,0x21212 + 80002bdc: 1210809b addiw ra,ra,289 + 80002be0: 0070df1b srliw t5,ra,0x7 + 80002be4: 00424eb7 lui t4,0x424 + 80002be8: 242e8e9b addiw t4,t4,578 + 80002bec: 00e00193 li gp,14 + 80002bf0: 17df1c63 bne t5,t4,80002d68 + +0000000080002bf4 : + 80002bf4: 212120b7 lui ra,0x21212 + 80002bf8: 1210809b addiw ra,ra,289 + 80002bfc: 00e0df1b srliw t5,ra,0xe + 80002c00: 00008eb7 lui t4,0x8 + 80002c04: 484e8e9b addiw t4,t4,1156 + 80002c08: 00f00193 li gp,15 + 80002c0c: 15df1e63 bne t5,t4,80002d68 + +0000000080002c10 : + 80002c10: 212120b7 lui ra,0x21212 + 80002c14: 1210809b addiw ra,ra,289 + 80002c18: 01f0df1b srliw t5,ra,0x1f + 80002c1c: 00000e93 li t4,0 + 80002c20: 01000193 li gp,16 + 80002c24: 15df1263 bne t5,t4,80002d68 + +0000000080002c28 : + 80002c28: 800000b7 lui ra,0x80000 + 80002c2c: 0070d09b srliw ra,ra,0x7 + 80002c30: 01000eb7 lui t4,0x1000 + 80002c34: 01100193 li gp,17 + 80002c38: 13d09863 bne ra,t4,80002d68 + +0000000080002c3c : + 80002c3c: 00000213 li tp,0 + 80002c40: 800000b7 lui ra,0x80000 + 80002c44: 0070df1b srliw t5,ra,0x7 + 80002c48: 000f0313 mv t1,t5 + 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c50: 00200293 li t0,2 + 80002c54: fe5216e3 bne tp,t0,80002c40 + 80002c58: 01000eb7 lui t4,0x1000 + 80002c5c: 01200193 li gp,18 + 80002c60: 11d31463 bne t1,t4,80002d68 + +0000000080002c64 : + 80002c64: 00000213 li tp,0 + 80002c68: 800000b7 lui ra,0x80000 + 80002c6c: 00e0df1b srliw t5,ra,0xe + 80002c70: 00000013 nop + 80002c74: 000f0313 mv t1,t5 + 80002c78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c7c: 00200293 li t0,2 + 80002c80: fe5214e3 bne tp,t0,80002c68 + 80002c84: 00020eb7 lui t4,0x20 + 80002c88: 01300193 li gp,19 + 80002c8c: 0dd31e63 bne t1,t4,80002d68 + +0000000080002c90 : + 80002c90: 00000213 li tp,0 + 80002c94: 800000b7 lui ra,0x80000 + 80002c98: 0010809b addiw ra,ra,1 + 80002c9c: 01f0df1b srliw t5,ra,0x1f + 80002ca0: 00000013 nop + 80002ca4: 00000013 nop + 80002ca8: 000f0313 mv t1,t5 + 80002cac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cb0: 00200293 li t0,2 + 80002cb4: fe5210e3 bne tp,t0,80002c94 + 80002cb8: 00100e93 li t4,1 + 80002cbc: 01400193 li gp,20 + 80002cc0: 0bd31463 bne t1,t4,80002d68 + +0000000080002cc4 : + 80002cc4: 00000213 li tp,0 + 80002cc8: 800000b7 lui ra,0x80000 + 80002ccc: 0070df1b srliw t5,ra,0x7 + 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd4: 00200293 li t0,2 + 80002cd8: fe5218e3 bne tp,t0,80002cc8 + 80002cdc: 01000eb7 lui t4,0x1000 + 80002ce0: 01500193 li gp,21 + 80002ce4: 09df1263 bne t5,t4,80002d68 + +0000000080002ce8 : + 80002ce8: 00000213 li tp,0 + 80002cec: 800000b7 lui ra,0x80000 + 80002cf0: 00000013 nop + 80002cf4: 00e0df1b srliw t5,ra,0xe + 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cfc: 00200293 li t0,2 + 80002d00: fe5216e3 bne tp,t0,80002cec + 80002d04: 00020eb7 lui t4,0x20 + 80002d08: 01600193 li gp,22 + 80002d0c: 05df1e63 bne t5,t4,80002d68 + +0000000080002d10 : + 80002d10: 00000213 li tp,0 + 80002d14: 800000b7 lui ra,0x80000 + 80002d18: 0010809b addiw ra,ra,1 + 80002d1c: 00000013 nop + 80002d20: 00000013 nop + 80002d24: 01f0df1b srliw t5,ra,0x1f + 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d2c: 00200293 li t0,2 + 80002d30: fe5212e3 bne tp,t0,80002d14 + 80002d34: 00100e93 li t4,1 + 80002d38: 01700193 li gp,23 + 80002d3c: 03df1663 bne t5,t4,80002d68 + +0000000080002d40 : + 80002d40: 01f0509b srliw ra,zero,0x1f + 80002d44: 00000e93 li t4,0 + 80002d48: 01800193 li gp,24 + 80002d4c: 01d09e63 bne ra,t4,80002d68 + +0000000080002d50 : + 80002d50: 01f00093 li ra,31 + 80002d54: 01c0d01b srliw zero,ra,0x1c + 80002d58: 00000e93 li t4,0 + 80002d5c: 01900193 li gp,25 + 80002d60: 01d01463 bne zero,t4,80002d68 + 80002d64: 00301a63 bne zero,gp,80002d78 + +0000000080002d68 : + 80002d68: 00119513 slli a0,gp,0x1 + 80002d6c: 00050063 beqz a0,80002d6c + 80002d70: 00156513 ori a0,a0,1 + 80002d74: 00000073 ecall + +0000000080002d78 : + 80002d78: 00100513 li a0,1 + 80002d7c: 00000073 ecall + 80002d80: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srliw.elf b/test/riscv/tests/rv64ui-v-srliw.elf new file mode 100644 index 00000000..eacd8701 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-srliw.elf differ diff --git a/test/riscv/tests/rv64ui-v-srlw.dump b/test/riscv/tests/rv64ui-v-srlw.dump new file mode 100644 index 00000000..2cbf7502 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-srlw.dump @@ -0,0 +1,1275 @@ + +rv64ui-v-srlw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c1068693 addi a3,a3,-1008 # 80003068 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c4460613 addi a2,a2,-956 # 800030f8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c0c60613 addi a2,a2,-1012 # 80003110 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: b5c68693 addi a3,a3,-1188 # 800030b0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: b7868693 addi a3,a3,-1160 # 800031e8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: af860613 addi a2,a2,-1288 # 800031c0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a2c68693 addi a3,a3,-1492 # 80003218 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 94c68693 addi a3,a3,-1716 # 80003188 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 8dc68693 addi a3,a3,-1828 # 80003150 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 00800793 li a5,8 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 069877b7 lui a5,0x6987 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: d1f78793 addi a5,a5,-737 # 6986d1f <_start-0x796792e1> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 800000b7 lui ra,0x80000 + 80002acc: 00000113 li sp,0 + 80002ad0: 0020df3b srlw t5,ra,sp + 80002ad4: 80000eb7 lui t4,0x80000 + 80002ad8: 00200193 li gp,2 + 80002adc: 57df1863 bne t5,t4,8000304c + +0000000080002ae0 : + 80002ae0: 800000b7 lui ra,0x80000 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0020df3b srlw t5,ra,sp + 80002aec: 40000eb7 lui t4,0x40000 + 80002af0: 00300193 li gp,3 + 80002af4: 55df1c63 bne t5,t4,8000304c + +0000000080002af8 : + 80002af8: 800000b7 lui ra,0x80000 + 80002afc: 00700113 li sp,7 + 80002b00: 0020df3b srlw t5,ra,sp + 80002b04: 01000eb7 lui t4,0x1000 + 80002b08: 00400193 li gp,4 + 80002b0c: 55df1063 bne t5,t4,8000304c + +0000000080002b10 : + 80002b10: 800000b7 lui ra,0x80000 + 80002b14: 00e00113 li sp,14 + 80002b18: 0020df3b srlw t5,ra,sp + 80002b1c: 00020eb7 lui t4,0x20 + 80002b20: 00500193 li gp,5 + 80002b24: 53df1463 bne t5,t4,8000304c + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 0010809b addiw ra,ra,1 + 80002b30: 01f00113 li sp,31 + 80002b34: 0020df3b srlw t5,ra,sp + 80002b38: 00100e93 li t4,1 + 80002b3c: 00600193 li gp,6 + 80002b40: 51df1663 bne t5,t4,8000304c + +0000000080002b44 : + 80002b44: fff00093 li ra,-1 + 80002b48: 00000113 li sp,0 + 80002b4c: 0020df3b srlw t5,ra,sp + 80002b50: fff00e93 li t4,-1 + 80002b54: 00700193 li gp,7 + 80002b58: 4fdf1a63 bne t5,t4,8000304c + +0000000080002b5c : + 80002b5c: fff00093 li ra,-1 + 80002b60: 00100113 li sp,1 + 80002b64: 0020df3b srlw t5,ra,sp + 80002b68: 80000eb7 lui t4,0x80000 + 80002b6c: fffe8e9b addiw t4,t4,-1 + 80002b70: 00800193 li gp,8 + 80002b74: 4ddf1c63 bne t5,t4,8000304c + +0000000080002b78 : + 80002b78: fff00093 li ra,-1 + 80002b7c: 00700113 li sp,7 + 80002b80: 0020df3b srlw t5,ra,sp + 80002b84: 02000eb7 lui t4,0x2000 + 80002b88: fffe8e9b addiw t4,t4,-1 + 80002b8c: 00900193 li gp,9 + 80002b90: 4bdf1e63 bne t5,t4,8000304c + +0000000080002b94 : + 80002b94: fff00093 li ra,-1 + 80002b98: 00e00113 li sp,14 + 80002b9c: 0020df3b srlw t5,ra,sp + 80002ba0: 00040eb7 lui t4,0x40 + 80002ba4: fffe8e9b addiw t4,t4,-1 + 80002ba8: 00a00193 li gp,10 + 80002bac: 4bdf1063 bne t5,t4,8000304c + +0000000080002bb0 : + 80002bb0: fff00093 li ra,-1 + 80002bb4: 01f00113 li sp,31 + 80002bb8: 0020df3b srlw t5,ra,sp + 80002bbc: 00100e93 li t4,1 + 80002bc0: 00b00193 li gp,11 + 80002bc4: 49df1463 bne t5,t4,8000304c + +0000000080002bc8 : + 80002bc8: 212120b7 lui ra,0x21212 + 80002bcc: 1210809b addiw ra,ra,289 + 80002bd0: 00000113 li sp,0 + 80002bd4: 0020df3b srlw t5,ra,sp + 80002bd8: 21212eb7 lui t4,0x21212 + 80002bdc: 121e8e9b addiw t4,t4,289 + 80002be0: 00c00193 li gp,12 + 80002be4: 47df1463 bne t5,t4,8000304c + +0000000080002be8 : + 80002be8: 212120b7 lui ra,0x21212 + 80002bec: 1210809b addiw ra,ra,289 + 80002bf0: 00100113 li sp,1 + 80002bf4: 0020df3b srlw t5,ra,sp + 80002bf8: 10909eb7 lui t4,0x10909 + 80002bfc: 090e8e9b addiw t4,t4,144 + 80002c00: 00d00193 li gp,13 + 80002c04: 45df1463 bne t5,t4,8000304c + +0000000080002c08 : + 80002c08: 212120b7 lui ra,0x21212 + 80002c0c: 1210809b addiw ra,ra,289 + 80002c10: 00700113 li sp,7 + 80002c14: 0020df3b srlw t5,ra,sp + 80002c18: 00424eb7 lui t4,0x424 + 80002c1c: 242e8e9b addiw t4,t4,578 + 80002c20: 00e00193 li gp,14 + 80002c24: 43df1463 bne t5,t4,8000304c + +0000000080002c28 : + 80002c28: 212120b7 lui ra,0x21212 + 80002c2c: 1210809b addiw ra,ra,289 + 80002c30: 00e00113 li sp,14 + 80002c34: 0020df3b srlw t5,ra,sp + 80002c38: 00008eb7 lui t4,0x8 + 80002c3c: 484e8e9b addiw t4,t4,1156 + 80002c40: 00f00193 li gp,15 + 80002c44: 41df1463 bne t5,t4,8000304c + +0000000080002c48 : + 80002c48: 212120b7 lui ra,0x21212 + 80002c4c: 1210809b addiw ra,ra,289 + 80002c50: 01f00113 li sp,31 + 80002c54: 0020df3b srlw t5,ra,sp + 80002c58: 00000e93 li t4,0 + 80002c5c: 01000193 li gp,16 + 80002c60: 3fdf1663 bne t5,t4,8000304c + +0000000080002c64 : + 80002c64: 212120b7 lui ra,0x21212 + 80002c68: 1210809b addiw ra,ra,289 + 80002c6c: fe000113 li sp,-32 + 80002c70: 0020df3b srlw t5,ra,sp + 80002c74: 21212eb7 lui t4,0x21212 + 80002c78: 121e8e9b addiw t4,t4,289 + 80002c7c: 01100193 li gp,17 + 80002c80: 3ddf1663 bne t5,t4,8000304c + +0000000080002c84 : + 80002c84: 212120b7 lui ra,0x21212 + 80002c88: 1210809b addiw ra,ra,289 + 80002c8c: fe100113 li sp,-31 + 80002c90: 0020df3b srlw t5,ra,sp + 80002c94: 10909eb7 lui t4,0x10909 + 80002c98: 090e8e9b addiw t4,t4,144 + 80002c9c: 01200193 li gp,18 + 80002ca0: 3bdf1663 bne t5,t4,8000304c + +0000000080002ca4 : + 80002ca4: 212120b7 lui ra,0x21212 + 80002ca8: 1210809b addiw ra,ra,289 + 80002cac: fe700113 li sp,-25 + 80002cb0: 0020df3b srlw t5,ra,sp + 80002cb4: 00424eb7 lui t4,0x424 + 80002cb8: 242e8e9b addiw t4,t4,578 + 80002cbc: 01300193 li gp,19 + 80002cc0: 39df1663 bne t5,t4,8000304c + +0000000080002cc4 : + 80002cc4: 212120b7 lui ra,0x21212 + 80002cc8: 1210809b addiw ra,ra,289 + 80002ccc: fee00113 li sp,-18 + 80002cd0: 0020df3b srlw t5,ra,sp + 80002cd4: 00008eb7 lui t4,0x8 + 80002cd8: 484e8e9b addiw t4,t4,1156 + 80002cdc: 01400193 li gp,20 + 80002ce0: 37df1663 bne t5,t4,8000304c + +0000000080002ce4 : + 80002ce4: 212120b7 lui ra,0x21212 + 80002ce8: 1210809b addiw ra,ra,289 + 80002cec: fff00113 li sp,-1 + 80002cf0: 0020df3b srlw t5,ra,sp + 80002cf4: 00000e93 li t4,0 + 80002cf8: 01500193 li gp,21 + 80002cfc: 35df1863 bne t5,t4,8000304c + +0000000080002d00 : + 80002d00: 800000b7 lui ra,0x80000 + 80002d04: 00700113 li sp,7 + 80002d08: 0020d0bb srlw ra,ra,sp + 80002d0c: 01000eb7 lui t4,0x1000 + 80002d10: 01600193 li gp,22 + 80002d14: 33d09c63 bne ra,t4,8000304c + +0000000080002d18 : + 80002d18: 800000b7 lui ra,0x80000 + 80002d1c: 00e00113 li sp,14 + 80002d20: 0020d13b srlw sp,ra,sp + 80002d24: 00020eb7 lui t4,0x20 + 80002d28: 01700193 li gp,23 + 80002d2c: 33d11063 bne sp,t4,8000304c + +0000000080002d30 : + 80002d30: 00700093 li ra,7 + 80002d34: 0010d0bb srlw ra,ra,ra + 80002d38: 00000e93 li t4,0 + 80002d3c: 01800193 li gp,24 + 80002d40: 31d09663 bne ra,t4,8000304c + +0000000080002d44 : + 80002d44: 00000213 li tp,0 + 80002d48: 800000b7 lui ra,0x80000 + 80002d4c: 00700113 li sp,7 + 80002d50: 0020df3b srlw t5,ra,sp + 80002d54: 000f0313 mv t1,t5 + 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d5c: 00200293 li t0,2 + 80002d60: fe5214e3 bne tp,t0,80002d48 + 80002d64: 01000eb7 lui t4,0x1000 + 80002d68: 01900193 li gp,25 + 80002d6c: 2fd31063 bne t1,t4,8000304c + +0000000080002d70 : + 80002d70: 00000213 li tp,0 + 80002d74: 800000b7 lui ra,0x80000 + 80002d78: 00e00113 li sp,14 + 80002d7c: 0020df3b srlw t5,ra,sp + 80002d80: 00000013 nop + 80002d84: 000f0313 mv t1,t5 + 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d8c: 00200293 li t0,2 + 80002d90: fe5212e3 bne tp,t0,80002d74 + 80002d94: 00020eb7 lui t4,0x20 + 80002d98: 01a00193 li gp,26 + 80002d9c: 2bd31863 bne t1,t4,8000304c + +0000000080002da0 : + 80002da0: 00000213 li tp,0 + 80002da4: 800000b7 lui ra,0x80000 + 80002da8: 01f00113 li sp,31 + 80002dac: 0020df3b srlw t5,ra,sp + 80002db0: 00000013 nop + 80002db4: 00000013 nop + 80002db8: 000f0313 mv t1,t5 + 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dc0: 00200293 li t0,2 + 80002dc4: fe5210e3 bne tp,t0,80002da4 + 80002dc8: 00100e93 li t4,1 + 80002dcc: 01b00193 li gp,27 + 80002dd0: 27d31e63 bne t1,t4,8000304c + +0000000080002dd4 : + 80002dd4: 00000213 li tp,0 + 80002dd8: 800000b7 lui ra,0x80000 + 80002ddc: 00700113 li sp,7 + 80002de0: 0020df3b srlw t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fe5216e3 bne tp,t0,80002dd8 + 80002df0: 01000eb7 lui t4,0x1000 + 80002df4: 01c00193 li gp,28 + 80002df8: 25df1a63 bne t5,t4,8000304c + +0000000080002dfc : + 80002dfc: 00000213 li tp,0 + 80002e00: 800000b7 lui ra,0x80000 + 80002e04: 00e00113 li sp,14 + 80002e08: 00000013 nop + 80002e0c: 0020df3b srlw t5,ra,sp + 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e14: 00200293 li t0,2 + 80002e18: fe5214e3 bne tp,t0,80002e00 + 80002e1c: 00020eb7 lui t4,0x20 + 80002e20: 01d00193 li gp,29 + 80002e24: 23df1463 bne t5,t4,8000304c + +0000000080002e28 : + 80002e28: 00000213 li tp,0 + 80002e2c: 800000b7 lui ra,0x80000 + 80002e30: 01f00113 li sp,31 + 80002e34: 00000013 nop + 80002e38: 00000013 nop + 80002e3c: 0020df3b srlw t5,ra,sp + 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e44: 00200293 li t0,2 + 80002e48: fe5212e3 bne tp,t0,80002e2c + 80002e4c: 00100e93 li t4,1 + 80002e50: 01e00193 li gp,30 + 80002e54: 1fdf1c63 bne t5,t4,8000304c + +0000000080002e58 : + 80002e58: 00000213 li tp,0 + 80002e5c: 800000b7 lui ra,0x80000 + 80002e60: 00000013 nop + 80002e64: 00700113 li sp,7 + 80002e68: 0020df3b srlw t5,ra,sp + 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e70: 00200293 li t0,2 + 80002e74: fe5214e3 bne tp,t0,80002e5c + 80002e78: 01000eb7 lui t4,0x1000 + 80002e7c: 01f00193 li gp,31 + 80002e80: 1ddf1663 bne t5,t4,8000304c + +0000000080002e84 : + 80002e84: 00000213 li tp,0 + 80002e88: 800000b7 lui ra,0x80000 + 80002e8c: 00000013 nop + 80002e90: 00e00113 li sp,14 + 80002e94: 00000013 nop + 80002e98: 0020df3b srlw t5,ra,sp + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fe5212e3 bne tp,t0,80002e88 + 80002ea8: 00020eb7 lui t4,0x20 + 80002eac: 02000193 li gp,32 + 80002eb0: 19df1e63 bne t5,t4,8000304c + +0000000080002eb4 : + 80002eb4: 00000213 li tp,0 + 80002eb8: 800000b7 lui ra,0x80000 + 80002ebc: 00000013 nop + 80002ec0: 00000013 nop + 80002ec4: 01f00113 li sp,31 + 80002ec8: 0020df3b srlw t5,ra,sp + 80002ecc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ed0: 00200293 li t0,2 + 80002ed4: fe5212e3 bne tp,t0,80002eb8 + 80002ed8: 00100e93 li t4,1 + 80002edc: 02100193 li gp,33 + 80002ee0: 17df1663 bne t5,t4,8000304c + +0000000080002ee4 : + 80002ee4: 00000213 li tp,0 + 80002ee8: 00700113 li sp,7 + 80002eec: 800000b7 lui ra,0x80000 + 80002ef0: 0020df3b srlw t5,ra,sp + 80002ef4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ef8: 00200293 li t0,2 + 80002efc: fe5216e3 bne tp,t0,80002ee8 + 80002f00: 01000eb7 lui t4,0x1000 + 80002f04: 02200193 li gp,34 + 80002f08: 15df1263 bne t5,t4,8000304c + +0000000080002f0c : + 80002f0c: 00000213 li tp,0 + 80002f10: 00e00113 li sp,14 + 80002f14: 800000b7 lui ra,0x80000 + 80002f18: 00000013 nop + 80002f1c: 0020df3b srlw t5,ra,sp + 80002f20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f24: 00200293 li t0,2 + 80002f28: fe5214e3 bne tp,t0,80002f10 + 80002f2c: 00020eb7 lui t4,0x20 + 80002f30: 02300193 li gp,35 + 80002f34: 11df1c63 bne t5,t4,8000304c + +0000000080002f38 : + 80002f38: 00000213 li tp,0 + 80002f3c: 01f00113 li sp,31 + 80002f40: 800000b7 lui ra,0x80000 + 80002f44: 00000013 nop + 80002f48: 00000013 nop + 80002f4c: 0020df3b srlw t5,ra,sp + 80002f50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f54: 00200293 li t0,2 + 80002f58: fe5212e3 bne tp,t0,80002f3c + 80002f5c: 00100e93 li t4,1 + 80002f60: 02400193 li gp,36 + 80002f64: 0fdf1463 bne t5,t4,8000304c + +0000000080002f68 : + 80002f68: 00000213 li tp,0 + 80002f6c: 00700113 li sp,7 + 80002f70: 00000013 nop + 80002f74: 800000b7 lui ra,0x80000 + 80002f78: 0020df3b srlw t5,ra,sp + 80002f7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f80: 00200293 li t0,2 + 80002f84: fe5214e3 bne tp,t0,80002f6c + 80002f88: 01000eb7 lui t4,0x1000 + 80002f8c: 02500193 li gp,37 + 80002f90: 0bdf1e63 bne t5,t4,8000304c + +0000000080002f94 : + 80002f94: 00000213 li tp,0 + 80002f98: 00e00113 li sp,14 + 80002f9c: 00000013 nop + 80002fa0: 800000b7 lui ra,0x80000 + 80002fa4: 00000013 nop + 80002fa8: 0020df3b srlw t5,ra,sp + 80002fac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fb0: 00200293 li t0,2 + 80002fb4: fe5212e3 bne tp,t0,80002f98 + 80002fb8: 00020eb7 lui t4,0x20 + 80002fbc: 02600193 li gp,38 + 80002fc0: 09df1663 bne t5,t4,8000304c + +0000000080002fc4 : + 80002fc4: 00000213 li tp,0 + 80002fc8: 01f00113 li sp,31 + 80002fcc: 00000013 nop + 80002fd0: 00000013 nop + 80002fd4: 800000b7 lui ra,0x80000 + 80002fd8: 0020df3b srlw t5,ra,sp + 80002fdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fe0: 00200293 li t0,2 + 80002fe4: fe5212e3 bne tp,t0,80002fc8 + 80002fe8: 00100e93 li t4,1 + 80002fec: 02700193 li gp,39 + 80002ff0: 05df1e63 bne t5,t4,8000304c + +0000000080002ff4 : + 80002ff4: 00f00093 li ra,15 + 80002ff8: 0010513b srlw sp,zero,ra + 80002ffc: 00000e93 li t4,0 + 80003000: 02800193 li gp,40 + 80003004: 05d11463 bne sp,t4,8000304c + +0000000080003008 : + 80003008: 02000093 li ra,32 + 8000300c: 0000d13b srlw sp,ra,zero + 80003010: 02000e93 li t4,32 + 80003014: 02900193 li gp,41 + 80003018: 03d11a63 bne sp,t4,8000304c + +000000008000301c : + 8000301c: 000050bb srlw ra,zero,zero + 80003020: 00000e93 li t4,0 + 80003024: 02a00193 li gp,42 + 80003028: 03d09263 bne ra,t4,8000304c + +000000008000302c : + 8000302c: 40000093 li ra,1024 + 80003030: 00001137 lui sp,0x1 + 80003034: 8001011b addiw sp,sp,-2048 + 80003038: 0020d03b srlw zero,ra,sp + 8000303c: 00000e93 li t4,0 + 80003040: 02b00193 li gp,43 + 80003044: 01d01463 bne zero,t4,8000304c + 80003048: 00301a63 bne zero,gp,8000305c + +000000008000304c : + 8000304c: 00119513 slli a0,gp,0x1 + 80003050: 00050063 beqz a0,80003050 + 80003054: 00156513 ori a0,a0,1 + 80003058: 00000073 ecall + +000000008000305c : + 8000305c: 00100513 li a0,1 + 80003060: 00000073 ecall + 80003064: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srlw.elf b/test/riscv/tests/rv64ui-v-srlw.elf new file mode 100644 index 00000000..87f8e6d4 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-srlw.elf differ diff --git a/test/riscv/tests/rv64ui-v-sub.dump b/test/riscv/tests/rv64ui-v-sub.dump new file mode 100644 index 00000000..1e59e971 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sub.dump @@ -0,0 +1,1218 @@ + +rv64ui-v-sub: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b6068693 addi a3,a3,-1184 # 80002fb8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b9460613 addi a2,a2,-1132 # 80003048 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b5c60613 addi a2,a2,-1188 # 80003060 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: aac68693 addi a3,a3,-1364 # 80003000 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ac868693 addi a3,a3,-1336 # 80003138 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a4860613 addi a2,a2,-1464 # 80003110 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 97c68693 addi a3,a3,-1668 # 80003168 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 89c68693 addi a3,a3,-1892 # 800030d8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 82c68693 addi a3,a3,-2004 # 800030a0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02500793 li a5,37 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0913b7b7 lui a5,0x913b + 80002a70: 000805b7 lui a1,0x80 + 80002a74: a7278793 addi a5,a5,-1422 # 913aa72 <_start-0x76ec558e> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 40208f33 sub t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4bdf1e63 bne t5,t4,80002f98 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 40208f33 sub t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 4bdf1263 bne t5,t4,80002f98 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 40208f33 sub t5,ra,sp + 80002b04: ffc00e93 li t4,-4 + 80002b08: 00400193 li gp,4 + 80002b0c: 49df1663 bne t5,t4,80002f98 + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 40208f33 sub t5,ra,sp + 80002b1c: 00008eb7 lui t4,0x8 + 80002b20: 00500193 li gp,5 + 80002b24: 47df1a63 bne t5,t4,80002f98 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 40208f33 sub t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 45df1e63 bne t5,t4,80002f98 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 40208f33 sub t5,ra,sp + 80002b4c: 80008eb7 lui t4,0x80008 + 80002b50: 00700193 li gp,7 + 80002b54: 45df1263 bne t5,t4,80002f98 + +0000000080002b58 : + 80002b58: 00000093 li ra,0 + 80002b5c: 00008137 lui sp,0x8 + 80002b60: fff1011b addiw sp,sp,-1 + 80002b64: 40208f33 sub t5,ra,sp + 80002b68: ffff8eb7 lui t4,0xffff8 + 80002b6c: 001e8e9b addiw t4,t4,1 + 80002b70: 00800193 li gp,8 + 80002b74: 43df1263 bne t5,t4,80002f98 + +0000000080002b78 : + 80002b78: 800000b7 lui ra,0x80000 + 80002b7c: fff0809b addiw ra,ra,-1 + 80002b80: 00000113 li sp,0 + 80002b84: 40208f33 sub t5,ra,sp + 80002b88: 80000eb7 lui t4,0x80000 + 80002b8c: fffe8e9b addiw t4,t4,-1 + 80002b90: 00900193 li gp,9 + 80002b94: 41df1263 bne t5,t4,80002f98 + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: fff0809b addiw ra,ra,-1 + 80002ba0: 00008137 lui sp,0x8 + 80002ba4: fff1011b addiw sp,sp,-1 + 80002ba8: 40208f33 sub t5,ra,sp + 80002bac: 7fff8eb7 lui t4,0x7fff8 + 80002bb0: 00a00193 li gp,10 + 80002bb4: 3fdf1263 bne t5,t4,80002f98 + +0000000080002bb8 : + 80002bb8: 800000b7 lui ra,0x80000 + 80002bbc: 00008137 lui sp,0x8 + 80002bc0: fff1011b addiw sp,sp,-1 + 80002bc4: 40208f33 sub t5,ra,sp + 80002bc8: ffff0eb7 lui t4,0xffff0 + 80002bcc: fffe8e9b addiw t4,t4,-1 + 80002bd0: 00fe9e93 slli t4,t4,0xf + 80002bd4: 001e8e93 addi t4,t4,1 # ffffffffffff0001 <_end+0xffffffff7ffe7811> + 80002bd8: 00b00193 li gp,11 + 80002bdc: 3bdf1e63 bne t5,t4,80002f98 + +0000000080002be0 : + 80002be0: 800000b7 lui ra,0x80000 + 80002be4: fff0809b addiw ra,ra,-1 + 80002be8: ffff8137 lui sp,0xffff8 + 80002bec: 40208f33 sub t5,ra,sp + 80002bf0: 00010eb7 lui t4,0x10 + 80002bf4: 001e8e9b addiw t4,t4,1 + 80002bf8: 00fe9e93 slli t4,t4,0xf + 80002bfc: fffe8e93 addi t4,t4,-1 # ffff <_start-0x7fff0001> + 80002c00: 00c00193 li gp,12 + 80002c04: 39df1a63 bne t5,t4,80002f98 + +0000000080002c08 : + 80002c08: 00000093 li ra,0 + 80002c0c: fff00113 li sp,-1 + 80002c10: 40208f33 sub t5,ra,sp + 80002c14: 00100e93 li t4,1 + 80002c18: 00d00193 li gp,13 + 80002c1c: 37df1e63 bne t5,t4,80002f98 + +0000000080002c20 : + 80002c20: fff00093 li ra,-1 + 80002c24: 00100113 li sp,1 + 80002c28: 40208f33 sub t5,ra,sp + 80002c2c: ffe00e93 li t4,-2 + 80002c30: 00e00193 li gp,14 + 80002c34: 37df1263 bne t5,t4,80002f98 + +0000000080002c38 : + 80002c38: fff00093 li ra,-1 + 80002c3c: fff00113 li sp,-1 + 80002c40: 40208f33 sub t5,ra,sp + 80002c44: 00000e93 li t4,0 + 80002c48: 00f00193 li gp,15 + 80002c4c: 35df1663 bne t5,t4,80002f98 + +0000000080002c50 : + 80002c50: 00d00093 li ra,13 + 80002c54: 00b00113 li sp,11 + 80002c58: 402080b3 sub ra,ra,sp + 80002c5c: 00200e93 li t4,2 + 80002c60: 01000193 li gp,16 + 80002c64: 33d09a63 bne ra,t4,80002f98 + +0000000080002c68 : + 80002c68: 00e00093 li ra,14 + 80002c6c: 00b00113 li sp,11 + 80002c70: 40208133 sub sp,ra,sp + 80002c74: 00300e93 li t4,3 + 80002c78: 01100193 li gp,17 + 80002c7c: 31d11e63 bne sp,t4,80002f98 + +0000000080002c80 : + 80002c80: 00d00093 li ra,13 + 80002c84: 401080b3 sub ra,ra,ra + 80002c88: 00000e93 li t4,0 + 80002c8c: 01200193 li gp,18 + 80002c90: 31d09463 bne ra,t4,80002f98 + +0000000080002c94 : + 80002c94: 00000213 li tp,0 + 80002c98: 00d00093 li ra,13 + 80002c9c: 00b00113 li sp,11 + 80002ca0: 40208f33 sub t5,ra,sp + 80002ca4: 000f0313 mv t1,t5 + 80002ca8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cac: 00200293 li t0,2 + 80002cb0: fe5214e3 bne tp,t0,80002c98 + 80002cb4: 00200e93 li t4,2 + 80002cb8: 01300193 li gp,19 + 80002cbc: 2dd31e63 bne t1,t4,80002f98 + +0000000080002cc0 : + 80002cc0: 00000213 li tp,0 + 80002cc4: 00e00093 li ra,14 + 80002cc8: 00b00113 li sp,11 + 80002ccc: 40208f33 sub t5,ra,sp + 80002cd0: 00000013 nop + 80002cd4: 000f0313 mv t1,t5 + 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cdc: 00200293 li t0,2 + 80002ce0: fe5212e3 bne tp,t0,80002cc4 + 80002ce4: 00300e93 li t4,3 + 80002ce8: 01400193 li gp,20 + 80002cec: 2bd31663 bne t1,t4,80002f98 + +0000000080002cf0 : + 80002cf0: 00000213 li tp,0 + 80002cf4: 00f00093 li ra,15 + 80002cf8: 00b00113 li sp,11 + 80002cfc: 40208f33 sub t5,ra,sp + 80002d00: 00000013 nop + 80002d04: 00000013 nop + 80002d08: 000f0313 mv t1,t5 + 80002d0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d10: 00200293 li t0,2 + 80002d14: fe5210e3 bne tp,t0,80002cf4 + 80002d18: 00400e93 li t4,4 + 80002d1c: 01500193 li gp,21 + 80002d20: 27d31c63 bne t1,t4,80002f98 + +0000000080002d24 : + 80002d24: 00000213 li tp,0 + 80002d28: 00d00093 li ra,13 + 80002d2c: 00b00113 li sp,11 + 80002d30: 40208f33 sub t5,ra,sp + 80002d34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d38: 00200293 li t0,2 + 80002d3c: fe5216e3 bne tp,t0,80002d28 + 80002d40: 00200e93 li t4,2 + 80002d44: 01600193 li gp,22 + 80002d48: 25df1863 bne t5,t4,80002f98 + +0000000080002d4c : + 80002d4c: 00000213 li tp,0 + 80002d50: 00e00093 li ra,14 + 80002d54: 00b00113 li sp,11 + 80002d58: 00000013 nop + 80002d5c: 40208f33 sub t5,ra,sp + 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d64: 00200293 li t0,2 + 80002d68: fe5214e3 bne tp,t0,80002d50 + 80002d6c: 00300e93 li t4,3 + 80002d70: 01700193 li gp,23 + 80002d74: 23df1263 bne t5,t4,80002f98 + +0000000080002d78 : + 80002d78: 00000213 li tp,0 + 80002d7c: 00f00093 li ra,15 + 80002d80: 00b00113 li sp,11 + 80002d84: 00000013 nop + 80002d88: 00000013 nop + 80002d8c: 40208f33 sub t5,ra,sp + 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d94: 00200293 li t0,2 + 80002d98: fe5212e3 bne tp,t0,80002d7c + 80002d9c: 00400e93 li t4,4 + 80002da0: 01800193 li gp,24 + 80002da4: 1fdf1a63 bne t5,t4,80002f98 + +0000000080002da8 : + 80002da8: 00000213 li tp,0 + 80002dac: 00d00093 li ra,13 + 80002db0: 00000013 nop + 80002db4: 00b00113 li sp,11 + 80002db8: 40208f33 sub t5,ra,sp + 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dc0: 00200293 li t0,2 + 80002dc4: fe5214e3 bne tp,t0,80002dac + 80002dc8: 00200e93 li t4,2 + 80002dcc: 01900193 li gp,25 + 80002dd0: 1ddf1463 bne t5,t4,80002f98 + +0000000080002dd4 : + 80002dd4: 00000213 li tp,0 + 80002dd8: 00e00093 li ra,14 + 80002ddc: 00000013 nop + 80002de0: 00b00113 li sp,11 + 80002de4: 00000013 nop + 80002de8: 40208f33 sub t5,ra,sp + 80002dec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002df0: 00200293 li t0,2 + 80002df4: fe5212e3 bne tp,t0,80002dd8 + 80002df8: 00300e93 li t4,3 + 80002dfc: 01a00193 li gp,26 + 80002e00: 19df1c63 bne t5,t4,80002f98 + +0000000080002e04 : + 80002e04: 00000213 li tp,0 + 80002e08: 00f00093 li ra,15 + 80002e0c: 00000013 nop + 80002e10: 00000013 nop + 80002e14: 00b00113 li sp,11 + 80002e18: 40208f33 sub t5,ra,sp + 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e20: 00200293 li t0,2 + 80002e24: fe5212e3 bne tp,t0,80002e08 + 80002e28: 00400e93 li t4,4 + 80002e2c: 01b00193 li gp,27 + 80002e30: 17df1463 bne t5,t4,80002f98 + +0000000080002e34 : + 80002e34: 00000213 li tp,0 + 80002e38: 00b00113 li sp,11 + 80002e3c: 00d00093 li ra,13 + 80002e40: 40208f33 sub t5,ra,sp + 80002e44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e48: 00200293 li t0,2 + 80002e4c: fe5216e3 bne tp,t0,80002e38 + 80002e50: 00200e93 li t4,2 + 80002e54: 01c00193 li gp,28 + 80002e58: 15df1063 bne t5,t4,80002f98 + +0000000080002e5c : + 80002e5c: 00000213 li tp,0 + 80002e60: 00b00113 li sp,11 + 80002e64: 00e00093 li ra,14 + 80002e68: 00000013 nop + 80002e6c: 40208f33 sub t5,ra,sp + 80002e70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e74: 00200293 li t0,2 + 80002e78: fe5214e3 bne tp,t0,80002e60 + 80002e7c: 00300e93 li t4,3 + 80002e80: 01d00193 li gp,29 + 80002e84: 11df1a63 bne t5,t4,80002f98 + +0000000080002e88 : + 80002e88: 00000213 li tp,0 + 80002e8c: 00b00113 li sp,11 + 80002e90: 00f00093 li ra,15 + 80002e94: 00000013 nop + 80002e98: 00000013 nop + 80002e9c: 40208f33 sub t5,ra,sp + 80002ea0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea4: 00200293 li t0,2 + 80002ea8: fe5212e3 bne tp,t0,80002e8c + 80002eac: 00400e93 li t4,4 + 80002eb0: 01e00193 li gp,30 + 80002eb4: 0fdf1263 bne t5,t4,80002f98 + +0000000080002eb8 : + 80002eb8: 00000213 li tp,0 + 80002ebc: 00b00113 li sp,11 + 80002ec0: 00000013 nop + 80002ec4: 00d00093 li ra,13 + 80002ec8: 40208f33 sub t5,ra,sp + 80002ecc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ed0: 00200293 li t0,2 + 80002ed4: fe5214e3 bne tp,t0,80002ebc + 80002ed8: 00200e93 li t4,2 + 80002edc: 01f00193 li gp,31 + 80002ee0: 0bdf1c63 bne t5,t4,80002f98 + +0000000080002ee4 : + 80002ee4: 00000213 li tp,0 + 80002ee8: 00b00113 li sp,11 + 80002eec: 00000013 nop + 80002ef0: 00e00093 li ra,14 + 80002ef4: 00000013 nop + 80002ef8: 40208f33 sub t5,ra,sp + 80002efc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f00: 00200293 li t0,2 + 80002f04: fe5212e3 bne tp,t0,80002ee8 + 80002f08: 00300e93 li t4,3 + 80002f0c: 02000193 li gp,32 + 80002f10: 09df1463 bne t5,t4,80002f98 + +0000000080002f14 : + 80002f14: 00000213 li tp,0 + 80002f18: 00b00113 li sp,11 + 80002f1c: 00000013 nop + 80002f20: 00000013 nop + 80002f24: 00f00093 li ra,15 + 80002f28: 40208f33 sub t5,ra,sp + 80002f2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f30: 00200293 li t0,2 + 80002f34: fe5212e3 bne tp,t0,80002f18 + 80002f38: 00400e93 li t4,4 + 80002f3c: 02100193 li gp,33 + 80002f40: 05df1c63 bne t5,t4,80002f98 + +0000000080002f44 : + 80002f44: ff100093 li ra,-15 + 80002f48: 40100133 neg sp,ra + 80002f4c: 00f00e93 li t4,15 + 80002f50: 02200193 li gp,34 + 80002f54: 05d11263 bne sp,t4,80002f98 + +0000000080002f58 : + 80002f58: 02000093 li ra,32 + 80002f5c: 40008133 sub sp,ra,zero + 80002f60: 02000e93 li t4,32 + 80002f64: 02300193 li gp,35 + 80002f68: 03d11863 bne sp,t4,80002f98 + +0000000080002f6c : + 80002f6c: 400000b3 neg ra,zero + 80002f70: 00000e93 li t4,0 + 80002f74: 02400193 li gp,36 + 80002f78: 03d09063 bne ra,t4,80002f98 + +0000000080002f7c : + 80002f7c: 01000093 li ra,16 + 80002f80: 01e00113 li sp,30 + 80002f84: 40208033 sub zero,ra,sp + 80002f88: 00000e93 li t4,0 + 80002f8c: 02500193 li gp,37 + 80002f90: 01d01463 bne zero,t4,80002f98 + 80002f94: 00301a63 bne zero,gp,80002fa8 + +0000000080002f98 : + 80002f98: 00119513 slli a0,gp,0x1 + 80002f9c: 00050063 beqz a0,80002f9c + 80002fa0: 00156513 ori a0,a0,1 + 80002fa4: 00000073 ecall + +0000000080002fa8 : + 80002fa8: 00100513 li a0,1 + 80002fac: 00000073 ecall + 80002fb0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sub.elf b/test/riscv/tests/rv64ui-v-sub.elf new file mode 100644 index 00000000..25ce44fb Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sub.elf differ diff --git a/test/riscv/tests/rv64ui-v-subw.dump b/test/riscv/tests/rv64ui-v-subw.dump new file mode 100644 index 00000000..8832cb76 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-subw.dump @@ -0,0 +1,1214 @@ + +rv64ui-v-subw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b5068693 addi a3,a3,-1200 # 80002fa8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b8460613 addi a2,a2,-1148 # 80003038 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b4c60613 addi a2,a2,-1204 # 80003050 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: a9c68693 addi a3,a3,-1380 # 80002ff0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ab868693 addi a3,a3,-1352 # 80003128 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a3860613 addi a2,a2,-1480 # 80003100 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 96c68693 addi a3,a3,-1684 # 80003158 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 88c68693 addi a3,a3,-1908 # 800030c8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 81c68693 addi a3,a3,-2020 # 80003090 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02a00793 li a5,42 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0accb7b7 lui a5,0xaccb + 80002a70: 000805b7 lui a1,0x80 + 80002a74: c3078793 addi a5,a5,-976 # accac30 <_start-0x753353d0> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 40208f3b subw t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4bdf1663 bne t5,t4,80002f88 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 40208f3b subw t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 49df1a63 bne t5,t4,80002f88 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 40208f3b subw t5,ra,sp + 80002b04: ffc00e93 li t4,-4 + 80002b08: 00400193 li gp,4 + 80002b0c: 47df1e63 bne t5,t4,80002f88 + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 40208f3b subw t5,ra,sp + 80002b1c: 00008eb7 lui t4,0x8 + 80002b20: 00500193 li gp,5 + 80002b24: 47df1263 bne t5,t4,80002f88 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 40208f3b subw t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 45df1663 bne t5,t4,80002f88 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 40208f3b subw t5,ra,sp + 80002b4c: 80008eb7 lui t4,0x80008 + 80002b50: 00700193 li gp,7 + 80002b54: 43df1a63 bne t5,t4,80002f88 + +0000000080002b58 : + 80002b58: 00000093 li ra,0 + 80002b5c: 00008137 lui sp,0x8 + 80002b60: fff1011b addiw sp,sp,-1 + 80002b64: 40208f3b subw t5,ra,sp + 80002b68: ffff8eb7 lui t4,0xffff8 + 80002b6c: 001e8e9b addiw t4,t4,1 + 80002b70: 00800193 li gp,8 + 80002b74: 41df1a63 bne t5,t4,80002f88 + +0000000080002b78 : + 80002b78: 800000b7 lui ra,0x80000 + 80002b7c: fff0809b addiw ra,ra,-1 + 80002b80: 00000113 li sp,0 + 80002b84: 40208f3b subw t5,ra,sp + 80002b88: 80000eb7 lui t4,0x80000 + 80002b8c: fffe8e9b addiw t4,t4,-1 + 80002b90: 00900193 li gp,9 + 80002b94: 3fdf1a63 bne t5,t4,80002f88 + +0000000080002b98 : + 80002b98: 800000b7 lui ra,0x80000 + 80002b9c: fff0809b addiw ra,ra,-1 + 80002ba0: 00008137 lui sp,0x8 + 80002ba4: fff1011b addiw sp,sp,-1 + 80002ba8: 40208f3b subw t5,ra,sp + 80002bac: 7fff8eb7 lui t4,0x7fff8 + 80002bb0: 00a00193 li gp,10 + 80002bb4: 3ddf1a63 bne t5,t4,80002f88 + +0000000080002bb8 : + 80002bb8: 800000b7 lui ra,0x80000 + 80002bbc: 00008137 lui sp,0x8 + 80002bc0: fff1011b addiw sp,sp,-1 + 80002bc4: 40208f3b subw t5,ra,sp + 80002bc8: 7fff8eb7 lui t4,0x7fff8 + 80002bcc: 001e8e9b addiw t4,t4,1 + 80002bd0: 00b00193 li gp,11 + 80002bd4: 3bdf1a63 bne t5,t4,80002f88 + +0000000080002bd8 : + 80002bd8: 800000b7 lui ra,0x80000 + 80002bdc: fff0809b addiw ra,ra,-1 + 80002be0: ffff8137 lui sp,0xffff8 + 80002be4: 40208f3b subw t5,ra,sp + 80002be8: 80008eb7 lui t4,0x80008 + 80002bec: fffe8e9b addiw t4,t4,-1 + 80002bf0: 00c00193 li gp,12 + 80002bf4: 39df1a63 bne t5,t4,80002f88 + +0000000080002bf8 : + 80002bf8: 00000093 li ra,0 + 80002bfc: fff00113 li sp,-1 + 80002c00: 40208f3b subw t5,ra,sp + 80002c04: 00100e93 li t4,1 + 80002c08: 00d00193 li gp,13 + 80002c0c: 37df1e63 bne t5,t4,80002f88 + +0000000080002c10 : + 80002c10: fff00093 li ra,-1 + 80002c14: 00100113 li sp,1 + 80002c18: 40208f3b subw t5,ra,sp + 80002c1c: ffe00e93 li t4,-2 + 80002c20: 00e00193 li gp,14 + 80002c24: 37df1263 bne t5,t4,80002f88 + +0000000080002c28 : + 80002c28: fff00093 li ra,-1 + 80002c2c: fff00113 li sp,-1 + 80002c30: 40208f3b subw t5,ra,sp + 80002c34: 00000e93 li t4,0 + 80002c38: 00f00193 li gp,15 + 80002c3c: 35df1663 bne t5,t4,80002f88 + +0000000080002c40 : + 80002c40: 00d00093 li ra,13 + 80002c44: 00b00113 li sp,11 + 80002c48: 402080bb subw ra,ra,sp + 80002c4c: 00200e93 li t4,2 + 80002c50: 01000193 li gp,16 + 80002c54: 33d09a63 bne ra,t4,80002f88 + +0000000080002c58 : + 80002c58: 00e00093 li ra,14 + 80002c5c: 00b00113 li sp,11 + 80002c60: 4020813b subw sp,ra,sp + 80002c64: 00300e93 li t4,3 + 80002c68: 01100193 li gp,17 + 80002c6c: 31d11e63 bne sp,t4,80002f88 + +0000000080002c70 : + 80002c70: 00d00093 li ra,13 + 80002c74: 401080bb subw ra,ra,ra + 80002c78: 00000e93 li t4,0 + 80002c7c: 01200193 li gp,18 + 80002c80: 31d09463 bne ra,t4,80002f88 + +0000000080002c84 : + 80002c84: 00000213 li tp,0 + 80002c88: 00d00093 li ra,13 + 80002c8c: 00b00113 li sp,11 + 80002c90: 40208f3b subw t5,ra,sp + 80002c94: 000f0313 mv t1,t5 + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5214e3 bne tp,t0,80002c88 + 80002ca4: 00200e93 li t4,2 + 80002ca8: 01300193 li gp,19 + 80002cac: 2dd31e63 bne t1,t4,80002f88 + +0000000080002cb0 : + 80002cb0: 00000213 li tp,0 + 80002cb4: 00e00093 li ra,14 + 80002cb8: 00b00113 li sp,11 + 80002cbc: 40208f3b subw t5,ra,sp + 80002cc0: 00000013 nop + 80002cc4: 000f0313 mv t1,t5 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fe5212e3 bne tp,t0,80002cb4 + 80002cd4: 00300e93 li t4,3 + 80002cd8: 01400193 li gp,20 + 80002cdc: 2bd31663 bne t1,t4,80002f88 + +0000000080002ce0 : + 80002ce0: 00000213 li tp,0 + 80002ce4: 00f00093 li ra,15 + 80002ce8: 00b00113 li sp,11 + 80002cec: 40208f3b subw t5,ra,sp + 80002cf0: 00000013 nop + 80002cf4: 00000013 nop + 80002cf8: 000f0313 mv t1,t5 + 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d00: 00200293 li t0,2 + 80002d04: fe5210e3 bne tp,t0,80002ce4 + 80002d08: 00400e93 li t4,4 + 80002d0c: 01500193 li gp,21 + 80002d10: 27d31c63 bne t1,t4,80002f88 + +0000000080002d14 : + 80002d14: 00000213 li tp,0 + 80002d18: 00d00093 li ra,13 + 80002d1c: 00b00113 li sp,11 + 80002d20: 40208f3b subw t5,ra,sp + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5216e3 bne tp,t0,80002d18 + 80002d30: 00200e93 li t4,2 + 80002d34: 01600193 li gp,22 + 80002d38: 25df1863 bne t5,t4,80002f88 + +0000000080002d3c : + 80002d3c: 00000213 li tp,0 + 80002d40: 00e00093 li ra,14 + 80002d44: 00b00113 li sp,11 + 80002d48: 00000013 nop + 80002d4c: 40208f3b subw t5,ra,sp + 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d54: 00200293 li t0,2 + 80002d58: fe5214e3 bne tp,t0,80002d40 + 80002d5c: 00300e93 li t4,3 + 80002d60: 01700193 li gp,23 + 80002d64: 23df1263 bne t5,t4,80002f88 + +0000000080002d68 : + 80002d68: 00000213 li tp,0 + 80002d6c: 00f00093 li ra,15 + 80002d70: 00b00113 li sp,11 + 80002d74: 00000013 nop + 80002d78: 00000013 nop + 80002d7c: 40208f3b subw t5,ra,sp + 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d84: 00200293 li t0,2 + 80002d88: fe5212e3 bne tp,t0,80002d6c + 80002d8c: 00400e93 li t4,4 + 80002d90: 01800193 li gp,24 + 80002d94: 1fdf1a63 bne t5,t4,80002f88 + +0000000080002d98 : + 80002d98: 00000213 li tp,0 + 80002d9c: 00d00093 li ra,13 + 80002da0: 00000013 nop + 80002da4: 00b00113 li sp,11 + 80002da8: 40208f3b subw t5,ra,sp + 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db0: 00200293 li t0,2 + 80002db4: fe5214e3 bne tp,t0,80002d9c + 80002db8: 00200e93 li t4,2 + 80002dbc: 01900193 li gp,25 + 80002dc0: 1ddf1463 bne t5,t4,80002f88 + +0000000080002dc4 : + 80002dc4: 00000213 li tp,0 + 80002dc8: 00e00093 li ra,14 + 80002dcc: 00000013 nop + 80002dd0: 00b00113 li sp,11 + 80002dd4: 00000013 nop + 80002dd8: 40208f3b subw t5,ra,sp + 80002ddc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de0: 00200293 li t0,2 + 80002de4: fe5212e3 bne tp,t0,80002dc8 + 80002de8: 00300e93 li t4,3 + 80002dec: 01a00193 li gp,26 + 80002df0: 19df1c63 bne t5,t4,80002f88 + +0000000080002df4 : + 80002df4: 00000213 li tp,0 + 80002df8: 00f00093 li ra,15 + 80002dfc: 00000013 nop + 80002e00: 00000013 nop + 80002e04: 00b00113 li sp,11 + 80002e08: 40208f3b subw t5,ra,sp + 80002e0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e10: 00200293 li t0,2 + 80002e14: fe5212e3 bne tp,t0,80002df8 + 80002e18: 00400e93 li t4,4 + 80002e1c: 01b00193 li gp,27 + 80002e20: 17df1463 bne t5,t4,80002f88 + +0000000080002e24 : + 80002e24: 00000213 li tp,0 + 80002e28: 00b00113 li sp,11 + 80002e2c: 00d00093 li ra,13 + 80002e30: 40208f3b subw t5,ra,sp + 80002e34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e38: 00200293 li t0,2 + 80002e3c: fe5216e3 bne tp,t0,80002e28 + 80002e40: 00200e93 li t4,2 + 80002e44: 01c00193 li gp,28 + 80002e48: 15df1063 bne t5,t4,80002f88 + +0000000080002e4c : + 80002e4c: 00000213 li tp,0 + 80002e50: 00b00113 li sp,11 + 80002e54: 00e00093 li ra,14 + 80002e58: 00000013 nop + 80002e5c: 40208f3b subw t5,ra,sp + 80002e60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e64: 00200293 li t0,2 + 80002e68: fe5214e3 bne tp,t0,80002e50 + 80002e6c: 00300e93 li t4,3 + 80002e70: 01d00193 li gp,29 + 80002e74: 11df1a63 bne t5,t4,80002f88 + +0000000080002e78 : + 80002e78: 00000213 li tp,0 + 80002e7c: 00b00113 li sp,11 + 80002e80: 00f00093 li ra,15 + 80002e84: 00000013 nop + 80002e88: 00000013 nop + 80002e8c: 40208f3b subw t5,ra,sp + 80002e90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e94: 00200293 li t0,2 + 80002e98: fe5212e3 bne tp,t0,80002e7c + 80002e9c: 00400e93 li t4,4 + 80002ea0: 01e00193 li gp,30 + 80002ea4: 0fdf1263 bne t5,t4,80002f88 + +0000000080002ea8 : + 80002ea8: 00000213 li tp,0 + 80002eac: 00b00113 li sp,11 + 80002eb0: 00000013 nop + 80002eb4: 00d00093 li ra,13 + 80002eb8: 40208f3b subw t5,ra,sp + 80002ebc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec0: 00200293 li t0,2 + 80002ec4: fe5214e3 bne tp,t0,80002eac + 80002ec8: 00200e93 li t4,2 + 80002ecc: 01f00193 li gp,31 + 80002ed0: 0bdf1c63 bne t5,t4,80002f88 + +0000000080002ed4 : + 80002ed4: 00000213 li tp,0 + 80002ed8: 00b00113 li sp,11 + 80002edc: 00000013 nop + 80002ee0: 00e00093 li ra,14 + 80002ee4: 00000013 nop + 80002ee8: 40208f3b subw t5,ra,sp + 80002eec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ef0: 00200293 li t0,2 + 80002ef4: fe5212e3 bne tp,t0,80002ed8 + 80002ef8: 00300e93 li t4,3 + 80002efc: 02000193 li gp,32 + 80002f00: 09df1463 bne t5,t4,80002f88 + +0000000080002f04 : + 80002f04: 00000213 li tp,0 + 80002f08: 00b00113 li sp,11 + 80002f0c: 00000013 nop + 80002f10: 00000013 nop + 80002f14: 00f00093 li ra,15 + 80002f18: 40208f3b subw t5,ra,sp + 80002f1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f20: 00200293 li t0,2 + 80002f24: fe5212e3 bne tp,t0,80002f08 + 80002f28: 00400e93 li t4,4 + 80002f2c: 02100193 li gp,33 + 80002f30: 05df1c63 bne t5,t4,80002f88 + +0000000080002f34 : + 80002f34: ff100093 li ra,-15 + 80002f38: 4010013b negw sp,ra + 80002f3c: 00f00e93 li t4,15 + 80002f40: 02200193 li gp,34 + 80002f44: 05d11263 bne sp,t4,80002f88 + +0000000080002f48 : + 80002f48: 02000093 li ra,32 + 80002f4c: 4000813b subw sp,ra,zero + 80002f50: 02000e93 li t4,32 + 80002f54: 02300193 li gp,35 + 80002f58: 03d11863 bne sp,t4,80002f88 + +0000000080002f5c : + 80002f5c: 400000bb negw ra,zero + 80002f60: 00000e93 li t4,0 + 80002f64: 02400193 li gp,36 + 80002f68: 03d09063 bne ra,t4,80002f88 + +0000000080002f6c : + 80002f6c: 01000093 li ra,16 + 80002f70: 01e00113 li sp,30 + 80002f74: 4020803b subw zero,ra,sp + 80002f78: 00000e93 li t4,0 + 80002f7c: 02500193 li gp,37 + 80002f80: 01d01463 bne zero,t4,80002f88 + 80002f84: 00301a63 bne zero,gp,80002f98 + +0000000080002f88 : + 80002f88: 00119513 slli a0,gp,0x1 + 80002f8c: 00050063 beqz a0,80002f8c + 80002f90: 00156513 ori a0,a0,1 + 80002f94: 00000073 ecall + +0000000080002f98 : + 80002f98: 00100513 li a0,1 + 80002f9c: 00000073 ecall + 80002fa0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-subw.elf b/test/riscv/tests/rv64ui-v-subw.elf new file mode 100644 index 00000000..0c451dbc Binary files /dev/null and b/test/riscv/tests/rv64ui-v-subw.elf differ diff --git a/test/riscv/tests/rv64ui-v-sw.dump b/test/riscv/tests/rv64ui-v-sw.dump new file mode 100644 index 00000000..60671e20 --- /dev/null +++ b/test/riscv/tests/rv64ui-v-sw.dump @@ -0,0 +1,1203 @@ + +rv64ui-v-sw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 0000a117 auipc sp,0xa + 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00003617 auipc a2,0x3 + 80002318: cec60613 addi a2,a2,-788 # 80005000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00007797 auipc a5,0x7 + 80002334: 4b878793 addi a5,a5,1208 # 800097e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00007717 auipc a4,0x7 + 80002348: 49c70713 addi a4,a4,1180 # 800097e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00007897 auipc a7,0x7 + 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00007797 auipc a5,0x7 + 80002384: 07078793 addi a5,a5,112 # 800093f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00007797 auipc a5,0x7 + 80002448: 3807be23 sd zero,924(a5) # 800097e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b1068693 addi a3,a3,-1264 # 80002f68 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b4460613 addi a2,a2,-1212 # 80002ff8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b0c60613 addi a2,a2,-1268 # 80003010 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: a5c68693 addi a3,a3,-1444 # 80002fb0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: a7868693 addi a3,a3,-1416 # 800030e8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 9f860613 addi a2,a2,-1544 # 800030c0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00007d17 auipc s10,0x7 + 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 + 80002724: 00003b97 auipc s7,0x3 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00007a17 auipc s4,0x7 + 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00007717 auipc a4,0x7 + 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00007717 auipc a4,0x7 + 800027d4: 00f73823 sd a5,16(a4) # 800097e0 + 800027d8: 00007717 auipc a4,0x7 + 800027dc: 00f73823 sd a5,16(a4) # 800097e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 92c68693 addi a3,a3,-1748 # 80003118 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 84c68693 addi a3,a3,-1972 # 80003088 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 7dc68693 addi a3,a3,2012 # 80003050 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00003697 auipc a3,0x3 + 800028e0: 72468693 addi a3,a3,1828 # 80006000 + 800028e4: 00004717 auipc a4,0x4 + 800028e8: 71c70713 addi a4,a4,1820 # 80007000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00005797 auipc a5,0x5 + 800028f8: 70c78793 addi a5,a5,1804 # 80008000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00002897 auipc a7,0x2 + 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00003697 auipc a3,0x3 + 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00002617 auipc a2,0x2 + 80002938: 6cc60613 addi a2,a2,1740 # 80005000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00005697 auipc a3,0x5 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 + 8000294c: 00003717 auipc a4,0x3 + 80002950: 6af73a23 sd a5,1716(a4) # 80006000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00006697 auipc a3,0x6 + 800029c0: 64468693 addi a3,a3,1604 # 80009000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00007617 auipc a2,0x7 + 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 + 800029d4: 00007797 auipc a5,0x7 + 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 + 800029dc: 00007317 auipc t1,0x7 + 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 + 800029e4: 02900793 li a5,41 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00007797 auipc a5,0x7 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 06fb17b7 lui a5,0x6fb1 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: a0a78793 addi a5,a5,-1526 # 6fb0a0a <_start-0x7904f5f6> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00001097 auipc ra,0x1 + 80002acc: 53808093 addi ra,ra,1336 # 80004000 + 80002ad0: 00aa0137 lui sp,0xaa0 + 80002ad4: 0aa1011b addiw sp,sp,170 + 80002ad8: 0020a023 sw sp,0(ra) + 80002adc: 0000af03 lw t5,0(ra) + 80002ae0: 00aa0eb7 lui t4,0xaa0 + 80002ae4: 0aae8e9b addiw t4,t4,170 + 80002ae8: 00200193 li gp,2 + 80002aec: 47df1063 bne t5,t4,80002f4c + +0000000080002af0 : + 80002af0: 00001097 auipc ra,0x1 + 80002af4: 51008093 addi ra,ra,1296 # 80004000 + 80002af8: aa00b137 lui sp,0xaa00b + 80002afc: a001011b addiw sp,sp,-1536 + 80002b00: 0020a223 sw sp,4(ra) + 80002b04: 0040af03 lw t5,4(ra) + 80002b08: aa00beb7 lui t4,0xaa00b + 80002b0c: a00e8e9b addiw t4,t4,-1536 + 80002b10: 00300193 li gp,3 + 80002b14: 43df1c63 bne t5,t4,80002f4c + +0000000080002b18 : + 80002b18: 00001097 auipc ra,0x1 + 80002b1c: 4e808093 addi ra,ra,1256 # 80004000 + 80002b20: 0aa01137 lui sp,0xaa01 + 80002b24: aa01011b addiw sp,sp,-1376 + 80002b28: 0020a423 sw sp,8(ra) + 80002b2c: 0080af03 lw t5,8(ra) + 80002b30: 0aa01eb7 lui t4,0xaa01 + 80002b34: aa0e8e9b addiw t4,t4,-1376 + 80002b38: 00400193 li gp,4 + 80002b3c: 41df1863 bne t5,t4,80002f4c + +0000000080002b40 : + 80002b40: 00001097 auipc ra,0x1 + 80002b44: 4c008093 addi ra,ra,1216 # 80004000 + 80002b48: a00aa137 lui sp,0xa00aa + 80002b4c: 00a1011b addiw sp,sp,10 + 80002b50: 0020a623 sw sp,12(ra) + 80002b54: 00c0af03 lw t5,12(ra) + 80002b58: a00aaeb7 lui t4,0xa00aa + 80002b5c: 00ae8e9b addiw t4,t4,10 + 80002b60: 00500193 li gp,5 + 80002b64: 3fdf1463 bne t5,t4,80002f4c + +0000000080002b68 : + 80002b68: 00001097 auipc ra,0x1 + 80002b6c: 4b408093 addi ra,ra,1204 # 8000401c + 80002b70: 00aa0137 lui sp,0xaa0 + 80002b74: 0aa1011b addiw sp,sp,170 + 80002b78: fe20aa23 sw sp,-12(ra) + 80002b7c: ff40af03 lw t5,-12(ra) + 80002b80: 00aa0eb7 lui t4,0xaa0 + 80002b84: 0aae8e9b addiw t4,t4,170 + 80002b88: 00600193 li gp,6 + 80002b8c: 3ddf1063 bne t5,t4,80002f4c + +0000000080002b90 : + 80002b90: 00001097 auipc ra,0x1 + 80002b94: 48c08093 addi ra,ra,1164 # 8000401c + 80002b98: aa00b137 lui sp,0xaa00b + 80002b9c: a001011b addiw sp,sp,-1536 + 80002ba0: fe20ac23 sw sp,-8(ra) + 80002ba4: ff80af03 lw t5,-8(ra) + 80002ba8: aa00beb7 lui t4,0xaa00b + 80002bac: a00e8e9b addiw t4,t4,-1536 + 80002bb0: 00700193 li gp,7 + 80002bb4: 39df1c63 bne t5,t4,80002f4c + +0000000080002bb8 : + 80002bb8: 00001097 auipc ra,0x1 + 80002bbc: 46408093 addi ra,ra,1124 # 8000401c + 80002bc0: 0aa01137 lui sp,0xaa01 + 80002bc4: aa01011b addiw sp,sp,-1376 + 80002bc8: fe20ae23 sw sp,-4(ra) + 80002bcc: ffc0af03 lw t5,-4(ra) + 80002bd0: 0aa01eb7 lui t4,0xaa01 + 80002bd4: aa0e8e9b addiw t4,t4,-1376 + 80002bd8: 00800193 li gp,8 + 80002bdc: 37df1863 bne t5,t4,80002f4c + +0000000080002be0 : + 80002be0: 00001097 auipc ra,0x1 + 80002be4: 43c08093 addi ra,ra,1084 # 8000401c + 80002be8: a00aa137 lui sp,0xa00aa + 80002bec: 00a1011b addiw sp,sp,10 + 80002bf0: 0020a023 sw sp,0(ra) + 80002bf4: 0000af03 lw t5,0(ra) + 80002bf8: a00aaeb7 lui t4,0xa00aa + 80002bfc: 00ae8e9b addiw t4,t4,10 + 80002c00: 00900193 li gp,9 + 80002c04: 35df1463 bne t5,t4,80002f4c + +0000000080002c08 : + 80002c08: 00001097 auipc ra,0x1 + 80002c0c: 41808093 addi ra,ra,1048 # 80004020 + 80002c10: 12345137 lui sp,0x12345 + 80002c14: 6781011b addiw sp,sp,1656 + 80002c18: fe008213 addi tp,ra,-32 + 80002c1c: 02222023 sw sp,32(tp) # 20 <_start-0x7fffffe0> + 80002c20: 0000a283 lw t0,0(ra) + 80002c24: 12345eb7 lui t4,0x12345 + 80002c28: 678e8e9b addiw t4,t4,1656 + 80002c2c: 00a00193 li gp,10 + 80002c30: 31d29e63 bne t0,t4,80002f4c + +0000000080002c34 : + 80002c34: 00001097 auipc ra,0x1 + 80002c38: 3ec08093 addi ra,ra,1004 # 80004020 + 80002c3c: 58213137 lui sp,0x58213 + 80002c40: 0981011b addiw sp,sp,152 + 80002c44: ffd08093 addi ra,ra,-3 + 80002c48: 0020a3a3 sw sp,7(ra) + 80002c4c: 00001217 auipc tp,0x1 + 80002c50: 3d820213 addi tp,tp,984 # 80004024 + 80002c54: 00022283 lw t0,0(tp) # 0 <_start-0x80000000> + 80002c58: 58213eb7 lui t4,0x58213 + 80002c5c: 098e8e9b addiw t4,t4,152 + 80002c60: 00b00193 li gp,11 + 80002c64: 2fd29463 bne t0,t4,80002f4c + +0000000080002c68 : + 80002c68: 00c00193 li gp,12 + 80002c6c: 00000213 li tp,0 + 80002c70: aabbd0b7 lui ra,0xaabbd + 80002c74: cdd0809b addiw ra,ra,-803 + 80002c78: 00001117 auipc sp,0x1 + 80002c7c: 38810113 addi sp,sp,904 # 80004000 + 80002c80: 00112023 sw ra,0(sp) + 80002c84: 00012f03 lw t5,0(sp) + 80002c88: aabbdeb7 lui t4,0xaabbd + 80002c8c: cdde8e9b addiw t4,t4,-803 + 80002c90: 2bdf1e63 bne t5,t4,80002f4c + 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c98: 00200293 li t0,2 + 80002c9c: fc521ae3 bne tp,t0,80002c70 + +0000000080002ca0 : + 80002ca0: 00d00193 li gp,13 + 80002ca4: 00000213 li tp,0 + 80002ca8: daabc0b7 lui ra,0xdaabc + 80002cac: ccd0809b addiw ra,ra,-819 + 80002cb0: 00001117 auipc sp,0x1 + 80002cb4: 35010113 addi sp,sp,848 # 80004000 + 80002cb8: 00000013 nop + 80002cbc: 00112223 sw ra,4(sp) + 80002cc0: 00412f03 lw t5,4(sp) + 80002cc4: daabceb7 lui t4,0xdaabc + 80002cc8: ccde8e9b addiw t4,t4,-819 + 80002ccc: 29df1063 bne t5,t4,80002f4c + 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd4: 00200293 li t0,2 + 80002cd8: fc5218e3 bne tp,t0,80002ca8 + +0000000080002cdc : + 80002cdc: 00e00193 li gp,14 + 80002ce0: 00000213 li tp,0 + 80002ce4: ddaac0b7 lui ra,0xddaac + 80002ce8: bcc0809b addiw ra,ra,-1076 + 80002cec: 00001117 auipc sp,0x1 + 80002cf0: 31410113 addi sp,sp,788 # 80004000 + 80002cf4: 00000013 nop + 80002cf8: 00000013 nop + 80002cfc: 00112423 sw ra,8(sp) + 80002d00: 00812f03 lw t5,8(sp) + 80002d04: ddaaceb7 lui t4,0xddaac + 80002d08: bcce8e9b addiw t4,t4,-1076 + 80002d0c: 25df1063 bne t5,t4,80002f4c + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fc5216e3 bne tp,t0,80002ce4 + +0000000080002d1c : + 80002d1c: 00f00193 li gp,15 + 80002d20: 00000213 li tp,0 + 80002d24: cddab0b7 lui ra,0xcddab + 80002d28: bbc0809b addiw ra,ra,-1092 + 80002d2c: 00000013 nop + 80002d30: 00001117 auipc sp,0x1 + 80002d34: 2d010113 addi sp,sp,720 # 80004000 + 80002d38: 00112623 sw ra,12(sp) + 80002d3c: 00c12f03 lw t5,12(sp) + 80002d40: cddabeb7 lui t4,0xcddab + 80002d44: bbce8e9b addiw t4,t4,-1092 + 80002d48: 21df1263 bne t5,t4,80002f4c + 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d50: 00200293 li t0,2 + 80002d54: fc5218e3 bne tp,t0,80002d24 + +0000000080002d58 : + 80002d58: 01000193 li gp,16 + 80002d5c: 00000213 li tp,0 + 80002d60: ccddb0b7 lui ra,0xccddb + 80002d64: abb0809b addiw ra,ra,-1349 + 80002d68: 00000013 nop + 80002d6c: 00001117 auipc sp,0x1 + 80002d70: 29410113 addi sp,sp,660 # 80004000 + 80002d74: 00000013 nop + 80002d78: 00112823 sw ra,16(sp) + 80002d7c: 01012f03 lw t5,16(sp) + 80002d80: ccddbeb7 lui t4,0xccddb + 80002d84: abbe8e9b addiw t4,t4,-1349 + 80002d88: 1ddf1263 bne t5,t4,80002f4c + 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d90: 00200293 li t0,2 + 80002d94: fc5216e3 bne tp,t0,80002d60 + +0000000080002d98 : + 80002d98: 01100193 li gp,17 + 80002d9c: 00000213 li tp,0 + 80002da0: bccde0b7 lui ra,0xbccde + 80002da4: aab0809b addiw ra,ra,-1365 + 80002da8: 00000013 nop + 80002dac: 00000013 nop + 80002db0: 00001117 auipc sp,0x1 + 80002db4: 25010113 addi sp,sp,592 # 80004000 + 80002db8: 00112a23 sw ra,20(sp) + 80002dbc: 01412f03 lw t5,20(sp) + 80002dc0: bccdeeb7 lui t4,0xbccde + 80002dc4: aabe8e9b addiw t4,t4,-1365 + 80002dc8: 19df1263 bne t5,t4,80002f4c + 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd0: 00200293 li t0,2 + 80002dd4: fc5216e3 bne tp,t0,80002da0 + +0000000080002dd8 : + 80002dd8: 01200193 li gp,18 + 80002ddc: 00000213 li tp,0 + 80002de0: 00001117 auipc sp,0x1 + 80002de4: 22010113 addi sp,sp,544 # 80004000 + 80002de8: 001120b7 lui ra,0x112 + 80002dec: 2330809b addiw ra,ra,563 + 80002df0: 00112023 sw ra,0(sp) + 80002df4: 00012f03 lw t5,0(sp) + 80002df8: 00112eb7 lui t4,0x112 + 80002dfc: 233e8e9b addiw t4,t4,563 + 80002e00: 15df1663 bne t5,t4,80002f4c + 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e08: 00200293 li t0,2 + 80002e0c: fc521ae3 bne tp,t0,80002de0 + +0000000080002e10 : + 80002e10: 01300193 li gp,19 + 80002e14: 00000213 li tp,0 + 80002e18: 00001117 auipc sp,0x1 + 80002e1c: 1e810113 addi sp,sp,488 # 80004000 + 80002e20: 300110b7 lui ra,0x30011 + 80002e24: 2230809b addiw ra,ra,547 + 80002e28: 00000013 nop + 80002e2c: 00112223 sw ra,4(sp) + 80002e30: 00412f03 lw t5,4(sp) + 80002e34: 30011eb7 lui t4,0x30011 + 80002e38: 223e8e9b addiw t4,t4,547 + 80002e3c: 11df1863 bne t5,t4,80002f4c + 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e44: 00200293 li t0,2 + 80002e48: fc5218e3 bne tp,t0,80002e18 + +0000000080002e4c : + 80002e4c: 01400193 li gp,20 + 80002e50: 00000213 li tp,0 + 80002e54: 00001117 auipc sp,0x1 + 80002e58: 1ac10113 addi sp,sp,428 # 80004000 + 80002e5c: 330010b7 lui ra,0x33001 + 80002e60: 1220809b addiw ra,ra,290 + 80002e64: 00000013 nop + 80002e68: 00000013 nop + 80002e6c: 00112423 sw ra,8(sp) + 80002e70: 00812f03 lw t5,8(sp) + 80002e74: 33001eb7 lui t4,0x33001 + 80002e78: 122e8e9b addiw t4,t4,290 + 80002e7c: 0ddf1863 bne t5,t4,80002f4c + 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e84: 00200293 li t0,2 + 80002e88: fc5216e3 bne tp,t0,80002e54 + +0000000080002e8c : + 80002e8c: 01500193 li gp,21 + 80002e90: 00000213 li tp,0 + 80002e94: 00001117 auipc sp,0x1 + 80002e98: 16c10113 addi sp,sp,364 # 80004000 + 80002e9c: 00000013 nop + 80002ea0: 233000b7 lui ra,0x23300 + 80002ea4: 1120809b addiw ra,ra,274 + 80002ea8: 00112623 sw ra,12(sp) + 80002eac: 00c12f03 lw t5,12(sp) + 80002eb0: 23300eb7 lui t4,0x23300 + 80002eb4: 112e8e9b addiw t4,t4,274 + 80002eb8: 09df1a63 bne t5,t4,80002f4c + 80002ebc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec0: 00200293 li t0,2 + 80002ec4: fc5218e3 bne tp,t0,80002e94 + +0000000080002ec8 : + 80002ec8: 01600193 li gp,22 + 80002ecc: 00000213 li tp,0 + 80002ed0: 00001117 auipc sp,0x1 + 80002ed4: 13010113 addi sp,sp,304 # 80004000 + 80002ed8: 00000013 nop + 80002edc: 223300b7 lui ra,0x22330 + 80002ee0: 0110809b addiw ra,ra,17 + 80002ee4: 00000013 nop + 80002ee8: 00112823 sw ra,16(sp) + 80002eec: 01012f03 lw t5,16(sp) + 80002ef0: 22330eb7 lui t4,0x22330 + 80002ef4: 011e8e9b addiw t4,t4,17 + 80002ef8: 05df1a63 bne t5,t4,80002f4c + 80002efc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f00: 00200293 li t0,2 + 80002f04: fc5216e3 bne tp,t0,80002ed0 + +0000000080002f08 : + 80002f08: 01700193 li gp,23 + 80002f0c: 00000213 li tp,0 + 80002f10: 00001117 auipc sp,0x1 + 80002f14: 0f010113 addi sp,sp,240 # 80004000 + 80002f18: 00000013 nop + 80002f1c: 00000013 nop + 80002f20: 122330b7 lui ra,0x12233 + 80002f24: 0010809b addiw ra,ra,1 + 80002f28: 00112a23 sw ra,20(sp) + 80002f2c: 01412f03 lw t5,20(sp) + 80002f30: 12233eb7 lui t4,0x12233 + 80002f34: 001e8e9b addiw t4,t4,1 + 80002f38: 01df1a63 bne t5,t4,80002f4c + 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f40: 00200293 li t0,2 + 80002f44: fc5216e3 bne tp,t0,80002f10 + 80002f48: 00301a63 bne zero,gp,80002f5c + +0000000080002f4c : + 80002f4c: 00119513 slli a0,gp,0x1 + 80002f50: 00050063 beqz a0,80002f50 + 80002f54: 00156513 ori a0,a0,1 + 80002f58: 00000073 ecall + +0000000080002f5c : + 80002f5c: 00100513 li a0,1 + 80002f60: 00000073 ecall + 80002f64: c0001073 unimp + +Disassembly of section .data: + +0000000080004000 : + 80004000: deadbeef jal t4,7ffdf5ea <_start-0x20a16> + +0000000080004004 : + 80004004: deadbeef jal t4,7ffdf5ee <_start-0x20a12> + +0000000080004008 : + 80004008: deadbeef jal t4,7ffdf5f2 <_start-0x20a0e> + +000000008000400c : + 8000400c: deadbeef jal t4,7ffdf5f6 <_start-0x20a0a> + +0000000080004010 : + 80004010: deadbeef jal t4,7ffdf5fa <_start-0x20a06> + +0000000080004014 : + 80004014: deadbeef jal t4,7ffdf5fe <_start-0x20a02> + +0000000080004018 : + 80004018: deadbeef jal t4,7ffdf602 <_start-0x209fe> + +000000008000401c : + 8000401c: deadbeef jal t4,7ffdf606 <_start-0x209fa> + +0000000080004020 : + 80004020: deadbeef jal t4,7ffdf60a <_start-0x209f6> + +0000000080004024 : + 80004024: deadbeef jal t4,7ffdf60e <_start-0x209f2> diff --git a/test/riscv/tests/rv64ui-v-sw.elf b/test/riscv/tests/rv64ui-v-sw.elf new file mode 100644 index 00000000..d52322bf Binary files /dev/null and b/test/riscv/tests/rv64ui-v-sw.elf differ diff --git a/test/riscv/tests/rv64ui-v-xor.dump b/test/riscv/tests/rv64ui-v-xor.dump new file mode 100644 index 00000000..8b95600c --- /dev/null +++ b/test/riscv/tests/rv64ui-v-xor.dump @@ -0,0 +1,1260 @@ + +rv64ui-v-xor: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: c5868693 addi a3,a3,-936 # 800030b0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: c8c60613 addi a2,a2,-884 # 80003140 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: c5460613 addi a2,a2,-940 # 80003158 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: ba468693 addi a3,a3,-1116 # 800030f8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: bc068693 addi a3,a3,-1088 # 80003230 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: b4060613 addi a2,a2,-1216 # 80003208 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: a7468693 addi a3,a3,-1420 # 80003260 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 99468693 addi a3,a3,-1644 # 800031d0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 92468693 addi a3,a3,-1756 # 80003198 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02900793 li a5,41 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0c2b87b7 lui a5,0xc2b8 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 9f278793 addi a5,a5,-1550 # c2b79f2 <_start-0x73d4860e> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000100b7 lui ra,0x10 + 80002acc: f010809b addiw ra,ra,-255 + 80002ad0: 01009093 slli ra,ra,0x10 + 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002ad8: 0f0f1137 lui sp,0xf0f1 + 80002adc: f0f1011b addiw sp,sp,-241 + 80002ae0: 0020cf33 xor t5,ra,sp + 80002ae4: 000f0eb7 lui t4,0xf0 + 80002ae8: 0ffe8e9b addiw t4,t4,255 + 80002aec: 00ce9e93 slli t4,t4,0xc + 80002af0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002af4: 00200193 li gp,2 + 80002af8: 59df1c63 bne t5,t4,80003090 + +0000000080002afc : + 80002afc: 0ff010b7 lui ra,0xff01 + 80002b00: ff00809b addiw ra,ra,-16 + 80002b04: 000f1137 lui sp,0xf1 + 80002b08: f0f1011b addiw sp,sp,-241 + 80002b0c: 00c11113 slli sp,sp,0xc + 80002b10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b14: 0020cf33 xor t5,ra,sp + 80002b18: 00010eb7 lui t4,0x10 + 80002b1c: f01e8e9b addiw t4,t4,-255 + 80002b20: 010e9e93 slli t4,t4,0x10 + 80002b24: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002b28: 00300193 li gp,3 + 80002b2c: 57df1263 bne t5,t4,80003090 + +0000000080002b30 : + 80002b30: 00ff00b7 lui ra,0xff0 + 80002b34: 0ff0809b addiw ra,ra,255 + 80002b38: 0f0f1137 lui sp,0xf0f1 + 80002b3c: f0f1011b addiw sp,sp,-241 + 80002b40: 0020cf33 xor t5,ra,sp + 80002b44: 0ff01eb7 lui t4,0xff01 + 80002b48: ff0e8e9b addiw t4,t4,-16 + 80002b4c: 00400193 li gp,4 + 80002b50: 55df1063 bne t5,t4,80003090 + +0000000080002b54 : + 80002b54: 000f00b7 lui ra,0xf0 + 80002b58: 0ff0809b addiw ra,ra,255 + 80002b5c: 00c09093 slli ra,ra,0xc + 80002b60: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80002b64: 000f1137 lui sp,0xf1 + 80002b68: f0f1011b addiw sp,sp,-241 + 80002b6c: 00c11113 slli sp,sp,0xc + 80002b70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002b74: 0020cf33 xor t5,ra,sp + 80002b78: 00ff0eb7 lui t4,0xff0 + 80002b7c: 0ffe8e9b addiw t4,t4,255 + 80002b80: 00500193 li gp,5 + 80002b84: 51df1663 bne t5,t4,80003090 + +0000000080002b88 : + 80002b88: 000100b7 lui ra,0x10 + 80002b8c: f010809b addiw ra,ra,-255 + 80002b90: 01009093 slli ra,ra,0x10 + 80002b94: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002b98: 0f0f1137 lui sp,0xf0f1 + 80002b9c: f0f1011b addiw sp,sp,-241 + 80002ba0: 0020c0b3 xor ra,ra,sp + 80002ba4: 000f0eb7 lui t4,0xf0 + 80002ba8: 0ffe8e9b addiw t4,t4,255 + 80002bac: 00ce9e93 slli t4,t4,0xc + 80002bb0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002bb4: 00600193 li gp,6 + 80002bb8: 4dd09c63 bne ra,t4,80003090 + +0000000080002bbc : + 80002bbc: 000100b7 lui ra,0x10 + 80002bc0: f010809b addiw ra,ra,-255 + 80002bc4: 01009093 slli ra,ra,0x10 + 80002bc8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002bcc: 0f0f1137 lui sp,0xf0f1 + 80002bd0: f0f1011b addiw sp,sp,-241 + 80002bd4: 0020c133 xor sp,ra,sp + 80002bd8: 000f0eb7 lui t4,0xf0 + 80002bdc: 0ffe8e9b addiw t4,t4,255 + 80002be0: 00ce9e93 slli t4,t4,0xc + 80002be4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002be8: 00700193 li gp,7 + 80002bec: 4bd11263 bne sp,t4,80003090 + +0000000080002bf0 : + 80002bf0: 000100b7 lui ra,0x10 + 80002bf4: f010809b addiw ra,ra,-255 + 80002bf8: 01009093 slli ra,ra,0x10 + 80002bfc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002c00: 0010c0b3 xor ra,ra,ra + 80002c04: 00000e93 li t4,0 + 80002c08: 00800193 li gp,8 + 80002c0c: 49d09263 bne ra,t4,80003090 + +0000000080002c10 : + 80002c10: 00000213 li tp,0 + 80002c14: 000100b7 lui ra,0x10 + 80002c18: f010809b addiw ra,ra,-255 + 80002c1c: 01009093 slli ra,ra,0x10 + 80002c20: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002c24: 0f0f1137 lui sp,0xf0f1 + 80002c28: f0f1011b addiw sp,sp,-241 + 80002c2c: 0020cf33 xor t5,ra,sp + 80002c30: 000f0313 mv t1,t5 + 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c38: 00200293 li t0,2 + 80002c3c: fc521ce3 bne tp,t0,80002c14 + 80002c40: 000f0eb7 lui t4,0xf0 + 80002c44: 0ffe8e9b addiw t4,t4,255 + 80002c48: 00ce9e93 slli t4,t4,0xc + 80002c4c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002c50: 00900193 li gp,9 + 80002c54: 43d31e63 bne t1,t4,80003090 + +0000000080002c58 : + 80002c58: 00000213 li tp,0 + 80002c5c: 0ff010b7 lui ra,0xff01 + 80002c60: ff00809b addiw ra,ra,-16 + 80002c64: 000f1137 lui sp,0xf1 + 80002c68: f0f1011b addiw sp,sp,-241 + 80002c6c: 00c11113 slli sp,sp,0xc + 80002c70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002c74: 0020cf33 xor t5,ra,sp + 80002c78: 00000013 nop + 80002c7c: 000f0313 mv t1,t5 + 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c84: 00200293 li t0,2 + 80002c88: fc521ae3 bne tp,t0,80002c5c + 80002c8c: 00010eb7 lui t4,0x10 + 80002c90: f01e8e9b addiw t4,t4,-255 + 80002c94: 010e9e93 slli t4,t4,0x10 + 80002c98: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002c9c: 00a00193 li gp,10 + 80002ca0: 3fd31863 bne t1,t4,80003090 + +0000000080002ca4 : + 80002ca4: 00000213 li tp,0 + 80002ca8: 00ff00b7 lui ra,0xff0 + 80002cac: 0ff0809b addiw ra,ra,255 + 80002cb0: 0f0f1137 lui sp,0xf0f1 + 80002cb4: f0f1011b addiw sp,sp,-241 + 80002cb8: 0020cf33 xor t5,ra,sp + 80002cbc: 00000013 nop + 80002cc0: 00000013 nop + 80002cc4: 000f0313 mv t1,t5 + 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ccc: 00200293 li t0,2 + 80002cd0: fc521ce3 bne tp,t0,80002ca8 + 80002cd4: 0ff01eb7 lui t4,0xff01 + 80002cd8: ff0e8e9b addiw t4,t4,-16 + 80002cdc: 00b00193 li gp,11 + 80002ce0: 3bd31863 bne t1,t4,80003090 + +0000000080002ce4 : + 80002ce4: 00000213 li tp,0 + 80002ce8: 000100b7 lui ra,0x10 + 80002cec: f010809b addiw ra,ra,-255 + 80002cf0: 01009093 slli ra,ra,0x10 + 80002cf4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002cf8: 0f0f1137 lui sp,0xf0f1 + 80002cfc: f0f1011b addiw sp,sp,-241 + 80002d00: 0020cf33 xor t5,ra,sp + 80002d04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d08: 00200293 li t0,2 + 80002d0c: fc521ee3 bne tp,t0,80002ce8 + 80002d10: 000f0eb7 lui t4,0xf0 + 80002d14: 0ffe8e9b addiw t4,t4,255 + 80002d18: 00ce9e93 slli t4,t4,0xc + 80002d1c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002d20: 00c00193 li gp,12 + 80002d24: 37df1663 bne t5,t4,80003090 + +0000000080002d28 : + 80002d28: 00000213 li tp,0 + 80002d2c: 0ff010b7 lui ra,0xff01 + 80002d30: ff00809b addiw ra,ra,-16 + 80002d34: 000f1137 lui sp,0xf1 + 80002d38: f0f1011b addiw sp,sp,-241 + 80002d3c: 00c11113 slli sp,sp,0xc + 80002d40: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002d44: 00000013 nop + 80002d48: 0020cf33 xor t5,ra,sp + 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d50: 00200293 li t0,2 + 80002d54: fc521ce3 bne tp,t0,80002d2c + 80002d58: 00010eb7 lui t4,0x10 + 80002d5c: f01e8e9b addiw t4,t4,-255 + 80002d60: 010e9e93 slli t4,t4,0x10 + 80002d64: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002d68: 00d00193 li gp,13 + 80002d6c: 33df1263 bne t5,t4,80003090 + +0000000080002d70 : + 80002d70: 00000213 li tp,0 + 80002d74: 00ff00b7 lui ra,0xff0 + 80002d78: 0ff0809b addiw ra,ra,255 + 80002d7c: 0f0f1137 lui sp,0xf0f1 + 80002d80: f0f1011b addiw sp,sp,-241 + 80002d84: 00000013 nop + 80002d88: 00000013 nop + 80002d8c: 0020cf33 xor t5,ra,sp + 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d94: 00200293 li t0,2 + 80002d98: fc521ee3 bne tp,t0,80002d74 + 80002d9c: 0ff01eb7 lui t4,0xff01 + 80002da0: ff0e8e9b addiw t4,t4,-16 + 80002da4: 00e00193 li gp,14 + 80002da8: 2fdf1463 bne t5,t4,80003090 + +0000000080002dac : + 80002dac: 00000213 li tp,0 + 80002db0: 000100b7 lui ra,0x10 + 80002db4: f010809b addiw ra,ra,-255 + 80002db8: 01009093 slli ra,ra,0x10 + 80002dbc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002dc0: 00000013 nop + 80002dc4: 0f0f1137 lui sp,0xf0f1 + 80002dc8: f0f1011b addiw sp,sp,-241 + 80002dcc: 0020cf33 xor t5,ra,sp + 80002dd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd4: 00200293 li t0,2 + 80002dd8: fc521ce3 bne tp,t0,80002db0 + 80002ddc: 000f0eb7 lui t4,0xf0 + 80002de0: 0ffe8e9b addiw t4,t4,255 + 80002de4: 00ce9e93 slli t4,t4,0xc + 80002de8: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002dec: 00f00193 li gp,15 + 80002df0: 2bdf1063 bne t5,t4,80003090 + +0000000080002df4 : + 80002df4: 00000213 li tp,0 + 80002df8: 0ff010b7 lui ra,0xff01 + 80002dfc: ff00809b addiw ra,ra,-16 + 80002e00: 00000013 nop + 80002e04: 000f1137 lui sp,0xf1 + 80002e08: f0f1011b addiw sp,sp,-241 + 80002e0c: 00c11113 slli sp,sp,0xc + 80002e10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002e14: 00000013 nop + 80002e18: 0020cf33 xor t5,ra,sp + 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e20: 00200293 li t0,2 + 80002e24: fc521ae3 bne tp,t0,80002df8 + 80002e28: 00010eb7 lui t4,0x10 + 80002e2c: f01e8e9b addiw t4,t4,-255 + 80002e30: 010e9e93 slli t4,t4,0x10 + 80002e34: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002e38: 01000193 li gp,16 + 80002e3c: 25df1a63 bne t5,t4,80003090 + +0000000080002e40 : + 80002e40: 00000213 li tp,0 + 80002e44: 00ff00b7 lui ra,0xff0 + 80002e48: 0ff0809b addiw ra,ra,255 + 80002e4c: 00000013 nop + 80002e50: 00000013 nop + 80002e54: 0f0f1137 lui sp,0xf0f1 + 80002e58: f0f1011b addiw sp,sp,-241 + 80002e5c: 0020cf33 xor t5,ra,sp + 80002e60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e64: 00200293 li t0,2 + 80002e68: fc521ee3 bne tp,t0,80002e44 + 80002e6c: 0ff01eb7 lui t4,0xff01 + 80002e70: ff0e8e9b addiw t4,t4,-16 + 80002e74: 01100193 li gp,17 + 80002e78: 21df1c63 bne t5,t4,80003090 + +0000000080002e7c : + 80002e7c: 00000213 li tp,0 + 80002e80: 0f0f1137 lui sp,0xf0f1 + 80002e84: f0f1011b addiw sp,sp,-241 + 80002e88: 000100b7 lui ra,0x10 + 80002e8c: f010809b addiw ra,ra,-255 + 80002e90: 01009093 slli ra,ra,0x10 + 80002e94: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002e98: 0020cf33 xor t5,ra,sp + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fc521ee3 bne tp,t0,80002e80 + 80002ea8: 000f0eb7 lui t4,0xf0 + 80002eac: 0ffe8e9b addiw t4,t4,255 + 80002eb0: 00ce9e93 slli t4,t4,0xc + 80002eb4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002eb8: 01200193 li gp,18 + 80002ebc: 1ddf1a63 bne t5,t4,80003090 + +0000000080002ec0 : + 80002ec0: 00000213 li tp,0 + 80002ec4: 000f1137 lui sp,0xf1 + 80002ec8: f0f1011b addiw sp,sp,-241 + 80002ecc: 00c11113 slli sp,sp,0xc + 80002ed0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002ed4: 0ff010b7 lui ra,0xff01 + 80002ed8: ff00809b addiw ra,ra,-16 + 80002edc: 00000013 nop + 80002ee0: 0020cf33 xor t5,ra,sp + 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ee8: 00200293 li t0,2 + 80002eec: fc521ce3 bne tp,t0,80002ec4 + 80002ef0: 00010eb7 lui t4,0x10 + 80002ef4: f01e8e9b addiw t4,t4,-255 + 80002ef8: 010e9e93 slli t4,t4,0x10 + 80002efc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002f00: 01300193 li gp,19 + 80002f04: 19df1663 bne t5,t4,80003090 + +0000000080002f08 : + 80002f08: 00000213 li tp,0 + 80002f0c: 0f0f1137 lui sp,0xf0f1 + 80002f10: f0f1011b addiw sp,sp,-241 + 80002f14: 00ff00b7 lui ra,0xff0 + 80002f18: 0ff0809b addiw ra,ra,255 + 80002f1c: 00000013 nop + 80002f20: 00000013 nop + 80002f24: 0020cf33 xor t5,ra,sp + 80002f28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f2c: 00200293 li t0,2 + 80002f30: fc521ee3 bne tp,t0,80002f0c + 80002f34: 0ff01eb7 lui t4,0xff01 + 80002f38: ff0e8e9b addiw t4,t4,-16 + 80002f3c: 01400193 li gp,20 + 80002f40: 15df1863 bne t5,t4,80003090 + +0000000080002f44 : + 80002f44: 00000213 li tp,0 + 80002f48: 0f0f1137 lui sp,0xf0f1 + 80002f4c: f0f1011b addiw sp,sp,-241 + 80002f50: 00000013 nop + 80002f54: 000100b7 lui ra,0x10 + 80002f58: f010809b addiw ra,ra,-255 + 80002f5c: 01009093 slli ra,ra,0x10 + 80002f60: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80002f64: 0020cf33 xor t5,ra,sp + 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f6c: 00200293 li t0,2 + 80002f70: fc521ce3 bne tp,t0,80002f48 + 80002f74: 000f0eb7 lui t4,0xf0 + 80002f78: 0ffe8e9b addiw t4,t4,255 + 80002f7c: 00ce9e93 slli t4,t4,0xc + 80002f80: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80002f84: 01500193 li gp,21 + 80002f88: 11df1463 bne t5,t4,80003090 + +0000000080002f8c : + 80002f8c: 00000213 li tp,0 + 80002f90: 000f1137 lui sp,0xf1 + 80002f94: f0f1011b addiw sp,sp,-241 + 80002f98: 00c11113 slli sp,sp,0xc + 80002f9c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80002fa0: 00000013 nop + 80002fa4: 0ff010b7 lui ra,0xff01 + 80002fa8: ff00809b addiw ra,ra,-16 + 80002fac: 00000013 nop + 80002fb0: 0020cf33 xor t5,ra,sp + 80002fb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002fb8: 00200293 li t0,2 + 80002fbc: fc521ae3 bne tp,t0,80002f90 + 80002fc0: 00010eb7 lui t4,0x10 + 80002fc4: f01e8e9b addiw t4,t4,-255 + 80002fc8: 010e9e93 slli t4,t4,0x10 + 80002fcc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80002fd0: 01600193 li gp,22 + 80002fd4: 0bdf1e63 bne t5,t4,80003090 + +0000000080002fd8 : + 80002fd8: 00000213 li tp,0 + 80002fdc: 0f0f1137 lui sp,0xf0f1 + 80002fe0: f0f1011b addiw sp,sp,-241 + 80002fe4: 00000013 nop + 80002fe8: 00000013 nop + 80002fec: 00ff00b7 lui ra,0xff0 + 80002ff0: 0ff0809b addiw ra,ra,255 + 80002ff4: 0020cf33 xor t5,ra,sp + 80002ff8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ffc: 00200293 li t0,2 + 80003000: fc521ee3 bne tp,t0,80002fdc + 80003004: 0ff01eb7 lui t4,0xff01 + 80003008: ff0e8e9b addiw t4,t4,-16 + 8000300c: 01700193 li gp,23 + 80003010: 09df1063 bne t5,t4,80003090 + +0000000080003014 : + 80003014: 000100b7 lui ra,0x10 + 80003018: f010809b addiw ra,ra,-255 + 8000301c: 01009093 slli ra,ra,0x10 + 80003020: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80003024: 00104133 xor sp,zero,ra + 80003028: 00010eb7 lui t4,0x10 + 8000302c: f01e8e9b addiw t4,t4,-255 + 80003030: 010e9e93 slli t4,t4,0x10 + 80003034: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80003038: 01800193 li gp,24 + 8000303c: 05d11a63 bne sp,t4,80003090 + +0000000080003040 : + 80003040: 00ff00b7 lui ra,0xff0 + 80003044: 0ff0809b addiw ra,ra,255 + 80003048: 0000c133 xor sp,ra,zero + 8000304c: 00ff0eb7 lui t4,0xff0 + 80003050: 0ffe8e9b addiw t4,t4,255 + 80003054: 01900193 li gp,25 + 80003058: 03d11c63 bne sp,t4,80003090 + +000000008000305c : + 8000305c: 000040b3 xor ra,zero,zero + 80003060: 00000e93 li t4,0 + 80003064: 01a00193 li gp,26 + 80003068: 03d09463 bne ra,t4,80003090 + +000000008000306c : + 8000306c: 111110b7 lui ra,0x11111 + 80003070: 1110809b addiw ra,ra,273 + 80003074: 22222137 lui sp,0x22222 + 80003078: 2221011b addiw sp,sp,546 + 8000307c: 0020c033 xor zero,ra,sp + 80003080: 00000e93 li t4,0 + 80003084: 01b00193 li gp,27 + 80003088: 01d01463 bne zero,t4,80003090 + 8000308c: 00301a63 bne zero,gp,800030a0 + +0000000080003090 : + 80003090: 00119513 slli a0,gp,0x1 + 80003094: 00050063 beqz a0,80003094 + 80003098: 00156513 ori a0,a0,1 + 8000309c: 00000073 ecall + +00000000800030a0 : + 800030a0: 00100513 li a0,1 + 800030a4: 00000073 ecall + 800030a8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-xor.elf b/test/riscv/tests/rv64ui-v-xor.elf new file mode 100644 index 00000000..151c2119 Binary files /dev/null and b/test/riscv/tests/rv64ui-v-xor.elf differ diff --git a/test/riscv/tests/rv64ui-v-xori.dump b/test/riscv/tests/rv64ui-v-xori.dump new file mode 100644 index 00000000..cc0d051a --- /dev/null +++ b/test/riscv/tests/rv64ui-v-xori.dump @@ -0,0 +1,985 @@ + +rv64ui-v-xori: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: 87068693 addi a3,a3,-1936 # 80002cc8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: 8a460613 addi a2,a2,-1884 # 80002d58 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: 86c60613 addi a2,a2,-1940 # 80002d70 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 7bc68693 addi a3,a3,1980 # 80002d10 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 7d868693 addi a3,a3,2008 # 80002e48 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 75860613 addi a2,a2,1880 # 80002e20 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 68c68693 addi a3,a3,1676 # 80002e78 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 5ac68693 addi a3,a3,1452 # 80002de8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 53c68693 addi a3,a3,1340 # 80002db0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02400793 li a5,36 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 08da87b7 lui a5,0x8da8 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: ffc78793 addi a5,a5,-4 # 8da7ffc <_start-0x77258004> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00ff10b7 lui ra,0xff1 + 80002acc: f000809b addiw ra,ra,-256 + 80002ad0: f0f0cf13 xori t5,ra,-241 + 80002ad4: ff00feb7 lui t4,0xff00f + 80002ad8: 00fe8e9b addiw t4,t4,15 + 80002adc: 00200193 li gp,2 + 80002ae0: 1ddf1663 bne t5,t4,80002cac + +0000000080002ae4 : + 80002ae4: 0ff010b7 lui ra,0xff01 + 80002ae8: ff00809b addiw ra,ra,-16 + 80002aec: 0f00cf13 xori t5,ra,240 + 80002af0: 0ff01eb7 lui t4,0xff01 + 80002af4: f00e8e9b addiw t4,t4,-256 + 80002af8: 00300193 li gp,3 + 80002afc: 1bdf1863 bne t5,t4,80002cac + +0000000080002b00 : + 80002b00: 00ff10b7 lui ra,0xff1 + 80002b04: 8ff0809b addiw ra,ra,-1793 + 80002b08: 70f0cf13 xori t5,ra,1807 + 80002b0c: 00ff1eb7 lui t4,0xff1 + 80002b10: ff0e8e9b addiw t4,t4,-16 + 80002b14: 00400193 li gp,4 + 80002b18: 19df1a63 bne t5,t4,80002cac + +0000000080002b1c : + 80002b1c: f00ff0b7 lui ra,0xf00ff + 80002b20: 00f0809b addiw ra,ra,15 + 80002b24: 0f00cf13 xori t5,ra,240 + 80002b28: f00ffeb7 lui t4,0xf00ff + 80002b2c: 0ffe8e9b addiw t4,t4,255 + 80002b30: 00500193 li gp,5 + 80002b34: 17df1c63 bne t5,t4,80002cac + +0000000080002b38 : + 80002b38: ff00f0b7 lui ra,0xff00f + 80002b3c: 7000809b addiw ra,ra,1792 + 80002b40: 70f0c093 xori ra,ra,1807 + 80002b44: ff00feb7 lui t4,0xff00f + 80002b48: 00fe8e9b addiw t4,t4,15 + 80002b4c: 00600193 li gp,6 + 80002b50: 15d09e63 bne ra,t4,80002cac + +0000000080002b54 : + 80002b54: 00000213 li tp,0 + 80002b58: 0ff010b7 lui ra,0xff01 + 80002b5c: ff00809b addiw ra,ra,-16 + 80002b60: 0f00cf13 xori t5,ra,240 + 80002b64: 000f0313 mv t1,t5 + 80002b68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002b6c: 00200293 li t0,2 + 80002b70: fe5214e3 bne tp,t0,80002b58 + 80002b74: 0ff01eb7 lui t4,0xff01 + 80002b78: f00e8e9b addiw t4,t4,-256 + 80002b7c: 00700193 li gp,7 + 80002b80: 13d31663 bne t1,t4,80002cac + +0000000080002b84 : + 80002b84: 00000213 li tp,0 + 80002b88: 00ff10b7 lui ra,0xff1 + 80002b8c: 8ff0809b addiw ra,ra,-1793 + 80002b90: 70f0cf13 xori t5,ra,1807 + 80002b94: 00000013 nop + 80002b98: 000f0313 mv t1,t5 + 80002b9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ba0: 00200293 li t0,2 + 80002ba4: fe5212e3 bne tp,t0,80002b88 + 80002ba8: 00ff1eb7 lui t4,0xff1 + 80002bac: ff0e8e9b addiw t4,t4,-16 + 80002bb0: 00800193 li gp,8 + 80002bb4: 0fd31c63 bne t1,t4,80002cac + +0000000080002bb8 : + 80002bb8: 00000213 li tp,0 + 80002bbc: f00ff0b7 lui ra,0xf00ff + 80002bc0: 00f0809b addiw ra,ra,15 + 80002bc4: 0f00cf13 xori t5,ra,240 + 80002bc8: 00000013 nop + 80002bcc: 00000013 nop + 80002bd0: 000f0313 mv t1,t5 + 80002bd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd8: 00200293 li t0,2 + 80002bdc: fe5210e3 bne tp,t0,80002bbc + 80002be0: f00ffeb7 lui t4,0xf00ff + 80002be4: 0ffe8e9b addiw t4,t4,255 + 80002be8: 00900193 li gp,9 + 80002bec: 0dd31063 bne t1,t4,80002cac + +0000000080002bf0 : + 80002bf0: 00000213 li tp,0 + 80002bf4: 0ff010b7 lui ra,0xff01 + 80002bf8: ff00809b addiw ra,ra,-16 + 80002bfc: 0f00cf13 xori t5,ra,240 + 80002c00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c04: 00200293 li t0,2 + 80002c08: fe5216e3 bne tp,t0,80002bf4 + 80002c0c: 0ff01eb7 lui t4,0xff01 + 80002c10: f00e8e9b addiw t4,t4,-256 + 80002c14: 00a00193 li gp,10 + 80002c18: 09df1a63 bne t5,t4,80002cac + +0000000080002c1c : + 80002c1c: 00000213 li tp,0 + 80002c20: 00ff10b7 lui ra,0xff1 + 80002c24: fff0809b addiw ra,ra,-1 + 80002c28: 00000013 nop + 80002c2c: 00f0cf13 xori t5,ra,15 + 80002c30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c34: 00200293 li t0,2 + 80002c38: fe5214e3 bne tp,t0,80002c20 + 80002c3c: 00ff1eb7 lui t4,0xff1 + 80002c40: ff0e8e9b addiw t4,t4,-16 + 80002c44: 00b00193 li gp,11 + 80002c48: 07df1263 bne t5,t4,80002cac + +0000000080002c4c : + 80002c4c: 00000213 li tp,0 + 80002c50: f00ff0b7 lui ra,0xf00ff + 80002c54: 00f0809b addiw ra,ra,15 + 80002c58: 00000013 nop + 80002c5c: 00000013 nop + 80002c60: 0f00cf13 xori t5,ra,240 + 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c68: 00200293 li t0,2 + 80002c6c: fe5212e3 bne tp,t0,80002c50 + 80002c70: f00ffeb7 lui t4,0xf00ff + 80002c74: 0ffe8e9b addiw t4,t4,255 + 80002c78: 00c00193 li gp,12 + 80002c7c: 03df1863 bne t5,t4,80002cac + +0000000080002c80 : + 80002c80: 0f004093 xori ra,zero,240 + 80002c84: 0f000e93 li t4,240 + 80002c88: 00d00193 li gp,13 + 80002c8c: 03d09063 bne ra,t4,80002cac + +0000000080002c90 : + 80002c90: 00ff00b7 lui ra,0xff0 + 80002c94: 0ff0809b addiw ra,ra,255 + 80002c98: 70f0c013 xori zero,ra,1807 + 80002c9c: 00000e93 li t4,0 + 80002ca0: 00e00193 li gp,14 + 80002ca4: 01d01463 bne zero,t4,80002cac + 80002ca8: 00301a63 bne zero,gp,80002cbc + +0000000080002cac : + 80002cac: 00119513 slli a0,gp,0x1 + 80002cb0: 00050063 beqz a0,80002cb0 + 80002cb4: 00156513 ori a0,a0,1 + 80002cb8: 00000073 ecall + +0000000080002cbc : + 80002cbc: 00100513 li a0,1 + 80002cc0: 00000073 ecall + 80002cc4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-xori.elf b/test/riscv/tests/rv64ui-v-xori.elf new file mode 100644 index 00000000..d716ff2e Binary files /dev/null and b/test/riscv/tests/rv64ui-v-xori.elf differ diff --git a/test/riscv/tests/rv64um-p-div.elf b/test/riscv/tests/rv64um-p-div.elf old mode 100755 new mode 100644 index f8df5452..d202d094 Binary files a/test/riscv/tests/rv64um-p-div.elf and b/test/riscv/tests/rv64um-p-div.elf differ diff --git a/test/riscv/tests/rv64um-p-divu.elf b/test/riscv/tests/rv64um-p-divu.elf old mode 100755 new mode 100644 index d02748e3..bef0d696 Binary files a/test/riscv/tests/rv64um-p-divu.elf and b/test/riscv/tests/rv64um-p-divu.elf differ diff --git a/test/riscv/tests/rv64um-p-divuw.elf b/test/riscv/tests/rv64um-p-divuw.elf old mode 100755 new mode 100644 index b0da149b..1d1e44fa Binary files a/test/riscv/tests/rv64um-p-divuw.elf and b/test/riscv/tests/rv64um-p-divuw.elf differ diff --git a/test/riscv/tests/rv64um-p-divw.elf b/test/riscv/tests/rv64um-p-divw.elf old mode 100755 new mode 100644 index eb2e0f58..e39eb53d Binary files a/test/riscv/tests/rv64um-p-divw.elf and b/test/riscv/tests/rv64um-p-divw.elf differ diff --git a/test/riscv/tests/rv64um-p-mul.elf b/test/riscv/tests/rv64um-p-mul.elf old mode 100755 new mode 100644 index 7107505a..4983abe5 Binary files a/test/riscv/tests/rv64um-p-mul.elf and b/test/riscv/tests/rv64um-p-mul.elf differ diff --git a/test/riscv/tests/rv64um-p-mulh.elf b/test/riscv/tests/rv64um-p-mulh.elf old mode 100755 new mode 100644 index f44264b4..4118cecd Binary files a/test/riscv/tests/rv64um-p-mulh.elf and b/test/riscv/tests/rv64um-p-mulh.elf differ diff --git a/test/riscv/tests/rv64um-p-mulhsu.elf b/test/riscv/tests/rv64um-p-mulhsu.elf old mode 100755 new mode 100644 index 93efb0b3..37979feb Binary files a/test/riscv/tests/rv64um-p-mulhsu.elf and b/test/riscv/tests/rv64um-p-mulhsu.elf differ diff --git a/test/riscv/tests/rv64um-p-mulhu.elf b/test/riscv/tests/rv64um-p-mulhu.elf old mode 100755 new mode 100644 index f2b74120..e3ae453e Binary files a/test/riscv/tests/rv64um-p-mulhu.elf and b/test/riscv/tests/rv64um-p-mulhu.elf differ diff --git a/test/riscv/tests/rv64um-p-mulw.elf b/test/riscv/tests/rv64um-p-mulw.elf old mode 100755 new mode 100644 index 7b1242fd..9c3214c6 Binary files a/test/riscv/tests/rv64um-p-mulw.elf and b/test/riscv/tests/rv64um-p-mulw.elf differ diff --git a/test/riscv/tests/rv64um-p-rem.elf b/test/riscv/tests/rv64um-p-rem.elf old mode 100755 new mode 100644 index 55cc62b8..cfe6e6c2 Binary files a/test/riscv/tests/rv64um-p-rem.elf and b/test/riscv/tests/rv64um-p-rem.elf differ diff --git a/test/riscv/tests/rv64um-p-remu.elf b/test/riscv/tests/rv64um-p-remu.elf old mode 100755 new mode 100644 index ba6c64ac..93dcf5ed Binary files a/test/riscv/tests/rv64um-p-remu.elf and b/test/riscv/tests/rv64um-p-remu.elf differ diff --git a/test/riscv/tests/rv64um-p-remuw.elf b/test/riscv/tests/rv64um-p-remuw.elf old mode 100755 new mode 100644 index 86cf837c..ba166ff5 Binary files a/test/riscv/tests/rv64um-p-remuw.elf and b/test/riscv/tests/rv64um-p-remuw.elf differ diff --git a/test/riscv/tests/rv64um-p-remw.elf b/test/riscv/tests/rv64um-p-remw.elf old mode 100755 new mode 100644 index 4ef57f28..55798a6e Binary files a/test/riscv/tests/rv64um-p-remw.elf and b/test/riscv/tests/rv64um-p-remw.elf differ diff --git a/test/riscv/tests/rv64um-v-div.dump b/test/riscv/tests/rv64um-v-div.dump new file mode 100644 index 00000000..bfc4ab13 --- /dev/null +++ b/test/riscv/tests/rv64um-v-div.dump @@ -0,0 +1,916 @@ + +rv64um-v-div: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 77c60613 addi a2,a2,1916 # 80002c80 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6e868693 addi a3,a3,1768 # 80002d58 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 66860613 addi a2,a2,1640 # 80002d30 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03c00793 li a5,60 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 07a167b7 lui a5,0x7a16 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: cc378793 addi a5,a5,-829 # 7a15cc3 <_start-0x785ea33d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220cf33 div t5,ra,sp + 80002ad4: 00300e93 li t4,3 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1e63 bne t5,t4,80002bb8 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220cf33 div t5,ra,sp + 80002aec: ffd00e93 li t4,-3 + 80002af0: 00300193 li gp,3 + 80002af4: 0ddf1263 bne t5,t4,80002bb8 + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220cf33 div t5,ra,sp + 80002b04: ffd00e93 li t4,-3 + 80002b08: 00400193 li gp,4 + 80002b0c: 0bdf1663 bne t5,t4,80002bb8 + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220cf33 div t5,ra,sp + 80002b1c: 00300e93 li t4,3 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1a63 bne t5,t4,80002bb8 + +0000000080002b28 : + 80002b28: fff0009b addiw ra,zero,-1 + 80002b2c: 03f09093 slli ra,ra,0x3f + 80002b30: 00100113 li sp,1 + 80002b34: 0220cf33 div t5,ra,sp + 80002b38: fff00e9b addiw t4,zero,-1 + 80002b3c: 03fe9e93 slli t4,t4,0x3f + 80002b40: 00600193 li gp,6 + 80002b44: 07df1a63 bne t5,t4,80002bb8 + +0000000080002b48 : + 80002b48: fff0009b addiw ra,zero,-1 + 80002b4c: 03f09093 slli ra,ra,0x3f + 80002b50: fff00113 li sp,-1 + 80002b54: 0220cf33 div t5,ra,sp + 80002b58: fff00e9b addiw t4,zero,-1 + 80002b5c: 03fe9e93 slli t4,t4,0x3f + 80002b60: 00700193 li gp,7 + 80002b64: 05df1a63 bne t5,t4,80002bb8 + +0000000080002b68 : + 80002b68: fff0009b addiw ra,zero,-1 + 80002b6c: 03f09093 slli ra,ra,0x3f + 80002b70: 00000113 li sp,0 + 80002b74: 0220cf33 div t5,ra,sp + 80002b78: fff00e93 li t4,-1 + 80002b7c: 00800193 li gp,8 + 80002b80: 03df1c63 bne t5,t4,80002bb8 + +0000000080002b84 : + 80002b84: 00100093 li ra,1 + 80002b88: 00000113 li sp,0 + 80002b8c: 0220cf33 div t5,ra,sp + 80002b90: fff00e93 li t4,-1 + 80002b94: 00900193 li gp,9 + 80002b98: 03df1063 bne t5,t4,80002bb8 + +0000000080002b9c : + 80002b9c: 00000093 li ra,0 + 80002ba0: 00000113 li sp,0 + 80002ba4: 0220cf33 div t5,ra,sp + 80002ba8: fff00e93 li t4,-1 + 80002bac: 00a00193 li gp,10 + 80002bb0: 01df1463 bne t5,t4,80002bb8 + 80002bb4: 00301a63 bne zero,gp,80002bc8 + +0000000080002bb8 : + 80002bb8: 00119513 slli a0,gp,0x1 + 80002bbc: 00050063 beqz a0,80002bbc + 80002bc0: 00156513 ori a0,a0,1 + 80002bc4: 00000073 ecall + +0000000080002bc8 : + 80002bc8: 00100513 li a0,1 + 80002bcc: 00000073 ecall + 80002bd0: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-div.elf b/test/riscv/tests/rv64um-v-div.elf new file mode 100644 index 00000000..3374b8ae Binary files /dev/null and b/test/riscv/tests/rv64um-v-div.elf differ diff --git a/test/riscv/tests/rv64um-v-divu.dump b/test/riscv/tests/rv64um-v-divu.dump new file mode 100644 index 00000000..68b9aab4 --- /dev/null +++ b/test/riscv/tests/rv64um-v-divu.dump @@ -0,0 +1,922 @@ + +rv64um-v-divu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 79868693 addi a3,a3,1944 # 80002bf0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7cc60613 addi a2,a2,1996 # 80002c80 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 79460613 addi a2,a2,1940 # 80002c98 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6e468693 addi a3,a3,1764 # 80002c38 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 70068693 addi a3,a3,1792 # 80002d70 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 68060613 addi a2,a2,1664 # 80002d48 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 5b468693 addi a3,a3,1460 # 80002da0 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4d468693 addi a3,a3,1236 # 80002d10 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 46468693 addi a3,a3,1124 # 80002cd8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01c00793 li a5,28 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0472c7b7 lui a5,0x472c + 80002a70: 000805b7 lui a1,0x80 + 80002a74: f1278793 addi a5,a5,-238 # 472bf12 <_start-0x7b8d40ee> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220df33 divu t5,ra,sp + 80002ad4: 00300e93 li t4,3 + 80002ad8: 00200193 li gp,2 + 80002adc: 0fdf1a63 bne t5,t4,80002bd0 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220df33 divu t5,ra,sp + 80002aec: 02aabeb7 lui t4,0x2aab + 80002af0: aabe8e9b addiw t4,t4,-1365 + 80002af4: 00ce9e93 slli t4,t4,0xc + 80002af8: aabe8e93 addi t4,t4,-1365 # 2aaaaab <_start-0x7d555555> + 80002afc: 00ce9e93 slli t4,t4,0xc + 80002b00: aabe8e93 addi t4,t4,-1365 + 80002b04: 00ce9e93 slli t4,t4,0xc + 80002b08: aa7e8e93 addi t4,t4,-1369 + 80002b0c: 00300193 li gp,3 + 80002b10: 0ddf1063 bne t5,t4,80002bd0 + +0000000080002b14 : + 80002b14: 01400093 li ra,20 + 80002b18: ffa00113 li sp,-6 + 80002b1c: 0220df33 divu t5,ra,sp + 80002b20: 00000e93 li t4,0 + 80002b24: 00400193 li gp,4 + 80002b28: 0bdf1463 bne t5,t4,80002bd0 + +0000000080002b2c : + 80002b2c: fec00093 li ra,-20 + 80002b30: ffa00113 li sp,-6 + 80002b34: 0220df33 divu t5,ra,sp + 80002b38: 00000e93 li t4,0 + 80002b3c: 00500193 li gp,5 + 80002b40: 09df1863 bne t5,t4,80002bd0 + +0000000080002b44 : + 80002b44: fff0009b addiw ra,zero,-1 + 80002b48: 03f09093 slli ra,ra,0x3f + 80002b4c: 00100113 li sp,1 + 80002b50: 0220df33 divu t5,ra,sp + 80002b54: fff00e9b addiw t4,zero,-1 + 80002b58: 03fe9e93 slli t4,t4,0x3f + 80002b5c: 00600193 li gp,6 + 80002b60: 07df1863 bne t5,t4,80002bd0 + +0000000080002b64 : + 80002b64: fff0009b addiw ra,zero,-1 + 80002b68: 03f09093 slli ra,ra,0x3f + 80002b6c: fff00113 li sp,-1 + 80002b70: 0220df33 divu t5,ra,sp + 80002b74: 00000e93 li t4,0 + 80002b78: 00700193 li gp,7 + 80002b7c: 05df1a63 bne t5,t4,80002bd0 + +0000000080002b80 : + 80002b80: fff0009b addiw ra,zero,-1 + 80002b84: 03f09093 slli ra,ra,0x3f + 80002b88: 00000113 li sp,0 + 80002b8c: 0220df33 divu t5,ra,sp + 80002b90: fff00e93 li t4,-1 + 80002b94: 00800193 li gp,8 + 80002b98: 03df1c63 bne t5,t4,80002bd0 + +0000000080002b9c : + 80002b9c: 00100093 li ra,1 + 80002ba0: 00000113 li sp,0 + 80002ba4: 0220df33 divu t5,ra,sp + 80002ba8: fff00e93 li t4,-1 + 80002bac: 00900193 li gp,9 + 80002bb0: 03df1063 bne t5,t4,80002bd0 + +0000000080002bb4 : + 80002bb4: 00000093 li ra,0 + 80002bb8: 00000113 li sp,0 + 80002bbc: 0220df33 divu t5,ra,sp + 80002bc0: fff00e93 li t4,-1 + 80002bc4: 00a00193 li gp,10 + 80002bc8: 01df1463 bne t5,t4,80002bd0 + 80002bcc: 00301a63 bne zero,gp,80002be0 + +0000000080002bd0 : + 80002bd0: 00119513 slli a0,gp,0x1 + 80002bd4: 00050063 beqz a0,80002bd4 + 80002bd8: 00156513 ori a0,a0,1 + 80002bdc: 00000073 ecall + +0000000080002be0 : + 80002be0: 00100513 li a0,1 + 80002be4: 00000073 ecall + 80002be8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divu.elf b/test/riscv/tests/rv64um-v-divu.elf new file mode 100644 index 00000000..4eec5386 Binary files /dev/null and b/test/riscv/tests/rv64um-v-divu.elf differ diff --git a/test/riscv/tests/rv64um-v-divuw.dump b/test/riscv/tests/rv64um-v-divuw.dump new file mode 100644 index 00000000..644f517e --- /dev/null +++ b/test/riscv/tests/rv64um-v-divuw.dump @@ -0,0 +1,914 @@ + +rv64um-v-divuw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 77868693 addi a3,a3,1912 # 80002bd0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7ac60613 addi a2,a2,1964 # 80002c60 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 77460613 addi a2,a2,1908 # 80002c78 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6c468693 addi a3,a3,1732 # 80002c18 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6e068693 addi a3,a3,1760 # 80002d50 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 66060613 addi a2,a2,1632 # 80002d28 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 59468693 addi a3,a3,1428 # 80002d80 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4b468693 addi a3,a3,1204 # 80002cf0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 44468693 addi a3,a3,1092 # 80002cb8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 02f00793 li a5,47 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0a3e47b7 lui a5,0xa3e4 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 49e78793 addi a5,a5,1182 # a3e449e <_start-0x75c1bb62> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220df3b divuw t5,ra,sp + 80002ad4: 00300e93 li t4,3 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1a63 bne t5,t4,80002bb0 + +0000000080002ae0 : + 80002ae0: 0010009b addiw ra,zero,1 + 80002ae4: 02009093 slli ra,ra,0x20 + 80002ae8: fec08093 addi ra,ra,-20 + 80002aec: 00600113 li sp,6 + 80002af0: 0220df3b divuw t5,ra,sp + 80002af4: 2aaabeb7 lui t4,0x2aaab + 80002af8: aa7e8e9b addiw t4,t4,-1369 + 80002afc: 00300193 li gp,3 + 80002b00: 0bdf1863 bne t5,t4,80002bb0 + +0000000080002b04 : + 80002b04: 01400093 li ra,20 + 80002b08: ffa00113 li sp,-6 + 80002b0c: 0220df3b divuw t5,ra,sp + 80002b10: 00000e93 li t4,0 + 80002b14: 00400193 li gp,4 + 80002b18: 09df1c63 bne t5,t4,80002bb0 + +0000000080002b1c : + 80002b1c: fec00093 li ra,-20 + 80002b20: ffa00113 li sp,-6 + 80002b24: 0220df3b divuw t5,ra,sp + 80002b28: 00000e93 li t4,0 + 80002b2c: 00500193 li gp,5 + 80002b30: 09df1063 bne t5,t4,80002bb0 + +0000000080002b34 : + 80002b34: 800000b7 lui ra,0x80000 + 80002b38: 00100113 li sp,1 + 80002b3c: 0220df3b divuw t5,ra,sp + 80002b40: 80000eb7 lui t4,0x80000 + 80002b44: 00600193 li gp,6 + 80002b48: 07df1463 bne t5,t4,80002bb0 + +0000000080002b4c : + 80002b4c: 800000b7 lui ra,0x80000 + 80002b50: fff00113 li sp,-1 + 80002b54: 0220df3b divuw t5,ra,sp + 80002b58: 00000e93 li t4,0 + 80002b5c: 00700193 li gp,7 + 80002b60: 05df1863 bne t5,t4,80002bb0 + +0000000080002b64 : + 80002b64: 800000b7 lui ra,0x80000 + 80002b68: 00000113 li sp,0 + 80002b6c: 0220df3b divuw t5,ra,sp + 80002b70: fff00e93 li t4,-1 + 80002b74: 00800193 li gp,8 + 80002b78: 03df1c63 bne t5,t4,80002bb0 + +0000000080002b7c : + 80002b7c: 00100093 li ra,1 + 80002b80: 00000113 li sp,0 + 80002b84: 0220df3b divuw t5,ra,sp + 80002b88: fff00e93 li t4,-1 + 80002b8c: 00900193 li gp,9 + 80002b90: 03df1063 bne t5,t4,80002bb0 + +0000000080002b94 : + 80002b94: 00000093 li ra,0 + 80002b98: 00000113 li sp,0 + 80002b9c: 0220df3b divuw t5,ra,sp + 80002ba0: fff00e93 li t4,-1 + 80002ba4: 00a00193 li gp,10 + 80002ba8: 01df1463 bne t5,t4,80002bb0 + 80002bac: 00301a63 bne zero,gp,80002bc0 + +0000000080002bb0 : + 80002bb0: 00119513 slli a0,gp,0x1 + 80002bb4: 00050063 beqz a0,80002bb4 + 80002bb8: 00156513 ori a0,a0,1 + 80002bbc: 00000073 ecall + +0000000080002bc0 : + 80002bc0: 00100513 li a0,1 + 80002bc4: 00000073 ecall + 80002bc8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divuw.elf b/test/riscv/tests/rv64um-v-divuw.elf new file mode 100644 index 00000000..f5ae7cb1 Binary files /dev/null and b/test/riscv/tests/rv64um-v-divuw.elf differ diff --git a/test/riscv/tests/rv64um-v-divw.dump b/test/riscv/tests/rv64um-v-divw.dump new file mode 100644 index 00000000..e2ba647c --- /dev/null +++ b/test/riscv/tests/rv64um-v-divw.dump @@ -0,0 +1,911 @@ + +rv64um-v-divw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 76868693 addi a3,a3,1896 # 80002bc0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 79c60613 addi a2,a2,1948 # 80002c50 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 76460613 addi a2,a2,1892 # 80002c68 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6b468693 addi a3,a3,1716 # 80002c08 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6d068693 addi a3,a3,1744 # 80002d40 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 65060613 addi a2,a2,1616 # 80002d18 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 58468693 addi a3,a3,1412 # 80002d70 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4a468693 addi a3,a3,1188 # 80002ce0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 43468693 addi a3,a3,1076 # 80002ca8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01700793 li a5,23 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 026ec7b7 lui a5,0x26ec + 80002a70: 000805b7 lui a1,0x80 + 80002a74: f8e78793 addi a5,a5,-114 # 26ebf8e <_start-0x7d914072> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220cf3b divw t5,ra,sp + 80002ad4: 00300e93 li t4,3 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1463 bne t5,t4,80002ba4 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220cf3b divw t5,ra,sp + 80002aec: ffd00e93 li t4,-3 + 80002af0: 00300193 li gp,3 + 80002af4: 0bdf1863 bne t5,t4,80002ba4 + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220cf3b divw t5,ra,sp + 80002b04: ffd00e93 li t4,-3 + 80002b08: 00400193 li gp,4 + 80002b0c: 09df1c63 bne t5,t4,80002ba4 + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220cf3b divw t5,ra,sp + 80002b1c: 00300e93 li t4,3 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1063 bne t5,t4,80002ba4 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00100113 li sp,1 + 80002b30: 0220cf3b divw t5,ra,sp + 80002b34: 80000eb7 lui t4,0x80000 + 80002b38: 00600193 li gp,6 + 80002b3c: 07df1463 bne t5,t4,80002ba4 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: fff00113 li sp,-1 + 80002b48: 0220cf3b divw t5,ra,sp + 80002b4c: 80000eb7 lui t4,0x80000 + 80002b50: 00700193 li gp,7 + 80002b54: 05df1863 bne t5,t4,80002ba4 + +0000000080002b58 : + 80002b58: 800000b7 lui ra,0x80000 + 80002b5c: 00000113 li sp,0 + 80002b60: 0220cf3b divw t5,ra,sp + 80002b64: fff00e93 li t4,-1 + 80002b68: 00800193 li gp,8 + 80002b6c: 03df1c63 bne t5,t4,80002ba4 + +0000000080002b70 : + 80002b70: 00100093 li ra,1 + 80002b74: 00000113 li sp,0 + 80002b78: 0220cf3b divw t5,ra,sp + 80002b7c: fff00e93 li t4,-1 + 80002b80: 00900193 li gp,9 + 80002b84: 03df1063 bne t5,t4,80002ba4 + +0000000080002b88 : + 80002b88: 00000093 li ra,0 + 80002b8c: 00000113 li sp,0 + 80002b90: 0220cf3b divw t5,ra,sp + 80002b94: fff00e93 li t4,-1 + 80002b98: 00a00193 li gp,10 + 80002b9c: 01df1463 bne t5,t4,80002ba4 + 80002ba0: 00301a63 bne zero,gp,80002bb4 + +0000000080002ba4 : + 80002ba4: 00119513 slli a0,gp,0x1 + 80002ba8: 00050063 beqz a0,80002ba8 + 80002bac: 00156513 ori a0,a0,1 + 80002bb0: 00000073 ecall + +0000000080002bb4 : + 80002bb4: 00100513 li a0,1 + 80002bb8: 00000073 ecall + 80002bbc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divw.elf b/test/riscv/tests/rv64um-v-divw.elf new file mode 100644 index 00000000..1ecdfcfb Binary files /dev/null and b/test/riscv/tests/rv64um-v-divw.elf differ diff --git a/test/riscv/tests/rv64um-v-mul.dump b/test/riscv/tests/rv64um-v-mul.dump new file mode 100644 index 00000000..784ee417 --- /dev/null +++ b/test/riscv/tests/rv64um-v-mul.dump @@ -0,0 +1,1209 @@ + +rv64um-v-mul: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b5868693 addi a3,a3,-1192 # 80002fb0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b8c60613 addi a2,a2,-1140 # 80003040 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b5460613 addi a2,a2,-1196 # 80003058 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: aa468693 addi a3,a3,-1372 # 80002ff8 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ac068693 addi a3,a3,-1344 # 80003130 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a4060613 addi a2,a2,-1472 # 80003108 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 97468693 addi a3,a3,-1676 # 80003160 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 89468693 addi a3,a3,-1900 # 800030d0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 82468693 addi a3,a3,-2012 # 80003098 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 02600793 li a5,38 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 054df7b7 lui a5,0x54df + 80002a70: 000805b7 lui a1,0x80 + 80002a74: b0278793 addi a5,a5,-1278 # 54deb02 <_start-0x7ab214fe> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 000080b7 lui ra,0x8 + 80002acc: e000809b addiw ra,ra,-512 + 80002ad0: 06db7137 lui sp,0x6db7 + 80002ad4: db71011b addiw sp,sp,-585 + 80002ad8: 00c11113 slli sp,sp,0xc + 80002adc: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> + 80002ae0: 00c11113 slli sp,sp,0xc + 80002ae4: db710113 addi sp,sp,-585 + 80002ae8: 00c11113 slli sp,sp,0xc + 80002aec: db710113 addi sp,sp,-585 + 80002af0: 02208f33 mul t5,ra,sp + 80002af4: 00001eb7 lui t4,0x1 + 80002af8: 200e8e9b addiw t4,t4,512 + 80002afc: 02000193 li gp,32 + 80002b00: 49df1a63 bne t5,t4,80002f94 + +0000000080002b04 : + 80002b04: 000080b7 lui ra,0x8 + 80002b08: fc00809b addiw ra,ra,-64 + 80002b0c: 06db7137 lui sp,0x6db7 + 80002b10: db71011b addiw sp,sp,-585 + 80002b14: 00c11113 slli sp,sp,0xc + 80002b18: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> + 80002b1c: 00c11113 slli sp,sp,0xc + 80002b20: db710113 addi sp,sp,-585 + 80002b24: 00c11113 slli sp,sp,0xc + 80002b28: db710113 addi sp,sp,-585 + 80002b2c: 02208f33 mul t5,ra,sp + 80002b30: 00001eb7 lui t4,0x1 + 80002b34: 240e8e9b addiw t4,t4,576 + 80002b38: 02100193 li gp,33 + 80002b3c: 45df1c63 bne t5,t4,80002f94 + +0000000080002b40 : + 80002b40: 00000093 li ra,0 + 80002b44: 00000113 li sp,0 + 80002b48: 02208f33 mul t5,ra,sp + 80002b4c: 00000e93 li t4,0 + 80002b50: 00200193 li gp,2 + 80002b54: 45df1063 bne t5,t4,80002f94 + +0000000080002b58 : + 80002b58: 00100093 li ra,1 + 80002b5c: 00100113 li sp,1 + 80002b60: 02208f33 mul t5,ra,sp + 80002b64: 00100e93 li t4,1 + 80002b68: 00300193 li gp,3 + 80002b6c: 43df1463 bne t5,t4,80002f94 + +0000000080002b70 : + 80002b70: 00300093 li ra,3 + 80002b74: 00700113 li sp,7 + 80002b78: 02208f33 mul t5,ra,sp + 80002b7c: 01500e93 li t4,21 + 80002b80: 00400193 li gp,4 + 80002b84: 41df1863 bne t5,t4,80002f94 + +0000000080002b88 : + 80002b88: 00000093 li ra,0 + 80002b8c: ffff8137 lui sp,0xffff8 + 80002b90: 02208f33 mul t5,ra,sp + 80002b94: 00000e93 li t4,0 + 80002b98: 00500193 li gp,5 + 80002b9c: 3fdf1c63 bne t5,t4,80002f94 + +0000000080002ba0 : + 80002ba0: 800000b7 lui ra,0x80000 + 80002ba4: 00000113 li sp,0 + 80002ba8: 02208f33 mul t5,ra,sp + 80002bac: 00000e93 li t4,0 + 80002bb0: 00600193 li gp,6 + 80002bb4: 3fdf1063 bne t5,t4,80002f94 + +0000000080002bb8 : + 80002bb8: 800000b7 lui ra,0x80000 + 80002bbc: ffff8137 lui sp,0xffff8 + 80002bc0: 02208f33 mul t5,ra,sp + 80002bc4: 00100e9b addiw t4,zero,1 + 80002bc8: 02ee9e93 slli t4,t4,0x2e + 80002bcc: 00700193 li gp,7 + 80002bd0: 3ddf1263 bne t5,t4,80002f94 + +0000000080002bd4 : + 80002bd4: faaab0b7 lui ra,0xfaaab + 80002bd8: aab0809b addiw ra,ra,-1365 + 80002bdc: 00c09093 slli ra,ra,0xc + 80002be0: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> + 80002be4: 00c09093 slli ra,ra,0xc + 80002be8: aab08093 addi ra,ra,-1365 + 80002bec: 00c09093 slli ra,ra,0xc + 80002bf0: aab08093 addi ra,ra,-1365 + 80002bf4: 00030137 lui sp,0x30 + 80002bf8: e7d1011b addiw sp,sp,-387 + 80002bfc: 02208f33 mul t5,ra,sp + 80002c00: 00010eb7 lui t4,0x10 + 80002c04: f7fe8e9b addiw t4,t4,-129 + 80002c08: 01e00193 li gp,30 + 80002c0c: 39df1463 bne t5,t4,80002f94 + +0000000080002c10 : + 80002c10: 000300b7 lui ra,0x30 + 80002c14: e7d0809b addiw ra,ra,-387 + 80002c18: faaab137 lui sp,0xfaaab + 80002c1c: aab1011b addiw sp,sp,-1365 + 80002c20: 00c11113 slli sp,sp,0xc + 80002c24: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> + 80002c28: 00c11113 slli sp,sp,0xc + 80002c2c: aab10113 addi sp,sp,-1365 + 80002c30: 00c11113 slli sp,sp,0xc + 80002c34: aab10113 addi sp,sp,-1365 + 80002c38: 02208f33 mul t5,ra,sp + 80002c3c: 00010eb7 lui t4,0x10 + 80002c40: f7fe8e9b addiw t4,t4,-129 + 80002c44: 01f00193 li gp,31 + 80002c48: 35df1663 bne t5,t4,80002f94 + +0000000080002c4c : + 80002c4c: 00d00093 li ra,13 + 80002c50: 00b00113 li sp,11 + 80002c54: 022080b3 mul ra,ra,sp + 80002c58: 08f00e93 li t4,143 + 80002c5c: 00800193 li gp,8 + 80002c60: 33d09a63 bne ra,t4,80002f94 + +0000000080002c64 : + 80002c64: 00e00093 li ra,14 + 80002c68: 00b00113 li sp,11 + 80002c6c: 02208133 mul sp,ra,sp + 80002c70: 09a00e93 li t4,154 + 80002c74: 00900193 li gp,9 + 80002c78: 31d11e63 bne sp,t4,80002f94 + +0000000080002c7c : + 80002c7c: 00d00093 li ra,13 + 80002c80: 021080b3 mul ra,ra,ra + 80002c84: 0a900e93 li t4,169 + 80002c88: 00a00193 li gp,10 + 80002c8c: 31d09463 bne ra,t4,80002f94 + +0000000080002c90 : + 80002c90: 00000213 li tp,0 + 80002c94: 00d00093 li ra,13 + 80002c98: 00b00113 li sp,11 + 80002c9c: 02208f33 mul t5,ra,sp + 80002ca0: 000f0313 mv t1,t5 + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5214e3 bne tp,t0,80002c94 + 80002cb0: 08f00e93 li t4,143 + 80002cb4: 00b00193 li gp,11 + 80002cb8: 2dd31e63 bne t1,t4,80002f94 + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 00e00093 li ra,14 + 80002cc4: 00b00113 li sp,11 + 80002cc8: 02208f33 mul t5,ra,sp + 80002ccc: 00000013 nop + 80002cd0: 000f0313 mv t1,t5 + 80002cd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cd8: 00200293 li t0,2 + 80002cdc: fe5212e3 bne tp,t0,80002cc0 + 80002ce0: 09a00e93 li t4,154 + 80002ce4: 00c00193 li gp,12 + 80002ce8: 2bd31663 bne t1,t4,80002f94 + +0000000080002cec : + 80002cec: 00000213 li tp,0 + 80002cf0: 00f00093 li ra,15 + 80002cf4: 00b00113 li sp,11 + 80002cf8: 02208f33 mul t5,ra,sp + 80002cfc: 00000013 nop + 80002d00: 00000013 nop + 80002d04: 000f0313 mv t1,t5 + 80002d08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d0c: 00200293 li t0,2 + 80002d10: fe5210e3 bne tp,t0,80002cf0 + 80002d14: 0a500e93 li t4,165 + 80002d18: 00d00193 li gp,13 + 80002d1c: 27d31c63 bne t1,t4,80002f94 + +0000000080002d20 : + 80002d20: 00000213 li tp,0 + 80002d24: 00d00093 li ra,13 + 80002d28: 00b00113 li sp,11 + 80002d2c: 02208f33 mul t5,ra,sp + 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d34: 00200293 li t0,2 + 80002d38: fe5216e3 bne tp,t0,80002d24 + 80002d3c: 08f00e93 li t4,143 + 80002d40: 00e00193 li gp,14 + 80002d44: 25df1863 bne t5,t4,80002f94 + +0000000080002d48 : + 80002d48: 00000213 li tp,0 + 80002d4c: 00e00093 li ra,14 + 80002d50: 00b00113 li sp,11 + 80002d54: 00000013 nop + 80002d58: 02208f33 mul t5,ra,sp + 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d60: 00200293 li t0,2 + 80002d64: fe5214e3 bne tp,t0,80002d4c + 80002d68: 09a00e93 li t4,154 + 80002d6c: 00f00193 li gp,15 + 80002d70: 23df1263 bne t5,t4,80002f94 + +0000000080002d74 : + 80002d74: 00000213 li tp,0 + 80002d78: 00f00093 li ra,15 + 80002d7c: 00b00113 li sp,11 + 80002d80: 00000013 nop + 80002d84: 00000013 nop + 80002d88: 02208f33 mul t5,ra,sp + 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d90: 00200293 li t0,2 + 80002d94: fe5212e3 bne tp,t0,80002d78 + 80002d98: 0a500e93 li t4,165 + 80002d9c: 01000193 li gp,16 + 80002da0: 1fdf1a63 bne t5,t4,80002f94 + +0000000080002da4 : + 80002da4: 00000213 li tp,0 + 80002da8: 00d00093 li ra,13 + 80002dac: 00000013 nop + 80002db0: 00b00113 li sp,11 + 80002db4: 02208f33 mul t5,ra,sp + 80002db8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dbc: 00200293 li t0,2 + 80002dc0: fe5214e3 bne tp,t0,80002da8 + 80002dc4: 08f00e93 li t4,143 + 80002dc8: 01100193 li gp,17 + 80002dcc: 1ddf1463 bne t5,t4,80002f94 + +0000000080002dd0 : + 80002dd0: 00000213 li tp,0 + 80002dd4: 00e00093 li ra,14 + 80002dd8: 00000013 nop + 80002ddc: 00b00113 li sp,11 + 80002de0: 00000013 nop + 80002de4: 02208f33 mul t5,ra,sp + 80002de8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dec: 00200293 li t0,2 + 80002df0: fe5212e3 bne tp,t0,80002dd4 + 80002df4: 09a00e93 li t4,154 + 80002df8: 01200193 li gp,18 + 80002dfc: 19df1c63 bne t5,t4,80002f94 + +0000000080002e00 : + 80002e00: 00000213 li tp,0 + 80002e04: 00f00093 li ra,15 + 80002e08: 00000013 nop + 80002e0c: 00000013 nop + 80002e10: 00b00113 li sp,11 + 80002e14: 02208f33 mul t5,ra,sp + 80002e18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e1c: 00200293 li t0,2 + 80002e20: fe5212e3 bne tp,t0,80002e04 + 80002e24: 0a500e93 li t4,165 + 80002e28: 01300193 li gp,19 + 80002e2c: 17df1463 bne t5,t4,80002f94 + +0000000080002e30 : + 80002e30: 00000213 li tp,0 + 80002e34: 00b00113 li sp,11 + 80002e38: 00d00093 li ra,13 + 80002e3c: 02208f33 mul t5,ra,sp + 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e44: 00200293 li t0,2 + 80002e48: fe5216e3 bne tp,t0,80002e34 + 80002e4c: 08f00e93 li t4,143 + 80002e50: 01400193 li gp,20 + 80002e54: 15df1063 bne t5,t4,80002f94 + +0000000080002e58 : + 80002e58: 00000213 li tp,0 + 80002e5c: 00b00113 li sp,11 + 80002e60: 00e00093 li ra,14 + 80002e64: 00000013 nop + 80002e68: 02208f33 mul t5,ra,sp + 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e70: 00200293 li t0,2 + 80002e74: fe5214e3 bne tp,t0,80002e5c + 80002e78: 09a00e93 li t4,154 + 80002e7c: 01500193 li gp,21 + 80002e80: 11df1a63 bne t5,t4,80002f94 + +0000000080002e84 : + 80002e84: 00000213 li tp,0 + 80002e88: 00b00113 li sp,11 + 80002e8c: 00f00093 li ra,15 + 80002e90: 00000013 nop + 80002e94: 00000013 nop + 80002e98: 02208f33 mul t5,ra,sp + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fe5212e3 bne tp,t0,80002e88 + 80002ea8: 0a500e93 li t4,165 + 80002eac: 01600193 li gp,22 + 80002eb0: 0fdf1263 bne t5,t4,80002f94 + +0000000080002eb4 : + 80002eb4: 00000213 li tp,0 + 80002eb8: 00b00113 li sp,11 + 80002ebc: 00000013 nop + 80002ec0: 00d00093 li ra,13 + 80002ec4: 02208f33 mul t5,ra,sp + 80002ec8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ecc: 00200293 li t0,2 + 80002ed0: fe5214e3 bne tp,t0,80002eb8 + 80002ed4: 08f00e93 li t4,143 + 80002ed8: 01700193 li gp,23 + 80002edc: 0bdf1c63 bne t5,t4,80002f94 + +0000000080002ee0 : + 80002ee0: 00000213 li tp,0 + 80002ee4: 00b00113 li sp,11 + 80002ee8: 00000013 nop + 80002eec: 00e00093 li ra,14 + 80002ef0: 00000013 nop + 80002ef4: 02208f33 mul t5,ra,sp + 80002ef8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002efc: 00200293 li t0,2 + 80002f00: fe5212e3 bne tp,t0,80002ee4 + 80002f04: 09a00e93 li t4,154 + 80002f08: 01800193 li gp,24 + 80002f0c: 09df1463 bne t5,t4,80002f94 + +0000000080002f10 : + 80002f10: 00000213 li tp,0 + 80002f14: 00b00113 li sp,11 + 80002f18: 00000013 nop + 80002f1c: 00000013 nop + 80002f20: 00f00093 li ra,15 + 80002f24: 02208f33 mul t5,ra,sp + 80002f28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f2c: 00200293 li t0,2 + 80002f30: fe5212e3 bne tp,t0,80002f14 + 80002f34: 0a500e93 li t4,165 + 80002f38: 01900193 li gp,25 + 80002f3c: 05df1c63 bne t5,t4,80002f94 + +0000000080002f40 : + 80002f40: 01f00093 li ra,31 + 80002f44: 02100133 mul sp,zero,ra + 80002f48: 00000e93 li t4,0 + 80002f4c: 01a00193 li gp,26 + 80002f50: 05d11263 bne sp,t4,80002f94 + +0000000080002f54 : + 80002f54: 02000093 li ra,32 + 80002f58: 02008133 mul sp,ra,zero + 80002f5c: 00000e93 li t4,0 + 80002f60: 01b00193 li gp,27 + 80002f64: 03d11863 bne sp,t4,80002f94 + +0000000080002f68 : + 80002f68: 020000b3 mul ra,zero,zero + 80002f6c: 00000e93 li t4,0 + 80002f70: 01c00193 li gp,28 + 80002f74: 03d09063 bne ra,t4,80002f94 + +0000000080002f78 : + 80002f78: 02100093 li ra,33 + 80002f7c: 02200113 li sp,34 + 80002f80: 02208033 mul zero,ra,sp + 80002f84: 00000e93 li t4,0 + 80002f88: 01d00193 li gp,29 + 80002f8c: 01d01463 bne zero,t4,80002f94 + 80002f90: 00301a63 bne zero,gp,80002fa4 + +0000000080002f94 : + 80002f94: 00119513 slli a0,gp,0x1 + 80002f98: 00050063 beqz a0,80002f98 + 80002f9c: 00156513 ori a0,a0,1 + 80002fa0: 00000073 ecall + +0000000080002fa4 : + 80002fa4: 00100513 li a0,1 + 80002fa8: 00000073 ecall + 80002fac: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mul.elf b/test/riscv/tests/rv64um-v-mul.elf new file mode 100644 index 00000000..64107a2c Binary files /dev/null and b/test/riscv/tests/rv64um-v-mul.elf differ diff --git a/test/riscv/tests/rv64um-v-mulh.dump b/test/riscv/tests/rv64um-v-mulh.dump new file mode 100644 index 00000000..17befcd4 --- /dev/null +++ b/test/riscv/tests/rv64um-v-mulh.dump @@ -0,0 +1,1179 @@ + +rv64um-v-mulh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b0068693 addi a3,a3,-1280 # 80002f58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b3460613 addi a2,a2,-1228 # 80002fe8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: afc60613 addi a2,a2,-1284 # 80003000 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: a4c68693 addi a3,a3,-1460 # 80002fa0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: a6868693 addi a3,a3,-1432 # 800030d8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 9e860613 addi a2,a2,-1560 # 800030b0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 91c68693 addi a3,a3,-1764 # 80003108 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 83c68693 addi a3,a3,-1988 # 80003078 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 7cc68693 addi a3,a3,1996 # 80003040 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 01700793 li a5,23 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0cb6d7b7 lui a5,0xcb6d + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 32278793 addi a5,a5,802 # cb6d322 <_start-0x73492cde> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 02209f33 mulh t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 47df1063 bne t5,t4,80002f3c + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 02209f33 mulh t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 45df1463 bne t5,t4,80002f3c + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 02209f33 mulh t5,ra,sp + 80002b04: 00000e93 li t4,0 + 80002b08: 00400193 li gp,4 + 80002b0c: 43df1863 bne t5,t4,80002f3c + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 02209f33 mulh t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 41df1c63 bne t5,t4,80002f3c + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 02209f33 mulh t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 41df1063 bne t5,t4,80002f3c + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 02209f33 mulh t5,ra,sp + 80002b4c: 00000e93 li t4,0 + 80002b50: 00700193 li gp,7 + 80002b54: 3fdf1463 bne t5,t4,80002f3c + +0000000080002b58 : + 80002b58: 00d0009b addiw ra,zero,13 + 80002b5c: 02009093 slli ra,ra,0x20 + 80002b60: 00b0011b addiw sp,zero,11 + 80002b64: 02011113 slli sp,sp,0x20 + 80002b68: 022090b3 mulh ra,ra,sp + 80002b6c: 08f00e93 li t4,143 + 80002b70: 00800193 li gp,8 + 80002b74: 3dd09463 bne ra,t4,80002f3c + +0000000080002b78 : + 80002b78: 0070009b addiw ra,zero,7 + 80002b7c: 02109093 slli ra,ra,0x21 + 80002b80: 00b0011b addiw sp,zero,11 + 80002b84: 02011113 slli sp,sp,0x20 + 80002b88: 02209133 mulh sp,ra,sp + 80002b8c: 09a00e93 li t4,154 + 80002b90: 00900193 li gp,9 + 80002b94: 3bd11463 bne sp,t4,80002f3c + +0000000080002b98 : + 80002b98: 00d0009b addiw ra,zero,13 + 80002b9c: 02009093 slli ra,ra,0x20 + 80002ba0: 021090b3 mulh ra,ra,ra + 80002ba4: 0a900e93 li t4,169 + 80002ba8: 00a00193 li gp,10 + 80002bac: 39d09863 bne ra,t4,80002f3c + +0000000080002bb0 : + 80002bb0: 00000213 li tp,0 + 80002bb4: 00d0009b addiw ra,zero,13 + 80002bb8: 02009093 slli ra,ra,0x20 + 80002bbc: 00b0011b addiw sp,zero,11 + 80002bc0: 02011113 slli sp,sp,0x20 + 80002bc4: 02209f33 mulh t5,ra,sp + 80002bc8: 000f0313 mv t1,t5 + 80002bcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd0: 00200293 li t0,2 + 80002bd4: fe5210e3 bne tp,t0,80002bb4 + 80002bd8: 08f00e93 li t4,143 + 80002bdc: 00b00193 li gp,11 + 80002be0: 35d31e63 bne t1,t4,80002f3c + +0000000080002be4 : + 80002be4: 00000213 li tp,0 + 80002be8: 0070009b addiw ra,zero,7 + 80002bec: 02109093 slli ra,ra,0x21 + 80002bf0: 00b0011b addiw sp,zero,11 + 80002bf4: 02011113 slli sp,sp,0x20 + 80002bf8: 02209f33 mulh t5,ra,sp + 80002bfc: 00000013 nop + 80002c00: 000f0313 mv t1,t5 + 80002c04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c08: 00200293 li t0,2 + 80002c0c: fc521ee3 bne tp,t0,80002be8 + 80002c10: 09a00e93 li t4,154 + 80002c14: 00c00193 li gp,12 + 80002c18: 33d31263 bne t1,t4,80002f3c + +0000000080002c1c : + 80002c1c: 00000213 li tp,0 + 80002c20: 00f0009b addiw ra,zero,15 + 80002c24: 02009093 slli ra,ra,0x20 + 80002c28: 00b0011b addiw sp,zero,11 + 80002c2c: 02011113 slli sp,sp,0x20 + 80002c30: 02209f33 mulh t5,ra,sp + 80002c34: 00000013 nop + 80002c38: 00000013 nop + 80002c3c: 000f0313 mv t1,t5 + 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c44: 00200293 li t0,2 + 80002c48: fc521ce3 bne tp,t0,80002c20 + 80002c4c: 0a500e93 li t4,165 + 80002c50: 00d00193 li gp,13 + 80002c54: 2fd31463 bne t1,t4,80002f3c + +0000000080002c58 : + 80002c58: 00000213 li tp,0 + 80002c5c: 00d0009b addiw ra,zero,13 + 80002c60: 02009093 slli ra,ra,0x20 + 80002c64: 00b0011b addiw sp,zero,11 + 80002c68: 02011113 slli sp,sp,0x20 + 80002c6c: 02209f33 mulh t5,ra,sp + 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c74: 00200293 li t0,2 + 80002c78: fe5212e3 bne tp,t0,80002c5c + 80002c7c: 08f00e93 li t4,143 + 80002c80: 00e00193 li gp,14 + 80002c84: 2bdf1c63 bne t5,t4,80002f3c + +0000000080002c88 : + 80002c88: 00000213 li tp,0 + 80002c8c: 0070009b addiw ra,zero,7 + 80002c90: 02109093 slli ra,ra,0x21 + 80002c94: 00b0011b addiw sp,zero,11 + 80002c98: 02011113 slli sp,sp,0x20 + 80002c9c: 00000013 nop + 80002ca0: 02209f33 mulh t5,ra,sp + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5210e3 bne tp,t0,80002c8c + 80002cb0: 09a00e93 li t4,154 + 80002cb4: 00f00193 li gp,15 + 80002cb8: 29df1263 bne t5,t4,80002f3c + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 00f0009b addiw ra,zero,15 + 80002cc4: 02009093 slli ra,ra,0x20 + 80002cc8: 00b0011b addiw sp,zero,11 + 80002ccc: 02011113 slli sp,sp,0x20 + 80002cd0: 00000013 nop + 80002cd4: 00000013 nop + 80002cd8: 02209f33 mulh t5,ra,sp + 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce0: 00200293 li t0,2 + 80002ce4: fc521ee3 bne tp,t0,80002cc0 + 80002ce8: 0a500e93 li t4,165 + 80002cec: 01000193 li gp,16 + 80002cf0: 25df1663 bne t5,t4,80002f3c + +0000000080002cf4 : + 80002cf4: 00000213 li tp,0 + 80002cf8: 00d0009b addiw ra,zero,13 + 80002cfc: 02009093 slli ra,ra,0x20 + 80002d00: 00000013 nop + 80002d04: 00b0011b addiw sp,zero,11 + 80002d08: 02011113 slli sp,sp,0x20 + 80002d0c: 02209f33 mulh t5,ra,sp + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fe5210e3 bne tp,t0,80002cf8 + 80002d1c: 08f00e93 li t4,143 + 80002d20: 01100193 li gp,17 + 80002d24: 21df1c63 bne t5,t4,80002f3c + +0000000080002d28 : + 80002d28: 00000213 li tp,0 + 80002d2c: 0070009b addiw ra,zero,7 + 80002d30: 02109093 slli ra,ra,0x21 + 80002d34: 00000013 nop + 80002d38: 00b0011b addiw sp,zero,11 + 80002d3c: 02011113 slli sp,sp,0x20 + 80002d40: 00000013 nop + 80002d44: 02209f33 mulh t5,ra,sp + 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d4c: 00200293 li t0,2 + 80002d50: fc521ee3 bne tp,t0,80002d2c + 80002d54: 09a00e93 li t4,154 + 80002d58: 01200193 li gp,18 + 80002d5c: 1fdf1063 bne t5,t4,80002f3c + +0000000080002d60 : + 80002d60: 00000213 li tp,0 + 80002d64: 00f0009b addiw ra,zero,15 + 80002d68: 02009093 slli ra,ra,0x20 + 80002d6c: 00000013 nop + 80002d70: 00000013 nop + 80002d74: 00b0011b addiw sp,zero,11 + 80002d78: 02011113 slli sp,sp,0x20 + 80002d7c: 02209f33 mulh t5,ra,sp + 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d84: 00200293 li t0,2 + 80002d88: fc521ee3 bne tp,t0,80002d64 + 80002d8c: 0a500e93 li t4,165 + 80002d90: 01300193 li gp,19 + 80002d94: 1bdf1463 bne t5,t4,80002f3c + +0000000080002d98 : + 80002d98: 00000213 li tp,0 + 80002d9c: 00b0011b addiw sp,zero,11 + 80002da0: 02011113 slli sp,sp,0x20 + 80002da4: 00d0009b addiw ra,zero,13 + 80002da8: 02009093 slli ra,ra,0x20 + 80002dac: 02209f33 mulh t5,ra,sp + 80002db0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db4: 00200293 li t0,2 + 80002db8: fe5212e3 bne tp,t0,80002d9c + 80002dbc: 08f00e93 li t4,143 + 80002dc0: 01400193 li gp,20 + 80002dc4: 17df1c63 bne t5,t4,80002f3c + +0000000080002dc8 : + 80002dc8: 00000213 li tp,0 + 80002dcc: 00b0011b addiw sp,zero,11 + 80002dd0: 02011113 slli sp,sp,0x20 + 80002dd4: 0070009b addiw ra,zero,7 + 80002dd8: 02109093 slli ra,ra,0x21 + 80002ddc: 00000013 nop + 80002de0: 02209f33 mulh t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fe5210e3 bne tp,t0,80002dcc + 80002df0: 09a00e93 li t4,154 + 80002df4: 01500193 li gp,21 + 80002df8: 15df1263 bne t5,t4,80002f3c + +0000000080002dfc : + 80002dfc: 00000213 li tp,0 + 80002e00: 00b0011b addiw sp,zero,11 + 80002e04: 02011113 slli sp,sp,0x20 + 80002e08: 00f0009b addiw ra,zero,15 + 80002e0c: 02009093 slli ra,ra,0x20 + 80002e10: 00000013 nop + 80002e14: 00000013 nop + 80002e18: 02209f33 mulh t5,ra,sp + 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e20: 00200293 li t0,2 + 80002e24: fc521ee3 bne tp,t0,80002e00 + 80002e28: 0a500e93 li t4,165 + 80002e2c: 01600193 li gp,22 + 80002e30: 11df1663 bne t5,t4,80002f3c + +0000000080002e34 : + 80002e34: 00000213 li tp,0 + 80002e38: 00b0011b addiw sp,zero,11 + 80002e3c: 02011113 slli sp,sp,0x20 + 80002e40: 00000013 nop + 80002e44: 00d0009b addiw ra,zero,13 + 80002e48: 02009093 slli ra,ra,0x20 + 80002e4c: 02209f33 mulh t5,ra,sp + 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e54: 00200293 li t0,2 + 80002e58: fe5210e3 bne tp,t0,80002e38 + 80002e5c: 08f00e93 li t4,143 + 80002e60: 01700193 li gp,23 + 80002e64: 0ddf1c63 bne t5,t4,80002f3c + +0000000080002e68 : + 80002e68: 00000213 li tp,0 + 80002e6c: 00b0011b addiw sp,zero,11 + 80002e70: 02011113 slli sp,sp,0x20 + 80002e74: 00000013 nop + 80002e78: 0070009b addiw ra,zero,7 + 80002e7c: 02109093 slli ra,ra,0x21 + 80002e80: 00000013 nop + 80002e84: 02209f33 mulh t5,ra,sp + 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e8c: 00200293 li t0,2 + 80002e90: fc521ee3 bne tp,t0,80002e6c + 80002e94: 09a00e93 li t4,154 + 80002e98: 01800193 li gp,24 + 80002e9c: 0bdf1063 bne t5,t4,80002f3c + +0000000080002ea0 : + 80002ea0: 00000213 li tp,0 + 80002ea4: 00b0011b addiw sp,zero,11 + 80002ea8: 02011113 slli sp,sp,0x20 + 80002eac: 00000013 nop + 80002eb0: 00000013 nop + 80002eb4: 00f0009b addiw ra,zero,15 + 80002eb8: 02009093 slli ra,ra,0x20 + 80002ebc: 02209f33 mulh t5,ra,sp + 80002ec0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec4: 00200293 li t0,2 + 80002ec8: fc521ee3 bne tp,t0,80002ea4 + 80002ecc: 0a500e93 li t4,165 + 80002ed0: 01900193 li gp,25 + 80002ed4: 07df1463 bne t5,t4,80002f3c + +0000000080002ed8 : + 80002ed8: 01f0009b addiw ra,zero,31 + 80002edc: 02009093 slli ra,ra,0x20 + 80002ee0: 02101133 mulh sp,zero,ra + 80002ee4: 00000e93 li t4,0 + 80002ee8: 01a00193 li gp,26 + 80002eec: 05d11863 bne sp,t4,80002f3c + +0000000080002ef0 : + 80002ef0: 0010009b addiw ra,zero,1 + 80002ef4: 02509093 slli ra,ra,0x25 + 80002ef8: 02009133 mulh sp,ra,zero + 80002efc: 00000e93 li t4,0 + 80002f00: 01b00193 li gp,27 + 80002f04: 03d11c63 bne sp,t4,80002f3c + +0000000080002f08 : + 80002f08: 020010b3 mulh ra,zero,zero + 80002f0c: 00000e93 li t4,0 + 80002f10: 01c00193 li gp,28 + 80002f14: 03d09463 bne ra,t4,80002f3c + +0000000080002f18 : + 80002f18: 0210009b addiw ra,zero,33 + 80002f1c: 02009093 slli ra,ra,0x20 + 80002f20: 0110011b addiw sp,zero,17 + 80002f24: 02111113 slli sp,sp,0x21 + 80002f28: 02209033 mulh zero,ra,sp + 80002f2c: 00000e93 li t4,0 + 80002f30: 01d00193 li gp,29 + 80002f34: 01d01463 bne zero,t4,80002f3c + 80002f38: 00301a63 bne zero,gp,80002f4c + +0000000080002f3c : + 80002f3c: 00119513 slli a0,gp,0x1 + 80002f40: 00050063 beqz a0,80002f40 + 80002f44: 00156513 ori a0,a0,1 + 80002f48: 00000073 ecall + +0000000080002f4c : + 80002f4c: 00100513 li a0,1 + 80002f50: 00000073 ecall + 80002f54: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulh.elf b/test/riscv/tests/rv64um-v-mulh.elf new file mode 100644 index 00000000..a644ac43 Binary files /dev/null and b/test/riscv/tests/rv64um-v-mulh.elf differ diff --git a/test/riscv/tests/rv64um-v-mulhsu.dump b/test/riscv/tests/rv64um-v-mulhsu.dump new file mode 100644 index 00000000..061224b6 --- /dev/null +++ b/test/riscv/tests/rv64um-v-mulhsu.dump @@ -0,0 +1,1179 @@ + +rv64um-v-mulhsu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b0068693 addi a3,a3,-1280 # 80002f58 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: b3460613 addi a2,a2,-1228 # 80002fe8 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: afc60613 addi a2,a2,-1284 # 80003000 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: a4c68693 addi a3,a3,-1460 # 80002fa0 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: a6868693 addi a3,a3,-1432 # 800030d8 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 9e860613 addi a2,a2,-1560 # 800030b0 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 91c68693 addi a3,a3,-1764 # 80003108 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 83c68693 addi a3,a3,-1988 # 80003078 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 7cc68693 addi a3,a3,1996 # 80003040 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 01000793 li a5,16 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 09a677b7 lui a5,0x9a67 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: d4078793 addi a5,a5,-704 # 9a66d40 <_start-0x765992c0> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 0220af33 mulhsu t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 47df1063 bne t5,t4,80002f3c + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0220af33 mulhsu t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 45df1463 bne t5,t4,80002f3c + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 0220af33 mulhsu t5,ra,sp + 80002b04: 00000e93 li t4,0 + 80002b08: 00400193 li gp,4 + 80002b0c: 43df1863 bne t5,t4,80002f3c + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 0220af33 mulhsu t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 41df1c63 bne t5,t4,80002f3c + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 0220af33 mulhsu t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 41df1063 bne t5,t4,80002f3c + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 0220af33 mulhsu t5,ra,sp + 80002b4c: 80000eb7 lui t4,0x80000 + 80002b50: 00700193 li gp,7 + 80002b54: 3fdf1463 bne t5,t4,80002f3c + +0000000080002b58 : + 80002b58: 00d0009b addiw ra,zero,13 + 80002b5c: 02009093 slli ra,ra,0x20 + 80002b60: 00b0011b addiw sp,zero,11 + 80002b64: 02011113 slli sp,sp,0x20 + 80002b68: 0220a0b3 mulhsu ra,ra,sp + 80002b6c: 08f00e93 li t4,143 + 80002b70: 00800193 li gp,8 + 80002b74: 3dd09463 bne ra,t4,80002f3c + +0000000080002b78 : + 80002b78: 0070009b addiw ra,zero,7 + 80002b7c: 02109093 slli ra,ra,0x21 + 80002b80: 00b0011b addiw sp,zero,11 + 80002b84: 02011113 slli sp,sp,0x20 + 80002b88: 0220a133 mulhsu sp,ra,sp + 80002b8c: 09a00e93 li t4,154 + 80002b90: 00900193 li gp,9 + 80002b94: 3bd11463 bne sp,t4,80002f3c + +0000000080002b98 : + 80002b98: 00d0009b addiw ra,zero,13 + 80002b9c: 02009093 slli ra,ra,0x20 + 80002ba0: 0210a0b3 mulhsu ra,ra,ra + 80002ba4: 0a900e93 li t4,169 + 80002ba8: 00a00193 li gp,10 + 80002bac: 39d09863 bne ra,t4,80002f3c + +0000000080002bb0 : + 80002bb0: 00000213 li tp,0 + 80002bb4: 00d0009b addiw ra,zero,13 + 80002bb8: 02009093 slli ra,ra,0x20 + 80002bbc: 00b0011b addiw sp,zero,11 + 80002bc0: 02011113 slli sp,sp,0x20 + 80002bc4: 0220af33 mulhsu t5,ra,sp + 80002bc8: 000f0313 mv t1,t5 + 80002bcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bd0: 00200293 li t0,2 + 80002bd4: fe5210e3 bne tp,t0,80002bb4 + 80002bd8: 08f00e93 li t4,143 + 80002bdc: 00b00193 li gp,11 + 80002be0: 35d31e63 bne t1,t4,80002f3c + +0000000080002be4 : + 80002be4: 00000213 li tp,0 + 80002be8: 0070009b addiw ra,zero,7 + 80002bec: 02109093 slli ra,ra,0x21 + 80002bf0: 00b0011b addiw sp,zero,11 + 80002bf4: 02011113 slli sp,sp,0x20 + 80002bf8: 0220af33 mulhsu t5,ra,sp + 80002bfc: 00000013 nop + 80002c00: 000f0313 mv t1,t5 + 80002c04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c08: 00200293 li t0,2 + 80002c0c: fc521ee3 bne tp,t0,80002be8 + 80002c10: 09a00e93 li t4,154 + 80002c14: 00c00193 li gp,12 + 80002c18: 33d31263 bne t1,t4,80002f3c + +0000000080002c1c : + 80002c1c: 00000213 li tp,0 + 80002c20: 00f0009b addiw ra,zero,15 + 80002c24: 02009093 slli ra,ra,0x20 + 80002c28: 00b0011b addiw sp,zero,11 + 80002c2c: 02011113 slli sp,sp,0x20 + 80002c30: 0220af33 mulhsu t5,ra,sp + 80002c34: 00000013 nop + 80002c38: 00000013 nop + 80002c3c: 000f0313 mv t1,t5 + 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c44: 00200293 li t0,2 + 80002c48: fc521ce3 bne tp,t0,80002c20 + 80002c4c: 0a500e93 li t4,165 + 80002c50: 00d00193 li gp,13 + 80002c54: 2fd31463 bne t1,t4,80002f3c + +0000000080002c58 : + 80002c58: 00000213 li tp,0 + 80002c5c: 00d0009b addiw ra,zero,13 + 80002c60: 02009093 slli ra,ra,0x20 + 80002c64: 00b0011b addiw sp,zero,11 + 80002c68: 02011113 slli sp,sp,0x20 + 80002c6c: 0220af33 mulhsu t5,ra,sp + 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c74: 00200293 li t0,2 + 80002c78: fe5212e3 bne tp,t0,80002c5c + 80002c7c: 08f00e93 li t4,143 + 80002c80: 00e00193 li gp,14 + 80002c84: 2bdf1c63 bne t5,t4,80002f3c + +0000000080002c88 : + 80002c88: 00000213 li tp,0 + 80002c8c: 0070009b addiw ra,zero,7 + 80002c90: 02109093 slli ra,ra,0x21 + 80002c94: 00b0011b addiw sp,zero,11 + 80002c98: 02011113 slli sp,sp,0x20 + 80002c9c: 00000013 nop + 80002ca0: 0220af33 mulhsu t5,ra,sp + 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ca8: 00200293 li t0,2 + 80002cac: fe5210e3 bne tp,t0,80002c8c + 80002cb0: 09a00e93 li t4,154 + 80002cb4: 00f00193 li gp,15 + 80002cb8: 29df1263 bne t5,t4,80002f3c + +0000000080002cbc : + 80002cbc: 00000213 li tp,0 + 80002cc0: 00f0009b addiw ra,zero,15 + 80002cc4: 02009093 slli ra,ra,0x20 + 80002cc8: 00b0011b addiw sp,zero,11 + 80002ccc: 02011113 slli sp,sp,0x20 + 80002cd0: 00000013 nop + 80002cd4: 00000013 nop + 80002cd8: 0220af33 mulhsu t5,ra,sp + 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ce0: 00200293 li t0,2 + 80002ce4: fc521ee3 bne tp,t0,80002cc0 + 80002ce8: 0a500e93 li t4,165 + 80002cec: 01000193 li gp,16 + 80002cf0: 25df1663 bne t5,t4,80002f3c + +0000000080002cf4 : + 80002cf4: 00000213 li tp,0 + 80002cf8: 00d0009b addiw ra,zero,13 + 80002cfc: 02009093 slli ra,ra,0x20 + 80002d00: 00000013 nop + 80002d04: 00b0011b addiw sp,zero,11 + 80002d08: 02011113 slli sp,sp,0x20 + 80002d0c: 0220af33 mulhsu t5,ra,sp + 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d14: 00200293 li t0,2 + 80002d18: fe5210e3 bne tp,t0,80002cf8 + 80002d1c: 08f00e93 li t4,143 + 80002d20: 01100193 li gp,17 + 80002d24: 21df1c63 bne t5,t4,80002f3c + +0000000080002d28 : + 80002d28: 00000213 li tp,0 + 80002d2c: 0070009b addiw ra,zero,7 + 80002d30: 02109093 slli ra,ra,0x21 + 80002d34: 00000013 nop + 80002d38: 00b0011b addiw sp,zero,11 + 80002d3c: 02011113 slli sp,sp,0x20 + 80002d40: 00000013 nop + 80002d44: 0220af33 mulhsu t5,ra,sp + 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d4c: 00200293 li t0,2 + 80002d50: fc521ee3 bne tp,t0,80002d2c + 80002d54: 09a00e93 li t4,154 + 80002d58: 01200193 li gp,18 + 80002d5c: 1fdf1063 bne t5,t4,80002f3c + +0000000080002d60 : + 80002d60: 00000213 li tp,0 + 80002d64: 00f0009b addiw ra,zero,15 + 80002d68: 02009093 slli ra,ra,0x20 + 80002d6c: 00000013 nop + 80002d70: 00000013 nop + 80002d74: 00b0011b addiw sp,zero,11 + 80002d78: 02011113 slli sp,sp,0x20 + 80002d7c: 0220af33 mulhsu t5,ra,sp + 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d84: 00200293 li t0,2 + 80002d88: fc521ee3 bne tp,t0,80002d64 + 80002d8c: 0a500e93 li t4,165 + 80002d90: 01300193 li gp,19 + 80002d94: 1bdf1463 bne t5,t4,80002f3c + +0000000080002d98 : + 80002d98: 00000213 li tp,0 + 80002d9c: 00b0011b addiw sp,zero,11 + 80002da0: 02011113 slli sp,sp,0x20 + 80002da4: 00d0009b addiw ra,zero,13 + 80002da8: 02009093 slli ra,ra,0x20 + 80002dac: 0220af33 mulhsu t5,ra,sp + 80002db0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002db4: 00200293 li t0,2 + 80002db8: fe5212e3 bne tp,t0,80002d9c + 80002dbc: 08f00e93 li t4,143 + 80002dc0: 01400193 li gp,20 + 80002dc4: 17df1c63 bne t5,t4,80002f3c + +0000000080002dc8 : + 80002dc8: 00000213 li tp,0 + 80002dcc: 00b0011b addiw sp,zero,11 + 80002dd0: 02011113 slli sp,sp,0x20 + 80002dd4: 0070009b addiw ra,zero,7 + 80002dd8: 02109093 slli ra,ra,0x21 + 80002ddc: 00000013 nop + 80002de0: 0220af33 mulhsu t5,ra,sp + 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002de8: 00200293 li t0,2 + 80002dec: fe5210e3 bne tp,t0,80002dcc + 80002df0: 09a00e93 li t4,154 + 80002df4: 01500193 li gp,21 + 80002df8: 15df1263 bne t5,t4,80002f3c + +0000000080002dfc : + 80002dfc: 00000213 li tp,0 + 80002e00: 00b0011b addiw sp,zero,11 + 80002e04: 02011113 slli sp,sp,0x20 + 80002e08: 00f0009b addiw ra,zero,15 + 80002e0c: 02009093 slli ra,ra,0x20 + 80002e10: 00000013 nop + 80002e14: 00000013 nop + 80002e18: 0220af33 mulhsu t5,ra,sp + 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e20: 00200293 li t0,2 + 80002e24: fc521ee3 bne tp,t0,80002e00 + 80002e28: 0a500e93 li t4,165 + 80002e2c: 01600193 li gp,22 + 80002e30: 11df1663 bne t5,t4,80002f3c + +0000000080002e34 : + 80002e34: 00000213 li tp,0 + 80002e38: 00b0011b addiw sp,zero,11 + 80002e3c: 02011113 slli sp,sp,0x20 + 80002e40: 00000013 nop + 80002e44: 00d0009b addiw ra,zero,13 + 80002e48: 02009093 slli ra,ra,0x20 + 80002e4c: 0220af33 mulhsu t5,ra,sp + 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e54: 00200293 li t0,2 + 80002e58: fe5210e3 bne tp,t0,80002e38 + 80002e5c: 08f00e93 li t4,143 + 80002e60: 01700193 li gp,23 + 80002e64: 0ddf1c63 bne t5,t4,80002f3c + +0000000080002e68 : + 80002e68: 00000213 li tp,0 + 80002e6c: 00b0011b addiw sp,zero,11 + 80002e70: 02011113 slli sp,sp,0x20 + 80002e74: 00000013 nop + 80002e78: 0070009b addiw ra,zero,7 + 80002e7c: 02109093 slli ra,ra,0x21 + 80002e80: 00000013 nop + 80002e84: 0220af33 mulhsu t5,ra,sp + 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e8c: 00200293 li t0,2 + 80002e90: fc521ee3 bne tp,t0,80002e6c + 80002e94: 09a00e93 li t4,154 + 80002e98: 01800193 li gp,24 + 80002e9c: 0bdf1063 bne t5,t4,80002f3c + +0000000080002ea0 : + 80002ea0: 00000213 li tp,0 + 80002ea4: 00b0011b addiw sp,zero,11 + 80002ea8: 02011113 slli sp,sp,0x20 + 80002eac: 00000013 nop + 80002eb0: 00000013 nop + 80002eb4: 00f0009b addiw ra,zero,15 + 80002eb8: 02009093 slli ra,ra,0x20 + 80002ebc: 0220af33 mulhsu t5,ra,sp + 80002ec0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ec4: 00200293 li t0,2 + 80002ec8: fc521ee3 bne tp,t0,80002ea4 + 80002ecc: 0a500e93 li t4,165 + 80002ed0: 01900193 li gp,25 + 80002ed4: 07df1463 bne t5,t4,80002f3c + +0000000080002ed8 : + 80002ed8: 01f0009b addiw ra,zero,31 + 80002edc: 02009093 slli ra,ra,0x20 + 80002ee0: 02102133 mulhsu sp,zero,ra + 80002ee4: 00000e93 li t4,0 + 80002ee8: 01a00193 li gp,26 + 80002eec: 05d11863 bne sp,t4,80002f3c + +0000000080002ef0 : + 80002ef0: 0010009b addiw ra,zero,1 + 80002ef4: 02509093 slli ra,ra,0x25 + 80002ef8: 0200a133 mulhsu sp,ra,zero + 80002efc: 00000e93 li t4,0 + 80002f00: 01b00193 li gp,27 + 80002f04: 03d11c63 bne sp,t4,80002f3c + +0000000080002f08 : + 80002f08: 020020b3 mulhsu ra,zero,zero + 80002f0c: 00000e93 li t4,0 + 80002f10: 01c00193 li gp,28 + 80002f14: 03d09463 bne ra,t4,80002f3c + +0000000080002f18 : + 80002f18: 0210009b addiw ra,zero,33 + 80002f1c: 02009093 slli ra,ra,0x20 + 80002f20: 0110011b addiw sp,zero,17 + 80002f24: 02111113 slli sp,sp,0x21 + 80002f28: 0220a033 mulhsu zero,ra,sp + 80002f2c: 00000e93 li t4,0 + 80002f30: 01d00193 li gp,29 + 80002f34: 01d01463 bne zero,t4,80002f3c + 80002f38: 00301a63 bne zero,gp,80002f4c + +0000000080002f3c : + 80002f3c: 00119513 slli a0,gp,0x1 + 80002f40: 00050063 beqz a0,80002f40 + 80002f44: 00156513 ori a0,a0,1 + 80002f48: 00000073 ecall + +0000000080002f4c : + 80002f4c: 00100513 li a0,1 + 80002f50: 00000073 ecall + 80002f54: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulhsu.elf b/test/riscv/tests/rv64um-v-mulhsu.elf new file mode 100644 index 00000000..a8afeaa1 Binary files /dev/null and b/test/riscv/tests/rv64um-v-mulhsu.elf differ diff --git a/test/riscv/tests/rv64um-v-mulhu.dump b/test/riscv/tests/rv64um-v-mulhu.dump new file mode 100644 index 00000000..85b66d05 --- /dev/null +++ b/test/riscv/tests/rv64um-v-mulhu.dump @@ -0,0 +1,1215 @@ + +rv64um-v-mulhu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: b8068693 addi a3,a3,-1152 # 80002fd8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: bb460613 addi a2,a2,-1100 # 80003068 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: b7c60613 addi a2,a2,-1156 # 80003080 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: acc68693 addi a3,a3,-1332 # 80003020 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: ae868693 addi a3,a3,-1304 # 80003158 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: a6860613 addi a2,a2,-1432 # 80003130 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 99c68693 addi a3,a3,-1636 # 80003188 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00001697 auipc a3,0x1 + 80002840: 8bc68693 addi a3,a3,-1860 # 800030f8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00001697 auipc a3,0x1 + 80002878: 84c68693 addi a3,a3,-1972 # 800030c0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 03200793 li a5,50 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0c0917b7 lui a5,0xc091 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 24978793 addi a5,a5,585 # c091249 <_start-0x73f6edb7> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 0220bf33 mulhu t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 4fdf1063 bne t5,t4,80002fbc + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 0220bf33 mulhu t5,ra,sp + 80002aec: 00000e93 li t4,0 + 80002af0: 00300193 li gp,3 + 80002af4: 4ddf1463 bne t5,t4,80002fbc + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 0220bf33 mulhu t5,ra,sp + 80002b04: 00000e93 li t4,0 + 80002b08: 00400193 li gp,4 + 80002b0c: 4bdf1863 bne t5,t4,80002fbc + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 0220bf33 mulhu t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 49df1c63 bne t5,t4,80002fbc + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 0220bf33 mulhu t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 49df1063 bne t5,t4,80002fbc + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 0220bf33 mulhu t5,ra,sp + 80002b4c: ffff0eb7 lui t4,0xffff0 + 80002b50: fffe8e9b addiw t4,t4,-1 + 80002b54: 00fe9e93 slli t4,t4,0xf + 80002b58: 00700193 li gp,7 + 80002b5c: 47df1063 bne t5,t4,80002fbc + +0000000080002b60 : + 80002b60: faaab0b7 lui ra,0xfaaab + 80002b64: aab0809b addiw ra,ra,-1365 + 80002b68: 00c09093 slli ra,ra,0xc + 80002b6c: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> + 80002b70: 00c09093 slli ra,ra,0xc + 80002b74: aab08093 addi ra,ra,-1365 + 80002b78: 00c09093 slli ra,ra,0xc + 80002b7c: aab08093 addi ra,ra,-1365 + 80002b80: 00030137 lui sp,0x30 + 80002b84: e7d1011b addiw sp,sp,-387 + 80002b88: 0220bf33 mulhu t5,ra,sp + 80002b8c: 00020eb7 lui t4,0x20 + 80002b90: efee8e9b addiw t4,t4,-258 + 80002b94: 01e00193 li gp,30 + 80002b98: 43df1263 bne t5,t4,80002fbc + +0000000080002b9c : + 80002b9c: 000300b7 lui ra,0x30 + 80002ba0: e7d0809b addiw ra,ra,-387 + 80002ba4: faaab137 lui sp,0xfaaab + 80002ba8: aab1011b addiw sp,sp,-1365 + 80002bac: 00c11113 slli sp,sp,0xc + 80002bb0: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> + 80002bb4: 00c11113 slli sp,sp,0xc + 80002bb8: aab10113 addi sp,sp,-1365 + 80002bbc: 00c11113 slli sp,sp,0xc + 80002bc0: aab10113 addi sp,sp,-1365 + 80002bc4: 0220bf33 mulhu t5,ra,sp + 80002bc8: 00020eb7 lui t4,0x20 + 80002bcc: efee8e9b addiw t4,t4,-258 + 80002bd0: 01f00193 li gp,31 + 80002bd4: 3fdf1463 bne t5,t4,80002fbc + +0000000080002bd8 : + 80002bd8: 00d0009b addiw ra,zero,13 + 80002bdc: 02009093 slli ra,ra,0x20 + 80002be0: 00b0011b addiw sp,zero,11 + 80002be4: 02011113 slli sp,sp,0x20 + 80002be8: 0220b0b3 mulhu ra,ra,sp + 80002bec: 08f00e93 li t4,143 + 80002bf0: 00800193 li gp,8 + 80002bf4: 3dd09463 bne ra,t4,80002fbc + +0000000080002bf8 : + 80002bf8: 0070009b addiw ra,zero,7 + 80002bfc: 02109093 slli ra,ra,0x21 + 80002c00: 00b0011b addiw sp,zero,11 + 80002c04: 02011113 slli sp,sp,0x20 + 80002c08: 0220b133 mulhu sp,ra,sp + 80002c0c: 09a00e93 li t4,154 + 80002c10: 00900193 li gp,9 + 80002c14: 3bd11463 bne sp,t4,80002fbc + +0000000080002c18 : + 80002c18: 00d0009b addiw ra,zero,13 + 80002c1c: 02009093 slli ra,ra,0x20 + 80002c20: 0210b0b3 mulhu ra,ra,ra + 80002c24: 0a900e93 li t4,169 + 80002c28: 00a00193 li gp,10 + 80002c2c: 39d09863 bne ra,t4,80002fbc + +0000000080002c30 : + 80002c30: 00000213 li tp,0 + 80002c34: 00d0009b addiw ra,zero,13 + 80002c38: 02009093 slli ra,ra,0x20 + 80002c3c: 00b0011b addiw sp,zero,11 + 80002c40: 02011113 slli sp,sp,0x20 + 80002c44: 0220bf33 mulhu t5,ra,sp + 80002c48: 000f0313 mv t1,t5 + 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c50: 00200293 li t0,2 + 80002c54: fe5210e3 bne tp,t0,80002c34 + 80002c58: 08f00e93 li t4,143 + 80002c5c: 00b00193 li gp,11 + 80002c60: 35d31e63 bne t1,t4,80002fbc + +0000000080002c64 : + 80002c64: 00000213 li tp,0 + 80002c68: 0070009b addiw ra,zero,7 + 80002c6c: 02109093 slli ra,ra,0x21 + 80002c70: 00b0011b addiw sp,zero,11 + 80002c74: 02011113 slli sp,sp,0x20 + 80002c78: 0220bf33 mulhu t5,ra,sp + 80002c7c: 00000013 nop + 80002c80: 000f0313 mv t1,t5 + 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c88: 00200293 li t0,2 + 80002c8c: fc521ee3 bne tp,t0,80002c68 + 80002c90: 09a00e93 li t4,154 + 80002c94: 00c00193 li gp,12 + 80002c98: 33d31263 bne t1,t4,80002fbc + +0000000080002c9c : + 80002c9c: 00000213 li tp,0 + 80002ca0: 00f0009b addiw ra,zero,15 + 80002ca4: 02009093 slli ra,ra,0x20 + 80002ca8: 00b0011b addiw sp,zero,11 + 80002cac: 02011113 slli sp,sp,0x20 + 80002cb0: 0220bf33 mulhu t5,ra,sp + 80002cb4: 00000013 nop + 80002cb8: 00000013 nop + 80002cbc: 000f0313 mv t1,t5 + 80002cc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc4: 00200293 li t0,2 + 80002cc8: fc521ce3 bne tp,t0,80002ca0 + 80002ccc: 0a500e93 li t4,165 + 80002cd0: 00d00193 li gp,13 + 80002cd4: 2fd31463 bne t1,t4,80002fbc + +0000000080002cd8 : + 80002cd8: 00000213 li tp,0 + 80002cdc: 00d0009b addiw ra,zero,13 + 80002ce0: 02009093 slli ra,ra,0x20 + 80002ce4: 00b0011b addiw sp,zero,11 + 80002ce8: 02011113 slli sp,sp,0x20 + 80002cec: 0220bf33 mulhu t5,ra,sp + 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf4: 00200293 li t0,2 + 80002cf8: fe5212e3 bne tp,t0,80002cdc + 80002cfc: 08f00e93 li t4,143 + 80002d00: 00e00193 li gp,14 + 80002d04: 2bdf1c63 bne t5,t4,80002fbc + +0000000080002d08 : + 80002d08: 00000213 li tp,0 + 80002d0c: 0070009b addiw ra,zero,7 + 80002d10: 02109093 slli ra,ra,0x21 + 80002d14: 00b0011b addiw sp,zero,11 + 80002d18: 02011113 slli sp,sp,0x20 + 80002d1c: 00000013 nop + 80002d20: 0220bf33 mulhu t5,ra,sp + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5210e3 bne tp,t0,80002d0c + 80002d30: 09a00e93 li t4,154 + 80002d34: 00f00193 li gp,15 + 80002d38: 29df1263 bne t5,t4,80002fbc + +0000000080002d3c : + 80002d3c: 00000213 li tp,0 + 80002d40: 00f0009b addiw ra,zero,15 + 80002d44: 02009093 slli ra,ra,0x20 + 80002d48: 00b0011b addiw sp,zero,11 + 80002d4c: 02011113 slli sp,sp,0x20 + 80002d50: 00000013 nop + 80002d54: 00000013 nop + 80002d58: 0220bf33 mulhu t5,ra,sp + 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d60: 00200293 li t0,2 + 80002d64: fc521ee3 bne tp,t0,80002d40 + 80002d68: 0a500e93 li t4,165 + 80002d6c: 01000193 li gp,16 + 80002d70: 25df1663 bne t5,t4,80002fbc + +0000000080002d74 : + 80002d74: 00000213 li tp,0 + 80002d78: 00d0009b addiw ra,zero,13 + 80002d7c: 02009093 slli ra,ra,0x20 + 80002d80: 00000013 nop + 80002d84: 00b0011b addiw sp,zero,11 + 80002d88: 02011113 slli sp,sp,0x20 + 80002d8c: 0220bf33 mulhu t5,ra,sp + 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d94: 00200293 li t0,2 + 80002d98: fe5210e3 bne tp,t0,80002d78 + 80002d9c: 08f00e93 li t4,143 + 80002da0: 01100193 li gp,17 + 80002da4: 21df1c63 bne t5,t4,80002fbc + +0000000080002da8 : + 80002da8: 00000213 li tp,0 + 80002dac: 0070009b addiw ra,zero,7 + 80002db0: 02109093 slli ra,ra,0x21 + 80002db4: 00000013 nop + 80002db8: 00b0011b addiw sp,zero,11 + 80002dbc: 02011113 slli sp,sp,0x20 + 80002dc0: 00000013 nop + 80002dc4: 0220bf33 mulhu t5,ra,sp + 80002dc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dcc: 00200293 li t0,2 + 80002dd0: fc521ee3 bne tp,t0,80002dac + 80002dd4: 09a00e93 li t4,154 + 80002dd8: 01200193 li gp,18 + 80002ddc: 1fdf1063 bne t5,t4,80002fbc + +0000000080002de0 : + 80002de0: 00000213 li tp,0 + 80002de4: 00f0009b addiw ra,zero,15 + 80002de8: 02009093 slli ra,ra,0x20 + 80002dec: 00000013 nop + 80002df0: 00000013 nop + 80002df4: 00b0011b addiw sp,zero,11 + 80002df8: 02011113 slli sp,sp,0x20 + 80002dfc: 0220bf33 mulhu t5,ra,sp + 80002e00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e04: 00200293 li t0,2 + 80002e08: fc521ee3 bne tp,t0,80002de4 + 80002e0c: 0a500e93 li t4,165 + 80002e10: 01300193 li gp,19 + 80002e14: 1bdf1463 bne t5,t4,80002fbc + +0000000080002e18 : + 80002e18: 00000213 li tp,0 + 80002e1c: 00b0011b addiw sp,zero,11 + 80002e20: 02011113 slli sp,sp,0x20 + 80002e24: 00d0009b addiw ra,zero,13 + 80002e28: 02009093 slli ra,ra,0x20 + 80002e2c: 0220bf33 mulhu t5,ra,sp + 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e34: 00200293 li t0,2 + 80002e38: fe5212e3 bne tp,t0,80002e1c + 80002e3c: 08f00e93 li t4,143 + 80002e40: 01400193 li gp,20 + 80002e44: 17df1c63 bne t5,t4,80002fbc + +0000000080002e48 : + 80002e48: 00000213 li tp,0 + 80002e4c: 00b0011b addiw sp,zero,11 + 80002e50: 02011113 slli sp,sp,0x20 + 80002e54: 0070009b addiw ra,zero,7 + 80002e58: 02109093 slli ra,ra,0x21 + 80002e5c: 00000013 nop + 80002e60: 0220bf33 mulhu t5,ra,sp + 80002e64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e68: 00200293 li t0,2 + 80002e6c: fe5210e3 bne tp,t0,80002e4c + 80002e70: 09a00e93 li t4,154 + 80002e74: 01500193 li gp,21 + 80002e78: 15df1263 bne t5,t4,80002fbc + +0000000080002e7c : + 80002e7c: 00000213 li tp,0 + 80002e80: 00b0011b addiw sp,zero,11 + 80002e84: 02011113 slli sp,sp,0x20 + 80002e88: 00f0009b addiw ra,zero,15 + 80002e8c: 02009093 slli ra,ra,0x20 + 80002e90: 00000013 nop + 80002e94: 00000013 nop + 80002e98: 0220bf33 mulhu t5,ra,sp + 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ea0: 00200293 li t0,2 + 80002ea4: fc521ee3 bne tp,t0,80002e80 + 80002ea8: 0a500e93 li t4,165 + 80002eac: 01600193 li gp,22 + 80002eb0: 11df1663 bne t5,t4,80002fbc + +0000000080002eb4 : + 80002eb4: 00000213 li tp,0 + 80002eb8: 00b0011b addiw sp,zero,11 + 80002ebc: 02011113 slli sp,sp,0x20 + 80002ec0: 00000013 nop + 80002ec4: 00d0009b addiw ra,zero,13 + 80002ec8: 02009093 slli ra,ra,0x20 + 80002ecc: 0220bf33 mulhu t5,ra,sp + 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002ed4: 00200293 li t0,2 + 80002ed8: fe5210e3 bne tp,t0,80002eb8 + 80002edc: 08f00e93 li t4,143 + 80002ee0: 01700193 li gp,23 + 80002ee4: 0ddf1c63 bne t5,t4,80002fbc + +0000000080002ee8 : + 80002ee8: 00000213 li tp,0 + 80002eec: 00b0011b addiw sp,zero,11 + 80002ef0: 02011113 slli sp,sp,0x20 + 80002ef4: 00000013 nop + 80002ef8: 0070009b addiw ra,zero,7 + 80002efc: 02109093 slli ra,ra,0x21 + 80002f00: 00000013 nop + 80002f04: 0220bf33 mulhu t5,ra,sp + 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f0c: 00200293 li t0,2 + 80002f10: fc521ee3 bne tp,t0,80002eec + 80002f14: 09a00e93 li t4,154 + 80002f18: 01800193 li gp,24 + 80002f1c: 0bdf1063 bne t5,t4,80002fbc + +0000000080002f20 : + 80002f20: 00000213 li tp,0 + 80002f24: 00b0011b addiw sp,zero,11 + 80002f28: 02011113 slli sp,sp,0x20 + 80002f2c: 00000013 nop + 80002f30: 00000013 nop + 80002f34: 00f0009b addiw ra,zero,15 + 80002f38: 02009093 slli ra,ra,0x20 + 80002f3c: 0220bf33 mulhu t5,ra,sp + 80002f40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002f44: 00200293 li t0,2 + 80002f48: fc521ee3 bne tp,t0,80002f24 + 80002f4c: 0a500e93 li t4,165 + 80002f50: 01900193 li gp,25 + 80002f54: 07df1463 bne t5,t4,80002fbc + +0000000080002f58 : + 80002f58: 01f0009b addiw ra,zero,31 + 80002f5c: 02009093 slli ra,ra,0x20 + 80002f60: 02103133 mulhu sp,zero,ra + 80002f64: 00000e93 li t4,0 + 80002f68: 01a00193 li gp,26 + 80002f6c: 05d11863 bne sp,t4,80002fbc + +0000000080002f70 : + 80002f70: 0010009b addiw ra,zero,1 + 80002f74: 02509093 slli ra,ra,0x25 + 80002f78: 0200b133 mulhu sp,ra,zero + 80002f7c: 00000e93 li t4,0 + 80002f80: 01b00193 li gp,27 + 80002f84: 03d11c63 bne sp,t4,80002fbc + +0000000080002f88 : + 80002f88: 020030b3 mulhu ra,zero,zero + 80002f8c: 00000e93 li t4,0 + 80002f90: 01c00193 li gp,28 + 80002f94: 03d09463 bne ra,t4,80002fbc + +0000000080002f98 : + 80002f98: 0210009b addiw ra,zero,33 + 80002f9c: 02009093 slli ra,ra,0x20 + 80002fa0: 0110011b addiw sp,zero,17 + 80002fa4: 02111113 slli sp,sp,0x21 + 80002fa8: 0220b033 mulhu zero,ra,sp + 80002fac: 00000e93 li t4,0 + 80002fb0: 01d00193 li gp,29 + 80002fb4: 01d01463 bne zero,t4,80002fbc + 80002fb8: 00301a63 bne zero,gp,80002fcc + +0000000080002fbc : + 80002fbc: 00119513 slli a0,gp,0x1 + 80002fc0: 00050063 beqz a0,80002fc0 + 80002fc4: 00156513 ori a0,a0,1 + 80002fc8: 00000073 ecall + +0000000080002fcc : + 80002fcc: 00100513 li a0,1 + 80002fd0: 00000073 ecall + 80002fd4: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulhu.elf b/test/riscv/tests/rv64um-v-mulhu.elf new file mode 100644 index 00000000..62759c83 Binary files /dev/null and b/test/riscv/tests/rv64um-v-mulhu.elf differ diff --git a/test/riscv/tests/rv64um-v-mulw.dump b/test/riscv/tests/rv64um-v-mulw.dump new file mode 100644 index 00000000..0d3598ff --- /dev/null +++ b/test/riscv/tests/rv64um-v-mulw.dump @@ -0,0 +1,1140 @@ + +rv64um-v-mulw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00009117 auipc sp,0x9 + 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00002617 auipc a2,0x2 + 80002318: cec60613 addi a2,a2,-788 # 80004000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00006797 auipc a5,0x6 + 80002334: 4b878793 addi a5,a5,1208 # 800087e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00006717 auipc a4,0x6 + 80002348: 49c70713 addi a4,a4,1180 # 800087e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00006897 auipc a7,0x6 + 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00006797 auipc a5,0x6 + 80002384: 07078793 addi a5,a5,112 # 800083f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00006797 auipc a5,0x6 + 80002448: 3807be23 sd zero,924(a5) # 800087e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00001697 auipc a3,0x1 + 8000245c: a6868693 addi a3,a3,-1432 # 80002ec0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00001617 auipc a2,0x1 + 800024b8: a9c60613 addi a2,a2,-1380 # 80002f50 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00001617 auipc a2,0x1 + 80002508: a6460613 addi a2,a2,-1436 # 80002f68 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00001697 auipc a3,0x1 + 80002558: 9b468693 addi a3,a3,-1612 # 80002f08 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00001697 auipc a3,0x1 + 80002674: 9d068693 addi a3,a3,-1584 # 80003040 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00001617 auipc a2,0x1 + 800026cc: 95060613 addi a2,a2,-1712 # 80003018 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00006d17 auipc s10,0x6 + 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 + 80002724: 00002b97 auipc s7,0x2 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00006a17 auipc s4,0x6 + 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00006717 auipc a4,0x6 + 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00006717 auipc a4,0x6 + 800027d4: 00f73823 sd a5,16(a4) # 800087e0 + 800027d8: 00006717 auipc a4,0x6 + 800027dc: 00f73823 sd a5,16(a4) # 800087e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00001697 auipc a3,0x1 + 800027f0: 88468693 addi a3,a3,-1916 # 80003070 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 7a468693 addi a3,a3,1956 # 80002fe0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 73468693 addi a3,a3,1844 # 80002fa8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00002697 auipc a3,0x2 + 800028e0: 72468693 addi a3,a3,1828 # 80005000 + 800028e4: 00003717 auipc a4,0x3 + 800028e8: 71c70713 addi a4,a4,1820 # 80006000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00004797 auipc a5,0x4 + 800028f8: 70c78793 addi a5,a5,1804 # 80007000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00001897 auipc a7,0x1 + 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00002697 auipc a3,0x2 + 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00001617 auipc a2,0x1 + 80002938: 6cc60613 addi a2,a2,1740 # 80004000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00004697 auipc a3,0x4 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 + 8000294c: 00002717 auipc a4,0x2 + 80002950: 6af73a23 sd a5,1716(a4) # 80005000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00005697 auipc a3,0x5 + 800029c0: 64468693 addi a3,a3,1604 # 80008000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00006617 auipc a2,0x6 + 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 + 800029d4: 00006797 auipc a5,0x6 + 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 + 800029dc: 00006317 auipc t1,0x6 + 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 + 800029e4: 01100793 li a5,17 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00006797 auipc a5,0x6 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0e99b7b7 lui a5,0xe99b + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 1b978793 addi a5,a5,441 # e99b1b9 <_start-0x71664e47> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 00000093 li ra,0 + 80002acc: 00000113 li sp,0 + 80002ad0: 02208f3b mulw t5,ra,sp + 80002ad4: 00000e93 li t4,0 + 80002ad8: 00200193 li gp,2 + 80002adc: 3ddf1263 bne t5,t4,80002ea0 + +0000000080002ae0 : + 80002ae0: 00100093 li ra,1 + 80002ae4: 00100113 li sp,1 + 80002ae8: 02208f3b mulw t5,ra,sp + 80002aec: 00100e93 li t4,1 + 80002af0: 00300193 li gp,3 + 80002af4: 3bdf1663 bne t5,t4,80002ea0 + +0000000080002af8 : + 80002af8: 00300093 li ra,3 + 80002afc: 00700113 li sp,7 + 80002b00: 02208f3b mulw t5,ra,sp + 80002b04: 01500e93 li t4,21 + 80002b08: 00400193 li gp,4 + 80002b0c: 39df1a63 bne t5,t4,80002ea0 + +0000000080002b10 : + 80002b10: 00000093 li ra,0 + 80002b14: ffff8137 lui sp,0xffff8 + 80002b18: 02208f3b mulw t5,ra,sp + 80002b1c: 00000e93 li t4,0 + 80002b20: 00500193 li gp,5 + 80002b24: 37df1e63 bne t5,t4,80002ea0 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00000113 li sp,0 + 80002b30: 02208f3b mulw t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 37df1263 bne t5,t4,80002ea0 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: ffff8137 lui sp,0xffff8 + 80002b48: 02208f3b mulw t5,ra,sp + 80002b4c: 00000e93 li t4,0 + 80002b50: 00700193 li gp,7 + 80002b54: 35df1663 bne t5,t4,80002ea0 + +0000000080002b58 : + 80002b58: 00d00093 li ra,13 + 80002b5c: 00b00113 li sp,11 + 80002b60: 022080bb mulw ra,ra,sp + 80002b64: 08f00e93 li t4,143 + 80002b68: 00800193 li gp,8 + 80002b6c: 33d09a63 bne ra,t4,80002ea0 + +0000000080002b70 : + 80002b70: 00e00093 li ra,14 + 80002b74: 00b00113 li sp,11 + 80002b78: 0220813b mulw sp,ra,sp + 80002b7c: 09a00e93 li t4,154 + 80002b80: 00900193 li gp,9 + 80002b84: 31d11e63 bne sp,t4,80002ea0 + +0000000080002b88 : + 80002b88: 00d00093 li ra,13 + 80002b8c: 021080bb mulw ra,ra,ra + 80002b90: 0a900e93 li t4,169 + 80002b94: 00a00193 li gp,10 + 80002b98: 31d09463 bne ra,t4,80002ea0 + +0000000080002b9c : + 80002b9c: 00000213 li tp,0 + 80002ba0: 00d00093 li ra,13 + 80002ba4: 00b00113 li sp,11 + 80002ba8: 02208f3b mulw t5,ra,sp + 80002bac: 000f0313 mv t1,t5 + 80002bb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002bb4: 00200293 li t0,2 + 80002bb8: fe5214e3 bne tp,t0,80002ba0 + 80002bbc: 08f00e93 li t4,143 + 80002bc0: 00b00193 li gp,11 + 80002bc4: 2dd31e63 bne t1,t4,80002ea0 + +0000000080002bc8 : + 80002bc8: 00000213 li tp,0 + 80002bcc: 00e00093 li ra,14 + 80002bd0: 00b00113 li sp,11 + 80002bd4: 02208f3b mulw t5,ra,sp + 80002bd8: 00000013 nop + 80002bdc: 000f0313 mv t1,t5 + 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002be4: 00200293 li t0,2 + 80002be8: fe5212e3 bne tp,t0,80002bcc + 80002bec: 09a00e93 li t4,154 + 80002bf0: 00c00193 li gp,12 + 80002bf4: 2bd31663 bne t1,t4,80002ea0 + +0000000080002bf8 : + 80002bf8: 00000213 li tp,0 + 80002bfc: 00f00093 li ra,15 + 80002c00: 00b00113 li sp,11 + 80002c04: 02208f3b mulw t5,ra,sp + 80002c08: 00000013 nop + 80002c0c: 00000013 nop + 80002c10: 000f0313 mv t1,t5 + 80002c14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c18: 00200293 li t0,2 + 80002c1c: fe5210e3 bne tp,t0,80002bfc + 80002c20: 0a500e93 li t4,165 + 80002c24: 00d00193 li gp,13 + 80002c28: 27d31c63 bne t1,t4,80002ea0 + +0000000080002c2c : + 80002c2c: 00000213 li tp,0 + 80002c30: 00d00093 li ra,13 + 80002c34: 00b00113 li sp,11 + 80002c38: 02208f3b mulw t5,ra,sp + 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c40: 00200293 li t0,2 + 80002c44: fe5216e3 bne tp,t0,80002c30 + 80002c48: 08f00e93 li t4,143 + 80002c4c: 00e00193 li gp,14 + 80002c50: 25df1863 bne t5,t4,80002ea0 + +0000000080002c54 : + 80002c54: 00000213 li tp,0 + 80002c58: 00e00093 li ra,14 + 80002c5c: 00b00113 li sp,11 + 80002c60: 00000013 nop + 80002c64: 02208f3b mulw t5,ra,sp + 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c6c: 00200293 li t0,2 + 80002c70: fe5214e3 bne tp,t0,80002c58 + 80002c74: 09a00e93 li t4,154 + 80002c78: 00f00193 li gp,15 + 80002c7c: 23df1263 bne t5,t4,80002ea0 + +0000000080002c80 : + 80002c80: 00000213 li tp,0 + 80002c84: 00f00093 li ra,15 + 80002c88: 00b00113 li sp,11 + 80002c8c: 00000013 nop + 80002c90: 00000013 nop + 80002c94: 02208f3b mulw t5,ra,sp + 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002c9c: 00200293 li t0,2 + 80002ca0: fe5212e3 bne tp,t0,80002c84 + 80002ca4: 0a500e93 li t4,165 + 80002ca8: 01000193 li gp,16 + 80002cac: 1fdf1a63 bne t5,t4,80002ea0 + +0000000080002cb0 : + 80002cb0: 00000213 li tp,0 + 80002cb4: 00d00093 li ra,13 + 80002cb8: 00000013 nop + 80002cbc: 00b00113 li sp,11 + 80002cc0: 02208f3b mulw t5,ra,sp + 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cc8: 00200293 li t0,2 + 80002ccc: fe5214e3 bne tp,t0,80002cb4 + 80002cd0: 08f00e93 li t4,143 + 80002cd4: 01100193 li gp,17 + 80002cd8: 1ddf1463 bne t5,t4,80002ea0 + +0000000080002cdc : + 80002cdc: 00000213 li tp,0 + 80002ce0: 00e00093 li ra,14 + 80002ce4: 00000013 nop + 80002ce8: 00b00113 li sp,11 + 80002cec: 00000013 nop + 80002cf0: 02208f3b mulw t5,ra,sp + 80002cf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002cf8: 00200293 li t0,2 + 80002cfc: fe5212e3 bne tp,t0,80002ce0 + 80002d00: 09a00e93 li t4,154 + 80002d04: 01200193 li gp,18 + 80002d08: 19df1c63 bne t5,t4,80002ea0 + +0000000080002d0c : + 80002d0c: 00000213 li tp,0 + 80002d10: 00f00093 li ra,15 + 80002d14: 00000013 nop + 80002d18: 00000013 nop + 80002d1c: 00b00113 li sp,11 + 80002d20: 02208f3b mulw t5,ra,sp + 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d28: 00200293 li t0,2 + 80002d2c: fe5212e3 bne tp,t0,80002d10 + 80002d30: 0a500e93 li t4,165 + 80002d34: 01300193 li gp,19 + 80002d38: 17df1463 bne t5,t4,80002ea0 + +0000000080002d3c : + 80002d3c: 00000213 li tp,0 + 80002d40: 00b00113 li sp,11 + 80002d44: 00d00093 li ra,13 + 80002d48: 02208f3b mulw t5,ra,sp + 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d50: 00200293 li t0,2 + 80002d54: fe5216e3 bne tp,t0,80002d40 + 80002d58: 08f00e93 li t4,143 + 80002d5c: 01400193 li gp,20 + 80002d60: 15df1063 bne t5,t4,80002ea0 + +0000000080002d64 : + 80002d64: 00000213 li tp,0 + 80002d68: 00b00113 li sp,11 + 80002d6c: 00e00093 li ra,14 + 80002d70: 00000013 nop + 80002d74: 02208f3b mulw t5,ra,sp + 80002d78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002d7c: 00200293 li t0,2 + 80002d80: fe5214e3 bne tp,t0,80002d68 + 80002d84: 09a00e93 li t4,154 + 80002d88: 01500193 li gp,21 + 80002d8c: 11df1a63 bne t5,t4,80002ea0 + +0000000080002d90 : + 80002d90: 00000213 li tp,0 + 80002d94: 00b00113 li sp,11 + 80002d98: 00f00093 li ra,15 + 80002d9c: 00000013 nop + 80002da0: 00000013 nop + 80002da4: 02208f3b mulw t5,ra,sp + 80002da8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dac: 00200293 li t0,2 + 80002db0: fe5212e3 bne tp,t0,80002d94 + 80002db4: 0a500e93 li t4,165 + 80002db8: 01600193 li gp,22 + 80002dbc: 0fdf1263 bne t5,t4,80002ea0 + +0000000080002dc0 : + 80002dc0: 00000213 li tp,0 + 80002dc4: 00b00113 li sp,11 + 80002dc8: 00000013 nop + 80002dcc: 00d00093 li ra,13 + 80002dd0: 02208f3b mulw t5,ra,sp + 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002dd8: 00200293 li t0,2 + 80002ddc: fe5214e3 bne tp,t0,80002dc4 + 80002de0: 08f00e93 li t4,143 + 80002de4: 01700193 li gp,23 + 80002de8: 0bdf1c63 bne t5,t4,80002ea0 + +0000000080002dec : + 80002dec: 00000213 li tp,0 + 80002df0: 00b00113 li sp,11 + 80002df4: 00000013 nop + 80002df8: 00e00093 li ra,14 + 80002dfc: 00000013 nop + 80002e00: 02208f3b mulw t5,ra,sp + 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e08: 00200293 li t0,2 + 80002e0c: fe5212e3 bne tp,t0,80002df0 + 80002e10: 09a00e93 li t4,154 + 80002e14: 01800193 li gp,24 + 80002e18: 09df1463 bne t5,t4,80002ea0 + +0000000080002e1c : + 80002e1c: 00000213 li tp,0 + 80002e20: 00b00113 li sp,11 + 80002e24: 00000013 nop + 80002e28: 00000013 nop + 80002e2c: 00f00093 li ra,15 + 80002e30: 02208f3b mulw t5,ra,sp + 80002e34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80002e38: 00200293 li t0,2 + 80002e3c: fe5212e3 bne tp,t0,80002e20 + 80002e40: 0a500e93 li t4,165 + 80002e44: 01900193 li gp,25 + 80002e48: 05df1c63 bne t5,t4,80002ea0 + +0000000080002e4c : + 80002e4c: 01f00093 li ra,31 + 80002e50: 0210013b mulw sp,zero,ra + 80002e54: 00000e93 li t4,0 + 80002e58: 01a00193 li gp,26 + 80002e5c: 05d11263 bne sp,t4,80002ea0 + +0000000080002e60 : + 80002e60: 02000093 li ra,32 + 80002e64: 0200813b mulw sp,ra,zero + 80002e68: 00000e93 li t4,0 + 80002e6c: 01b00193 li gp,27 + 80002e70: 03d11863 bne sp,t4,80002ea0 + +0000000080002e74 : + 80002e74: 020000bb mulw ra,zero,zero + 80002e78: 00000e93 li t4,0 + 80002e7c: 01c00193 li gp,28 + 80002e80: 03d09063 bne ra,t4,80002ea0 + +0000000080002e84 : + 80002e84: 02100093 li ra,33 + 80002e88: 02200113 li sp,34 + 80002e8c: 0220803b mulw zero,ra,sp + 80002e90: 00000e93 li t4,0 + 80002e94: 01d00193 li gp,29 + 80002e98: 01d01463 bne zero,t4,80002ea0 + 80002e9c: 00301a63 bne zero,gp,80002eb0 + +0000000080002ea0 : + 80002ea0: 00119513 slli a0,gp,0x1 + 80002ea4: 00050063 beqz a0,80002ea4 + 80002ea8: 00156513 ori a0,a0,1 + 80002eac: 00000073 ecall + +0000000080002eb0 : + 80002eb0: 00100513 li a0,1 + 80002eb4: 00000073 ecall + 80002eb8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulw.elf b/test/riscv/tests/rv64um-v-mulw.elf new file mode 100644 index 00000000..bfc28b25 Binary files /dev/null and b/test/riscv/tests/rv64um-v-mulw.elf differ diff --git a/test/riscv/tests/rv64um-v-rem.dump b/test/riscv/tests/rv64um-v-rem.dump new file mode 100644 index 00000000..8c29a0c4 --- /dev/null +++ b/test/riscv/tests/rv64um-v-rem.dump @@ -0,0 +1,915 @@ + +rv64um-v-rem: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 77868693 addi a3,a3,1912 # 80002bd0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7ac60613 addi a2,a2,1964 # 80002c60 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 77460613 addi a2,a2,1908 # 80002c78 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6c468693 addi a3,a3,1732 # 80002c18 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6e068693 addi a3,a3,1760 # 80002d50 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 66060613 addi a2,a2,1632 # 80002d28 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 59468693 addi a3,a3,1428 # 80002d80 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4b468693 addi a3,a3,1204 # 80002cf0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 44468693 addi a3,a3,1092 # 80002cb8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03100793 li a5,49 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 03a277b7 lui a5,0x3a27 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: ea378793 addi a5,a5,-349 # 3a26ea3 <_start-0x7c5d915d> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220ef33 rem t5,ra,sp + 80002ad4: 00200e93 li t4,2 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1c63 bne t5,t4,80002bb4 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220ef33 rem t5,ra,sp + 80002aec: ffe00e93 li t4,-2 + 80002af0: 00300193 li gp,3 + 80002af4: 0ddf1063 bne t5,t4,80002bb4 + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220ef33 rem t5,ra,sp + 80002b04: 00200e93 li t4,2 + 80002b08: 00400193 li gp,4 + 80002b0c: 0bdf1463 bne t5,t4,80002bb4 + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220ef33 rem t5,ra,sp + 80002b1c: ffe00e93 li t4,-2 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1863 bne t5,t4,80002bb4 + +0000000080002b28 : + 80002b28: fff0009b addiw ra,zero,-1 + 80002b2c: 03f09093 slli ra,ra,0x3f + 80002b30: 00100113 li sp,1 + 80002b34: 0220ef33 rem t5,ra,sp + 80002b38: 00000e93 li t4,0 + 80002b3c: 00600193 li gp,6 + 80002b40: 07df1a63 bne t5,t4,80002bb4 + +0000000080002b44 : + 80002b44: fff0009b addiw ra,zero,-1 + 80002b48: 03f09093 slli ra,ra,0x3f + 80002b4c: fff00113 li sp,-1 + 80002b50: 0220ef33 rem t5,ra,sp + 80002b54: 00000e93 li t4,0 + 80002b58: 00700193 li gp,7 + 80002b5c: 05df1c63 bne t5,t4,80002bb4 + +0000000080002b60 : + 80002b60: fff0009b addiw ra,zero,-1 + 80002b64: 03f09093 slli ra,ra,0x3f + 80002b68: 00000113 li sp,0 + 80002b6c: 0220ef33 rem t5,ra,sp + 80002b70: fff00e9b addiw t4,zero,-1 + 80002b74: 03fe9e93 slli t4,t4,0x3f + 80002b78: 00800193 li gp,8 + 80002b7c: 03df1c63 bne t5,t4,80002bb4 + +0000000080002b80 : + 80002b80: 00100093 li ra,1 + 80002b84: 00000113 li sp,0 + 80002b88: 0220ef33 rem t5,ra,sp + 80002b8c: 00100e93 li t4,1 + 80002b90: 00900193 li gp,9 + 80002b94: 03df1063 bne t5,t4,80002bb4 + +0000000080002b98 : + 80002b98: 00000093 li ra,0 + 80002b9c: 00000113 li sp,0 + 80002ba0: 0220ef33 rem t5,ra,sp + 80002ba4: 00000e93 li t4,0 + 80002ba8: 00a00193 li gp,10 + 80002bac: 01df1463 bne t5,t4,80002bb4 + 80002bb0: 00301a63 bne zero,gp,80002bc4 + +0000000080002bb4 : + 80002bb4: 00119513 slli a0,gp,0x1 + 80002bb8: 00050063 beqz a0,80002bb8 + 80002bbc: 00156513 ori a0,a0,1 + 80002bc0: 00000073 ecall + +0000000080002bc4 : + 80002bc4: 00100513 li a0,1 + 80002bc8: 00000073 ecall + 80002bcc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-rem.elf b/test/riscv/tests/rv64um-v-rem.elf new file mode 100644 index 00000000..9caa3b3b Binary files /dev/null and b/test/riscv/tests/rv64um-v-rem.elf differ diff --git a/test/riscv/tests/rv64um-v-remu.dump b/test/riscv/tests/rv64um-v-remu.dump new file mode 100644 index 00000000..01d50acb --- /dev/null +++ b/test/riscv/tests/rv64um-v-remu.dump @@ -0,0 +1,916 @@ + +rv64um-v-remu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 77c60613 addi a2,a2,1916 # 80002c80 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6e868693 addi a3,a3,1768 # 80002d58 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 66860613 addi a2,a2,1640 # 80002d30 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03e00793 li a5,62 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 05d337b7 lui a5,0x5d33 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 2c578793 addi a5,a5,709 # 5d332c5 <_start-0x7a2ccd3b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220ff33 remu t5,ra,sp + 80002ad4: 00200e93 li t4,2 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1e63 bne t5,t4,80002bb8 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220ff33 remu t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 0ddf1263 bne t5,t4,80002bb8 + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220ff33 remu t5,ra,sp + 80002b04: 01400e93 li t4,20 + 80002b08: 00400193 li gp,4 + 80002b0c: 0bdf1663 bne t5,t4,80002bb8 + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220ff33 remu t5,ra,sp + 80002b1c: fec00e93 li t4,-20 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1a63 bne t5,t4,80002bb8 + +0000000080002b28 : + 80002b28: fff0009b addiw ra,zero,-1 + 80002b2c: 03f09093 slli ra,ra,0x3f + 80002b30: 00100113 li sp,1 + 80002b34: 0220ff33 remu t5,ra,sp + 80002b38: 00000e93 li t4,0 + 80002b3c: 00600193 li gp,6 + 80002b40: 07df1c63 bne t5,t4,80002bb8 + +0000000080002b44 : + 80002b44: fff0009b addiw ra,zero,-1 + 80002b48: 03f09093 slli ra,ra,0x3f + 80002b4c: fff00113 li sp,-1 + 80002b50: 0220ff33 remu t5,ra,sp + 80002b54: fff00e9b addiw t4,zero,-1 + 80002b58: 03fe9e93 slli t4,t4,0x3f + 80002b5c: 00700193 li gp,7 + 80002b60: 05df1c63 bne t5,t4,80002bb8 + +0000000080002b64 : + 80002b64: fff0009b addiw ra,zero,-1 + 80002b68: 03f09093 slli ra,ra,0x3f + 80002b6c: 00000113 li sp,0 + 80002b70: 0220ff33 remu t5,ra,sp + 80002b74: fff00e9b addiw t4,zero,-1 + 80002b78: 03fe9e93 slli t4,t4,0x3f + 80002b7c: 00800193 li gp,8 + 80002b80: 03df1c63 bne t5,t4,80002bb8 + +0000000080002b84 : + 80002b84: 00100093 li ra,1 + 80002b88: 00000113 li sp,0 + 80002b8c: 0220ff33 remu t5,ra,sp + 80002b90: 00100e93 li t4,1 + 80002b94: 00900193 li gp,9 + 80002b98: 03df1063 bne t5,t4,80002bb8 + +0000000080002b9c : + 80002b9c: 00000093 li ra,0 + 80002ba0: 00000113 li sp,0 + 80002ba4: 0220ff33 remu t5,ra,sp + 80002ba8: 00000e93 li t4,0 + 80002bac: 00a00193 li gp,10 + 80002bb0: 01df1463 bne t5,t4,80002bb8 + 80002bb4: 00301a63 bne zero,gp,80002bc8 + +0000000080002bb8 : + 80002bb8: 00119513 slli a0,gp,0x1 + 80002bbc: 00050063 beqz a0,80002bbc + 80002bc0: 00156513 ori a0,a0,1 + 80002bc4: 00000073 ecall + +0000000080002bc8 : + 80002bc8: 00100513 li a0,1 + 80002bcc: 00000073 ecall + 80002bd0: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remu.elf b/test/riscv/tests/rv64um-v-remu.elf new file mode 100644 index 00000000..26ead9d0 Binary files /dev/null and b/test/riscv/tests/rv64um-v-remu.elf differ diff --git a/test/riscv/tests/rv64um-v-remuw.dump b/test/riscv/tests/rv64um-v-remuw.dump new file mode 100644 index 00000000..f0688a43 --- /dev/null +++ b/test/riscv/tests/rv64um-v-remuw.dump @@ -0,0 +1,911 @@ + +rv64um-v-remuw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 76868693 addi a3,a3,1896 # 80002bc0 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 79c60613 addi a2,a2,1948 # 80002c50 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 76460613 addi a2,a2,1892 # 80002c68 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6b468693 addi a3,a3,1716 # 80002c08 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6d068693 addi a3,a3,1744 # 80002d40 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 65060613 addi a2,a2,1616 # 80002d18 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 58468693 addi a3,a3,1412 # 80002d70 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4a468693 addi a3,a3,1188 # 80002ce0 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 43468693 addi a3,a3,1076 # 80002ca8 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 01700793 li a5,23 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 01bd87b7 lui a5,0x1bd8 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 7ed78793 addi a5,a5,2029 # 1bd87ed <_start-0x7e427813> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220ff3b remuw t5,ra,sp + 80002ad4: 00200e93 li t4,2 + 80002ad8: 00200193 li gp,2 + 80002adc: 0ddf1463 bne t5,t4,80002ba4 + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220ff3b remuw t5,ra,sp + 80002aec: 00200e93 li t4,2 + 80002af0: 00300193 li gp,3 + 80002af4: 0bdf1863 bne t5,t4,80002ba4 + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220ff3b remuw t5,ra,sp + 80002b04: 01400e93 li t4,20 + 80002b08: 00400193 li gp,4 + 80002b0c: 09df1c63 bne t5,t4,80002ba4 + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220ff3b remuw t5,ra,sp + 80002b1c: fec00e93 li t4,-20 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1063 bne t5,t4,80002ba4 + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00100113 li sp,1 + 80002b30: 0220ff3b remuw t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 07df1463 bne t5,t4,80002ba4 + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: fff00113 li sp,-1 + 80002b48: 0220ff3b remuw t5,ra,sp + 80002b4c: 80000eb7 lui t4,0x80000 + 80002b50: 00700193 li gp,7 + 80002b54: 05df1863 bne t5,t4,80002ba4 + +0000000080002b58 : + 80002b58: 800000b7 lui ra,0x80000 + 80002b5c: 00000113 li sp,0 + 80002b60: 0220ff3b remuw t5,ra,sp + 80002b64: 80000eb7 lui t4,0x80000 + 80002b68: 00800193 li gp,8 + 80002b6c: 03df1c63 bne t5,t4,80002ba4 + +0000000080002b70 : + 80002b70: 00100093 li ra,1 + 80002b74: 00000113 li sp,0 + 80002b78: 0220ff3b remuw t5,ra,sp + 80002b7c: 00100e93 li t4,1 + 80002b80: 00900193 li gp,9 + 80002b84: 03df1063 bne t5,t4,80002ba4 + +0000000080002b88 : + 80002b88: 00000093 li ra,0 + 80002b8c: 00000113 li sp,0 + 80002b90: 0220ff3b remuw t5,ra,sp + 80002b94: 00000e93 li t4,0 + 80002b98: 00a00193 li gp,10 + 80002b9c: 01df1463 bne t5,t4,80002ba4 + 80002ba0: 00301a63 bne zero,gp,80002bb4 + +0000000080002ba4 : + 80002ba4: 00119513 slli a0,gp,0x1 + 80002ba8: 00050063 beqz a0,80002ba8 + 80002bac: 00156513 ori a0,a0,1 + 80002bb0: 00000073 ecall + +0000000080002bb4 : + 80002bb4: 00100513 li a0,1 + 80002bb8: 00000073 ecall + 80002bbc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remuw.elf b/test/riscv/tests/rv64um-v-remuw.elf new file mode 100644 index 00000000..795ae59c Binary files /dev/null and b/test/riscv/tests/rv64um-v-remuw.elf differ diff --git a/test/riscv/tests/rv64um-v-remw.dump b/test/riscv/tests/rv64um-v-remw.dump new file mode 100644 index 00000000..659d882e --- /dev/null +++ b/test/riscv/tests/rv64um-v-remw.dump @@ -0,0 +1,919 @@ + +rv64um-v-remw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 00c0006f j 8000000c + +0000000080000004 : + 80000004: 2580206f j 8000225c + +0000000080000008 : + 80000008: 2540206f j 8000225c + +000000008000000c : + 8000000c: 00000297 auipc t0,0x0 + 80000010: ffc28293 addi t0,t0,-4 # 80000008 + 80000014: 30529073 csrw mtvec,t0 + 80000018: 00008117 auipc sp,0x8 + 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> + 80000020: f14022f3 csrr t0,mhartid + 80000024: 00c29293 slli t0,t0,0xc + 80000028: 00510133 add sp,sp,t0 + 8000002c: 34011073 csrw mscratch,sp + 80000030: 00003517 auipc a0,0x3 + 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 + 80000038: 09d0206f j 800028d4 + +000000008000003c : + 8000003c: 10853283 ld t0,264(a0) + 80000040: 14129073 csrw sepc,t0 + 80000044: 00853083 ld ra,8(a0) + 80000048: 01053103 ld sp,16(a0) + 8000004c: 01853183 ld gp,24(a0) + 80000050: 02053203 ld tp,32(a0) + 80000054: 02853283 ld t0,40(a0) + 80000058: 03053303 ld t1,48(a0) + 8000005c: 03853383 ld t2,56(a0) + 80000060: 04053403 ld s0,64(a0) + 80000064: 04853483 ld s1,72(a0) + 80000068: 05853583 ld a1,88(a0) + 8000006c: 06053603 ld a2,96(a0) + 80000070: 06853683 ld a3,104(a0) + 80000074: 07053703 ld a4,112(a0) + 80000078: 07853783 ld a5,120(a0) + 8000007c: 08053803 ld a6,128(a0) + 80000080: 08853883 ld a7,136(a0) + 80000084: 09053903 ld s2,144(a0) + 80000088: 09853983 ld s3,152(a0) + 8000008c: 0a053a03 ld s4,160(a0) + 80000090: 0a853a83 ld s5,168(a0) + 80000094: 0b053b03 ld s6,176(a0) + 80000098: 0b853b83 ld s7,184(a0) + 8000009c: 0c053c03 ld s8,192(a0) + 800000a0: 0c853c83 ld s9,200(a0) + 800000a4: 0d053d03 ld s10,208(a0) + 800000a8: 0d853d83 ld s11,216(a0) + 800000ac: 0e053e03 ld t3,224(a0) + 800000b0: 0e853e83 ld t4,232(a0) + 800000b4: 0f053f03 ld t5,240(a0) + 800000b8: 0f853f83 ld t6,248(a0) + 800000bc: 05053503 ld a0,80(a0) + 800000c0: 10200073 sret + +00000000800000c4 : + 800000c4: 14011173 csrrw sp,sscratch,sp + 800000c8: 00113423 sd ra,8(sp) + 800000cc: 00313c23 sd gp,24(sp) + 800000d0: 02413023 sd tp,32(sp) + 800000d4: 02513423 sd t0,40(sp) + 800000d8: 02613823 sd t1,48(sp) + 800000dc: 02713c23 sd t2,56(sp) + 800000e0: 04813023 sd s0,64(sp) + 800000e4: 04913423 sd s1,72(sp) + 800000e8: 04a13823 sd a0,80(sp) + 800000ec: 04b13c23 sd a1,88(sp) + 800000f0: 06c13023 sd a2,96(sp) + 800000f4: 06d13423 sd a3,104(sp) + 800000f8: 06e13823 sd a4,112(sp) + 800000fc: 06f13c23 sd a5,120(sp) + 80000100: 09013023 sd a6,128(sp) + 80000104: 09113423 sd a7,136(sp) + 80000108: 09213823 sd s2,144(sp) + 8000010c: 09313c23 sd s3,152(sp) + 80000110: 0b413023 sd s4,160(sp) + 80000114: 0b513423 sd s5,168(sp) + 80000118: 0b613823 sd s6,176(sp) + 8000011c: 0b713c23 sd s7,184(sp) + 80000120: 0d813023 sd s8,192(sp) + 80000124: 0d913423 sd s9,200(sp) + 80000128: 0da13823 sd s10,208(sp) + 8000012c: 0db13c23 sd s11,216(sp) + 80000130: 0fc13023 sd t3,224(sp) + 80000134: 0fd13423 sd t4,232(sp) + 80000138: 0fe13823 sd t5,240(sp) + 8000013c: 0ff13c23 sd t6,248(sp) + 80000140: 140112f3 csrrw t0,sscratch,sp + 80000144: 00513823 sd t0,16(sp) + 80000148: 100022f3 csrr t0,sstatus + 8000014c: 10513023 sd t0,256(sp) + 80000150: 141022f3 csrr t0,sepc + 80000154: 10513423 sd t0,264(sp) + 80000158: 143022f3 csrr t0,sbadaddr + 8000015c: 10513823 sd t0,272(sp) + 80000160: 142022f3 csrr t0,scause + 80000164: 10513c23 sd t0,280(sp) + 80000168: 00010513 mv a0,sp + 8000016c: 4300206f j 8000259c + +Disassembly of section .text: + +0000000080002000 : + 80002000: 00c5e7b3 or a5,a1,a2 + 80002004: 00f567b3 or a5,a0,a5 + 80002008: 0077f793 andi a5,a5,7 + 8000200c: 00c506b3 add a3,a0,a2 + 80002010: 02078463 beqz a5,80002038 + 80002014: 00c58633 add a2,a1,a2 + 80002018: 00050793 mv a5,a0 + 8000201c: 02d57e63 bleu a3,a0,80002058 + 80002020: 00158593 addi a1,a1,1 + 80002024: fff5c703 lbu a4,-1(a1) + 80002028: 00178793 addi a5,a5,1 + 8000202c: fee78fa3 sb a4,-1(a5) + 80002030: feb618e3 bne a2,a1,80002020 + 80002034: 00008067 ret + 80002038: fed57ee3 bleu a3,a0,80002034 + 8000203c: 00050793 mv a5,a0 + 80002040: 00858593 addi a1,a1,8 + 80002044: ff85b703 ld a4,-8(a1) + 80002048: 00878793 addi a5,a5,8 + 8000204c: fee7bc23 sd a4,-8(a5) + 80002050: fed7e8e3 bltu a5,a3,80002040 + 80002054: 00008067 ret + 80002058: 00008067 ret + +000000008000205c : + 8000205c: 00c567b3 or a5,a0,a2 + 80002060: 0077f793 andi a5,a5,7 + 80002064: 00c50633 add a2,a0,a2 + 80002068: 0ff5f593 andi a1,a1,255 + 8000206c: 00078e63 beqz a5,80002088 + 80002070: 00050793 mv a5,a0 + 80002074: 04c57263 bleu a2,a0,800020b8 + 80002078: 00178793 addi a5,a5,1 + 8000207c: feb78fa3 sb a1,-1(a5) + 80002080: fef61ce3 bne a2,a5,80002078 + 80002084: 00008067 ret + 80002088: 00859793 slli a5,a1,0x8 + 8000208c: 00b7e5b3 or a1,a5,a1 + 80002090: 01059793 slli a5,a1,0x10 + 80002094: 00b7e7b3 or a5,a5,a1 + 80002098: 02079593 slli a1,a5,0x20 + 8000209c: 00f5e5b3 or a1,a1,a5 + 800020a0: fec572e3 bleu a2,a0,80002084 + 800020a4: 00050793 mv a5,a0 + 800020a8: 00878793 addi a5,a5,8 + 800020ac: feb7bc23 sd a1,-8(a5) + 800020b0: fec7ece3 bltu a5,a2,800020a8 + 800020b4: 00008067 ret + 800020b8: 00008067 ret + +00000000800020bc : + 800020bc: 00054783 lbu a5,0(a0) + 800020c0: 00050713 mv a4,a0 + 800020c4: 00078c63 beqz a5,800020dc + 800020c8: 00150513 addi a0,a0,1 + 800020cc: 00054783 lbu a5,0(a0) + 800020d0: fe079ce3 bnez a5,800020c8 + 800020d4: 40e50533 sub a0,a0,a4 + 800020d8: 00008067 ret + 800020dc: 00000513 li a0,0 + 800020e0: 00008067 ret + +00000000800020e4 : + 800020e4: 00150513 addi a0,a0,1 + 800020e8: fff54783 lbu a5,-1(a0) + 800020ec: 00158593 addi a1,a1,1 + 800020f0: fff5c703 lbu a4,-1(a1) + 800020f4: 00078a63 beqz a5,80002108 + 800020f8: fee786e3 beq a5,a4,800020e4 + 800020fc: 0007851b sext.w a0,a5 + 80002100: 40e5053b subw a0,a0,a4 + 80002104: 00008067 ret + 80002108: 00000513 li a0,0 + 8000210c: ff5ff06f j 80002100 + +0000000080002110 : + 80002110: 00b567b3 or a5,a0,a1 + 80002114: 0077f793 andi a5,a5,7 + 80002118: 04079263 bnez a5,8000215c + 8000211c: ff867693 andi a3,a2,-8 + 80002120: 00d506b3 add a3,a0,a3 + 80002124: 00050813 mv a6,a0 + 80002128: 02d57a63 bleu a3,a0,8000215c + 8000212c: 00053703 ld a4,0(a0) + 80002130: 0005b783 ld a5,0(a1) + 80002134: 00f70a63 beq a4,a5,80002148 + 80002138: 0240006f j 8000215c + 8000213c: 00053703 ld a4,0(a0) + 80002140: 0005b783 ld a5,0(a1) + 80002144: 00f71863 bne a4,a5,80002154 + 80002148: 00850513 addi a0,a0,8 + 8000214c: 00858593 addi a1,a1,8 + 80002150: fed566e3 bltu a0,a3,8000213c + 80002154: 41050833 sub a6,a0,a6 + 80002158: 41060633 sub a2,a2,a6 + 8000215c: 00c58633 add a2,a1,a2 + 80002160: 0140006f j 80002174 + 80002164: 00158593 addi a1,a1,1 + 80002168: fff54783 lbu a5,-1(a0) + 8000216c: fff5c703 lbu a4,-1(a1) + 80002170: 00e79a63 bne a5,a4,80002184 + 80002174: 00150513 addi a0,a0,1 + 80002178: fec596e3 bne a1,a2,80002164 + 8000217c: 00000513 li a0,0 + 80002180: 00008067 ret + 80002184: 40e7853b subw a0,a5,a4 + 80002188: 00008067 ret + +000000008000218c : + 8000218c: 00050793 mv a5,a0 + 80002190: 00158593 addi a1,a1,1 + 80002194: fff5c703 lbu a4,-1(a1) + 80002198: 00178793 addi a5,a5,1 + 8000219c: fee78fa3 sb a4,-1(a5) + 800021a0: fe0718e3 bnez a4,80002190 + 800021a4: 00008067 ret + +00000000800021a8 : + 800021a8: 00054783 lbu a5,0(a0) + 800021ac: 02000713 li a4,32 + 800021b0: 00e79863 bne a5,a4,800021c0 + 800021b4: 00150513 addi a0,a0,1 + 800021b8: 00054783 lbu a5,0(a0) + 800021bc: fee78ce3 beq a5,a4,800021b4 + 800021c0: fd57871b addiw a4,a5,-43 + 800021c4: 0fd77713 andi a4,a4,253 + 800021c8: 04070263 beqz a4,8000220c + 800021cc: 00054683 lbu a3,0(a0) + 800021d0: 00050793 mv a5,a0 + 800021d4: 00000613 li a2,0 + 800021d8: 04068863 beqz a3,80002228 + 800021dc: 00000513 li a0,0 + 800021e0: 00178793 addi a5,a5,1 + 800021e4: fd06859b addiw a1,a3,-48 + 800021e8: 00251713 slli a4,a0,0x2 + 800021ec: 0007c683 lbu a3,0(a5) + 800021f0: 00a70533 add a0,a4,a0 + 800021f4: 00151513 slli a0,a0,0x1 + 800021f8: 00a58533 add a0,a1,a0 + 800021fc: fe0692e3 bnez a3,800021e0 + 80002200: 00060463 beqz a2,80002208 + 80002204: 40a00533 neg a0,a0 + 80002208: 00008067 ret + 8000220c: 00154683 lbu a3,1(a0) + 80002210: fd378793 addi a5,a5,-45 + 80002214: 0017b613 seqz a2,a5 + 80002218: 00150793 addi a5,a0,1 + 8000221c: fc0690e3 bnez a3,800021dc + 80002220: 00000513 li a0,0 + 80002224: fddff06f j 80002200 + 80002228: 00000513 li a0,0 + 8000222c: 00008067 ret + +0000000080002230 : + 80002230: fffff797 auipc a5,0xfffff + 80002234: dd078793 addi a5,a5,-560 # 80001000 + 80002238: 0007b703 ld a4,0(a5) + 8000223c: 00070a63 beqz a4,80002250 + 80002240: fffff717 auipc a4,0xfffff + 80002244: e0073023 sd zero,-512(a4) # 80001040 + 80002248: 0007b703 ld a4,0(a5) + 8000224c: fe071ae3 bnez a4,80002240 + 80002250: fffff797 auipc a5,0xfffff + 80002254: daa7b823 sd a0,-592(a5) # 80001000 + 80002258: 0000006f j 80002258 + +000000008000225c : + 8000225c: ff010113 addi sp,sp,-16 + 80002260: 34900513 li a0,841 + 80002264: 00113423 sd ra,8(sp) + 80002268: fc9ff0ef jal ra,80002230 + +000000008000226c : + 8000226c: fe010113 addi sp,sp,-32 + 80002270: 01710713 addi a4,sp,23 + 80002274: 00710813 addi a6,sp,7 + 80002278: 00900593 li a1,9 + 8000227c: 00f57793 andi a5,a0,15 + 80002280: 03000613 li a2,48 + 80002284: 0ff7f693 andi a3,a5,255 + 80002288: 00f5f463 bleu a5,a1,80002290 + 8000228c: 05700613 li a2,87 + 80002290: 00c687bb addw a5,a3,a2 + 80002294: 00f70023 sb a5,0(a4) + 80002298: fff70713 addi a4,a4,-1 + 8000229c: 00455513 srli a0,a0,0x4 + 800022a0: fd071ee3 bne a4,a6,8000227c + 800022a4: 00814783 lbu a5,8(sp) + 800022a8: 00010c23 sb zero,24(sp) + 800022ac: 04078463 beqz a5,800022f4 + 800022b0: 10100513 li a0,257 + 800022b4: 00810693 addi a3,sp,8 + 800022b8: fffff717 auipc a4,0xfffff + 800022bc: d4870713 addi a4,a4,-696 # 80001000 + 800022c0: 03051513 slli a0,a0,0x30 + 800022c4: 00073583 ld a1,0(a4) + 800022c8: 00168693 addi a3,a3,1 + 800022cc: 00a7e633 or a2,a5,a0 + 800022d0: 00058a63 beqz a1,800022e4 + 800022d4: fffff797 auipc a5,0xfffff + 800022d8: d607b623 sd zero,-660(a5) # 80001040 + 800022dc: 00073783 ld a5,0(a4) + 800022e0: fe079ae3 bnez a5,800022d4 + 800022e4: 0006c783 lbu a5,0(a3) + 800022e8: fffff597 auipc a1,0xfffff + 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 + 800022f0: fc079ae3 bnez a5,800022c4 + 800022f4: 02010113 addi sp,sp,32 + 800022f8: 00008067 ret + +00000000800022fc : + 800022fc: fffff8b7 lui a7,0xfffff + 80002300: 01150733 add a4,a0,a7 + 80002304: 0003e7b7 lui a5,0x3e + 80002308: 14f77463 bleu a5,a4,80002450 + 8000230c: 00c55693 srli a3,a0,0xc + 80002310: 60068813 addi a6,a3,1536 + 80002314: 00001617 auipc a2,0x1 + 80002318: cec60613 addi a2,a2,-788 # 80003000 + 8000231c: 00381793 slli a5,a6,0x3 + 80002320: 00f607b3 add a5,a2,a5 + 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> + 80002328: 01157533 and a0,a0,a7 + 8000232c: 0e071063 bnez a4,8000240c + 80002330: 00005797 auipc a5,0x5 + 80002334: 4b878793 addi a5,a5,1208 # 800077e8 + 80002338: 0007b583 ld a1,0(a5) + 8000233c: 16058863 beqz a1,800024ac + 80002340: 0085b783 ld a5,8(a1) + 80002344: 00005717 auipc a4,0x5 + 80002348: 49c70713 addi a4,a4,1180 # 800077e0 + 8000234c: 00073703 ld a4,0(a4) + 80002350: 00005897 auipc a7,0x5 + 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 + 80002358: 0ee78663 beq a5,a4,80002444 + 8000235c: 0005b783 ld a5,0(a1) + 80002360: 00381893 slli a7,a6,0x3 + 80002364: 011608b3 add a7,a2,a7 + 80002368: 00c7d793 srli a5,a5,0xc + 8000236c: 00a79793 slli a5,a5,0xa + 80002370: 0df7e313 ori t1,a5,223 + 80002374: 01f7e713 ori a4,a5,31 + 80002378: 0068b023 sd t1,0(a7) + 8000237c: 12050073 sfence.vma a0 + 80002380: 00005797 auipc a5,0x5 + 80002384: 07078793 addi a5,a5,112 # 800073f0 + 80002388: 00469693 slli a3,a3,0x4 + 8000238c: 00d786b3 add a3,a5,a3 + 80002390: 0006b783 ld a5,0(a3) + 80002394: 16079463 bnez a5,800024fc + 80002398: 0005b783 ld a5,0(a1) + 8000239c: 00f6b023 sd a5,0(a3) + 800023a0: 0085b783 ld a5,8(a1) + 800023a4: 00f6b423 sd a5,8(a3) + 800023a8: 000407b7 lui a5,0x40 + 800023ac: 1007a8f3 csrrs a7,sstatus,a5 + 800023b0: ffe007b7 lui a5,0xffe00 + 800023b4: 00f507b3 add a5,a0,a5 + 800023b8: 000015b7 lui a1,0x1 + 800023bc: 00050693 mv a3,a0 + 800023c0: 00b785b3 add a1,a5,a1 + 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> + 800023c8: 0087be83 ld t4,8(a5) + 800023cc: 0107be03 ld t3,16(a5) + 800023d0: 0187b303 ld t1,24(a5) + 800023d4: 01e6b023 sd t5,0(a3) + 800023d8: 01d6b423 sd t4,8(a3) + 800023dc: 01c6b823 sd t3,16(a3) + 800023e0: 0066bc23 sd t1,24(a3) + 800023e4: 02078793 addi a5,a5,32 + 800023e8: 02068693 addi a3,a3,32 + 800023ec: fcb79ce3 bne a5,a1,800023c4 + 800023f0: 10089073 csrw sstatus,a7 + 800023f4: 00381813 slli a6,a6,0x3 + 800023f8: 01060633 add a2,a2,a6 + 800023fc: 00e63023 sd a4,0(a2) + 80002400: 12050073 sfence.vma a0 + 80002404: 0000100f fence.i + 80002408: 00008067 ret + 8000240c: 04077693 andi a3,a4,64 + 80002410: 00069a63 bnez a3,80002424 + 80002414: 04076713 ori a4,a4,64 + 80002418: 00e7b023 sd a4,0(a5) + 8000241c: 12050073 sfence.vma a0 + 80002420: 00008067 ret + 80002424: 08077693 andi a3,a4,128 + 80002428: 12069263 bnez a3,8000254c + 8000242c: 00f00693 li a3,15 + 80002430: 10d59e63 bne a1,a3,8000254c + 80002434: 08076713 ori a4,a4,128 + 80002438: 00e7b023 sd a4,0(a5) + 8000243c: 12050073 sfence.vma a0 + 80002440: 00008067 ret + 80002444: 00005797 auipc a5,0x5 + 80002448: 3807be23 sd zero,924(a5) # 800077e0 + 8000244c: f11ff06f j 8000235c + 80002450: 10100613 li a2,257 + 80002454: 04100713 li a4,65 + 80002458: 00000697 auipc a3,0x0 + 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 + 80002460: fffff797 auipc a5,0xfffff + 80002464: ba078793 addi a5,a5,-1120 # 80001000 + 80002468: 03061613 slli a2,a2,0x30 + 8000246c: 0007b503 ld a0,0(a5) + 80002470: 00168693 addi a3,a3,1 + 80002474: 00c765b3 or a1,a4,a2 + 80002478: 00050a63 beqz a0,8000248c + 8000247c: fffff717 auipc a4,0xfffff + 80002480: bc073223 sd zero,-1084(a4) # 80001040 + 80002484: 0007b703 ld a4,0(a5) + 80002488: fe071ae3 bnez a4,8000247c + 8000248c: 0006c703 lbu a4,0(a3) + 80002490: fffff517 auipc a0,0xfffff + 80002494: b6b53823 sd a1,-1168(a0) # 80001000 + 80002498: fc071ae3 bnez a4,8000246c + 8000249c: ff010113 addi sp,sp,-16 + 800024a0: 00300513 li a0,3 + 800024a4: 00113423 sd ra,8(sp) + 800024a8: d89ff0ef jal ra,80002230 + 800024ac: 10100693 li a3,257 + 800024b0: 04100713 li a4,65 + 800024b4: 00000617 auipc a2,0x0 + 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 + 800024bc: fffff797 auipc a5,0xfffff + 800024c0: b4478793 addi a5,a5,-1212 # 80001000 + 800024c4: 03069693 slli a3,a3,0x30 + 800024c8: 0007b503 ld a0,0(a5) + 800024cc: 00160613 addi a2,a2,1 + 800024d0: 00d765b3 or a1,a4,a3 + 800024d4: 00050a63 beqz a0,800024e8 + 800024d8: fffff717 auipc a4,0xfffff + 800024dc: b6073423 sd zero,-1176(a4) # 80001040 + 800024e0: 0007b703 ld a4,0(a5) + 800024e4: fe071ae3 bnez a4,800024d8 + 800024e8: 00064703 lbu a4,0(a2) + 800024ec: fffff517 auipc a0,0xfffff + 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 + 800024f4: fc071ae3 bnez a4,800024c8 + 800024f8: fa5ff06f j 8000249c + 800024fc: 10100693 li a3,257 + 80002500: 04100713 li a4,65 + 80002504: 00000617 auipc a2,0x0 + 80002508: 77c60613 addi a2,a2,1916 # 80002c80 + 8000250c: fffff797 auipc a5,0xfffff + 80002510: af478793 addi a5,a5,-1292 # 80001000 + 80002514: 03069693 slli a3,a3,0x30 + 80002518: 0007b503 ld a0,0(a5) + 8000251c: 00160613 addi a2,a2,1 + 80002520: 00d765b3 or a1,a4,a3 + 80002524: 00050a63 beqz a0,80002538 + 80002528: fffff717 auipc a4,0xfffff + 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 + 80002530: 0007b703 ld a4,0(a5) + 80002534: fe071ae3 bnez a4,80002528 + 80002538: 00064703 lbu a4,0(a2) + 8000253c: fffff517 auipc a0,0xfffff + 80002540: acb53223 sd a1,-1340(a0) # 80001000 + 80002544: fc071ae3 bnez a4,80002518 + 80002548: f55ff06f j 8000249c + 8000254c: 10100613 li a2,257 + 80002550: 04100713 li a4,65 + 80002554: 00000697 auipc a3,0x0 + 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 + 8000255c: fffff797 auipc a5,0xfffff + 80002560: aa478793 addi a5,a5,-1372 # 80001000 + 80002564: 03061613 slli a2,a2,0x30 + 80002568: 0007b503 ld a0,0(a5) + 8000256c: 00168693 addi a3,a3,1 + 80002570: 00c765b3 or a1,a4,a2 + 80002574: 00050a63 beqz a0,80002588 + 80002578: fffff717 auipc a4,0xfffff + 8000257c: ac073423 sd zero,-1336(a4) # 80001040 + 80002580: 0007b703 ld a4,0(a5) + 80002584: fe071ae3 bnez a4,80002578 + 80002588: 0006c703 lbu a4,0(a3) + 8000258c: fffff517 auipc a0,0xfffff + 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 + 80002594: fc071ae3 bnez a4,80002568 + 80002598: f05ff06f j 8000249c + +000000008000259c : + 8000259c: 11853583 ld a1,280(a0) + 800025a0: f9010113 addi sp,sp,-112 + 800025a4: 06813023 sd s0,96(sp) + 800025a8: 06113423 sd ra,104(sp) + 800025ac: 04913c23 sd s1,88(sp) + 800025b0: 05213823 sd s2,80(sp) + 800025b4: 05313423 sd s3,72(sp) + 800025b8: 05413023 sd s4,64(sp) + 800025bc: 03513c23 sd s5,56(sp) + 800025c0: 03613823 sd s6,48(sp) + 800025c4: 03713423 sd s7,40(sp) + 800025c8: 03813023 sd s8,32(sp) + 800025cc: 01913c23 sd s9,24(sp) + 800025d0: 01a13823 sd s10,16(sp) + 800025d4: 01b13423 sd s11,8(sp) + 800025d8: 00800793 li a5,8 + 800025dc: 00050413 mv s0,a0 + 800025e0: 12f58a63 beq a1,a5,80002714 + 800025e4: 00200793 li a5,2 + 800025e8: 06f58063 beq a1,a5,80002648 + 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> + 800025f0: 00100713 li a4,1 + 800025f4: 00f77663 bleu a5,a4,80002600 + 800025f8: 00f00793 li a5,15 + 800025fc: 1ef59463 bne a1,a5,800027e4 + 80002600: 11043503 ld a0,272(s0) + 80002604: cf9ff0ef jal ra,800022fc + 80002608: 00040513 mv a0,s0 + 8000260c: 06013403 ld s0,96(sp) + 80002610: 06813083 ld ra,104(sp) + 80002614: 05813483 ld s1,88(sp) + 80002618: 05013903 ld s2,80(sp) + 8000261c: 04813983 ld s3,72(sp) + 80002620: 04013a03 ld s4,64(sp) + 80002624: 03813a83 ld s5,56(sp) + 80002628: 03013b03 ld s6,48(sp) + 8000262c: 02813b83 ld s7,40(sp) + 80002630: 02013c03 ld s8,32(sp) + 80002634: 01813c83 ld s9,24(sp) + 80002638: 01013d03 ld s10,16(sp) + 8000263c: 00813d83 ld s11,8(sp) + 80002640: 07010113 addi sp,sp,112 + 80002644: 9f9fd06f j 8000003c + 80002648: 10853703 ld a4,264(a0) + 8000264c: 00377793 andi a5,a4,3 + 80002650: 06079a63 bnez a5,800026c4 + 80002654: 008007ef jal a5,8000265c + 80002658: 00301073 fssr zero + 8000265c: 00072703 lw a4,0(a4) + 80002660: 0007a783 lw a5,0(a5) + 80002664: 04f70c63 beq a4,a5,800026bc + 80002668: 10100513 li a0,257 + 8000266c: 04100793 li a5,65 + 80002670: 00000697 auipc a3,0x0 + 80002674: 6e868693 addi a3,a3,1768 # 80002d58 + 80002678: fffff717 auipc a4,0xfffff + 8000267c: 98870713 addi a4,a4,-1656 # 80001000 + 80002680: 03051513 slli a0,a0,0x30 + 80002684: 00073583 ld a1,0(a4) + 80002688: 00168693 addi a3,a3,1 + 8000268c: 00a7e633 or a2,a5,a0 + 80002690: 00058a63 beqz a1,800026a4 + 80002694: fffff797 auipc a5,0xfffff + 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 + 8000269c: 00073783 ld a5,0(a4) + 800026a0: fe079ae3 bnez a5,80002694 + 800026a4: 0006c783 lbu a5,0(a3) + 800026a8: fffff597 auipc a1,0xfffff + 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 + 800026b0: fc079ae3 bnez a5,80002684 + 800026b4: 00300513 li a0,3 + 800026b8: b79ff0ef jal ra,80002230 + 800026bc: 00100513 li a0,1 + 800026c0: b71ff0ef jal ra,80002230 + 800026c4: 10100793 li a5,257 + 800026c8: 00000617 auipc a2,0x0 + 800026cc: 66860613 addi a2,a2,1640 # 80002d30 + 800026d0: 04100693 li a3,65 + 800026d4: fffff717 auipc a4,0xfffff + 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 + 800026dc: 03079793 slli a5,a5,0x30 + 800026e0: 00073503 ld a0,0(a4) + 800026e4: 00160613 addi a2,a2,1 + 800026e8: 00f6e5b3 or a1,a3,a5 + 800026ec: 00050a63 beqz a0,80002700 + 800026f0: fffff697 auipc a3,0xfffff + 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 + 800026f8: 00073683 ld a3,0(a4) + 800026fc: fe069ae3 bnez a3,800026f0 + 80002700: 00064683 lbu a3,0(a2) + 80002704: fffff517 auipc a0,0xfffff + 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 + 8000270c: fc069ae3 bnez a3,800026e0 + 80002710: fa5ff06f j 800026b4 + 80002714: 05052983 lw s3,80(a0) + 80002718: 00001437 lui s0,0x1 + 8000271c: 00005d17 auipc s10,0x5 + 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 + 80002724: 00001b97 auipc s7,0x1 + 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 + 8000272c: 00040b37 lui s6,0x40 + 80002730: ffe00ab7 lui s5,0xffe00 + 80002734: 00005a17 auipc s4,0x5 + 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 + 8000273c: 0003f937 lui s2,0x3f + 80002740: 01c0006f j 8000275c + 80002744: 00f73423 sd a5,8(a4) + 80002748: 00005717 auipc a4,0x5 + 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 + 80002750: 000017b7 lui a5,0x1 + 80002754: 00f40433 add s0,s0,a5 + 80002758: 15240663 beq s0,s2,800028a4 + 8000275c: 00c45793 srli a5,s0,0xc + 80002760: 00479493 slli s1,a5,0x4 + 80002764: 009d0733 add a4,s10,s1 + 80002768: 00073703 ld a4,0(a4) + 8000276c: fe0702e3 beqz a4,80002750 + 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> + 80002774: 00379793 slli a5,a5,0x3 + 80002778: 00fb87b3 add a5,s7,a5 + 8000277c: 0007bc03 ld s8,0(a5) + 80002780: 040c7793 andi a5,s8,64 + 80002784: 0e078463 beqz a5,8000286c + 80002788: 100b2cf3 csrrs s9,sstatus,s6 + 8000278c: 01540db3 add s11,s0,s5 + 80002790: 00001637 lui a2,0x1 + 80002794: 000d8593 mv a1,s11 + 80002798: 00040513 mv a0,s0 + 8000279c: 975ff0ef jal ra,80002110 + 800027a0: 00050e63 beqz a0,800027bc + 800027a4: 080c7c13 andi s8,s8,128 + 800027a8: 080c0663 beqz s8,80002834 + 800027ac: 00001637 lui a2,0x1 + 800027b0: 000d8593 mv a1,s11 + 800027b4: 00040513 mv a0,s0 + 800027b8: 849ff0ef jal ra,80002000 + 800027bc: 009d07b3 add a5,s10,s1 + 800027c0: 100c9073 csrw sstatus,s9 + 800027c4: 000a3703 ld a4,0(s4) + 800027c8: 0007b023 sd zero,0(a5) + 800027cc: f6071ce3 bnez a4,80002744 + 800027d0: 00005717 auipc a4,0x5 + 800027d4: 00f73823 sd a5,16(a4) # 800077e0 + 800027d8: 00005717 auipc a4,0x5 + 800027dc: 00f73823 sd a5,16(a4) # 800077e8 + 800027e0: f71ff06f j 80002750 + 800027e4: 10100793 li a5,257 + 800027e8: 04100613 li a2,65 + 800027ec: 00000697 auipc a3,0x0 + 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 + 800027f4: fffff717 auipc a4,0xfffff + 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 + 800027fc: 03079793 slli a5,a5,0x30 + 80002800: 00073503 ld a0,0(a4) + 80002804: 00168693 addi a3,a3,1 + 80002808: 00f665b3 or a1,a2,a5 + 8000280c: 00050a63 beqz a0,80002820 + 80002810: fffff617 auipc a2,0xfffff + 80002814: 82063823 sd zero,-2000(a2) # 80001040 + 80002818: 00073603 ld a2,0(a4) + 8000281c: fe061ae3 bnez a2,80002810 + 80002820: 0006c603 lbu a2,0(a3) + 80002824: ffffe517 auipc a0,0xffffe + 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 + 8000282c: fc061ae3 bnez a2,80002800 + 80002830: e85ff06f j 800026b4 + 80002834: 10100793 li a5,257 + 80002838: 04100613 li a2,65 + 8000283c: 00000697 auipc a3,0x0 + 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 + 80002844: ffffe717 auipc a4,0xffffe + 80002848: 7bc70713 addi a4,a4,1980 # 80001000 + 8000284c: 03079793 slli a5,a5,0x30 + 80002850: 00168693 addi a3,a3,1 + 80002854: 00f665b3 or a1,a2,a5 + 80002858: 00073603 ld a2,0(a4) + 8000285c: 04060863 beqz a2,800028ac + 80002860: ffffe617 auipc a2,0xffffe + 80002864: 7e063023 sd zero,2016(a2) # 80001040 + 80002868: ff1ff06f j 80002858 + 8000286c: 10100793 li a5,257 + 80002870: 04100613 li a2,65 + 80002874: 00000697 auipc a3,0x0 + 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 + 8000287c: ffffe717 auipc a4,0xffffe + 80002880: 78470713 addi a4,a4,1924 # 80001000 + 80002884: 03079793 slli a5,a5,0x30 + 80002888: 00168693 addi a3,a3,1 + 8000288c: 00f665b3 or a1,a2,a5 + 80002890: 00073603 ld a2,0(a4) + 80002894: 02060663 beqz a2,800028c0 + 80002898: ffffe617 auipc a2,0xffffe + 8000289c: 7a063423 sd zero,1960(a2) # 80001040 + 800028a0: ff1ff06f j 80002890 + 800028a4: 00098513 mv a0,s3 + 800028a8: 989ff0ef jal ra,80002230 + 800028ac: 0006c603 lbu a2,0(a3) + 800028b0: ffffe517 auipc a0,0xffffe + 800028b4: 74b53823 sd a1,1872(a0) # 80001000 + 800028b8: f8061ce3 bnez a2,80002850 + 800028bc: df9ff06f j 800026b4 + 800028c0: 0006c603 lbu a2,0(a3) + 800028c4: ffffe517 auipc a0,0xffffe + 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 + 800028cc: fa061ee3 bnez a2,80002888 + 800028d0: de5ff06f j 800026b4 + +00000000800028d4 : + 800028d4: f14027f3 csrr a5,mhartid + 800028d8: 18079a63 bnez a5,80002a6c + 800028dc: 00001697 auipc a3,0x1 + 800028e0: 72468693 addi a3,a3,1828 # 80004000 + 800028e4: 00002717 auipc a4,0x2 + 800028e8: 71c70713 addi a4,a4,1820 # 80005000 + 800028ec: 00c6d693 srli a3,a3,0xc + 800028f0: 00c75713 srli a4,a4,0xc + 800028f4: 00003797 auipc a5,0x3 + 800028f8: 70c78793 addi a5,a5,1804 # 80006000 + 800028fc: 00a69693 slli a3,a3,0xa + 80002900: 00a71713 slli a4,a4,0xa + 80002904: 0016e693 ori a3,a3,1 + 80002908: 00176713 ori a4,a4,1 + 8000290c: 00c7d793 srli a5,a5,0xc + 80002910: 00000897 auipc a7,0x0 + 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 + 80002918: 00a79793 slli a5,a5,0xa + 8000291c: 00001697 auipc a3,0x1 + 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 + 80002924: 20000737 lui a4,0x20000 + 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> + 8000292c: fff00593 li a1,-1 + 80002930: 0017e793 ori a5,a5,1 + 80002934: 00000617 auipc a2,0x0 + 80002938: 6cc60613 addi a2,a2,1740 # 80003000 + 8000293c: ed010113 addi sp,sp,-304 + 80002940: 03f59813 slli a6,a1,0x3f + 80002944: 00003697 auipc a3,0x3 + 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 + 8000294c: 00001717 auipc a4,0x1 + 80002950: 6af73a23 sd a5,1716(a4) # 80004000 + 80002954: 00c65793 srli a5,a2,0xc + 80002958: 12113423 sd ra,296(sp) + 8000295c: 12813023 sd s0,288(sp) + 80002960: 0107e7b3 or a5,a5,a6 + 80002964: 18079073 csrw satp,a5 + 80002968: 01f00793 li a5,31 + 8000296c: 00000297 auipc t0,0x0 + 80002970: 01428293 addi t0,t0,20 # 80002980 + 80002974: 305292f3 csrrw t0,mtvec,t0 + 80002978: 3b059073 csrw pmpaddr0,a1 + 8000297c: 3a079073 csrw pmpcfg0,a5 + 80002980: bff00813 li a6,-1025 + 80002984: 01581813 slli a6,a6,0x15 + 80002988: ffffd797 auipc a5,0xffffd + 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 + 80002990: 010787b3 add a5,a5,a6 + 80002994: 10579073 csrw stvec,a5 + 80002998: 340027f3 csrr a5,mscratch + 8000299c: 010787b3 add a5,a5,a6 + 800029a0: 14079073 csrw sscratch,a5 + 800029a4: 0000b7b7 lui a5,0xb + 800029a8: 1007879b addiw a5,a5,256 + 800029ac: 30279073 csrw medeleg,a5 + 800029b0: 0001e7b7 lui a5,0x1e + 800029b4: 30079073 csrw mstatus,a5 + 800029b8: 30405073 csrwi mie,0 + 800029bc: 00004697 auipc a3,0x4 + 800029c0: 64468693 addi a3,a3,1604 # 80007000 + 800029c4: 010687b3 add a5,a3,a6 + 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> + 800029cc: 00005617 auipc a2,0x5 + 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 + 800029d4: 00005797 auipc a5,0x5 + 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 + 800029dc: 00005317 auipc t1,0x5 + 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 + 800029e4: 03d00793 li a5,61 + 800029e8: 000808b7 lui a7,0x80 + 800029ec: 01080813 addi a6,a6,16 + 800029f0: 03f7871b addiw a4,a5,63 + 800029f4: 02071713 slli a4,a4,0x20 + 800029f8: 0017d61b srliw a2,a5,0x1 + 800029fc: 02075713 srli a4,a4,0x20 + 80002a00: 00c7c7b3 xor a5,a5,a2 + 80002a04: 01170733 add a4,a4,a7 + 80002a08: 010685b3 add a1,a3,a6 + 80002a0c: 00c71713 slli a4,a4,0xc + 80002a10: 0057979b slliw a5,a5,0x5 + 80002a14: 00e6b023 sd a4,0(a3) + 80002a18: 00b6b423 sd a1,8(a3) + 80002a1c: 0207f793 andi a5,a5,32 + 80002a20: 01068693 addi a3,a3,16 + 80002a24: 00c7e7b3 or a5,a5,a2 + 80002a28: fcd314e3 bne t1,a3,800029f0 + 80002a2c: 00050413 mv s0,a0 + 80002a30: 12000613 li a2,288 + 80002a34: 00000593 li a1,0 + 80002a38: 00010513 mv a0,sp + 80002a3c: 00005797 auipc a5,0x5 + 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 + 80002a44: e18ff0ef jal ra,8000205c + 80002a48: 800007b7 lui a5,0x80000 + 80002a4c: 00f40433 add s0,s0,a5 + 80002a50: 00010513 mv a0,sp + 80002a54: 10813423 sd s0,264(sp) + 80002a58: de4fd0ef jal ra,8000003c + 80002a5c: 12813083 ld ra,296(sp) + 80002a60: 12013403 ld s0,288(sp) + 80002a64: 13010113 addi sp,sp,304 + 80002a68: 00008067 ret + 80002a6c: 0ffa37b7 lui a5,0xffa3 + 80002a70: 000805b7 lui a1,0x80 + 80002a74: 57578793 addi a5,a5,1397 # ffa3575 <_start-0x7005ca8b> + 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> + 80002a7c: 00100613 li a2,1 + 80002a80: 00b7f733 and a4,a5,a1 + 80002a84: 01f61613 slli a2,a2,0x1f + 80002a88: 0017f693 andi a3,a5,1 + 80002a8c: 02079793 slli a5,a5,0x20 + 80002a90: 0207d793 srli a5,a5,0x20 + 80002a94: 00c70733 add a4,a4,a2 + 80002a98: 02068263 beqz a3,80002abc + 80002a9c: 0007202f amoadd.w zero,zero,(a4) + 80002aa0: 0017d793 srli a5,a5,0x1 + 80002aa4: 00b7f733 and a4,a5,a1 + 80002aa8: 0017f693 andi a3,a5,1 + 80002aac: 02079793 slli a5,a5,0x20 + 80002ab0: 0207d793 srli a5,a5,0x20 + 80002ab4: 00c70733 add a4,a4,a2 + 80002ab8: fe0692e3 bnez a3,80002a9c + 80002abc: 00072003 lw zero,0(a4) + 80002ac0: 0017d793 srli a5,a5,0x1 + 80002ac4: fe1ff06f j 80002aa4 + +0000000080002ac8 : + 80002ac8: 01400093 li ra,20 + 80002acc: 00600113 li sp,6 + 80002ad0: 0220ef3b remw t5,ra,sp + 80002ad4: 00200e93 li t4,2 + 80002ad8: 00200193 li gp,2 + 80002adc: 0fdf1063 bne t5,t4,80002bbc + +0000000080002ae0 : + 80002ae0: fec00093 li ra,-20 + 80002ae4: 00600113 li sp,6 + 80002ae8: 0220ef3b remw t5,ra,sp + 80002aec: ffe00e93 li t4,-2 + 80002af0: 00300193 li gp,3 + 80002af4: 0ddf1463 bne t5,t4,80002bbc + +0000000080002af8 : + 80002af8: 01400093 li ra,20 + 80002afc: ffa00113 li sp,-6 + 80002b00: 0220ef3b remw t5,ra,sp + 80002b04: 00200e93 li t4,2 + 80002b08: 00400193 li gp,4 + 80002b0c: 0bdf1863 bne t5,t4,80002bbc + +0000000080002b10 : + 80002b10: fec00093 li ra,-20 + 80002b14: ffa00113 li sp,-6 + 80002b18: 0220ef3b remw t5,ra,sp + 80002b1c: ffe00e93 li t4,-2 + 80002b20: 00500193 li gp,5 + 80002b24: 09df1c63 bne t5,t4,80002bbc + +0000000080002b28 : + 80002b28: 800000b7 lui ra,0x80000 + 80002b2c: 00100113 li sp,1 + 80002b30: 0220ef3b remw t5,ra,sp + 80002b34: 00000e93 li t4,0 + 80002b38: 00600193 li gp,6 + 80002b3c: 09df1063 bne t5,t4,80002bbc + +0000000080002b40 : + 80002b40: 800000b7 lui ra,0x80000 + 80002b44: fff00113 li sp,-1 + 80002b48: 0220ef3b remw t5,ra,sp + 80002b4c: 00000e93 li t4,0 + 80002b50: 00700193 li gp,7 + 80002b54: 07df1463 bne t5,t4,80002bbc + +0000000080002b58 : + 80002b58: 800000b7 lui ra,0x80000 + 80002b5c: 00000113 li sp,0 + 80002b60: 0220ef3b remw t5,ra,sp + 80002b64: 80000eb7 lui t4,0x80000 + 80002b68: 00800193 li gp,8 + 80002b6c: 05df1863 bne t5,t4,80002bbc + +0000000080002b70 : + 80002b70: 00100093 li ra,1 + 80002b74: 00000113 li sp,0 + 80002b78: 0220ef3b remw t5,ra,sp + 80002b7c: 00100e93 li t4,1 + 80002b80: 00900193 li gp,9 + 80002b84: 03df1c63 bne t5,t4,80002bbc + +0000000080002b88 : + 80002b88: 00000093 li ra,0 + 80002b8c: 00000113 li sp,0 + 80002b90: 0220ef3b remw t5,ra,sp + 80002b94: 00000e93 li t4,0 + 80002b98: 00a00193 li gp,10 + 80002b9c: 03df1063 bne t5,t4,80002bbc + +0000000080002ba0 : + 80002ba0: 89700093 li ra,-1897 + 80002ba4: 00000113 li sp,0 + 80002ba8: 0220ef3b remw t5,ra,sp + 80002bac: 89700e93 li t4,-1897 + 80002bb0: 00b00193 li gp,11 + 80002bb4: 01df1463 bne t5,t4,80002bbc + 80002bb8: 00301a63 bne zero,gp,80002bcc + +0000000080002bbc : + 80002bbc: 00119513 slli a0,gp,0x1 + 80002bc0: 00050063 beqz a0,80002bc0 + 80002bc4: 00156513 ori a0,a0,1 + 80002bc8: 00000073 ecall + +0000000080002bcc : + 80002bcc: 00100513 li a0,1 + 80002bd0: 00000073 ecall + 80002bd4: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remw.elf b/test/riscv/tests/rv64um-v-remw.elf new file mode 100644 index 00000000..74715363 Binary files /dev/null and b/test/riscv/tests/rv64um-v-remw.elf differ -- cgit v1.2.3 From ae4ae4460fbda8c594e95d4555abd4a30290f6fe Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Tue, 15 May 2018 09:22:35 -0700 Subject: Fix the ebreak instruction to trap, and remove the now obsolete internal exception. This should fix the sbreak test. --- riscv/main.sail | 1 - riscv/riscv.sail | 3 ++- riscv/riscv_types.sail | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/riscv/main.sail b/riscv/main.sail index 28afe5ac..0a46181b 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -43,7 +43,6 @@ function main () = { loop () } catch { Error_not_implemented(s) => print_string("Error: Not implemented: ", s), - Error_EBREAK() => print("EBREAK"), Error_internal_error() => print("Error: internal error") } } diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 374ea4a9..e855a53d 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -573,7 +573,8 @@ union clause ast = EBREAK : unit function clause decode 0b000000000001 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 = Some(EBREAK()) -function clause execute EBREAK() = { throw Error_EBREAK() } +function clause execute EBREAK() = + handle_mem_exception(PC, E_Breakpoint) function clause print_insn (EBREAK()) = "ebreak" diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail index ee0eb94d..5a71c737 100644 --- a/riscv/riscv_types.sail +++ b/riscv/riscv_types.sail @@ -259,7 +259,6 @@ function trapVectorMode_of_bits (m) = { union exception = { Error_not_implemented : string, - Error_EBREAK : unit, Error_internal_error : unit } -- cgit v1.2.3 From 77b393e4f53d14955d301cbd16e22d2e7b026ede Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Tue, 15 May 2018 17:49:44 +0100 Subject: Really don't remove those files --- snapshots/hol4/sail/lib/hol/Holmakefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile index d7df9bcb..e8b34295 100644 --- a/snapshots/hol4/sail/lib/hol/Holmakefile +++ b/snapshots/hol4/sail/lib/hol/Holmakefile @@ -15,7 +15,8 @@ all: $(THYS) ifdef POLY HOLHEAP = sail-heap -EXTRA_CLEANS = $(SCRIPTS) $(HOLHEAP) $(HOLHEAP).o +#EXTRA_CLEANS = $(SCRIPTS) $(HOLHEAP) $(HOLHEAP).o +EXTRA_CLEANS = $(HOLHEAP) $(HOLHEAP).o BASE_HEAP = $(LEMDIR)/lemheap -- cgit v1.2.3