From aa0f2943103e4186e3a56c35bb460ddc12df1034 Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Mon, 21 May 2018 20:43:52 -0700 Subject: Fix a doc typo. --- doc/usage.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage.tex b/doc/usage.tex index c37c835a..b7a47934 100644 --- a/doc/usage.tex +++ b/doc/usage.tex @@ -21,7 +21,7 @@ and \verb+riscv_vmem.sail+ describe the physical and virtual memory interaction, and then \verb+riscv_sys.sail+ and \verb+riscv.sail+ implement most of the specification. -For more complex projects, once can use \ll{$include} statements in +For more complex projects, one can use \ll{$include} statements in Sail source, for example: \begin{lstlisting} $include -- cgit v1.2.3